Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 420
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T111 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1317173773 May 21 02:31:49 PM PDT 24 May 21 02:32:25 PM PDT 24 6950891318 ps
T71 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3611509189 May 21 02:31:51 PM PDT 24 May 21 02:32:21 PM PDT 24 450650882 ps
T72 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2376743120 May 21 02:32:00 PM PDT 24 May 21 02:32:27 PM PDT 24 988293334 ps
T284 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.416374067 May 21 02:31:58 PM PDT 24 May 21 02:32:26 PM PDT 24 772027985 ps
T30 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4151138821 May 21 02:32:34 PM PDT 24 May 21 02:32:51 PM PDT 24 4428972578 ps
T285 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3763295465 May 21 02:32:47 PM PDT 24 May 21 02:33:03 PM PDT 24 339215570 ps
T73 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.158131134 May 21 02:32:10 PM PDT 24 May 21 02:32:35 PM PDT 24 1393486931 ps
T286 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.808697177 May 21 02:32:15 PM PDT 24 May 21 02:32:35 PM PDT 24 516577911 ps
T112 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1427835410 May 21 02:32:05 PM PDT 24 May 21 02:32:30 PM PDT 24 444307897 ps
T287 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3460063492 May 21 02:32:34 PM PDT 24 May 21 02:32:49 PM PDT 24 470800180 ps
T288 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2939719954 May 21 02:31:50 PM PDT 24 May 21 02:32:23 PM PDT 24 333906621 ps
T289 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1626899923 May 21 02:31:53 PM PDT 24 May 21 02:32:23 PM PDT 24 297600544 ps
T113 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1263614309 May 21 02:32:54 PM PDT 24 May 21 02:33:13 PM PDT 24 481473897 ps
T290 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4160827995 May 21 02:31:47 PM PDT 24 May 21 02:32:18 PM PDT 24 492603250 ps
T74 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.945396866 May 21 02:31:51 PM PDT 24 May 21 02:32:28 PM PDT 24 2269462843 ps
T291 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1392646697 May 21 02:32:03 PM PDT 24 May 21 02:32:28 PM PDT 24 273509012 ps
T75 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2492327474 May 21 02:32:39 PM PDT 24 May 21 02:32:58 PM PDT 24 2538017987 ps
T292 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3795382655 May 21 02:31:53 PM PDT 24 May 21 02:32:23 PM PDT 24 409152230 ps
T57 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3195949284 May 21 02:31:52 PM PDT 24 May 21 02:32:40 PM PDT 24 13355051287 ps
T58 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.68696411 May 21 02:32:34 PM PDT 24 May 21 02:32:48 PM PDT 24 400781541 ps
T76 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1306519830 May 21 02:32:16 PM PDT 24 May 21 02:32:40 PM PDT 24 2741472506 ps
T31 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3694038106 May 21 02:32:05 PM PDT 24 May 21 02:32:31 PM PDT 24 4243310852 ps
T293 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1633586594 May 21 02:32:53 PM PDT 24 May 21 02:33:12 PM PDT 24 318724586 ps
T294 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2514611781 May 21 02:32:33 PM PDT 24 May 21 02:32:49 PM PDT 24 915195639 ps
T295 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1774899265 May 21 02:32:16 PM PDT 24 May 21 02:32:37 PM PDT 24 461135457 ps
T296 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1209473566 May 21 02:32:38 PM PDT 24 May 21 02:32:56 PM PDT 24 1412149930 ps
T297 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1204792011 May 21 02:32:08 PM PDT 24 May 21 02:32:33 PM PDT 24 715755927 ps
T59 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.299834330 May 21 02:31:56 PM PDT 24 May 21 02:32:25 PM PDT 24 509694193 ps
T298 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3821268195 May 21 02:32:04 PM PDT 24 May 21 02:32:29 PM PDT 24 486692737 ps
T299 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3272249695 May 21 02:31:47 PM PDT 24 May 21 02:32:18 PM PDT 24 493762059 ps
T300 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1267785307 May 21 02:32:15 PM PDT 24 May 21 02:32:35 PM PDT 24 436331025 ps
T301 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3424588211 May 21 02:32:26 PM PDT 24 May 21 02:32:42 PM PDT 24 365766808 ps
T32 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3060761041 May 21 02:32:20 PM PDT 24 May 21 02:32:40 PM PDT 24 8961168743 ps
T106 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1686397749 May 21 02:32:21 PM PDT 24 May 21 02:32:41 PM PDT 24 4695901061 ps
T302 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3193914831 May 21 02:32:10 PM PDT 24 May 21 02:32:34 PM PDT 24 335362100 ps
T303 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3055510112 May 21 02:32:11 PM PDT 24 May 21 02:32:33 PM PDT 24 439651614 ps
T304 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.925106343 May 21 02:32:06 PM PDT 24 May 21 02:32:31 PM PDT 24 305089930 ps
T305 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.182117741 May 21 02:32:17 PM PDT 24 May 21 02:32:36 PM PDT 24 485917198 ps
T306 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2783468147 May 21 02:32:52 PM PDT 24 May 21 02:33:12 PM PDT 24 454577282 ps
T107 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.110285499 May 21 02:31:58 PM PDT 24 May 21 02:32:33 PM PDT 24 4339207409 ps
T307 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3989921295 May 21 02:32:22 PM PDT 24 May 21 02:32:39 PM PDT 24 408352908 ps
T308 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2626815231 May 21 02:31:51 PM PDT 24 May 21 02:32:22 PM PDT 24 512733532 ps
T309 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.664904987 May 21 02:32:46 PM PDT 24 May 21 02:33:02 PM PDT 24 278863941 ps
T310 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1016572911 May 21 02:32:32 PM PDT 24 May 21 02:32:54 PM PDT 24 4315232754 ps
T311 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2653814645 May 21 02:32:54 PM PDT 24 May 21 02:33:13 PM PDT 24 353421932 ps
T312 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2316950785 May 21 02:32:03 PM PDT 24 May 21 02:32:30 PM PDT 24 367755291 ps
T313 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.308830921 May 21 02:32:32 PM PDT 24 May 21 02:32:48 PM PDT 24 583784202 ps
T314 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3112653800 May 21 02:32:27 PM PDT 24 May 21 02:32:50 PM PDT 24 4545110185 ps
T315 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1678825450 May 21 02:32:09 PM PDT 24 May 21 02:32:32 PM PDT 24 891414846 ps
T316 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.72052693 May 21 02:31:53 PM PDT 24 May 21 02:32:23 PM PDT 24 313088711 ps
T317 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4253210609 May 21 02:31:50 PM PDT 24 May 21 02:32:22 PM PDT 24 539996743 ps
T318 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4106627722 May 21 02:32:10 PM PDT 24 May 21 02:32:32 PM PDT 24 421276575 ps
T319 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2012174235 May 21 02:32:45 PM PDT 24 May 21 02:33:00 PM PDT 24 450240053 ps
T320 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2397373729 May 21 02:32:17 PM PDT 24 May 21 02:32:45 PM PDT 24 8144937664 ps
T321 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3180554555 May 21 02:32:16 PM PDT 24 May 21 02:32:35 PM PDT 24 379171035 ps
T322 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4068986540 May 21 02:31:52 PM PDT 24 May 21 02:32:23 PM PDT 24 379088081 ps
T108 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2607783381 May 21 02:32:40 PM PDT 24 May 21 02:33:00 PM PDT 24 7725246964 ps
T323 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3394424690 May 21 02:32:45 PM PDT 24 May 21 02:32:59 PM PDT 24 300075056 ps
T324 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3426990805 May 21 02:32:34 PM PDT 24 May 21 02:32:49 PM PDT 24 522826250 ps
T109 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.915644371 May 21 02:31:53 PM PDT 24 May 21 02:32:26 PM PDT 24 7977836715 ps
T325 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4180815040 May 21 02:32:06 PM PDT 24 May 21 02:32:30 PM PDT 24 429988144 ps
T104 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3704831246 May 21 02:32:09 PM PDT 24 May 21 02:32:38 PM PDT 24 4328735573 ps
T326 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.143065327 May 21 02:31:52 PM PDT 24 May 21 02:32:22 PM PDT 24 379805199 ps
T327 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1283673785 May 21 02:32:53 PM PDT 24 May 21 02:33:13 PM PDT 24 427290078 ps
T328 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1423008062 May 21 02:32:52 PM PDT 24 May 21 02:33:11 PM PDT 24 498478362 ps
T329 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1064828536 May 21 02:32:03 PM PDT 24 May 21 02:32:29 PM PDT 24 345889298 ps
T330 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3368151418 May 21 02:32:32 PM PDT 24 May 21 02:32:47 PM PDT 24 513693298 ps
T331 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1429960872 May 21 02:31:53 PM PDT 24 May 21 02:32:24 PM PDT 24 7443156600 ps
T332 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.942334583 May 21 02:32:08 PM PDT 24 May 21 02:32:33 PM PDT 24 852994162 ps
T60 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.241740833 May 21 02:31:45 PM PDT 24 May 21 02:32:18 PM PDT 24 888653318 ps
T61 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3029049557 May 21 02:32:05 PM PDT 24 May 21 02:32:38 PM PDT 24 4603670951 ps
T333 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2981201136 May 21 02:31:58 PM PDT 24 May 21 02:32:26 PM PDT 24 534450628 ps
T334 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2036056507 May 21 02:32:26 PM PDT 24 May 21 02:32:42 PM PDT 24 648445799 ps
T62 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.793118330 May 21 02:32:43 PM PDT 24 May 21 02:32:57 PM PDT 24 521686191 ps
T335 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3804156524 May 21 02:32:04 PM PDT 24 May 21 02:32:28 PM PDT 24 430603883 ps
T336 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4233243745 May 21 02:31:58 PM PDT 24 May 21 02:32:26 PM PDT 24 367659276 ps
T337 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1733895935 May 21 02:32:46 PM PDT 24 May 21 02:33:01 PM PDT 24 329112554 ps
T338 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1510444968 May 21 02:32:46 PM PDT 24 May 21 02:33:01 PM PDT 24 340459288 ps
T339 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2480861122 May 21 02:32:29 PM PDT 24 May 21 02:32:44 PM PDT 24 292162388 ps
T340 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2891854382 May 21 02:32:20 PM PDT 24 May 21 02:32:42 PM PDT 24 8928078422 ps
T341 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1592057937 May 21 02:32:31 PM PDT 24 May 21 02:32:47 PM PDT 24 522623201 ps
T342 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3633171743 May 21 02:32:33 PM PDT 24 May 21 02:32:49 PM PDT 24 1083921802 ps
T343 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3844802722 May 21 02:32:55 PM PDT 24 May 21 02:33:15 PM PDT 24 432437196 ps
T344 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.906986115 May 21 02:31:53 PM PDT 24 May 21 02:32:23 PM PDT 24 447609833 ps
T345 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.243510918 May 21 02:32:21 PM PDT 24 May 21 02:32:38 PM PDT 24 1634064144 ps
T346 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3881729016 May 21 02:32:45 PM PDT 24 May 21 02:33:00 PM PDT 24 455538822 ps
T347 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2724381030 May 21 02:32:22 PM PDT 24 May 21 02:32:40 PM PDT 24 419156077 ps
T348 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3834152532 May 21 02:31:47 PM PDT 24 May 21 02:32:18 PM PDT 24 495065252 ps
T349 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1607291851 May 21 02:32:09 PM PDT 24 May 21 02:32:33 PM PDT 24 494705285 ps
T350 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.666319498 May 21 02:32:02 PM PDT 24 May 21 02:32:28 PM PDT 24 288547662 ps
T110 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1116277791 May 21 02:32:09 PM PDT 24 May 21 02:32:39 PM PDT 24 8074057987 ps
T351 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2051672882 May 21 02:32:32 PM PDT 24 May 21 02:32:48 PM PDT 24 385084960 ps
T352 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.38764673 May 21 02:32:52 PM PDT 24 May 21 02:33:12 PM PDT 24 416664772 ps
T63 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.435355115 May 21 02:32:03 PM PDT 24 May 21 02:32:32 PM PDT 24 9793673411 ps
T353 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.815661331 May 21 02:32:21 PM PDT 24 May 21 02:32:39 PM PDT 24 1068888901 ps
T354 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3880764304 May 21 02:32:09 PM PDT 24 May 21 02:32:43 PM PDT 24 8223925856 ps
T355 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1672628095 May 21 02:32:11 PM PDT 24 May 21 02:32:37 PM PDT 24 2338347409 ps
T356 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3087750074 May 21 02:32:21 PM PDT 24 May 21 02:32:38 PM PDT 24 450581921 ps
T357 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1767951121 May 21 02:32:26 PM PDT 24 May 21 02:32:42 PM PDT 24 385464714 ps
T358 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3806210717 May 21 02:32:47 PM PDT 24 May 21 02:33:02 PM PDT 24 297057155 ps
T359 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3483819618 May 21 02:32:50 PM PDT 24 May 21 02:33:08 PM PDT 24 340921178 ps
T360 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2020600612 May 21 02:32:42 PM PDT 24 May 21 02:32:56 PM PDT 24 437346265 ps
T361 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1789202306 May 21 02:32:09 PM PDT 24 May 21 02:32:33 PM PDT 24 539232526 ps
T362 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.416572768 May 21 02:31:52 PM PDT 24 May 21 02:32:30 PM PDT 24 2732827263 ps
T363 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.564181317 May 21 02:32:05 PM PDT 24 May 21 02:32:30 PM PDT 24 4373147882 ps
T364 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3674736208 May 21 02:32:50 PM PDT 24 May 21 02:33:09 PM PDT 24 326026282 ps
T365 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1315828711 May 21 02:32:12 PM PDT 24 May 21 02:32:33 PM PDT 24 462820147 ps
T366 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1489995880 May 21 02:32:07 PM PDT 24 May 21 02:32:31 PM PDT 24 418300584 ps
T367 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1055921732 May 21 02:32:40 PM PDT 24 May 21 02:32:54 PM PDT 24 493026575 ps
T368 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2618169273 May 21 02:32:10 PM PDT 24 May 21 02:32:32 PM PDT 24 547792970 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.189374045 May 21 02:31:52 PM PDT 24 May 21 02:32:23 PM PDT 24 504266544 ps
T369 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2067396007 May 21 02:32:49 PM PDT 24 May 21 02:33:06 PM PDT 24 511901511 ps
T65 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1203605201 May 21 02:32:05 PM PDT 24 May 21 02:32:30 PM PDT 24 558526199 ps
T66 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3013443810 May 21 02:32:09 PM PDT 24 May 21 02:32:33 PM PDT 24 288656524 ps
T370 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1075943133 May 21 02:32:06 PM PDT 24 May 21 02:32:31 PM PDT 24 1190577280 ps
T371 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4256709701 May 21 02:32:39 PM PDT 24 May 21 02:32:53 PM PDT 24 442477577 ps
T372 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2070052257 May 21 02:32:52 PM PDT 24 May 21 02:33:11 PM PDT 24 412301323 ps
T373 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.198297580 May 21 02:32:06 PM PDT 24 May 21 02:32:30 PM PDT 24 331567731 ps
T374 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2913177736 May 21 02:32:06 PM PDT 24 May 21 02:32:43 PM PDT 24 8293971917 ps
T375 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1281659391 May 21 02:32:22 PM PDT 24 May 21 02:32:39 PM PDT 24 374353362 ps
T376 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1898315647 May 21 02:31:47 PM PDT 24 May 21 02:32:21 PM PDT 24 4149180224 ps
T377 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1855954523 May 21 02:32:47 PM PDT 24 May 21 02:33:04 PM PDT 24 389366914 ps
T378 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1759150326 May 21 02:32:24 PM PDT 24 May 21 02:32:41 PM PDT 24 493236859 ps
T379 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3713141156 May 21 02:32:00 PM PDT 24 May 21 02:32:27 PM PDT 24 458520301 ps
T67 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.183826633 May 21 02:32:20 PM PDT 24 May 21 02:32:38 PM PDT 24 367370421 ps
T380 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2223282984 May 21 02:32:35 PM PDT 24 May 21 02:32:51 PM PDT 24 564767109 ps
T381 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1520614827 May 21 02:32:27 PM PDT 24 May 21 02:32:46 PM PDT 24 2525415654 ps
T382 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3572242546 May 21 02:32:49 PM PDT 24 May 21 02:33:07 PM PDT 24 390825856 ps
T383 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.4062294460 May 21 02:32:56 PM PDT 24 May 21 02:33:16 PM PDT 24 305798555 ps
T384 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2572998133 May 21 02:32:46 PM PDT 24 May 21 02:33:01 PM PDT 24 468224053 ps
T385 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.342293086 May 21 02:32:09 PM PDT 24 May 21 02:32:33 PM PDT 24 2681213523 ps
T386 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2347579360 May 21 02:32:20 PM PDT 24 May 21 02:32:38 PM PDT 24 688612095 ps
T387 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.427169206 May 21 02:31:56 PM PDT 24 May 21 02:32:25 PM PDT 24 471376694 ps
T388 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3517636552 May 21 02:32:09 PM PDT 24 May 21 02:32:32 PM PDT 24 528014931 ps
T389 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1987473963 May 21 02:31:57 PM PDT 24 May 21 02:32:25 PM PDT 24 375557970 ps
T390 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1097638666 May 21 02:32:23 PM PDT 24 May 21 02:32:41 PM PDT 24 543264382 ps
T391 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1833677624 May 21 02:32:09 PM PDT 24 May 21 02:32:32 PM PDT 24 400127182 ps
T392 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.953355094 May 21 02:32:42 PM PDT 24 May 21 02:32:56 PM PDT 24 573554154 ps
T393 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.649382741 May 21 02:32:07 PM PDT 24 May 21 02:32:31 PM PDT 24 392229831 ps
T394 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2957238763 May 21 02:32:53 PM PDT 24 May 21 02:33:12 PM PDT 24 308970755 ps
T395 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4143002877 May 21 02:32:49 PM PDT 24 May 21 02:33:07 PM PDT 24 432127621 ps
T396 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.548460799 May 21 02:32:43 PM PDT 24 May 21 02:33:00 PM PDT 24 8777141252 ps
T64 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2558680338 May 21 02:32:45 PM PDT 24 May 21 02:33:00 PM PDT 24 471998814 ps
T70 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.338375912 May 21 02:32:02 PM PDT 24 May 21 02:32:28 PM PDT 24 348512696 ps
T397 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.449776991 May 21 02:32:02 PM PDT 24 May 21 02:32:30 PM PDT 24 517057000 ps
T398 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1841696086 May 21 02:32:07 PM PDT 24 May 21 02:32:32 PM PDT 24 1291948445 ps
T399 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2379777923 May 21 02:32:49 PM PDT 24 May 21 02:33:06 PM PDT 24 424407730 ps
T400 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1990405420 May 21 02:32:09 PM PDT 24 May 21 02:32:40 PM PDT 24 8320367199 ps
T68 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3915600874 May 21 02:32:02 PM PDT 24 May 21 02:32:29 PM PDT 24 1033165262 ps
T401 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4219537590 May 21 02:32:46 PM PDT 24 May 21 02:33:01 PM PDT 24 335969589 ps
T402 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2328121670 May 21 02:31:51 PM PDT 24 May 21 02:32:21 PM PDT 24 507038250 ps
T403 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3328686627 May 21 02:32:21 PM PDT 24 May 21 02:32:39 PM PDT 24 332894174 ps
T404 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.175335753 May 21 02:32:33 PM PDT 24 May 21 02:32:49 PM PDT 24 499245499 ps
T405 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2412347920 May 21 02:31:55 PM PDT 24 May 21 02:32:24 PM PDT 24 627314379 ps
T406 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3562946240 May 21 02:32:37 PM PDT 24 May 21 02:32:52 PM PDT 24 1364358456 ps
T407 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1389559906 May 21 02:32:15 PM PDT 24 May 21 02:32:38 PM PDT 24 2586837897 ps
T408 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.254560373 May 21 02:32:47 PM PDT 24 May 21 02:33:03 PM PDT 24 394442065 ps
T409 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3251989747 May 21 02:31:58 PM PDT 24 May 21 02:32:28 PM PDT 24 380189397 ps
T410 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3647083281 May 21 02:32:29 PM PDT 24 May 21 02:32:46 PM PDT 24 491064783 ps
T411 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.211594654 May 21 02:32:40 PM PDT 24 May 21 02:32:55 PM PDT 24 431460840 ps
T412 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1826249960 May 21 02:32:05 PM PDT 24 May 21 02:32:30 PM PDT 24 478613688 ps
T105 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1998483770 May 21 02:31:52 PM PDT 24 May 21 02:32:34 PM PDT 24 7526263468 ps
T413 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.4208770377 May 21 02:32:06 PM PDT 24 May 21 02:32:33 PM PDT 24 2413650246 ps
T414 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1324758173 May 21 02:32:50 PM PDT 24 May 21 02:33:08 PM PDT 24 471161300 ps
T415 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2744651782 May 21 02:32:47 PM PDT 24 May 21 02:33:03 PM PDT 24 324602463 ps
T416 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3689771501 May 21 02:32:09 PM PDT 24 May 21 02:32:33 PM PDT 24 597871292 ps
T417 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2580768451 May 21 02:32:06 PM PDT 24 May 21 02:32:31 PM PDT 24 538374019 ps
T418 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3167036369 May 21 02:31:51 PM PDT 24 May 21 02:32:22 PM PDT 24 503150446 ps
T419 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.825643889 May 21 02:31:45 PM PDT 24 May 21 02:32:19 PM PDT 24 525493563 ps
T420 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3798343570 May 21 02:32:11 PM PDT 24 May 21 02:32:34 PM PDT 24 472050571 ps

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2211651500
Short name T6
Test name
Test status
Simulation time 108005824388 ps
CPU time 245.6 seconds
Started May 21 02:10:34 PM PDT 24
Finished May 21 02:14:42 PM PDT 24
Peak memory 198464 kb
Host smart-70fe89d2-e380-439f-be25-7a2b84b1c4e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211651500 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2211651500
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4151138821
Short name T30
Test name
Test status
Simulation time 4428972578 ps
CPU time 3.26 seconds
Started May 21 02:32:34 PM PDT 24
Finished May 21 02:32:51 PM PDT 24
Peak memory 197444 kb
Host smart-15b3c481-93f7-40f0-a9b6-3612bceef264
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151138821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.4151138821
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3720882578
Short name T40
Test name
Test status
Simulation time 499192073943 ps
CPU time 846.57 seconds
Started May 21 02:10:48 PM PDT 24
Finished May 21 02:24:57 PM PDT 24
Peak memory 201972 kb
Host smart-10d12210-b3cf-43cc-871e-dc188f2565b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720882578 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3720882578
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2590375494
Short name T11
Test name
Test status
Simulation time 270750800996 ps
CPU time 30.31 seconds
Started May 21 02:10:23 PM PDT 24
Finished May 21 02:10:57 PM PDT 24
Peak memory 192996 kb
Host smart-90f60842-eab6-4feb-bcfe-ed31291b6dbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590375494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2590375494
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3850506872
Short name T16
Test name
Test status
Simulation time 3835818274 ps
CPU time 3.73 seconds
Started May 21 02:10:21 PM PDT 24
Finished May 21 02:10:28 PM PDT 24
Peak memory 215416 kb
Host smart-919cfb0c-329f-420b-8662-ee69646d6e87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850506872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3850506872
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1712205089
Short name T36
Test name
Test status
Simulation time 196483153230 ps
CPU time 1066.04 seconds
Started May 21 02:10:40 PM PDT 24
Finished May 21 02:28:29 PM PDT 24
Peak memory 205484 kb
Host smart-ec3d3d23-2733-4ef6-8ca6-4b22774da10d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712205089 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1712205089
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1685257699
Short name T29
Test name
Test status
Simulation time 520187518 ps
CPU time 1.13 seconds
Started May 21 02:31:51 PM PDT 24
Finished May 21 02:32:22 PM PDT 24
Peak memory 183784 kb
Host smart-0cf41abf-1bf8-4440-9a7c-ce6bea60897d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685257699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1685257699
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.727794786
Short name T45
Test name
Test status
Simulation time 418464176280 ps
CPU time 666.59 seconds
Started May 21 02:11:11 PM PDT 24
Finished May 21 02:22:21 PM PDT 24
Peak memory 195316 kb
Host smart-ace2081f-2152-4175-9c6a-17f5885864e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727794786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.727794786
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3611509189
Short name T71
Test name
Test status
Simulation time 450650882 ps
CPU time 0.74 seconds
Started May 21 02:31:51 PM PDT 24
Finished May 21 02:32:21 PM PDT 24
Peak memory 193104 kb
Host smart-019a1c49-7e27-40d0-8832-152a896bfe73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611509189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3611509189
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1998483770
Short name T105
Test name
Test status
Simulation time 7526263468 ps
CPU time 12.37 seconds
Started May 21 02:31:52 PM PDT 24
Finished May 21 02:32:34 PM PDT 24
Peak memory 198028 kb
Host smart-cc7596a6-82b7-4488-be0f-9d81114c604d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998483770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1998483770
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2607783381
Short name T108
Test name
Test status
Simulation time 7725246964 ps
CPU time 6.92 seconds
Started May 21 02:32:40 PM PDT 24
Finished May 21 02:33:00 PM PDT 24
Peak memory 197928 kb
Host smart-bb5880f9-98e3-47bd-a9a3-55bbd9bb2227
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607783381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2607783381
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1102826032
Short name T122
Test name
Test status
Simulation time 501381002 ps
CPU time 1.38 seconds
Started May 21 02:10:39 PM PDT 24
Finished May 21 02:10:42 PM PDT 24
Peak memory 183504 kb
Host smart-1b9730f9-53b1-4404-bfc2-d10f9f0abf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102826032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1102826032
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1429960872
Short name T331
Test name
Test status
Simulation time 7443156600 ps
CPU time 2.36 seconds
Started May 21 02:31:53 PM PDT 24
Finished May 21 02:32:24 PM PDT 24
Peak memory 192284 kb
Host smart-f33f090c-e609-420e-a7d1-9f07b99e6952
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429960872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1429960872
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.241740833
Short name T60
Test name
Test status
Simulation time 888653318 ps
CPU time 1.21 seconds
Started May 21 02:31:45 PM PDT 24
Finished May 21 02:32:18 PM PDT 24
Peak memory 183856 kb
Host smart-8b489dfa-fb92-4ece-81da-19b4fea8f594
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241740833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.241740833
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4068986540
Short name T322
Test name
Test status
Simulation time 379088081 ps
CPU time 1.12 seconds
Started May 21 02:31:52 PM PDT 24
Finished May 21 02:32:23 PM PDT 24
Peak memory 195236 kb
Host smart-7fa40a7e-7073-4e14-b5e3-801222c3da4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068986540 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.4068986540
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3834152532
Short name T348
Test name
Test status
Simulation time 495065252 ps
CPU time 0.73 seconds
Started May 21 02:31:47 PM PDT 24
Finished May 21 02:32:18 PM PDT 24
Peak memory 183720 kb
Host smart-103f954c-f305-4fd9-8a0f-edc525bac79a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834152532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3834152532
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3272249695
Short name T299
Test name
Test status
Simulation time 493762059 ps
CPU time 0.85 seconds
Started May 21 02:31:47 PM PDT 24
Finished May 21 02:32:18 PM PDT 24
Peak memory 183628 kb
Host smart-10e60819-0c8f-4240-a310-2bfb42b9cb72
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272249695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3272249695
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4160827995
Short name T290
Test name
Test status
Simulation time 492603250 ps
CPU time 0.57 seconds
Started May 21 02:31:47 PM PDT 24
Finished May 21 02:32:18 PM PDT 24
Peak memory 183868 kb
Host smart-b534d403-202c-4931-af29-15b940977a36
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160827995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.4160827995
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.945396866
Short name T74
Test name
Test status
Simulation time 2269462843 ps
CPU time 7.49 seconds
Started May 21 02:31:51 PM PDT 24
Finished May 21 02:32:28 PM PDT 24
Peak memory 192132 kb
Host smart-9c6dd1fc-612f-4de1-8236-0e8692cef667
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945396866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.945396866
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.825643889
Short name T419
Test name
Test status
Simulation time 525493563 ps
CPU time 2.76 seconds
Started May 21 02:31:45 PM PDT 24
Finished May 21 02:32:19 PM PDT 24
Peak memory 198644 kb
Host smart-0c514ed8-589d-47be-8af3-ce1a96ccdef8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825643889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.825643889
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1898315647
Short name T376
Test name
Test status
Simulation time 4149180224 ps
CPU time 3.59 seconds
Started May 21 02:31:47 PM PDT 24
Finished May 21 02:32:21 PM PDT 24
Peak memory 197428 kb
Host smart-255c0f13-9bae-42f9-a55f-43c9715c983f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898315647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1898315647
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.189374045
Short name T69
Test name
Test status
Simulation time 504266544 ps
CPU time 0.95 seconds
Started May 21 02:31:52 PM PDT 24
Finished May 21 02:32:23 PM PDT 24
Peak memory 183772 kb
Host smart-7c3306f6-72b1-44fc-8617-aa3a04af673d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189374045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.189374045
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3195949284
Short name T57
Test name
Test status
Simulation time 13355051287 ps
CPU time 18.95 seconds
Started May 21 02:31:52 PM PDT 24
Finished May 21 02:32:40 PM PDT 24
Peak memory 184056 kb
Host smart-f42b2f3c-628d-410c-80b7-5cf06b1ef22c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195949284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3195949284
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2412347920
Short name T405
Test name
Test status
Simulation time 627314379 ps
CPU time 0.68 seconds
Started May 21 02:31:55 PM PDT 24
Finished May 21 02:32:24 PM PDT 24
Peak memory 183780 kb
Host smart-09223aec-5c3e-4eb8-aab6-454217a48ca6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412347920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2412347920
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2981201136
Short name T333
Test name
Test status
Simulation time 534450628 ps
CPU time 1.08 seconds
Started May 21 02:31:58 PM PDT 24
Finished May 21 02:32:26 PM PDT 24
Peak memory 195748 kb
Host smart-f74fd7c0-af57-4205-a3bf-d897fc761955
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981201136 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2981201136
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3167036369
Short name T418
Test name
Test status
Simulation time 503150446 ps
CPU time 1.35 seconds
Started May 21 02:31:51 PM PDT 24
Finished May 21 02:32:22 PM PDT 24
Peak memory 193072 kb
Host smart-f447e0f0-cb60-4ca8-af56-3d356929066b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167036369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3167036369
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.72052693
Short name T316
Test name
Test status
Simulation time 313088711 ps
CPU time 0.76 seconds
Started May 21 02:31:53 PM PDT 24
Finished May 21 02:32:23 PM PDT 24
Peak memory 183708 kb
Host smart-d6698f79-8876-4704-85ad-50e073a7852e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72052693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.72052693
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.143065327
Short name T326
Test name
Test status
Simulation time 379805199 ps
CPU time 0.7 seconds
Started May 21 02:31:52 PM PDT 24
Finished May 21 02:32:22 PM PDT 24
Peak memory 183624 kb
Host smart-744505c0-891e-46b2-a5c5-997e1d527702
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143065327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.143065327
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1626899923
Short name T289
Test name
Test status
Simulation time 297600544 ps
CPU time 0.72 seconds
Started May 21 02:31:53 PM PDT 24
Finished May 21 02:32:23 PM PDT 24
Peak memory 183704 kb
Host smart-1eb2dc8a-a0a0-42ab-b1ee-f663a4e99678
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626899923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1626899923
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.416572768
Short name T362
Test name
Test status
Simulation time 2732827263 ps
CPU time 8.09 seconds
Started May 21 02:31:52 PM PDT 24
Finished May 21 02:32:30 PM PDT 24
Peak memory 194532 kb
Host smart-bd76f3cb-5180-44a2-b8d3-9c54518a9703
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416572768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.416572768
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4253210609
Short name T317
Test name
Test status
Simulation time 539996743 ps
CPU time 1.79 seconds
Started May 21 02:31:50 PM PDT 24
Finished May 21 02:32:22 PM PDT 24
Peak memory 198672 kb
Host smart-228efff6-cfcf-497b-81a1-aa103d72b15b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253210609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.4253210609
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.808697177
Short name T286
Test name
Test status
Simulation time 516577911 ps
CPU time 1.05 seconds
Started May 21 02:32:15 PM PDT 24
Finished May 21 02:32:35 PM PDT 24
Peak memory 198168 kb
Host smart-3a311ba5-acf3-4df8-954e-700bf5f43867
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808697177 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.808697177
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1267785307
Short name T300
Test name
Test status
Simulation time 436331025 ps
CPU time 0.88 seconds
Started May 21 02:32:15 PM PDT 24
Finished May 21 02:32:35 PM PDT 24
Peak memory 193024 kb
Host smart-eb39386d-e9a2-42e5-b82b-d5e3b374f061
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267785307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1267785307
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3055510112
Short name T303
Test name
Test status
Simulation time 439651614 ps
CPU time 0.89 seconds
Started May 21 02:32:11 PM PDT 24
Finished May 21 02:32:33 PM PDT 24
Peak memory 183704 kb
Host smart-aa6a5b3a-3040-4a6c-9862-ebdb37c71f9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055510112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3055510112
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1389559906
Short name T407
Test name
Test status
Simulation time 2586837897 ps
CPU time 4.15 seconds
Started May 21 02:32:15 PM PDT 24
Finished May 21 02:32:38 PM PDT 24
Peak memory 194484 kb
Host smart-7ed691f9-7bd0-43da-b993-bac6f8e9db28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389559906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1389559906
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3798343570
Short name T420
Test name
Test status
Simulation time 472050571 ps
CPU time 1.8 seconds
Started May 21 02:32:11 PM PDT 24
Finished May 21 02:32:34 PM PDT 24
Peak memory 198596 kb
Host smart-23d50124-4bed-4769-9c19-ade2f154caa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798343570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3798343570
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3704831246
Short name T104
Test name
Test status
Simulation time 4328735573 ps
CPU time 6.91 seconds
Started May 21 02:32:09 PM PDT 24
Finished May 21 02:32:38 PM PDT 24
Peak memory 197444 kb
Host smart-1bbf6f92-7f0c-4856-af01-e1b8b546a943
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704831246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3704831246
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1767951121
Short name T357
Test name
Test status
Simulation time 385464714 ps
CPU time 0.76 seconds
Started May 21 02:32:26 PM PDT 24
Finished May 21 02:32:42 PM PDT 24
Peak memory 195272 kb
Host smart-5289e6d8-0cd2-4d40-a7ae-7c73c864e47b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767951121 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1767951121
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.182117741
Short name T305
Test name
Test status
Simulation time 485917198 ps
CPU time 0.66 seconds
Started May 21 02:32:17 PM PDT 24
Finished May 21 02:32:36 PM PDT 24
Peak memory 193152 kb
Host smart-040a3d4f-e40c-4c53-9916-d796e58db593
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182117741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.182117741
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3180554555
Short name T321
Test name
Test status
Simulation time 379171035 ps
CPU time 0.71 seconds
Started May 21 02:32:16 PM PDT 24
Finished May 21 02:32:35 PM PDT 24
Peak memory 183692 kb
Host smart-e9e24c5d-424b-468b-81c9-2042c8cd26f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180554555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3180554555
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1306519830
Short name T76
Test name
Test status
Simulation time 2741472506 ps
CPU time 5.03 seconds
Started May 21 02:32:16 PM PDT 24
Finished May 21 02:32:40 PM PDT 24
Peak memory 183932 kb
Host smart-9e1dc986-f08c-4fe8-9596-adb3a798bb82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306519830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1306519830
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1774899265
Short name T295
Test name
Test status
Simulation time 461135457 ps
CPU time 2.18 seconds
Started May 21 02:32:16 PM PDT 24
Finished May 21 02:32:37 PM PDT 24
Peak memory 198560 kb
Host smart-470b3b1b-bef6-48cd-b98f-2372253842d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774899265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1774899265
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2397373729
Short name T320
Test name
Test status
Simulation time 8144937664 ps
CPU time 9.97 seconds
Started May 21 02:32:17 PM PDT 24
Finished May 21 02:32:45 PM PDT 24
Peak memory 198204 kb
Host smart-7d6bb78a-26ef-4057-8dbb-12748fa9eb9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397373729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2397373729
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2347579360
Short name T386
Test name
Test status
Simulation time 688612095 ps
CPU time 1.34 seconds
Started May 21 02:32:20 PM PDT 24
Finished May 21 02:32:38 PM PDT 24
Peak memory 198668 kb
Host smart-9fbc8702-7970-496b-94e2-44196efcc1f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347579360 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2347579360
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.183826633
Short name T67
Test name
Test status
Simulation time 367370421 ps
CPU time 0.93 seconds
Started May 21 02:32:20 PM PDT 24
Finished May 21 02:32:38 PM PDT 24
Peak memory 193064 kb
Host smart-46b235fd-e11d-4478-b31c-7ff46da2eb9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183826633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.183826633
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3424588211
Short name T301
Test name
Test status
Simulation time 365766808 ps
CPU time 0.83 seconds
Started May 21 02:32:26 PM PDT 24
Finished May 21 02:32:42 PM PDT 24
Peak memory 183700 kb
Host smart-39399db8-fe9f-4a67-8c0c-a48254c7b2fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424588211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3424588211
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.815661331
Short name T353
Test name
Test status
Simulation time 1068888901 ps
CPU time 1.51 seconds
Started May 21 02:32:21 PM PDT 24
Finished May 21 02:32:39 PM PDT 24
Peak memory 183836 kb
Host smart-394f1772-81bd-4b58-825c-a48cee1b1afc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815661331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.815661331
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1097638666
Short name T390
Test name
Test status
Simulation time 543264382 ps
CPU time 2 seconds
Started May 21 02:32:23 PM PDT 24
Finished May 21 02:32:41 PM PDT 24
Peak memory 198664 kb
Host smart-871750fa-dd7e-47b5-aeef-94b7e7b133ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097638666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1097638666
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2891854382
Short name T340
Test name
Test status
Simulation time 8928078422 ps
CPU time 4.99 seconds
Started May 21 02:32:20 PM PDT 24
Finished May 21 02:32:42 PM PDT 24
Peak memory 197976 kb
Host smart-def74607-9181-4b4c-b882-dfbdc2ce29d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891854382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2891854382
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2036056507
Short name T334
Test name
Test status
Simulation time 648445799 ps
CPU time 1.13 seconds
Started May 21 02:32:26 PM PDT 24
Finished May 21 02:32:42 PM PDT 24
Peak memory 198476 kb
Host smart-fc1754d5-aacb-42f4-a5d4-619fe5dd0790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036056507 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2036056507
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2724381030
Short name T347
Test name
Test status
Simulation time 419156077 ps
CPU time 0.89 seconds
Started May 21 02:32:22 PM PDT 24
Finished May 21 02:32:40 PM PDT 24
Peak memory 184064 kb
Host smart-6a6bdc6f-252f-49a2-b1c7-1bb137e28634
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724381030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2724381030
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3087750074
Short name T356
Test name
Test status
Simulation time 450581921 ps
CPU time 0.85 seconds
Started May 21 02:32:21 PM PDT 24
Finished May 21 02:32:38 PM PDT 24
Peak memory 183716 kb
Host smart-bb2431e7-c064-4ab6-9356-2c836b608aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087750074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3087750074
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.243510918
Short name T345
Test name
Test status
Simulation time 1634064144 ps
CPU time 0.91 seconds
Started May 21 02:32:21 PM PDT 24
Finished May 21 02:32:38 PM PDT 24
Peak memory 193784 kb
Host smart-c9d5e1b5-f051-4fb6-949f-edc3a49c9bc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243510918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.243510918
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1759150326
Short name T378
Test name
Test status
Simulation time 493236859 ps
CPU time 1.35 seconds
Started May 21 02:32:24 PM PDT 24
Finished May 21 02:32:41 PM PDT 24
Peak memory 198564 kb
Host smart-0d342b0d-93df-4fb9-afad-a6a5f8da1f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759150326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1759150326
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3060761041
Short name T32
Test name
Test status
Simulation time 8961168743 ps
CPU time 2.92 seconds
Started May 21 02:32:20 PM PDT 24
Finished May 21 02:32:40 PM PDT 24
Peak memory 198140 kb
Host smart-8a989e3b-c8cb-4659-bca4-9b38c056d104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060761041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3060761041
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2223282984
Short name T380
Test name
Test status
Simulation time 564767109 ps
CPU time 1.51 seconds
Started May 21 02:32:35 PM PDT 24
Finished May 21 02:32:51 PM PDT 24
Peak memory 196164 kb
Host smart-cdce8082-e768-4cd4-b517-33844cbb1d43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223282984 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2223282984
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3989921295
Short name T307
Test name
Test status
Simulation time 408352908 ps
CPU time 0.73 seconds
Started May 21 02:32:22 PM PDT 24
Finished May 21 02:32:39 PM PDT 24
Peak memory 193148 kb
Host smart-2c4803c5-1e64-468b-a99f-fbb6bb28f9be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989921295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3989921295
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1281659391
Short name T375
Test name
Test status
Simulation time 374353362 ps
CPU time 1.09 seconds
Started May 21 02:32:22 PM PDT 24
Finished May 21 02:32:39 PM PDT 24
Peak memory 183708 kb
Host smart-db4feaeb-e06a-4b70-bc6d-ab4d3978f196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281659391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1281659391
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1520614827
Short name T381
Test name
Test status
Simulation time 2525415654 ps
CPU time 3.85 seconds
Started May 21 02:32:27 PM PDT 24
Finished May 21 02:32:46 PM PDT 24
Peak memory 184040 kb
Host smart-472c11a0-364c-4abf-830c-bf8597ebddf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520614827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1520614827
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3328686627
Short name T403
Test name
Test status
Simulation time 332894174 ps
CPU time 1.47 seconds
Started May 21 02:32:21 PM PDT 24
Finished May 21 02:32:39 PM PDT 24
Peak memory 198792 kb
Host smart-0ff2a05f-d39d-4dd0-9f5a-db5830d1f819
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328686627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3328686627
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1686397749
Short name T106
Test name
Test status
Simulation time 4695901061 ps
CPU time 3.91 seconds
Started May 21 02:32:21 PM PDT 24
Finished May 21 02:32:41 PM PDT 24
Peak memory 196268 kb
Host smart-b15a3dda-fea0-44f4-ab63-a33174cebef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686397749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1686397749
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.308830921
Short name T313
Test name
Test status
Simulation time 583784202 ps
CPU time 1.55 seconds
Started May 21 02:32:32 PM PDT 24
Finished May 21 02:32:48 PM PDT 24
Peak memory 195896 kb
Host smart-83bb292f-4fc0-4f26-a4ba-948fabeabac8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308830921 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.308830921
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1592057937
Short name T341
Test name
Test status
Simulation time 522623201 ps
CPU time 0.77 seconds
Started May 21 02:32:31 PM PDT 24
Finished May 21 02:32:47 PM PDT 24
Peak memory 183884 kb
Host smart-b9aae4da-bbb2-4365-a841-7c1131793075
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592057937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1592057937
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2480861122
Short name T339
Test name
Test status
Simulation time 292162388 ps
CPU time 0.63 seconds
Started May 21 02:32:29 PM PDT 24
Finished May 21 02:32:44 PM PDT 24
Peak memory 183712 kb
Host smart-e7610701-df69-4e54-81db-d23c5c47af88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480861122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2480861122
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2514611781
Short name T294
Test name
Test status
Simulation time 915195639 ps
CPU time 1.77 seconds
Started May 21 02:32:33 PM PDT 24
Finished May 21 02:32:49 PM PDT 24
Peak memory 193252 kb
Host smart-8347c01c-6701-48d4-844f-0a23a0512df3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514611781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2514611781
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3647083281
Short name T410
Test name
Test status
Simulation time 491064783 ps
CPU time 2.19 seconds
Started May 21 02:32:29 PM PDT 24
Finished May 21 02:32:46 PM PDT 24
Peak memory 198648 kb
Host smart-532b749b-2c87-4a0b-98da-d68020a7eccc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647083281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3647083281
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3112653800
Short name T314
Test name
Test status
Simulation time 4545110185 ps
CPU time 8.29 seconds
Started May 21 02:32:27 PM PDT 24
Finished May 21 02:32:50 PM PDT 24
Peak memory 197880 kb
Host smart-58853be3-8ac6-4adc-983f-b54582bfa852
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112653800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3112653800
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3426990805
Short name T324
Test name
Test status
Simulation time 522826250 ps
CPU time 1.3 seconds
Started May 21 02:32:34 PM PDT 24
Finished May 21 02:32:49 PM PDT 24
Peak memory 195748 kb
Host smart-ac991665-e074-4485-9a54-70992beac63d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426990805 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3426990805
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.68696411
Short name T58
Test name
Test status
Simulation time 400781541 ps
CPU time 0.87 seconds
Started May 21 02:32:34 PM PDT 24
Finished May 21 02:32:48 PM PDT 24
Peak memory 183812 kb
Host smart-fc6457b9-8367-4b80-a21e-26dfca080479
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68696411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.68696411
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3460063492
Short name T287
Test name
Test status
Simulation time 470800180 ps
CPU time 0.69 seconds
Started May 21 02:32:34 PM PDT 24
Finished May 21 02:32:49 PM PDT 24
Peak memory 183748 kb
Host smart-50d58e70-ab6a-4ddd-a94a-918be78775b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460063492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3460063492
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3562946240
Short name T406
Test name
Test status
Simulation time 1364358456 ps
CPU time 1.23 seconds
Started May 21 02:32:37 PM PDT 24
Finished May 21 02:32:52 PM PDT 24
Peak memory 193352 kb
Host smart-0638a270-04b6-491c-b729-5199173e1a51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562946240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3562946240
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3633171743
Short name T342
Test name
Test status
Simulation time 1083921802 ps
CPU time 2.39 seconds
Started May 21 02:32:33 PM PDT 24
Finished May 21 02:32:49 PM PDT 24
Peak memory 198640 kb
Host smart-98125033-4ac4-4d42-a3da-af1006e884d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633171743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3633171743
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4256709701
Short name T371
Test name
Test status
Simulation time 442477577 ps
CPU time 1.33 seconds
Started May 21 02:32:39 PM PDT 24
Finished May 21 02:32:53 PM PDT 24
Peak memory 195892 kb
Host smart-763e806b-434f-4e44-a852-6cbfa005aae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256709701 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.4256709701
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3368151418
Short name T330
Test name
Test status
Simulation time 513693298 ps
CPU time 0.65 seconds
Started May 21 02:32:32 PM PDT 24
Finished May 21 02:32:47 PM PDT 24
Peak memory 183788 kb
Host smart-f05a55b7-9288-4a33-bd5b-a31338a2fc3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368151418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3368151418
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2051672882
Short name T351
Test name
Test status
Simulation time 385084960 ps
CPU time 1.21 seconds
Started May 21 02:32:32 PM PDT 24
Finished May 21 02:32:48 PM PDT 24
Peak memory 183708 kb
Host smart-11cd886f-1b1a-4e7a-99a8-7af917168944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051672882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2051672882
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1209473566
Short name T296
Test name
Test status
Simulation time 1412149930 ps
CPU time 4.31 seconds
Started May 21 02:32:38 PM PDT 24
Finished May 21 02:32:56 PM PDT 24
Peak memory 193316 kb
Host smart-f5bacfe1-45b4-425d-a488-240b099f8051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209473566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1209473566
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.175335753
Short name T404
Test name
Test status
Simulation time 499245499 ps
CPU time 1.43 seconds
Started May 21 02:32:33 PM PDT 24
Finished May 21 02:32:49 PM PDT 24
Peak memory 198528 kb
Host smart-037224c8-85c9-4411-aac7-fde512558039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175335753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.175335753
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1016572911
Short name T310
Test name
Test status
Simulation time 4315232754 ps
CPU time 6.97 seconds
Started May 21 02:32:32 PM PDT 24
Finished May 21 02:32:54 PM PDT 24
Peak memory 197336 kb
Host smart-1551e276-d155-4824-b36b-3a4ac4846f77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016572911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1016572911
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.953355094
Short name T392
Test name
Test status
Simulation time 573554154 ps
CPU time 1.27 seconds
Started May 21 02:32:42 PM PDT 24
Finished May 21 02:32:56 PM PDT 24
Peak memory 196244 kb
Host smart-68ac8008-e0c2-43cf-a8ab-7704e4d4ada5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953355094 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.953355094
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.793118330
Short name T62
Test name
Test status
Simulation time 521686191 ps
CPU time 1.35 seconds
Started May 21 02:32:43 PM PDT 24
Finished May 21 02:32:57 PM PDT 24
Peak memory 183784 kb
Host smart-fc2daa0b-16ce-4dd2-816c-25b448708c8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793118330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.793118330
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1055921732
Short name T367
Test name
Test status
Simulation time 493026575 ps
CPU time 0.73 seconds
Started May 21 02:32:40 PM PDT 24
Finished May 21 02:32:54 PM PDT 24
Peak memory 183700 kb
Host smart-0ff14e49-3884-43e6-876a-18bfdffc92ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055921732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1055921732
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2492327474
Short name T75
Test name
Test status
Simulation time 2538017987 ps
CPU time 5.71 seconds
Started May 21 02:32:39 PM PDT 24
Finished May 21 02:32:58 PM PDT 24
Peak memory 183992 kb
Host smart-70616791-6eb8-405a-a71f-8ec83d47b3b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492327474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2492327474
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.211594654
Short name T411
Test name
Test status
Simulation time 431460840 ps
CPU time 1.36 seconds
Started May 21 02:32:40 PM PDT 24
Finished May 21 02:32:55 PM PDT 24
Peak memory 198384 kb
Host smart-983d495f-4b89-4728-97e3-72a2f489ddd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211594654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.211594654
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1263614309
Short name T113
Test name
Test status
Simulation time 481473897 ps
CPU time 1.05 seconds
Started May 21 02:32:54 PM PDT 24
Finished May 21 02:33:13 PM PDT 24
Peak memory 198012 kb
Host smart-7926a4d8-665a-4868-95cb-d02dae750808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263614309 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1263614309
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2558680338
Short name T64
Test name
Test status
Simulation time 471998814 ps
CPU time 0.77 seconds
Started May 21 02:32:45 PM PDT 24
Finished May 21 02:33:00 PM PDT 24
Peak memory 193068 kb
Host smart-501d7ba9-e2c6-407e-b47d-e38b7f726f27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558680338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2558680338
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1510444968
Short name T338
Test name
Test status
Simulation time 340459288 ps
CPU time 1.02 seconds
Started May 21 02:32:46 PM PDT 24
Finished May 21 02:33:01 PM PDT 24
Peak memory 183716 kb
Host smart-682a2fb0-3965-480e-b36f-82d75ca6fe3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510444968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1510444968
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2741838551
Short name T33
Test name
Test status
Simulation time 1823886690 ps
CPU time 1.2 seconds
Started May 21 02:32:45 PM PDT 24
Finished May 21 02:32:59 PM PDT 24
Peak memory 193324 kb
Host smart-4d3432ea-9f05-453f-8792-a74c224c952c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741838551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2741838551
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2020600612
Short name T360
Test name
Test status
Simulation time 437346265 ps
CPU time 1.91 seconds
Started May 21 02:32:42 PM PDT 24
Finished May 21 02:32:56 PM PDT 24
Peak memory 198636 kb
Host smart-2b188739-926c-4f88-8ab9-d38e84bcd3c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020600612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2020600612
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.548460799
Short name T396
Test name
Test status
Simulation time 8777141252 ps
CPU time 4.66 seconds
Started May 21 02:32:43 PM PDT 24
Finished May 21 02:33:00 PM PDT 24
Peak memory 198192 kb
Host smart-0d3cd6db-094a-461a-91a6-46c045d2d33c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548460799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.548460799
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.299834330
Short name T59
Test name
Test status
Simulation time 509694193 ps
CPU time 0.96 seconds
Started May 21 02:31:56 PM PDT 24
Finished May 21 02:32:25 PM PDT 24
Peak memory 194208 kb
Host smart-6a453440-4294-49f0-bee1-39533782271d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299834330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.299834330
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1317173773
Short name T111
Test name
Test status
Simulation time 6950891318 ps
CPU time 5.63 seconds
Started May 21 02:31:49 PM PDT 24
Finished May 21 02:32:25 PM PDT 24
Peak memory 192284 kb
Host smart-b66ece16-e546-4526-a762-b2a0d36b82a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317173773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1317173773
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.416374067
Short name T284
Test name
Test status
Simulation time 772027985 ps
CPU time 0.89 seconds
Started May 21 02:31:58 PM PDT 24
Finished May 21 02:32:26 PM PDT 24
Peak memory 183840 kb
Host smart-102e013e-8aaf-45d3-8a14-c61aab5767da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416374067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.416374067
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.427169206
Short name T387
Test name
Test status
Simulation time 471376694 ps
CPU time 0.88 seconds
Started May 21 02:31:56 PM PDT 24
Finished May 21 02:32:25 PM PDT 24
Peak memory 197404 kb
Host smart-34b9b9e2-1b58-407f-83f8-25c680803f8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427169206 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.427169206
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2626815231
Short name T308
Test name
Test status
Simulation time 512733532 ps
CPU time 0.97 seconds
Started May 21 02:31:51 PM PDT 24
Finished May 21 02:32:22 PM PDT 24
Peak memory 183904 kb
Host smart-28279e28-a839-4b2b-a8d8-fc2ec8422a44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626815231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2626815231
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.906986115
Short name T344
Test name
Test status
Simulation time 447609833 ps
CPU time 0.91 seconds
Started May 21 02:31:53 PM PDT 24
Finished May 21 02:32:23 PM PDT 24
Peak memory 183712 kb
Host smart-3213c77a-51a4-48a5-9638-e468f45c395f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906986115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.906986115
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3795382655
Short name T292
Test name
Test status
Simulation time 409152230 ps
CPU time 0.66 seconds
Started May 21 02:31:53 PM PDT 24
Finished May 21 02:32:23 PM PDT 24
Peak memory 183628 kb
Host smart-51223a5d-1d55-4647-8e45-359ceca8c66d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795382655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3795382655
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2328121670
Short name T402
Test name
Test status
Simulation time 507038250 ps
CPU time 0.7 seconds
Started May 21 02:31:51 PM PDT 24
Finished May 21 02:32:21 PM PDT 24
Peak memory 183660 kb
Host smart-52c9e52d-b710-436f-aa4e-e32baeca2e32
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328121670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2328121670
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2376743120
Short name T72
Test name
Test status
Simulation time 988293334 ps
CPU time 1.27 seconds
Started May 21 02:32:00 PM PDT 24
Finished May 21 02:32:27 PM PDT 24
Peak memory 183844 kb
Host smart-832bd69e-b207-4a96-94af-4371f6095f1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376743120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2376743120
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2939719954
Short name T288
Test name
Test status
Simulation time 333906621 ps
CPU time 2.88 seconds
Started May 21 02:31:50 PM PDT 24
Finished May 21 02:32:23 PM PDT 24
Peak memory 198604 kb
Host smart-513720a2-9763-4436-9441-0454d85154e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939719954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2939719954
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.915644371
Short name T109
Test name
Test status
Simulation time 7977836715 ps
CPU time 3.79 seconds
Started May 21 02:31:53 PM PDT 24
Finished May 21 02:32:26 PM PDT 24
Peak memory 198088 kb
Host smart-089d409f-21b9-4c89-8a61-adc08b49cf81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915644371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.915644371
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3394424690
Short name T323
Test name
Test status
Simulation time 300075056 ps
CPU time 0.64 seconds
Started May 21 02:32:45 PM PDT 24
Finished May 21 02:32:59 PM PDT 24
Peak memory 183664 kb
Host smart-08921c49-00cb-4b16-a92d-ee28e5abe1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394424690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3394424690
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3483819618
Short name T359
Test name
Test status
Simulation time 340921178 ps
CPU time 1.06 seconds
Started May 21 02:32:50 PM PDT 24
Finished May 21 02:33:08 PM PDT 24
Peak memory 183684 kb
Host smart-7842cbd8-c21f-4c67-b45d-663fa775716d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483819618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3483819618
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2572998133
Short name T384
Test name
Test status
Simulation time 468224053 ps
CPU time 0.81 seconds
Started May 21 02:32:46 PM PDT 24
Finished May 21 02:33:01 PM PDT 24
Peak memory 183624 kb
Host smart-1871dfae-985d-4253-ab39-37ddd7222ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572998133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2572998133
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3806210717
Short name T358
Test name
Test status
Simulation time 297057155 ps
CPU time 0.94 seconds
Started May 21 02:32:47 PM PDT 24
Finished May 21 02:33:02 PM PDT 24
Peak memory 183708 kb
Host smart-c3901b5d-3863-4517-a4a8-f26bbe2af0b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806210717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3806210717
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2379777923
Short name T399
Test name
Test status
Simulation time 424407730 ps
CPU time 0.6 seconds
Started May 21 02:32:49 PM PDT 24
Finished May 21 02:33:06 PM PDT 24
Peak memory 183688 kb
Host smart-294d1ff2-d167-41b7-a7bf-e2c86e807484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379777923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2379777923
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.38764673
Short name T352
Test name
Test status
Simulation time 416664772 ps
CPU time 1.22 seconds
Started May 21 02:32:52 PM PDT 24
Finished May 21 02:33:12 PM PDT 24
Peak memory 183684 kb
Host smart-953f3086-626b-411c-97b3-bb161c53b4e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38764673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.38764673
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.254560373
Short name T408
Test name
Test status
Simulation time 394442065 ps
CPU time 0.84 seconds
Started May 21 02:32:47 PM PDT 24
Finished May 21 02:33:03 PM PDT 24
Peak memory 183680 kb
Host smart-20490365-f9c3-4952-8f8a-15d314e467d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254560373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.254560373
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2744651782
Short name T415
Test name
Test status
Simulation time 324602463 ps
CPU time 0.69 seconds
Started May 21 02:32:47 PM PDT 24
Finished May 21 02:33:03 PM PDT 24
Peak memory 183680 kb
Host smart-d6581ece-dfe2-4762-ad18-6e9f907a4130
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744651782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2744651782
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1855954523
Short name T377
Test name
Test status
Simulation time 389366914 ps
CPU time 1.1 seconds
Started May 21 02:32:47 PM PDT 24
Finished May 21 02:33:04 PM PDT 24
Peak memory 183716 kb
Host smart-afae4afd-a40e-4bd2-84cd-60ca7f05cebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855954523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1855954523
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2653814645
Short name T311
Test name
Test status
Simulation time 353421932 ps
CPU time 0.78 seconds
Started May 21 02:32:54 PM PDT 24
Finished May 21 02:33:13 PM PDT 24
Peak memory 183680 kb
Host smart-7155425c-4a14-45a4-8b72-ede40d097163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653814645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2653814645
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1826249960
Short name T412
Test name
Test status
Simulation time 478613688 ps
CPU time 0.78 seconds
Started May 21 02:32:05 PM PDT 24
Finished May 21 02:32:30 PM PDT 24
Peak memory 183780 kb
Host smart-9a26d118-a7c9-4fdf-9f2d-ce4afa7964e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826249960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1826249960
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.435355115
Short name T63
Test name
Test status
Simulation time 9793673411 ps
CPU time 3.58 seconds
Started May 21 02:32:03 PM PDT 24
Finished May 21 02:32:32 PM PDT 24
Peak memory 192312 kb
Host smart-6e86d3f4-9411-470a-a1a1-7f2f42c77c93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435355115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.435355115
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3915600874
Short name T68
Test name
Test status
Simulation time 1033165262 ps
CPU time 2.19 seconds
Started May 21 02:32:02 PM PDT 24
Finished May 21 02:32:29 PM PDT 24
Peak memory 183776 kb
Host smart-51628b6a-3b4b-4c17-84fc-6f5e70b4d5a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915600874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3915600874
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1064828536
Short name T329
Test name
Test status
Simulation time 345889298 ps
CPU time 1.1 seconds
Started May 21 02:32:03 PM PDT 24
Finished May 21 02:32:29 PM PDT 24
Peak memory 195704 kb
Host smart-9e41feb9-84e2-4a16-88db-e451f037ce8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064828536 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1064828536
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.338375912
Short name T70
Test name
Test status
Simulation time 348512696 ps
CPU time 0.63 seconds
Started May 21 02:32:02 PM PDT 24
Finished May 21 02:32:28 PM PDT 24
Peak memory 193096 kb
Host smart-6e8da78e-b193-4b4a-9b58-a5bb6056ed13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338375912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.338375912
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3713141156
Short name T379
Test name
Test status
Simulation time 458520301 ps
CPU time 0.84 seconds
Started May 21 02:32:00 PM PDT 24
Finished May 21 02:32:27 PM PDT 24
Peak memory 183724 kb
Host smart-616e325a-d2ed-4045-8589-ee31e5091129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713141156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3713141156
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4233243745
Short name T336
Test name
Test status
Simulation time 367659276 ps
CPU time 1.07 seconds
Started May 21 02:31:58 PM PDT 24
Finished May 21 02:32:26 PM PDT 24
Peak memory 183600 kb
Host smart-246cbdcd-71bd-4aab-9517-222dc0aa651d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233243745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.4233243745
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1987473963
Short name T389
Test name
Test status
Simulation time 375557970 ps
CPU time 0.67 seconds
Started May 21 02:31:57 PM PDT 24
Finished May 21 02:32:25 PM PDT 24
Peak memory 183700 kb
Host smart-92adcc57-9676-4e03-bc8b-ca828b1874e5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987473963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1987473963
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3858341847
Short name T27
Test name
Test status
Simulation time 1394184525 ps
CPU time 2.88 seconds
Started May 21 02:32:05 PM PDT 24
Finished May 21 02:32:32 PM PDT 24
Peak memory 193232 kb
Host smart-bf2ff851-1526-433c-8bc9-8c1f76a07cb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858341847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3858341847
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3251989747
Short name T409
Test name
Test status
Simulation time 380189397 ps
CPU time 2.35 seconds
Started May 21 02:31:58 PM PDT 24
Finished May 21 02:32:28 PM PDT 24
Peak memory 198600 kb
Host smart-c3f26e14-3c57-48b1-9280-45a59dd24f29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251989747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3251989747
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.110285499
Short name T107
Test name
Test status
Simulation time 4339207409 ps
CPU time 7.77 seconds
Started May 21 02:31:58 PM PDT 24
Finished May 21 02:32:33 PM PDT 24
Peak memory 197648 kb
Host smart-35e35289-0863-4804-bac7-86a1634ca2b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110285499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.110285499
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1324758173
Short name T414
Test name
Test status
Simulation time 471161300 ps
CPU time 0.71 seconds
Started May 21 02:32:50 PM PDT 24
Finished May 21 02:33:08 PM PDT 24
Peak memory 183684 kb
Host smart-e4f5de05-bee4-4e5b-8466-cc77017f0750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324758173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1324758173
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3763295465
Short name T285
Test name
Test status
Simulation time 339215570 ps
CPU time 0.69 seconds
Started May 21 02:32:47 PM PDT 24
Finished May 21 02:33:03 PM PDT 24
Peak memory 183708 kb
Host smart-edfe556a-2b25-4506-ae02-3621caec467a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763295465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3763295465
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.664904987
Short name T309
Test name
Test status
Simulation time 278863941 ps
CPU time 0.75 seconds
Started May 21 02:32:46 PM PDT 24
Finished May 21 02:33:02 PM PDT 24
Peak memory 183704 kb
Host smart-84e44097-2368-48b0-93a9-e1c3b1324a24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664904987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.664904987
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3674736208
Short name T364
Test name
Test status
Simulation time 326026282 ps
CPU time 0.66 seconds
Started May 21 02:32:50 PM PDT 24
Finished May 21 02:33:09 PM PDT 24
Peak memory 183684 kb
Host smart-c112d90c-0f3f-4ab2-b090-29f693545b90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674736208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3674736208
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2012174235
Short name T319
Test name
Test status
Simulation time 450240053 ps
CPU time 1.26 seconds
Started May 21 02:32:45 PM PDT 24
Finished May 21 02:33:00 PM PDT 24
Peak memory 183744 kb
Host smart-8a296707-7796-430c-956e-2d5332e01c8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012174235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2012174235
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4219537590
Short name T401
Test name
Test status
Simulation time 335969589 ps
CPU time 0.78 seconds
Started May 21 02:32:46 PM PDT 24
Finished May 21 02:33:01 PM PDT 24
Peak memory 183668 kb
Host smart-a56d3b1d-d2c4-491d-a112-eb2f297255c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219537590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.4219537590
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3572242546
Short name T382
Test name
Test status
Simulation time 390825856 ps
CPU time 1.14 seconds
Started May 21 02:32:49 PM PDT 24
Finished May 21 02:33:07 PM PDT 24
Peak memory 183128 kb
Host smart-b0763496-d5e1-4422-82a5-68fee3bf4914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572242546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3572242546
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1283673785
Short name T327
Test name
Test status
Simulation time 427290078 ps
CPU time 0.77 seconds
Started May 21 02:32:53 PM PDT 24
Finished May 21 02:33:13 PM PDT 24
Peak memory 183672 kb
Host smart-44b35572-0dcd-4081-a2a1-06513969c271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283673785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1283673785
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3881729016
Short name T346
Test name
Test status
Simulation time 455538822 ps
CPU time 1.26 seconds
Started May 21 02:32:45 PM PDT 24
Finished May 21 02:33:00 PM PDT 24
Peak memory 183668 kb
Host smart-88ae922c-c93b-4721-ad13-812ae29c0644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881729016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3881729016
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4143002877
Short name T395
Test name
Test status
Simulation time 432127621 ps
CPU time 0.82 seconds
Started May 21 02:32:49 PM PDT 24
Finished May 21 02:33:07 PM PDT 24
Peak memory 183736 kb
Host smart-3da156fd-1be1-4a11-a227-6ae65ceb1807
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143002877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4143002877
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1203605201
Short name T65
Test name
Test status
Simulation time 558526199 ps
CPU time 1.03 seconds
Started May 21 02:32:05 PM PDT 24
Finished May 21 02:32:30 PM PDT 24
Peak memory 183880 kb
Host smart-d103fb1c-5d11-4dbf-b93c-46b185b47238
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203605201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1203605201
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3029049557
Short name T61
Test name
Test status
Simulation time 4603670951 ps
CPU time 8.98 seconds
Started May 21 02:32:05 PM PDT 24
Finished May 21 02:32:38 PM PDT 24
Peak memory 192312 kb
Host smart-ee0fba87-6069-441d-bdf8-6aca8d10e565
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029049557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3029049557
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.942334583
Short name T332
Test name
Test status
Simulation time 852994162 ps
CPU time 2.01 seconds
Started May 21 02:32:08 PM PDT 24
Finished May 21 02:32:33 PM PDT 24
Peak memory 183852 kb
Host smart-75b9e904-0cdd-44b3-a237-3b72e1e6ca71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942334583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.942334583
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1427835410
Short name T112
Test name
Test status
Simulation time 444307897 ps
CPU time 1.31 seconds
Started May 21 02:32:05 PM PDT 24
Finished May 21 02:32:30 PM PDT 24
Peak memory 195816 kb
Host smart-03f4d63b-fa84-4e11-9688-4b85402eb776
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427835410 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1427835410
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1809139008
Short name T28
Test name
Test status
Simulation time 453329167 ps
CPU time 0.72 seconds
Started May 21 02:32:02 PM PDT 24
Finished May 21 02:32:28 PM PDT 24
Peak memory 193068 kb
Host smart-6b3e3005-2774-40e2-a28b-ae79c24df977
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809139008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1809139008
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.666319498
Short name T350
Test name
Test status
Simulation time 288547662 ps
CPU time 0.78 seconds
Started May 21 02:32:02 PM PDT 24
Finished May 21 02:32:28 PM PDT 24
Peak memory 183700 kb
Host smart-1a10ecf9-e0cc-4b75-aefa-0a5b8145e6b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666319498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.666319498
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1489995880
Short name T366
Test name
Test status
Simulation time 418300584 ps
CPU time 0.85 seconds
Started May 21 02:32:07 PM PDT 24
Finished May 21 02:32:31 PM PDT 24
Peak memory 183600 kb
Host smart-7a321257-2d8d-48e3-8260-56f366eebece
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489995880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1489995880
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1392646697
Short name T291
Test name
Test status
Simulation time 273509012 ps
CPU time 0.72 seconds
Started May 21 02:32:03 PM PDT 24
Finished May 21 02:32:28 PM PDT 24
Peak memory 183700 kb
Host smart-8fe30bd2-9581-4075-b8f2-96d526ef37d9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392646697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1392646697
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1841696086
Short name T398
Test name
Test status
Simulation time 1291948445 ps
CPU time 1.58 seconds
Started May 21 02:32:07 PM PDT 24
Finished May 21 02:32:32 PM PDT 24
Peak memory 193360 kb
Host smart-b2ed69b4-05c8-4884-86b9-88ec3c170bdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841696086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1841696086
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.449776991
Short name T397
Test name
Test status
Simulation time 517057000 ps
CPU time 2.17 seconds
Started May 21 02:32:02 PM PDT 24
Finished May 21 02:32:30 PM PDT 24
Peak memory 198536 kb
Host smart-d383b413-58b7-4628-b7ed-0c6a6b401773
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449776991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.449776991
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3694038106
Short name T31
Test name
Test status
Simulation time 4243310852 ps
CPU time 1.99 seconds
Started May 21 02:32:05 PM PDT 24
Finished May 21 02:32:31 PM PDT 24
Peak memory 197516 kb
Host smart-9c215062-65eb-4d97-a44e-c52b51ad11db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694038106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3694038106
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1733895935
Short name T337
Test name
Test status
Simulation time 329112554 ps
CPU time 0.67 seconds
Started May 21 02:32:46 PM PDT 24
Finished May 21 02:33:01 PM PDT 24
Peak memory 183676 kb
Host smart-fc7b4ab0-23c1-4e7a-92a7-9ec3bf5b5825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733895935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1733895935
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2067396007
Short name T369
Test name
Test status
Simulation time 511901511 ps
CPU time 0.71 seconds
Started May 21 02:32:49 PM PDT 24
Finished May 21 02:33:06 PM PDT 24
Peak memory 183048 kb
Host smart-6ab2366f-3aeb-482e-85e1-a3231aac06a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067396007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2067396007
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2783468147
Short name T306
Test name
Test status
Simulation time 454577282 ps
CPU time 0.71 seconds
Started May 21 02:32:52 PM PDT 24
Finished May 21 02:33:12 PM PDT 24
Peak memory 183680 kb
Host smart-2cc7bbf7-e121-4f5d-80c3-4dbaf8f8218b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783468147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2783468147
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.19189486
Short name T283
Test name
Test status
Simulation time 428836040 ps
CPU time 0.79 seconds
Started May 21 02:32:52 PM PDT 24
Finished May 21 02:33:12 PM PDT 24
Peak memory 183700 kb
Host smart-d8ec8441-4890-453f-b4f9-ca2e5ad3f6ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19189486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.19189486
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2957238763
Short name T394
Test name
Test status
Simulation time 308970755 ps
CPU time 0.64 seconds
Started May 21 02:32:53 PM PDT 24
Finished May 21 02:33:12 PM PDT 24
Peak memory 183716 kb
Host smart-d7e6558f-a0b0-4bfb-ae4c-00bc92e56108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957238763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2957238763
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1633586594
Short name T293
Test name
Test status
Simulation time 318724586 ps
CPU time 0.68 seconds
Started May 21 02:32:53 PM PDT 24
Finished May 21 02:33:12 PM PDT 24
Peak memory 183708 kb
Host smart-891294bd-1d9a-4ae1-ba1d-bc4e47949a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633586594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1633586594
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1423008062
Short name T328
Test name
Test status
Simulation time 498478362 ps
CPU time 0.64 seconds
Started May 21 02:32:52 PM PDT 24
Finished May 21 02:33:11 PM PDT 24
Peak memory 183704 kb
Host smart-531f6fab-9d10-4f2a-9ad3-71f257073a36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423008062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1423008062
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2070052257
Short name T372
Test name
Test status
Simulation time 412301323 ps
CPU time 1.16 seconds
Started May 21 02:32:52 PM PDT 24
Finished May 21 02:33:11 PM PDT 24
Peak memory 183676 kb
Host smart-0e9eb7e7-3d58-424b-9cc5-0c019a28e821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070052257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2070052257
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.4062294460
Short name T383
Test name
Test status
Simulation time 305798555 ps
CPU time 0.62 seconds
Started May 21 02:32:56 PM PDT 24
Finished May 21 02:33:16 PM PDT 24
Peak memory 183680 kb
Host smart-a718d6fb-dc91-4486-9f98-61d53472792d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062294460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.4062294460
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3844802722
Short name T343
Test name
Test status
Simulation time 432437196 ps
CPU time 0.7 seconds
Started May 21 02:32:55 PM PDT 24
Finished May 21 02:33:15 PM PDT 24
Peak memory 183708 kb
Host smart-b157539d-fc32-4f8f-9668-5b22c9b24330
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844802722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3844802722
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.649382741
Short name T393
Test name
Test status
Simulation time 392229831 ps
CPU time 0.82 seconds
Started May 21 02:32:07 PM PDT 24
Finished May 21 02:32:31 PM PDT 24
Peak memory 195504 kb
Host smart-637276f9-9916-4dca-a7bc-3689ab3ce282
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649382741 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.649382741
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.925106343
Short name T304
Test name
Test status
Simulation time 305089930 ps
CPU time 1.02 seconds
Started May 21 02:32:06 PM PDT 24
Finished May 21 02:32:31 PM PDT 24
Peak memory 193080 kb
Host smart-3ee8ce34-86f3-4a74-9a98-4d0d86431326
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925106343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.925106343
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3804156524
Short name T335
Test name
Test status
Simulation time 430603883 ps
CPU time 0.68 seconds
Started May 21 02:32:04 PM PDT 24
Finished May 21 02:32:28 PM PDT 24
Peak memory 183680 kb
Host smart-d3923862-d4cb-444c-83b0-0557c3c6303d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804156524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3804156524
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1075943133
Short name T370
Test name
Test status
Simulation time 1190577280 ps
CPU time 1.22 seconds
Started May 21 02:32:06 PM PDT 24
Finished May 21 02:32:31 PM PDT 24
Peak memory 193216 kb
Host smart-8b61ac52-8ced-43f2-ba88-69648e793c45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075943133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1075943133
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2316950785
Short name T312
Test name
Test status
Simulation time 367755291 ps
CPU time 2.18 seconds
Started May 21 02:32:03 PM PDT 24
Finished May 21 02:32:30 PM PDT 24
Peak memory 198616 kb
Host smart-18db1f40-d1f3-4f14-8df4-974ea541c3d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316950785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2316950785
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2913177736
Short name T374
Test name
Test status
Simulation time 8293971917 ps
CPU time 13.94 seconds
Started May 21 02:32:06 PM PDT 24
Finished May 21 02:32:43 PM PDT 24
Peak memory 197852 kb
Host smart-705797e3-054d-493e-bb74-1d5d06d41989
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913177736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2913177736
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3821268195
Short name T298
Test name
Test status
Simulation time 486692737 ps
CPU time 1.12 seconds
Started May 21 02:32:04 PM PDT 24
Finished May 21 02:32:29 PM PDT 24
Peak memory 198452 kb
Host smart-075d90b9-a2a5-4305-8c15-5a6e6c162477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821268195 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3821268195
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.198297580
Short name T373
Test name
Test status
Simulation time 331567731 ps
CPU time 1 seconds
Started May 21 02:32:06 PM PDT 24
Finished May 21 02:32:30 PM PDT 24
Peak memory 183780 kb
Host smart-9aa5fe55-c1d0-4ecb-ad77-c86bf53c5d4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198297580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.198297580
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4180815040
Short name T325
Test name
Test status
Simulation time 429988144 ps
CPU time 0.72 seconds
Started May 21 02:32:06 PM PDT 24
Finished May 21 02:32:30 PM PDT 24
Peak memory 183708 kb
Host smart-7e4ba4a2-2d8f-4a3c-ae5c-dbb4a63f9b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180815040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.4180815040
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.4208770377
Short name T413
Test name
Test status
Simulation time 2413650246 ps
CPU time 3.27 seconds
Started May 21 02:32:06 PM PDT 24
Finished May 21 02:32:33 PM PDT 24
Peak memory 194580 kb
Host smart-0bbaecdd-81dd-4e5f-997f-3a147eb5336e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208770377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.4208770377
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2580768451
Short name T417
Test name
Test status
Simulation time 538374019 ps
CPU time 1.52 seconds
Started May 21 02:32:06 PM PDT 24
Finished May 21 02:32:31 PM PDT 24
Peak memory 198460 kb
Host smart-8ad653ab-6b80-4f4b-b020-5bc0d348a9d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580768451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2580768451
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.564181317
Short name T363
Test name
Test status
Simulation time 4373147882 ps
CPU time 1.19 seconds
Started May 21 02:32:05 PM PDT 24
Finished May 21 02:32:30 PM PDT 24
Peak memory 196664 kb
Host smart-ac987e11-1764-4177-bb6f-52c83180e5cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564181317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.564181317
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4106627722
Short name T318
Test name
Test status
Simulation time 421276575 ps
CPU time 0.76 seconds
Started May 21 02:32:10 PM PDT 24
Finished May 21 02:32:32 PM PDT 24
Peak memory 195456 kb
Host smart-71deb803-18f6-4f3c-8540-f0d69cedaf0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106627722 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.4106627722
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3517636552
Short name T388
Test name
Test status
Simulation time 528014931 ps
CPU time 0.94 seconds
Started May 21 02:32:09 PM PDT 24
Finished May 21 02:32:32 PM PDT 24
Peak memory 183800 kb
Host smart-ca95da42-26c5-4599-afff-c1c4dfe75660
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517636552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3517636552
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1607291851
Short name T349
Test name
Test status
Simulation time 494705285 ps
CPU time 0.71 seconds
Started May 21 02:32:09 PM PDT 24
Finished May 21 02:32:33 PM PDT 24
Peak memory 183752 kb
Host smart-d9625c4d-9da3-4e08-b3b7-519fa639d63b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607291851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1607291851
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1672628095
Short name T355
Test name
Test status
Simulation time 2338347409 ps
CPU time 4.18 seconds
Started May 21 02:32:11 PM PDT 24
Finished May 21 02:32:37 PM PDT 24
Peak memory 194448 kb
Host smart-fb460c63-4e53-4e6c-bab8-cfffec5734f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672628095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1672628095
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3193914831
Short name T302
Test name
Test status
Simulation time 335362100 ps
CPU time 1.82 seconds
Started May 21 02:32:10 PM PDT 24
Finished May 21 02:32:34 PM PDT 24
Peak memory 198632 kb
Host smart-f7aaa4ef-bd53-4395-a84f-96e7642a001d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193914831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3193914831
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1990405420
Short name T400
Test name
Test status
Simulation time 8320367199 ps
CPU time 8.32 seconds
Started May 21 02:32:09 PM PDT 24
Finished May 21 02:32:40 PM PDT 24
Peak memory 198044 kb
Host smart-ebc3cca9-03e0-43d4-9528-46dfc6b1dd6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990405420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1990405420
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1789202306
Short name T361
Test name
Test status
Simulation time 539232526 ps
CPU time 1.07 seconds
Started May 21 02:32:09 PM PDT 24
Finished May 21 02:32:33 PM PDT 24
Peak memory 195344 kb
Host smart-89413f79-777b-4d61-af9c-5c6b79577947
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789202306 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1789202306
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3013443810
Short name T66
Test name
Test status
Simulation time 288656524 ps
CPU time 0.94 seconds
Started May 21 02:32:09 PM PDT 24
Finished May 21 02:32:33 PM PDT 24
Peak memory 193140 kb
Host smart-c7537781-cf9f-4478-b69a-a063ed4cb77c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013443810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3013443810
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2618169273
Short name T368
Test name
Test status
Simulation time 547792970 ps
CPU time 0.62 seconds
Started May 21 02:32:10 PM PDT 24
Finished May 21 02:32:32 PM PDT 24
Peak memory 183720 kb
Host smart-811f22f6-c70d-4c2d-acba-0cb26d2a7681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618169273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2618169273
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.342293086
Short name T385
Test name
Test status
Simulation time 2681213523 ps
CPU time 1.83 seconds
Started May 21 02:32:09 PM PDT 24
Finished May 21 02:32:33 PM PDT 24
Peak memory 194408 kb
Host smart-615bc3ee-ef4c-4f61-ad0f-fbb6931fc10b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342293086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.342293086
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1204792011
Short name T297
Test name
Test status
Simulation time 715755927 ps
CPU time 1.99 seconds
Started May 21 02:32:08 PM PDT 24
Finished May 21 02:32:33 PM PDT 24
Peak memory 198592 kb
Host smart-5c157235-7361-41ea-b877-fdd2cddb302f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204792011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1204792011
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1116277791
Short name T110
Test name
Test status
Simulation time 8074057987 ps
CPU time 7.22 seconds
Started May 21 02:32:09 PM PDT 24
Finished May 21 02:32:39 PM PDT 24
Peak memory 197948 kb
Host smart-c5c8af6c-0781-484b-82aa-10f752031f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116277791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1116277791
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1678825450
Short name T315
Test name
Test status
Simulation time 891414846 ps
CPU time 0.78 seconds
Started May 21 02:32:09 PM PDT 24
Finished May 21 02:32:32 PM PDT 24
Peak memory 196160 kb
Host smart-f2f486b0-f8e4-4d1f-a501-b1872a36c790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678825450 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1678825450
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1315828711
Short name T365
Test name
Test status
Simulation time 462820147 ps
CPU time 1.31 seconds
Started May 21 02:32:12 PM PDT 24
Finished May 21 02:32:33 PM PDT 24
Peak memory 193132 kb
Host smart-cd996166-8148-4bb1-8969-19cc7dcffa9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315828711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1315828711
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1833677624
Short name T391
Test name
Test status
Simulation time 400127182 ps
CPU time 0.8 seconds
Started May 21 02:32:09 PM PDT 24
Finished May 21 02:32:32 PM PDT 24
Peak memory 183724 kb
Host smart-4ad6eff8-45a5-49a9-b355-ca0c978f5bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833677624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1833677624
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.158131134
Short name T73
Test name
Test status
Simulation time 1393486931 ps
CPU time 2.64 seconds
Started May 21 02:32:10 PM PDT 24
Finished May 21 02:32:35 PM PDT 24
Peak memory 183884 kb
Host smart-626c2564-ebd2-4c8c-ae82-5637d7ffebd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158131134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.158131134
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3689771501
Short name T416
Test name
Test status
Simulation time 597871292 ps
CPU time 1.87 seconds
Started May 21 02:32:09 PM PDT 24
Finished May 21 02:32:33 PM PDT 24
Peak memory 198564 kb
Host smart-7cf479ae-c140-421d-ba19-9e002d733320
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689771501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3689771501
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3880764304
Short name T354
Test name
Test status
Simulation time 8223925856 ps
CPU time 11.82 seconds
Started May 21 02:32:09 PM PDT 24
Finished May 21 02:32:43 PM PDT 24
Peak memory 198124 kb
Host smart-94e30b1e-f747-4613-bfd1-202b4e94be47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880764304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3880764304
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2905109827
Short name T262
Test name
Test status
Simulation time 448963896 ps
CPU time 0.88 seconds
Started May 21 02:10:20 PM PDT 24
Finished May 21 02:10:25 PM PDT 24
Peak memory 183392 kb
Host smart-3a23c61a-055d-4a2a-8308-dd0377f36361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905109827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2905109827
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.776401240
Short name T126
Test name
Test status
Simulation time 18249189276 ps
CPU time 11.66 seconds
Started May 21 02:10:19 PM PDT 24
Finished May 21 02:10:34 PM PDT 24
Peak memory 192016 kb
Host smart-5f2069d9-1cd0-4582-99f7-826d5b5ace9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776401240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.776401240
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2519320647
Short name T181
Test name
Test status
Simulation time 414435723 ps
CPU time 0.65 seconds
Started May 21 02:10:20 PM PDT 24
Finished May 21 02:10:24 PM PDT 24
Peak memory 183504 kb
Host smart-2a872e3e-0445-42bf-947b-e9010e53c892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519320647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2519320647
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3360939983
Short name T224
Test name
Test status
Simulation time 256918192883 ps
CPU time 180.59 seconds
Started May 21 02:10:17 PM PDT 24
Finished May 21 02:13:21 PM PDT 24
Peak memory 183592 kb
Host smart-c723404b-7a33-4b92-ad4a-d3b95b1e5132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360939983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3360939983
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.122918865
Short name T51
Test name
Test status
Simulation time 35270528945 ps
CPU time 299.15 seconds
Started May 21 02:10:19 PM PDT 24
Finished May 21 02:15:21 PM PDT 24
Peak memory 198408 kb
Host smart-04982656-0744-44cd-b406-c83064461bb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122918865 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.122918865
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3579204084
Short name T166
Test name
Test status
Simulation time 528189360 ps
CPU time 0.73 seconds
Started May 21 02:10:18 PM PDT 24
Finished May 21 02:10:23 PM PDT 24
Peak memory 183404 kb
Host smart-0129d99e-7cde-4f2f-ac14-37117bd05dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579204084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3579204084
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1847616584
Short name T130
Test name
Test status
Simulation time 50471329931 ps
CPU time 5.64 seconds
Started May 21 02:10:21 PM PDT 24
Finished May 21 02:10:31 PM PDT 24
Peak memory 191372 kb
Host smart-a06f96bf-73fd-4c63-9d79-cc95ba6a817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847616584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1847616584
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3366726934
Short name T15
Test name
Test status
Simulation time 4377157816 ps
CPU time 3.84 seconds
Started May 21 02:10:22 PM PDT 24
Finished May 21 02:10:30 PM PDT 24
Peak memory 215136 kb
Host smart-7c7eed63-b5b1-4b2c-a779-61f78b8b4839
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366726934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3366726934
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1356010197
Short name T9
Test name
Test status
Simulation time 590836456 ps
CPU time 0.75 seconds
Started May 21 02:10:22 PM PDT 24
Finished May 21 02:10:27 PM PDT 24
Peak memory 183540 kb
Host smart-3c0cdb46-7a46-44f7-8ef8-b0c3f220df8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356010197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1356010197
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.885761059
Short name T98
Test name
Test status
Simulation time 71071474374 ps
CPU time 55.08 seconds
Started May 21 02:10:21 PM PDT 24
Finished May 21 02:11:20 PM PDT 24
Peak memory 194072 kb
Host smart-69876a24-44fc-456d-be06-5f9a88c5cd45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885761059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.885761059
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.661177817
Short name T199
Test name
Test status
Simulation time 297134665909 ps
CPU time 605.58 seconds
Started May 21 02:10:16 PM PDT 24
Finished May 21 02:20:25 PM PDT 24
Peak memory 207828 kb
Host smart-36b3b393-bd80-4610-ae1c-21c6307fb5d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661177817 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.661177817
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1354405988
Short name T78
Test name
Test status
Simulation time 409426320 ps
CPU time 1.19 seconds
Started May 21 02:10:29 PM PDT 24
Finished May 21 02:10:33 PM PDT 24
Peak memory 183520 kb
Host smart-78293d89-ee11-4151-a03d-84d5f2f2f934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354405988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1354405988
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3672493407
Short name T216
Test name
Test status
Simulation time 23328070073 ps
CPU time 38.23 seconds
Started May 21 02:10:32 PM PDT 24
Finished May 21 02:11:12 PM PDT 24
Peak memory 183508 kb
Host smart-de174bfb-971f-4195-817d-b48689c55320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672493407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3672493407
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1197500731
Short name T250
Test name
Test status
Simulation time 556024985 ps
CPU time 1.36 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:10:32 PM PDT 24
Peak memory 183544 kb
Host smart-468dfd5c-d2a1-406a-a96c-a752d369df9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197500731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1197500731
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3938948256
Short name T190
Test name
Test status
Simulation time 168867864868 ps
CPU time 129.11 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:12:41 PM PDT 24
Peak memory 191768 kb
Host smart-97e1c8a0-550e-4c98-bfce-f0988c042c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938948256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3938948256
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.4124860442
Short name T248
Test name
Test status
Simulation time 364343280624 ps
CPU time 815.73 seconds
Started May 21 02:10:30 PM PDT 24
Finished May 21 02:24:09 PM PDT 24
Peak memory 201796 kb
Host smart-94e517b8-97c1-483c-94c0-7ab6fe5cd385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124860442 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.4124860442
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.427512252
Short name T141
Test name
Test status
Simulation time 467411545 ps
CPU time 0.95 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:10:32 PM PDT 24
Peak memory 183392 kb
Host smart-5fab6fa6-23b4-455b-85f2-dc7101268084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427512252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.427512252
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.4027385456
Short name T242
Test name
Test status
Simulation time 39645689165 ps
CPU time 14.78 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:10:46 PM PDT 24
Peak memory 191768 kb
Host smart-b01e34ee-5571-4432-9dbf-1aa67229f542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027385456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.4027385456
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.147939493
Short name T148
Test name
Test status
Simulation time 336127930 ps
CPU time 0.67 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:10:32 PM PDT 24
Peak memory 183508 kb
Host smart-dce72ac6-69da-48a9-9573-0058043a5323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147939493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.147939493
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1331947934
Short name T226
Test name
Test status
Simulation time 90536240331 ps
CPU time 29.98 seconds
Started May 21 02:10:34 PM PDT 24
Finished May 21 02:11:06 PM PDT 24
Peak memory 195212 kb
Host smart-377ded7a-d55a-47d8-84a9-edb25057fd01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331947934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1331947934
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2115986779
Short name T172
Test name
Test status
Simulation time 380837920 ps
CPU time 0.84 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:10:32 PM PDT 24
Peak memory 183516 kb
Host smart-bc84d905-ead7-4327-9835-98ef65d56b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115986779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2115986779
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.4151435480
Short name T246
Test name
Test status
Simulation time 12677439076 ps
CPU time 20.65 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:10:51 PM PDT 24
Peak memory 183588 kb
Host smart-39ea1600-8ef1-44e2-a384-5bac57c82d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151435480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.4151435480
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.158312860
Short name T225
Test name
Test status
Simulation time 604570651 ps
CPU time 0.69 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:10:32 PM PDT 24
Peak memory 183492 kb
Host smart-5e93f164-bf6f-4f4b-8050-801d2a50b45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158312860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.158312860
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.4055421001
Short name T41
Test name
Test status
Simulation time 146227862146 ps
CPU time 103.65 seconds
Started May 21 02:10:32 PM PDT 24
Finished May 21 02:12:18 PM PDT 24
Peak memory 183540 kb
Host smart-b7e9dbd9-611b-487b-8e60-81c156712854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055421001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.4055421001
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3796549869
Short name T277
Test name
Test status
Simulation time 566457134 ps
CPU time 1.53 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:10:33 PM PDT 24
Peak memory 183480 kb
Host smart-d2a2ebbd-a25d-44f0-a154-cde8fdb98bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796549869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3796549869
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3471453990
Short name T135
Test name
Test status
Simulation time 11329018488 ps
CPU time 9.62 seconds
Started May 21 02:10:27 PM PDT 24
Finished May 21 02:10:40 PM PDT 24
Peak memory 183556 kb
Host smart-2ead0708-d692-426e-9af9-1ac94e11d53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471453990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3471453990
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2047265445
Short name T223
Test name
Test status
Simulation time 480515799 ps
CPU time 0.69 seconds
Started May 21 02:10:34 PM PDT 24
Finished May 21 02:10:37 PM PDT 24
Peak memory 183496 kb
Host smart-be4dd9d3-c771-444b-aa2d-e40f6315eb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047265445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2047265445
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2093823046
Short name T138
Test name
Test status
Simulation time 115743314521 ps
CPU time 94.48 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:12:06 PM PDT 24
Peak memory 195360 kb
Host smart-a8b7fd82-cf4c-44e9-920f-847804ef4949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093823046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2093823046
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1038661899
Short name T160
Test name
Test status
Simulation time 175250497197 ps
CPU time 664.5 seconds
Started May 21 02:10:32 PM PDT 24
Finished May 21 02:21:38 PM PDT 24
Peak memory 200084 kb
Host smart-c188e005-5361-4d4a-94db-90b7bc269045
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038661899 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1038661899
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.447185815
Short name T54
Test name
Test status
Simulation time 469634426 ps
CPU time 0.99 seconds
Started May 21 02:10:29 PM PDT 24
Finished May 21 02:10:33 PM PDT 24
Peak memory 183548 kb
Host smart-ae96e620-2614-4198-b3cf-9f1d7e48bce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447185815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.447185815
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1324024322
Short name T221
Test name
Test status
Simulation time 15795617705 ps
CPU time 25.5 seconds
Started May 21 02:10:31 PM PDT 24
Finished May 21 02:10:59 PM PDT 24
Peak memory 183600 kb
Host smart-e59a1474-6df9-43a5-adf3-15ba89bb7d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324024322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1324024322
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3276993654
Short name T169
Test name
Test status
Simulation time 456380678 ps
CPU time 1.13 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:10:33 PM PDT 24
Peak memory 183436 kb
Host smart-4d8f5559-380f-47dc-88b1-98d0933d9ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276993654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3276993654
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.296082550
Short name T189
Test name
Test status
Simulation time 229002040463 ps
CPU time 385.72 seconds
Started May 21 02:10:32 PM PDT 24
Finished May 21 02:16:59 PM PDT 24
Peak memory 194008 kb
Host smart-c64e9c51-a432-4efe-a563-b1bb5bcc535d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296082550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.296082550
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.424943112
Short name T275
Test name
Test status
Simulation time 41276104141 ps
CPU time 205.41 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:13:57 PM PDT 24
Peak memory 214356 kb
Host smart-06bfe966-3660-46c6-b744-4290a038d4cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424943112 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.424943112
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2229260617
Short name T251
Test name
Test status
Simulation time 375907121 ps
CPU time 1.09 seconds
Started May 21 02:10:36 PM PDT 24
Finished May 21 02:10:38 PM PDT 24
Peak memory 183472 kb
Host smart-9115660f-9886-40be-a098-f78d486415e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229260617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2229260617
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1405591399
Short name T155
Test name
Test status
Simulation time 17177704150 ps
CPU time 6.88 seconds
Started May 21 02:10:37 PM PDT 24
Finished May 21 02:10:44 PM PDT 24
Peak memory 191696 kb
Host smart-7ef849cf-1677-4b34-83a1-d9153a5c53bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405591399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1405591399
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.4132030492
Short name T146
Test name
Test status
Simulation time 378611350 ps
CPU time 1.16 seconds
Started May 21 02:10:40 PM PDT 24
Finished May 21 02:10:42 PM PDT 24
Peak memory 183508 kb
Host smart-f82b980e-1874-49ac-98df-722f93f79ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132030492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.4132030492
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.909693510
Short name T143
Test name
Test status
Simulation time 123974063857 ps
CPU time 9.47 seconds
Started May 21 02:10:34 PM PDT 24
Finished May 21 02:10:45 PM PDT 24
Peak memory 195120 kb
Host smart-4ce43771-36b5-4375-92dc-20b291660ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909693510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.909693510
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3947808381
Short name T14
Test name
Test status
Simulation time 142214390690 ps
CPU time 632.17 seconds
Started May 21 02:10:38 PM PDT 24
Finished May 21 02:21:11 PM PDT 24
Peak memory 199280 kb
Host smart-c4c300f3-f5b9-4113-a749-3360e268d7d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947808381 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3947808381
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2817920729
Short name T211
Test name
Test status
Simulation time 375412316 ps
CPU time 0.67 seconds
Started May 21 02:10:35 PM PDT 24
Finished May 21 02:10:37 PM PDT 24
Peak memory 183500 kb
Host smart-e04e5d94-4f1e-4cf2-a178-dd080b74903c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817920729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2817920729
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3646677718
Short name T173
Test name
Test status
Simulation time 56259392110 ps
CPU time 11.27 seconds
Started May 21 02:10:35 PM PDT 24
Finished May 21 02:10:48 PM PDT 24
Peak memory 191744 kb
Host smart-78bd5216-fd79-4b61-aa98-60728e75fc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646677718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3646677718
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3111702471
Short name T209
Test name
Test status
Simulation time 474496713 ps
CPU time 0.7 seconds
Started May 21 02:10:37 PM PDT 24
Finished May 21 02:10:38 PM PDT 24
Peak memory 183500 kb
Host smart-ec67670a-6778-4c8c-9c15-7038e4e7e9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111702471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3111702471
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.657227776
Short name T231
Test name
Test status
Simulation time 126923745184 ps
CPU time 15.56 seconds
Started May 21 02:10:35 PM PDT 24
Finished May 21 02:10:52 PM PDT 24
Peak memory 194308 kb
Host smart-7543428b-5a92-4a43-a85e-3c2461e2ea01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657227776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.657227776
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1236822569
Short name T153
Test name
Test status
Simulation time 26187232479 ps
CPU time 8.96 seconds
Started May 21 02:10:40 PM PDT 24
Finished May 21 02:10:51 PM PDT 24
Peak memory 183348 kb
Host smart-18ec29e3-0117-4ffc-806d-7d040601d738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236822569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1236822569
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.243628290
Short name T192
Test name
Test status
Simulation time 377084623 ps
CPU time 1.11 seconds
Started May 21 02:10:40 PM PDT 24
Finished May 21 02:10:44 PM PDT 24
Peak memory 183240 kb
Host smart-f8c8fb2d-37da-42b0-acbe-85eb293b1211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243628290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.243628290
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1246630545
Short name T179
Test name
Test status
Simulation time 176199057290 ps
CPU time 19.93 seconds
Started May 21 02:10:33 PM PDT 24
Finished May 21 02:10:54 PM PDT 24
Peak memory 183556 kb
Host smart-355a61b4-43ba-446b-973e-0cf3686cc78e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246630545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1246630545
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2475564979
Short name T235
Test name
Test status
Simulation time 101594617386 ps
CPU time 261.99 seconds
Started May 21 02:10:33 PM PDT 24
Finished May 21 02:14:56 PM PDT 24
Peak memory 198468 kb
Host smart-bf245e13-fd8d-4e34-82e2-bd143702911a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475564979 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2475564979
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2598061786
Short name T97
Test name
Test status
Simulation time 520865329 ps
CPU time 0.68 seconds
Started May 21 02:10:33 PM PDT 24
Finished May 21 02:10:36 PM PDT 24
Peak memory 183500 kb
Host smart-ee89c051-f46d-4513-8944-61e426d3bf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598061786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2598061786
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.116983310
Short name T136
Test name
Test status
Simulation time 59547098739 ps
CPU time 44.28 seconds
Started May 21 02:10:37 PM PDT 24
Finished May 21 02:11:23 PM PDT 24
Peak memory 183608 kb
Host smart-9a526629-e585-41f3-b8be-a07880f6f0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116983310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.116983310
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1103520167
Short name T121
Test name
Test status
Simulation time 428865032 ps
CPU time 0.84 seconds
Started May 21 02:10:35 PM PDT 24
Finished May 21 02:10:37 PM PDT 24
Peak memory 183528 kb
Host smart-d47d54bf-1800-477d-a029-1f578927c2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103520167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1103520167
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2693285302
Short name T240
Test name
Test status
Simulation time 267961483555 ps
CPU time 118.84 seconds
Started May 21 02:10:36 PM PDT 24
Finished May 21 02:12:36 PM PDT 24
Peak memory 183616 kb
Host smart-d3322029-3851-4143-987f-453e6ebcfa10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693285302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2693285302
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3722517721
Short name T203
Test name
Test status
Simulation time 225519870992 ps
CPU time 290.24 seconds
Started May 21 02:10:34 PM PDT 24
Finished May 21 02:15:26 PM PDT 24
Peak memory 214832 kb
Host smart-e47a74dc-b744-4851-900e-26e8185f4edf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722517721 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3722517721
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.301198358
Short name T243
Test name
Test status
Simulation time 474228477 ps
CPU time 0.71 seconds
Started May 21 02:10:39 PM PDT 24
Finished May 21 02:10:42 PM PDT 24
Peak memory 183504 kb
Host smart-84c43a1d-f7f7-40a4-8378-4dcefb0a8c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301198358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.301198358
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1065908622
Short name T123
Test name
Test status
Simulation time 16017029566 ps
CPU time 24.25 seconds
Started May 21 02:10:38 PM PDT 24
Finished May 21 02:11:03 PM PDT 24
Peak memory 183544 kb
Host smart-42963b0a-6949-45c1-9852-f43939e309f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065908622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1065908622
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3944911680
Short name T198
Test name
Test status
Simulation time 408544322 ps
CPU time 0.67 seconds
Started May 21 02:10:34 PM PDT 24
Finished May 21 02:10:37 PM PDT 24
Peak memory 183496 kb
Host smart-d5476c28-e008-4ea1-a2da-e8ee2a4ff16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944911680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3944911680
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1872872795
Short name T229
Test name
Test status
Simulation time 62197797247 ps
CPU time 94.92 seconds
Started May 21 02:10:38 PM PDT 24
Finished May 21 02:12:14 PM PDT 24
Peak memory 183592 kb
Host smart-498383a6-2f3e-46ef-b90c-d5ef73728315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872872795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1872872795
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.326060924
Short name T281
Test name
Test status
Simulation time 591886961 ps
CPU time 0.75 seconds
Started May 21 02:10:18 PM PDT 24
Finished May 21 02:10:22 PM PDT 24
Peak memory 183508 kb
Host smart-43c8d4d1-e9ac-457b-af80-d7896227d17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326060924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.326060924
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1248779157
Short name T210
Test name
Test status
Simulation time 29144360843 ps
CPU time 3.95 seconds
Started May 21 02:10:20 PM PDT 24
Finished May 21 02:10:27 PM PDT 24
Peak memory 183568 kb
Host smart-29148ad9-65d2-4a9a-b9e9-46263f4a8ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248779157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1248779157
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.699835563
Short name T17
Test name
Test status
Simulation time 7415817745 ps
CPU time 12.3 seconds
Started May 21 02:10:23 PM PDT 24
Finished May 21 02:10:39 PM PDT 24
Peak memory 215132 kb
Host smart-c305bded-c09f-4d2b-a221-f2e78da185ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699835563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.699835563
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3463167750
Short name T214
Test name
Test status
Simulation time 491291256 ps
CPU time 0.62 seconds
Started May 21 02:10:18 PM PDT 24
Finished May 21 02:10:22 PM PDT 24
Peak memory 183504 kb
Host smart-e0f5499f-3fa3-4379-bbfa-f926c2d2bc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463167750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3463167750
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.963944497
Short name T204
Test name
Test status
Simulation time 172891756437 ps
CPU time 372.67 seconds
Started May 21 02:10:21 PM PDT 24
Finished May 21 02:16:38 PM PDT 24
Peak memory 197968 kb
Host smart-ee023739-b066-48ce-b06b-8ff59e34ea7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963944497 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.963944497
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3312415184
Short name T182
Test name
Test status
Simulation time 478059036 ps
CPU time 0.7 seconds
Started May 21 02:10:41 PM PDT 24
Finished May 21 02:10:44 PM PDT 24
Peak memory 183504 kb
Host smart-3c847bfe-fd16-4f1e-97b3-648ea4e5ba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312415184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3312415184
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3927630681
Short name T266
Test name
Test status
Simulation time 41021534392 ps
CPU time 70.54 seconds
Started May 21 02:10:41 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 183584 kb
Host smart-17b71fe8-2283-43f8-9238-ded8a0cb4eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927630681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3927630681
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2111614477
Short name T168
Test name
Test status
Simulation time 489245320 ps
CPU time 1.22 seconds
Started May 21 02:10:37 PM PDT 24
Finished May 21 02:10:39 PM PDT 24
Peak memory 183436 kb
Host smart-351e977f-a093-44ca-b948-687e9615e101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111614477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2111614477
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1632985541
Short name T200
Test name
Test status
Simulation time 16624174507 ps
CPU time 27.08 seconds
Started May 21 02:10:41 PM PDT 24
Finished May 21 02:11:10 PM PDT 24
Peak memory 183580 kb
Host smart-8e8f9b3a-d34b-4715-b323-7801cdf61665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632985541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1632985541
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.748415245
Short name T88
Test name
Test status
Simulation time 563393509656 ps
CPU time 1296.88 seconds
Started May 21 02:10:40 PM PDT 24
Finished May 21 02:32:19 PM PDT 24
Peak memory 208880 kb
Host smart-cb8cd42d-f03f-4d05-bf2b-ab12709bf43e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748415245 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.748415245
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2188530622
Short name T270
Test name
Test status
Simulation time 361708814 ps
CPU time 1.03 seconds
Started May 21 02:10:48 PM PDT 24
Finished May 21 02:10:51 PM PDT 24
Peak memory 183464 kb
Host smart-7ae09a33-0d35-4ab8-a3d6-981fee674fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188530622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2188530622
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2199420737
Short name T134
Test name
Test status
Simulation time 39070395952 ps
CPU time 14.29 seconds
Started May 21 02:11:25 PM PDT 24
Finished May 21 02:11:40 PM PDT 24
Peak memory 191808 kb
Host smart-ea473c2e-7d2f-446b-b5ae-b87b5f280130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199420737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2199420737
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2886165441
Short name T218
Test name
Test status
Simulation time 640844578 ps
CPU time 0.62 seconds
Started May 21 02:10:38 PM PDT 24
Finished May 21 02:10:39 PM PDT 24
Peak memory 183500 kb
Host smart-080481d1-7189-40a2-a4e8-e280935078ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886165441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2886165441
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3079910802
Short name T259
Test name
Test status
Simulation time 216998916252 ps
CPU time 33.62 seconds
Started May 21 02:10:39 PM PDT 24
Finished May 21 02:11:14 PM PDT 24
Peak memory 193176 kb
Host smart-1ddaac62-892c-4297-a9a3-1fe2ade9a944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079910802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3079910802
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1433386664
Short name T236
Test name
Test status
Simulation time 491559395 ps
CPU time 1.28 seconds
Started May 21 02:10:43 PM PDT 24
Finished May 21 02:10:45 PM PDT 24
Peak memory 183396 kb
Host smart-005d5f1c-3ff0-4a2f-b8c3-ef50e8d4b4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433386664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1433386664
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1363705290
Short name T83
Test name
Test status
Simulation time 21899357078 ps
CPU time 16.51 seconds
Started May 21 02:10:38 PM PDT 24
Finished May 21 02:10:56 PM PDT 24
Peak memory 191800 kb
Host smart-c15de2c3-ce47-423c-83e8-ee65e70152e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363705290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1363705290
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3418558243
Short name T128
Test name
Test status
Simulation time 342311012 ps
CPU time 1.12 seconds
Started May 21 02:10:41 PM PDT 24
Finished May 21 02:10:44 PM PDT 24
Peak memory 183520 kb
Host smart-3ec3864a-39be-4fc4-b92f-ea508faed9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418558243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3418558243
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.368583232
Short name T264
Test name
Test status
Simulation time 27761492367 ps
CPU time 46.26 seconds
Started May 21 02:10:40 PM PDT 24
Finished May 21 02:11:28 PM PDT 24
Peak memory 191752 kb
Host smart-0f63f679-78fb-45a4-9c9a-28db447186a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368583232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.368583232
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2517301037
Short name T220
Test name
Test status
Simulation time 375856906 ps
CPU time 0.87 seconds
Started May 21 02:10:38 PM PDT 24
Finished May 21 02:10:40 PM PDT 24
Peak memory 183504 kb
Host smart-bb1b5b51-1514-4208-a7b0-52ef5009b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517301037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2517301037
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3642906972
Short name T8
Test name
Test status
Simulation time 24064561472 ps
CPU time 3.67 seconds
Started May 21 02:10:43 PM PDT 24
Finished May 21 02:10:48 PM PDT 24
Peak memory 183484 kb
Host smart-cc9b1bb7-0cd9-4c04-8765-915564bc24e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642906972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3642906972
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2476016043
Short name T206
Test name
Test status
Simulation time 601179384 ps
CPU time 0.78 seconds
Started May 21 02:10:48 PM PDT 24
Finished May 21 02:10:51 PM PDT 24
Peak memory 183468 kb
Host smart-9cc9bf56-8219-46c7-899d-3e5a6366b3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476016043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2476016043
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3949719682
Short name T201
Test name
Test status
Simulation time 116578937734 ps
CPU time 86.91 seconds
Started May 21 02:10:38 PM PDT 24
Finished May 21 02:12:06 PM PDT 24
Peak memory 183552 kb
Host smart-77414398-a1e0-435e-ba4d-73243703a103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949719682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3949719682
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3460091872
Short name T165
Test name
Test status
Simulation time 308611888666 ps
CPU time 622.71 seconds
Started May 21 02:10:41 PM PDT 24
Finished May 21 02:21:06 PM PDT 24
Peak memory 207876 kb
Host smart-922484d0-ea66-4340-80d5-bd7cd85ea572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460091872 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3460091872
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.364988972
Short name T46
Test name
Test status
Simulation time 575385060 ps
CPU time 1.47 seconds
Started May 21 02:10:39 PM PDT 24
Finished May 21 02:10:42 PM PDT 24
Peak memory 183476 kb
Host smart-4876b73d-1276-4389-8cd4-2ed17735dd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364988972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.364988972
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2523099582
Short name T82
Test name
Test status
Simulation time 39740380724 ps
CPU time 33.82 seconds
Started May 21 02:10:38 PM PDT 24
Finished May 21 02:11:13 PM PDT 24
Peak memory 191756 kb
Host smart-32d08dd1-5154-4260-9484-1983fd4afda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523099582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2523099582
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2893755972
Short name T47
Test name
Test status
Simulation time 412143803 ps
CPU time 1.21 seconds
Started May 21 02:10:43 PM PDT 24
Finished May 21 02:10:45 PM PDT 24
Peak memory 183424 kb
Host smart-b9b0b6dc-8052-4815-aaa3-e7757b5830b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893755972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2893755972
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3019504270
Short name T1
Test name
Test status
Simulation time 46927411920 ps
CPU time 58.62 seconds
Started May 21 02:10:38 PM PDT 24
Finished May 21 02:11:38 PM PDT 24
Peak memory 183564 kb
Host smart-390422c7-0471-4633-a92b-09bdf04ea3e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019504270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3019504270
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3401222441
Short name T35
Test name
Test status
Simulation time 410944170329 ps
CPU time 763.55 seconds
Started May 21 02:10:40 PM PDT 24
Finished May 21 02:23:25 PM PDT 24
Peak memory 202200 kb
Host smart-b056e8ac-792c-428e-a7f4-db72fcaa439d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401222441 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3401222441
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.4289059998
Short name T256
Test name
Test status
Simulation time 573042783 ps
CPU time 1.39 seconds
Started May 21 02:10:43 PM PDT 24
Finished May 21 02:10:45 PM PDT 24
Peak memory 183400 kb
Host smart-1b8adb2e-f75a-4403-92f0-2f6950e8f040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289059998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.4289059998
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1898271321
Short name T268
Test name
Test status
Simulation time 7807021664 ps
CPU time 7.03 seconds
Started May 21 02:10:48 PM PDT 24
Finished May 21 02:10:57 PM PDT 24
Peak memory 191732 kb
Host smart-3f90da48-52b0-4fe7-a898-500bd0ecb9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898271321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1898271321
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3490956441
Short name T48
Test name
Test status
Simulation time 606744729 ps
CPU time 0.96 seconds
Started May 21 02:10:43 PM PDT 24
Finished May 21 02:10:45 PM PDT 24
Peak memory 183540 kb
Host smart-8ce1dda1-6292-4933-8e4f-0ee937fbb486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490956441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3490956441
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3672630575
Short name T171
Test name
Test status
Simulation time 147199958904 ps
CPU time 57.89 seconds
Started May 21 02:10:47 PM PDT 24
Finished May 21 02:11:47 PM PDT 24
Peak memory 194372 kb
Host smart-37d65fa1-ffed-42a0-812d-f3c2b46981b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672630575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3672630575
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.939971742
Short name T124
Test name
Test status
Simulation time 553827180 ps
CPU time 0.77 seconds
Started May 21 02:10:46 PM PDT 24
Finished May 21 02:10:49 PM PDT 24
Peak memory 183536 kb
Host smart-7824cd4c-3252-45cc-81b4-49678bc93165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939971742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.939971742
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1362015416
Short name T175
Test name
Test status
Simulation time 59055451778 ps
CPU time 8.96 seconds
Started May 21 02:10:49 PM PDT 24
Finished May 21 02:11:00 PM PDT 24
Peak memory 183496 kb
Host smart-690956c4-8e5a-48f3-8fb7-2d4b2c284c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362015416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1362015416
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.840916721
Short name T249
Test name
Test status
Simulation time 455770058 ps
CPU time 0.59 seconds
Started May 21 02:10:46 PM PDT 24
Finished May 21 02:10:48 PM PDT 24
Peak memory 183468 kb
Host smart-73986ff6-392c-40f4-8057-baa993c2d749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840916721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.840916721
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1542917158
Short name T195
Test name
Test status
Simulation time 103876333654 ps
CPU time 87.71 seconds
Started May 21 02:10:48 PM PDT 24
Finished May 21 02:12:18 PM PDT 24
Peak memory 195412 kb
Host smart-a69f564e-dc52-4a80-b541-ab4f6ff866c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542917158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1542917158
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1049587485
Short name T94
Test name
Test status
Simulation time 37677119738 ps
CPU time 304.36 seconds
Started May 21 02:10:47 PM PDT 24
Finished May 21 02:15:54 PM PDT 24
Peak memory 198472 kb
Host smart-1fc01956-fde5-4256-bc55-4999be0f70a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049587485 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1049587485
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3316851173
Short name T274
Test name
Test status
Simulation time 429262658 ps
CPU time 1.2 seconds
Started May 21 02:10:47 PM PDT 24
Finished May 21 02:10:50 PM PDT 24
Peak memory 183508 kb
Host smart-2bea7fed-b409-444c-956e-717de0c366bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316851173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3316851173
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2001591848
Short name T267
Test name
Test status
Simulation time 55011483312 ps
CPU time 87.26 seconds
Started May 21 02:10:46 PM PDT 24
Finished May 21 02:12:14 PM PDT 24
Peak memory 191696 kb
Host smart-a18dfba0-ffec-4bb1-b346-55a5433b0a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001591848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2001591848
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2924902976
Short name T276
Test name
Test status
Simulation time 434664426 ps
CPU time 0.63 seconds
Started May 21 02:10:46 PM PDT 24
Finished May 21 02:10:49 PM PDT 24
Peak memory 183512 kb
Host smart-f1effb1f-cb6f-40a6-b58d-493d2b9102a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924902976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2924902976
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2106134204
Short name T202
Test name
Test status
Simulation time 185345253102 ps
CPU time 302.32 seconds
Started May 21 02:10:47 PM PDT 24
Finished May 21 02:15:51 PM PDT 24
Peak memory 194300 kb
Host smart-64805fe7-0916-4f88-8888-05f65427f944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106134204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2106134204
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2204542937
Short name T157
Test name
Test status
Simulation time 22236390339 ps
CPU time 226.43 seconds
Started May 21 02:10:45 PM PDT 24
Finished May 21 02:14:33 PM PDT 24
Peak memory 198436 kb
Host smart-12ce2638-3006-42ff-afa5-7241242b418b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204542937 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2204542937
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2413727207
Short name T2
Test name
Test status
Simulation time 528294733 ps
CPU time 0.77 seconds
Started May 21 02:10:49 PM PDT 24
Finished May 21 02:10:51 PM PDT 24
Peak memory 183432 kb
Host smart-7e449af4-ba1e-4d63-94b9-9926939e0e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413727207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2413727207
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1518024078
Short name T125
Test name
Test status
Simulation time 26264978631 ps
CPU time 10.23 seconds
Started May 21 02:10:46 PM PDT 24
Finished May 21 02:10:59 PM PDT 24
Peak memory 183592 kb
Host smart-2ae9d28d-08a3-41da-97cb-d47708728f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518024078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1518024078
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.147160547
Short name T188
Test name
Test status
Simulation time 493625249 ps
CPU time 1.33 seconds
Started May 21 02:10:47 PM PDT 24
Finished May 21 02:10:51 PM PDT 24
Peak memory 183484 kb
Host smart-075d114a-b85b-4fd5-8b39-8660608e5f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147160547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.147160547
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1612648271
Short name T194
Test name
Test status
Simulation time 46379170815 ps
CPU time 77.48 seconds
Started May 21 02:10:46 PM PDT 24
Finished May 21 02:12:05 PM PDT 24
Peak memory 183480 kb
Host smart-9d2704c6-ed5b-47da-a5df-60d082060ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612648271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1612648271
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1698390001
Short name T253
Test name
Test status
Simulation time 68306104966 ps
CPU time 85.01 seconds
Started May 21 02:10:47 PM PDT 24
Finished May 21 02:12:15 PM PDT 24
Peak memory 198472 kb
Host smart-3e200d9f-2c1f-4874-b6dc-7cca75c34dcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698390001 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1698390001
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3359722564
Short name T207
Test name
Test status
Simulation time 430065184 ps
CPU time 1.24 seconds
Started May 21 02:10:46 PM PDT 24
Finished May 21 02:10:50 PM PDT 24
Peak memory 183472 kb
Host smart-d3569531-8084-4c63-8fe6-5aee18f1a4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359722564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3359722564
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.717235609
Short name T52
Test name
Test status
Simulation time 17517020333 ps
CPU time 7.99 seconds
Started May 21 02:10:46 PM PDT 24
Finished May 21 02:10:56 PM PDT 24
Peak memory 183592 kb
Host smart-3aad7764-dfd0-41e6-acaa-798caa29462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717235609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.717235609
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.39734185
Short name T114
Test name
Test status
Simulation time 590761882 ps
CPU time 0.77 seconds
Started May 21 02:10:45 PM PDT 24
Finished May 21 02:10:47 PM PDT 24
Peak memory 183528 kb
Host smart-1e2c9f68-5bbc-426e-9564-599477f69df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39734185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.39734185
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3837644215
Short name T131
Test name
Test status
Simulation time 321657522874 ps
CPU time 434.68 seconds
Started May 21 02:10:46 PM PDT 24
Finished May 21 02:18:03 PM PDT 24
Peak memory 183612 kb
Host smart-1a5cdb2b-c28c-4125-9e14-14fd024b4467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837644215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3837644215
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2726571245
Short name T215
Test name
Test status
Simulation time 425343065 ps
CPU time 1.12 seconds
Started May 21 02:10:24 PM PDT 24
Finished May 21 02:10:29 PM PDT 24
Peak memory 183488 kb
Host smart-960456b4-5b72-4c10-bb16-2bb1f3adab2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726571245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2726571245
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2035391367
Short name T77
Test name
Test status
Simulation time 32994621970 ps
CPU time 52.4 seconds
Started May 21 02:10:22 PM PDT 24
Finished May 21 02:11:18 PM PDT 24
Peak memory 183548 kb
Host smart-52702d94-28dc-458d-ae4c-d82250391a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035391367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2035391367
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.812681283
Short name T19
Test name
Test status
Simulation time 4371039468 ps
CPU time 2.43 seconds
Started May 21 02:10:23 PM PDT 24
Finished May 21 02:10:29 PM PDT 24
Peak memory 215116 kb
Host smart-2a25b7cb-1954-450b-a1ec-cbaab3bcefd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812681283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.812681283
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.334892218
Short name T222
Test name
Test status
Simulation time 362795656 ps
CPU time 1.09 seconds
Started May 21 02:10:23 PM PDT 24
Finished May 21 02:10:28 PM PDT 24
Peak memory 183480 kb
Host smart-abc16d52-128b-487e-a1e3-ec454d21ff0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334892218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.334892218
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2391445199
Short name T49
Test name
Test status
Simulation time 146734678046 ps
CPU time 239.94 seconds
Started May 21 02:10:22 PM PDT 24
Finished May 21 02:14:26 PM PDT 24
Peak memory 194324 kb
Host smart-bca5acec-d622-48b4-983c-b43720086f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391445199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2391445199
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3062747357
Short name T56
Test name
Test status
Simulation time 14700350956 ps
CPU time 68.26 seconds
Started May 21 02:10:25 PM PDT 24
Finished May 21 02:11:36 PM PDT 24
Peak memory 198408 kb
Host smart-6ed9c8c2-4f5f-4de2-955d-d0f66ceac07b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062747357 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3062747357
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.652941112
Short name T7
Test name
Test status
Simulation time 438640502 ps
CPU time 0.72 seconds
Started May 21 02:10:48 PM PDT 24
Finished May 21 02:10:51 PM PDT 24
Peak memory 183464 kb
Host smart-917a6dcd-c844-443c-8a7f-5134b121ed16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652941112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.652941112
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3679414634
Short name T252
Test name
Test status
Simulation time 19605767586 ps
CPU time 15.35 seconds
Started May 21 02:10:52 PM PDT 24
Finished May 21 02:11:08 PM PDT 24
Peak memory 183556 kb
Host smart-bbbe03da-ee71-4673-88f5-41b83bf24ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679414634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3679414634
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2777824260
Short name T161
Test name
Test status
Simulation time 514853485 ps
CPU time 0.71 seconds
Started May 21 02:10:46 PM PDT 24
Finished May 21 02:10:49 PM PDT 24
Peak memory 183508 kb
Host smart-6207a64f-592c-4f8a-a4dc-0faf42b22e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777824260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2777824260
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1267632468
Short name T50
Test name
Test status
Simulation time 122607745888 ps
CPU time 48.68 seconds
Started May 21 02:10:47 PM PDT 24
Finished May 21 02:11:38 PM PDT 24
Peak memory 195324 kb
Host smart-b11d518d-c085-4bc3-9a70-aace00ab0642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267632468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1267632468
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2943183966
Short name T37
Test name
Test status
Simulation time 64688237472 ps
CPU time 134.47 seconds
Started May 21 02:10:47 PM PDT 24
Finished May 21 02:13:04 PM PDT 24
Peak memory 198484 kb
Host smart-c21700d1-2483-4e82-8e37-4fbaf757b405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943183966 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2943183966
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.890721990
Short name T187
Test name
Test status
Simulation time 482851321 ps
CPU time 1.28 seconds
Started May 21 02:10:47 PM PDT 24
Finished May 21 02:10:50 PM PDT 24
Peak memory 183544 kb
Host smart-e5b551c0-69dc-4f33-94b3-5acd9f81bf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890721990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.890721990
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.676087422
Short name T26
Test name
Test status
Simulation time 28847937241 ps
CPU time 6.78 seconds
Started May 21 02:10:48 PM PDT 24
Finished May 21 02:10:57 PM PDT 24
Peak memory 191776 kb
Host smart-bc655b99-0623-435d-b819-b36160bfe5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676087422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.676087422
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1185257961
Short name T152
Test name
Test status
Simulation time 505924192 ps
CPU time 0.72 seconds
Started May 21 02:10:47 PM PDT 24
Finished May 21 02:10:50 PM PDT 24
Peak memory 183516 kb
Host smart-de5decd5-44ca-4a13-b352-76e2ccdf894c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185257961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1185257961
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1919585789
Short name T178
Test name
Test status
Simulation time 27133024109 ps
CPU time 10.94 seconds
Started May 21 02:10:52 PM PDT 24
Finished May 21 02:11:04 PM PDT 24
Peak memory 183568 kb
Host smart-dcfc1b73-06a7-44fb-aff2-b44c94ed06ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919585789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1919585789
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3359044726
Short name T258
Test name
Test status
Simulation time 26873143468 ps
CPU time 194.02 seconds
Started May 21 02:10:46 PM PDT 24
Finished May 21 02:14:02 PM PDT 24
Peak memory 198492 kb
Host smart-67a04dff-4340-4df2-a572-0fd56beb12ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359044726 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3359044726
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.4047484177
Short name T269
Test name
Test status
Simulation time 415316219 ps
CPU time 1.15 seconds
Started May 21 02:10:49 PM PDT 24
Finished May 21 02:10:52 PM PDT 24
Peak memory 183548 kb
Host smart-cf0517fa-fc5e-4d4a-ad5b-2d29a4f8783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047484177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.4047484177
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1614727687
Short name T137
Test name
Test status
Simulation time 22744153853 ps
CPU time 22.04 seconds
Started May 21 02:10:50 PM PDT 24
Finished May 21 02:11:13 PM PDT 24
Peak memory 183556 kb
Host smart-8251d081-ff70-4613-91ba-877bbfc13f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614727687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1614727687
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3978298491
Short name T10
Test name
Test status
Simulation time 420057567 ps
CPU time 0.68 seconds
Started May 21 02:10:51 PM PDT 24
Finished May 21 02:10:53 PM PDT 24
Peak memory 183540 kb
Host smart-982e7051-cb73-415b-920a-e89f184eb3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978298491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3978298491
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3326570717
Short name T191
Test name
Test status
Simulation time 353988926879 ps
CPU time 476.75 seconds
Started May 21 02:10:52 PM PDT 24
Finished May 21 02:18:50 PM PDT 24
Peak memory 183568 kb
Host smart-05fd62c2-a4d3-4e9b-9383-954452f53110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326570717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3326570717
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.261292089
Short name T205
Test name
Test status
Simulation time 162303682905 ps
CPU time 465.15 seconds
Started May 21 02:10:51 PM PDT 24
Finished May 21 02:18:37 PM PDT 24
Peak memory 198468 kb
Host smart-457136c4-6b4e-40f4-a98b-1b5155003432
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261292089 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.261292089
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.4198275121
Short name T119
Test name
Test status
Simulation time 406150465 ps
CPU time 1.25 seconds
Started May 21 02:10:51 PM PDT 24
Finished May 21 02:10:53 PM PDT 24
Peak memory 183540 kb
Host smart-6801d94d-dcde-4f43-811e-265e0a1ab638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198275121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4198275121
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.177118648
Short name T144
Test name
Test status
Simulation time 46242320237 ps
CPU time 18.72 seconds
Started May 21 02:10:51 PM PDT 24
Finished May 21 02:11:11 PM PDT 24
Peak memory 183580 kb
Host smart-e34050f9-79a1-4418-a0be-3819554eac72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177118648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.177118648
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3711358158
Short name T129
Test name
Test status
Simulation time 572305880 ps
CPU time 1.39 seconds
Started May 21 02:10:55 PM PDT 24
Finished May 21 02:10:57 PM PDT 24
Peak memory 183400 kb
Host smart-333b5228-7f37-4956-8333-f2e83dfe3513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711358158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3711358158
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.819928474
Short name T278
Test name
Test status
Simulation time 231485130091 ps
CPU time 99.59 seconds
Started May 21 02:10:51 PM PDT 24
Finished May 21 02:12:32 PM PDT 24
Peak memory 183592 kb
Host smart-ebbdc24e-d5f4-442a-9089-2caeaab77ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819928474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.819928474
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2974669796
Short name T93
Test name
Test status
Simulation time 40491034721 ps
CPU time 296.52 seconds
Started May 21 02:10:52 PM PDT 24
Finished May 21 02:15:50 PM PDT 24
Peak memory 198464 kb
Host smart-166f80ce-42bc-46be-b583-2c384e2d56cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974669796 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2974669796
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1769556983
Short name T245
Test name
Test status
Simulation time 589924995 ps
CPU time 0.78 seconds
Started May 21 02:10:56 PM PDT 24
Finished May 21 02:10:58 PM PDT 24
Peak memory 183528 kb
Host smart-17c833ef-efca-440e-a684-8fe322371d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769556983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1769556983
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2505251568
Short name T147
Test name
Test status
Simulation time 37665658166 ps
CPU time 13.29 seconds
Started May 21 02:10:55 PM PDT 24
Finished May 21 02:11:10 PM PDT 24
Peak memory 191740 kb
Host smart-8c7a1670-345f-4b15-8d64-6b70da9f55f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505251568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2505251568
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.66893975
Short name T273
Test name
Test status
Simulation time 551477255 ps
CPU time 0.71 seconds
Started May 21 02:10:55 PM PDT 24
Finished May 21 02:10:57 PM PDT 24
Peak memory 183552 kb
Host smart-b1261502-9d60-422e-9ae7-49889e3b9fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66893975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.66893975
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.4154135536
Short name T13
Test name
Test status
Simulation time 190210747268 ps
CPU time 263.69 seconds
Started May 21 02:10:57 PM PDT 24
Finished May 21 02:15:21 PM PDT 24
Peak memory 183576 kb
Host smart-e0cc9ea3-da38-4963-9f4e-8746cb0170fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154135536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.4154135536
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3771064548
Short name T84
Test name
Test status
Simulation time 95731296232 ps
CPU time 488.66 seconds
Started May 21 02:10:55 PM PDT 24
Finished May 21 02:19:04 PM PDT 24
Peak memory 198460 kb
Host smart-2b0c219c-327a-4b64-8f73-a58716471ed2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771064548 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3771064548
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3677713641
Short name T154
Test name
Test status
Simulation time 511870005 ps
CPU time 0.74 seconds
Started May 21 02:11:01 PM PDT 24
Finished May 21 02:11:03 PM PDT 24
Peak memory 183536 kb
Host smart-dead3a4e-232e-40d8-b2d9-b02d47f4153b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677713641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3677713641
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1197677904
Short name T140
Test name
Test status
Simulation time 41169389011 ps
CPU time 60.01 seconds
Started May 21 02:10:58 PM PDT 24
Finished May 21 02:11:59 PM PDT 24
Peak memory 183584 kb
Host smart-652a76b9-49e8-4838-8dd9-2cca3caab081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197677904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1197677904
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1455502761
Short name T163
Test name
Test status
Simulation time 439884077 ps
CPU time 0.86 seconds
Started May 21 02:10:58 PM PDT 24
Finished May 21 02:11:00 PM PDT 24
Peak memory 183524 kb
Host smart-f0919cbc-1e6c-4337-a829-b8ba0214506c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455502761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1455502761
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2834073585
Short name T20
Test name
Test status
Simulation time 156220889451 ps
CPU time 234.83 seconds
Started May 21 02:10:59 PM PDT 24
Finished May 21 02:14:55 PM PDT 24
Peak memory 183724 kb
Host smart-952b457b-6cc4-424f-927d-5e706b72d259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834073585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2834073585
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.493286290
Short name T279
Test name
Test status
Simulation time 114272572520 ps
CPU time 206.1 seconds
Started May 21 02:11:00 PM PDT 24
Finished May 21 02:14:27 PM PDT 24
Peak memory 198492 kb
Host smart-d954a68b-5485-4b8b-a249-51f10f5c5a50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493286290 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.493286290
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1868182355
Short name T34
Test name
Test status
Simulation time 579312875 ps
CPU time 0.99 seconds
Started May 21 02:10:56 PM PDT 24
Finished May 21 02:10:58 PM PDT 24
Peak memory 183544 kb
Host smart-5a1cb9f0-13f0-4f55-988f-c1e27d74f604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868182355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1868182355
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1715157833
Short name T186
Test name
Test status
Simulation time 40783142751 ps
CPU time 15.4 seconds
Started May 21 02:10:56 PM PDT 24
Finished May 21 02:11:13 PM PDT 24
Peak memory 183484 kb
Host smart-0f60ddbf-6307-4292-b86e-32d7f0d3137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715157833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1715157833
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2501510231
Short name T116
Test name
Test status
Simulation time 520701916 ps
CPU time 1.38 seconds
Started May 21 02:10:58 PM PDT 24
Finished May 21 02:11:00 PM PDT 24
Peak memory 183524 kb
Host smart-12ba3452-fd46-4983-82dd-13fa643e5398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501510231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2501510231
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.526475785
Short name T90
Test name
Test status
Simulation time 79516734095 ps
CPU time 315.67 seconds
Started May 21 02:11:01 PM PDT 24
Finished May 21 02:16:18 PM PDT 24
Peak memory 198460 kb
Host smart-b56d8c0f-53c5-4ad2-85a0-afa70062a266
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526475785 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.526475785
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2356758778
Short name T177
Test name
Test status
Simulation time 490039791 ps
CPU time 0.72 seconds
Started May 21 02:11:07 PM PDT 24
Finished May 21 02:11:11 PM PDT 24
Peak memory 183508 kb
Host smart-33c00059-2e45-4ce1-a1d2-43d434cf7972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356758778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2356758778
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1142163477
Short name T261
Test name
Test status
Simulation time 1833177313 ps
CPU time 3.17 seconds
Started May 21 02:11:04 PM PDT 24
Finished May 21 02:11:09 PM PDT 24
Peak memory 183492 kb
Host smart-dcad4438-c82c-4ea3-9e43-8d2216e3a85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142163477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1142163477
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2972973814
Short name T174
Test name
Test status
Simulation time 566131805 ps
CPU time 0.78 seconds
Started May 21 02:11:01 PM PDT 24
Finished May 21 02:11:03 PM PDT 24
Peak memory 183520 kb
Host smart-2fdd9793-baca-4478-9f2d-60ee6977c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972973814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2972973814
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.380326537
Short name T164
Test name
Test status
Simulation time 312789738953 ps
CPU time 128.88 seconds
Started May 21 02:11:05 PM PDT 24
Finished May 21 02:13:16 PM PDT 24
Peak memory 194468 kb
Host smart-4b2edad8-673c-4f62-93eb-0483e3da5b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380326537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.380326537
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2613535360
Short name T24
Test name
Test status
Simulation time 174177968109 ps
CPU time 386.31 seconds
Started May 21 02:11:04 PM PDT 24
Finished May 21 02:17:33 PM PDT 24
Peak memory 198500 kb
Host smart-246e7e97-783d-4d50-ab73-66cfbb1d35ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613535360 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2613535360
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3130766106
Short name T133
Test name
Test status
Simulation time 498544662 ps
CPU time 0.71 seconds
Started May 21 02:11:04 PM PDT 24
Finished May 21 02:11:07 PM PDT 24
Peak memory 183500 kb
Host smart-b34baa3d-934e-4368-8ea2-b7484994606a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130766106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3130766106
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3307810146
Short name T4
Test name
Test status
Simulation time 40150852378 ps
CPU time 29.47 seconds
Started May 21 02:11:08 PM PDT 24
Finished May 21 02:11:41 PM PDT 24
Peak memory 191744 kb
Host smart-8f307735-ee48-427b-b82b-b6ddc0f99770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307810146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3307810146
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2266367639
Short name T117
Test name
Test status
Simulation time 598900821 ps
CPU time 1.37 seconds
Started May 21 02:11:04 PM PDT 24
Finished May 21 02:11:08 PM PDT 24
Peak memory 183500 kb
Host smart-1a0e0da7-9cf1-4525-99ab-09b8d4bd420e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266367639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2266367639
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1576225813
Short name T234
Test name
Test status
Simulation time 84385063320 ps
CPU time 33.39 seconds
Started May 21 02:11:04 PM PDT 24
Finished May 21 02:11:40 PM PDT 24
Peak memory 194496 kb
Host smart-6181db3a-dc09-4659-854a-50d1b1d0aca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576225813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1576225813
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1862701323
Short name T96
Test name
Test status
Simulation time 45059809714 ps
CPU time 351.06 seconds
Started May 21 02:11:04 PM PDT 24
Finished May 21 02:16:58 PM PDT 24
Peak memory 198484 kb
Host smart-7b714176-bd87-486e-a584-ff8a5fd1d129
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862701323 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1862701323
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2307443936
Short name T79
Test name
Test status
Simulation time 433510489 ps
CPU time 0.68 seconds
Started May 21 02:11:03 PM PDT 24
Finished May 21 02:11:04 PM PDT 24
Peak memory 183480 kb
Host smart-8b8a48eb-a0b8-42ee-9656-c5fc40c0b87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307443936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2307443936
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1936798184
Short name T102
Test name
Test status
Simulation time 32228954027 ps
CPU time 13.77 seconds
Started May 21 02:11:04 PM PDT 24
Finished May 21 02:11:19 PM PDT 24
Peak memory 191804 kb
Host smart-5dec4bab-2a88-4ebf-a9c5-c4ca4658f2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936798184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1936798184
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2540804253
Short name T230
Test name
Test status
Simulation time 394140479 ps
CPU time 1.17 seconds
Started May 21 02:11:03 PM PDT 24
Finished May 21 02:11:05 PM PDT 24
Peak memory 183552 kb
Host smart-c0d7c697-19c1-4f0f-a54b-3bd12793c971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540804253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2540804253
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.115562564
Short name T25
Test name
Test status
Simulation time 274093354167 ps
CPU time 111.88 seconds
Started May 21 02:11:06 PM PDT 24
Finished May 21 02:13:00 PM PDT 24
Peak memory 183576 kb
Host smart-889085f0-47af-4aac-b45c-ed9cfbaff342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115562564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.115562564
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.80566195
Short name T95
Test name
Test status
Simulation time 61993965595 ps
CPU time 505.18 seconds
Started May 21 02:11:04 PM PDT 24
Finished May 21 02:19:30 PM PDT 24
Peak memory 198396 kb
Host smart-a1ee5a96-a157-4210-97e8-e4d59bfbf573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80566195 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.80566195
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1495479379
Short name T99
Test name
Test status
Simulation time 497784841 ps
CPU time 0.92 seconds
Started May 21 02:10:22 PM PDT 24
Finished May 21 02:10:27 PM PDT 24
Peak memory 183392 kb
Host smart-254ac0b5-1cf0-4273-b91e-ec3c18844418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495479379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1495479379
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.574911939
Short name T151
Test name
Test status
Simulation time 54359168947 ps
CPU time 48.21 seconds
Started May 21 02:10:22 PM PDT 24
Finished May 21 02:11:14 PM PDT 24
Peak memory 191760 kb
Host smart-bb7217cb-c2af-467a-8c5d-83ffa44703af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574911939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.574911939
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2768599907
Short name T18
Test name
Test status
Simulation time 4960583789 ps
CPU time 1.4 seconds
Started May 21 02:10:24 PM PDT 24
Finished May 21 02:10:29 PM PDT 24
Peak memory 215112 kb
Host smart-0f551382-1f51-4195-8149-0ffe62399b2a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768599907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2768599907
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1487714991
Short name T237
Test name
Test status
Simulation time 530849668 ps
CPU time 1.34 seconds
Started May 21 02:10:22 PM PDT 24
Finished May 21 02:10:27 PM PDT 24
Peak memory 183744 kb
Host smart-b8a13e14-0c30-4c64-8347-5f52b878d7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487714991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1487714991
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1458353000
Short name T12
Test name
Test status
Simulation time 30605450038 ps
CPU time 250.05 seconds
Started May 21 02:10:23 PM PDT 24
Finished May 21 02:14:37 PM PDT 24
Peak memory 198476 kb
Host smart-cc3e22dd-823e-4880-95a5-bd8f514a9040
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458353000 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1458353000
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2396304422
Short name T228
Test name
Test status
Simulation time 432390014 ps
CPU time 1.35 seconds
Started May 21 02:11:04 PM PDT 24
Finished May 21 02:11:08 PM PDT 24
Peak memory 183484 kb
Host smart-6413d967-f415-49f5-bbf6-a7031dd843c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396304422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2396304422
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.6902011
Short name T219
Test name
Test status
Simulation time 21632207072 ps
CPU time 7.85 seconds
Started May 21 02:11:05 PM PDT 24
Finished May 21 02:11:15 PM PDT 24
Peak memory 183580 kb
Host smart-49d3604e-6794-4988-bf00-7c9c1a6dc01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6902011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.6902011
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2397660398
Short name T150
Test name
Test status
Simulation time 473733741 ps
CPU time 0.7 seconds
Started May 21 02:11:05 PM PDT 24
Finished May 21 02:11:08 PM PDT 24
Peak memory 183548 kb
Host smart-f8dd75b3-9014-4813-90bc-f832ee8a6a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397660398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2397660398
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1027641522
Short name T183
Test name
Test status
Simulation time 735367589760 ps
CPU time 911.42 seconds
Started May 21 02:11:07 PM PDT 24
Finished May 21 02:26:21 PM PDT 24
Peak memory 194536 kb
Host smart-71f7961b-da29-4f94-a54a-c4938e39f7b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027641522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1027641522
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3056970498
Short name T87
Test name
Test status
Simulation time 70265648855 ps
CPU time 482.71 seconds
Started May 21 02:11:04 PM PDT 24
Finished May 21 02:19:09 PM PDT 24
Peak memory 198528 kb
Host smart-ce0448dd-98c4-4e67-aae9-e49d1e6a5a7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056970498 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3056970498
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3452630301
Short name T184
Test name
Test status
Simulation time 462544706 ps
CPU time 0.72 seconds
Started May 21 02:11:04 PM PDT 24
Finished May 21 02:11:07 PM PDT 24
Peak memory 183500 kb
Host smart-28490eb5-6798-48e6-91cd-913c64c90eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452630301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3452630301
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2741190640
Short name T170
Test name
Test status
Simulation time 40778353027 ps
CPU time 15.99 seconds
Started May 21 02:11:05 PM PDT 24
Finished May 21 02:11:24 PM PDT 24
Peak memory 183568 kb
Host smart-d72f4d46-764f-40f8-84e1-f444fc3b5373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741190640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2741190640
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1611728763
Short name T197
Test name
Test status
Simulation time 340742986 ps
CPU time 0.68 seconds
Started May 21 02:11:06 PM PDT 24
Finished May 21 02:11:09 PM PDT 24
Peak memory 183484 kb
Host smart-d877ffb9-ad6a-4188-8ded-b4ed1666cc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611728763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1611728763
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3134273850
Short name T142
Test name
Test status
Simulation time 271243620558 ps
CPU time 455.83 seconds
Started May 21 02:11:05 PM PDT 24
Finished May 21 02:18:43 PM PDT 24
Peak memory 193276 kb
Host smart-a7939fda-b2e1-49e0-b4e5-f05d21a5dea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134273850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3134273850
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3164693329
Short name T92
Test name
Test status
Simulation time 2866554474 ps
CPU time 17.66 seconds
Started May 21 02:11:03 PM PDT 24
Finished May 21 02:11:21 PM PDT 24
Peak memory 198444 kb
Host smart-0e0d8b4f-05d7-42df-bb9c-895e9c99de14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164693329 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3164693329
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2772143959
Short name T158
Test name
Test status
Simulation time 502380456 ps
CPU time 1.09 seconds
Started May 21 02:11:11 PM PDT 24
Finished May 21 02:11:15 PM PDT 24
Peak memory 183500 kb
Host smart-09c94a6a-3332-4872-8cc8-80092d969c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772143959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2772143959
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2214752681
Short name T282
Test name
Test status
Simulation time 40420885729 ps
CPU time 34.63 seconds
Started May 21 02:11:04 PM PDT 24
Finished May 21 02:11:41 PM PDT 24
Peak memory 191660 kb
Host smart-60d8d9c0-b204-47f4-ba50-72b3e9c058fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214752681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2214752681
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1231389101
Short name T255
Test name
Test status
Simulation time 531679777 ps
CPU time 0.7 seconds
Started May 21 02:11:07 PM PDT 24
Finished May 21 02:11:10 PM PDT 24
Peak memory 183496 kb
Host smart-ad741aeb-cb8f-416e-bb66-8c2c7f890cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231389101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1231389101
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.32393176
Short name T180
Test name
Test status
Simulation time 74199690517 ps
CPU time 62.63 seconds
Started May 21 02:11:07 PM PDT 24
Finished May 21 02:12:13 PM PDT 24
Peak memory 183584 kb
Host smart-2474ee19-2231-4c89-bef0-2d44d58e8210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32393176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_al
l.32393176
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2565401990
Short name T86
Test name
Test status
Simulation time 168346095591 ps
CPU time 312.48 seconds
Started May 21 02:11:10 PM PDT 24
Finished May 21 02:16:26 PM PDT 24
Peak memory 198444 kb
Host smart-d8282386-4e4b-41bc-be0a-0cab41393cf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565401990 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2565401990
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.323565577
Short name T115
Test name
Test status
Simulation time 512231028 ps
CPU time 1.37 seconds
Started May 21 02:11:10 PM PDT 24
Finished May 21 02:11:15 PM PDT 24
Peak memory 183516 kb
Host smart-dcf82ea8-646b-4f22-b22a-cec4a65e7d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323565577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.323565577
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1958877783
Short name T208
Test name
Test status
Simulation time 58729574311 ps
CPU time 40 seconds
Started May 21 02:11:10 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 183568 kb
Host smart-52d6172b-0441-4f95-b34c-f64b0d405ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958877783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1958877783
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3451761477
Short name T217
Test name
Test status
Simulation time 458271462 ps
CPU time 0.69 seconds
Started May 21 02:11:08 PM PDT 24
Finished May 21 02:11:12 PM PDT 24
Peak memory 183492 kb
Host smart-2057586c-45f2-4dbb-965e-2eec26da3e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451761477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3451761477
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1109740560
Short name T162
Test name
Test status
Simulation time 305175364628 ps
CPU time 476.33 seconds
Started May 21 02:11:08 PM PDT 24
Finished May 21 02:19:08 PM PDT 24
Peak memory 183560 kb
Host smart-bd2ab699-9ec4-472a-bac4-54d2c7471d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109740560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1109740560
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1402170529
Short name T260
Test name
Test status
Simulation time 140790295684 ps
CPU time 473.57 seconds
Started May 21 02:11:08 PM PDT 24
Finished May 21 02:19:05 PM PDT 24
Peak memory 198452 kb
Host smart-79e2e931-343a-4796-a2fd-5d4918938e09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402170529 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1402170529
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3836405229
Short name T241
Test name
Test status
Simulation time 685599700 ps
CPU time 0.63 seconds
Started May 21 02:11:09 PM PDT 24
Finished May 21 02:11:14 PM PDT 24
Peak memory 183540 kb
Host smart-70cedaaa-de78-4e28-a786-3edce2f694bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836405229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3836405229
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1589496958
Short name T227
Test name
Test status
Simulation time 10345535263 ps
CPU time 3.7 seconds
Started May 21 02:11:12 PM PDT 24
Finished May 21 02:11:19 PM PDT 24
Peak memory 183580 kb
Host smart-f9abbf70-1db7-4202-8383-d7ae267dc64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589496958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1589496958
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1860964402
Short name T132
Test name
Test status
Simulation time 581691012 ps
CPU time 0.81 seconds
Started May 21 02:11:11 PM PDT 24
Finished May 21 02:11:15 PM PDT 24
Peak memory 183404 kb
Host smart-b5210970-315f-4ec4-a644-1655c4a9a222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860964402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1860964402
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1305989259
Short name T257
Test name
Test status
Simulation time 424923503 ps
CPU time 0.7 seconds
Started May 21 02:11:09 PM PDT 24
Finished May 21 02:11:14 PM PDT 24
Peak memory 183392 kb
Host smart-0529adc2-8f2f-447c-b24d-57a168646ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305989259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1305989259
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2116188209
Short name T118
Test name
Test status
Simulation time 37917317339 ps
CPU time 60.32 seconds
Started May 21 02:11:08 PM PDT 24
Finished May 21 02:12:12 PM PDT 24
Peak memory 191788 kb
Host smart-cb0062a7-98df-406d-a67a-7f0671299b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116188209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2116188209
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.575183378
Short name T271
Test name
Test status
Simulation time 352849390 ps
CPU time 0.86 seconds
Started May 21 02:11:08 PM PDT 24
Finished May 21 02:11:13 PM PDT 24
Peak memory 183492 kb
Host smart-588610c5-7e98-450c-9b68-6c92503e5235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575183378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.575183378
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1501678860
Short name T21
Test name
Test status
Simulation time 32932906405 ps
CPU time 4.08 seconds
Started May 21 02:11:09 PM PDT 24
Finished May 21 02:11:17 PM PDT 24
Peak memory 183600 kb
Host smart-329ea47f-0da7-4102-b496-1b27046f2038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501678860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1501678860
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3550389843
Short name T85
Test name
Test status
Simulation time 84152717200 ps
CPU time 848.5 seconds
Started May 21 02:11:09 PM PDT 24
Finished May 21 02:25:21 PM PDT 24
Peak memory 202592 kb
Host smart-18fe1b2e-5ec0-4044-82c3-1b823943fdb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550389843 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3550389843
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1182086314
Short name T22
Test name
Test status
Simulation time 541670018 ps
CPU time 0.75 seconds
Started May 21 02:11:09 PM PDT 24
Finished May 21 02:11:14 PM PDT 24
Peak memory 183488 kb
Host smart-89d50838-e263-4fca-995c-cfad532a76c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182086314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1182086314
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1040383453
Short name T127
Test name
Test status
Simulation time 18226597671 ps
CPU time 29.62 seconds
Started May 21 02:11:10 PM PDT 24
Finished May 21 02:11:43 PM PDT 24
Peak memory 191756 kb
Host smart-ad28e1df-9d71-4d0b-b98b-f927a1864aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040383453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1040383453
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.907522103
Short name T196
Test name
Test status
Simulation time 571009636 ps
CPU time 0.74 seconds
Started May 21 02:11:07 PM PDT 24
Finished May 21 02:11:12 PM PDT 24
Peak memory 183508 kb
Host smart-06b3f2b4-1e9f-472d-9bfc-d27e63f408dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907522103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.907522103
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1536301877
Short name T139
Test name
Test status
Simulation time 232031260047 ps
CPU time 354.27 seconds
Started May 21 02:11:12 PM PDT 24
Finished May 21 02:17:09 PM PDT 24
Peak memory 194396 kb
Host smart-ae1c67d8-3f38-41e7-8ee6-e48714d0df73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536301877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1536301877
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.267115053
Short name T38
Test name
Test status
Simulation time 78210864519 ps
CPU time 159.81 seconds
Started May 21 02:11:11 PM PDT 24
Finished May 21 02:13:54 PM PDT 24
Peak memory 198368 kb
Host smart-ccbd5bea-4bc6-43d2-bd61-28eee4cd99a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267115053 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.267115053
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2986214410
Short name T43
Test name
Test status
Simulation time 530782594 ps
CPU time 1.36 seconds
Started May 21 02:11:10 PM PDT 24
Finished May 21 02:11:15 PM PDT 24
Peak memory 183500 kb
Host smart-74bf3d85-3ab3-4031-834e-122d77ddc142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986214410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2986214410
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1146319396
Short name T233
Test name
Test status
Simulation time 42237533727 ps
CPU time 17.79 seconds
Started May 21 02:11:12 PM PDT 24
Finished May 21 02:11:33 PM PDT 24
Peak memory 191784 kb
Host smart-56ef5586-73bd-44a5-884b-39bf84ba0cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146319396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1146319396
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.762596688
Short name T185
Test name
Test status
Simulation time 637059457 ps
CPU time 0.71 seconds
Started May 21 02:11:10 PM PDT 24
Finished May 21 02:11:14 PM PDT 24
Peak memory 183480 kb
Host smart-a228c0ad-94ee-41ae-8415-b7b5f71f8d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762596688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.762596688
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.711893677
Short name T120
Test name
Test status
Simulation time 133372577477 ps
CPU time 211.25 seconds
Started May 21 02:11:10 PM PDT 24
Finished May 21 02:14:45 PM PDT 24
Peak memory 183576 kb
Host smart-5928281e-6864-48e5-a191-3a4df710befb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711893677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.711893677
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1379100847
Short name T55
Test name
Test status
Simulation time 70567663612 ps
CPU time 381.28 seconds
Started May 21 02:11:09 PM PDT 24
Finished May 21 02:17:34 PM PDT 24
Peak memory 198472 kb
Host smart-658c3566-0efc-4526-beed-cff7d17f8fd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379100847 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1379100847
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3394837827
Short name T280
Test name
Test status
Simulation time 391512739 ps
CPU time 0.74 seconds
Started May 21 02:11:20 PM PDT 24
Finished May 21 02:11:23 PM PDT 24
Peak memory 183432 kb
Host smart-502bead9-e1ed-4648-8fa2-1f702c51d9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394837827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3394837827
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1099542206
Short name T23
Test name
Test status
Simulation time 9664509078 ps
CPU time 9.24 seconds
Started May 21 02:11:11 PM PDT 24
Finished May 21 02:11:24 PM PDT 24
Peak memory 191664 kb
Host smart-14a33f77-b817-4be4-89b3-c345897edd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099542206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1099542206
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2270427650
Short name T100
Test name
Test status
Simulation time 371506356 ps
CPU time 1.04 seconds
Started May 21 02:11:07 PM PDT 24
Finished May 21 02:11:11 PM PDT 24
Peak memory 183544 kb
Host smart-8ab1a8d2-69d5-483a-94eb-b3f5565754aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270427650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2270427650
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2295622074
Short name T42
Test name
Test status
Simulation time 246246886331 ps
CPU time 198.93 seconds
Started May 21 02:11:14 PM PDT 24
Finished May 21 02:14:36 PM PDT 24
Peak memory 194084 kb
Host smart-1f223674-356a-4a59-9dce-a619adb4d07d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295622074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2295622074
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.181049854
Short name T89
Test name
Test status
Simulation time 218121802439 ps
CPU time 299.01 seconds
Started May 21 02:11:14 PM PDT 24
Finished May 21 02:16:16 PM PDT 24
Peak memory 198492 kb
Host smart-d734de65-82f2-48da-b9de-6cb4d7354788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181049854 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.181049854
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2179288378
Short name T212
Test name
Test status
Simulation time 578830028 ps
CPU time 0.76 seconds
Started May 21 02:11:17 PM PDT 24
Finished May 21 02:11:19 PM PDT 24
Peak memory 183492 kb
Host smart-6f094f38-ba11-432a-bf4c-ee22bd71da8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179288378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2179288378
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1369605597
Short name T239
Test name
Test status
Simulation time 33705502781 ps
CPU time 14.06 seconds
Started May 21 02:11:14 PM PDT 24
Finished May 21 02:11:31 PM PDT 24
Peak memory 191772 kb
Host smart-7baf485f-62bc-4ce2-9e27-29bba7d48e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369605597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1369605597
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3227826008
Short name T3
Test name
Test status
Simulation time 438104652 ps
CPU time 0.58 seconds
Started May 21 02:11:14 PM PDT 24
Finished May 21 02:11:18 PM PDT 24
Peak memory 183508 kb
Host smart-e67f9928-b294-454b-91d0-5e199f2b6a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227826008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3227826008
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2026204949
Short name T53
Test name
Test status
Simulation time 39528706440 ps
CPU time 18.13 seconds
Started May 21 02:11:15 PM PDT 24
Finished May 21 02:11:35 PM PDT 24
Peak memory 193720 kb
Host smart-a8086fde-6814-4a18-aa53-4daa0c168780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026204949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2026204949
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3670643033
Short name T254
Test name
Test status
Simulation time 87495773352 ps
CPU time 420.41 seconds
Started May 21 02:11:20 PM PDT 24
Finished May 21 02:18:22 PM PDT 24
Peak memory 198376 kb
Host smart-d11536a0-6ba3-4de0-bad7-f8ed349b0893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670643033 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3670643033
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2317659064
Short name T44
Test name
Test status
Simulation time 571567638 ps
CPU time 1.31 seconds
Started May 21 02:10:24 PM PDT 24
Finished May 21 02:10:29 PM PDT 24
Peak memory 183556 kb
Host smart-e16c0540-4c8e-4738-ac4a-49183dc41bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317659064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2317659064
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.871141087
Short name T213
Test name
Test status
Simulation time 38595235574 ps
CPU time 15.36 seconds
Started May 21 02:10:21 PM PDT 24
Finished May 21 02:10:41 PM PDT 24
Peak memory 191824 kb
Host smart-3e167e8a-726f-4d65-8b16-4fa297c729a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871141087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.871141087
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3243187909
Short name T232
Test name
Test status
Simulation time 482682572 ps
CPU time 1.29 seconds
Started May 21 02:10:25 PM PDT 24
Finished May 21 02:10:29 PM PDT 24
Peak memory 183512 kb
Host smart-23025347-d72b-46f5-a5b0-01366e8e165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243187909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3243187909
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.128279527
Short name T244
Test name
Test status
Simulation time 244349142212 ps
CPU time 370.55 seconds
Started May 21 02:10:23 PM PDT 24
Finished May 21 02:16:38 PM PDT 24
Peak memory 193912 kb
Host smart-3e1fb3a6-fb0e-456d-8d47-937120e1b057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128279527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.128279527
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2509935811
Short name T238
Test name
Test status
Simulation time 47538288030 ps
CPU time 174.99 seconds
Started May 21 02:10:22 PM PDT 24
Finished May 21 02:13:21 PM PDT 24
Peak memory 198428 kb
Host smart-f1fb5441-557d-41c7-ba37-47e2a2fbce27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509935811 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2509935811
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3982881314
Short name T263
Test name
Test status
Simulation time 419063769 ps
CPU time 1.25 seconds
Started May 21 02:10:21 PM PDT 24
Finished May 21 02:10:26 PM PDT 24
Peak memory 183508 kb
Host smart-1606246a-17f1-4e43-9205-8fb7a079a627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982881314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3982881314
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.4062145095
Short name T81
Test name
Test status
Simulation time 3672553765 ps
CPU time 3.64 seconds
Started May 21 02:10:22 PM PDT 24
Finished May 21 02:10:30 PM PDT 24
Peak memory 183452 kb
Host smart-956a1433-126c-4d61-9fb0-62fd65a5f3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062145095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4062145095
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3576703077
Short name T156
Test name
Test status
Simulation time 525564467 ps
CPU time 0.72 seconds
Started May 21 02:10:23 PM PDT 24
Finished May 21 02:10:27 PM PDT 24
Peak memory 183480 kb
Host smart-b05c938c-a653-4b53-81c2-6262e8680dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576703077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3576703077
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1756917014
Short name T149
Test name
Test status
Simulation time 35599607219 ps
CPU time 59.99 seconds
Started May 21 02:10:23 PM PDT 24
Finished May 21 02:11:27 PM PDT 24
Peak memory 183608 kb
Host smart-75e51246-e5b8-4e3a-9777-44ab811c66eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756917014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1756917014
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3307670450
Short name T176
Test name
Test status
Simulation time 374546331 ps
CPU time 1.14 seconds
Started May 21 02:10:21 PM PDT 24
Finished May 21 02:10:26 PM PDT 24
Peak memory 183480 kb
Host smart-203659fd-2ec2-4681-a326-e330c88845af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307670450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3307670450
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2939514469
Short name T272
Test name
Test status
Simulation time 45367492448 ps
CPU time 5.44 seconds
Started May 21 02:10:23 PM PDT 24
Finished May 21 02:10:32 PM PDT 24
Peak memory 183584 kb
Host smart-03c943e5-1e32-4253-856d-a5aad0684294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939514469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2939514469
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3260120867
Short name T5
Test name
Test status
Simulation time 437647806 ps
CPU time 1.14 seconds
Started May 21 02:10:21 PM PDT 24
Finished May 21 02:10:26 PM PDT 24
Peak memory 183508 kb
Host smart-97f0c973-6a4f-4ccc-b1fd-c9b3789683f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260120867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3260120867
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.326881889
Short name T103
Test name
Test status
Simulation time 220037598244 ps
CPU time 92.39 seconds
Started May 21 02:10:23 PM PDT 24
Finished May 21 02:11:59 PM PDT 24
Peak memory 183488 kb
Host smart-a1b89d43-28ae-4eb2-9db5-574b937240c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326881889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.326881889
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2803983633
Short name T39
Test name
Test status
Simulation time 38837138120 ps
CPU time 390.29 seconds
Started May 21 02:10:22 PM PDT 24
Finished May 21 02:16:56 PM PDT 24
Peak memory 198400 kb
Host smart-7489c25e-6d99-49b3-a971-991ac460cb01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803983633 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2803983633
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3165500496
Short name T159
Test name
Test status
Simulation time 397455218 ps
CPU time 1.17 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:10:32 PM PDT 24
Peak memory 183496 kb
Host smart-c01651a0-032d-4d4b-88dc-aef23137db03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165500496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3165500496
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1816296831
Short name T80
Test name
Test status
Simulation time 34605261358 ps
CPU time 4.22 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:10:36 PM PDT 24
Peak memory 191748 kb
Host smart-3905a821-ea04-4fc1-8d5e-073b323f4a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816296831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1816296831
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.4092633292
Short name T193
Test name
Test status
Simulation time 552981367 ps
CPU time 1.42 seconds
Started May 21 02:10:22 PM PDT 24
Finished May 21 02:10:28 PM PDT 24
Peak memory 183492 kb
Host smart-f821db8f-4534-452e-89fc-cc24b314d334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092633292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4092633292
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2265920898
Short name T167
Test name
Test status
Simulation time 191424314886 ps
CPU time 23.44 seconds
Started May 21 02:10:28 PM PDT 24
Finished May 21 02:10:54 PM PDT 24
Peak memory 195000 kb
Host smart-21333201-2df3-4716-b046-4017d99bf761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265920898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2265920898
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3047583228
Short name T247
Test name
Test status
Simulation time 451409723 ps
CPU time 0.75 seconds
Started May 21 02:10:29 PM PDT 24
Finished May 21 02:10:33 PM PDT 24
Peak memory 183532 kb
Host smart-1bf53184-7f37-4ad1-8659-2a41fbcd3e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047583228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3047583228
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2063524244
Short name T145
Test name
Test status
Simulation time 13686500351 ps
CPU time 20.98 seconds
Started May 21 02:10:27 PM PDT 24
Finished May 21 02:10:51 PM PDT 24
Peak memory 191752 kb
Host smart-a3803002-5af2-403f-8feb-dd38778101ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063524244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2063524244
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.4120882180
Short name T265
Test name
Test status
Simulation time 594318370 ps
CPU time 0.77 seconds
Started May 21 02:10:34 PM PDT 24
Finished May 21 02:10:37 PM PDT 24
Peak memory 183488 kb
Host smart-c45b2cf2-3bf8-4ddf-8efd-18092865121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120882180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.4120882180
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3766414343
Short name T101
Test name
Test status
Simulation time 11292562881 ps
CPU time 9.23 seconds
Started May 21 02:10:29 PM PDT 24
Finished May 21 02:10:42 PM PDT 24
Peak memory 194904 kb
Host smart-ff874b82-b9d1-42ce-8f8b-f39cb4e64fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766414343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3766414343
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2435562507
Short name T91
Test name
Test status
Simulation time 56994223489 ps
CPU time 343.16 seconds
Started May 21 02:10:31 PM PDT 24
Finished May 21 02:16:17 PM PDT 24
Peak memory 198476 kb
Host smart-19c30850-7994-4626-a07e-e89db2d8b526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435562507 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2435562507
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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