Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 422
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T284 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2097741134 May 23 02:04:23 PM PDT 24 May 23 02:04:25 PM PDT 24 523474100 ps
T23 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2919300530 May 23 02:05:01 PM PDT 24 May 23 02:05:04 PM PDT 24 439626709 ps
T285 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2694332974 May 23 02:04:35 PM PDT 24 May 23 02:04:37 PM PDT 24 409024905 ps
T24 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2740017580 May 23 02:04:33 PM PDT 24 May 23 02:04:36 PM PDT 24 503226634 ps
T98 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3476239065 May 23 02:04:46 PM PDT 24 May 23 02:04:49 PM PDT 24 351023763 ps
T286 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1642271600 May 23 02:04:57 PM PDT 24 May 23 02:05:00 PM PDT 24 336296271 ps
T25 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2622461143 May 23 02:05:12 PM PDT 24 May 23 02:05:14 PM PDT 24 351061277 ps
T27 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2021086514 May 23 02:05:12 PM PDT 24 May 23 02:05:21 PM PDT 24 4655095736 ps
T287 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3994503205 May 23 02:05:10 PM PDT 24 May 23 02:05:11 PM PDT 24 347920588 ps
T288 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4034168938 May 23 02:04:32 PM PDT 24 May 23 02:04:34 PM PDT 24 487511858 ps
T289 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2560839196 May 23 02:05:22 PM PDT 24 May 23 02:05:24 PM PDT 24 474904395 ps
T28 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2889762774 May 23 02:04:46 PM PDT 24 May 23 02:04:50 PM PDT 24 4637196670 ps
T73 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.842222157 May 23 02:04:56 PM PDT 24 May 23 02:04:59 PM PDT 24 399378892 ps
T74 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.451090078 May 23 02:05:10 PM PDT 24 May 23 02:05:12 PM PDT 24 1221655325 ps
T51 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1879853732 May 23 02:04:34 PM PDT 24 May 23 02:04:47 PM PDT 24 6580065412 ps
T290 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3308718713 May 23 02:05:10 PM PDT 24 May 23 02:05:12 PM PDT 24 375240536 ps
T75 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3514459078 May 23 02:04:37 PM PDT 24 May 23 02:04:39 PM PDT 24 494329383 ps
T52 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.779965866 May 23 02:04:21 PM PDT 24 May 23 02:04:23 PM PDT 24 605841115 ps
T89 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.340525249 May 23 02:05:10 PM PDT 24 May 23 02:05:13 PM PDT 24 711169109 ps
T291 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2423461788 May 23 02:05:22 PM PDT 24 May 23 02:05:24 PM PDT 24 295961597 ps
T29 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.568458106 May 23 02:04:38 PM PDT 24 May 23 02:04:51 PM PDT 24 7969784489 ps
T292 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3814635742 May 23 02:05:09 PM PDT 24 May 23 02:05:10 PM PDT 24 354196342 ps
T76 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1846592141 May 23 02:05:00 PM PDT 24 May 23 02:05:03 PM PDT 24 2175261440 ps
T293 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2404336370 May 23 02:05:25 PM PDT 24 May 23 02:05:27 PM PDT 24 370566825 ps
T294 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2022535232 May 23 02:04:32 PM PDT 24 May 23 02:04:33 PM PDT 24 514231110 ps
T295 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1274725254 May 23 02:05:09 PM PDT 24 May 23 02:05:12 PM PDT 24 363062904 ps
T296 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.33046906 May 23 02:05:22 PM PDT 24 May 23 02:05:24 PM PDT 24 340458470 ps
T53 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3366155742 May 23 02:04:46 PM PDT 24 May 23 02:04:48 PM PDT 24 426887991 ps
T297 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2993974227 May 23 02:04:58 PM PDT 24 May 23 02:05:01 PM PDT 24 459263328 ps
T298 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.358722736 May 23 02:04:57 PM PDT 24 May 23 02:05:00 PM PDT 24 509878914 ps
T110 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2827218225 May 23 02:04:35 PM PDT 24 May 23 02:04:42 PM PDT 24 4533748771 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.654720606 May 23 02:04:22 PM PDT 24 May 23 02:04:24 PM PDT 24 521857725 ps
T299 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.523087268 May 23 02:05:09 PM PDT 24 May 23 02:05:12 PM PDT 24 474601689 ps
T300 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.628731697 May 23 02:05:01 PM PDT 24 May 23 02:05:04 PM PDT 24 723222273 ps
T301 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2851113950 May 23 02:04:58 PM PDT 24 May 23 02:05:01 PM PDT 24 525602130 ps
T302 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.233376854 May 23 02:04:33 PM PDT 24 May 23 02:04:36 PM PDT 24 507103073 ps
T303 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.706600250 May 23 02:05:22 PM PDT 24 May 23 02:05:23 PM PDT 24 379923308 ps
T77 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.548182272 May 23 02:04:35 PM PDT 24 May 23 02:04:39 PM PDT 24 1636767046 ps
T304 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1914027322 May 23 02:04:44 PM PDT 24 May 23 02:04:49 PM PDT 24 462417994 ps
T305 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.657499320 May 23 02:04:33 PM PDT 24 May 23 02:04:35 PM PDT 24 287655088 ps
T78 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2371330964 May 23 02:04:45 PM PDT 24 May 23 02:04:48 PM PDT 24 1374713681 ps
T111 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1167641952 May 23 02:04:46 PM PDT 24 May 23 02:04:58 PM PDT 24 8397850012 ps
T306 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1580941758 May 23 02:04:32 PM PDT 24 May 23 02:04:34 PM PDT 24 330382026 ps
T307 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1891821420 May 23 02:04:56 PM PDT 24 May 23 02:04:58 PM PDT 24 466911224 ps
T308 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4005717545 May 23 02:04:33 PM PDT 24 May 23 02:04:35 PM PDT 24 588005189 ps
T309 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4192810631 May 23 02:04:24 PM PDT 24 May 23 02:04:26 PM PDT 24 313784319 ps
T310 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1726584485 May 23 02:05:10 PM PDT 24 May 23 02:05:13 PM PDT 24 389928007 ps
T311 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3012995514 May 23 02:04:59 PM PDT 24 May 23 02:05:03 PM PDT 24 316754818 ps
T312 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1299912988 May 23 02:05:10 PM PDT 24 May 23 02:05:12 PM PDT 24 300855747 ps
T313 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3694733576 May 23 02:04:37 PM PDT 24 May 23 02:04:39 PM PDT 24 512590935 ps
T314 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.210278312 May 23 02:04:46 PM PDT 24 May 23 02:04:48 PM PDT 24 429946160 ps
T315 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3327583738 May 23 02:05:15 PM PDT 24 May 23 02:05:16 PM PDT 24 377738107 ps
T316 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3507234899 May 23 02:05:09 PM PDT 24 May 23 02:05:11 PM PDT 24 360922018 ps
T317 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.750283373 May 23 02:04:22 PM PDT 24 May 23 02:04:24 PM PDT 24 500105871 ps
T318 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1137962415 May 23 02:05:22 PM PDT 24 May 23 02:05:24 PM PDT 24 493091343 ps
T319 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2639188251 May 23 02:05:28 PM PDT 24 May 23 02:05:29 PM PDT 24 456412529 ps
T320 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.476329704 May 23 02:05:24 PM PDT 24 May 23 02:05:26 PM PDT 24 399653490 ps
T321 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3883568967 May 23 02:05:23 PM PDT 24 May 23 02:05:26 PM PDT 24 483058629 ps
T55 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3697196072 May 23 02:04:33 PM PDT 24 May 23 02:04:35 PM PDT 24 494683700 ps
T322 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.80952964 May 23 02:04:57 PM PDT 24 May 23 02:04:59 PM PDT 24 480089064 ps
T323 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1529244819 May 23 02:05:08 PM PDT 24 May 23 02:05:09 PM PDT 24 411646050 ps
T324 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.845933048 May 23 02:04:26 PM PDT 24 May 23 02:04:28 PM PDT 24 369836551 ps
T325 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1690939279 May 23 02:05:11 PM PDT 24 May 23 02:05:14 PM PDT 24 341938018 ps
T326 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3622667088 May 23 02:04:23 PM PDT 24 May 23 02:04:26 PM PDT 24 528522217 ps
T79 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.483988705 May 23 02:05:00 PM PDT 24 May 23 02:05:03 PM PDT 24 1834258362 ps
T327 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1810632315 May 23 02:05:09 PM PDT 24 May 23 02:05:10 PM PDT 24 620256783 ps
T328 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.309385902 May 23 02:04:22 PM PDT 24 May 23 02:04:24 PM PDT 24 509982280 ps
T329 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1973609028 May 23 02:04:33 PM PDT 24 May 23 02:04:37 PM PDT 24 4120325384 ps
T330 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1766079184 May 23 02:04:36 PM PDT 24 May 23 02:04:38 PM PDT 24 672699716 ps
T331 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1360472298 May 23 02:05:09 PM PDT 24 May 23 02:05:11 PM PDT 24 451998858 ps
T80 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2324364206 May 23 02:04:58 PM PDT 24 May 23 02:05:01 PM PDT 24 413366692 ps
T332 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2269435584 May 23 02:04:35 PM PDT 24 May 23 02:04:37 PM PDT 24 1561763437 ps
T59 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3572456544 May 23 02:05:29 PM PDT 24 May 23 02:05:31 PM PDT 24 303593862 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1355822161 May 23 02:05:10 PM PDT 24 May 23 02:05:12 PM PDT 24 455654170 ps
T334 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3877797418 May 23 02:05:23 PM PDT 24 May 23 02:05:25 PM PDT 24 395289379 ps
T335 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2567988275 May 23 02:04:58 PM PDT 24 May 23 02:05:02 PM PDT 24 596953266 ps
T336 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3605705147 May 23 02:04:21 PM PDT 24 May 23 02:04:23 PM PDT 24 842171971 ps
T337 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3825129422 May 23 02:04:35 PM PDT 24 May 23 02:04:37 PM PDT 24 431118736 ps
T58 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1905654576 May 23 02:04:22 PM PDT 24 May 23 02:04:29 PM PDT 24 6842636837 ps
T338 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4136154120 May 23 02:04:56 PM PDT 24 May 23 02:04:58 PM PDT 24 1314234380 ps
T112 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3902560729 May 23 02:05:12 PM PDT 24 May 23 02:05:20 PM PDT 24 4554600893 ps
T339 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.22910258 May 23 02:05:13 PM PDT 24 May 23 02:05:16 PM PDT 24 1205887517 ps
T340 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1639437912 May 23 02:04:34 PM PDT 24 May 23 02:04:37 PM PDT 24 361113367 ps
T341 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.765715862 May 23 02:05:10 PM PDT 24 May 23 02:05:13 PM PDT 24 351604664 ps
T342 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2555858103 May 23 02:05:24 PM PDT 24 May 23 02:05:26 PM PDT 24 510349813 ps
T343 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3505089333 May 23 02:05:12 PM PDT 24 May 23 02:05:14 PM PDT 24 280727822 ps
T344 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4017040063 May 23 02:04:37 PM PDT 24 May 23 02:04:39 PM PDT 24 1176885575 ps
T345 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1557523433 May 23 02:05:12 PM PDT 24 May 23 02:05:14 PM PDT 24 380664257 ps
T346 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.93324351 May 23 02:04:29 PM PDT 24 May 23 02:04:30 PM PDT 24 372634090 ps
T347 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3342802066 May 23 02:04:44 PM PDT 24 May 23 02:04:49 PM PDT 24 7852681210 ps
T348 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2237036124 May 23 02:05:10 PM PDT 24 May 23 02:05:16 PM PDT 24 4454610921 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2774369758 May 23 02:04:27 PM PDT 24 May 23 02:04:40 PM PDT 24 13569016331 ps
T349 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2166429012 May 23 02:05:24 PM PDT 24 May 23 02:05:26 PM PDT 24 422372788 ps
T350 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1259555317 May 23 02:04:56 PM PDT 24 May 23 02:05:09 PM PDT 24 8423788868 ps
T351 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.906392472 May 23 02:05:12 PM PDT 24 May 23 02:05:15 PM PDT 24 956355552 ps
T352 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1487874308 May 23 02:05:09 PM PDT 24 May 23 02:05:10 PM PDT 24 516472928 ps
T353 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4082598655 May 23 02:04:57 PM PDT 24 May 23 02:05:13 PM PDT 24 8376880301 ps
T354 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1029052923 May 23 02:05:11 PM PDT 24 May 23 02:05:14 PM PDT 24 2487456060 ps
T355 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.265263360 May 23 02:04:45 PM PDT 24 May 23 02:04:48 PM PDT 24 545695867 ps
T356 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.234239667 May 23 02:04:57 PM PDT 24 May 23 02:05:00 PM PDT 24 622828795 ps
T357 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2598022867 May 23 02:04:21 PM PDT 24 May 23 02:04:23 PM PDT 24 329460209 ps
T358 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.642448124 May 23 02:04:56 PM PDT 24 May 23 02:05:01 PM PDT 24 571684616 ps
T359 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.65849108 May 23 02:04:45 PM PDT 24 May 23 02:04:48 PM PDT 24 410888355 ps
T360 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.358777489 May 23 02:04:59 PM PDT 24 May 23 02:05:02 PM PDT 24 471328318 ps
T361 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2464736549 May 23 02:04:28 PM PDT 24 May 23 02:04:30 PM PDT 24 593372380 ps
T362 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1437997998 May 23 02:04:35 PM PDT 24 May 23 02:04:38 PM PDT 24 585848532 ps
T363 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1987818777 May 23 02:04:21 PM PDT 24 May 23 02:04:36 PM PDT 24 7834176283 ps
T364 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1616305502 May 23 02:04:57 PM PDT 24 May 23 02:05:00 PM PDT 24 410195799 ps
T365 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1486837616 May 23 02:04:35 PM PDT 24 May 23 02:04:38 PM PDT 24 514914565 ps
T366 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3346594418 May 23 02:04:57 PM PDT 24 May 23 02:04:59 PM PDT 24 524540379 ps
T367 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.731204359 May 23 02:04:24 PM PDT 24 May 23 02:04:27 PM PDT 24 484293567 ps
T368 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1150859216 May 23 02:04:22 PM PDT 24 May 23 02:04:25 PM PDT 24 542898949 ps
T369 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2092452553 May 23 02:04:33 PM PDT 24 May 23 02:04:35 PM PDT 24 837166133 ps
T370 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2111852646 May 23 02:04:23 PM PDT 24 May 23 02:04:29 PM PDT 24 8858558771 ps
T371 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2362468881 May 23 02:04:32 PM PDT 24 May 23 02:04:33 PM PDT 24 547596093 ps
T372 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4022093153 May 23 02:04:46 PM PDT 24 May 23 02:04:51 PM PDT 24 388960587 ps
T373 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1797750519 May 23 02:05:15 PM PDT 24 May 23 02:05:17 PM PDT 24 463162881 ps
T374 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.659986863 May 23 02:04:58 PM PDT 24 May 23 02:05:06 PM PDT 24 1819522381 ps
T375 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1923332196 May 23 02:05:11 PM PDT 24 May 23 02:05:14 PM PDT 24 324392611 ps
T376 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1860433263 May 23 02:04:26 PM PDT 24 May 23 02:04:27 PM PDT 24 397450877 ps
T377 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1957333904 May 23 02:04:59 PM PDT 24 May 23 02:05:02 PM PDT 24 501984665 ps
T378 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2516891937 May 23 02:05:22 PM PDT 24 May 23 02:05:24 PM PDT 24 298191744 ps
T379 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2397765213 May 23 02:04:21 PM PDT 24 May 23 02:04:23 PM PDT 24 403594373 ps
T380 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4294789039 May 23 02:05:12 PM PDT 24 May 23 02:05:14 PM PDT 24 633539659 ps
T381 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3617283463 May 23 02:04:58 PM PDT 24 May 23 02:05:01 PM PDT 24 449868567 ps
T61 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1628176109 May 23 02:04:22 PM PDT 24 May 23 02:04:25 PM PDT 24 443495371 ps
T382 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.188768828 May 23 02:04:46 PM PDT 24 May 23 02:04:50 PM PDT 24 1163738783 ps
T383 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2940909251 May 23 02:05:23 PM PDT 24 May 23 02:05:25 PM PDT 24 472412738 ps
T384 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2307814204 May 23 02:05:00 PM PDT 24 May 23 02:05:16 PM PDT 24 8667353138 ps
T385 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1858203251 May 23 02:05:09 PM PDT 24 May 23 02:05:12 PM PDT 24 1193425236 ps
T386 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3162257652 May 23 02:04:58 PM PDT 24 May 23 02:05:01 PM PDT 24 591340753 ps
T387 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.198367435 May 23 02:04:59 PM PDT 24 May 23 02:05:01 PM PDT 24 303210733 ps
T388 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1158334230 May 23 02:04:21 PM PDT 24 May 23 02:04:22 PM PDT 24 622422623 ps
T389 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.84852462 May 23 02:04:32 PM PDT 24 May 23 02:04:34 PM PDT 24 970433351 ps
T390 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3714269473 May 23 02:05:09 PM PDT 24 May 23 02:05:11 PM PDT 24 340514019 ps
T391 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.591426673 May 23 02:04:57 PM PDT 24 May 23 02:05:07 PM PDT 24 4435167452 ps
T392 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.390699197 May 23 02:04:58 PM PDT 24 May 23 02:05:01 PM PDT 24 1766963322 ps
T393 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4160474645 May 23 02:04:24 PM PDT 24 May 23 02:04:27 PM PDT 24 1203179873 ps
T394 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2793030026 May 23 02:04:56 PM PDT 24 May 23 02:04:59 PM PDT 24 335569315 ps
T395 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3381794343 May 23 02:05:25 PM PDT 24 May 23 02:05:27 PM PDT 24 427565855 ps
T396 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.985812224 May 23 02:04:21 PM PDT 24 May 23 02:04:26 PM PDT 24 8381362889 ps
T397 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1197604306 May 23 02:04:29 PM PDT 24 May 23 02:04:31 PM PDT 24 526685879 ps
T72 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1847554821 May 23 02:04:35 PM PDT 24 May 23 02:04:38 PM PDT 24 358892679 ps
T398 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.612343448 May 23 02:05:09 PM PDT 24 May 23 02:05:11 PM PDT 24 997322445 ps
T62 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1758510181 May 23 02:04:33 PM PDT 24 May 23 02:04:40 PM PDT 24 10551492936 ps
T399 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.4252728832 May 23 02:05:14 PM PDT 24 May 23 02:05:16 PM PDT 24 309661261 ps
T400 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2624598878 May 23 02:05:13 PM PDT 24 May 23 02:05:16 PM PDT 24 436595137 ps
T401 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4026424292 May 23 02:05:11 PM PDT 24 May 23 02:05:16 PM PDT 24 4314892736 ps
T402 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3612157407 May 23 02:05:08 PM PDT 24 May 23 02:05:09 PM PDT 24 409759420 ps
T403 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.4107268451 May 23 02:04:37 PM PDT 24 May 23 02:04:39 PM PDT 24 439982485 ps
T404 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2536405191 May 23 02:05:10 PM PDT 24 May 23 02:05:12 PM PDT 24 1118060677 ps
T405 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.489495185 May 23 02:04:26 PM PDT 24 May 23 02:04:28 PM PDT 24 917778323 ps
T113 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3824794345 May 23 02:05:11 PM PDT 24 May 23 02:05:19 PM PDT 24 4310987474 ps
T406 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2982295397 May 23 02:04:21 PM PDT 24 May 23 02:04:27 PM PDT 24 1556965697 ps
T407 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2521150800 May 23 02:04:56 PM PDT 24 May 23 02:04:58 PM PDT 24 1199714460 ps
T408 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1636553590 May 23 02:04:21 PM PDT 24 May 23 02:04:24 PM PDT 24 503898744 ps
T409 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2376091456 May 23 02:04:29 PM PDT 24 May 23 02:04:58 PM PDT 24 13875603000 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1663267988 May 23 02:04:34 PM PDT 24 May 23 02:04:36 PM PDT 24 353476730 ps
T410 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.470041506 May 23 02:05:09 PM PDT 24 May 23 02:05:11 PM PDT 24 369090231 ps
T411 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2999907284 May 23 02:05:26 PM PDT 24 May 23 02:05:28 PM PDT 24 482940289 ps
T412 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1860566681 May 23 02:05:09 PM PDT 24 May 23 02:05:12 PM PDT 24 552448904 ps
T413 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.713559543 May 23 02:04:34 PM PDT 24 May 23 02:04:36 PM PDT 24 400568770 ps
T414 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1900802830 May 23 02:05:16 PM PDT 24 May 23 02:05:24 PM PDT 24 7385157900 ps
T415 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2960307403 May 23 02:05:25 PM PDT 24 May 23 02:05:26 PM PDT 24 387128222 ps
T416 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2533892174 May 23 02:04:45 PM PDT 24 May 23 02:04:47 PM PDT 24 544414487 ps
T417 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.308432451 May 23 02:05:09 PM PDT 24 May 23 02:05:11 PM PDT 24 379493040 ps
T418 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.124034175 May 23 02:05:24 PM PDT 24 May 23 02:05:26 PM PDT 24 518258212 ps
T419 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.364669011 May 23 02:04:34 PM PDT 24 May 23 02:04:39 PM PDT 24 2682749918 ps
T57 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2276498012 May 23 02:05:09 PM PDT 24 May 23 02:05:11 PM PDT 24 410307550 ps
T420 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1486230852 May 23 02:05:09 PM PDT 24 May 23 02:05:11 PM PDT 24 490752717 ps
T421 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.4065543488 May 23 02:04:59 PM PDT 24 May 23 02:05:10 PM PDT 24 4690768561 ps
T422 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2261968007 May 23 02:04:21 PM PDT 24 May 23 02:04:23 PM PDT 24 458021756 ps

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.979979890
Short name T2
Test name
Test status
Simulation time 1401284733705 ps
CPU time 735.21 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:45:59 PM PDT 24
Peak memory 200952 kb
Host smart-f3fbaef1-44f3-4fd3-b649-8c785382cfe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979979890 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.979979890
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.821644428
Short name T35
Test name
Test status
Simulation time 61190597357 ps
CPU time 706.56 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:45:32 PM PDT 24
Peak memory 199188 kb
Host smart-134aa3a1-c0a8-4f3d-9663-f467b3e8bbfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821644428 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.821644428
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2021086514
Short name T27
Test name
Test status
Simulation time 4655095736 ps
CPU time 7.98 seconds
Started May 23 02:05:12 PM PDT 24
Finished May 23 02:05:21 PM PDT 24
Peak memory 196752 kb
Host smart-5130c98d-81cd-434b-863d-69a140bcc74d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021086514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2021086514
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2740017580
Short name T24
Test name
Test status
Simulation time 503226634 ps
CPU time 1.56 seconds
Started May 23 02:04:33 PM PDT 24
Finished May 23 02:04:36 PM PDT 24
Peak memory 183772 kb
Host smart-afcc8489-7a02-4ad3-85f3-6d276346cf30
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740017580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2740017580
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1568948008
Short name T1
Test name
Test status
Simulation time 140946892493 ps
CPU time 23.29 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:31 PM PDT 24
Peak memory 193332 kb
Host smart-187e8ca3-aad5-4c48-ba48-473ffdf20d0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568948008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1568948008
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.4094258918
Short name T17
Test name
Test status
Simulation time 4212175367 ps
CPU time 2.4 seconds
Started May 23 03:33:22 PM PDT 24
Finished May 23 03:33:27 PM PDT 24
Peak memory 214928 kb
Host smart-8b2026bb-18da-43ba-b135-0aaa5fd77a94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094258918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4094258918
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3653593498
Short name T32
Test name
Test status
Simulation time 68793793095 ps
CPU time 660.54 seconds
Started May 23 03:33:25 PM PDT 24
Finished May 23 03:44:29 PM PDT 24
Peak memory 198960 kb
Host smart-0b2bccb2-0dfe-4961-9cbe-524d99621d22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653593498 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3653593498
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3093654960
Short name T40
Test name
Test status
Simulation time 34696298557 ps
CPU time 256.1 seconds
Started May 23 03:33:42 PM PDT 24
Finished May 23 03:38:04 PM PDT 24
Peak memory 198532 kb
Host smart-9c6400c4-063c-4251-8612-00a6656b2d8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093654960 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3093654960
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.842222157
Short name T73
Test name
Test status
Simulation time 399378892 ps
CPU time 1.12 seconds
Started May 23 02:04:56 PM PDT 24
Finished May 23 02:04:59 PM PDT 24
Peak memory 183816 kb
Host smart-05137365-354f-4df2-accc-1f3368e98769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842222157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.842222157
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.985812224
Short name T396
Test name
Test status
Simulation time 8381362889 ps
CPU time 3.53 seconds
Started May 23 02:04:21 PM PDT 24
Finished May 23 02:04:26 PM PDT 24
Peak memory 198136 kb
Host smart-b527432e-05e6-4dec-8b5d-3fe85a79ce49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985812224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.985812224
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3824794345
Short name T113
Test name
Test status
Simulation time 4310987474 ps
CPU time 6.78 seconds
Started May 23 02:05:11 PM PDT 24
Finished May 23 02:05:19 PM PDT 24
Peak memory 196624 kb
Host smart-69aa5be0-5d41-4b77-abaf-2183de39c357
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824794345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3824794345
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1158334230
Short name T388
Test name
Test status
Simulation time 622422623 ps
CPU time 0.9 seconds
Started May 23 02:04:21 PM PDT 24
Finished May 23 02:04:22 PM PDT 24
Peak memory 193220 kb
Host smart-6f346f66-6ec3-48f5-888d-24961c4b9e8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158334230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1158334230
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2376091456
Short name T409
Test name
Test status
Simulation time 13875603000 ps
CPU time 28.76 seconds
Started May 23 02:04:29 PM PDT 24
Finished May 23 02:04:58 PM PDT 24
Peak memory 192308 kb
Host smart-9e8a3fa3-7a8a-4f75-8d0d-96acba28d281
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376091456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2376091456
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.779965866
Short name T52
Test name
Test status
Simulation time 605841115 ps
CPU time 0.81 seconds
Started May 23 02:04:21 PM PDT 24
Finished May 23 02:04:23 PM PDT 24
Peak memory 183728 kb
Host smart-382c838c-f2c2-49c7-a741-86300b799d7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779965866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.779965866
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1197604306
Short name T397
Test name
Test status
Simulation time 526685879 ps
CPU time 1.58 seconds
Started May 23 02:04:29 PM PDT 24
Finished May 23 02:04:31 PM PDT 24
Peak memory 195872 kb
Host smart-3acd06f5-9ee0-478f-a6c3-98cd108a9539
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197604306 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1197604306
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1628176109
Short name T61
Test name
Test status
Simulation time 443495371 ps
CPU time 0.93 seconds
Started May 23 02:04:22 PM PDT 24
Finished May 23 02:04:25 PM PDT 24
Peak memory 193148 kb
Host smart-a7a87b1a-439f-456b-9c2a-7f0f3df214ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628176109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1628176109
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2097741134
Short name T284
Test name
Test status
Simulation time 523474100 ps
CPU time 0.7 seconds
Started May 23 02:04:23 PM PDT 24
Finished May 23 02:04:25 PM PDT 24
Peak memory 183692 kb
Host smart-39bee695-9302-4afb-9043-ae2597a17695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097741134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2097741134
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.845933048
Short name T324
Test name
Test status
Simulation time 369836551 ps
CPU time 1.1 seconds
Started May 23 02:04:26 PM PDT 24
Finished May 23 02:04:28 PM PDT 24
Peak memory 183668 kb
Host smart-c1775544-d545-447a-b937-a661f9d900ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845933048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.845933048
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2261968007
Short name T422
Test name
Test status
Simulation time 458021756 ps
CPU time 0.89 seconds
Started May 23 02:04:21 PM PDT 24
Finished May 23 02:04:23 PM PDT 24
Peak memory 183708 kb
Host smart-f5b57dd5-e3d3-497d-8a76-ee679eb711e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261968007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2261968007
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4160474645
Short name T393
Test name
Test status
Simulation time 1203179873 ps
CPU time 2.13 seconds
Started May 23 02:04:24 PM PDT 24
Finished May 23 02:04:27 PM PDT 24
Peak memory 193276 kb
Host smart-1f1d6a59-7a28-4487-bf23-e60ac0306345
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160474645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.4160474645
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2397765213
Short name T379
Test name
Test status
Simulation time 403594373 ps
CPU time 1.86 seconds
Started May 23 02:04:21 PM PDT 24
Finished May 23 02:04:23 PM PDT 24
Peak memory 198312 kb
Host smart-1a07947a-f55a-4a06-b409-687af0850b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397765213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2397765213
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2111852646
Short name T370
Test name
Test status
Simulation time 8858558771 ps
CPU time 4.96 seconds
Started May 23 02:04:23 PM PDT 24
Finished May 23 02:04:29 PM PDT 24
Peak memory 198052 kb
Host smart-7da24400-1017-4d14-b73e-09dc82addde9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111852646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2111852646
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3622667088
Short name T326
Test name
Test status
Simulation time 528522217 ps
CPU time 1.16 seconds
Started May 23 02:04:23 PM PDT 24
Finished May 23 02:04:26 PM PDT 24
Peak memory 183872 kb
Host smart-47e6f882-b643-4e78-9229-b9b885a990eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622667088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3622667088
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2774369758
Short name T60
Test name
Test status
Simulation time 13569016331 ps
CPU time 11.51 seconds
Started May 23 02:04:27 PM PDT 24
Finished May 23 02:04:40 PM PDT 24
Peak memory 192312 kb
Host smart-56dd2ed0-afc0-46ea-be51-81cc58077242
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774369758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2774369758
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3605705147
Short name T336
Test name
Test status
Simulation time 842171971 ps
CPU time 0.74 seconds
Started May 23 02:04:21 PM PDT 24
Finished May 23 02:04:23 PM PDT 24
Peak memory 183884 kb
Host smart-e9ec33f4-aa0e-4d95-9b91-5e45658f905c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605705147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3605705147
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2464736549
Short name T361
Test name
Test status
Simulation time 593372380 ps
CPU time 0.66 seconds
Started May 23 02:04:28 PM PDT 24
Finished May 23 02:04:30 PM PDT 24
Peak memory 195500 kb
Host smart-531561ed-830a-4ef2-ba5a-fa2004d43342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464736549 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2464736549
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.654720606
Short name T54
Test name
Test status
Simulation time 521857725 ps
CPU time 0.78 seconds
Started May 23 02:04:22 PM PDT 24
Finished May 23 02:04:24 PM PDT 24
Peak memory 183860 kb
Host smart-57ecfa83-46df-49a8-b591-d7fb217ff2b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654720606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.654720606
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4192810631
Short name T309
Test name
Test status
Simulation time 313784319 ps
CPU time 1 seconds
Started May 23 02:04:24 PM PDT 24
Finished May 23 02:04:26 PM PDT 24
Peak memory 183760 kb
Host smart-d1751bef-2fff-4a75-9a12-cd56407f6870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192810631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.4192810631
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2598022867
Short name T357
Test name
Test status
Simulation time 329460209 ps
CPU time 0.72 seconds
Started May 23 02:04:21 PM PDT 24
Finished May 23 02:04:23 PM PDT 24
Peak memory 183628 kb
Host smart-6eb1465e-942a-41a8-8a19-268d991948c5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598022867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2598022867
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.731204359
Short name T367
Test name
Test status
Simulation time 484293567 ps
CPU time 0.89 seconds
Started May 23 02:04:24 PM PDT 24
Finished May 23 02:04:27 PM PDT 24
Peak memory 183720 kb
Host smart-57fbec0c-9567-45d6-8a90-c6941195c583
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731204359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.731204359
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2982295397
Short name T406
Test name
Test status
Simulation time 1556965697 ps
CPU time 4.21 seconds
Started May 23 02:04:21 PM PDT 24
Finished May 23 02:04:27 PM PDT 24
Peak memory 193456 kb
Host smart-b1507e37-ac46-4a54-be1d-a4e1f14da40c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982295397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2982295397
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.309385902
Short name T328
Test name
Test status
Simulation time 509982280 ps
CPU time 1.12 seconds
Started May 23 02:04:22 PM PDT 24
Finished May 23 02:04:24 PM PDT 24
Peak memory 197296 kb
Host smart-c2e9c520-f9be-4ab5-9a2d-a358f9d26ec3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309385902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.309385902
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.358722736
Short name T298
Test name
Test status
Simulation time 509878914 ps
CPU time 0.81 seconds
Started May 23 02:04:57 PM PDT 24
Finished May 23 02:05:00 PM PDT 24
Peak memory 195300 kb
Host smart-b61e3e14-194a-4578-b8ae-65cdd98aaa86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358722736 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.358722736
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3617283463
Short name T381
Test name
Test status
Simulation time 449868567 ps
CPU time 0.7 seconds
Started May 23 02:04:58 PM PDT 24
Finished May 23 02:05:01 PM PDT 24
Peak memory 183712 kb
Host smart-253c85d8-74d5-4984-bea7-07189f0ca403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617283463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3617283463
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.483988705
Short name T79
Test name
Test status
Simulation time 1834258362 ps
CPU time 1.4 seconds
Started May 23 02:05:00 PM PDT 24
Finished May 23 02:05:03 PM PDT 24
Peak memory 194456 kb
Host smart-32b0c0c6-905a-4e7a-bbab-dbcf518bfcbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483988705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.483988705
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.642448124
Short name T358
Test name
Test status
Simulation time 571684616 ps
CPU time 2.65 seconds
Started May 23 02:04:56 PM PDT 24
Finished May 23 02:05:01 PM PDT 24
Peak memory 198608 kb
Host smart-aba889eb-0f07-4f78-b5b9-8d062266dd87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642448124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.642448124
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.4065543488
Short name T421
Test name
Test status
Simulation time 4690768561 ps
CPU time 7.98 seconds
Started May 23 02:04:59 PM PDT 24
Finished May 23 02:05:10 PM PDT 24
Peak memory 197896 kb
Host smart-7b918ad0-454e-49ff-9c30-3d9b1aacf420
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065543488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.4065543488
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2993974227
Short name T297
Test name
Test status
Simulation time 459263328 ps
CPU time 1.41 seconds
Started May 23 02:04:58 PM PDT 24
Finished May 23 02:05:01 PM PDT 24
Peak memory 195252 kb
Host smart-02e6661a-4320-4f80-b06f-a7fd71928dfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993974227 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2993974227
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2793030026
Short name T394
Test name
Test status
Simulation time 335569315 ps
CPU time 1.11 seconds
Started May 23 02:04:56 PM PDT 24
Finished May 23 02:04:59 PM PDT 24
Peak memory 183824 kb
Host smart-1a23c605-37ef-449c-a16f-68a5c02b1fc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793030026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2793030026
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3913593509
Short name T283
Test name
Test status
Simulation time 430059966 ps
CPU time 0.97 seconds
Started May 23 02:04:59 PM PDT 24
Finished May 23 02:05:02 PM PDT 24
Peak memory 183736 kb
Host smart-98d9c349-beba-4d79-aca9-7d9f36795bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913593509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3913593509
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2521150800
Short name T407
Test name
Test status
Simulation time 1199714460 ps
CPU time 0.77 seconds
Started May 23 02:04:56 PM PDT 24
Finished May 23 02:04:58 PM PDT 24
Peak memory 193528 kb
Host smart-ace35253-7d61-4d6e-b5f8-76865770bb73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521150800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2521150800
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3012995514
Short name T311
Test name
Test status
Simulation time 316754818 ps
CPU time 1.45 seconds
Started May 23 02:04:59 PM PDT 24
Finished May 23 02:05:03 PM PDT 24
Peak memory 198444 kb
Host smart-615166fb-5113-464b-9b44-a6d2254374ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012995514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3012995514
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.591426673
Short name T391
Test name
Test status
Simulation time 4435167452 ps
CPU time 8.44 seconds
Started May 23 02:04:57 PM PDT 24
Finished May 23 02:05:07 PM PDT 24
Peak memory 197676 kb
Host smart-70eb7275-35e5-4701-83e1-c4829bd6d977
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591426673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.591426673
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.234239667
Short name T356
Test name
Test status
Simulation time 622828795 ps
CPU time 1.04 seconds
Started May 23 02:04:57 PM PDT 24
Finished May 23 02:05:00 PM PDT 24
Peak memory 196056 kb
Host smart-f1741e3f-96f5-496d-ac00-69b9d5b54dbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234239667 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.234239667
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.198367435
Short name T387
Test name
Test status
Simulation time 303210733 ps
CPU time 0.71 seconds
Started May 23 02:04:59 PM PDT 24
Finished May 23 02:05:01 PM PDT 24
Peak memory 193076 kb
Host smart-ef40b182-5ff3-4a5a-aba8-65863b37fa9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198367435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.198367435
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1891821420
Short name T307
Test name
Test status
Simulation time 466911224 ps
CPU time 1.2 seconds
Started May 23 02:04:56 PM PDT 24
Finished May 23 02:04:58 PM PDT 24
Peak memory 183672 kb
Host smart-60100799-ed09-4023-ab10-fe9614c85c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891821420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1891821420
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1846592141
Short name T76
Test name
Test status
Simulation time 2175261440 ps
CPU time 1.39 seconds
Started May 23 02:05:00 PM PDT 24
Finished May 23 02:05:03 PM PDT 24
Peak memory 194088 kb
Host smart-8d7182fb-34f4-4109-b9c3-64a20412d9af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846592141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1846592141
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.628731697
Short name T300
Test name
Test status
Simulation time 723222273 ps
CPU time 1.86 seconds
Started May 23 02:05:01 PM PDT 24
Finished May 23 02:05:04 PM PDT 24
Peak memory 198616 kb
Host smart-798b5349-97df-4900-a689-fd2636c402d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628731697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.628731697
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1259555317
Short name T350
Test name
Test status
Simulation time 8423788868 ps
CPU time 11.08 seconds
Started May 23 02:04:56 PM PDT 24
Finished May 23 02:05:09 PM PDT 24
Peak memory 197996 kb
Host smart-3249e141-f24a-492c-a42e-f7f5a007b93c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259555317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1259555317
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2884070114
Short name T22
Test name
Test status
Simulation time 315893014 ps
CPU time 1.09 seconds
Started May 23 02:05:01 PM PDT 24
Finished May 23 02:05:03 PM PDT 24
Peak memory 195640 kb
Host smart-2568a6d8-970d-4b73-913c-407900ef7bfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884070114 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2884070114
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2919300530
Short name T23
Test name
Test status
Simulation time 439626709 ps
CPU time 1.19 seconds
Started May 23 02:05:01 PM PDT 24
Finished May 23 02:05:04 PM PDT 24
Peak memory 183780 kb
Host smart-d3b0f5ea-c732-4e9f-9933-12d4ea07d8b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919300530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2919300530
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1616305502
Short name T364
Test name
Test status
Simulation time 410195799 ps
CPU time 0.64 seconds
Started May 23 02:04:57 PM PDT 24
Finished May 23 02:05:00 PM PDT 24
Peak memory 183712 kb
Host smart-27c67bea-9776-481e-b6d0-8fbb118ff991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616305502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1616305502
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.390699197
Short name T392
Test name
Test status
Simulation time 1766963322 ps
CPU time 1.67 seconds
Started May 23 02:04:58 PM PDT 24
Finished May 23 02:05:01 PM PDT 24
Peak memory 193308 kb
Host smart-bec4a12c-ece6-4a72-947f-c53aa6bb71f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390699197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.390699197
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2567988275
Short name T335
Test name
Test status
Simulation time 596953266 ps
CPU time 2.7 seconds
Started May 23 02:04:58 PM PDT 24
Finished May 23 02:05:02 PM PDT 24
Peak memory 198648 kb
Host smart-b57bffd7-f5e2-48a2-9f13-ba52859aa282
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567988275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2567988275
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4082598655
Short name T353
Test name
Test status
Simulation time 8376880301 ps
CPU time 15.01 seconds
Started May 23 02:04:57 PM PDT 24
Finished May 23 02:05:13 PM PDT 24
Peak memory 198032 kb
Host smart-65bad97d-6b8c-4c1e-ac3d-a9f2fd888ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082598655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.4082598655
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1274725254
Short name T295
Test name
Test status
Simulation time 363062904 ps
CPU time 1.15 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:12 PM PDT 24
Peak memory 195200 kb
Host smart-ad361edb-7576-40fa-aee4-d41bdff073fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274725254 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1274725254
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3572456544
Short name T59
Test name
Test status
Simulation time 303593862 ps
CPU time 1.08 seconds
Started May 23 02:05:29 PM PDT 24
Finished May 23 02:05:31 PM PDT 24
Peak memory 183768 kb
Host smart-37983d47-e423-4de9-9626-584e244b7304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572456544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3572456544
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3814635742
Short name T292
Test name
Test status
Simulation time 354196342 ps
CPU time 0.68 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:10 PM PDT 24
Peak memory 183720 kb
Host smart-4fd23b6b-ac3c-4b0f-a5a9-39c66ce04ef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814635742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3814635742
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.451090078
Short name T74
Test name
Test status
Simulation time 1221655325 ps
CPU time 0.81 seconds
Started May 23 02:05:10 PM PDT 24
Finished May 23 02:05:12 PM PDT 24
Peak memory 183808 kb
Host smart-6c0475fe-8d07-4539-9521-960e0bed8493
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451090078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.451090078
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3346594418
Short name T366
Test name
Test status
Simulation time 524540379 ps
CPU time 1.19 seconds
Started May 23 02:04:57 PM PDT 24
Finished May 23 02:04:59 PM PDT 24
Peak memory 198396 kb
Host smart-fbb0e5bb-b2f7-42c0-802c-52e052187397
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346594418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3346594418
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3902560729
Short name T112
Test name
Test status
Simulation time 4554600893 ps
CPU time 7.29 seconds
Started May 23 02:05:12 PM PDT 24
Finished May 23 02:05:20 PM PDT 24
Peak memory 197852 kb
Host smart-90d6cfdc-9a99-4c0e-a564-0d8f3a23ea2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902560729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3902560729
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1355822161
Short name T333
Test name
Test status
Simulation time 455654170 ps
CPU time 0.96 seconds
Started May 23 02:05:10 PM PDT 24
Finished May 23 02:05:12 PM PDT 24
Peak memory 196856 kb
Host smart-97aa2210-b2dc-4987-b492-f47c3bc13979
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355822161 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1355822161
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3994503205
Short name T287
Test name
Test status
Simulation time 347920588 ps
CPU time 0.62 seconds
Started May 23 02:05:10 PM PDT 24
Finished May 23 02:05:11 PM PDT 24
Peak memory 193100 kb
Host smart-cf4a7efc-98df-44ac-b66f-be9b7e26cc60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994503205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3994503205
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3507234899
Short name T316
Test name
Test status
Simulation time 360922018 ps
CPU time 0.84 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:11 PM PDT 24
Peak memory 183708 kb
Host smart-1f68b9a6-f064-41c6-8140-c5352c2557d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507234899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3507234899
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1858203251
Short name T385
Test name
Test status
Simulation time 1193425236 ps
CPU time 2.14 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:12 PM PDT 24
Peak memory 193544 kb
Host smart-82266f37-e60b-4268-be50-65b7aae19d66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858203251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1858203251
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.308432451
Short name T417
Test name
Test status
Simulation time 379493040 ps
CPU time 1.81 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:11 PM PDT 24
Peak memory 198624 kb
Host smart-aa965168-f1d8-45cb-887b-36b92a9f0667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308432451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.308432451
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2237036124
Short name T348
Test name
Test status
Simulation time 4454610921 ps
CPU time 4.65 seconds
Started May 23 02:05:10 PM PDT 24
Finished May 23 02:05:16 PM PDT 24
Peak memory 197444 kb
Host smart-ebb56daa-a91a-438c-b296-7be362dcecbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237036124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2237036124
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4294789039
Short name T380
Test name
Test status
Simulation time 633539659 ps
CPU time 0.76 seconds
Started May 23 02:05:12 PM PDT 24
Finished May 23 02:05:14 PM PDT 24
Peak memory 195840 kb
Host smart-dd352235-92ed-40f6-a587-c639c44e8de1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294789039 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.4294789039
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2622461143
Short name T25
Test name
Test status
Simulation time 351061277 ps
CPU time 0.7 seconds
Started May 23 02:05:12 PM PDT 24
Finished May 23 02:05:14 PM PDT 24
Peak memory 193052 kb
Host smart-0de3c4a5-bf6c-46fa-8f3d-0b339816b9f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622461143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2622461143
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1557523433
Short name T345
Test name
Test status
Simulation time 380664257 ps
CPU time 1.07 seconds
Started May 23 02:05:12 PM PDT 24
Finished May 23 02:05:14 PM PDT 24
Peak memory 183732 kb
Host smart-a8610220-acb1-4c9e-8f48-c2d1d84a8f67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557523433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1557523433
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.22910258
Short name T339
Test name
Test status
Simulation time 1205887517 ps
CPU time 2.1 seconds
Started May 23 02:05:13 PM PDT 24
Finished May 23 02:05:16 PM PDT 24
Peak memory 193316 kb
Host smart-496dc49d-dffe-442f-8b8f-ec7a58622b2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22910258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_
timer_same_csr_outstanding.22910258
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.906392472
Short name T351
Test name
Test status
Simulation time 956355552 ps
CPU time 2.23 seconds
Started May 23 02:05:12 PM PDT 24
Finished May 23 02:05:15 PM PDT 24
Peak memory 198592 kb
Host smart-616d282a-8918-4508-91a7-8f1ed632bd82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906392472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.906392472
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1900802830
Short name T414
Test name
Test status
Simulation time 7385157900 ps
CPU time 7.18 seconds
Started May 23 02:05:16 PM PDT 24
Finished May 23 02:05:24 PM PDT 24
Peak memory 197916 kb
Host smart-1c8340c5-13a3-4aa5-85da-ede4ba099e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900802830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1900802830
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.340525249
Short name T89
Test name
Test status
Simulation time 711169109 ps
CPU time 0.91 seconds
Started May 23 02:05:10 PM PDT 24
Finished May 23 02:05:13 PM PDT 24
Peak memory 196504 kb
Host smart-9febc153-91a5-4572-9b3c-7017c794ce2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340525249 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.340525249
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.470041506
Short name T410
Test name
Test status
Simulation time 369090231 ps
CPU time 1.2 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:11 PM PDT 24
Peak memory 184092 kb
Host smart-f532fa50-4178-475a-b105-02a325e132cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470041506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.470041506
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1360472298
Short name T331
Test name
Test status
Simulation time 451998858 ps
CPU time 1.21 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:11 PM PDT 24
Peak memory 183720 kb
Host smart-28abcbd2-8680-4e24-b3dd-208759278e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360472298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1360472298
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.612343448
Short name T398
Test name
Test status
Simulation time 997322445 ps
CPU time 1.09 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:11 PM PDT 24
Peak memory 193356 kb
Host smart-90be646f-ce05-4887-8e6d-faf8c87e2f57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612343448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.612343448
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1860566681
Short name T412
Test name
Test status
Simulation time 552448904 ps
CPU time 1.93 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:12 PM PDT 24
Peak memory 198624 kb
Host smart-6f1e772c-deb4-4d53-a54f-180fefc50a1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860566681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1860566681
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1810632315
Short name T327
Test name
Test status
Simulation time 620256783 ps
CPU time 1.18 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:10 PM PDT 24
Peak memory 195756 kb
Host smart-dad4ee81-79b5-4b4c-9a73-93d5c10f4beb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810632315 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1810632315
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2276498012
Short name T57
Test name
Test status
Simulation time 410307550 ps
CPU time 0.64 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:11 PM PDT 24
Peak memory 183948 kb
Host smart-a11a9980-f699-4c8e-96f3-9a9b8526d646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276498012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2276498012
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1299912988
Short name T312
Test name
Test status
Simulation time 300855747 ps
CPU time 0.93 seconds
Started May 23 02:05:10 PM PDT 24
Finished May 23 02:05:12 PM PDT 24
Peak memory 183672 kb
Host smart-03404cde-24a3-41bd-bda9-69e49af3b635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299912988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1299912988
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2536405191
Short name T404
Test name
Test status
Simulation time 1118060677 ps
CPU time 0.97 seconds
Started May 23 02:05:10 PM PDT 24
Finished May 23 02:05:12 PM PDT 24
Peak memory 193428 kb
Host smart-096cda53-fb8d-4489-b293-3f04fa970876
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536405191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2536405191
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1726584485
Short name T310
Test name
Test status
Simulation time 389928007 ps
CPU time 1.73 seconds
Started May 23 02:05:10 PM PDT 24
Finished May 23 02:05:13 PM PDT 24
Peak memory 198624 kb
Host smart-e0108f71-f55c-4862-ab0a-72ceae90fcef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726584485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1726584485
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.523087268
Short name T299
Test name
Test status
Simulation time 474601689 ps
CPU time 1.12 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:12 PM PDT 24
Peak memory 196252 kb
Host smart-9b18a161-d074-4089-b8bb-e3a06f0f7c4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523087268 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.523087268
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3612157407
Short name T402
Test name
Test status
Simulation time 409759420 ps
CPU time 0.72 seconds
Started May 23 02:05:08 PM PDT 24
Finished May 23 02:05:09 PM PDT 24
Peak memory 183824 kb
Host smart-9632d81c-4cb7-4d52-8c53-eadc863e0f27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612157407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3612157407
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3714269473
Short name T390
Test name
Test status
Simulation time 340514019 ps
CPU time 0.9 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:11 PM PDT 24
Peak memory 183652 kb
Host smart-841fdd01-3224-4575-8504-c88549715e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714269473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3714269473
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1029052923
Short name T354
Test name
Test status
Simulation time 2487456060 ps
CPU time 1.7 seconds
Started May 23 02:05:11 PM PDT 24
Finished May 23 02:05:14 PM PDT 24
Peak memory 194828 kb
Host smart-9f5ace94-631f-49b8-b0d0-a5eccd300129
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029052923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1029052923
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2624598878
Short name T400
Test name
Test status
Simulation time 436595137 ps
CPU time 2.22 seconds
Started May 23 02:05:13 PM PDT 24
Finished May 23 02:05:16 PM PDT 24
Peak memory 198668 kb
Host smart-f76eba82-ee56-4648-a756-c6a5934df3c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624598878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2624598878
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4026424292
Short name T401
Test name
Test status
Simulation time 4314892736 ps
CPU time 3.62 seconds
Started May 23 02:05:11 PM PDT 24
Finished May 23 02:05:16 PM PDT 24
Peak memory 196648 kb
Host smart-f6fdc28a-ee1d-4c62-b2ad-ad58b587af27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026424292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.4026424292
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1905654576
Short name T58
Test name
Test status
Simulation time 6842636837 ps
CPU time 5.55 seconds
Started May 23 02:04:22 PM PDT 24
Finished May 23 02:04:29 PM PDT 24
Peak memory 192352 kb
Host smart-6e9a8269-4add-4a01-bb1b-4c91186e06f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905654576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1905654576
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.489495185
Short name T405
Test name
Test status
Simulation time 917778323 ps
CPU time 0.87 seconds
Started May 23 02:04:26 PM PDT 24
Finished May 23 02:04:28 PM PDT 24
Peak memory 183888 kb
Host smart-f512d767-2384-49a0-a418-3ec297afa4a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489495185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.489495185
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1486837616
Short name T365
Test name
Test status
Simulation time 514914565 ps
CPU time 1.39 seconds
Started May 23 02:04:35 PM PDT 24
Finished May 23 02:04:38 PM PDT 24
Peak memory 195708 kb
Host smart-2f5e4388-2d6f-4972-afba-9c083b06561f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486837616 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1486837616
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1150859216
Short name T368
Test name
Test status
Simulation time 542898949 ps
CPU time 0.72 seconds
Started May 23 02:04:22 PM PDT 24
Finished May 23 02:04:25 PM PDT 24
Peak memory 183832 kb
Host smart-b351e2d6-e447-4e3b-a71a-ff7aa745ff8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150859216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1150859216
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.750283373
Short name T317
Test name
Test status
Simulation time 500105871 ps
CPU time 0.61 seconds
Started May 23 02:04:22 PM PDT 24
Finished May 23 02:04:24 PM PDT 24
Peak memory 183708 kb
Host smart-f58387e6-8497-4bce-8493-386c31cd164c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750283373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.750283373
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1860433263
Short name T376
Test name
Test status
Simulation time 397450877 ps
CPU time 0.64 seconds
Started May 23 02:04:26 PM PDT 24
Finished May 23 02:04:27 PM PDT 24
Peak memory 183656 kb
Host smart-3b840409-34ea-417e-8315-7be63a9bcc9f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860433263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1860433263
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.93324351
Short name T346
Test name
Test status
Simulation time 372634090 ps
CPU time 0.63 seconds
Started May 23 02:04:29 PM PDT 24
Finished May 23 02:04:30 PM PDT 24
Peak memory 183716 kb
Host smart-82f80bad-a4c5-4a30-83cb-d852b7ba0bbb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93324351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wal
k.93324351
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2269435584
Short name T332
Test name
Test status
Simulation time 1561763437 ps
CPU time 1.18 seconds
Started May 23 02:04:35 PM PDT 24
Finished May 23 02:04:37 PM PDT 24
Peak memory 193264 kb
Host smart-6dad5484-4435-478c-8a8a-cb1cc5dd6c36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269435584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2269435584
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1636553590
Short name T408
Test name
Test status
Simulation time 503898744 ps
CPU time 1.96 seconds
Started May 23 02:04:21 PM PDT 24
Finished May 23 02:04:24 PM PDT 24
Peak memory 198556 kb
Host smart-495faf6e-89f2-4408-a2db-5743d54f4fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636553590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1636553590
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1987818777
Short name T363
Test name
Test status
Simulation time 7834176283 ps
CPU time 13.13 seconds
Started May 23 02:04:21 PM PDT 24
Finished May 23 02:04:36 PM PDT 24
Peak memory 197840 kb
Host smart-fbbee06e-1433-448d-b29f-3072cb249e63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987818777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1987818777
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3505089333
Short name T343
Test name
Test status
Simulation time 280727822 ps
CPU time 0.69 seconds
Started May 23 02:05:12 PM PDT 24
Finished May 23 02:05:14 PM PDT 24
Peak memory 183768 kb
Host smart-410e2cab-2610-4f9c-aaea-3aeb15e515c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505089333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3505089333
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1797750519
Short name T373
Test name
Test status
Simulation time 463162881 ps
CPU time 0.75 seconds
Started May 23 02:05:15 PM PDT 24
Finished May 23 02:05:17 PM PDT 24
Peak memory 183568 kb
Host smart-6430779b-a04a-45c2-94b2-d5f40ef940df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797750519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1797750519
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3327583738
Short name T315
Test name
Test status
Simulation time 377738107 ps
CPU time 0.67 seconds
Started May 23 02:05:15 PM PDT 24
Finished May 23 02:05:16 PM PDT 24
Peak memory 183568 kb
Host smart-935892ec-1b73-4151-9e52-c0e512d19355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327583738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3327583738
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.4252728832
Short name T399
Test name
Test status
Simulation time 309661261 ps
CPU time 0.65 seconds
Started May 23 02:05:14 PM PDT 24
Finished May 23 02:05:16 PM PDT 24
Peak memory 183732 kb
Host smart-afd9ba01-57a6-4280-accf-cdb0d2b03c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252728832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.4252728832
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1529244819
Short name T323
Test name
Test status
Simulation time 411646050 ps
CPU time 0.62 seconds
Started May 23 02:05:08 PM PDT 24
Finished May 23 02:05:09 PM PDT 24
Peak memory 183708 kb
Host smart-55a47647-2038-44cb-ac1b-169512464e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529244819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1529244819
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1690939279
Short name T325
Test name
Test status
Simulation time 341938018 ps
CPU time 0.81 seconds
Started May 23 02:05:11 PM PDT 24
Finished May 23 02:05:14 PM PDT 24
Peak memory 183696 kb
Host smart-17bb4baf-af19-434f-b6e1-8e1295efaa70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690939279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1690939279
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.765715862
Short name T341
Test name
Test status
Simulation time 351604664 ps
CPU time 1.09 seconds
Started May 23 02:05:10 PM PDT 24
Finished May 23 02:05:13 PM PDT 24
Peak memory 183768 kb
Host smart-bd24ce0d-7264-41aa-9cbe-2f246b4841d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765715862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.765715862
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3308718713
Short name T290
Test name
Test status
Simulation time 375240536 ps
CPU time 1.13 seconds
Started May 23 02:05:10 PM PDT 24
Finished May 23 02:05:12 PM PDT 24
Peak memory 183720 kb
Host smart-5ae2b2c7-bbbd-485a-bdae-ab4ee0028a73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308718713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3308718713
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1486230852
Short name T420
Test name
Test status
Simulation time 490752717 ps
CPU time 0.75 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:11 PM PDT 24
Peak memory 183744 kb
Host smart-09d2bd88-6254-464f-b723-18de3a6c87b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486230852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1486230852
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1923332196
Short name T375
Test name
Test status
Simulation time 324392611 ps
CPU time 0.89 seconds
Started May 23 02:05:11 PM PDT 24
Finished May 23 02:05:14 PM PDT 24
Peak memory 183760 kb
Host smart-56d0c637-f935-48c8-af5d-e84b248cf136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923332196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1923332196
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4005717545
Short name T308
Test name
Test status
Simulation time 588005189 ps
CPU time 1.65 seconds
Started May 23 02:04:33 PM PDT 24
Finished May 23 02:04:35 PM PDT 24
Peak memory 183876 kb
Host smart-251b0c77-426b-46e5-88c5-c7f78befb8cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005717545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4005717545
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1758510181
Short name T62
Test name
Test status
Simulation time 10551492936 ps
CPU time 5.87 seconds
Started May 23 02:04:33 PM PDT 24
Finished May 23 02:04:40 PM PDT 24
Peak memory 184080 kb
Host smart-18c72443-a7c2-41e2-8e78-839e941ed01f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758510181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1758510181
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4017040063
Short name T344
Test name
Test status
Simulation time 1176885575 ps
CPU time 0.95 seconds
Started May 23 02:04:37 PM PDT 24
Finished May 23 02:04:39 PM PDT 24
Peak memory 183876 kb
Host smart-5c47c849-db14-471c-bb54-a7051a2bb68b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017040063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.4017040063
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2362468881
Short name T371
Test name
Test status
Simulation time 547596093 ps
CPU time 0.86 seconds
Started May 23 02:04:32 PM PDT 24
Finished May 23 02:04:33 PM PDT 24
Peak memory 196276 kb
Host smart-0636004b-f287-4b30-8c4f-1674f8963852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362468881 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2362468881
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3697196072
Short name T55
Test name
Test status
Simulation time 494683700 ps
CPU time 0.63 seconds
Started May 23 02:04:33 PM PDT 24
Finished May 23 02:04:35 PM PDT 24
Peak memory 183832 kb
Host smart-083b541b-9d0b-4b75-a453-5d17c8941732
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697196072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3697196072
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.657499320
Short name T305
Test name
Test status
Simulation time 287655088 ps
CPU time 0.93 seconds
Started May 23 02:04:33 PM PDT 24
Finished May 23 02:04:35 PM PDT 24
Peak memory 183712 kb
Host smart-dc7cf2d1-8d27-44d7-afd9-96c1ae48855c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657499320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.657499320
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2022535232
Short name T294
Test name
Test status
Simulation time 514231110 ps
CPU time 0.66 seconds
Started May 23 02:04:32 PM PDT 24
Finished May 23 02:04:33 PM PDT 24
Peak memory 183660 kb
Host smart-b6503af1-5d35-47e8-8b1e-e73521f10bfc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022535232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2022535232
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1580941758
Short name T306
Test name
Test status
Simulation time 330382026 ps
CPU time 0.67 seconds
Started May 23 02:04:32 PM PDT 24
Finished May 23 02:04:34 PM PDT 24
Peak memory 183720 kb
Host smart-f0b8a950-ff72-4548-b13c-fb569b9a1815
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580941758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1580941758
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.84852462
Short name T389
Test name
Test status
Simulation time 970433351 ps
CPU time 1.04 seconds
Started May 23 02:04:32 PM PDT 24
Finished May 23 02:04:34 PM PDT 24
Peak memory 193308 kb
Host smart-f1a216cf-49bd-4a8e-9478-6ba5efc45e28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84852462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_same_csr_outstanding.84852462
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.233376854
Short name T302
Test name
Test status
Simulation time 507103073 ps
CPU time 1.73 seconds
Started May 23 02:04:33 PM PDT 24
Finished May 23 02:04:36 PM PDT 24
Peak memory 198440 kb
Host smart-23757c2f-7804-4973-add9-dfe76168e166
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233376854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.233376854
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2827218225
Short name T110
Test name
Test status
Simulation time 4533748771 ps
CPU time 5.52 seconds
Started May 23 02:04:35 PM PDT 24
Finished May 23 02:04:42 PM PDT 24
Peak memory 197612 kb
Host smart-61d7918e-ddaa-4962-8893-44b9b1b7e515
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827218225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2827218225
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1487874308
Short name T352
Test name
Test status
Simulation time 516472928 ps
CPU time 0.75 seconds
Started May 23 02:05:09 PM PDT 24
Finished May 23 02:05:10 PM PDT 24
Peak memory 183780 kb
Host smart-da7d4761-946a-4af6-ad43-0163dac952e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487874308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1487874308
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1137962415
Short name T318
Test name
Test status
Simulation time 493091343 ps
CPU time 1.19 seconds
Started May 23 02:05:22 PM PDT 24
Finished May 23 02:05:24 PM PDT 24
Peak memory 183708 kb
Host smart-79986868-0796-49db-aa3e-4c17b5610d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137962415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1137962415
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3883568967
Short name T321
Test name
Test status
Simulation time 483058629 ps
CPU time 1.24 seconds
Started May 23 02:05:23 PM PDT 24
Finished May 23 02:05:26 PM PDT 24
Peak memory 183696 kb
Host smart-50af03bf-d8ba-4d36-88db-9428154677ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883568967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3883568967
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2423461788
Short name T291
Test name
Test status
Simulation time 295961597 ps
CPU time 0.63 seconds
Started May 23 02:05:22 PM PDT 24
Finished May 23 02:05:24 PM PDT 24
Peak memory 183740 kb
Host smart-a5f13cd6-4735-4df5-b7b0-6a816b105991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423461788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2423461788
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3790423163
Short name T282
Test name
Test status
Simulation time 505763129 ps
CPU time 1.31 seconds
Started May 23 02:05:21 PM PDT 24
Finished May 23 02:05:23 PM PDT 24
Peak memory 183780 kb
Host smart-6311bc53-f1b9-465c-b68d-8e49bebfe5c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790423163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3790423163
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2166429012
Short name T349
Test name
Test status
Simulation time 422372788 ps
CPU time 0.88 seconds
Started May 23 02:05:24 PM PDT 24
Finished May 23 02:05:26 PM PDT 24
Peak memory 183676 kb
Host smart-0d2424f1-7712-4317-aad1-5264a79fbf2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166429012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2166429012
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.476329704
Short name T320
Test name
Test status
Simulation time 399653490 ps
CPU time 0.91 seconds
Started May 23 02:05:24 PM PDT 24
Finished May 23 02:05:26 PM PDT 24
Peak memory 183672 kb
Host smart-b4f173bc-d017-4bd4-91f1-f7f77a5493b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476329704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.476329704
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3877797418
Short name T334
Test name
Test status
Simulation time 395289379 ps
CPU time 1.07 seconds
Started May 23 02:05:23 PM PDT 24
Finished May 23 02:05:25 PM PDT 24
Peak memory 183720 kb
Host smart-9533df4e-3b08-46b3-8dbf-0e0644e35be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877797418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3877797418
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.706600250
Short name T303
Test name
Test status
Simulation time 379923308 ps
CPU time 0.69 seconds
Started May 23 02:05:22 PM PDT 24
Finished May 23 02:05:23 PM PDT 24
Peak memory 183712 kb
Host smart-1bda55f6-c5dc-4a32-9464-f76d692d9131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706600250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.706600250
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.33046906
Short name T296
Test name
Test status
Simulation time 340458470 ps
CPU time 0.84 seconds
Started May 23 02:05:22 PM PDT 24
Finished May 23 02:05:24 PM PDT 24
Peak memory 183736 kb
Host smart-2ab0d969-4eb0-4821-b82c-c1a007b397ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33046906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.33046906
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1663267988
Short name T56
Test name
Test status
Simulation time 353476730 ps
CPU time 1.34 seconds
Started May 23 02:04:34 PM PDT 24
Finished May 23 02:04:36 PM PDT 24
Peak memory 183784 kb
Host smart-dfa1e976-da06-4266-b58e-607994ee3b0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663267988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1663267988
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1879853732
Short name T51
Test name
Test status
Simulation time 6580065412 ps
CPU time 11.85 seconds
Started May 23 02:04:34 PM PDT 24
Finished May 23 02:04:47 PM PDT 24
Peak memory 192232 kb
Host smart-51da8f9b-14f8-4dd0-a983-5244686cf6dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879853732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1879853732
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2092452553
Short name T369
Test name
Test status
Simulation time 837166133 ps
CPU time 0.86 seconds
Started May 23 02:04:33 PM PDT 24
Finished May 23 02:04:35 PM PDT 24
Peak memory 183824 kb
Host smart-dadce2bf-08e1-4018-8e6b-511dea050f42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092452553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2092452553
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1639437912
Short name T340
Test name
Test status
Simulation time 361113367 ps
CPU time 0.92 seconds
Started May 23 02:04:34 PM PDT 24
Finished May 23 02:04:37 PM PDT 24
Peak memory 195888 kb
Host smart-a7b0e105-6ed8-4b5f-878f-b340280be35e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639437912 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1639437912
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3514459078
Short name T75
Test name
Test status
Simulation time 494329383 ps
CPU time 0.71 seconds
Started May 23 02:04:37 PM PDT 24
Finished May 23 02:04:39 PM PDT 24
Peak memory 193312 kb
Host smart-ac898652-492b-4513-b318-53fdd3271d86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514459078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3514459078
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4034168938
Short name T288
Test name
Test status
Simulation time 487511858 ps
CPU time 0.72 seconds
Started May 23 02:04:32 PM PDT 24
Finished May 23 02:04:34 PM PDT 24
Peak memory 183748 kb
Host smart-5d95e86d-d0c5-4912-9a20-8342f39e7910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034168938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.4034168938
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3825129422
Short name T337
Test name
Test status
Simulation time 431118736 ps
CPU time 0.65 seconds
Started May 23 02:04:35 PM PDT 24
Finished May 23 02:04:37 PM PDT 24
Peak memory 183624 kb
Host smart-68b00357-4713-44e9-9d46-a685a30b751b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825129422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3825129422
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2694332974
Short name T285
Test name
Test status
Simulation time 409024905 ps
CPU time 0.72 seconds
Started May 23 02:04:35 PM PDT 24
Finished May 23 02:04:37 PM PDT 24
Peak memory 183676 kb
Host smart-b08813f9-e84d-440c-a7d1-0ef4e0f4408b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694332974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2694332974
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.548182272
Short name T77
Test name
Test status
Simulation time 1636767046 ps
CPU time 3.34 seconds
Started May 23 02:04:35 PM PDT 24
Finished May 23 02:04:39 PM PDT 24
Peak memory 193268 kb
Host smart-56245030-4a6a-49c5-b601-b67a3d6b99e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548182272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.548182272
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3694733576
Short name T313
Test name
Test status
Simulation time 512590935 ps
CPU time 1.77 seconds
Started May 23 02:04:37 PM PDT 24
Finished May 23 02:04:39 PM PDT 24
Peak memory 198420 kb
Host smart-3959dc40-d6e6-4be9-ba11-4cb523058af1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694733576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3694733576
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1973609028
Short name T329
Test name
Test status
Simulation time 4120325384 ps
CPU time 2.3 seconds
Started May 23 02:04:33 PM PDT 24
Finished May 23 02:04:37 PM PDT 24
Peak memory 197352 kb
Host smart-ec15edc3-f3b2-4d5a-8198-c8eb718fdfe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973609028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1973609028
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.124034175
Short name T418
Test name
Test status
Simulation time 518258212 ps
CPU time 1.35 seconds
Started May 23 02:05:24 PM PDT 24
Finished May 23 02:05:26 PM PDT 24
Peak memory 183636 kb
Host smart-3acaffc6-bc6d-4876-97bd-8b1ecd9f475e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124034175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.124034175
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2560839196
Short name T289
Test name
Test status
Simulation time 474904395 ps
CPU time 1.27 seconds
Started May 23 02:05:22 PM PDT 24
Finished May 23 02:05:24 PM PDT 24
Peak memory 183724 kb
Host smart-4cdd6099-e9f1-48e5-8ade-6a96e68f8677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560839196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2560839196
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2940909251
Short name T383
Test name
Test status
Simulation time 472412738 ps
CPU time 1.29 seconds
Started May 23 02:05:23 PM PDT 24
Finished May 23 02:05:25 PM PDT 24
Peak memory 183700 kb
Host smart-888f1796-dbe5-4189-a016-90da6f6e5478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940909251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2940909251
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2999907284
Short name T411
Test name
Test status
Simulation time 482940289 ps
CPU time 1.36 seconds
Started May 23 02:05:26 PM PDT 24
Finished May 23 02:05:28 PM PDT 24
Peak memory 183696 kb
Host smart-c454c67f-ffa4-49c9-b4ef-a2de3a1642e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999907284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2999907284
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2555858103
Short name T342
Test name
Test status
Simulation time 510349813 ps
CPU time 1.23 seconds
Started May 23 02:05:24 PM PDT 24
Finished May 23 02:05:26 PM PDT 24
Peak memory 183704 kb
Host smart-8ec0b730-516f-4cee-ab3c-a601aa66e9c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555858103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2555858103
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2404336370
Short name T293
Test name
Test status
Simulation time 370566825 ps
CPU time 0.68 seconds
Started May 23 02:05:25 PM PDT 24
Finished May 23 02:05:27 PM PDT 24
Peak memory 183528 kb
Host smart-de2d50f7-210a-44c7-b273-71a13c6746a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404336370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2404336370
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2516891937
Short name T378
Test name
Test status
Simulation time 298191744 ps
CPU time 0.66 seconds
Started May 23 02:05:22 PM PDT 24
Finished May 23 02:05:24 PM PDT 24
Peak memory 183656 kb
Host smart-b0a76f7d-77c2-4eaa-816c-e2a9fd946e7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516891937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2516891937
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2639188251
Short name T319
Test name
Test status
Simulation time 456412529 ps
CPU time 0.66 seconds
Started May 23 02:05:28 PM PDT 24
Finished May 23 02:05:29 PM PDT 24
Peak memory 183696 kb
Host smart-a476a46e-3682-4cf5-b88a-1fe844fe4e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639188251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2639188251
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3381794343
Short name T395
Test name
Test status
Simulation time 427565855 ps
CPU time 0.71 seconds
Started May 23 02:05:25 PM PDT 24
Finished May 23 02:05:27 PM PDT 24
Peak memory 183708 kb
Host smart-59868b11-1eb3-4ccb-9138-d8d691d2f733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381794343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3381794343
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2960307403
Short name T415
Test name
Test status
Simulation time 387128222 ps
CPU time 0.74 seconds
Started May 23 02:05:25 PM PDT 24
Finished May 23 02:05:26 PM PDT 24
Peak memory 183748 kb
Host smart-f051d06c-48b2-45fb-8c64-52547a11598d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960307403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2960307403
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.713559543
Short name T413
Test name
Test status
Simulation time 400568770 ps
CPU time 0.81 seconds
Started May 23 02:04:34 PM PDT 24
Finished May 23 02:04:36 PM PDT 24
Peak memory 196956 kb
Host smart-37bed37b-f967-492d-9d6a-75d3ef44df78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713559543 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.713559543
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1847554821
Short name T72
Test name
Test status
Simulation time 358892679 ps
CPU time 1.02 seconds
Started May 23 02:04:35 PM PDT 24
Finished May 23 02:04:38 PM PDT 24
Peak memory 193080 kb
Host smart-008aa439-2f60-4605-8116-5a0d82e3594a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847554821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1847554821
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.4107268451
Short name T403
Test name
Test status
Simulation time 439982485 ps
CPU time 1.18 seconds
Started May 23 02:04:37 PM PDT 24
Finished May 23 02:04:39 PM PDT 24
Peak memory 183748 kb
Host smart-772212fa-4e63-4b7c-ac8d-5dc84226e3a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107268451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.4107268451
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.364669011
Short name T419
Test name
Test status
Simulation time 2682749918 ps
CPU time 4.38 seconds
Started May 23 02:04:34 PM PDT 24
Finished May 23 02:04:39 PM PDT 24
Peak memory 194448 kb
Host smart-03770b6e-bb37-44b5-90d4-dedd75cbba56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364669011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.364669011
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1437997998
Short name T362
Test name
Test status
Simulation time 585848532 ps
CPU time 2.01 seconds
Started May 23 02:04:35 PM PDT 24
Finished May 23 02:04:38 PM PDT 24
Peak memory 198632 kb
Host smart-e2829022-4f35-444b-9e59-77456ba074bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437997998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1437997998
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.568458106
Short name T29
Test name
Test status
Simulation time 7969784489 ps
CPU time 12.33 seconds
Started May 23 02:04:38 PM PDT 24
Finished May 23 02:04:51 PM PDT 24
Peak memory 197992 kb
Host smart-d19e77dd-5bdf-4eea-b23d-0c2c4ffc86fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568458106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.568458106
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2533892174
Short name T416
Test name
Test status
Simulation time 544414487 ps
CPU time 1.1 seconds
Started May 23 02:04:45 PM PDT 24
Finished May 23 02:04:47 PM PDT 24
Peak memory 195872 kb
Host smart-2842a153-df29-47ba-a2c7-87be764c2d58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533892174 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2533892174
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3366155742
Short name T53
Test name
Test status
Simulation time 426887991 ps
CPU time 0.86 seconds
Started May 23 02:04:46 PM PDT 24
Finished May 23 02:04:48 PM PDT 24
Peak memory 193140 kb
Host smart-da919a5a-fef9-4608-a1bc-ebfaae32c7bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366155742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3366155742
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.65849108
Short name T359
Test name
Test status
Simulation time 410888355 ps
CPU time 1.14 seconds
Started May 23 02:04:45 PM PDT 24
Finished May 23 02:04:48 PM PDT 24
Peak memory 183720 kb
Host smart-c74e6ad0-cd29-4045-aa53-630dfa0904ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65849108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.65849108
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.188768828
Short name T382
Test name
Test status
Simulation time 1163738783 ps
CPU time 3.36 seconds
Started May 23 02:04:46 PM PDT 24
Finished May 23 02:04:50 PM PDT 24
Peak memory 183728 kb
Host smart-1de6c7cc-1d6f-455b-ad39-eafde05eb913
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188768828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.188768828
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1766079184
Short name T330
Test name
Test status
Simulation time 672699716 ps
CPU time 1.44 seconds
Started May 23 02:04:36 PM PDT 24
Finished May 23 02:04:38 PM PDT 24
Peak memory 198456 kb
Host smart-6e7577db-3d99-47b0-be49-9d74bc112869
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766079184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1766079184
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1167641952
Short name T111
Test name
Test status
Simulation time 8397850012 ps
CPU time 10.62 seconds
Started May 23 02:04:46 PM PDT 24
Finished May 23 02:04:58 PM PDT 24
Peak memory 198084 kb
Host smart-0021423b-6571-440d-849a-16da6cc655c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167641952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1167641952
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.265263360
Short name T355
Test name
Test status
Simulation time 545695867 ps
CPU time 1.18 seconds
Started May 23 02:04:45 PM PDT 24
Finished May 23 02:04:48 PM PDT 24
Peak memory 197224 kb
Host smart-691d3319-2020-4e03-8b35-68df69cc0920
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265263360 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.265263360
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3476239065
Short name T98
Test name
Test status
Simulation time 351023763 ps
CPU time 0.87 seconds
Started May 23 02:04:46 PM PDT 24
Finished May 23 02:04:49 PM PDT 24
Peak memory 183776 kb
Host smart-d7948b31-ef59-40af-bb74-6b65456b41be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476239065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3476239065
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.210278312
Short name T314
Test name
Test status
Simulation time 429946160 ps
CPU time 0.58 seconds
Started May 23 02:04:46 PM PDT 24
Finished May 23 02:04:48 PM PDT 24
Peak memory 183684 kb
Host smart-55f57312-938e-4e15-ba64-fe5e8218cb2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210278312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.210278312
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2371330964
Short name T78
Test name
Test status
Simulation time 1374713681 ps
CPU time 2.32 seconds
Started May 23 02:04:45 PM PDT 24
Finished May 23 02:04:48 PM PDT 24
Peak memory 183828 kb
Host smart-e07bfa89-249b-4098-9c11-54c0b662db36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371330964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2371330964
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1914027322
Short name T304
Test name
Test status
Simulation time 462417994 ps
CPU time 3.07 seconds
Started May 23 02:04:44 PM PDT 24
Finished May 23 02:04:49 PM PDT 24
Peak memory 198712 kb
Host smart-8fb3e298-ca22-44c8-8e29-98bc9c01a4f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914027322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1914027322
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3342802066
Short name T347
Test name
Test status
Simulation time 7852681210 ps
CPU time 4.18 seconds
Started May 23 02:04:44 PM PDT 24
Finished May 23 02:04:49 PM PDT 24
Peak memory 197952 kb
Host smart-0d8d5e68-c405-4bf5-811a-8ecc234296be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342802066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3342802066
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.80952964
Short name T322
Test name
Test status
Simulation time 480089064 ps
CPU time 0.9 seconds
Started May 23 02:04:57 PM PDT 24
Finished May 23 02:04:59 PM PDT 24
Peak memory 197332 kb
Host smart-ec4a7e87-86a2-48e1-b8ef-bdff8d47f1d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80952964 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.80952964
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2324364206
Short name T80
Test name
Test status
Simulation time 413366692 ps
CPU time 1.21 seconds
Started May 23 02:04:58 PM PDT 24
Finished May 23 02:05:01 PM PDT 24
Peak memory 193088 kb
Host smart-cdc72b8a-bd61-4534-bea3-d0900c1a3833
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324364206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2324364206
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.358777489
Short name T360
Test name
Test status
Simulation time 471328318 ps
CPU time 0.76 seconds
Started May 23 02:04:59 PM PDT 24
Finished May 23 02:05:02 PM PDT 24
Peak memory 183736 kb
Host smart-077fe795-6b85-4ca6-a561-cb10264b3eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358777489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.358777489
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4136154120
Short name T338
Test name
Test status
Simulation time 1314234380 ps
CPU time 1.33 seconds
Started May 23 02:04:56 PM PDT 24
Finished May 23 02:04:58 PM PDT 24
Peak memory 183804 kb
Host smart-33ac7611-88c8-481d-a992-8a4bf7c0f099
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136154120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4136154120
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4022093153
Short name T372
Test name
Test status
Simulation time 388960587 ps
CPU time 3.25 seconds
Started May 23 02:04:46 PM PDT 24
Finished May 23 02:04:51 PM PDT 24
Peak memory 198620 kb
Host smart-91ba65c9-1d40-4cba-91e6-3b19a79b8691
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022093153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4022093153
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2889762774
Short name T28
Test name
Test status
Simulation time 4637196670 ps
CPU time 2.43 seconds
Started May 23 02:04:46 PM PDT 24
Finished May 23 02:04:50 PM PDT 24
Peak memory 197672 kb
Host smart-0b40b838-0091-4f28-a5a3-bbc22ca8c531
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889762774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2889762774
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1957333904
Short name T377
Test name
Test status
Simulation time 501984665 ps
CPU time 1.49 seconds
Started May 23 02:04:59 PM PDT 24
Finished May 23 02:05:02 PM PDT 24
Peak memory 196144 kb
Host smart-a5651823-f910-455d-b225-d29206d88da6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957333904 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1957333904
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2851113950
Short name T301
Test name
Test status
Simulation time 525602130 ps
CPU time 1.07 seconds
Started May 23 02:04:58 PM PDT 24
Finished May 23 02:05:01 PM PDT 24
Peak memory 183768 kb
Host smart-3bdd9708-40d5-402a-a4f8-810368bc5229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851113950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2851113950
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1642271600
Short name T286
Test name
Test status
Simulation time 336296271 ps
CPU time 0.66 seconds
Started May 23 02:04:57 PM PDT 24
Finished May 23 02:05:00 PM PDT 24
Peak memory 183728 kb
Host smart-c23845ab-0a83-4a43-8e57-ad7aea4d5cdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642271600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1642271600
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.659986863
Short name T374
Test name
Test status
Simulation time 1819522381 ps
CPU time 5.55 seconds
Started May 23 02:04:58 PM PDT 24
Finished May 23 02:05:06 PM PDT 24
Peak memory 194396 kb
Host smart-c79e13cb-9595-4c56-b979-033a55715acf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659986863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.659986863
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3162257652
Short name T386
Test name
Test status
Simulation time 591340753 ps
CPU time 1.22 seconds
Started May 23 02:04:58 PM PDT 24
Finished May 23 02:05:01 PM PDT 24
Peak memory 198240 kb
Host smart-5dee7bb5-4e8b-4d6d-801a-fb24257654f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162257652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3162257652
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2307814204
Short name T384
Test name
Test status
Simulation time 8667353138 ps
CPU time 14.47 seconds
Started May 23 02:05:00 PM PDT 24
Finished May 23 02:05:16 PM PDT 24
Peak memory 197948 kb
Host smart-fa00604a-186d-4321-98cb-3c5fd61fff2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307814204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2307814204
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2091710288
Short name T217
Test name
Test status
Simulation time 423474543 ps
CPU time 0.74 seconds
Started May 23 03:33:25 PM PDT 24
Finished May 23 03:33:29 PM PDT 24
Peak memory 183588 kb
Host smart-999b22a5-173b-42eb-bdd9-e8a3540fc8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091710288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2091710288
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3011389559
Short name T68
Test name
Test status
Simulation time 940928960 ps
CPU time 1.27 seconds
Started May 23 03:33:20 PM PDT 24
Finished May 23 03:33:23 PM PDT 24
Peak memory 183564 kb
Host smart-6ca39aea-cf88-405c-804c-77a238cc4323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011389559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3011389559
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3633336133
Short name T229
Test name
Test status
Simulation time 502827429 ps
CPU time 0.64 seconds
Started May 23 03:33:23 PM PDT 24
Finished May 23 03:33:27 PM PDT 24
Peak memory 183456 kb
Host smart-c56800a7-6051-47a2-bdbe-2212ae3f6fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633336133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3633336133
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3608991472
Short name T42
Test name
Test status
Simulation time 28569437153 ps
CPU time 11.77 seconds
Started May 23 03:33:22 PM PDT 24
Finished May 23 03:33:37 PM PDT 24
Peak memory 183600 kb
Host smart-a8b98c57-8e45-491e-87e9-ee979d610be8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608991472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3608991472
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2378318774
Short name T161
Test name
Test status
Simulation time 406057280 ps
CPU time 1.15 seconds
Started May 23 03:33:21 PM PDT 24
Finished May 23 03:33:24 PM PDT 24
Peak memory 183568 kb
Host smart-3d65508d-afc1-4bce-b140-979ebfd7a548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378318774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2378318774
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3349408312
Short name T204
Test name
Test status
Simulation time 38421499511 ps
CPU time 8.09 seconds
Started May 23 03:33:21 PM PDT 24
Finished May 23 03:33:32 PM PDT 24
Peak memory 183620 kb
Host smart-ec012e39-7f8f-4d61-90e6-e3797247a1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349408312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3349408312
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2066806882
Short name T19
Test name
Test status
Simulation time 4300635204 ps
CPU time 1.94 seconds
Started May 23 03:33:20 PM PDT 24
Finished May 23 03:33:24 PM PDT 24
Peak memory 215224 kb
Host smart-fdf1cc6c-fd56-4149-8f17-d03ce409ad57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066806882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2066806882
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3318874343
Short name T186
Test name
Test status
Simulation time 403411021 ps
CPU time 0.67 seconds
Started May 23 03:33:22 PM PDT 24
Finished May 23 03:33:25 PM PDT 24
Peak memory 183564 kb
Host smart-d0ee9ea0-b7ab-4c11-95fa-15a3886df4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318874343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3318874343
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.697972825
Short name T5
Test name
Test status
Simulation time 77033571768 ps
CPU time 126.17 seconds
Started May 23 03:33:19 PM PDT 24
Finished May 23 03:35:28 PM PDT 24
Peak memory 183624 kb
Host smart-28691b83-22a2-4956-b1a5-5b908f7f1801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697972825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.697972825
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1012056784
Short name T209
Test name
Test status
Simulation time 410480728 ps
CPU time 0.71 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:33:43 PM PDT 24
Peak memory 183540 kb
Host smart-78d64786-fb92-4a63-bb6c-b80613693ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012056784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1012056784
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2546112064
Short name T264
Test name
Test status
Simulation time 50906882428 ps
CPU time 8.05 seconds
Started May 23 03:33:37 PM PDT 24
Finished May 23 03:33:47 PM PDT 24
Peak memory 183624 kb
Host smart-50b49a07-0875-46f6-a8cd-e7ba1d1cd9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546112064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2546112064
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3730028863
Short name T207
Test name
Test status
Simulation time 580742864 ps
CPU time 1.33 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:33:46 PM PDT 24
Peak memory 183572 kb
Host smart-3b893b06-1b17-4d57-8eaf-bf5830c2ed18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730028863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3730028863
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.427775629
Short name T260
Test name
Test status
Simulation time 91406606398 ps
CPU time 69.94 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:34:55 PM PDT 24
Peak memory 194316 kb
Host smart-cbb2e50b-2b18-4ac6-aef1-15ed5798b97f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427775629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.427775629
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1232050169
Short name T272
Test name
Test status
Simulation time 571372243 ps
CPU time 1.29 seconds
Started May 23 03:33:42 PM PDT 24
Finished May 23 03:33:49 PM PDT 24
Peak memory 183516 kb
Host smart-d0363253-bdf2-4313-b7fb-47568d4143b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232050169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1232050169
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.342251676
Short name T194
Test name
Test status
Simulation time 6459589559 ps
CPU time 2.96 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:33:46 PM PDT 24
Peak memory 183624 kb
Host smart-3322afe8-e8c6-411d-b407-5366e9d0b1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342251676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.342251676
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3453403157
Short name T187
Test name
Test status
Simulation time 549712764 ps
CPU time 1.41 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:33:44 PM PDT 24
Peak memory 183572 kb
Host smart-3431e295-232d-4149-bbe8-ad7cbf0469ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453403157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3453403157
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2376104152
Short name T70
Test name
Test status
Simulation time 117630972633 ps
CPU time 38.67 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:34:23 PM PDT 24
Peak memory 194924 kb
Host smart-6db5b689-58d4-46e3-a962-4a72aed021c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376104152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2376104152
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1009948833
Short name T172
Test name
Test status
Simulation time 170028266859 ps
CPU time 437.21 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:41:02 PM PDT 24
Peak memory 198576 kb
Host smart-d2cad767-25dc-4793-b453-d02e74cbd601
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009948833 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1009948833
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.39804616
Short name T270
Test name
Test status
Simulation time 505006995 ps
CPU time 0.62 seconds
Started May 23 03:33:36 PM PDT 24
Finished May 23 03:33:38 PM PDT 24
Peak memory 183560 kb
Host smart-c640c60a-dc03-48ba-ae83-00eaff56430b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39804616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.39804616
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2481819617
Short name T237
Test name
Test status
Simulation time 7768049401 ps
CPU time 6.84 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:33:50 PM PDT 24
Peak memory 183624 kb
Host smart-743d5322-14ff-40d3-bc25-3174be95293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481819617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2481819617
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3143472441
Short name T253
Test name
Test status
Simulation time 362899745 ps
CPU time 1.13 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:33:45 PM PDT 24
Peak memory 183564 kb
Host smart-0f028f50-be10-4b91-bf9c-f58ce9b1f868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143472441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3143472441
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.4030827050
Short name T184
Test name
Test status
Simulation time 203716978485 ps
CPU time 309.69 seconds
Started May 23 03:33:37 PM PDT 24
Finished May 23 03:38:49 PM PDT 24
Peak memory 193928 kb
Host smart-53504328-3ca9-4538-8a06-ef8240f5da67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030827050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.4030827050
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2052430599
Short name T87
Test name
Test status
Simulation time 113860504185 ps
CPU time 453.9 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:41:19 PM PDT 24
Peak memory 198540 kb
Host smart-5b0cda70-a28a-4b9b-ba0f-860581a86497
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052430599 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2052430599
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.4117424176
Short name T158
Test name
Test status
Simulation time 409283573 ps
CPU time 0.69 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:33:46 PM PDT 24
Peak memory 183360 kb
Host smart-b32b8e85-e0a3-4a34-9b1d-b9bd397bfca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117424176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.4117424176
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1305340054
Short name T281
Test name
Test status
Simulation time 22116230560 ps
CPU time 29.59 seconds
Started May 23 03:33:38 PM PDT 24
Finished May 23 03:34:11 PM PDT 24
Peak memory 183632 kb
Host smart-1e2314b8-3a09-493d-b800-d2872138fe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305340054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1305340054
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1655632054
Short name T140
Test name
Test status
Simulation time 513718316 ps
CPU time 1.29 seconds
Started May 23 03:33:42 PM PDT 24
Finished May 23 03:33:49 PM PDT 24
Peak memory 183532 kb
Host smart-33e77ea5-029d-4fd1-9a2e-e138dbbccdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655632054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1655632054
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1335486165
Short name T71
Test name
Test status
Simulation time 45780049823 ps
CPU time 4.7 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:33:48 PM PDT 24
Peak memory 194112 kb
Host smart-28ad6b8a-2c62-4d08-a858-bce0b0c7d83a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335486165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1335486165
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.765578795
Short name T200
Test name
Test status
Simulation time 551339455 ps
CPU time 0.65 seconds
Started May 23 03:33:38 PM PDT 24
Finished May 23 03:33:42 PM PDT 24
Peak memory 183536 kb
Host smart-58cc6bc3-39d1-4be8-beff-e99dd09ebada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765578795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.765578795
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.557267535
Short name T223
Test name
Test status
Simulation time 45206643103 ps
CPU time 67.29 seconds
Started May 23 03:33:42 PM PDT 24
Finished May 23 03:34:55 PM PDT 24
Peak memory 183592 kb
Host smart-17c9aa78-1049-41a1-af19-ebac909f7366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557267535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.557267535
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.4035790196
Short name T228
Test name
Test status
Simulation time 478808175 ps
CPU time 1.42 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:33:44 PM PDT 24
Peak memory 183564 kb
Host smart-45f6b3b4-25ad-4de1-adf4-6987c8d2af2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035790196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.4035790196
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3889301383
Short name T150
Test name
Test status
Simulation time 72627894270 ps
CPU time 119.48 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:35:43 PM PDT 24
Peak memory 194084 kb
Host smart-2b5960c9-844c-404e-a4af-81fcc6a549f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889301383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3889301383
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3714444765
Short name T147
Test name
Test status
Simulation time 302828353278 ps
CPU time 829.56 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:47:35 PM PDT 24
Peak memory 203664 kb
Host smart-d3702a43-cfc1-4169-a179-bceaf000c713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714444765 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3714444765
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3565655398
Short name T250
Test name
Test status
Simulation time 635336850 ps
CPU time 0.66 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:33:42 PM PDT 24
Peak memory 183568 kb
Host smart-cc74017f-353f-431b-8ef4-b0e0bfa62fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565655398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3565655398
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3124794585
Short name T268
Test name
Test status
Simulation time 2245474196 ps
CPU time 2.13 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:33:48 PM PDT 24
Peak memory 183636 kb
Host smart-e036c620-0a86-4802-bd12-a811573cf128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124794585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3124794585
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.4004348861
Short name T151
Test name
Test status
Simulation time 548154622 ps
CPU time 0.77 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:33:45 PM PDT 24
Peak memory 183532 kb
Host smart-d5f26806-dea6-41a9-ab79-e4f35d86dc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004348861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.4004348861
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3544505583
Short name T273
Test name
Test status
Simulation time 54804970114 ps
CPU time 76.02 seconds
Started May 23 03:33:44 PM PDT 24
Finished May 23 03:35:06 PM PDT 24
Peak memory 183608 kb
Host smart-d0c0abb8-7f70-434d-940e-44cbca36c3d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544505583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3544505583
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.4100186903
Short name T38
Test name
Test status
Simulation time 24766820729 ps
CPU time 178.22 seconds
Started May 23 03:33:37 PM PDT 24
Finished May 23 03:36:38 PM PDT 24
Peak memory 198448 kb
Host smart-1e66a005-28a2-460c-9fc9-ba89be7ccfe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100186903 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.4100186903
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.989041433
Short name T276
Test name
Test status
Simulation time 476422874 ps
CPU time 0.91 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:33:47 PM PDT 24
Peak memory 183564 kb
Host smart-13250986-9565-4921-ba56-e293b7d9ab52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989041433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.989041433
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.26789239
Short name T67
Test name
Test status
Simulation time 9435199661 ps
CPU time 4.07 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:33:48 PM PDT 24
Peak memory 183648 kb
Host smart-7de6348b-d604-4fd8-8435-3f8c9c097c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26789239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.26789239
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3829268622
Short name T44
Test name
Test status
Simulation time 553447456 ps
CPU time 0.76 seconds
Started May 23 03:33:42 PM PDT 24
Finished May 23 03:33:49 PM PDT 24
Peak memory 183532 kb
Host smart-ae2c21dc-33bb-4138-95cc-14edff307da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829268622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3829268622
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2871095466
Short name T63
Test name
Test status
Simulation time 53284345280 ps
CPU time 71.04 seconds
Started May 23 03:33:42 PM PDT 24
Finished May 23 03:34:59 PM PDT 24
Peak memory 194144 kb
Host smart-a77b2efd-ccd1-4490-b873-367ea9946c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871095466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2871095466
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3665684060
Short name T84
Test name
Test status
Simulation time 58093460763 ps
CPU time 602.4 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:43:48 PM PDT 24
Peak memory 198536 kb
Host smart-363f6940-a963-4b18-8f17-579c2e4dd0e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665684060 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3665684060
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1616823461
Short name T149
Test name
Test status
Simulation time 608402950 ps
CPU time 0.72 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:33:47 PM PDT 24
Peak memory 183408 kb
Host smart-394131e4-c82d-45b7-bb95-a1fcca511ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616823461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1616823461
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1130658413
Short name T243
Test name
Test status
Simulation time 6623354299 ps
CPU time 10.48 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:33:56 PM PDT 24
Peak memory 183636 kb
Host smart-7c84ee63-ce89-4aa7-9f01-409459165451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130658413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1130658413
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2982418487
Short name T139
Test name
Test status
Simulation time 425633691 ps
CPU time 1.06 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:33:45 PM PDT 24
Peak memory 183544 kb
Host smart-b155f242-a35d-4ac3-936f-06ca6ed7719e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982418487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2982418487
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1873980042
Short name T142
Test name
Test status
Simulation time 96649769639 ps
CPU time 55.5 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:34:41 PM PDT 24
Peak memory 194336 kb
Host smart-c486d8fb-db93-42bc-bb34-34bd537d7590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873980042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1873980042
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3205839559
Short name T48
Test name
Test status
Simulation time 117852606514 ps
CPU time 453.39 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:41:20 PM PDT 24
Peak memory 198360 kb
Host smart-73ca2d87-2acc-4e93-b1d6-47d0cd818530
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205839559 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3205839559
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2951808406
Short name T118
Test name
Test status
Simulation time 419511916 ps
CPU time 0.78 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:33:46 PM PDT 24
Peak memory 183572 kb
Host smart-f30a6a10-cc68-4923-8e46-42072d4b8b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951808406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2951808406
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3647707666
Short name T91
Test name
Test status
Simulation time 42410834806 ps
CPU time 7.13 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:33:52 PM PDT 24
Peak memory 183604 kb
Host smart-926999c3-1585-4986-bff2-d07dff147710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647707666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3647707666
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1091301913
Short name T168
Test name
Test status
Simulation time 582217668 ps
CPU time 0.97 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:33:48 PM PDT 24
Peak memory 183544 kb
Host smart-50656d21-affb-4656-b4b4-e7fa71633192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091301913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1091301913
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2674778206
Short name T233
Test name
Test status
Simulation time 158623961612 ps
CPU time 19.46 seconds
Started May 23 03:33:36 PM PDT 24
Finished May 23 03:33:58 PM PDT 24
Peak memory 183664 kb
Host smart-b0166fef-f138-47a5-a209-05e514c4056f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674778206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2674778206
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.300371802
Short name T148
Test name
Test status
Simulation time 77404986094 ps
CPU time 157.22 seconds
Started May 23 03:33:42 PM PDT 24
Finished May 23 03:36:25 PM PDT 24
Peak memory 198488 kb
Host smart-a383b2e3-2f86-48f4-bc37-3af900c25413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300371802 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.300371802
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.4048389109
Short name T45
Test name
Test status
Simulation time 466630829 ps
CPU time 1.16 seconds
Started May 23 03:33:38 PM PDT 24
Finished May 23 03:33:42 PM PDT 24
Peak memory 183552 kb
Host smart-f0e4f699-1ca9-4a89-8997-f78368e98a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048389109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.4048389109
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3066791921
Short name T43
Test name
Test status
Simulation time 22558278503 ps
CPU time 8.92 seconds
Started May 23 03:33:34 PM PDT 24
Finished May 23 03:33:44 PM PDT 24
Peak memory 183604 kb
Host smart-b4221926-facf-4368-b45b-dd3e6de8c826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066791921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3066791921
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1008535714
Short name T171
Test name
Test status
Simulation time 413571458 ps
CPU time 0.67 seconds
Started May 23 03:33:38 PM PDT 24
Finished May 23 03:33:41 PM PDT 24
Peak memory 183560 kb
Host smart-1abd25bc-e308-4f5e-917f-b5c851fca9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008535714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1008535714
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3652810842
Short name T240
Test name
Test status
Simulation time 92112234689 ps
CPU time 29.56 seconds
Started May 23 03:33:44 PM PDT 24
Finished May 23 03:34:20 PM PDT 24
Peak memory 183608 kb
Host smart-2e113da4-5326-4e48-8cbd-146088e264a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652810842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3652810842
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2570700869
Short name T85
Test name
Test status
Simulation time 51231840446 ps
CPU time 374.8 seconds
Started May 23 03:33:37 PM PDT 24
Finished May 23 03:39:54 PM PDT 24
Peak memory 198604 kb
Host smart-c0646937-1ca6-4c3a-8790-0d19427d51e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570700869 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2570700869
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1546577956
Short name T141
Test name
Test status
Simulation time 592760251 ps
CPU time 1.48 seconds
Started May 23 03:33:21 PM PDT 24
Finished May 23 03:33:25 PM PDT 24
Peak memory 183568 kb
Host smart-87d7180c-7dcf-4f11-baa1-9ff28b38020c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546577956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1546577956
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2873600122
Short name T278
Test name
Test status
Simulation time 34606496957 ps
CPU time 52.22 seconds
Started May 23 03:33:23 PM PDT 24
Finished May 23 03:34:18 PM PDT 24
Peak memory 191868 kb
Host smart-b5c949a5-56e5-4394-bb12-c3599eabef13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873600122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2873600122
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.163915056
Short name T18
Test name
Test status
Simulation time 4315983699 ps
CPU time 4.37 seconds
Started May 23 03:33:21 PM PDT 24
Finished May 23 03:33:28 PM PDT 24
Peak memory 215588 kb
Host smart-bec8cc82-ecb4-49f3-90de-29d553765a47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163915056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.163915056
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3824462283
Short name T94
Test name
Test status
Simulation time 452067551 ps
CPU time 0.93 seconds
Started May 23 03:33:21 PM PDT 24
Finished May 23 03:33:24 PM PDT 24
Peak memory 183608 kb
Host smart-66d048c4-a171-4247-ab5f-247487d12a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824462283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3824462283
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3031874548
Short name T145
Test name
Test status
Simulation time 233865950980 ps
CPU time 337.97 seconds
Started May 23 03:33:20 PM PDT 24
Finished May 23 03:39:00 PM PDT 24
Peak memory 183640 kb
Host smart-cb3d0ac4-c4fc-4866-8a09-e6ad3bef1cd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031874548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3031874548
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2675266780
Short name T241
Test name
Test status
Simulation time 8537896503 ps
CPU time 66.65 seconds
Started May 23 03:33:19 PM PDT 24
Finished May 23 03:34:27 PM PDT 24
Peak memory 198504 kb
Host smart-273d023c-b53b-4278-ab1a-0a1ef6f79cdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675266780 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2675266780
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1939091977
Short name T155
Test name
Test status
Simulation time 412559647 ps
CPU time 1.15 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:33:46 PM PDT 24
Peak memory 183556 kb
Host smart-0da90d4b-f3c2-4bc1-adfc-31dd2d9e14ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939091977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1939091977
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3872580785
Short name T208
Test name
Test status
Simulation time 56784378909 ps
CPU time 81.83 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:35:07 PM PDT 24
Peak memory 191648 kb
Host smart-26c4dd6f-aa8c-4b0e-840c-b6812e26e477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872580785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3872580785
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.881635618
Short name T96
Test name
Test status
Simulation time 416227061 ps
CPU time 1.21 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:33:46 PM PDT 24
Peak memory 183560 kb
Host smart-c632db44-88ed-4267-99f7-16daecb5554e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881635618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.881635618
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.387671467
Short name T109
Test name
Test status
Simulation time 174604219292 ps
CPU time 278.59 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:38:24 PM PDT 24
Peak memory 183608 kb
Host smart-064e381f-e84d-4ea3-9464-dcc3c91c7777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387671467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.387671467
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2335677435
Short name T246
Test name
Test status
Simulation time 471244407 ps
CPU time 0.69 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:33:46 PM PDT 24
Peak memory 183536 kb
Host smart-87fa3ff0-021b-4867-af2b-62f731732e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335677435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2335677435
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.381673104
Short name T95
Test name
Test status
Simulation time 20835408642 ps
CPU time 29.24 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:34:14 PM PDT 24
Peak memory 183600 kb
Host smart-93418cfb-f392-4434-9fef-2a95bdf881be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381673104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.381673104
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1189276960
Short name T169
Test name
Test status
Simulation time 512516174 ps
CPU time 0.65 seconds
Started May 23 03:33:36 PM PDT 24
Finished May 23 03:33:39 PM PDT 24
Peak memory 183568 kb
Host smart-1fb3199f-5a49-4113-a123-086008e9e189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189276960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1189276960
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.288727888
Short name T190
Test name
Test status
Simulation time 378876031074 ps
CPU time 558.4 seconds
Started May 23 03:33:45 PM PDT 24
Finished May 23 03:43:09 PM PDT 24
Peak memory 183704 kb
Host smart-110813a8-9c0e-4a07-ad59-e8ad7e802c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288727888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.288727888
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.4294820837
Short name T30
Test name
Test status
Simulation time 34588622063 ps
CPU time 152.94 seconds
Started May 23 03:33:45 PM PDT 24
Finished May 23 03:36:24 PM PDT 24
Peak memory 198488 kb
Host smart-d86a5bad-4da6-4dee-aea9-98758b9eef3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294820837 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.4294820837
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.830028560
Short name T198
Test name
Test status
Simulation time 405357616 ps
CPU time 1.23 seconds
Started May 23 03:33:45 PM PDT 24
Finished May 23 03:33:52 PM PDT 24
Peak memory 183540 kb
Host smart-79cdd0b0-6c93-41a9-b701-e7040794640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830028560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.830028560
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2109211085
Short name T192
Test name
Test status
Simulation time 1572664680 ps
CPU time 2.73 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:33:47 PM PDT 24
Peak memory 183540 kb
Host smart-0fd3e35c-4a05-4f98-a27c-d14c64037165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109211085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2109211085
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.455457948
Short name T66
Test name
Test status
Simulation time 377561014 ps
CPU time 1.02 seconds
Started May 23 03:33:44 PM PDT 24
Finished May 23 03:33:52 PM PDT 24
Peak memory 183548 kb
Host smart-03e278a8-1d66-4f3f-86f5-dd2a2ef41ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455457948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.455457948
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1560652379
Short name T185
Test name
Test status
Simulation time 166426798414 ps
CPU time 237.82 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:37:42 PM PDT 24
Peak memory 195080 kb
Host smart-6acae9df-ee42-4045-b24b-a648ecae1cd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560652379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1560652379
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.4277107753
Short name T159
Test name
Test status
Simulation time 51249696541 ps
CPU time 203.95 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:37:08 PM PDT 24
Peak memory 198540 kb
Host smart-ba862215-4653-4786-bab3-b24e83ab9c32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277107753 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.4277107753
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.807332569
Short name T69
Test name
Test status
Simulation time 518053906 ps
CPU time 0.61 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:33:42 PM PDT 24
Peak memory 183228 kb
Host smart-fd6d7686-df1d-4923-a539-228425fb54ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807332569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.807332569
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.703554933
Short name T154
Test name
Test status
Simulation time 47079398607 ps
CPU time 66.12 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:34:51 PM PDT 24
Peak memory 183600 kb
Host smart-a8204e01-192e-4d8b-9a3e-00ed8ef797a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703554933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.703554933
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3001430592
Short name T8
Test name
Test status
Simulation time 377946082 ps
CPU time 0.85 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:33:44 PM PDT 24
Peak memory 183564 kb
Host smart-0ae4618f-7a55-4009-8234-a61723667d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001430592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3001430592
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2280126398
Short name T254
Test name
Test status
Simulation time 104661753317 ps
CPU time 157.99 seconds
Started May 23 03:33:45 PM PDT 24
Finished May 23 03:36:29 PM PDT 24
Peak memory 194088 kb
Host smart-7ea1d613-cff9-4943-b679-b8f97cf37a0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280126398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2280126398
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.75952435
Short name T31
Test name
Test status
Simulation time 19082323986 ps
CPU time 193.82 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:36:56 PM PDT 24
Peak memory 198124 kb
Host smart-aad4a46d-1071-4e19-bbee-e47269fa8258
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75952435 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.75952435
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.298397482
Short name T201
Test name
Test status
Simulation time 478323943 ps
CPU time 0.7 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:08 PM PDT 24
Peak memory 183536 kb
Host smart-a9d6ff6c-da85-4526-b1d8-7e3693ccd99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298397482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.298397482
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2128156163
Short name T195
Test name
Test status
Simulation time 25138568024 ps
CPU time 20.08 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:34:20 PM PDT 24
Peak memory 183596 kb
Host smart-805da802-fa62-4641-9844-24c021611c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128156163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2128156163
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2974434917
Short name T215
Test name
Test status
Simulation time 380400468 ps
CPU time 0.6 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:34:00 PM PDT 24
Peak memory 183536 kb
Host smart-62cc8db8-a61c-4152-bdbc-21c61e803388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974434917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2974434917
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2996929346
Short name T104
Test name
Test status
Simulation time 141598312296 ps
CPU time 63.31 seconds
Started May 23 03:34:02 PM PDT 24
Finished May 23 03:35:12 PM PDT 24
Peak memory 195456 kb
Host smart-1683eed0-67b6-46bd-b07f-1270c5e3e2e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996929346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2996929346
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1295949173
Short name T262
Test name
Test status
Simulation time 629231576 ps
CPU time 0.78 seconds
Started May 23 03:33:59 PM PDT 24
Finished May 23 03:34:06 PM PDT 24
Peak memory 183528 kb
Host smart-47071ef7-f68f-41dd-a8c0-8f2544b9af73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295949173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1295949173
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2232486271
Short name T211
Test name
Test status
Simulation time 30363068566 ps
CPU time 44.52 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:52 PM PDT 24
Peak memory 183604 kb
Host smart-a55190f4-f595-429b-9706-68fb907ef02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232486271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2232486271
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4036442432
Short name T162
Test name
Test status
Simulation time 387773993 ps
CPU time 0.85 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:34:00 PM PDT 24
Peak memory 183544 kb
Host smart-528ac6c3-bd2b-46d3-a2e8-435abe677d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036442432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4036442432
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3592593909
Short name T163
Test name
Test status
Simulation time 125844804409 ps
CPU time 209.06 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:37:35 PM PDT 24
Peak memory 194140 kb
Host smart-718ce7fc-1c7e-46d7-bd21-ab66353444af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592593909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3592593909
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.4067976463
Short name T269
Test name
Test status
Simulation time 23593989777 ps
CPU time 250.13 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:38:18 PM PDT 24
Peak memory 198504 kb
Host smart-0f3fee6d-af7b-4881-b126-b59e36f6b429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067976463 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.4067976463
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2380312914
Short name T193
Test name
Test status
Simulation time 589569856 ps
CPU time 0.72 seconds
Started May 23 03:33:59 PM PDT 24
Finished May 23 03:34:06 PM PDT 24
Peak memory 183564 kb
Host smart-9cfc3260-7516-46e1-ad41-f0e2919077a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380312914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2380312914
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2668568506
Short name T153
Test name
Test status
Simulation time 29398128881 ps
CPU time 27.91 seconds
Started May 23 03:33:55 PM PDT 24
Finished May 23 03:34:25 PM PDT 24
Peak memory 191808 kb
Host smart-91c942fd-3895-408a-a47d-9714039442de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668568506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2668568506
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1329143982
Short name T226
Test name
Test status
Simulation time 472195278 ps
CPU time 1.31 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:09 PM PDT 24
Peak memory 183544 kb
Host smart-6437c1de-246f-4888-87fc-87de833e1143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329143982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1329143982
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3719235609
Short name T196
Test name
Test status
Simulation time 91520366365 ps
CPU time 135.99 seconds
Started May 23 03:33:58 PM PDT 24
Finished May 23 03:36:18 PM PDT 24
Peak memory 194352 kb
Host smart-202118a1-eb6e-4629-89dc-c6db85cf121b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719235609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3719235609
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3714410967
Short name T33
Test name
Test status
Simulation time 40611068564 ps
CPU time 353.43 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:39:53 PM PDT 24
Peak memory 198572 kb
Host smart-a4287532-ae41-44b7-a97a-0d71519f4d03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714410967 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3714410967
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.66843167
Short name T144
Test name
Test status
Simulation time 459150687 ps
CPU time 0.72 seconds
Started May 23 03:34:03 PM PDT 24
Finished May 23 03:34:11 PM PDT 24
Peak memory 183560 kb
Host smart-360b9793-939d-4afc-96d7-ed9f9f2b0a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66843167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.66843167
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1225543009
Short name T116
Test name
Test status
Simulation time 33075685188 ps
CPU time 6.23 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:34:13 PM PDT 24
Peak memory 183584 kb
Host smart-0e6f64a8-0cf0-4400-876d-f94cbf27bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225543009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1225543009
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2278350363
Short name T46
Test name
Test status
Simulation time 365746014 ps
CPU time 1.11 seconds
Started May 23 03:34:02 PM PDT 24
Finished May 23 03:34:10 PM PDT 24
Peak memory 183544 kb
Host smart-220ea129-9c38-4e99-b074-4d2c914017e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278350363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2278350363
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2851665793
Short name T258
Test name
Test status
Simulation time 131529727271 ps
CPU time 34.13 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:41 PM PDT 24
Peak memory 193772 kb
Host smart-d8f93be6-6fd9-4397-b9c5-20bf544133fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851665793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2851665793
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1036115333
Short name T167
Test name
Test status
Simulation time 70668306087 ps
CPU time 195.43 seconds
Started May 23 03:33:58 PM PDT 24
Finished May 23 03:37:18 PM PDT 24
Peak memory 198584 kb
Host smart-e22cc84b-efcd-486b-90e4-7386d1d434e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036115333 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1036115333
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.4124335853
Short name T115
Test name
Test status
Simulation time 425126765 ps
CPU time 0.62 seconds
Started May 23 03:33:58 PM PDT 24
Finished May 23 03:34:03 PM PDT 24
Peak memory 183556 kb
Host smart-6982dbaa-2635-480a-a3e0-d219371ac540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124335853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.4124335853
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.781917412
Short name T97
Test name
Test status
Simulation time 12132182185 ps
CPU time 5.85 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:34:05 PM PDT 24
Peak memory 183624 kb
Host smart-0de99f00-799a-49af-be84-a3ea29b8b528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781917412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.781917412
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1136595899
Short name T119
Test name
Test status
Simulation time 549245565 ps
CPU time 0.84 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:08 PM PDT 24
Peak memory 183556 kb
Host smart-067b9a2e-90f1-46e9-a7d8-8326c02292db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136595899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1136595899
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1246479962
Short name T188
Test name
Test status
Simulation time 41843309512 ps
CPU time 13.74 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:34:20 PM PDT 24
Peak memory 193832 kb
Host smart-d0687ee1-1365-4189-bc12-c2be1f355dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246479962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1246479962
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.898829450
Short name T222
Test name
Test status
Simulation time 24668975692 ps
CPU time 275.71 seconds
Started May 23 03:33:58 PM PDT 24
Finished May 23 03:38:38 PM PDT 24
Peak memory 198552 kb
Host smart-b7760346-ae3d-468e-9692-d82d2675b6b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898829450 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.898829450
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1082724091
Short name T242
Test name
Test status
Simulation time 432701484 ps
CPU time 0.72 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:34:01 PM PDT 24
Peak memory 183540 kb
Host smart-b40df9fd-2e88-42ea-b1fa-43bb0fe02f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082724091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1082724091
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.639338172
Short name T132
Test name
Test status
Simulation time 32542683428 ps
CPU time 13.06 seconds
Started May 23 03:33:59 PM PDT 24
Finished May 23 03:34:19 PM PDT 24
Peak memory 183628 kb
Host smart-71938886-89e2-4ff9-a3cd-eca02c5de3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639338172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.639338172
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2566752923
Short name T210
Test name
Test status
Simulation time 379236368 ps
CPU time 0.82 seconds
Started May 23 03:34:03 PM PDT 24
Finished May 23 03:34:11 PM PDT 24
Peak memory 183556 kb
Host smart-57bc2e29-154b-4fe0-88a2-7c888852076c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566752923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2566752923
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2110688398
Short name T106
Test name
Test status
Simulation time 160899973301 ps
CPU time 258.11 seconds
Started May 23 03:33:59 PM PDT 24
Finished May 23 03:38:23 PM PDT 24
Peak memory 194820 kb
Host smart-687a3bea-9fda-4cef-b713-a0222fcf52d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110688398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2110688398
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.980050675
Short name T191
Test name
Test status
Simulation time 54821192829 ps
CPU time 442.31 seconds
Started May 23 03:33:56 PM PDT 24
Finished May 23 03:41:21 PM PDT 24
Peak memory 198528 kb
Host smart-ec567c35-f5d1-4db8-81ad-4b482218f87c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980050675 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.980050675
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.68644460
Short name T225
Test name
Test status
Simulation time 580095314 ps
CPU time 0.99 seconds
Started May 23 03:33:22 PM PDT 24
Finished May 23 03:33:25 PM PDT 24
Peak memory 183548 kb
Host smart-53d0ca75-4944-4e52-aa70-a6fc023c77e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68644460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.68644460
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.404949117
Short name T131
Test name
Test status
Simulation time 21648164005 ps
CPU time 18.45 seconds
Started May 23 03:33:20 PM PDT 24
Finished May 23 03:33:41 PM PDT 24
Peak memory 183628 kb
Host smart-bbcec7b3-688c-45eb-a6f8-63b7aeb1e42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404949117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.404949117
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1903105052
Short name T11
Test name
Test status
Simulation time 8244983055 ps
CPU time 3.78 seconds
Started May 23 03:33:20 PM PDT 24
Finished May 23 03:33:26 PM PDT 24
Peak memory 215256 kb
Host smart-f59d46f3-faf6-4b78-a0ce-a9b39dd35e85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903105052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1903105052
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3619407707
Short name T9
Test name
Test status
Simulation time 471626857 ps
CPU time 0.69 seconds
Started May 23 03:33:21 PM PDT 24
Finished May 23 03:33:23 PM PDT 24
Peak memory 183612 kb
Host smart-3eb27e38-9812-4848-af84-3841904922bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619407707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3619407707
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2871963050
Short name T133
Test name
Test status
Simulation time 116974640959 ps
CPU time 48.95 seconds
Started May 23 03:33:20 PM PDT 24
Finished May 23 03:34:12 PM PDT 24
Peak memory 194136 kb
Host smart-5a20d4c5-be4f-4b9f-95ac-08bee79f2daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871963050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2871963050
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3498002456
Short name T134
Test name
Test status
Simulation time 565282303 ps
CPU time 0.78 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:34:06 PM PDT 24
Peak memory 183568 kb
Host smart-17590493-297d-46d1-878f-b4f444096cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498002456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3498002456
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1551345655
Short name T266
Test name
Test status
Simulation time 56892276990 ps
CPU time 23.73 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:31 PM PDT 24
Peak memory 183616 kb
Host smart-65f871f7-b2b6-4bc5-9ff0-33b2556cb234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551345655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1551345655
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3735726422
Short name T39
Test name
Test status
Simulation time 407608991 ps
CPU time 1.22 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:34:01 PM PDT 24
Peak memory 183564 kb
Host smart-2498ec9f-448f-43cd-99fd-4b4309b42b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735726422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3735726422
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3519731890
Short name T160
Test name
Test status
Simulation time 339874710967 ps
CPU time 603.3 seconds
Started May 23 03:33:58 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 183616 kb
Host smart-b9bebc0b-f960-4625-bd6c-c639c002ff21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519731890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3519731890
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2173096443
Short name T83
Test name
Test status
Simulation time 450432799286 ps
CPU time 588.62 seconds
Started May 23 03:33:55 PM PDT 24
Finished May 23 03:43:45 PM PDT 24
Peak memory 199880 kb
Host smart-f98819e6-c1e3-47ba-b359-a6b07430bebd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173096443 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2173096443
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2432274391
Short name T122
Test name
Test status
Simulation time 460663338 ps
CPU time 1.04 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:34:08 PM PDT 24
Peak memory 183564 kb
Host smart-dd6de1c3-2e01-455f-900b-3af0a7dc22bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432274391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2432274391
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1970792104
Short name T14
Test name
Test status
Simulation time 20323601253 ps
CPU time 7.52 seconds
Started May 23 03:33:58 PM PDT 24
Finished May 23 03:34:10 PM PDT 24
Peak memory 183624 kb
Host smart-b9e456d5-1119-41e1-8970-e1f23391e9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970792104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1970792104
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1621075878
Short name T177
Test name
Test status
Simulation time 364763431 ps
CPU time 0.68 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:08 PM PDT 24
Peak memory 183524 kb
Host smart-eb2d272b-c12b-40fe-949c-44753b51628a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621075878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1621075878
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1032621738
Short name T206
Test name
Test status
Simulation time 51269432929 ps
CPU time 85.2 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:35:25 PM PDT 24
Peak memory 194124 kb
Host smart-0f47b4f4-6546-4167-b353-288e8f7dad26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032621738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1032621738
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2517968988
Short name T138
Test name
Test status
Simulation time 20266762600 ps
CPU time 168.78 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:36:56 PM PDT 24
Peak memory 198492 kb
Host smart-d68643a6-8eac-439f-8211-0df6757f1901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517968988 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2517968988
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.865906167
Short name T173
Test name
Test status
Simulation time 404763715 ps
CPU time 0.65 seconds
Started May 23 03:33:54 PM PDT 24
Finished May 23 03:33:57 PM PDT 24
Peak memory 183596 kb
Host smart-f994f2b5-0e10-4cc5-abb8-3570b8f4dd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865906167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.865906167
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2219125328
Short name T248
Test name
Test status
Simulation time 2514677330 ps
CPU time 4.38 seconds
Started May 23 03:33:59 PM PDT 24
Finished May 23 03:34:10 PM PDT 24
Peak memory 183620 kb
Host smart-a6b629db-9d8d-461d-bbef-5fcdb0f4cdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219125328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2219125328
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1744255358
Short name T176
Test name
Test status
Simulation time 535547797 ps
CPU time 0.94 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:08 PM PDT 24
Peak memory 183508 kb
Host smart-24b668cb-600f-4e00-b65c-5fa86d7f61fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744255358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1744255358
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.939688716
Short name T152
Test name
Test status
Simulation time 189466749790 ps
CPU time 302.77 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:39:09 PM PDT 24
Peak memory 194140 kb
Host smart-e2b0dcf8-1292-4855-ac9c-75b74f1844aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939688716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.939688716
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.239539977
Short name T47
Test name
Test status
Simulation time 589231042 ps
CPU time 1.5 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:09 PM PDT 24
Peak memory 183500 kb
Host smart-88c9db47-9b9e-4ab1-9ccc-6869035ef606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239539977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.239539977
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3555580975
Short name T12
Test name
Test status
Simulation time 40688336937 ps
CPU time 57.67 seconds
Started May 23 03:34:02 PM PDT 24
Finished May 23 03:35:06 PM PDT 24
Peak memory 191824 kb
Host smart-34ef1580-143c-4612-8b35-68f73ff4bdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555580975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3555580975
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3196169111
Short name T165
Test name
Test status
Simulation time 426151138 ps
CPU time 1.24 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:34:09 PM PDT 24
Peak memory 183508 kb
Host smart-77907883-9e82-4f08-badf-6fd30ae6018a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196169111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3196169111
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2763610436
Short name T267
Test name
Test status
Simulation time 121688234054 ps
CPU time 31.25 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:39 PM PDT 24
Peak memory 194776 kb
Host smart-3989a7fc-99a1-4549-9169-547a8f88d23a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763610436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2763610436
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.103683845
Short name T205
Test name
Test status
Simulation time 353905705 ps
CPU time 1.12 seconds
Started May 23 03:33:56 PM PDT 24
Finished May 23 03:33:59 PM PDT 24
Peak memory 183568 kb
Host smart-835308aa-c842-4339-bdde-7e3b6068a58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103683845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.103683845
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2438487360
Short name T265
Test name
Test status
Simulation time 13819519606 ps
CPU time 4.47 seconds
Started May 23 03:33:59 PM PDT 24
Finished May 23 03:34:10 PM PDT 24
Peak memory 183668 kb
Host smart-7daca1a5-0446-45e1-9399-d0d80e25adeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438487360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2438487360
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3477354241
Short name T143
Test name
Test status
Simulation time 506842396 ps
CPU time 0.89 seconds
Started May 23 03:33:56 PM PDT 24
Finished May 23 03:33:59 PM PDT 24
Peak memory 183572 kb
Host smart-a8ca622a-9dc4-4451-b292-3529c370229c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477354241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3477354241
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1487538303
Short name T227
Test name
Test status
Simulation time 170630364063 ps
CPU time 220.28 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:37:48 PM PDT 24
Peak memory 195052 kb
Host smart-b72c0769-7992-4452-8449-58041aa874d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487538303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1487538303
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.160808775
Short name T49
Test name
Test status
Simulation time 32312677349 ps
CPU time 222.35 seconds
Started May 23 03:34:02 PM PDT 24
Finished May 23 03:37:52 PM PDT 24
Peak memory 198576 kb
Host smart-6782e999-1874-4a68-94af-c4f9113f6059
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160808775 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.160808775
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1325292937
Short name T36
Test name
Test status
Simulation time 526629461 ps
CPU time 0.91 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:34:00 PM PDT 24
Peak memory 183540 kb
Host smart-2076e877-9f7f-4424-93c3-57f12aac7932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325292937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1325292937
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1786836359
Short name T99
Test name
Test status
Simulation time 4300741258 ps
CPU time 2.13 seconds
Started May 23 03:33:58 PM PDT 24
Finished May 23 03:34:05 PM PDT 24
Peak memory 183676 kb
Host smart-ba07fe70-0c14-4ef3-bcd9-da8aa75ee834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786836359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1786836359
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1282064781
Short name T126
Test name
Test status
Simulation time 380379894 ps
CPU time 0.82 seconds
Started May 23 03:33:55 PM PDT 24
Finished May 23 03:33:58 PM PDT 24
Peak memory 183564 kb
Host smart-02f25c83-62f0-4b1d-8dad-07b4b86c5665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282064781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1282064781
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2780366988
Short name T100
Test name
Test status
Simulation time 57085555318 ps
CPU time 4.76 seconds
Started May 23 03:33:56 PM PDT 24
Finished May 23 03:34:03 PM PDT 24
Peak memory 183636 kb
Host smart-ff524c19-687b-4e46-a95c-8f2b2d0d8df4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780366988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2780366988
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3772453055
Short name T175
Test name
Test status
Simulation time 19473026660 ps
CPU time 214.38 seconds
Started May 23 03:33:56 PM PDT 24
Finished May 23 03:37:32 PM PDT 24
Peak memory 198564 kb
Host smart-64611bb2-9783-4773-ad56-d0a8b8e91ba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772453055 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3772453055
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1705576102
Short name T127
Test name
Test status
Simulation time 573874137 ps
CPU time 0.76 seconds
Started May 23 03:33:58 PM PDT 24
Finished May 23 03:34:05 PM PDT 24
Peak memory 183608 kb
Host smart-b762dac9-fb36-440c-ad32-c88f74f37b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705576102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1705576102
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1905607516
Short name T93
Test name
Test status
Simulation time 921630357 ps
CPU time 1.21 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:34:01 PM PDT 24
Peak memory 183528 kb
Host smart-0a5cf8c1-2dba-411e-b411-3948fd4261ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905607516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1905607516
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1207354042
Short name T231
Test name
Test status
Simulation time 371224448 ps
CPU time 0.66 seconds
Started May 23 03:34:02 PM PDT 24
Finished May 23 03:34:10 PM PDT 24
Peak memory 183564 kb
Host smart-db309f39-2cfa-459f-8b18-007c2d0ae4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207354042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1207354042
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3781029633
Short name T86
Test name
Test status
Simulation time 40865003742 ps
CPU time 299.23 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:39:06 PM PDT 24
Peak memory 198512 kb
Host smart-9a0cbdd3-3cf4-43c7-b1d7-34b7b715057a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781029633 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3781029633
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3804319396
Short name T130
Test name
Test status
Simulation time 582509977 ps
CPU time 0.73 seconds
Started May 23 03:33:58 PM PDT 24
Finished May 23 03:34:03 PM PDT 24
Peak memory 183536 kb
Host smart-e267c37a-7442-409f-b01f-9f3f8527111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804319396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3804319396
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2174923484
Short name T156
Test name
Test status
Simulation time 28171144038 ps
CPU time 46.33 seconds
Started May 23 03:33:56 PM PDT 24
Finished May 23 03:34:46 PM PDT 24
Peak memory 191792 kb
Host smart-0be78a07-8f04-451e-bb48-bfd6ccf647ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174923484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2174923484
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2338076679
Short name T214
Test name
Test status
Simulation time 408002762 ps
CPU time 1.12 seconds
Started May 23 03:33:56 PM PDT 24
Finished May 23 03:33:59 PM PDT 24
Peak memory 183568 kb
Host smart-1ebf65bd-54b5-473e-a001-6b2723939b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338076679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2338076679
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1124824470
Short name T92
Test name
Test status
Simulation time 80209216919 ps
CPU time 124.65 seconds
Started May 23 03:33:58 PM PDT 24
Finished May 23 03:36:07 PM PDT 24
Peak memory 194504 kb
Host smart-3fa7f75a-98f9-4134-801c-65ef6b50dbb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124824470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1124824470
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.562489080
Short name T4
Test name
Test status
Simulation time 262459893180 ps
CPU time 528.9 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:42:48 PM PDT 24
Peak memory 198744 kb
Host smart-b054e03f-ca4c-4c1c-be73-bcf0a1824d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562489080 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.562489080
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1713443602
Short name T213
Test name
Test status
Simulation time 382974614 ps
CPU time 0.67 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:08 PM PDT 24
Peak memory 183552 kb
Host smart-22fb32b5-92cd-4c8f-bb61-8f9360f32a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713443602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1713443602
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.131877578
Short name T136
Test name
Test status
Simulation time 30836353954 ps
CPU time 6.35 seconds
Started May 23 03:34:03 PM PDT 24
Finished May 23 03:34:16 PM PDT 24
Peak memory 191824 kb
Host smart-dd802fbb-0a11-442f-9283-25ba025e2e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131877578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.131877578
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1923650527
Short name T26
Test name
Test status
Simulation time 541237189 ps
CPU time 0.78 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:08 PM PDT 24
Peak memory 183508 kb
Host smart-c9e1abf9-122e-4c8e-8ef1-c85ce009fde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923650527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1923650527
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3090656344
Short name T20
Test name
Test status
Simulation time 20314412591 ps
CPU time 8.35 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:16 PM PDT 24
Peak memory 194784 kb
Host smart-8dd7bed2-4909-4cb8-b067-b58bcadb4627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090656344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3090656344
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2455999950
Short name T274
Test name
Test status
Simulation time 52690331856 ps
CPU time 136.74 seconds
Started May 23 03:34:03 PM PDT 24
Finished May 23 03:36:26 PM PDT 24
Peak memory 198512 kb
Host smart-3f1b7f25-ce71-494e-a082-439df0f903b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455999950 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2455999950
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.49595088
Short name T199
Test name
Test status
Simulation time 358943345 ps
CPU time 0.67 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:34:15 PM PDT 24
Peak memory 183524 kb
Host smart-2f0531a3-b7db-4fdc-b067-d015a526b400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49595088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.49595088
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.4173550809
Short name T107
Test name
Test status
Simulation time 26465035611 ps
CPU time 10.9 seconds
Started May 23 03:34:02 PM PDT 24
Finished May 23 03:34:20 PM PDT 24
Peak memory 191824 kb
Host smart-1d35e537-9217-4e71-8fc2-e3000710b32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173550809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.4173550809
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3236324591
Short name T219
Test name
Test status
Simulation time 443926538 ps
CPU time 1.34 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:34:03 PM PDT 24
Peak memory 183532 kb
Host smart-f1e247ca-64a7-4ea5-a096-d959b3792f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236324591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3236324591
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2439920949
Short name T81
Test name
Test status
Simulation time 146972470945 ps
CPU time 444.08 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:41:31 PM PDT 24
Peak memory 198536 kb
Host smart-83656e9c-9c7d-4267-a098-c4114da28bbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439920949 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2439920949
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.4062671858
Short name T256
Test name
Test status
Simulation time 592750728 ps
CPU time 1.37 seconds
Started May 23 03:33:38 PM PDT 24
Finished May 23 03:33:43 PM PDT 24
Peak memory 183544 kb
Host smart-e60b44b9-8d48-4242-a896-3a591727da79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062671858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.4062671858
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.101044274
Short name T263
Test name
Test status
Simulation time 39960955828 ps
CPU time 25.8 seconds
Started May 23 03:33:18 PM PDT 24
Finished May 23 03:33:45 PM PDT 24
Peak memory 183636 kb
Host smart-36245b45-75f7-4736-a28e-790624e117e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101044274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.101044274
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.54267656
Short name T16
Test name
Test status
Simulation time 4141871583 ps
CPU time 3.42 seconds
Started May 23 03:33:34 PM PDT 24
Finished May 23 03:33:38 PM PDT 24
Peak memory 214924 kb
Host smart-ec96a6cb-5fee-4994-9762-4e50f50a54fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54267656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.54267656
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.421394692
Short name T41
Test name
Test status
Simulation time 591489072 ps
CPU time 1.45 seconds
Started May 23 03:33:22 PM PDT 24
Finished May 23 03:33:26 PM PDT 24
Peak memory 183452 kb
Host smart-f94da246-8ee5-4156-9a2a-5065dcaabdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421394692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.421394692
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2219210498
Short name T252
Test name
Test status
Simulation time 83241496257 ps
CPU time 31.54 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:34:14 PM PDT 24
Peak memory 183640 kb
Host smart-39c6a1fa-5fdf-427f-b28f-cce319918b3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219210498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2219210498
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1160697214
Short name T88
Test name
Test status
Simulation time 26790896662 ps
CPU time 172.59 seconds
Started May 23 03:33:35 PM PDT 24
Finished May 23 03:36:29 PM PDT 24
Peak memory 198572 kb
Host smart-216d1756-ff08-4c0f-b528-4c3bab0588a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160697214 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1160697214
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3696955152
Short name T212
Test name
Test status
Simulation time 541389993 ps
CPU time 0.71 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:34:14 PM PDT 24
Peak memory 183512 kb
Host smart-746db0a3-0b25-474b-b6c1-7333551bbe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696955152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3696955152
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3736193423
Short name T249
Test name
Test status
Simulation time 30862275244 ps
CPU time 44.93 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:34:58 PM PDT 24
Peak memory 191788 kb
Host smart-52e75d31-725b-43cb-89cd-9b60704a0385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736193423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3736193423
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.328432770
Short name T197
Test name
Test status
Simulation time 410735828 ps
CPU time 1.09 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:34:15 PM PDT 24
Peak memory 183528 kb
Host smart-755fba94-dabc-4469-bbb0-53f6e7d7a054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328432770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.328432770
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1397729384
Short name T120
Test name
Test status
Simulation time 64351534758 ps
CPU time 69.98 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:35:18 PM PDT 24
Peak memory 183636 kb
Host smart-336231e9-ad5c-45b7-b6eb-8eab3ffdead6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397729384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1397729384
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2278398651
Short name T202
Test name
Test status
Simulation time 93662868081 ps
CPU time 195.12 seconds
Started May 23 03:34:02 PM PDT 24
Finished May 23 03:37:23 PM PDT 24
Peak memory 198536 kb
Host smart-6c95f31d-ff16-44d7-a0d5-c51093aa6018
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278398651 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2278398651
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1654045088
Short name T114
Test name
Test status
Simulation time 398175174 ps
CPU time 1.02 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:34:14 PM PDT 24
Peak memory 183628 kb
Host smart-eaaea9b2-2e2f-4f9f-b398-31668ddd001b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654045088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1654045088
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.4116839694
Short name T37
Test name
Test status
Simulation time 11636498462 ps
CPU time 10.05 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:34:24 PM PDT 24
Peak memory 183588 kb
Host smart-4eb82dae-8f35-4d49-949f-e7467daa2c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116839694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.4116839694
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2181887495
Short name T90
Test name
Test status
Simulation time 523654826 ps
CPU time 1.37 seconds
Started May 23 03:34:03 PM PDT 24
Finished May 23 03:34:12 PM PDT 24
Peak memory 183572 kb
Host smart-b52f638c-a921-4db7-9d6a-8de98c4eff09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181887495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2181887495
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2487198085
Short name T13
Test name
Test status
Simulation time 121973194717 ps
CPU time 77.04 seconds
Started May 23 03:34:04 PM PDT 24
Finished May 23 03:35:28 PM PDT 24
Peak memory 195456 kb
Host smart-553f68eb-c61d-4c8b-b565-3465572fe5e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487198085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2487198085
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2321674941
Short name T50
Test name
Test status
Simulation time 212078060390 ps
CPU time 423.75 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:41:17 PM PDT 24
Peak memory 197388 kb
Host smart-4d2857ec-e0d3-442e-b0a9-19b87fc62be3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321674941 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2321674941
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2498529060
Short name T121
Test name
Test status
Simulation time 522175369 ps
CPU time 1.49 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:34:14 PM PDT 24
Peak memory 183628 kb
Host smart-265e70f6-88d5-4848-8871-2a50c4f44a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498529060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2498529060
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2148848228
Short name T117
Test name
Test status
Simulation time 27209012264 ps
CPU time 9.69 seconds
Started May 23 03:33:47 PM PDT 24
Finished May 23 03:34:02 PM PDT 24
Peak memory 183628 kb
Host smart-079ad6f1-5dbb-4c11-8222-f1bf73c70524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148848228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2148848228
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1410597908
Short name T65
Test name
Test status
Simulation time 383455694 ps
CPU time 1.13 seconds
Started May 23 03:34:04 PM PDT 24
Finished May 23 03:34:12 PM PDT 24
Peak memory 183540 kb
Host smart-53ed42da-c061-4b6a-82ff-db9fff45a150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410597908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1410597908
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2926136711
Short name T180
Test name
Test status
Simulation time 84267661341 ps
CPU time 56.85 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:35:10 PM PDT 24
Peak memory 195232 kb
Host smart-39a0e04f-371e-499f-aeef-3b0177ec75f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926136711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2926136711
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1920647466
Short name T34
Test name
Test status
Simulation time 106570889776 ps
CPU time 185.22 seconds
Started May 23 03:34:07 PM PDT 24
Finished May 23 03:37:20 PM PDT 24
Peak memory 206632 kb
Host smart-9b6803d5-38fb-483d-850c-d68fff905f8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920647466 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1920647466
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3494014078
Short name T203
Test name
Test status
Simulation time 588669723 ps
CPU time 1.54 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:34:15 PM PDT 24
Peak memory 183628 kb
Host smart-72e525ec-af39-471f-a951-dc3fb73a8f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494014078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3494014078
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3663428624
Short name T166
Test name
Test status
Simulation time 11697960760 ps
CPU time 6.84 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:34:20 PM PDT 24
Peak memory 182528 kb
Host smart-35c765f2-2e1a-4392-af1e-9e564c461ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663428624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3663428624
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1448650238
Short name T238
Test name
Test status
Simulation time 430498516 ps
CPU time 0.93 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:34:15 PM PDT 24
Peak memory 183472 kb
Host smart-364c8cbf-086e-4807-ba97-3ccf0524bd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448650238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1448650238
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.349066065
Short name T182
Test name
Test status
Simulation time 57053323063 ps
CPU time 89.12 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:35:42 PM PDT 24
Peak memory 194408 kb
Host smart-e49d8b85-899f-4cc8-9911-544d47d31127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349066065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.349066065
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.94876765
Short name T15
Test name
Test status
Simulation time 72287594021 ps
CPU time 639.79 seconds
Started May 23 03:34:07 PM PDT 24
Finished May 23 03:44:55 PM PDT 24
Peak memory 198756 kb
Host smart-66d91acc-c805-4045-8047-3b96f2857362
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94876765 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.94876765
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1999848063
Short name T275
Test name
Test status
Simulation time 440256550 ps
CPU time 1.05 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:34:01 PM PDT 24
Peak memory 183560 kb
Host smart-e28693c4-49d5-4c61-a44e-95725312c603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999848063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1999848063
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.639056193
Short name T123
Test name
Test status
Simulation time 1525721047 ps
CPU time 0.75 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:34:07 PM PDT 24
Peak memory 183572 kb
Host smart-27e70823-0c31-440f-be62-401e6fe49099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639056193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.639056193
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.566345505
Short name T280
Test name
Test status
Simulation time 547770726 ps
CPU time 1.27 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:34:09 PM PDT 24
Peak memory 183576 kb
Host smart-9e6a4e57-6cd3-4776-bc6e-48fe78ca55e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566345505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.566345505
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2317220354
Short name T183
Test name
Test status
Simulation time 155468227353 ps
CPU time 54.52 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:35:08 PM PDT 24
Peak memory 183540 kb
Host smart-834e806b-ec23-4c00-b603-6f2da54efb28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317220354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2317220354
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3217798037
Short name T6
Test name
Test status
Simulation time 67009046767 ps
CPU time 741.7 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:46:36 PM PDT 24
Peak memory 200196 kb
Host smart-09a4fc01-4e8b-4c0c-a3b8-6672438c5ea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217798037 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3217798037
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.765976802
Short name T257
Test name
Test status
Simulation time 544738106 ps
CPU time 0.78 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:34:07 PM PDT 24
Peak memory 183604 kb
Host smart-4923d6b7-603c-465b-9fda-f8efde4bf3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765976802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.765976802
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2255328202
Short name T164
Test name
Test status
Simulation time 33807280894 ps
CPU time 17.07 seconds
Started May 23 03:33:59 PM PDT 24
Finished May 23 03:34:22 PM PDT 24
Peak memory 183628 kb
Host smart-7d3387ed-4a13-400d-9bf9-f8ee7421b7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255328202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2255328202
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1634316638
Short name T3
Test name
Test status
Simulation time 403095184 ps
CPU time 1.13 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:34:14 PM PDT 24
Peak memory 183576 kb
Host smart-4d25453f-1c5b-472b-b145-f0f794c7aede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634316638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1634316638
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.907535371
Short name T174
Test name
Test status
Simulation time 65600077167 ps
CPU time 108.52 seconds
Started May 23 03:34:02 PM PDT 24
Finished May 23 03:35:57 PM PDT 24
Peak memory 183632 kb
Host smart-64749c59-a01c-408c-ad4c-98ea499b6f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907535371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.907535371
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3988613542
Short name T105
Test name
Test status
Simulation time 15187035039 ps
CPU time 172.29 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:37:00 PM PDT 24
Peak memory 198572 kb
Host smart-a9a783f4-96b3-4cf5-a221-2f9f86b2da12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988613542 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3988613542
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.4161627294
Short name T247
Test name
Test status
Simulation time 517709861 ps
CPU time 1.27 seconds
Started May 23 03:34:03 PM PDT 24
Finished May 23 03:34:11 PM PDT 24
Peak memory 183552 kb
Host smart-511bc258-f484-4895-b7f6-8e8f72122da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161627294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.4161627294
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2027264459
Short name T101
Test name
Test status
Simulation time 16301282302 ps
CPU time 20.81 seconds
Started May 23 03:34:02 PM PDT 24
Finished May 23 03:34:30 PM PDT 24
Peak memory 183616 kb
Host smart-ed9ab803-4878-48b1-8134-157221b030be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027264459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2027264459
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1505540373
Short name T218
Test name
Test status
Simulation time 406070449 ps
CPU time 0.88 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:34:02 PM PDT 24
Peak memory 183568 kb
Host smart-ce3df756-c9bd-4456-b929-82b8f7ca798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505540373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1505540373
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2150171741
Short name T261
Test name
Test status
Simulation time 158228145048 ps
CPU time 126.51 seconds
Started May 23 03:34:02 PM PDT 24
Finished May 23 03:36:16 PM PDT 24
Peak memory 183768 kb
Host smart-ffb790f9-99f1-4592-8b4c-917a3072fb5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150171741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2150171741
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.266518957
Short name T82
Test name
Test status
Simulation time 141653663755 ps
CPU time 763.24 seconds
Started May 23 03:34:03 PM PDT 24
Finished May 23 03:46:53 PM PDT 24
Peak memory 201896 kb
Host smart-caf6783d-65b4-4843-98fb-60b887c2b77c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266518957 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.266518957
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3687435551
Short name T7
Test name
Test status
Simulation time 528023358 ps
CPU time 1.36 seconds
Started May 23 03:34:03 PM PDT 24
Finished May 23 03:34:11 PM PDT 24
Peak memory 183552 kb
Host smart-c9fa7485-fcd3-42af-a974-ce0e4d4d2b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687435551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3687435551
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1884004571
Short name T10
Test name
Test status
Simulation time 12830472498 ps
CPU time 6.08 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:34:13 PM PDT 24
Peak memory 183584 kb
Host smart-e1e68029-b997-433f-9786-c0dc4546f0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884004571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1884004571
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.498469356
Short name T234
Test name
Test status
Simulation time 343645767 ps
CPU time 0.83 seconds
Started May 23 03:34:02 PM PDT 24
Finished May 23 03:34:10 PM PDT 24
Peak memory 183556 kb
Host smart-1214a06f-6147-4df9-9c02-e44729c89c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498469356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.498469356
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3467636262
Short name T220
Test name
Test status
Simulation time 32995822378 ps
CPU time 51.89 seconds
Started May 23 03:34:02 PM PDT 24
Finished May 23 03:35:01 PM PDT 24
Peak memory 183624 kb
Host smart-0f9da9f5-b41a-412d-81a0-df429686482f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467636262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3467636262
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2131413129
Short name T239
Test name
Test status
Simulation time 363648639707 ps
CPU time 716.98 seconds
Started May 23 03:34:03 PM PDT 24
Finished May 23 03:46:07 PM PDT 24
Peak memory 201804 kb
Host smart-c232167d-becd-48f9-8f60-2d13b1e142ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131413129 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2131413129
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3388351831
Short name T128
Test name
Test status
Simulation time 430920818 ps
CPU time 0.73 seconds
Started May 23 03:34:04 PM PDT 24
Finished May 23 03:34:12 PM PDT 24
Peak memory 183560 kb
Host smart-ee559496-9b50-4d79-a138-6d3eebad859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388351831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3388351831
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.624426481
Short name T103
Test name
Test status
Simulation time 22952772301 ps
CPU time 37.09 seconds
Started May 23 03:33:57 PM PDT 24
Finished May 23 03:34:37 PM PDT 24
Peak memory 183604 kb
Host smart-fc2f8a19-90f9-4d63-ad59-bb58503d7a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624426481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.624426481
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.628396069
Short name T179
Test name
Test status
Simulation time 531505841 ps
CPU time 0.91 seconds
Started May 23 03:34:04 PM PDT 24
Finished May 23 03:34:12 PM PDT 24
Peak memory 183564 kb
Host smart-ef35643b-1074-489f-a28a-ce4534e0575b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628396069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.628396069
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.788545255
Short name T64
Test name
Test status
Simulation time 823645514708 ps
CPU time 475.98 seconds
Started May 23 03:34:01 PM PDT 24
Finished May 23 03:42:04 PM PDT 24
Peak memory 198748 kb
Host smart-b167fe3b-5676-4593-bfeb-61ff6b0ead4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788545255 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.788545255
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2546476870
Short name T216
Test name
Test status
Simulation time 604127277 ps
CPU time 0.67 seconds
Started May 23 03:34:03 PM PDT 24
Finished May 23 03:34:11 PM PDT 24
Peak memory 183564 kb
Host smart-55b2a887-9133-4800-b85a-fc0a94afd6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546476870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2546476870
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.922412752
Short name T129
Test name
Test status
Simulation time 61104713867 ps
CPU time 71.44 seconds
Started May 23 03:34:00 PM PDT 24
Finished May 23 03:35:18 PM PDT 24
Peak memory 191836 kb
Host smart-b78f4011-8239-4c63-a355-93b17a4384ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922412752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.922412752
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3942291279
Short name T135
Test name
Test status
Simulation time 551130861 ps
CPU time 1.43 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:34:15 PM PDT 24
Peak memory 183528 kb
Host smart-774199e0-ac29-4dca-82d7-2a0fb4cee024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942291279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3942291279
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2109821473
Short name T221
Test name
Test status
Simulation time 193964804869 ps
CPU time 89.73 seconds
Started May 23 03:34:04 PM PDT 24
Finished May 23 03:35:41 PM PDT 24
Peak memory 183784 kb
Host smart-d44997b5-e3d4-4d3d-bf7a-506734723de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109821473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2109821473
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1330258096
Short name T244
Test name
Test status
Simulation time 133867034840 ps
CPU time 294.71 seconds
Started May 23 03:34:04 PM PDT 24
Finished May 23 03:39:06 PM PDT 24
Peak memory 198568 kb
Host smart-550c858c-8ae9-48f7-afb1-30e2d44da156
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330258096 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1330258096
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3327971241
Short name T255
Test name
Test status
Simulation time 438275795 ps
CPU time 1.15 seconds
Started May 23 03:33:36 PM PDT 24
Finished May 23 03:33:39 PM PDT 24
Peak memory 183564 kb
Host smart-aadf1aac-55d9-4dbb-861a-7f85d16551f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327971241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3327971241
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1798650027
Short name T124
Test name
Test status
Simulation time 22011639078 ps
CPU time 3.18 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:33:48 PM PDT 24
Peak memory 183632 kb
Host smart-3f8e994c-d75e-46b2-94f1-9b4e76a4ec3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798650027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1798650027
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.333831132
Short name T277
Test name
Test status
Simulation time 485337485 ps
CPU time 1.28 seconds
Started May 23 03:33:37 PM PDT 24
Finished May 23 03:33:40 PM PDT 24
Peak memory 183560 kb
Host smart-c01f7f8b-a48b-4c63-bcfe-3e25374d100a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333831132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.333831132
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1691822684
Short name T157
Test name
Test status
Simulation time 183240535600 ps
CPU time 62.72 seconds
Started May 23 03:33:43 PM PDT 24
Finished May 23 03:34:51 PM PDT 24
Peak memory 195064 kb
Host smart-d71063b2-ccc0-4b59-946a-df3e6aef1560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691822684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1691822684
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2227522956
Short name T137
Test name
Test status
Simulation time 96786924396 ps
CPU time 168.5 seconds
Started May 23 03:33:37 PM PDT 24
Finished May 23 03:36:27 PM PDT 24
Peak memory 198520 kb
Host smart-234f2f19-24f8-4fe9-8bed-febdcbf41612
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227522956 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2227522956
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3588201435
Short name T224
Test name
Test status
Simulation time 367510061 ps
CPU time 0.67 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:33:46 PM PDT 24
Peak memory 183584 kb
Host smart-6adbfc5f-2b36-4f59-9af6-e66377e162a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588201435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3588201435
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1383683052
Short name T259
Test name
Test status
Simulation time 34029597054 ps
CPU time 45.49 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:34:29 PM PDT 24
Peak memory 183588 kb
Host smart-a5f74a9e-ba2a-47dd-9dbd-442d60cfc0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383683052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1383683052
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2899750507
Short name T235
Test name
Test status
Simulation time 510992911 ps
CPU time 0.74 seconds
Started May 23 03:33:36 PM PDT 24
Finished May 23 03:33:37 PM PDT 24
Peak memory 183568 kb
Host smart-714b544f-22e2-4427-baa5-bf027e9287f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899750507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2899750507
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3348313551
Short name T178
Test name
Test status
Simulation time 183432858208 ps
CPU time 70.43 seconds
Started May 23 03:33:37 PM PDT 24
Finished May 23 03:34:50 PM PDT 24
Peak memory 195580 kb
Host smart-08290e4d-9ed1-42a0-a935-e0a897bf2a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348313551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3348313551
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.24580773
Short name T146
Test name
Test status
Simulation time 246309852484 ps
CPU time 363.08 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:39:47 PM PDT 24
Peak memory 198492 kb
Host smart-dd407d35-b7b7-4036-80ef-8996053870aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24580773 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.24580773
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.4206995228
Short name T125
Test name
Test status
Simulation time 415888178 ps
CPU time 1.12 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:33:46 PM PDT 24
Peak memory 183588 kb
Host smart-b532c5e0-2c77-4261-baf3-0c1d02f4875f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206995228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.4206995228
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3436143454
Short name T245
Test name
Test status
Simulation time 61343294989 ps
CPU time 90.14 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:35:14 PM PDT 24
Peak memory 183600 kb
Host smart-31a1f8bc-8aec-4781-84b4-13c75be79edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436143454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3436143454
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3885978063
Short name T236
Test name
Test status
Simulation time 388048262 ps
CPU time 0.83 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:33:44 PM PDT 24
Peak memory 183564 kb
Host smart-e8be6eab-6f70-4618-af53-3e2b7cbb04a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885978063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3885978063
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.742018486
Short name T170
Test name
Test status
Simulation time 21930449806 ps
CPU time 8.38 seconds
Started May 23 03:33:36 PM PDT 24
Finished May 23 03:33:46 PM PDT 24
Peak memory 183524 kb
Host smart-627caa54-421b-4dfa-9d15-f373b0b4c920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742018486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.742018486
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.4073542001
Short name T251
Test name
Test status
Simulation time 293934664497 ps
CPU time 367.38 seconds
Started May 23 03:33:36 PM PDT 24
Finished May 23 03:39:45 PM PDT 24
Peak memory 198568 kb
Host smart-8aebd3a4-1a2b-4d5e-9b86-2d1bc1bfdf64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073542001 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.4073542001
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.25593140
Short name T181
Test name
Test status
Simulation time 506247633 ps
CPU time 1.32 seconds
Started May 23 03:33:36 PM PDT 24
Finished May 23 03:33:39 PM PDT 24
Peak memory 183552 kb
Host smart-3351cdab-5f7c-4064-82c9-b82470d39a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25593140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.25593140
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1923671262
Short name T102
Test name
Test status
Simulation time 18041000658 ps
CPU time 27.92 seconds
Started May 23 03:33:35 PM PDT 24
Finished May 23 03:34:03 PM PDT 24
Peak memory 183628 kb
Host smart-ae071612-3233-49bc-8ed9-d5d57d1d4e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923671262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1923671262
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3788494061
Short name T232
Test name
Test status
Simulation time 614392157 ps
CPU time 0.9 seconds
Started May 23 03:33:38 PM PDT 24
Finished May 23 03:33:42 PM PDT 24
Peak memory 183548 kb
Host smart-bfaa836f-e7c7-49c5-a762-3ffd3aa75c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788494061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3788494061
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.522846716
Short name T108
Test name
Test status
Simulation time 91818036791 ps
CPU time 40.42 seconds
Started May 23 03:33:39 PM PDT 24
Finished May 23 03:34:22 PM PDT 24
Peak memory 194940 kb
Host smart-05942f43-d1aa-491d-8ebd-dcc2f2a9092d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522846716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.522846716
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.830171268
Short name T189
Test name
Test status
Simulation time 427629262 ps
CPU time 1.21 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:33:45 PM PDT 24
Peak memory 183572 kb
Host smart-e125c15d-2499-4f7d-8050-0061ddd7e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830171268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.830171268
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1771022747
Short name T21
Test name
Test status
Simulation time 26161136066 ps
CPU time 19.89 seconds
Started May 23 03:33:41 PM PDT 24
Finished May 23 03:34:05 PM PDT 24
Peak memory 183628 kb
Host smart-90c7c031-1cd7-4316-bec7-185cf3dcb03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771022747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1771022747
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1320184844
Short name T230
Test name
Test status
Simulation time 594651234 ps
CPU time 0.78 seconds
Started May 23 03:33:43 PM PDT 24
Finished May 23 03:33:49 PM PDT 24
Peak memory 183568 kb
Host smart-29158c3a-2e3b-4755-b20b-647d60390e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320184844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1320184844
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1878857367
Short name T279
Test name
Test status
Simulation time 130889153926 ps
CPU time 195.75 seconds
Started May 23 03:33:36 PM PDT 24
Finished May 23 03:36:53 PM PDT 24
Peak memory 195412 kb
Host smart-8c5d913b-be9a-46b7-bcdc-544bf1fa17de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878857367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1878857367
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.4160588560
Short name T271
Test name
Test status
Simulation time 13582500516 ps
CPU time 126.19 seconds
Started May 23 03:33:40 PM PDT 24
Finished May 23 03:35:50 PM PDT 24
Peak memory 198564 kb
Host smart-451f06e8-9087-49cf-9651-4b2cc348f857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160588560 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.4160588560
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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