Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	29625	1		T1	238		T3	12		T4	12
bark[1]	909	1		T116	21		T18	194		T42	21
bark[2]	149	1		T16	21		T117	14		T40	44
bark[3]	524	1		T119	161		T126	21		T177	215
bark[4]	771	1		T197	14		T17	212		T116	21
bark[5]	281	1		T42	21		T128	14		T146	14
bark[6]	586	1		T41	137		T107	66		T85	7
bark[7]	550	1		T160	21		T42	21		T43	21
bark[8]	769	1		T125	23		T42	310		T43	26
bark[9]	538	1		T160	21		T41	317		T90	14
bark[10]	392	1		T139	14		T137	127		T173	21
bark[11]	612	1		T43	7		T124	14		T94	26
bark[12]	847	1		T41	209		T107	21		T88	14
bark[13]	477	1		T26	21		T160	79		T109	78
bark[14]	677	1		T29	14		T43	30		T89	14
bark[15]	226	1		T2	14		T41	7		T157	30
bark[16]	439	1		T6	14		T193	14		T158	21
bark[17]	586	1		T5	96		T40	92		T43	45
bark[18]	409	1		T150	63		T41	26		T94	94
bark[19]	173	1		T8	14		T42	21		T122	138
bark[20]	193	1		T5	26		T130	14		T95	83
bark[21]	320	1		T89	21		T126	21		T169	26
bark[22]	1003	1		T107	69		T85	188		T158	21
bark[23]	516	1		T139	35		T93	193		T199	14
bark[24]	909	1		T16	21		T160	21		T139	21
bark[25]	483	1		T144	14		T150	21		T44	21
bark[26]	418	1		T9	14		T109	31		T100	148
bark[27]	422	1		T25	14		T160	23		T125	21
bark[28]	328	1		T43	181		T93	26		T198	26
bark[29]	607	1		T31	14		T84	35		T90	60
bark[30]	655	1		T7	21		T89	39		T138	30
bark[31]	917	1		T7	21		T89	61		T137	241
bark_0	4643	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	29500	1		T1	237		T3	11		T4	11
bite[1]	589	1		T5	96		T16	21		T157	30
bite[2]	428	1		T7	21		T26	21		T116	21
bite[3]	197	1		T118	47		T120	13		T121	21
bite[4]	1086	1		T31	13		T116	30		T125	21
bite[5]	482	1		T7	21		T29	13		T40	61
bite[6]	582	1		T125	21		T43	44		T109	39
bite[7]	823	1		T6	13		T25	13		T41	316
bite[8]	438	1		T109	26		T88	49		T132	13
bite[9]	693	1		T5	26		T17	211		T139	21
bite[10]	644	1		T2	13		T125	21		T44	46
bite[11]	184	1		T144	13		T116	21		T84	34
bite[12]	416	1		T43	21		T85	6		T147	24
bite[13]	176	1		T150	21		T199	13		T173	21
bite[14]	273	1		T40	43		T46	21		T90	21
bite[15]	540	1		T41	6		T90	13		T93	21
bite[16]	585	1		T160	101		T205	13		T147	239
bite[17]	456	1		T107	21		T90	21		T161	13
bite[18]	543	1		T9	13		T113	13		T137	240
bite[19]	846	1		T5	21		T16	21		T150	42
bite[20]	428	1		T8	13		T93	25		T137	71
bite[21]	440	1		T160	21		T90	30		T93	192
bite[22]	340	1		T42	21		T137	30		T198	21
bite[23]	441	1		T100	94		T138	13		T97	21
bite[24]	444	1		T42	21		T43	6		T202	13
bite[25]	330	1		T150	21		T193	13		T89	61
bite[26]	177	1		T42	21		T189	13		T204	13
bite[27]	721	1		T41	208		T43	71		T139	13
bite[28]	407	1		T160	21		T43	180		T107	21
bite[29]	580	1		T45	21		T91	13		T137	30
bite[30]	592	1		T41	136		T108	13		T85	187
bite[31]	1428	1		T109	39		T84	21		T90	60
bite_0	5145	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	50954	1		T1	245		T2	21		T3	19

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1137	1		T18	83		T43	71		T210	9
prescale[1]	902	1		T1	33		T3	9		T17	19
prescale[2]	1151	1		T150	24		T17	29		T40	19
prescale[3]	796	1		T13	9		T17	249		T18	23
prescale[4]	704	1		T1	37		T17	61		T42	19
prescale[5]	1815	1		T16	115		T40	150		T41	252
prescale[6]	915	1		T1	19		T17	9		T18	73
prescale[7]	588	1		T125	23		T42	84		T85	33
prescale[8]	725	1		T4	9		T7	28		T160	23
prescale[9]	936	1		T7	19		T116	37		T41	120
prescale[10]	399	1		T5	9		T14	9		T48	9
prescale[11]	504	1		T116	33		T42	37		T43	48
prescale[12]	994	1		T26	37		T150	28		T17	98
prescale[13]	803	1		T211	9		T18	2		T125	40
prescale[14]	883	1		T10	9		T41	63		T43	106
prescale[15]	661	1		T16	2		T38	9		T17	71
prescale[16]	603	1		T150	19		T41	28		T42	51
prescale[17]	1067	1		T7	48		T41	72		T42	79
prescale[18]	513	1		T16	88		T18	2		T157	42
prescale[19]	618	1		T16	19		T17	33		T40	79
prescale[20]	424	1		T16	20		T84	61		T158	19
prescale[21]	873	1		T26	62		T42	40		T43	2
prescale[22]	600	1		T49	9		T150	9		T41	19
prescale[23]	271	1		T46	76		T84	2		T137	16
prescale[24]	728	1		T16	87		T50	9		T40	19
prescale[25]	869	1		T7	40		T26	19		T16	27
prescale[26]	903	1		T16	2		T150	19		T160	58
prescale[27]	1131	1		T1	33		T26	37		T17	19
prescale[28]	404	1		T16	40		T40	20		T44	28
prescale[29]	1120	1		T5	41		T15	9		T16	84
prescale[30]	918	1		T41	19		T42	58		T107	23
prescale[31]	444	1		T26	19		T18	2		T125	19
prescale_0	25555	1		T1	123		T2	21		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	37970	1		T1	133		T2	21		T3	9
auto[1]	12984	1		T1	112		T3	10		T4	10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	50954	1		T1	245		T2	21		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	29691	1		T1	240		T2	1		T3	14
wkup[1]	394	1		T17	21		T42	42		T124	15
wkup[2]	346	1		T41	44		T46	21		T194	21
wkup[3]	296	1		T160	21		T43	21		T139	15
wkup[4]	249	1		T41	15		T46	21		T94	42
wkup[5]	299	1		T18	21		T41	21		T42	35
wkup[6]	275	1		T150	21		T17	26		T42	21
wkup[7]	154	1		T17	26		T41	15		T147	21
wkup[8]	232	1		T16	21		T18	8		T147	21
wkup[9]	268	1		T41	21		T90	21		T137	30
wkup[10]	374	1		T16	21		T18	26		T41	21
wkup[11]	322	1		T8	15		T160	21		T85	30
wkup[12]	342	1		T150	21		T117	15		T41	8
wkup[13]	238	1		T7	21		T197	15		T107	21
wkup[14]	281	1		T25	15		T18	21		T40	42
wkup[15]	218	1		T17	21		T42	21		T137	15
wkup[16]	248	1		T44	21		T85	21		T173	21
wkup[17]	251	1		T116	21		T43	15		T137	21
wkup[18]	267	1		T147	27		T137	21		T119	21
wkup[19]	309	1		T17	21		T40	21		T41	26
wkup[20]	388	1		T2	15		T26	15		T125	24
wkup[21]	340	1		T40	21		T42	21		T109	31
wkup[22]	153	1		T17	21		T46	21		T90	21
wkup[23]	193	1		T43	21		T137	50		T180	8
wkup[24]	254	1		T18	21		T40	21		T41	30
wkup[25]	239	1		T26	21		T40	21		T41	21
wkup[26]	202	1		T16	21		T17	21		T46	21
wkup[27]	277	1		T125	21		T44	21		T45	21
wkup[28]	323	1		T16	21		T107	21		T147	21
wkup[29]	346	1		T16	41		T17	21		T125	21
wkup[30]	311	1		T109	39		T89	21		T94	21
wkup[31]	200	1		T40	21		T43	29		T85	30
wkup[32]	340	1		T16	21		T17	21		T139	21
wkup[33]	385	1		T40	45		T42	36		T43	21
wkup[34]	222	1		T7	21		T147	21		T137	35
wkup[35]	343	1		T125	21		T40	26		T41	21
wkup[36]	163	1		T84	21		T97	35		T142	21
wkup[37]	427	1		T5	21		T16	30		T17	26
wkup[38]	113	1		T119	21		T173	21		T135	21
wkup[39]	218	1		T5	21		T42	21		T100	21
wkup[40]	204	1		T5	21		T42	21		T107	21
wkup[41]	329	1		T7	21		T9	15		T31	15
wkup[42]	221	1		T116	30		T193	15		T93	21
wkup[43]	231	1		T42	21		T46	21		T199	15
wkup[44]	467	1		T43	30		T85	21		T202	15
wkup[45]	124	1		T41	21		T96	21		T138	21
wkup[46]	336	1		T18	21		T84	21		T89	21
wkup[47]	236	1		T84	21		T101	21		T118	21
wkup[48]	236	1		T16	21		T29	15		T150	21
wkup[49]	363	1		T17	21		T116	21		T125	21
wkup[50]	323	1		T108	15		T91	15		T93	21
wkup[51]	407	1		T45	8		T46	51		T84	21
wkup[52]	274	1		T43	21		T107	21		T113	15
wkup[53]	199	1		T160	21		T18	21		T90	30
wkup[54]	250	1		T93	15		T100	26		T147	21
wkup[55]	234	1		T5	26		T16	21		T160	24
wkup[56]	273	1		T40	21		T42	21		T107	21
wkup[57]	181	1		T16	21		T41	21		T44	21
wkup[58]	267	1		T88	35		T89	15		T93	15
wkup[59]	457	1		T6	15		T150	21		T160	21
wkup[60]	303	1		T16	21		T17	40		T40	21
wkup[61]	304	1		T40	30		T43	35		T89	21
wkup[62]	309	1		T160	21		T41	21		T43	21
wkup[63]	306	1		T144	15		T42	15		T43	21
wkup_0	3629	1		T1	5		T2	5		T3	5