Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
3529 |
1 |
|
T1 |
23 |
|
T2 |
3 |
|
T3 |
3 |
all_pins[1] |
3529 |
1 |
|
T1 |
23 |
|
T2 |
3 |
|
T3 |
3 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
4944 |
1 |
|
T1 |
35 |
|
T2 |
5 |
|
T3 |
5 |
values[0x1] |
2114 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T3 |
1 |
transitions[0x0=>0x1] |
1683 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T3 |
1 |
transitions[0x1=>0x0] |
1622 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
2891 |
1 |
|
T1 |
23 |
|
T2 |
3 |
|
T3 |
3 |
all_pins[0] |
values[0x1] |
638 |
1 |
|
T5 |
9 |
|
T7 |
6 |
|
T9 |
1 |
all_pins[0] |
transitions[0x0=>0x1] |
346 |
1 |
|
T5 |
5 |
|
T7 |
3 |
|
T9 |
1 |
all_pins[0] |
transitions[0x1=>0x0] |
1184 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T3 |
1 |
all_pins[1] |
values[0x0] |
2053 |
1 |
|
T1 |
12 |
|
T2 |
2 |
|
T3 |
2 |
all_pins[1] |
values[0x1] |
1476 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T3 |
1 |
all_pins[1] |
transitions[0x0=>0x1] |
1337 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T3 |
1 |
all_pins[1] |
transitions[0x1=>0x0] |
438 |
1 |
|
T5 |
7 |
|
T7 |
6 |
|
T12 |
1 |