| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 90.13 | 99.33 | 93.67 | 100.00 | 98.40 | 99.51 | 49.86 |
| T286 | /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1504168255 | May 26 02:36:58 PM PDT 24 | May 26 02:37:00 PM PDT 24 | 661936476 ps | ||
| T32 | /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2733043902 | May 26 02:37:39 PM PDT 24 | May 26 02:37:40 PM PDT 24 | 627214262 ps | ||
| T287 | /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.175718957 | May 26 02:37:54 PM PDT 24 | May 26 02:37:58 PM PDT 24 | 516936207 ps | ||
| T33 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3292092009 | May 26 02:37:21 PM PDT 24 | May 26 02:37:23 PM PDT 24 | 452538974 ps | ||
| T39 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1257194563 | May 26 02:37:22 PM PDT 24 | May 26 02:37:28 PM PDT 24 | 7951671284 ps | ||
| T288 | /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3139852468 | May 26 02:38:01 PM PDT 24 | May 26 02:38:03 PM PDT 24 | 453341677 ps | ||
| T289 | /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2875412721 | May 26 02:37:46 PM PDT 24 | May 26 02:37:49 PM PDT 24 | 550171461 ps | ||
| T290 | /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3560960834 | May 26 02:37:29 PM PDT 24 | May 26 02:37:32 PM PDT 24 | 690270506 ps | ||
| T34 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3960273171 | May 26 02:37:15 PM PDT 24 | May 26 02:37:17 PM PDT 24 | 409352253 ps | ||
| T291 | /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3768765948 | May 26 02:37:15 PM PDT 24 | May 26 02:37:17 PM PDT 24 | 312064230 ps | ||
| T35 | /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2045915407 | May 26 02:37:39 PM PDT 24 | May 26 02:37:44 PM PDT 24 | 8793909989 ps | ||
| T59 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3852277691 | May 26 02:37:08 PM PDT 24 | May 26 02:37:26 PM PDT 24 | 13750415946 ps | ||
| T36 | /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1870286650 | May 26 02:37:29 PM PDT 24 | May 26 02:37:34 PM PDT 24 | 3743133097 ps | ||
| T75 | /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4241835067 | May 26 02:38:11 PM PDT 24 | May 26 02:38:14 PM PDT 24 | 1587580901 ps | ||
| T76 | /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2530277903 | May 26 02:37:58 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 1263498481 ps | ||
| T292 | /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.410932200 | May 26 02:37:09 PM PDT 24 | May 26 02:37:11 PM PDT 24 | 508419270 ps | ||
| T60 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2448285869 | May 26 02:37:23 PM PDT 24 | May 26 02:37:34 PM PDT 24 | 3535931005 ps | ||
| T37 | /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2963653534 | May 26 02:37:12 PM PDT 24 | May 26 02:37:27 PM PDT 24 | 8418227437 ps | ||
| T61 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3249123622 | May 26 02:37:14 PM PDT 24 | May 26 02:37:16 PM PDT 24 | 629036518 ps | ||
| T293 | /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2148401683 | May 26 02:37:44 PM PDT 24 | May 26 02:37:46 PM PDT 24 | 299663248 ps | ||
| T294 | /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3258854479 | May 26 02:37:51 PM PDT 24 | May 26 02:37:55 PM PDT 24 | 3942041689 ps | ||
| T295 | /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.12536773 | May 26 02:38:10 PM PDT 24 | May 26 02:38:12 PM PDT 24 | 392647247 ps | ||
| T296 | /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2740389243 | May 26 02:37:51 PM PDT 24 | May 26 02:38:05 PM PDT 24 | 7825685153 ps | ||
| T62 | /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.308954003 | May 26 02:37:55 PM PDT 24 | May 26 02:37:58 PM PDT 24 | 285356309 ps | ||
| T77 | /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3369728750 | May 26 02:37:55 PM PDT 24 | May 26 02:37:59 PM PDT 24 | 1359164071 ps | ||
| T78 | /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.622894197 | May 26 02:38:00 PM PDT 24 | May 26 02:38:03 PM PDT 24 | 426363015 ps | ||
| T207 | /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.314055310 | May 26 02:37:54 PM PDT 24 | May 26 02:37:59 PM PDT 24 | 4874404278 ps | ||
| T297 | /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1596469419 | May 26 02:36:58 PM PDT 24 | May 26 02:36:59 PM PDT 24 | 361692240 ps | ||
| T298 | /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2958830122 | May 26 02:36:59 PM PDT 24 | May 26 02:37:01 PM PDT 24 | 318782960 ps | ||
| T299 | /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2388756376 | May 26 02:38:00 PM PDT 24 | May 26 02:38:03 PM PDT 24 | 422309920 ps | ||
| T300 | /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3953502165 | May 26 02:37:06 PM PDT 24 | May 26 02:37:07 PM PDT 24 | 592005059 ps | ||
| T301 | /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3111688044 | May 26 02:37:15 PM PDT 24 | May 26 02:37:17 PM PDT 24 | 271335383 ps | ||
| T302 | /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4159984278 | May 26 02:37:38 PM PDT 24 | May 26 02:37:40 PM PDT 24 | 404656576 ps | ||
| T303 | /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.824442987 | May 26 02:37:36 PM PDT 24 | May 26 02:37:37 PM PDT 24 | 349978265 ps | ||
| T304 | /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.564890239 | May 26 02:37:29 PM PDT 24 | May 26 02:37:30 PM PDT 24 | 381802598 ps | ||
| T305 | /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3636592581 | May 26 02:37:23 PM PDT 24 | May 26 02:37:26 PM PDT 24 | 417179060 ps | ||
| T306 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3478900161 | May 26 02:37:16 PM PDT 24 | May 26 02:37:18 PM PDT 24 | 930410792 ps | ||
| T208 | /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3194294312 | May 26 02:37:21 PM PDT 24 | May 26 02:37:25 PM PDT 24 | 8341076746 ps | ||
| T79 | /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2239807352 | May 26 02:37:30 PM PDT 24 | May 26 02:37:33 PM PDT 24 | 1215513832 ps | ||
| T307 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2012570025 | May 26 02:37:09 PM PDT 24 | May 26 02:37:11 PM PDT 24 | 509329479 ps | ||
| T80 | /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.830035260 | May 26 02:37:21 PM PDT 24 | May 26 02:37:25 PM PDT 24 | 2124576808 ps | ||
| T308 | /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.220917256 | May 26 02:37:43 PM PDT 24 | May 26 02:37:46 PM PDT 24 | 570462370 ps | ||
| T309 | /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1305859337 | May 26 02:37:59 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 515079661 ps | ||
| T63 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4101588916 | May 26 02:37:21 PM PDT 24 | May 26 02:37:23 PM PDT 24 | 472802084 ps | ||
| T310 | /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1904725370 | May 26 02:37:42 PM PDT 24 | May 26 02:37:43 PM PDT 24 | 520454379 ps | ||
| T311 | /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.957870633 | May 26 02:37:27 PM PDT 24 | May 26 02:37:29 PM PDT 24 | 428772024 ps | ||
| T312 | /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3672780016 | May 26 02:37:47 PM PDT 24 | May 26 02:37:49 PM PDT 24 | 443094348 ps | ||
| T313 | /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3037894985 | May 26 02:37:37 PM PDT 24 | May 26 02:37:39 PM PDT 24 | 492186767 ps | ||
| T314 | /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.222911957 | May 26 02:37:36 PM PDT 24 | May 26 02:37:38 PM PDT 24 | 453787719 ps | ||
| T315 | /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.29389783 | May 26 02:37:08 PM PDT 24 | May 26 02:37:11 PM PDT 24 | 507915244 ps | ||
| T316 | /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.975601703 | May 26 02:37:14 PM PDT 24 | May 26 02:37:15 PM PDT 24 | 370162804 ps | ||
| T317 | /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.136797352 | May 26 02:37:07 PM PDT 24 | May 26 02:37:08 PM PDT 24 | 404209860 ps | ||
| T318 | /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2695368808 | May 26 02:38:09 PM PDT 24 | May 26 02:38:10 PM PDT 24 | 318985392 ps | ||
| T319 | /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2651756033 | May 26 02:37:59 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 354542445 ps | ||
| T320 | /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2066708756 | May 26 02:37:30 PM PDT 24 | May 26 02:37:32 PM PDT 24 | 431820975 ps | ||
| T81 | /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.160576311 | May 26 02:37:36 PM PDT 24 | May 26 02:37:38 PM PDT 24 | 1522188705 ps | ||
| T321 | /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2948646590 | May 26 02:38:10 PM PDT 24 | May 26 02:38:13 PM PDT 24 | 401018268 ps | ||
| T322 | /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3741724991 | May 26 02:38:10 PM PDT 24 | May 26 02:38:12 PM PDT 24 | 327359878 ps | ||
| T323 | /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.61427214 | May 26 02:37:46 PM PDT 24 | May 26 02:37:48 PM PDT 24 | 620342430 ps | ||
| T324 | /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3783902124 | May 26 02:37:47 PM PDT 24 | May 26 02:37:49 PM PDT 24 | 760614895 ps | ||
| T325 | /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2964956469 | May 26 02:37:53 PM PDT 24 | May 26 02:37:57 PM PDT 24 | 499109257 ps | ||
| T326 | /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1998335967 | May 26 02:37:37 PM PDT 24 | May 26 02:37:45 PM PDT 24 | 8076245247 ps | ||
| T327 | /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1475886322 | May 26 02:37:59 PM PDT 24 | May 26 02:38:01 PM PDT 24 | 530227861 ps | ||
| T328 | /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2283656080 | May 26 02:37:59 PM PDT 24 | May 26 02:38:01 PM PDT 24 | 300980375 ps | ||
| T82 | /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4282350408 | May 26 02:37:43 PM PDT 24 | May 26 02:37:47 PM PDT 24 | 1412180738 ps | ||
| T329 | /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1429581751 | May 26 02:37:51 PM PDT 24 | May 26 02:37:53 PM PDT 24 | 434939369 ps | ||
| T330 | /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2296714496 | May 26 02:37:59 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 311276359 ps | ||
| T64 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3119294991 | May 26 02:37:12 PM PDT 24 | May 26 02:37:15 PM PDT 24 | 1157243802 ps | ||
| T331 | /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1788465660 | May 26 02:38:10 PM PDT 24 | May 26 02:38:13 PM PDT 24 | 431901068 ps | ||
| T65 | /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1774054000 | May 26 02:37:45 PM PDT 24 | May 26 02:37:46 PM PDT 24 | 377608132 ps | ||
| T332 | /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2700555561 | May 26 02:37:47 PM PDT 24 | May 26 02:38:00 PM PDT 24 | 8365254869 ps | ||
| T333 | /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3485007805 | May 26 02:38:07 PM PDT 24 | May 26 02:38:08 PM PDT 24 | 302079844 ps | ||
| T334 | /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.813740809 | May 26 02:37:51 PM PDT 24 | May 26 02:37:53 PM PDT 24 | 475037194 ps | ||
| T83 | /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3388437451 | May 26 02:37:58 PM PDT 24 | May 26 02:38:05 PM PDT 24 | 2534884933 ps | ||
| T335 | /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3365259565 | May 26 02:38:00 PM PDT 24 | May 26 02:38:03 PM PDT 24 | 432934619 ps | ||
| T336 | /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.355220496 | May 26 02:37:43 PM PDT 24 | May 26 02:37:45 PM PDT 24 | 517171330 ps | ||
| T337 | /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3908138627 | May 26 02:38:09 PM PDT 24 | May 26 02:38:11 PM PDT 24 | 473357545 ps | ||
| T338 | /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.380471662 | May 26 02:37:17 PM PDT 24 | May 26 02:37:20 PM PDT 24 | 830733755 ps | ||
| T209 | /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.392949236 | May 26 02:37:52 PM PDT 24 | May 26 02:38:01 PM PDT 24 | 7676836155 ps | ||
| T339 | /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3498363034 | May 26 02:37:52 PM PDT 24 | May 26 02:37:55 PM PDT 24 | 421689967 ps | ||
| T340 | /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3530717529 | May 26 02:37:43 PM PDT 24 | May 26 02:37:48 PM PDT 24 | 4289710457 ps | ||
| T341 | /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3591704465 | May 26 02:38:00 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 391158279 ps | ||
| T72 | /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2352817150 | May 26 02:37:29 PM PDT 24 | May 26 02:37:31 PM PDT 24 | 438599730 ps | ||
| T342 | /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.106859997 | May 26 02:37:16 PM PDT 24 | May 26 02:37:17 PM PDT 24 | 1169221164 ps | ||
| T343 | /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3635736398 | May 26 02:37:55 PM PDT 24 | May 26 02:38:05 PM PDT 24 | 8145725257 ps | ||
| T344 | /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.316279252 | May 26 02:37:54 PM PDT 24 | May 26 02:37:59 PM PDT 24 | 4466266267 ps | ||
| T345 | /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.722115590 | May 26 02:37:21 PM PDT 24 | May 26 02:37:22 PM PDT 24 | 1628287615 ps | ||
| T346 | /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1505832656 | May 26 02:37:59 PM PDT 24 | May 26 02:38:13 PM PDT 24 | 8989007042 ps | ||
| T347 | /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.358204786 | May 26 02:37:30 PM PDT 24 | May 26 02:37:32 PM PDT 24 | 504683992 ps | ||
| T348 | /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.795746577 | May 26 02:37:37 PM PDT 24 | May 26 02:37:39 PM PDT 24 | 358436844 ps | ||
| T349 | /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2717818138 | May 26 02:37:46 PM PDT 24 | May 26 02:37:49 PM PDT 24 | 2779915277 ps | ||
| T350 | /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.132357717 | May 26 02:37:36 PM PDT 24 | May 26 02:37:38 PM PDT 24 | 535508356 ps | ||
| T351 | /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3189618183 | May 26 02:38:07 PM PDT 24 | May 26 02:38:09 PM PDT 24 | 325503240 ps | ||
| T352 | /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3685365931 | May 26 02:37:58 PM PDT 24 | May 26 02:38:01 PM PDT 24 | 512868472 ps | ||
| T353 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4196685116 | May 26 02:37:08 PM PDT 24 | May 26 02:37:10 PM PDT 24 | 420508998 ps | ||
| T354 | /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1657767338 | May 26 02:37:58 PM PDT 24 | May 26 02:38:03 PM PDT 24 | 477992229 ps | ||
| T355 | /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.342255925 | May 26 02:37:43 PM PDT 24 | May 26 02:37:45 PM PDT 24 | 393197072 ps | ||
| T356 | /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1439698354 | May 26 02:38:02 PM PDT 24 | May 26 02:38:04 PM PDT 24 | 377154691 ps | ||
| T357 | /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2133806147 | May 26 02:38:02 PM PDT 24 | May 26 02:38:03 PM PDT 24 | 618718992 ps | ||
| T358 | /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1616250927 | May 26 02:37:52 PM PDT 24 | May 26 02:37:55 PM PDT 24 | 3155987073 ps | ||
| T67 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3385360623 | May 26 02:37:22 PM PDT 24 | May 26 02:37:24 PM PDT 24 | 578929154 ps | ||
| T359 | /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.689407443 | May 26 02:37:59 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 413015493 ps | ||
| T360 | /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2950950941 | May 26 02:38:01 PM PDT 24 | May 26 02:38:04 PM PDT 24 | 642581432 ps | ||
| T73 | /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3964025207 | May 26 02:37:55 PM PDT 24 | May 26 02:37:58 PM PDT 24 | 525992716 ps | ||
| T361 | /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1449525278 | May 26 02:37:20 PM PDT 24 | May 26 02:37:21 PM PDT 24 | 370033752 ps | ||
| T362 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.309551979 | May 26 02:37:20 PM PDT 24 | May 26 02:37:23 PM PDT 24 | 541612210 ps | ||
| T363 | /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1461937649 | May 26 02:37:37 PM PDT 24 | May 26 02:37:42 PM PDT 24 | 2341849061 ps | ||
| T364 | /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4042148629 | May 26 02:37:59 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 414980633 ps | ||
| T68 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2383630802 | May 26 02:37:15 PM PDT 24 | May 26 02:37:18 PM PDT 24 | 7148548222 ps | ||
| T365 | /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2866766177 | May 26 02:37:59 PM PDT 24 | May 26 02:38:03 PM PDT 24 | 424418782 ps | ||
| T366 | /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1115119298 | May 26 02:37:28 PM PDT 24 | May 26 02:37:34 PM PDT 24 | 3911110914 ps | ||
| T367 | /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3260052687 | May 26 02:38:09 PM PDT 24 | May 26 02:38:10 PM PDT 24 | 518601713 ps | ||
| T368 | /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1354033088 | May 26 02:38:06 PM PDT 24 | May 26 02:38:08 PM PDT 24 | 440254584 ps | ||
| T369 | /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2775769901 | May 26 02:37:37 PM PDT 24 | May 26 02:37:41 PM PDT 24 | 8914205219 ps | ||
| T370 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2756929963 | May 26 02:37:29 PM PDT 24 | May 26 02:37:31 PM PDT 24 | 645053075 ps | ||
| T371 | /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1083377989 | May 26 02:37:44 PM PDT 24 | May 26 02:37:46 PM PDT 24 | 495064209 ps | ||
| T372 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2339966265 | May 26 02:37:15 PM PDT 24 | May 26 02:37:16 PM PDT 24 | 459486945 ps | ||
| T373 | /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1831661599 | May 26 02:36:58 PM PDT 24 | May 26 02:37:07 PM PDT 24 | 4201116404 ps | ||
| T374 | /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1114954052 | May 26 02:37:59 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 483523251 ps | ||
| T375 | /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.799562665 | May 26 02:37:53 PM PDT 24 | May 26 02:37:56 PM PDT 24 | 351537227 ps | ||
| T376 | /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1551767438 | May 26 02:37:43 PM PDT 24 | May 26 02:37:50 PM PDT 24 | 2828664756 ps | ||
| T377 | /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3586952998 | May 26 02:38:00 PM PDT 24 | May 26 02:38:03 PM PDT 24 | 390779207 ps | ||
| T378 | /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.865761845 | May 26 02:37:38 PM PDT 24 | May 26 02:37:42 PM PDT 24 | 3000302558 ps | ||
| T74 | /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2558985603 | May 26 02:37:38 PM PDT 24 | May 26 02:37:40 PM PDT 24 | 504422224 ps | ||
| T379 | /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.556702203 | May 26 02:37:46 PM PDT 24 | May 26 02:37:48 PM PDT 24 | 1063030954 ps | ||
| T69 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.769093805 | May 26 02:37:09 PM PDT 24 | May 26 02:37:10 PM PDT 24 | 923275039 ps | ||
| T380 | /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1165803992 | May 26 02:38:00 PM PDT 24 | May 26 02:38:03 PM PDT 24 | 517259201 ps | ||
| T381 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1424924063 | May 26 02:37:07 PM PDT 24 | May 26 02:37:09 PM PDT 24 | 412896884 ps | ||
| T382 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2871782797 | May 26 02:37:01 PM PDT 24 | May 26 02:37:03 PM PDT 24 | 690388274 ps | ||
| T383 | /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2466902161 | May 26 02:37:53 PM PDT 24 | May 26 02:37:57 PM PDT 24 | 697732373 ps | ||
| T384 | /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2765187209 | May 26 02:37:53 PM PDT 24 | May 26 02:37:59 PM PDT 24 | 2432137083 ps | ||
| T385 | /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.61812135 | May 26 02:37:52 PM PDT 24 | May 26 02:37:56 PM PDT 24 | 719654625 ps | ||
| T386 | /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.469402491 | May 26 02:37:47 PM PDT 24 | May 26 02:38:01 PM PDT 24 | 8490916034 ps | ||
| T387 | /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.434178272 | May 26 02:37:59 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 481210152 ps | ||
| T388 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2981020730 | May 26 02:37:22 PM PDT 24 | May 26 02:37:24 PM PDT 24 | 942556123 ps | ||
| T389 | /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3255747004 | May 26 02:37:52 PM PDT 24 | May 26 02:37:56 PM PDT 24 | 396934872 ps | ||
| T390 | /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2442734875 | May 26 02:37:59 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 374771672 ps | ||
| T391 | /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3195369677 | May 26 02:37:38 PM PDT 24 | May 26 02:37:40 PM PDT 24 | 279173811 ps | ||
| T392 | /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3027922429 | May 26 02:36:59 PM PDT 24 | May 26 02:37:00 PM PDT 24 | 314593191 ps | ||
| T393 | /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2525508496 | May 26 02:37:53 PM PDT 24 | May 26 02:37:57 PM PDT 24 | 446545035 ps | ||
| T66 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4174106457 | May 26 02:37:02 PM PDT 24 | May 26 02:37:04 PM PDT 24 | 460974593 ps | ||
| T394 | /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3208632287 | May 26 02:37:42 PM PDT 24 | May 26 02:37:44 PM PDT 24 | 480825268 ps | ||
| T395 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.294478764 | May 26 02:37:01 PM PDT 24 | May 26 02:37:06 PM PDT 24 | 7307544794 ps | ||
| T396 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3801959944 | May 26 02:37:16 PM PDT 24 | May 26 02:37:19 PM PDT 24 | 1263715428 ps | ||
| T397 | /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.4068130228 | May 26 02:38:01 PM PDT 24 | May 26 02:38:03 PM PDT 24 | 476554919 ps | ||
| T70 | /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3317061529 | May 26 02:37:52 PM PDT 24 | May 26 02:37:56 PM PDT 24 | 579798757 ps | ||
| T398 | /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1965460156 | May 26 02:37:54 PM PDT 24 | May 26 02:37:58 PM PDT 24 | 474880727 ps | ||
| T399 | /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1006849109 | May 26 02:38:00 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 429921194 ps | ||
| T400 | /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2739796793 | May 26 02:37:37 PM PDT 24 | May 26 02:37:39 PM PDT 24 | 543961554 ps | ||
| T401 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2972208131 | May 26 02:37:07 PM PDT 24 | May 26 02:37:09 PM PDT 24 | 707543582 ps | ||
| T402 | /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3891229307 | May 26 02:37:37 PM PDT 24 | May 26 02:37:40 PM PDT 24 | 525122335 ps | ||
| T403 | /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3422912401 | May 26 02:37:59 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 373908449 ps | ||
| T71 | /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.94016089 | May 26 02:37:44 PM PDT 24 | May 26 02:37:46 PM PDT 24 | 322686101 ps | ||
| T404 | /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1272054255 | May 26 02:37:52 PM PDT 24 | May 26 02:37:56 PM PDT 24 | 342142843 ps | ||
| T405 | /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2204459683 | May 26 02:37:07 PM PDT 24 | May 26 02:37:10 PM PDT 24 | 1476032519 ps | ||
| T406 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.936492800 | May 26 02:37:22 PM PDT 24 | May 26 02:37:24 PM PDT 24 | 523343513 ps | ||
| T407 | /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3149463252 | May 26 02:37:56 PM PDT 24 | May 26 02:37:59 PM PDT 24 | 379844688 ps | ||
| T408 | /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1384534160 | May 26 02:37:54 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 2599985792 ps | ||
| T409 | /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.227524745 | May 26 02:37:54 PM PDT 24 | May 26 02:38:00 PM PDT 24 | 497614963 ps | ||
| T410 | /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.858595642 | May 26 02:37:51 PM PDT 24 | May 26 02:37:55 PM PDT 24 | 365816087 ps | ||
| T411 | /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.960684646 | May 26 02:37:06 PM PDT 24 | May 26 02:37:07 PM PDT 24 | 371386762 ps | ||
| T412 | /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1490235455 | May 26 02:37:17 PM PDT 24 | May 26 02:37:19 PM PDT 24 | 462018406 ps | ||
| T413 | /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1245047338 | May 26 02:37:07 PM PDT 24 | May 26 02:37:09 PM PDT 24 | 1329036336 ps | ||
| T414 | /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2474521885 | May 26 02:37:51 PM PDT 24 | May 26 02:37:54 PM PDT 24 | 549122395 ps | ||
| T415 | /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3378687707 | May 26 02:37:47 PM PDT 24 | May 26 02:37:49 PM PDT 24 | 1021641472 ps | ||
| T416 | /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2411920745 | May 26 02:37:15 PM PDT 24 | May 26 02:37:17 PM PDT 24 | 455138421 ps | ||
| T417 | /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.434682289 | May 26 02:37:21 PM PDT 24 | May 26 02:37:23 PM PDT 24 | 391143902 ps | ||
| T418 | /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3869806505 | May 26 02:37:43 PM PDT 24 | May 26 02:37:45 PM PDT 24 | 756807338 ps | ||
| T419 | /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3564066950 | May 26 02:37:18 PM PDT 24 | May 26 02:37:22 PM PDT 24 | 4634024270 ps | ||
| T420 | /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2918918942 | May 26 02:37:16 PM PDT 24 | May 26 02:37:17 PM PDT 24 | 286864143 ps | ||
| T421 | /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3123255739 | May 26 02:38:00 PM PDT 24 | May 26 02:38:02 PM PDT 24 | 293798993 ps | ||
| T422 | /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1348216465 | May 26 02:37:46 PM PDT 24 | May 26 02:37:48 PM PDT 24 | 480333071 ps | ||
| T423 | /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3997437969 | May 26 02:37:51 PM PDT 24 | May 26 02:37:55 PM PDT 24 | 556166324 ps | ||
| T424 | /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3526787931 | May 26 02:37:21 PM PDT 24 | May 26 02:37:23 PM PDT 24 | 385578922 ps | ||
| T425 | /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2527739014 | May 26 02:37:16 PM PDT 24 | May 26 02:37:26 PM PDT 24 | 8371715221 ps |
| Test location | /workspace/coverage/default/34.aon_timer_prescaler.176976889 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4048343289 ps |
| CPU time | 6.81 seconds |
| Started | May 26 01:54:44 PM PDT 24 |
| Finished | May 26 01:54:52 PM PDT 24 |
| Peak memory | 191904 kb |
| Host | smart-d93f74df-9ae1-471e-ab0d-4a92af1f36a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176976889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.176976889 |
| Directory | /workspace/34.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.4083682313 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 105673798158 ps |
| CPU time | 532.56 seconds |
| Started | May 26 01:54:58 PM PDT 24 |
| Finished | May 26 02:03:52 PM PDT 24 |
| Peak memory | 215064 kb |
| Host | smart-53383e6a-8378-47c7-abe9-f70aa3c76c2a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083682313 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.4083682313 |
| Directory | /workspace/44.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.aon_timer_stress_all.309576423 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 63311040648 ps |
| CPU time | 44.09 seconds |
| Started | May 26 01:54:40 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 192420 kb |
| Host | smart-40da7c7c-b219-4d0f-8b59-32acfa57615f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309576423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a ll.309576423 |
| Directory | /workspace/31.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2045915407 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8793909989 ps |
| CPU time | 4.61 seconds |
| Started | May 26 02:37:39 PM PDT 24 |
| Finished | May 26 02:37:44 PM PDT 24 |
| Peak memory | 198012 kb |
| Host | smart-9bb82513-08eb-4b4a-9e6f-f4bef96cd127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045915407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl _intg_err.2045915407 |
| Directory | /workspace/8.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2678061037 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 239402233370 ps |
| CPU time | 393.13 seconds |
| Started | May 26 01:54:25 PM PDT 24 |
| Finished | May 26 02:00:59 PM PDT 24 |
| Peak memory | 202500 kb |
| Host | smart-dd9db6e7-f467-42ce-981f-77d966ef9a2e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678061037 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2678061037 |
| Directory | /workspace/11.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3560061482 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 846657696691 ps |
| CPU time | 748.23 seconds |
| Started | May 26 01:54:35 PM PDT 24 |
| Finished | May 26 02:07:03 PM PDT 24 |
| Peak memory | 214188 kb |
| Host | smart-ea8a2059-a746-490d-a40d-b9f1cbce89fa |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560061482 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3560061482 |
| Directory | /workspace/22.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1257194563 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7951671284 ps |
| CPU time | 4.49 seconds |
| Started | May 26 02:37:22 PM PDT 24 |
| Finished | May 26 02:37:28 PM PDT 24 |
| Peak memory | 192296 kb |
| Host | smart-cb584d87-0d9a-4e85-8d39-78df71436d56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257194563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b it_bash.1257194563 |
| Directory | /workspace/3.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1756798051 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 100911242033 ps |
| CPU time | 551.42 seconds |
| Started | May 26 01:54:50 PM PDT 24 |
| Finished | May 26 02:04:03 PM PDT 24 |
| Peak memory | 212952 kb |
| Host | smart-daf2a2f3-4b4f-4291-bdf0-a9b6edcbf8d5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756798051 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1756798051 |
| Directory | /workspace/41.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3258573112 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2476374647418 ps |
| CPU time | 1028.35 seconds |
| Started | May 26 01:54:43 PM PDT 24 |
| Finished | May 26 02:11:52 PM PDT 24 |
| Peak memory | 209784 kb |
| Host | smart-a325442b-633e-4b0d-b662-a46daf2ff0dd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258573112 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3258573112 |
| Directory | /workspace/38.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1477527653 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 285614025929 ps |
| CPU time | 366.02 seconds |
| Started | May 26 01:54:37 PM PDT 24 |
| Finished | May 26 02:00:43 PM PDT 24 |
| Peak memory | 201984 kb |
| Host | smart-e44ac939-3dad-4a53-8bba-7808ee3ce344 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477527653 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1477527653 |
| Directory | /workspace/23.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1108920408 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 18845500847 ps |
| CPU time | 193.14 seconds |
| Started | May 26 01:54:39 PM PDT 24 |
| Finished | May 26 01:57:53 PM PDT 24 |
| Peak memory | 206884 kb |
| Host | smart-6bed7584-8ea3-4e38-b6aa-1a0c4b3de74e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108920408 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1108920408 |
| Directory | /workspace/28.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.aon_timer_stress_all.3621289547 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 48510545820 ps |
| CPU time | 80.05 seconds |
| Started | May 26 01:54:43 PM PDT 24 |
| Finished | May 26 01:56:04 PM PDT 24 |
| Peak memory | 184404 kb |
| Host | smart-0803ae95-57cc-410f-93ce-358a046a761e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621289547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_ all.3621289547 |
| Directory | /workspace/20.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.aon_timer_sec_cm.749503953 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7962089424 ps |
| CPU time | 13.62 seconds |
| Started | May 26 01:54:24 PM PDT 24 |
| Finished | May 26 01:54:38 PM PDT 24 |
| Peak memory | 215664 kb |
| Host | smart-1d098ffc-8528-437a-8bde-73194db09941 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749503953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.749503953 |
| Directory | /workspace/0.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3277078713 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 722702235710 ps |
| CPU time | 554.23 seconds |
| Started | May 26 01:54:14 PM PDT 24 |
| Finished | May 26 02:03:29 PM PDT 24 |
| Peak memory | 212776 kb |
| Host | smart-547c51d6-ddc8-4eed-80a9-967e92c0480d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277078713 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3277078713 |
| Directory | /workspace/2.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.aon_timer_stress_all.4257815320 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 388568621439 ps |
| CPU time | 161.42 seconds |
| Started | May 26 01:54:14 PM PDT 24 |
| Finished | May 26 01:56:56 PM PDT 24 |
| Peak memory | 192480 kb |
| Host | smart-a5e8dffe-2d1e-4988-8931-ae1ea00be7ee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257815320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a ll.4257815320 |
| Directory | /workspace/5.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3949903782 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 369779680967 ps |
| CPU time | 583.28 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 02:04:01 PM PDT 24 |
| Peak memory | 204152 kb |
| Host | smart-e46c9859-d4bd-4cc2-ab1a-99719eba27cd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949903782 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3949903782 |
| Directory | /workspace/10.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.4137186208 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 30461633616 ps |
| CPU time | 251.57 seconds |
| Started | May 26 01:54:32 PM PDT 24 |
| Finished | May 26 01:58:45 PM PDT 24 |
| Peak memory | 198568 kb |
| Host | smart-6e4dcdaf-64d2-43cf-a3ff-1de28f5c72c0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137186208 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.4137186208 |
| Directory | /workspace/25.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.35445819 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 21073842697 ps |
| CPU time | 77.31 seconds |
| Started | May 26 01:54:18 PM PDT 24 |
| Finished | May 26 01:55:36 PM PDT 24 |
| Peak memory | 206856 kb |
| Host | smart-806ebd3b-01a6-43b4-943b-cf89386a1ab6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35445819 -assert nopo stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.35445819 |
| Directory | /workspace/12.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.aon_timer_stress_all.2721852403 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 54406684138 ps |
| CPU time | 43.02 seconds |
| Started | May 26 01:54:35 PM PDT 24 |
| Finished | May 26 01:55:19 PM PDT 24 |
| Peak memory | 191948 kb |
| Host | smart-0759fbcf-a064-4f5b-b72e-d9a73a3c128b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721852403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_ all.2721852403 |
| Directory | /workspace/29.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1581618642 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 33887276809 ps |
| CPU time | 274.25 seconds |
| Started | May 26 01:54:47 PM PDT 24 |
| Finished | May 26 01:59:23 PM PDT 24 |
| Peak memory | 198636 kb |
| Host | smart-e6d01060-e020-42f0-a52e-fff7b91131a0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581618642 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1581618642 |
| Directory | /workspace/33.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3220419315 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 327393144019 ps |
| CPU time | 678.49 seconds |
| Started | May 26 01:54:40 PM PDT 24 |
| Finished | May 26 02:06:00 PM PDT 24 |
| Peak memory | 214168 kb |
| Host | smart-712f0428-6b4a-4ca5-8919-ff0f536b14aa |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220419315 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3220419315 |
| Directory | /workspace/29.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.626058975 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 137704785652 ps |
| CPU time | 362.55 seconds |
| Started | May 26 01:54:25 PM PDT 24 |
| Finished | May 26 02:00:28 PM PDT 24 |
| Peak memory | 215016 kb |
| Host | smart-0403f55a-59df-4711-871e-979a7a679626 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626058975 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.626058975 |
| Directory | /workspace/17.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3435718295 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 328470852846 ps |
| CPU time | 815.7 seconds |
| Started | May 26 01:54:21 PM PDT 24 |
| Finished | May 26 02:07:58 PM PDT 24 |
| Peak memory | 215004 kb |
| Host | smart-023229e0-5de4-4b9b-89c2-1753de3871ab |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435718295 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3435718295 |
| Directory | /workspace/6.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.aon_timer_stress_all.1183660324 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 179571117351 ps |
| CPU time | 261.96 seconds |
| Started | May 26 01:54:15 PM PDT 24 |
| Finished | May 26 01:58:39 PM PDT 24 |
| Peak memory | 192984 kb |
| Host | smart-17544f63-fd2a-4770-845e-73f95af55d19 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183660324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a ll.1183660324 |
| Directory | /workspace/7.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.777080376 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 31993889706 ps |
| CPU time | 327.16 seconds |
| Started | May 26 01:54:46 PM PDT 24 |
| Finished | May 26 02:00:14 PM PDT 24 |
| Peak memory | 198640 kb |
| Host | smart-20d327dc-a0e3-4fce-ac55-4da79cd99255 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777080376 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.777080376 |
| Directory | /workspace/36.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.aon_timer_stress_all.3549727989 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 142196833999 ps |
| CPU time | 187.3 seconds |
| Started | May 26 01:54:43 PM PDT 24 |
| Finished | May 26 01:57:51 PM PDT 24 |
| Peak memory | 184528 kb |
| Host | smart-3f0700c8-d86f-48e9-bebf-5187849da1e8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549727989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_ all.3549727989 |
| Directory | /workspace/32.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/36.aon_timer_stress_all.2813975039 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 65175424259 ps |
| CPU time | 24.08 seconds |
| Started | May 26 01:54:47 PM PDT 24 |
| Finished | May 26 01:55:12 PM PDT 24 |
| Peak memory | 192524 kb |
| Host | smart-3670e4ee-5e15-408c-988a-5b5b4d9a544d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813975039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_ all.2813975039 |
| Directory | /workspace/36.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/40.aon_timer_stress_all.2599355780 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 129899793952 ps |
| CPU time | 178.66 seconds |
| Started | May 26 01:54:44 PM PDT 24 |
| Finished | May 26 01:57:43 PM PDT 24 |
| Peak memory | 192920 kb |
| Host | smart-2cf1d389-85fb-406c-bd1c-890f3b86cfd1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599355780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_ all.2599355780 |
| Directory | /workspace/40.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/8.aon_timer_stress_all.792938986 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 64402928922 ps |
| CPU time | 93.87 seconds |
| Started | May 26 01:54:19 PM PDT 24 |
| Finished | May 26 01:55:54 PM PDT 24 |
| Peak memory | 192608 kb |
| Host | smart-c4264146-159c-464d-bea0-2e6135240bb3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792938986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al l.792938986 |
| Directory | /workspace/8.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.293420391 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 47002498502 ps |
| CPU time | 504.45 seconds |
| Started | May 26 01:54:35 PM PDT 24 |
| Finished | May 26 02:03:00 PM PDT 24 |
| Peak memory | 201424 kb |
| Host | smart-20b6b890-6a90-4b9d-a061-929081e43d9c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293420391 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.293420391 |
| Directory | /workspace/21.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.aon_timer_stress_all.222489039 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 350542815217 ps |
| CPU time | 241.72 seconds |
| Started | May 26 01:54:46 PM PDT 24 |
| Finished | May 26 01:58:49 PM PDT 24 |
| Peak memory | 192388 kb |
| Host | smart-8974ec33-ba17-42c5-ad09-057448ba7140 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222489039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a ll.222489039 |
| Directory | /workspace/34.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.aon_timer_stress_all.2214724023 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 367862561178 ps |
| CPU time | 32.41 seconds |
| Started | May 26 01:54:09 PM PDT 24 |
| Finished | May 26 01:54:43 PM PDT 24 |
| Peak memory | 191896 kb |
| Host | smart-f7ec8117-bcbf-46cb-8152-2f603dc78364 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214724023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a ll.2214724023 |
| Directory | /workspace/0.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.aon_timer_stress_all.801890934 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 328382063593 ps |
| CPU time | 435.48 seconds |
| Started | May 26 01:54:46 PM PDT 24 |
| Finished | May 26 02:02:03 PM PDT 24 |
| Peak memory | 192828 kb |
| Host | smart-63446160-ba44-45cc-a539-dd43e9422009 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801890934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a ll.801890934 |
| Directory | /workspace/37.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.aon_timer_stress_all.381833592 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 23752753104 ps |
| CPU time | 18.52 seconds |
| Started | May 26 01:54:49 PM PDT 24 |
| Finished | May 26 01:55:09 PM PDT 24 |
| Peak memory | 191900 kb |
| Host | smart-d3c4a7cc-45d2-4e82-8d77-45917dd1054e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381833592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a ll.381833592 |
| Directory | /workspace/26.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.4163736351 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 29145282755 ps |
| CPU time | 209.89 seconds |
| Started | May 26 01:54:11 PM PDT 24 |
| Finished | May 26 01:57:43 PM PDT 24 |
| Peak memory | 206864 kb |
| Host | smart-b15fd85f-6326-4129-9485-5d5116eb0aa2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163736351 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.4163736351 |
| Directory | /workspace/3.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2152877922 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 75048600684 ps |
| CPU time | 561.5 seconds |
| Started | May 26 01:54:46 PM PDT 24 |
| Finished | May 26 02:04:09 PM PDT 24 |
| Peak memory | 211848 kb |
| Host | smart-b7713b22-d6f4-416c-bd7c-f75f03d45014 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152877922 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2152877922 |
| Directory | /workspace/39.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2201642418 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 332562712174 ps |
| CPU time | 201.09 seconds |
| Started | May 26 01:54:54 PM PDT 24 |
| Finished | May 26 01:58:16 PM PDT 24 |
| Peak memory | 208596 kb |
| Host | smart-6c913057-1144-431f-bc57-cae2c027bc0d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201642418 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2201642418 |
| Directory | /workspace/42.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1876042298 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 289724433241 ps |
| CPU time | 229.24 seconds |
| Started | May 26 01:54:31 PM PDT 24 |
| Finished | May 26 01:58:22 PM PDT 24 |
| Peak memory | 208608 kb |
| Host | smart-78b549a9-61b8-48a4-8ade-f1ed87c9f217 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876042298 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1876042298 |
| Directory | /workspace/19.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.aon_timer_stress_all.2925947150 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 88082568957 ps |
| CPU time | 38.16 seconds |
| Started | May 26 01:54:47 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 191936 kb |
| Host | smart-9f9a57bb-8050-42de-9ff5-9e8f5ca9836e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925947150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_ all.2925947150 |
| Directory | /workspace/35.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.4215716344 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 10106378216 ps |
| CPU time | 74.29 seconds |
| Started | May 26 01:55:04 PM PDT 24 |
| Finished | May 26 01:56:19 PM PDT 24 |
| Peak memory | 206984 kb |
| Host | smart-ead17079-eb85-4fba-ae7f-29fe869782d8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215716344 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.4215716344 |
| Directory | /workspace/47.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.aon_timer_stress_all.583655283 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 163397632144 ps |
| CPU time | 69.51 seconds |
| Started | May 26 01:54:15 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 192364 kb |
| Host | smart-96693b91-1d8a-4b58-a0b5-dd5f42cf8f49 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583655283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a ll.583655283 |
| Directory | /workspace/10.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/16.aon_timer_stress_all.2221792630 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 180196030685 ps |
| CPU time | 276.39 seconds |
| Started | May 26 01:54:24 PM PDT 24 |
| Finished | May 26 01:59:01 PM PDT 24 |
| Peak memory | 192656 kb |
| Host | smart-bee684d2-08a7-4444-a8a5-7469333766f0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221792630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_ all.2221792630 |
| Directory | /workspace/16.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.aon_timer_stress_all.950630754 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 8471015523 ps |
| CPU time | 5.03 seconds |
| Started | May 26 01:54:14 PM PDT 24 |
| Finished | May 26 01:54:21 PM PDT 24 |
| Peak memory | 192748 kb |
| Host | smart-8553feb1-b068-48e8-922c-18828ad5d56c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950630754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al l.950630754 |
| Directory | /workspace/4.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2596041299 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 82196833500 ps |
| CPU time | 412.28 seconds |
| Started | May 26 01:54:43 PM PDT 24 |
| Finished | May 26 02:01:37 PM PDT 24 |
| Peak memory | 206768 kb |
| Host | smart-adc38744-0f71-4f69-be6c-204feed8bdeb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596041299 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2596041299 |
| Directory | /workspace/27.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.aon_timer_stress_all.2603873238 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 859013533920 ps |
| CPU time | 343.15 seconds |
| Started | May 26 01:54:33 PM PDT 24 |
| Finished | May 26 02:00:17 PM PDT 24 |
| Peak memory | 192704 kb |
| Host | smart-28c34990-7802-4bfe-8658-2ed5269cae49 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603873238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_ all.2603873238 |
| Directory | /workspace/14.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/24.aon_timer_stress_all.1934520498 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 222336345261 ps |
| CPU time | 76.79 seconds |
| Started | May 26 01:54:28 PM PDT 24 |
| Finished | May 26 01:55:46 PM PDT 24 |
| Peak memory | 192960 kb |
| Host | smart-d1427254-bef6-4d12-931e-77f0da597bc2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934520498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_ all.1934520498 |
| Directory | /workspace/24.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/42.aon_timer_stress_all.1682415460 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 167620364235 ps |
| CPU time | 66.25 seconds |
| Started | May 26 01:54:57 PM PDT 24 |
| Finished | May 26 01:56:05 PM PDT 24 |
| Peak memory | 191932 kb |
| Host | smart-2341c137-6e78-494c-99a2-511bf9294864 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682415460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_ all.1682415460 |
| Directory | /workspace/42.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.aon_timer_stress_all.4026038838 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 170269200884 ps |
| CPU time | 249.59 seconds |
| Started | May 26 01:55:02 PM PDT 24 |
| Finished | May 26 01:59:12 PM PDT 24 |
| Peak memory | 191940 kb |
| Host | smart-7859d29e-0cc0-4a05-a2ad-9f0b747f9433 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026038838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_ all.4026038838 |
| Directory | /workspace/47.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/30.aon_timer_stress_all.3604676363 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 298343559198 ps |
| CPU time | 104.87 seconds |
| Started | May 26 01:54:42 PM PDT 24 |
| Finished | May 26 01:56:28 PM PDT 24 |
| Peak memory | 192808 kb |
| Host | smart-13fa2385-5d2a-4bc6-bbe6-355c77e2cf8a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604676363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_ all.3604676363 |
| Directory | /workspace/30.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1540017104 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 131252670177 ps |
| CPU time | 342.04 seconds |
| Started | May 26 01:54:48 PM PDT 24 |
| Finished | May 26 02:00:32 PM PDT 24 |
| Peak memory | 201672 kb |
| Host | smart-36c2de5a-0f73-4cf7-97cb-5a558157f07d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540017104 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1540017104 |
| Directory | /workspace/32.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2726848844 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 184991537819 ps |
| CPU time | 629.25 seconds |
| Started | May 26 01:54:51 PM PDT 24 |
| Finished | May 26 02:05:21 PM PDT 24 |
| Peak memory | 213992 kb |
| Host | smart-72f99dba-4fa3-46d9-b313-76fe5526d942 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726848844 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2726848844 |
| Directory | /workspace/46.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.aon_timer_stress_all.1972601661 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 92542968035 ps |
| CPU time | 68.72 seconds |
| Started | May 26 01:54:24 PM PDT 24 |
| Finished | May 26 01:55:33 PM PDT 24 |
| Peak memory | 184108 kb |
| Host | smart-b7ab923d-ee8d-445b-b8ce-2705873ac60c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972601661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_ all.1972601661 |
| Directory | /workspace/19.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/28.aon_timer_stress_all.3009500064 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 200180002630 ps |
| CPU time | 51.75 seconds |
| Started | May 26 01:54:35 PM PDT 24 |
| Finished | May 26 01:55:27 PM PDT 24 |
| Peak memory | 192992 kb |
| Host | smart-32fac8e5-ff38-450b-b488-fa70f514913e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009500064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_ all.3009500064 |
| Directory | /workspace/28.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1729715523 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 14425048213 ps |
| CPU time | 106.66 seconds |
| Started | May 26 01:54:58 PM PDT 24 |
| Finished | May 26 01:56:46 PM PDT 24 |
| Peak memory | 206816 kb |
| Host | smart-39c31879-df33-4bee-87c2-a313fdf6078a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729715523 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1729715523 |
| Directory | /workspace/48.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.aon_timer_stress_all.2768116914 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 14574364455 ps |
| CPU time | 21.57 seconds |
| Started | May 26 01:54:25 PM PDT 24 |
| Finished | May 26 01:54:48 PM PDT 24 |
| Peak memory | 191844 kb |
| Host | smart-6682e1aa-5e73-4653-9867-cdb42894a9d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768116914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a ll.2768116914 |
| Directory | /workspace/1.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/18.aon_timer_stress_all.501800321 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 150051587348 ps |
| CPU time | 63.5 seconds |
| Started | May 26 01:54:31 PM PDT 24 |
| Finished | May 26 01:55:36 PM PDT 24 |
| Peak memory | 191900 kb |
| Host | smart-251b6ee6-2648-441d-beb8-0a34ab2d1785 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501800321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a ll.501800321 |
| Directory | /workspace/18.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.448738660 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 55911284441 ps |
| CPU time | 443.69 seconds |
| Started | May 26 01:54:34 PM PDT 24 |
| Finished | May 26 02:01:58 PM PDT 24 |
| Peak memory | 209128 kb |
| Host | smart-6df4d811-0d99-4ccb-9fc2-8ad67dcc1a09 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448738660 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.448738660 |
| Directory | /workspace/20.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.aon_timer_stress_all.1400114512 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 130848966995 ps |
| CPU time | 46.84 seconds |
| Started | May 26 01:54:49 PM PDT 24 |
| Finished | May 26 01:55:37 PM PDT 24 |
| Peak memory | 192608 kb |
| Host | smart-0741b333-d5af-49c4-bedb-dfe965101c87 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400114512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_ all.1400114512 |
| Directory | /workspace/43.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.aon_timer_stress_all.1998357913 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 201167971378 ps |
| CPU time | 284.03 seconds |
| Started | May 26 01:54:57 PM PDT 24 |
| Finished | May 26 01:59:42 PM PDT 24 |
| Peak memory | 191876 kb |
| Host | smart-0bd86a4c-ccfc-4846-b0e6-2de36d77ebe0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998357913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_ all.1998357913 |
| Directory | /workspace/48.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1774054000 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 377608132 ps |
| CPU time | 1.22 seconds |
| Started | May 26 02:37:45 PM PDT 24 |
| Finished | May 26 02:37:46 PM PDT 24 |
| Peak memory | 193168 kb |
| Host | smart-ed73b615-c07b-459e-9222-45486f5fb362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774054000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1774054000 |
| Directory | /workspace/11.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/default/41.aon_timer_stress_all.2080750819 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 43114628235 ps |
| CPU time | 58.3 seconds |
| Started | May 26 01:54:49 PM PDT 24 |
| Finished | May 26 01:55:49 PM PDT 24 |
| Peak memory | 191864 kb |
| Host | smart-10024611-f67c-4d80-8026-50d63351006e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080750819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_ all.2080750819 |
| Directory | /workspace/41.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/23.aon_timer_stress_all.2499026591 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 61098768664 ps |
| CPU time | 26.79 seconds |
| Started | May 26 01:54:30 PM PDT 24 |
| Finished | May 26 01:54:58 PM PDT 24 |
| Peak memory | 191948 kb |
| Host | smart-21684fdb-faa6-4a2d-b187-fb6affb0b607 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499026591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_ all.2499026591 |
| Directory | /workspace/23.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2253387094 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 71942892542 ps |
| CPU time | 364.26 seconds |
| Started | May 26 01:54:32 PM PDT 24 |
| Finished | May 26 02:00:37 PM PDT 24 |
| Peak memory | 214512 kb |
| Host | smart-fc575f5b-ddaf-4085-a7de-ddd0a4718d9e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253387094 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2253387094 |
| Directory | /workspace/30.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.aon_timer_stress_all.2419993939 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 151913576752 ps |
| CPU time | 59.36 seconds |
| Started | May 26 01:54:45 PM PDT 24 |
| Finished | May 26 01:55:45 PM PDT 24 |
| Peak memory | 191800 kb |
| Host | smart-1e05d8af-760e-49ba-9474-55b26de90a96 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419993939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_ all.2419993939 |
| Directory | /workspace/33.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/39.aon_timer_stress_all.2488604329 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 65712796826 ps |
| CPU time | 103.42 seconds |
| Started | May 26 01:54:46 PM PDT 24 |
| Finished | May 26 01:56:31 PM PDT 24 |
| Peak memory | 192616 kb |
| Host | smart-d71e95c0-42bc-458d-9ab6-ab5a35f8a540 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488604329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_ all.2488604329 |
| Directory | /workspace/39.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1932730853 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 226188834052 ps |
| CPU time | 613.32 seconds |
| Started | May 26 01:54:53 PM PDT 24 |
| Finished | May 26 02:05:08 PM PDT 24 |
| Peak memory | 205608 kb |
| Host | smart-b7dba638-85de-4ec2-ab04-3ae88f1f4ba1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932730853 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1932730853 |
| Directory | /workspace/43.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.534750628 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 177621570776 ps |
| CPU time | 196.02 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:57:34 PM PDT 24 |
| Peak memory | 200412 kb |
| Host | smart-cf8602a1-b241-4c7e-9177-d7dbf1477fa0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534750628 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.534750628 |
| Directory | /workspace/8.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.aon_timer_stress_all.1548009828 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 125333523584 ps |
| CPU time | 15.06 seconds |
| Started | May 26 01:54:24 PM PDT 24 |
| Finished | May 26 01:54:40 PM PDT 24 |
| Peak memory | 192432 kb |
| Host | smart-d4a011dc-774c-465b-aa27-453b2366d974 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548009828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_ all.1548009828 |
| Directory | /workspace/11.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/30.aon_timer_jump.156715482 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 447498715 ps |
| CPU time | 1.29 seconds |
| Started | May 26 01:54:40 PM PDT 24 |
| Finished | May 26 01:54:43 PM PDT 24 |
| Peak memory | 196648 kb |
| Host | smart-4a72ddb9-ce3c-41a1-b9d9-4a37652bea42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=156715482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.156715482 |
| Directory | /workspace/30.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.918435785 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 83534553321 ps |
| CPU time | 135.04 seconds |
| Started | May 26 01:54:45 PM PDT 24 |
| Finished | May 26 01:57:01 PM PDT 24 |
| Peak memory | 206868 kb |
| Host | smart-996bafd2-a13a-4f36-a6da-9be265d0ee85 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918435785 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.918435785 |
| Directory | /workspace/40.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.405216202 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 131553938499 ps |
| CPU time | 214.57 seconds |
| Started | May 26 01:54:54 PM PDT 24 |
| Finished | May 26 01:58:30 PM PDT 24 |
| Peak memory | 199616 kb |
| Host | smart-17fb8c71-47b5-4a68-9f18-3febb9d497a4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405216202 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.405216202 |
| Directory | /workspace/45.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.aon_timer_stress_all.3733861189 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 59954992083 ps |
| CPU time | 31.77 seconds |
| Started | May 26 01:54:52 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 191908 kb |
| Host | smart-faf8efb5-8804-41be-9435-c70ccdfb16da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733861189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_ all.3733861189 |
| Directory | /workspace/46.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/5.aon_timer_jump.1914074180 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 535126102 ps |
| CPU time | 1.59 seconds |
| Started | May 26 01:54:26 PM PDT 24 |
| Finished | May 26 01:54:28 PM PDT 24 |
| Peak memory | 196456 kb |
| Host | smart-e590989f-6204-439c-bd06-c66ab60fd411 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1914074180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1914074180 |
| Directory | /workspace/5.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2700171523 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 199895658158 ps |
| CPU time | 418.99 seconds |
| Started | May 26 01:54:30 PM PDT 24 |
| Finished | May 26 02:01:30 PM PDT 24 |
| Peak memory | 210896 kb |
| Host | smart-cf2cc86e-b397-4385-9a34-24d8c272f923 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700171523 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2700171523 |
| Directory | /workspace/14.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.aon_timer_jump.1416340872 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 340980351 ps |
| CPU time | 1.08 seconds |
| Started | May 26 01:54:30 PM PDT 24 |
| Finished | May 26 01:54:33 PM PDT 24 |
| Peak memory | 196428 kb |
| Host | smart-bf049d60-c6bd-4445-8fff-35ae6358685a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1416340872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1416340872 |
| Directory | /workspace/16.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/26.aon_timer_jump.837578339 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 509870568 ps |
| CPU time | 1.25 seconds |
| Started | May 26 01:54:44 PM PDT 24 |
| Finished | May 26 01:54:46 PM PDT 24 |
| Peak memory | 196448 kb |
| Host | smart-1c882131-dac8-4a46-a393-57c6d621488d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837578339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.837578339 |
| Directory | /workspace/26.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/31.aon_timer_jump.1759640237 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 591844822 ps |
| CPU time | 1.56 seconds |
| Started | May 26 01:54:43 PM PDT 24 |
| Finished | May 26 01:54:45 PM PDT 24 |
| Peak memory | 196504 kb |
| Host | smart-e5affdf4-ba04-4d87-8098-835d8d27bab5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1759640237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1759640237 |
| Directory | /workspace/31.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.375728672 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 108696687902 ps |
| CPU time | 325.12 seconds |
| Started | May 26 01:54:41 PM PDT 24 |
| Finished | May 26 02:00:07 PM PDT 24 |
| Peak memory | 206868 kb |
| Host | smart-5060d825-5880-4afd-9939-15e880df9072 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375728672 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.375728672 |
| Directory | /workspace/31.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.aon_timer_jump.1924987265 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 477298422 ps |
| CPU time | 0.78 seconds |
| Started | May 26 01:54:48 PM PDT 24 |
| Finished | May 26 01:54:50 PM PDT 24 |
| Peak memory | 196480 kb |
| Host | smart-ed79a13e-5f57-4315-bc8c-4c6f321f64fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924987265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1924987265 |
| Directory | /workspace/34.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/37.aon_timer_jump.567021784 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 463960066 ps |
| CPU time | 1.35 seconds |
| Started | May 26 01:54:48 PM PDT 24 |
| Finished | May 26 01:54:50 PM PDT 24 |
| Peak memory | 196412 kb |
| Host | smart-692c21de-5414-4de2-bca8-f60bb196f201 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=567021784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.567021784 |
| Directory | /workspace/37.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/44.aon_timer_stress_all.3202192956 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 172757086838 ps |
| CPU time | 277.44 seconds |
| Started | May 26 01:54:54 PM PDT 24 |
| Finished | May 26 01:59:33 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-1c7109e6-46dd-48c2-b457-647ee5446f09 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202192956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_ all.3202192956 |
| Directory | /workspace/44.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.aon_timer_jump.2616785115 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 389136474 ps |
| CPU time | 0.88 seconds |
| Started | May 26 01:54:55 PM PDT 24 |
| Finished | May 26 01:54:57 PM PDT 24 |
| Peak memory | 196480 kb |
| Host | smart-3c6a3785-72c4-43a8-a777-0129c0e7e216 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616785115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2616785115 |
| Directory | /workspace/45.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/9.aon_timer_jump.1723673225 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 425628822 ps |
| CPU time | 0.76 seconds |
| Started | May 26 01:54:25 PM PDT 24 |
| Finished | May 26 01:54:26 PM PDT 24 |
| Peak memory | 196428 kb |
| Host | smart-4e38457b-bc1a-4b1c-b52a-803261f7ebef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1723673225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1723673225 |
| Directory | /workspace/9.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2659919597 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 25351543132 ps |
| CPU time | 200.35 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:57:37 PM PDT 24 |
| Peak memory | 206892 kb |
| Host | smart-31071f62-135e-44ae-bff7-b72e0103b261 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659919597 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2659919597 |
| Directory | /workspace/0.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.aon_timer_jump.4091390966 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 445793076 ps |
| CPU time | 1.29 seconds |
| Started | May 26 01:54:18 PM PDT 24 |
| Finished | May 26 01:54:20 PM PDT 24 |
| Peak memory | 196464 kb |
| Host | smart-6f33ea85-8026-4566-82ab-d8d525097631 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091390966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4091390966 |
| Directory | /workspace/11.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/21.aon_timer_jump.1553745222 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 345102144 ps |
| CPU time | 0.82 seconds |
| Started | May 26 01:54:29 PM PDT 24 |
| Finished | May 26 01:54:31 PM PDT 24 |
| Peak memory | 196448 kb |
| Host | smart-46c1848d-c68b-41b0-82b9-f993e426799c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553745222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1553745222 |
| Directory | /workspace/21.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.4254288616 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 66895006919 ps |
| CPU time | 357.16 seconds |
| Started | May 26 01:54:31 PM PDT 24 |
| Finished | May 26 02:00:30 PM PDT 24 |
| Peak memory | 208824 kb |
| Host | smart-6991c041-1968-4a3b-bc6b-b1945db4edce |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254288616 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.4254288616 |
| Directory | /workspace/24.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.aon_timer_jump.2139711599 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 444917081 ps |
| CPU time | 1.33 seconds |
| Started | May 26 01:54:45 PM PDT 24 |
| Finished | May 26 01:54:48 PM PDT 24 |
| Peak memory | 196460 kb |
| Host | smart-64062afa-4597-49b9-b03e-a0cb7ccb79ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139711599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2139711599 |
| Directory | /workspace/35.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/13.aon_timer_stress_all.455754134 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 62506722348 ps |
| CPU time | 24.92 seconds |
| Started | May 26 01:54:29 PM PDT 24 |
| Finished | May 26 01:54:55 PM PDT 24 |
| Peak memory | 192412 kb |
| Host | smart-b9777578-6905-48da-9818-74017a29be51 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455754134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a ll.455754134 |
| Directory | /workspace/13.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/17.aon_timer_stress_all.4052209490 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 230837104770 ps |
| CPU time | 179.86 seconds |
| Started | May 26 01:54:29 PM PDT 24 |
| Finished | May 26 01:57:30 PM PDT 24 |
| Peak memory | 184316 kb |
| Host | smart-a051c036-da20-4cac-a85a-bb603e4dece0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052209490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_ all.4052209490 |
| Directory | /workspace/17.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/19.aon_timer_jump.2737229844 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 468994091 ps |
| CPU time | 1.24 seconds |
| Started | May 26 01:54:29 PM PDT 24 |
| Finished | May 26 01:54:32 PM PDT 24 |
| Peak memory | 196476 kb |
| Host | smart-cc454223-03e7-494b-ae06-3de2fad6947b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737229844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2737229844 |
| Directory | /workspace/19.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/2.aon_timer_jump.1276713320 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 360215218 ps |
| CPU time | 0.71 seconds |
| Started | May 26 01:54:09 PM PDT 24 |
| Finished | May 26 01:54:11 PM PDT 24 |
| Peak memory | 196412 kb |
| Host | smart-2601fe0f-9363-4f3b-bf5c-d294c6f6d41a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1276713320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1276713320 |
| Directory | /workspace/2.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/27.aon_timer_stress_all.1942768718 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 149288976801 ps |
| CPU time | 63.97 seconds |
| Started | May 26 01:54:48 PM PDT 24 |
| Finished | May 26 01:55:53 PM PDT 24 |
| Peak memory | 191900 kb |
| Host | smart-5dfce3c5-abdf-4bdb-b8b0-c7e8bd2487cd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942768718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_ all.1942768718 |
| Directory | /workspace/27.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/32.aon_timer_jump.699314113 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 446458099 ps |
| CPU time | 0.65 seconds |
| Started | May 26 01:54:46 PM PDT 24 |
| Finished | May 26 01:54:48 PM PDT 24 |
| Peak memory | 196328 kb |
| Host | smart-82595e79-0f44-4223-8748-691f4ed4e077 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699314113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.699314113 |
| Directory | /workspace/32.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/48.aon_timer_jump.841616306 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 454351213 ps |
| CPU time | 0.8 seconds |
| Started | May 26 01:55:06 PM PDT 24 |
| Finished | May 26 01:55:08 PM PDT 24 |
| Peak memory | 196476 kb |
| Host | smart-35663567-8812-4d65-a1d9-438ceac287e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=841616306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.841616306 |
| Directory | /workspace/48.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/6.aon_timer_stress_all.1325057436 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 57669788038 ps |
| CPU time | 10.72 seconds |
| Started | May 26 01:54:10 PM PDT 24 |
| Finished | May 26 01:54:23 PM PDT 24 |
| Peak memory | 191940 kb |
| Host | smart-b8791cb2-b6ad-4f62-8fba-e79c3f2e1fb8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325057436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a ll.1325057436 |
| Directory | /workspace/6.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/9.aon_timer_stress_all.1362724681 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 175144276185 ps |
| CPU time | 281.4 seconds |
| Started | May 26 01:54:15 PM PDT 24 |
| Finished | May 26 01:58:58 PM PDT 24 |
| Peak memory | 191936 kb |
| Host | smart-3d339c6e-2cb3-4c59-9f0b-e9f573f62b2f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362724681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a ll.1362724681 |
| Directory | /workspace/9.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/18.aon_timer_jump.240274387 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 559704882 ps |
| CPU time | 1.47 seconds |
| Started | May 26 01:54:28 PM PDT 24 |
| Finished | May 26 01:54:30 PM PDT 24 |
| Peak memory | 196460 kb |
| Host | smart-a659242b-dc50-406e-8256-9ff6c80994d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240274387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.240274387 |
| Directory | /workspace/18.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.973323436 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 9717091766 ps |
| CPU time | 107.94 seconds |
| Started | May 26 01:54:29 PM PDT 24 |
| Finished | May 26 01:56:18 PM PDT 24 |
| Peak memory | 206884 kb |
| Host | smart-e10e9621-fb8e-4f01-bc63-7bcbfcfbf68d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973323436 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.973323436 |
| Directory | /workspace/18.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.aon_timer_stress_all.1903271806 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 450866663433 ps |
| CPU time | 408.54 seconds |
| Started | May 26 01:54:10 PM PDT 24 |
| Finished | May 26 02:01:01 PM PDT 24 |
| Peak memory | 192400 kb |
| Host | smart-cdc83ef6-0f02-4d40-b9a6-16e7f6e3103e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903271806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a ll.1903271806 |
| Directory | /workspace/3.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/41.aon_timer_jump.3036881667 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 473918563 ps |
| CPU time | 1.34 seconds |
| Started | May 26 01:54:51 PM PDT 24 |
| Finished | May 26 01:54:53 PM PDT 24 |
| Peak memory | 196436 kb |
| Host | smart-948a8063-b723-45af-87f6-d4ac51d6ce86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036881667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3036881667 |
| Directory | /workspace/41.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/43.aon_timer_jump.3561370585 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 480500614 ps |
| CPU time | 1.22 seconds |
| Started | May 26 01:54:51 PM PDT 24 |
| Finished | May 26 01:54:53 PM PDT 24 |
| Peak memory | 196404 kb |
| Host | smart-6832034e-ec47-4cd8-a00f-bf0f75ff6568 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3561370585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3561370585 |
| Directory | /workspace/43.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/13.aon_timer_jump.890890125 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 557607539 ps |
| CPU time | 0.8 seconds |
| Started | May 26 01:54:35 PM PDT 24 |
| Finished | May 26 01:54:36 PM PDT 24 |
| Peak memory | 196372 kb |
| Host | smart-2f2ef525-4515-472e-9f85-0cf298a93a06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=890890125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.890890125 |
| Directory | /workspace/13.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2677466952 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 220165770525 ps |
| CPU time | 401.38 seconds |
| Started | May 26 01:54:41 PM PDT 24 |
| Finished | May 26 02:01:23 PM PDT 24 |
| Peak memory | 202736 kb |
| Host | smart-669c2f8f-83b0-4f28-a27c-767b05162076 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677466952 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2677466952 |
| Directory | /workspace/15.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.aon_timer_stress_all.27768520 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 883150091638 ps |
| CPU time | 1145.77 seconds |
| Started | May 26 01:54:43 PM PDT 24 |
| Finished | May 26 02:13:49 PM PDT 24 |
| Peak memory | 192508 kb |
| Host | smart-a95427ab-e9c3-4ad7-87bb-507765f876ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27768520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_al l.27768520 |
| Directory | /workspace/21.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/25.aon_timer_jump.3300679714 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 475112855 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:54:41 PM PDT 24 |
| Finished | May 26 01:54:43 PM PDT 24 |
| Peak memory | 196440 kb |
| Host | smart-f459e2da-b313-489a-a750-5474db6739cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3300679714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3300679714 |
| Directory | /workspace/25.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.980875232 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 18294405067 ps |
| CPU time | 196.32 seconds |
| Started | May 26 01:54:46 PM PDT 24 |
| Finished | May 26 01:58:04 PM PDT 24 |
| Peak memory | 198668 kb |
| Host | smart-b8101afa-4edd-4829-a587-0218fe8d4a8b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980875232 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.980875232 |
| Directory | /workspace/26.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.aon_timer_jump.3890442562 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 517922788 ps |
| CPU time | 1.02 seconds |
| Started | May 26 01:54:42 PM PDT 24 |
| Finished | May 26 01:54:44 PM PDT 24 |
| Peak memory | 196436 kb |
| Host | smart-85151400-1c1b-4aac-b4f5-3ca59ffe9232 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3890442562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3890442562 |
| Directory | /workspace/27.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/38.aon_timer_jump.2605113146 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 559845947 ps |
| CPU time | 1.52 seconds |
| Started | May 26 01:54:45 PM PDT 24 |
| Finished | May 26 01:54:48 PM PDT 24 |
| Peak memory | 196496 kb |
| Host | smart-c06dfa22-e191-4502-940c-8c58aab8d2d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605113146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2605113146 |
| Directory | /workspace/38.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/38.aon_timer_stress_all.1926705109 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 47204575042 ps |
| CPU time | 38.16 seconds |
| Started | May 26 01:54:46 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 191920 kb |
| Host | smart-876c28a9-59ec-4972-8f88-39fcbb4a239d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926705109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_ all.1926705109 |
| Directory | /workspace/38.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/39.aon_timer_jump.1935860023 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 552895158 ps |
| CPU time | 0.88 seconds |
| Started | May 26 01:54:43 PM PDT 24 |
| Finished | May 26 01:54:45 PM PDT 24 |
| Peak memory | 196424 kb |
| Host | smart-e1c49654-19b9-41fb-bf8e-214e209e507b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1935860023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1935860023 |
| Directory | /workspace/39.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/40.aon_timer_jump.4033169984 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 575919120 ps |
| CPU time | 1 seconds |
| Started | May 26 01:54:48 PM PDT 24 |
| Finished | May 26 01:54:50 PM PDT 24 |
| Peak memory | 196432 kb |
| Host | smart-c2467321-644d-4608-9eeb-fd8afde904f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033169984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4033169984 |
| Directory | /workspace/40.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/29.aon_timer_jump.3310574073 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 363976828 ps |
| CPU time | 0.76 seconds |
| Started | May 26 01:54:50 PM PDT 24 |
| Finished | May 26 01:54:51 PM PDT 24 |
| Peak memory | 196428 kb |
| Host | smart-95f8a20e-6772-488a-aa06-9c98b62aad2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3310574073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3310574073 |
| Directory | /workspace/29.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.4291562562 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 43558775944 ps |
| CPU time | 469.13 seconds |
| Started | May 26 01:54:46 PM PDT 24 |
| Finished | May 26 02:02:37 PM PDT 24 |
| Peak memory | 200880 kb |
| Host | smart-5382a80c-5147-46b5-ad17-f42ed2375774 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291562562 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.4291562562 |
| Directory | /workspace/34.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.aon_timer_jump.1841749653 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 544636247 ps |
| CPU time | 0.78 seconds |
| Started | May 26 01:54:50 PM PDT 24 |
| Finished | May 26 01:54:51 PM PDT 24 |
| Peak memory | 196420 kb |
| Host | smart-e3602edb-2709-4319-9479-9442437ecca5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1841749653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1841749653 |
| Directory | /workspace/36.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/4.aon_timer_jump.2635949914 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 520987594 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:54:18 PM PDT 24 |
| Peak memory | 196408 kb |
| Host | smart-320f8b69-076a-43d0-983a-34d2c1095b21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635949914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2635949914 |
| Directory | /workspace/4.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.4091199103 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 33210691613 ps |
| CPU time | 123.05 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:56:20 PM PDT 24 |
| Peak memory | 198624 kb |
| Host | smart-44af9b46-0112-4f00-a097-cd7d9160bfc1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091199103 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.4091199103 |
| Directory | /workspace/4.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.aon_timer_jump.3746044276 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 534090407 ps |
| CPU time | 1.07 seconds |
| Started | May 26 01:54:54 PM PDT 24 |
| Finished | May 26 01:54:56 PM PDT 24 |
| Peak memory | 196440 kb |
| Host | smart-c5095759-e0f5-43cd-8b23-e902f8f685f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746044276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3746044276 |
| Directory | /workspace/42.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/45.aon_timer_stress_all.3076201362 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 554075861930 ps |
| CPU time | 233.35 seconds |
| Started | May 26 01:54:55 PM PDT 24 |
| Finished | May 26 01:58:49 PM PDT 24 |
| Peak memory | 191900 kb |
| Host | smart-6a290439-3a1a-4745-ae99-0f0604fac9b7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076201362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_ all.3076201362 |
| Directory | /workspace/45.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/46.aon_timer_jump.1664340176 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 468846649 ps |
| CPU time | 0.91 seconds |
| Started | May 26 01:54:52 PM PDT 24 |
| Finished | May 26 01:54:54 PM PDT 24 |
| Peak memory | 196444 kb |
| Host | smart-fbca47b1-ddb0-4e99-ad03-24ee9e340796 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664340176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1664340176 |
| Directory | /workspace/46.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/47.aon_timer_jump.1087871226 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 605822474 ps |
| CPU time | 0.82 seconds |
| Started | May 26 01:54:51 PM PDT 24 |
| Finished | May 26 01:54:53 PM PDT 24 |
| Peak memory | 196432 kb |
| Host | smart-ce1ecd97-1739-4ca4-9da1-46020339777f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1087871226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1087871226 |
| Directory | /workspace/47.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/7.aon_timer_jump.2473012874 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 642798425 ps |
| CPU time | 0.76 seconds |
| Started | May 26 01:54:15 PM PDT 24 |
| Finished | May 26 01:54:17 PM PDT 24 |
| Peak memory | 196444 kb |
| Host | smart-fdb752cf-54db-4a35-8bef-b75bed818fe0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473012874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2473012874 |
| Directory | /workspace/7.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/0.aon_timer_jump.2211006219 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 459926484 ps |
| CPU time | 0.76 seconds |
| Started | May 26 01:54:11 PM PDT 24 |
| Finished | May 26 01:54:13 PM PDT 24 |
| Peak memory | 196428 kb |
| Host | smart-6b5e4144-58a1-4492-8232-5549b6f1c620 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2211006219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2211006219 |
| Directory | /workspace/0.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3552425968 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 29225472389 ps |
| CPU time | 121.18 seconds |
| Started | May 26 01:54:32 PM PDT 24 |
| Finished | May 26 01:56:34 PM PDT 24 |
| Peak memory | 198636 kb |
| Host | smart-f36b4ff9-8535-4ea5-aa92-37262dad7bf6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552425968 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3552425968 |
| Directory | /workspace/13.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.aon_timer_jump.286614601 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 369444019 ps |
| CPU time | 1.19 seconds |
| Started | May 26 01:54:30 PM PDT 24 |
| Finished | May 26 01:54:32 PM PDT 24 |
| Peak memory | 196332 kb |
| Host | smart-c7b6e2cf-88a5-412c-bd29-9503a3a136d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286614601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.286614601 |
| Directory | /workspace/14.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/2.aon_timer_stress_all.2549052526 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 206689158427 ps |
| CPU time | 86.03 seconds |
| Started | May 26 01:54:06 PM PDT 24 |
| Finished | May 26 01:55:34 PM PDT 24 |
| Peak memory | 191888 kb |
| Host | smart-63945b39-6faa-45df-8c42-f8d178506d24 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549052526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a ll.2549052526 |
| Directory | /workspace/2.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/22.aon_timer_stress_all.3584660394 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 318791692199 ps |
| CPU time | 111.7 seconds |
| Started | May 26 01:54:31 PM PDT 24 |
| Finished | May 26 01:56:24 PM PDT 24 |
| Peak memory | 191936 kb |
| Host | smart-b29a98dd-d574-4cc5-a134-364b83439c07 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584660394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_ all.3584660394 |
| Directory | /workspace/22.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/28.aon_timer_jump.1924383877 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 447042947 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:54:44 PM PDT 24 |
| Finished | May 26 01:54:46 PM PDT 24 |
| Peak memory | 196528 kb |
| Host | smart-d4030924-d479-408a-80c9-b0883fe1ff14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924383877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1924383877 |
| Directory | /workspace/28.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1045765203 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 36717143406 ps |
| CPU time | 141.19 seconds |
| Started | May 26 01:54:46 PM PDT 24 |
| Finished | May 26 01:57:08 PM PDT 24 |
| Peak memory | 214436 kb |
| Host | smart-60f6155e-21e7-4076-a734-8ab9829ce209 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045765203 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1045765203 |
| Directory | /workspace/37.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1833974537 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 117358415969 ps |
| CPU time | 256.75 seconds |
| Started | May 26 01:54:56 PM PDT 24 |
| Finished | May 26 01:59:14 PM PDT 24 |
| Peak memory | 209124 kb |
| Host | smart-40d73ac5-0995-4a3e-aec4-d0e4c50d1857 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833974537 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1833974537 |
| Directory | /workspace/49.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.aon_timer_jump.1481155810 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 493267844 ps |
| CPU time | 0.8 seconds |
| Started | May 26 01:54:11 PM PDT 24 |
| Finished | May 26 01:54:14 PM PDT 24 |
| Peak memory | 196392 kb |
| Host | smart-eb0d990f-1d26-4199-a9d8-d202c2911213 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1481155810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1481155810 |
| Directory | /workspace/6.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/8.aon_timer_jump.545580407 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 437078295 ps |
| CPU time | 0.9 seconds |
| Started | May 26 01:54:18 PM PDT 24 |
| Finished | May 26 01:54:20 PM PDT 24 |
| Peak memory | 196432 kb |
| Host | smart-e732d997-2222-4484-8c6e-8a497382ac44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=545580407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.545580407 |
| Directory | /workspace/8.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/1.aon_timer_jump.2444150945 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 516758469 ps |
| CPU time | 1.46 seconds |
| Started | May 26 01:54:36 PM PDT 24 |
| Finished | May 26 01:54:38 PM PDT 24 |
| Peak memory | 196440 kb |
| Host | smart-f9177b80-b5e8-4ac3-8120-032bd7d47419 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2444150945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2444150945 |
| Directory | /workspace/1.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/12.aon_timer_jump.686998133 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 386119873 ps |
| CPU time | 0.72 seconds |
| Started | May 26 01:54:15 PM PDT 24 |
| Finished | May 26 01:54:17 PM PDT 24 |
| Peak memory | 196412 kb |
| Host | smart-c756223a-d5bf-4d2d-a93d-ec82e218193d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686998133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.686998133 |
| Directory | /workspace/12.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/15.aon_timer_jump.1571172706 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 498935420 ps |
| CPU time | 0.78 seconds |
| Started | May 26 01:54:26 PM PDT 24 |
| Finished | May 26 01:54:27 PM PDT 24 |
| Peak memory | 196424 kb |
| Host | smart-837d5960-f7ea-4814-b37b-fdc17e62be38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1571172706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1571172706 |
| Directory | /workspace/15.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/17.aon_timer_jump.63222997 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 589888411 ps |
| CPU time | 0.86 seconds |
| Started | May 26 01:54:33 PM PDT 24 |
| Finished | May 26 01:54:34 PM PDT 24 |
| Peak memory | 196472 kb |
| Host | smart-4fe5cf3f-18cb-46b0-8958-e0d8ef351f85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63222997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.63222997 |
| Directory | /workspace/17.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/20.aon_timer_jump.1978422467 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 489896407 ps |
| CPU time | 0.79 seconds |
| Started | May 26 01:54:39 PM PDT 24 |
| Finished | May 26 01:54:40 PM PDT 24 |
| Peak memory | 196400 kb |
| Host | smart-e8690842-a8bc-4a6c-b9e6-a95ddd5d4c29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978422467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1978422467 |
| Directory | /workspace/20.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/3.aon_timer_jump.370145708 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 556018261 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:54:13 PM PDT 24 |
| Finished | May 26 01:54:15 PM PDT 24 |
| Peak memory | 196420 kb |
| Host | smart-0ad98906-48ea-4c64-8625-ea34566cb284 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=370145708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.370145708 |
| Directory | /workspace/3.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/33.aon_timer_jump.52721290 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 429652903 ps |
| CPU time | 0.71 seconds |
| Started | May 26 01:54:43 PM PDT 24 |
| Finished | May 26 01:54:45 PM PDT 24 |
| Peak memory | 196516 kb |
| Host | smart-aac68303-1d0c-4352-bcc2-e99efee17b24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52721290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.52721290 |
| Directory | /workspace/33.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/49.aon_timer_stress_all.2979702111 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 289549184319 ps |
| CPU time | 426.72 seconds |
| Started | May 26 01:54:57 PM PDT 24 |
| Finished | May 26 02:02:05 PM PDT 24 |
| Peak memory | 191952 kb |
| Host | smart-90d6e23c-ce57-40f6-acb0-ec715e52d20b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979702111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_ all.2979702111 |
| Directory | /workspace/49.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2972208131 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 707543582 ps |
| CPU time | 1.06 seconds |
| Started | May 26 02:37:07 PM PDT 24 |
| Finished | May 26 02:37:09 PM PDT 24 |
| Peak memory | 194264 kb |
| Host | smart-19b3d55f-d5ff-4b3c-8901-b879044b3d10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972208131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a liasing.2972208131 |
| Directory | /workspace/0.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.294478764 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 7307544794 ps |
| CPU time | 4.12 seconds |
| Started | May 26 02:37:01 PM PDT 24 |
| Finished | May 26 02:37:06 PM PDT 24 |
| Peak memory | 192156 kb |
| Host | smart-d8cfbf15-5b51-4007-97a7-f29c41c7b7bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294478764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi t_bash.294478764 |
| Directory | /workspace/0.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2871782797 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 690388274 ps |
| CPU time | 0.88 seconds |
| Started | May 26 02:37:01 PM PDT 24 |
| Finished | May 26 02:37:03 PM PDT 24 |
| Peak memory | 183812 kb |
| Host | smart-fe01be2c-782c-4af7-97cd-09ba405762fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871782797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h w_reset.2871782797 |
| Directory | /workspace/0.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1424924063 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 412896884 ps |
| CPU time | 1.19 seconds |
| Started | May 26 02:37:07 PM PDT 24 |
| Finished | May 26 02:37:09 PM PDT 24 |
| Peak memory | 195952 kb |
| Host | smart-958d8d21-f7b1-4618-a730-a3ef7cd6ae55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424924063 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1424924063 |
| Directory | /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4174106457 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 460974593 ps |
| CPU time | 0.9 seconds |
| Started | May 26 02:37:02 PM PDT 24 |
| Finished | May 26 02:37:04 PM PDT 24 |
| Peak memory | 194108 kb |
| Host | smart-d085c38e-5a12-4826-8bf2-eb17c92e5677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174106457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.4174106457 |
| Directory | /workspace/0.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3027922429 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 314593191 ps |
| CPU time | 0.71 seconds |
| Started | May 26 02:36:59 PM PDT 24 |
| Finished | May 26 02:37:00 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-56b33b7e-2695-4b4b-b11e-c8aaba1d69ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027922429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3027922429 |
| Directory | /workspace/0.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2958830122 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 318782960 ps |
| CPU time | 0.85 seconds |
| Started | May 26 02:36:59 PM PDT 24 |
| Finished | May 26 02:37:01 PM PDT 24 |
| Peak memory | 183564 kb |
| Host | smart-706e620f-073e-4952-8488-f54b8c2b79f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958830122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t imer_mem_partial_access.2958830122 |
| Directory | /workspace/0.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1596469419 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 361692240 ps |
| CPU time | 0.54 seconds |
| Started | May 26 02:36:58 PM PDT 24 |
| Finished | May 26 02:36:59 PM PDT 24 |
| Peak memory | 183628 kb |
| Host | smart-0a706130-a6c3-4587-8eb0-985d5637802b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596469419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w alk.1596469419 |
| Directory | /workspace/0.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2204459683 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1476032519 ps |
| CPU time | 1.82 seconds |
| Started | May 26 02:37:07 PM PDT 24 |
| Finished | May 26 02:37:10 PM PDT 24 |
| Peak memory | 193228 kb |
| Host | smart-f1fff2f0-db8a-4bf1-9c42-c06d4b544383 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204459683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon _timer_same_csr_outstanding.2204459683 |
| Directory | /workspace/0.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1504168255 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 661936476 ps |
| CPU time | 1.57 seconds |
| Started | May 26 02:36:58 PM PDT 24 |
| Finished | May 26 02:37:00 PM PDT 24 |
| Peak memory | 198444 kb |
| Host | smart-9148bcd9-c7f4-4660-87f9-85902d70ed64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504168255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1504168255 |
| Directory | /workspace/0.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1831661599 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 4201116404 ps |
| CPU time | 7.74 seconds |
| Started | May 26 02:36:58 PM PDT 24 |
| Finished | May 26 02:37:07 PM PDT 24 |
| Peak memory | 197680 kb |
| Host | smart-e930930b-60eb-4dca-996b-61bd219beda1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831661599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl _intg_err.1831661599 |
| Directory | /workspace/0.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.769093805 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 923275039 ps |
| CPU time | 0.84 seconds |
| Started | May 26 02:37:09 PM PDT 24 |
| Finished | May 26 02:37:10 PM PDT 24 |
| Peak memory | 191904 kb |
| Host | smart-55370127-f4d0-4a57-b7b4-9fefc43a571c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769093805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al iasing.769093805 |
| Directory | /workspace/1.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3852277691 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 13750415946 ps |
| CPU time | 16.67 seconds |
| Started | May 26 02:37:08 PM PDT 24 |
| Finished | May 26 02:37:26 PM PDT 24 |
| Peak memory | 192108 kb |
| Host | smart-c902749d-b05c-4d90-8cd7-66f5ab231dba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852277691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b it_bash.3852277691 |
| Directory | /workspace/1.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3119294991 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1157243802 ps |
| CPU time | 2.27 seconds |
| Started | May 26 02:37:12 PM PDT 24 |
| Finished | May 26 02:37:15 PM PDT 24 |
| Peak memory | 193076 kb |
| Host | smart-f7b1b926-2c6c-45fb-a531-12dedc358442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119294991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h w_reset.3119294991 |
| Directory | /workspace/1.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4196685116 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 420508998 ps |
| CPU time | 0.75 seconds |
| Started | May 26 02:37:08 PM PDT 24 |
| Finished | May 26 02:37:10 PM PDT 24 |
| Peak memory | 195564 kb |
| Host | smart-6bd97a45-8a37-4bc3-a0da-12ca9bcdfd57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196685116 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.4196685116 |
| Directory | /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2012570025 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 509329479 ps |
| CPU time | 1.3 seconds |
| Started | May 26 02:37:09 PM PDT 24 |
| Finished | May 26 02:37:11 PM PDT 24 |
| Peak memory | 191984 kb |
| Host | smart-ee9c8b58-f064-4ff7-82e5-0c25141dd59c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012570025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2012570025 |
| Directory | /workspace/1.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.136797352 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 404209860 ps |
| CPU time | 0.68 seconds |
| Started | May 26 02:37:07 PM PDT 24 |
| Finished | May 26 02:37:08 PM PDT 24 |
| Peak memory | 183604 kb |
| Host | smart-fd906279-9b6a-4b9e-805e-dbc5bf81d4d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136797352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.136797352 |
| Directory | /workspace/1.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.960684646 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 371386762 ps |
| CPU time | 0.75 seconds |
| Started | May 26 02:37:06 PM PDT 24 |
| Finished | May 26 02:37:07 PM PDT 24 |
| Peak memory | 183556 kb |
| Host | smart-2eb30f14-1f19-43c4-8b98-73996c47bb49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960684646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti mer_mem_partial_access.960684646 |
| Directory | /workspace/1.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.410932200 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 508419270 ps |
| CPU time | 1.11 seconds |
| Started | May 26 02:37:09 PM PDT 24 |
| Finished | May 26 02:37:11 PM PDT 24 |
| Peak memory | 183644 kb |
| Host | smart-3372c253-256c-44f9-a810-a524d6d7df34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410932200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa lk.410932200 |
| Directory | /workspace/1.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1245047338 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1329036336 ps |
| CPU time | 1.11 seconds |
| Started | May 26 02:37:07 PM PDT 24 |
| Finished | May 26 02:37:09 PM PDT 24 |
| Peak memory | 191852 kb |
| Host | smart-49000558-3e0e-4423-ac02-0128ef498764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245047338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon _timer_same_csr_outstanding.1245047338 |
| Directory | /workspace/1.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.29389783 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 507915244 ps |
| CPU time | 1.81 seconds |
| Started | May 26 02:37:08 PM PDT 24 |
| Finished | May 26 02:37:11 PM PDT 24 |
| Peak memory | 198316 kb |
| Host | smart-c33bf08f-b1dd-4d4e-9759-be6a3e773b25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29389783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.29389783 |
| Directory | /workspace/1.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2963653534 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8418227437 ps |
| CPU time | 15.15 seconds |
| Started | May 26 02:37:12 PM PDT 24 |
| Finished | May 26 02:37:27 PM PDT 24 |
| Peak memory | 198304 kb |
| Host | smart-cc8d373e-a8bc-436b-9c0b-29f845ddfe02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963653534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl _intg_err.2963653534 |
| Directory | /workspace/1.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3672780016 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 443094348 ps |
| CPU time | 1.28 seconds |
| Started | May 26 02:37:47 PM PDT 24 |
| Finished | May 26 02:37:49 PM PDT 24 |
| Peak memory | 195304 kb |
| Host | smart-29aa7b85-a9af-4ba4-b66a-86fe1b6dbef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672780016 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3672780016 |
| Directory | /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3208632287 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 480825268 ps |
| CPU time | 1.17 seconds |
| Started | May 26 02:37:42 PM PDT 24 |
| Finished | May 26 02:37:44 PM PDT 24 |
| Peak memory | 183816 kb |
| Host | smart-d5167507-2d1f-4051-8ecf-1c18f9825cbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208632287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3208632287 |
| Directory | /workspace/10.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1348216465 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 480333071 ps |
| CPU time | 1.24 seconds |
| Started | May 26 02:37:46 PM PDT 24 |
| Finished | May 26 02:37:48 PM PDT 24 |
| Peak memory | 183644 kb |
| Host | smart-6660cdb0-df5c-4835-9b77-3b59dff55b39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348216465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1348216465 |
| Directory | /workspace/10.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.556702203 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1063030954 ps |
| CPU time | 1.15 seconds |
| Started | May 26 02:37:46 PM PDT 24 |
| Finished | May 26 02:37:48 PM PDT 24 |
| Peak memory | 193144 kb |
| Host | smart-c886d808-18e1-4a7b-9953-cb11e5f2c177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556702203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon _timer_same_csr_outstanding.556702203 |
| Directory | /workspace/10.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3378687707 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1021641472 ps |
| CPU time | 1.11 seconds |
| Started | May 26 02:37:47 PM PDT 24 |
| Finished | May 26 02:37:49 PM PDT 24 |
| Peak memory | 198360 kb |
| Host | smart-76d1cc50-4426-456c-973f-4fcfe9d8b542 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378687707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3378687707 |
| Directory | /workspace/10.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2700555561 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 8365254869 ps |
| CPU time | 12.95 seconds |
| Started | May 26 02:37:47 PM PDT 24 |
| Finished | May 26 02:38:00 PM PDT 24 |
| Peak memory | 198052 kb |
| Host | smart-0994e6e0-9e43-42d8-88af-485638e46bfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700555561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t l_intg_err.2700555561 |
| Directory | /workspace/10.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3869806505 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 756807338 ps |
| CPU time | 0.77 seconds |
| Started | May 26 02:37:43 PM PDT 24 |
| Finished | May 26 02:37:45 PM PDT 24 |
| Peak memory | 196360 kb |
| Host | smart-283ac25d-e394-4419-8184-fc045299ee13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869806505 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3869806505 |
| Directory | /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2148401683 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 299663248 ps |
| CPU time | 0.74 seconds |
| Started | May 26 02:37:44 PM PDT 24 |
| Finished | May 26 02:37:46 PM PDT 24 |
| Peak memory | 183620 kb |
| Host | smart-7cc53ac9-020b-42ad-a0b2-1ab111f5e30a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148401683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2148401683 |
| Directory | /workspace/11.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4282350408 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1412180738 ps |
| CPU time | 2.47 seconds |
| Started | May 26 02:37:43 PM PDT 24 |
| Finished | May 26 02:37:47 PM PDT 24 |
| Peak memory | 193224 kb |
| Host | smart-e7fd03f2-f92b-4bc9-b311-1fdcb5caa9bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282350408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao n_timer_same_csr_outstanding.4282350408 |
| Directory | /workspace/11.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2875412721 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 550171461 ps |
| CPU time | 2.7 seconds |
| Started | May 26 02:37:46 PM PDT 24 |
| Finished | May 26 02:37:49 PM PDT 24 |
| Peak memory | 198472 kb |
| Host | smart-958e8d86-d340-4e32-85a3-f0de3b85b557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875412721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2875412721 |
| Directory | /workspace/11.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3258854479 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 3942041689 ps |
| CPU time | 2.13 seconds |
| Started | May 26 02:37:51 PM PDT 24 |
| Finished | May 26 02:37:55 PM PDT 24 |
| Peak memory | 197752 kb |
| Host | smart-9fc9b618-2537-4aeb-90c8-f26e9ad24b7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258854479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t l_intg_err.3258854479 |
| Directory | /workspace/11.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1083377989 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 495064209 ps |
| CPU time | 0.76 seconds |
| Started | May 26 02:37:44 PM PDT 24 |
| Finished | May 26 02:37:46 PM PDT 24 |
| Peak memory | 197348 kb |
| Host | smart-43c7c578-2da9-4602-a17c-6fe317fe88fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083377989 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1083377989 |
| Directory | /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2474521885 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 549122395 ps |
| CPU time | 0.76 seconds |
| Started | May 26 02:37:51 PM PDT 24 |
| Finished | May 26 02:37:54 PM PDT 24 |
| Peak memory | 193096 kb |
| Host | smart-ce4e8e2d-2e63-4f63-889d-a709aaf718f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474521885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2474521885 |
| Directory | /workspace/12.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.355220496 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 517171330 ps |
| CPU time | 0.71 seconds |
| Started | May 26 02:37:43 PM PDT 24 |
| Finished | May 26 02:37:45 PM PDT 24 |
| Peak memory | 183588 kb |
| Host | smart-1eec22c0-f6d2-4df7-8ffe-471ecec2adb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355220496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.355220496 |
| Directory | /workspace/12.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2717818138 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2779915277 ps |
| CPU time | 1.65 seconds |
| Started | May 26 02:37:46 PM PDT 24 |
| Finished | May 26 02:37:49 PM PDT 24 |
| Peak memory | 194964 kb |
| Host | smart-e314a123-ccc9-4df5-85cb-eb2ba25a368a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717818138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao n_timer_same_csr_outstanding.2717818138 |
| Directory | /workspace/12.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3783902124 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 760614895 ps |
| CPU time | 1.38 seconds |
| Started | May 26 02:37:47 PM PDT 24 |
| Finished | May 26 02:37:49 PM PDT 24 |
| Peak memory | 198436 kb |
| Host | smart-995d78bf-8af2-41e6-b7f5-4e51766dad07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783902124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3783902124 |
| Directory | /workspace/12.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3530717529 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4289710457 ps |
| CPU time | 4.19 seconds |
| Started | May 26 02:37:43 PM PDT 24 |
| Finished | May 26 02:37:48 PM PDT 24 |
| Peak memory | 197744 kb |
| Host | smart-f3a1624e-53f4-4734-b045-bd04b90c7fa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530717529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t l_intg_err.3530717529 |
| Directory | /workspace/12.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1965460156 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 474880727 ps |
| CPU time | 1.34 seconds |
| Started | May 26 02:37:54 PM PDT 24 |
| Finished | May 26 02:37:58 PM PDT 24 |
| Peak memory | 196008 kb |
| Host | smart-735dfaa3-eae3-4dae-a406-632620bf7c7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965460156 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1965460156 |
| Directory | /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.308954003 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 285356309 ps |
| CPU time | 0.96 seconds |
| Started | May 26 02:37:55 PM PDT 24 |
| Finished | May 26 02:37:58 PM PDT 24 |
| Peak memory | 183932 kb |
| Host | smart-48eb65f5-1602-4946-b959-d88c507d8c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308954003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.308954003 |
| Directory | /workspace/13.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1904725370 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 520454379 ps |
| CPU time | 0.65 seconds |
| Started | May 26 02:37:42 PM PDT 24 |
| Finished | May 26 02:37:43 PM PDT 24 |
| Peak memory | 183640 kb |
| Host | smart-2f296d3c-0170-4bd7-8a4e-630a9677daa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904725370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1904725370 |
| Directory | /workspace/13.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3388437451 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2534884933 ps |
| CPU time | 4.5 seconds |
| Started | May 26 02:37:58 PM PDT 24 |
| Finished | May 26 02:38:05 PM PDT 24 |
| Peak memory | 191980 kb |
| Host | smart-4c043edf-e24b-4040-8f12-31c413a91c1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388437451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao n_timer_same_csr_outstanding.3388437451 |
| Directory | /workspace/13.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.220917256 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 570462370 ps |
| CPU time | 1.44 seconds |
| Started | May 26 02:37:43 PM PDT 24 |
| Finished | May 26 02:37:46 PM PDT 24 |
| Peak memory | 198456 kb |
| Host | smart-aa07f95b-8e97-4422-af8b-3dd59222b5ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220917256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.220917256 |
| Directory | /workspace/13.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.469402491 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 8490916034 ps |
| CPU time | 13.18 seconds |
| Started | May 26 02:37:47 PM PDT 24 |
| Finished | May 26 02:38:01 PM PDT 24 |
| Peak memory | 198036 kb |
| Host | smart-bcb7b754-3e91-4f00-9b35-e3f3bd5755f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469402491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl _intg_err.469402491 |
| Directory | /workspace/13.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3997437969 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 556166324 ps |
| CPU time | 1.53 seconds |
| Started | May 26 02:37:51 PM PDT 24 |
| Finished | May 26 02:37:55 PM PDT 24 |
| Peak memory | 195836 kb |
| Host | smart-deb459ce-d9b5-4b09-a069-e07157f9d5fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997437969 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3997437969 |
| Directory | /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3964025207 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 525992716 ps |
| CPU time | 0.65 seconds |
| Started | May 26 02:37:55 PM PDT 24 |
| Finished | May 26 02:37:58 PM PDT 24 |
| Peak memory | 192980 kb |
| Host | smart-726a1ad9-8b17-4970-a1a8-6f6440bbed45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964025207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3964025207 |
| Directory | /workspace/14.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1272054255 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 342142843 ps |
| CPU time | 1.05 seconds |
| Started | May 26 02:37:52 PM PDT 24 |
| Finished | May 26 02:37:56 PM PDT 24 |
| Peak memory | 183624 kb |
| Host | smart-5e55fda1-99f7-457e-be1d-b0ed0081fa02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272054255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1272054255 |
| Directory | /workspace/14.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1384534160 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2599985792 ps |
| CPU time | 4.83 seconds |
| Started | May 26 02:37:54 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 194876 kb |
| Host | smart-17c141b0-87f7-4589-be8b-8daeb0f76ee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384534160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao n_timer_same_csr_outstanding.1384534160 |
| Directory | /workspace/14.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2466902161 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 697732373 ps |
| CPU time | 1.49 seconds |
| Started | May 26 02:37:53 PM PDT 24 |
| Finished | May 26 02:37:57 PM PDT 24 |
| Peak memory | 198488 kb |
| Host | smart-76ea15b6-2f16-4db5-9ef2-f5c985c32b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466902161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2466902161 |
| Directory | /workspace/14.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3635736398 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 8145725257 ps |
| CPU time | 7.98 seconds |
| Started | May 26 02:37:55 PM PDT 24 |
| Finished | May 26 02:38:05 PM PDT 24 |
| Peak memory | 197912 kb |
| Host | smart-62f92a20-258a-419b-a594-7a6bfdadba0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635736398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t l_intg_err.3635736398 |
| Directory | /workspace/14.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.813740809 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 475037194 ps |
| CPU time | 1.37 seconds |
| Started | May 26 02:37:51 PM PDT 24 |
| Finished | May 26 02:37:53 PM PDT 24 |
| Peak memory | 195076 kb |
| Host | smart-6094fb72-4a61-47e6-b2b0-e907bd6bb431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813740809 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.813740809 |
| Directory | /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3317061529 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 579798757 ps |
| CPU time | 0.67 seconds |
| Started | May 26 02:37:52 PM PDT 24 |
| Finished | May 26 02:37:56 PM PDT 24 |
| Peak memory | 183712 kb |
| Host | smart-d5d7b2f3-83ed-4d03-b92d-a5c7b415209f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317061529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3317061529 |
| Directory | /workspace/15.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2964956469 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 499109257 ps |
| CPU time | 1.23 seconds |
| Started | May 26 02:37:53 PM PDT 24 |
| Finished | May 26 02:37:57 PM PDT 24 |
| Peak memory | 183616 kb |
| Host | smart-dc668512-d5b6-4938-bcf0-e769452385dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964956469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2964956469 |
| Directory | /workspace/15.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2765187209 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2432137083 ps |
| CPU time | 2.81 seconds |
| Started | May 26 02:37:53 PM PDT 24 |
| Finished | May 26 02:37:59 PM PDT 24 |
| Peak memory | 194384 kb |
| Host | smart-7084579b-b90e-4370-80aa-d152878675ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765187209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao n_timer_same_csr_outstanding.2765187209 |
| Directory | /workspace/15.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1657767338 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 477992229 ps |
| CPU time | 2.56 seconds |
| Started | May 26 02:37:58 PM PDT 24 |
| Finished | May 26 02:38:03 PM PDT 24 |
| Peak memory | 198448 kb |
| Host | smart-3cf288d5-f460-45e4-866e-2258cd9864e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657767338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1657767338 |
| Directory | /workspace/15.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2740389243 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 7825685153 ps |
| CPU time | 12.77 seconds |
| Started | May 26 02:37:51 PM PDT 24 |
| Finished | May 26 02:38:05 PM PDT 24 |
| Peak memory | 197992 kb |
| Host | smart-2a991dd6-6fa0-4366-9939-4d79a931555c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740389243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t l_intg_err.2740389243 |
| Directory | /workspace/15.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3498363034 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 421689967 ps |
| CPU time | 1.16 seconds |
| Started | May 26 02:37:52 PM PDT 24 |
| Finished | May 26 02:37:55 PM PDT 24 |
| Peak memory | 195540 kb |
| Host | smart-4bd7e68c-12eb-496d-adfd-6eaa244e6559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498363034 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3498363034 |
| Directory | /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2525508496 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 446545035 ps |
| CPU time | 0.71 seconds |
| Started | May 26 02:37:53 PM PDT 24 |
| Finished | May 26 02:37:57 PM PDT 24 |
| Peak memory | 183740 kb |
| Host | smart-bb37ed97-fbbd-4139-9553-3a0ec784aaf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525508496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2525508496 |
| Directory | /workspace/16.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3255747004 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 396934872 ps |
| CPU time | 0.77 seconds |
| Started | May 26 02:37:52 PM PDT 24 |
| Finished | May 26 02:37:56 PM PDT 24 |
| Peak memory | 183640 kb |
| Host | smart-d7342552-a84d-4a24-ad5d-8f1ba4f99f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255747004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3255747004 |
| Directory | /workspace/16.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1616250927 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 3155987073 ps |
| CPU time | 1.68 seconds |
| Started | May 26 02:37:52 PM PDT 24 |
| Finished | May 26 02:37:55 PM PDT 24 |
| Peak memory | 194836 kb |
| Host | smart-787999b2-4229-47fe-82fd-dc2180e4a907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616250927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao n_timer_same_csr_outstanding.1616250927 |
| Directory | /workspace/16.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.227524745 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 497614963 ps |
| CPU time | 2.8 seconds |
| Started | May 26 02:37:54 PM PDT 24 |
| Finished | May 26 02:38:00 PM PDT 24 |
| Peak memory | 198316 kb |
| Host | smart-e711c0b4-3950-47a6-b46f-93489f75598d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227524745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.227524745 |
| Directory | /workspace/16.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.314055310 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 4874404278 ps |
| CPU time | 2.77 seconds |
| Started | May 26 02:37:54 PM PDT 24 |
| Finished | May 26 02:37:59 PM PDT 24 |
| Peak memory | 197360 kb |
| Host | smart-976228c9-bd1a-4003-a75e-a45a2df8581e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314055310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl _intg_err.314055310 |
| Directory | /workspace/16.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3149463252 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 379844688 ps |
| CPU time | 1 seconds |
| Started | May 26 02:37:56 PM PDT 24 |
| Finished | May 26 02:37:59 PM PDT 24 |
| Peak memory | 198332 kb |
| Host | smart-0920e3a2-5bfd-41c0-88da-6725180895dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149463252 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3149463252 |
| Directory | /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3685365931 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 512868472 ps |
| CPU time | 0.91 seconds |
| Started | May 26 02:37:58 PM PDT 24 |
| Finished | May 26 02:38:01 PM PDT 24 |
| Peak memory | 192196 kb |
| Host | smart-428a972e-207f-49aa-959f-05b44ee3e984 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685365931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3685365931 |
| Directory | /workspace/17.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.799562665 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 351537227 ps |
| CPU time | 0.66 seconds |
| Started | May 26 02:37:53 PM PDT 24 |
| Finished | May 26 02:37:56 PM PDT 24 |
| Peak memory | 183628 kb |
| Host | smart-dc4413f2-4994-48f4-bb84-2bf4f8c78c4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799562665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.799562665 |
| Directory | /workspace/17.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2530277903 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1263498481 ps |
| CPU time | 1.48 seconds |
| Started | May 26 02:37:58 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 192936 kb |
| Host | smart-b89b2bac-b0f3-4231-845a-1f80b54cd51e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530277903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao n_timer_same_csr_outstanding.2530277903 |
| Directory | /workspace/17.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.175718957 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 516936207 ps |
| CPU time | 1.78 seconds |
| Started | May 26 02:37:54 PM PDT 24 |
| Finished | May 26 02:37:58 PM PDT 24 |
| Peak memory | 198360 kb |
| Host | smart-fbd95a03-3e34-4277-9e77-984c17369f37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175718957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.175718957 |
| Directory | /workspace/17.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.392949236 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 7676836155 ps |
| CPU time | 6.74 seconds |
| Started | May 26 02:37:52 PM PDT 24 |
| Finished | May 26 02:38:01 PM PDT 24 |
| Peak memory | 198064 kb |
| Host | smart-7a1e699a-3846-4e69-aa03-d81050ddd597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392949236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl _intg_err.392949236 |
| Directory | /workspace/17.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2950950941 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 642581432 ps |
| CPU time | 1.13 seconds |
| Started | May 26 02:38:01 PM PDT 24 |
| Finished | May 26 02:38:04 PM PDT 24 |
| Peak memory | 198360 kb |
| Host | smart-998cf770-468d-423c-9e10-a6198cb15f89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950950941 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2950950941 |
| Directory | /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.858595642 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 365816087 ps |
| CPU time | 1.14 seconds |
| Started | May 26 02:37:51 PM PDT 24 |
| Finished | May 26 02:37:55 PM PDT 24 |
| Peak memory | 183784 kb |
| Host | smart-e29ea161-1c2b-476e-b017-7347ea509b84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858595642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.858595642 |
| Directory | /workspace/18.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1429581751 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 434939369 ps |
| CPU time | 0.86 seconds |
| Started | May 26 02:37:51 PM PDT 24 |
| Finished | May 26 02:37:53 PM PDT 24 |
| Peak memory | 183620 kb |
| Host | smart-b64f001d-3724-42c5-b476-6cbb8c3839f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429581751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1429581751 |
| Directory | /workspace/18.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3369728750 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1359164071 ps |
| CPU time | 1.63 seconds |
| Started | May 26 02:37:55 PM PDT 24 |
| Finished | May 26 02:37:59 PM PDT 24 |
| Peak memory | 192856 kb |
| Host | smart-79819240-ce98-46b2-ae64-375c5a256e44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369728750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao n_timer_same_csr_outstanding.3369728750 |
| Directory | /workspace/18.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.61812135 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 719654625 ps |
| CPU time | 1.36 seconds |
| Started | May 26 02:37:52 PM PDT 24 |
| Finished | May 26 02:37:56 PM PDT 24 |
| Peak memory | 198364 kb |
| Host | smart-82d6b037-1b63-4012-962b-4df87bfd8ea3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61812135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.61812135 |
| Directory | /workspace/18.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.316279252 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4466266267 ps |
| CPU time | 1.75 seconds |
| Started | May 26 02:37:54 PM PDT 24 |
| Finished | May 26 02:37:59 PM PDT 24 |
| Peak memory | 197720 kb |
| Host | smart-a264fdd5-351a-409a-a67a-396684a59a96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316279252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl _intg_err.316279252 |
| Directory | /workspace/18.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4042148629 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 414980633 ps |
| CPU time | 0.98 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 196760 kb |
| Host | smart-2205ee9c-d8b4-44f4-ada9-ef997b79f0c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042148629 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.4042148629 |
| Directory | /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.622894197 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 426363015 ps |
| CPU time | 1.2 seconds |
| Started | May 26 02:38:00 PM PDT 24 |
| Finished | May 26 02:38:03 PM PDT 24 |
| Peak memory | 192920 kb |
| Host | smart-f607b927-072c-45d7-a8bd-f8640d7e6524 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622894197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.622894197 |
| Directory | /workspace/19.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3422912401 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 373908449 ps |
| CPU time | 1.05 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 183632 kb |
| Host | smart-08050c4f-3a2a-44db-af5c-ba41adbf5f03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422912401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3422912401 |
| Directory | /workspace/19.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4241835067 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1587580901 ps |
| CPU time | 1.24 seconds |
| Started | May 26 02:38:11 PM PDT 24 |
| Finished | May 26 02:38:14 PM PDT 24 |
| Peak memory | 183756 kb |
| Host | smart-318279cb-38cd-4755-8ef8-d95119b2b5ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241835067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao n_timer_same_csr_outstanding.4241835067 |
| Directory | /workspace/19.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2866766177 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 424418782 ps |
| CPU time | 1.99 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:03 PM PDT 24 |
| Peak memory | 198440 kb |
| Host | smart-2f48d7d9-945b-4ec6-a935-587432c2afe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866766177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2866766177 |
| Directory | /workspace/19.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1505832656 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 8989007042 ps |
| CPU time | 12.13 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:13 PM PDT 24 |
| Peak memory | 198012 kb |
| Host | smart-bc538be0-31b7-4774-9083-7d7d361dd1be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505832656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t l_intg_err.1505832656 |
| Directory | /workspace/19.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3249123622 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 629036518 ps |
| CPU time | 1.15 seconds |
| Started | May 26 02:37:14 PM PDT 24 |
| Finished | May 26 02:37:16 PM PDT 24 |
| Peak memory | 193152 kb |
| Host | smart-a6b7e028-00ed-44c7-9bd7-2274dd0e3cfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249123622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a liasing.3249123622 |
| Directory | /workspace/2.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2383630802 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 7148548222 ps |
| CPU time | 2.34 seconds |
| Started | May 26 02:37:15 PM PDT 24 |
| Finished | May 26 02:37:18 PM PDT 24 |
| Peak memory | 192120 kb |
| Host | smart-1c33e2de-e898-4204-b42f-33b172658a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383630802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b it_bash.2383630802 |
| Directory | /workspace/2.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3801959944 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1263715428 ps |
| CPU time | 1.52 seconds |
| Started | May 26 02:37:16 PM PDT 24 |
| Finished | May 26 02:37:19 PM PDT 24 |
| Peak memory | 183672 kb |
| Host | smart-7a7f549d-f6c3-4465-b801-5053683facff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801959944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h w_reset.3801959944 |
| Directory | /workspace/2.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3960273171 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 409352253 ps |
| CPU time | 1.26 seconds |
| Started | May 26 02:37:15 PM PDT 24 |
| Finished | May 26 02:37:17 PM PDT 24 |
| Peak memory | 196012 kb |
| Host | smart-984986ea-c200-4c11-ad18-49aeba7918ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960273171 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3960273171 |
| Directory | /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2339966265 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 459486945 ps |
| CPU time | 0.75 seconds |
| Started | May 26 02:37:15 PM PDT 24 |
| Finished | May 26 02:37:16 PM PDT 24 |
| Peak memory | 193136 kb |
| Host | smart-93be7efd-1b48-496f-9aa2-9846ba3bec68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339966265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2339966265 |
| Directory | /workspace/2.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.975601703 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 370162804 ps |
| CPU time | 0.81 seconds |
| Started | May 26 02:37:14 PM PDT 24 |
| Finished | May 26 02:37:15 PM PDT 24 |
| Peak memory | 183620 kb |
| Host | smart-ed2efb68-1045-4b28-8fa4-2d83730f9a1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975601703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.975601703 |
| Directory | /workspace/2.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3111688044 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 271335383 ps |
| CPU time | 0.89 seconds |
| Started | May 26 02:37:15 PM PDT 24 |
| Finished | May 26 02:37:17 PM PDT 24 |
| Peak memory | 183560 kb |
| Host | smart-4727eb7e-be18-4102-a976-d803847ad495 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111688044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t imer_mem_partial_access.3111688044 |
| Directory | /workspace/2.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3768765948 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 312064230 ps |
| CPU time | 0.99 seconds |
| Started | May 26 02:37:15 PM PDT 24 |
| Finished | May 26 02:37:17 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-fd100b98-c90d-4b82-ba51-77efa551ea23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768765948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w alk.3768765948 |
| Directory | /workspace/2.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.106859997 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1169221164 ps |
| CPU time | 1.02 seconds |
| Started | May 26 02:37:16 PM PDT 24 |
| Finished | May 26 02:37:17 PM PDT 24 |
| Peak memory | 183708 kb |
| Host | smart-a03810a8-4113-44de-a64d-f26c28830cc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106859997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ timer_same_csr_outstanding.106859997 |
| Directory | /workspace/2.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3953502165 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 592005059 ps |
| CPU time | 1.07 seconds |
| Started | May 26 02:37:06 PM PDT 24 |
| Finished | May 26 02:37:07 PM PDT 24 |
| Peak memory | 198316 kb |
| Host | smart-21164f82-91ff-4850-b27a-748a42e9d538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953502165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3953502165 |
| Directory | /workspace/2.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3564066950 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 4634024270 ps |
| CPU time | 2.69 seconds |
| Started | May 26 02:37:18 PM PDT 24 |
| Finished | May 26 02:37:22 PM PDT 24 |
| Peak memory | 197412 kb |
| Host | smart-98942e3b-f0cd-496a-8468-c1c8f0a6ed30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564066950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl _intg_err.3564066950 |
| Directory | /workspace/2.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2296714496 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 311276359 ps |
| CPU time | 0.65 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 183624 kb |
| Host | smart-8cf2e76f-d52a-4e48-b6d7-884b4499bf54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296714496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2296714496 |
| Directory | /workspace/20.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3123255739 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 293798993 ps |
| CPU time | 0.75 seconds |
| Started | May 26 02:38:00 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 183600 kb |
| Host | smart-492622ca-1f3a-48a8-9398-178313322295 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123255739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3123255739 |
| Directory | /workspace/21.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2695368808 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 318985392 ps |
| CPU time | 0.63 seconds |
| Started | May 26 02:38:09 PM PDT 24 |
| Finished | May 26 02:38:10 PM PDT 24 |
| Peak memory | 183684 kb |
| Host | smart-05a4f212-64c4-480b-8c0c-a244a5c195a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695368808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2695368808 |
| Directory | /workspace/22.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3189618183 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 325503240 ps |
| CPU time | 0.97 seconds |
| Started | May 26 02:38:07 PM PDT 24 |
| Finished | May 26 02:38:09 PM PDT 24 |
| Peak memory | 183652 kb |
| Host | smart-f05d99fa-f753-4edd-b833-f03122284b3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189618183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3189618183 |
| Directory | /workspace/23.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3741724991 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 327359878 ps |
| CPU time | 0.76 seconds |
| Started | May 26 02:38:10 PM PDT 24 |
| Finished | May 26 02:38:12 PM PDT 24 |
| Peak memory | 183684 kb |
| Host | smart-b767372a-8e7c-4ca2-b579-cf606b72d3bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741724991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3741724991 |
| Directory | /workspace/24.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1305859337 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 515079661 ps |
| CPU time | 0.82 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 183616 kb |
| Host | smart-e8c7b894-93d3-4fd4-87de-96ebe7e74e6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305859337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1305859337 |
| Directory | /workspace/25.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3908138627 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 473357545 ps |
| CPU time | 0.9 seconds |
| Started | May 26 02:38:09 PM PDT 24 |
| Finished | May 26 02:38:11 PM PDT 24 |
| Peak memory | 183684 kb |
| Host | smart-462c9a1f-4be5-478f-89a4-354ba657a52b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908138627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3908138627 |
| Directory | /workspace/26.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3260052687 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 518601713 ps |
| CPU time | 1.01 seconds |
| Started | May 26 02:38:09 PM PDT 24 |
| Finished | May 26 02:38:10 PM PDT 24 |
| Peak memory | 183680 kb |
| Host | smart-47efd18c-609e-49d3-a3f7-690b06586bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260052687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3260052687 |
| Directory | /workspace/27.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1475886322 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 530227861 ps |
| CPU time | 0.57 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:01 PM PDT 24 |
| Peak memory | 183640 kb |
| Host | smart-c992af0c-12d9-48a7-a033-ea27e3564089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475886322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1475886322 |
| Directory | /workspace/28.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2133806147 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 618718992 ps |
| CPU time | 0.61 seconds |
| Started | May 26 02:38:02 PM PDT 24 |
| Finished | May 26 02:38:03 PM PDT 24 |
| Peak memory | 183640 kb |
| Host | smart-80a46c30-de53-49a0-8bdd-43efddf77142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133806147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2133806147 |
| Directory | /workspace/29.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3385360623 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 578929154 ps |
| CPU time | 1 seconds |
| Started | May 26 02:37:22 PM PDT 24 |
| Finished | May 26 02:37:24 PM PDT 24 |
| Peak memory | 194256 kb |
| Host | smart-d6c41535-0f73-43ee-bc07-d6b4b413abbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385360623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a liasing.3385360623 |
| Directory | /workspace/3.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3478900161 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 930410792 ps |
| CPU time | 0.95 seconds |
| Started | May 26 02:37:16 PM PDT 24 |
| Finished | May 26 02:37:18 PM PDT 24 |
| Peak memory | 183708 kb |
| Host | smart-452e0a04-bfea-4665-95c7-1515058f6fa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478900161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h w_reset.3478900161 |
| Directory | /workspace/3.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.309551979 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 541612210 ps |
| CPU time | 1.5 seconds |
| Started | May 26 02:37:20 PM PDT 24 |
| Finished | May 26 02:37:23 PM PDT 24 |
| Peak memory | 195820 kb |
| Host | smart-9eed1d22-508c-44db-9395-c9281a957d91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309551979 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.309551979 |
| Directory | /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4101588916 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 472802084 ps |
| CPU time | 0.83 seconds |
| Started | May 26 02:37:21 PM PDT 24 |
| Finished | May 26 02:37:23 PM PDT 24 |
| Peak memory | 183752 kb |
| Host | smart-72c47c02-12fe-42e6-9963-138beda00a58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101588916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4101588916 |
| Directory | /workspace/3.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2918918942 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 286864143 ps |
| CPU time | 0.71 seconds |
| Started | May 26 02:37:16 PM PDT 24 |
| Finished | May 26 02:37:17 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-41ccf6cc-66b8-49b2-b943-09d217c4709a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918918942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2918918942 |
| Directory | /workspace/3.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1490235455 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 462018406 ps |
| CPU time | 0.67 seconds |
| Started | May 26 02:37:17 PM PDT 24 |
| Finished | May 26 02:37:19 PM PDT 24 |
| Peak memory | 183720 kb |
| Host | smart-0c0fbbb4-0e24-4aab-a651-c7b849d87f2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490235455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t imer_mem_partial_access.1490235455 |
| Directory | /workspace/3.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2411920745 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 455138421 ps |
| CPU time | 0.84 seconds |
| Started | May 26 02:37:15 PM PDT 24 |
| Finished | May 26 02:37:17 PM PDT 24 |
| Peak memory | 183688 kb |
| Host | smart-2e1e3ddf-2b43-4396-a736-4eaad13ccf39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411920745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w alk.2411920745 |
| Directory | /workspace/3.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.722115590 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1628287615 ps |
| CPU time | 0.77 seconds |
| Started | May 26 02:37:21 PM PDT 24 |
| Finished | May 26 02:37:22 PM PDT 24 |
| Peak memory | 193148 kb |
| Host | smart-ba4a566f-c17d-4b86-b21f-03bfa67c6138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722115590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ timer_same_csr_outstanding.722115590 |
| Directory | /workspace/3.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.380471662 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 830733755 ps |
| CPU time | 2.27 seconds |
| Started | May 26 02:37:17 PM PDT 24 |
| Finished | May 26 02:37:20 PM PDT 24 |
| Peak memory | 198604 kb |
| Host | smart-a6f9c877-4af7-4e7a-978e-f82532940e37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380471662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.380471662 |
| Directory | /workspace/3.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2527739014 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 8371715221 ps |
| CPU time | 9.68 seconds |
| Started | May 26 02:37:16 PM PDT 24 |
| Finished | May 26 02:37:26 PM PDT 24 |
| Peak memory | 198060 kb |
| Host | smart-c7c1e2ec-dcfe-4605-b556-293b3f11ddef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527739014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl _intg_err.2527739014 |
| Directory | /workspace/3.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1006849109 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 429921194 ps |
| CPU time | 0.67 seconds |
| Started | May 26 02:38:00 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 183624 kb |
| Host | smart-4f488969-a242-47a1-beee-2538e07e776a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006849109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1006849109 |
| Directory | /workspace/30.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3591704465 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 391158279 ps |
| CPU time | 0.68 seconds |
| Started | May 26 02:38:00 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 183632 kb |
| Host | smart-b8701b38-d217-4138-8c70-4cf42602340c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591704465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3591704465 |
| Directory | /workspace/31.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3586952998 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 390779207 ps |
| CPU time | 0.83 seconds |
| Started | May 26 02:38:00 PM PDT 24 |
| Finished | May 26 02:38:03 PM PDT 24 |
| Peak memory | 183600 kb |
| Host | smart-6520a166-e006-49ad-9cd3-29b41a5a178e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586952998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3586952998 |
| Directory | /workspace/32.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1165803992 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 517259201 ps |
| CPU time | 0.97 seconds |
| Started | May 26 02:38:00 PM PDT 24 |
| Finished | May 26 02:38:03 PM PDT 24 |
| Peak memory | 183612 kb |
| Host | smart-6740b52a-e81b-4964-9f0d-f178064211ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165803992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1165803992 |
| Directory | /workspace/33.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1114954052 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 483523251 ps |
| CPU time | 0.69 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 183644 kb |
| Host | smart-842dbdf4-f25b-4cdb-a702-3b2c3fa5072e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114954052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1114954052 |
| Directory | /workspace/34.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.689407443 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 413015493 ps |
| CPU time | 0.71 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 183536 kb |
| Host | smart-e23d5847-27a2-4e71-bf94-4f4157d92355 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689407443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.689407443 |
| Directory | /workspace/35.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.434178272 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 481210152 ps |
| CPU time | 0.83 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 183632 kb |
| Host | smart-e4ecd80c-9c2d-4d8d-aabf-119f884a1277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434178272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.434178272 |
| Directory | /workspace/36.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2388756376 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 422309920 ps |
| CPU time | 0.85 seconds |
| Started | May 26 02:38:00 PM PDT 24 |
| Finished | May 26 02:38:03 PM PDT 24 |
| Peak memory | 183624 kb |
| Host | smart-16ebf2e1-7fcd-4449-9fcd-1a66ccbfb2be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388756376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2388756376 |
| Directory | /workspace/37.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2651756033 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 354542445 ps |
| CPU time | 1 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 183816 kb |
| Host | smart-d820c43f-9b0f-4c23-9692-8d9e141b8894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651756033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2651756033 |
| Directory | /workspace/38.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2948646590 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 401018268 ps |
| CPU time | 1.17 seconds |
| Started | May 26 02:38:10 PM PDT 24 |
| Finished | May 26 02:38:13 PM PDT 24 |
| Peak memory | 183680 kb |
| Host | smart-6d588d87-8e2a-42a0-aef1-34596329ae53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948646590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2948646590 |
| Directory | /workspace/39.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.936492800 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 523343513 ps |
| CPU time | 1.33 seconds |
| Started | May 26 02:37:22 PM PDT 24 |
| Finished | May 26 02:37:24 PM PDT 24 |
| Peak memory | 183696 kb |
| Host | smart-ac933d35-8530-47e4-9817-ad61e6b65f1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936492800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al iasing.936492800 |
| Directory | /workspace/4.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2448285869 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3535931005 ps |
| CPU time | 10.49 seconds |
| Started | May 26 02:37:23 PM PDT 24 |
| Finished | May 26 02:37:34 PM PDT 24 |
| Peak memory | 192108 kb |
| Host | smart-2dac865b-e6dc-4a81-a6fd-e3980a4a9d3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448285869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b it_bash.2448285869 |
| Directory | /workspace/4.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2981020730 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 942556123 ps |
| CPU time | 0.89 seconds |
| Started | May 26 02:37:22 PM PDT 24 |
| Finished | May 26 02:37:24 PM PDT 24 |
| Peak memory | 183684 kb |
| Host | smart-8942fc75-f102-41da-8ffc-71c9c6a2758a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981020730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h w_reset.2981020730 |
| Directory | /workspace/4.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2756929963 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 645053075 ps |
| CPU time | 0.89 seconds |
| Started | May 26 02:37:29 PM PDT 24 |
| Finished | May 26 02:37:31 PM PDT 24 |
| Peak memory | 198272 kb |
| Host | smart-46e27032-0992-4249-aafe-3d56f8ce157e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756929963 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2756929963 |
| Directory | /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3292092009 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 452538974 ps |
| CPU time | 1.27 seconds |
| Started | May 26 02:37:21 PM PDT 24 |
| Finished | May 26 02:37:23 PM PDT 24 |
| Peak memory | 193004 kb |
| Host | smart-ef77ac49-ddff-4f20-b1ff-6e798ed2b7f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292092009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3292092009 |
| Directory | /workspace/4.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1449525278 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 370033752 ps |
| CPU time | 0.56 seconds |
| Started | May 26 02:37:20 PM PDT 24 |
| Finished | May 26 02:37:21 PM PDT 24 |
| Peak memory | 183600 kb |
| Host | smart-68f17f21-2610-475b-9e1d-ddf33638ed9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449525278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1449525278 |
| Directory | /workspace/4.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.434682289 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 391143902 ps |
| CPU time | 1.14 seconds |
| Started | May 26 02:37:21 PM PDT 24 |
| Finished | May 26 02:37:23 PM PDT 24 |
| Peak memory | 183568 kb |
| Host | smart-07f7b363-5677-4775-837e-00ffc66aa443 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434682289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti mer_mem_partial_access.434682289 |
| Directory | /workspace/4.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3526787931 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 385578922 ps |
| CPU time | 1.11 seconds |
| Started | May 26 02:37:21 PM PDT 24 |
| Finished | May 26 02:37:23 PM PDT 24 |
| Peak memory | 183640 kb |
| Host | smart-0aed1666-e63a-4e59-ac9f-cc8f6631d205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526787931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w alk.3526787931 |
| Directory | /workspace/4.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.830035260 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2124576808 ps |
| CPU time | 3.51 seconds |
| Started | May 26 02:37:21 PM PDT 24 |
| Finished | May 26 02:37:25 PM PDT 24 |
| Peak memory | 193912 kb |
| Host | smart-71a5fd74-6421-4d76-af9c-7fe4426fc596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830035260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ timer_same_csr_outstanding.830035260 |
| Directory | /workspace/4.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3636592581 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 417179060 ps |
| CPU time | 2.08 seconds |
| Started | May 26 02:37:23 PM PDT 24 |
| Finished | May 26 02:37:26 PM PDT 24 |
| Peak memory | 198648 kb |
| Host | smart-b6d619ab-4f70-4374-a001-e6681a615d01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636592581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3636592581 |
| Directory | /workspace/4.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3194294312 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 8341076746 ps |
| CPU time | 3.72 seconds |
| Started | May 26 02:37:21 PM PDT 24 |
| Finished | May 26 02:37:25 PM PDT 24 |
| Peak memory | 198056 kb |
| Host | smart-c1b81566-29f1-4f00-bd5a-1139c199d05f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194294312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl _intg_err.3194294312 |
| Directory | /workspace/4.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1439698354 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 377154691 ps |
| CPU time | 1.11 seconds |
| Started | May 26 02:38:02 PM PDT 24 |
| Finished | May 26 02:38:04 PM PDT 24 |
| Peak memory | 183608 kb |
| Host | smart-acdd42f5-976d-4156-ba8d-3d166911b568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439698354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1439698354 |
| Directory | /workspace/40.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2283656080 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 300980375 ps |
| CPU time | 0.63 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:01 PM PDT 24 |
| Peak memory | 183644 kb |
| Host | smart-50511d90-c9b7-4a92-95c5-0c2ee58acbe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283656080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2283656080 |
| Directory | /workspace/41.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1788465660 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 431901068 ps |
| CPU time | 0.71 seconds |
| Started | May 26 02:38:10 PM PDT 24 |
| Finished | May 26 02:38:13 PM PDT 24 |
| Peak memory | 183684 kb |
| Host | smart-6a744ada-de4e-45ba-98ef-91aa9972acad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788465660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1788465660 |
| Directory | /workspace/42.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3139852468 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 453341677 ps |
| CPU time | 0.88 seconds |
| Started | May 26 02:38:01 PM PDT 24 |
| Finished | May 26 02:38:03 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-54ed7b02-9fd7-4a96-a829-5a1dd4a84ce8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139852468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3139852468 |
| Directory | /workspace/43.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3365259565 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 432934619 ps |
| CPU time | 1.31 seconds |
| Started | May 26 02:38:00 PM PDT 24 |
| Finished | May 26 02:38:03 PM PDT 24 |
| Peak memory | 183796 kb |
| Host | smart-fdc0eb8d-e008-42c1-8e49-4e9a1eb89580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365259565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3365259565 |
| Directory | /workspace/44.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2442734875 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 374771672 ps |
| CPU time | 0.66 seconds |
| Started | May 26 02:37:59 PM PDT 24 |
| Finished | May 26 02:38:02 PM PDT 24 |
| Peak memory | 183640 kb |
| Host | smart-777fb7d7-bdc5-4ca1-b853-50a04057c7e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442734875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2442734875 |
| Directory | /workspace/45.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.4068130228 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 476554919 ps |
| CPU time | 0.7 seconds |
| Started | May 26 02:38:01 PM PDT 24 |
| Finished | May 26 02:38:03 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-5e5a218d-ddf2-4782-8675-5a3c1edd455b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068130228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.4068130228 |
| Directory | /workspace/46.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.12536773 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 392647247 ps |
| CPU time | 1.04 seconds |
| Started | May 26 02:38:10 PM PDT 24 |
| Finished | May 26 02:38:12 PM PDT 24 |
| Peak memory | 183660 kb |
| Host | smart-4a657611-d0de-4c3b-ba69-d982d6cea0b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12536773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.12536773 |
| Directory | /workspace/47.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3485007805 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 302079844 ps |
| CPU time | 0.68 seconds |
| Started | May 26 02:38:07 PM PDT 24 |
| Finished | May 26 02:38:08 PM PDT 24 |
| Peak memory | 183600 kb |
| Host | smart-cc3ea999-bb8b-40bc-a4c5-f78b2be91528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485007805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3485007805 |
| Directory | /workspace/48.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1354033088 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 440254584 ps |
| CPU time | 0.79 seconds |
| Started | May 26 02:38:06 PM PDT 24 |
| Finished | May 26 02:38:08 PM PDT 24 |
| Peak memory | 183812 kb |
| Host | smart-dd252965-72b6-4a81-99fa-afe1fd49e621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354033088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1354033088 |
| Directory | /workspace/49.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.358204786 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 504683992 ps |
| CPU time | 1.41 seconds |
| Started | May 26 02:37:30 PM PDT 24 |
| Finished | May 26 02:37:32 PM PDT 24 |
| Peak memory | 196052 kb |
| Host | smart-87b84a18-b35f-4ff9-b445-6a3bfc4d8f41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358204786 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.358204786 |
| Directory | /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2352817150 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 438599730 ps |
| CPU time | 0.93 seconds |
| Started | May 26 02:37:29 PM PDT 24 |
| Finished | May 26 02:37:31 PM PDT 24 |
| Peak memory | 193156 kb |
| Host | smart-e9d2ec49-fe4c-46b3-8b6a-f06e7b9cd51e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352817150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2352817150 |
| Directory | /workspace/5.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.564890239 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 381802598 ps |
| CPU time | 0.55 seconds |
| Started | May 26 02:37:29 PM PDT 24 |
| Finished | May 26 02:37:30 PM PDT 24 |
| Peak memory | 183640 kb |
| Host | smart-523135f0-31b6-4c1f-a4d2-8a0384f54f40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564890239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.564890239 |
| Directory | /workspace/5.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2239807352 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1215513832 ps |
| CPU time | 2.57 seconds |
| Started | May 26 02:37:30 PM PDT 24 |
| Finished | May 26 02:37:33 PM PDT 24 |
| Peak memory | 193520 kb |
| Host | smart-c4d98bc3-4f93-49d9-9f4e-f50c8cfa4f6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239807352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon _timer_same_csr_outstanding.2239807352 |
| Directory | /workspace/5.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3560960834 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 690270506 ps |
| CPU time | 2.18 seconds |
| Started | May 26 02:37:29 PM PDT 24 |
| Finished | May 26 02:37:32 PM PDT 24 |
| Peak memory | 198420 kb |
| Host | smart-68d833ad-efbb-479d-b2a7-9265f0938a1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560960834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3560960834 |
| Directory | /workspace/5.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1870286650 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3743133097 ps |
| CPU time | 4.15 seconds |
| Started | May 26 02:37:29 PM PDT 24 |
| Finished | May 26 02:37:34 PM PDT 24 |
| Peak memory | 197644 kb |
| Host | smart-0978e24c-dd19-4de5-9f33-b1886b4d2cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870286650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl _intg_err.1870286650 |
| Directory | /workspace/5.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2733043902 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 627214262 ps |
| CPU time | 1.13 seconds |
| Started | May 26 02:37:39 PM PDT 24 |
| Finished | May 26 02:37:40 PM PDT 24 |
| Peak memory | 196368 kb |
| Host | smart-005a15aa-5712-49a9-b415-32b8455bd222 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733043902 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2733043902 |
| Directory | /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2558985603 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 504422224 ps |
| CPU time | 0.73 seconds |
| Started | May 26 02:37:38 PM PDT 24 |
| Finished | May 26 02:37:40 PM PDT 24 |
| Peak memory | 183768 kb |
| Host | smart-cbc9f4a5-ff47-4d39-861e-7f0afa1dd42c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558985603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2558985603 |
| Directory | /workspace/6.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2066708756 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 431820975 ps |
| CPU time | 1.17 seconds |
| Started | May 26 02:37:30 PM PDT 24 |
| Finished | May 26 02:37:32 PM PDT 24 |
| Peak memory | 183640 kb |
| Host | smart-bfc8eed0-8ac0-434f-85c7-df693865fe8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066708756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2066708756 |
| Directory | /workspace/6.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1461937649 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2341849061 ps |
| CPU time | 4.02 seconds |
| Started | May 26 02:37:37 PM PDT 24 |
| Finished | May 26 02:37:42 PM PDT 24 |
| Peak memory | 183956 kb |
| Host | smart-79797e95-e009-435e-a736-98dd5c7b03a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461937649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon _timer_same_csr_outstanding.1461937649 |
| Directory | /workspace/6.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.957870633 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 428772024 ps |
| CPU time | 1.46 seconds |
| Started | May 26 02:37:27 PM PDT 24 |
| Finished | May 26 02:37:29 PM PDT 24 |
| Peak memory | 198392 kb |
| Host | smart-8d5493bd-1978-484c-b58d-73ae93a7486f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957870633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.957870633 |
| Directory | /workspace/6.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1115119298 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3911110914 ps |
| CPU time | 5.08 seconds |
| Started | May 26 02:37:28 PM PDT 24 |
| Finished | May 26 02:37:34 PM PDT 24 |
| Peak memory | 196684 kb |
| Host | smart-a7ca3f92-62e4-4c99-8590-0e46887c3b29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115119298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl _intg_err.1115119298 |
| Directory | /workspace/6.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.824442987 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 349978265 ps |
| CPU time | 0.77 seconds |
| Started | May 26 02:37:36 PM PDT 24 |
| Finished | May 26 02:37:37 PM PDT 24 |
| Peak memory | 195924 kb |
| Host | smart-c96e3ccb-dd8f-4552-8882-306eb5431c78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824442987 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.824442987 |
| Directory | /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4159984278 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 404656576 ps |
| CPU time | 0.68 seconds |
| Started | May 26 02:37:38 PM PDT 24 |
| Finished | May 26 02:37:40 PM PDT 24 |
| Peak memory | 183776 kb |
| Host | smart-c513fa36-8841-4169-a877-fda92ded6c81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159984278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.4159984278 |
| Directory | /workspace/7.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3037894985 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 492186767 ps |
| CPU time | 0.92 seconds |
| Started | May 26 02:37:37 PM PDT 24 |
| Finished | May 26 02:37:39 PM PDT 24 |
| Peak memory | 183624 kb |
| Host | smart-ebdb332c-8f7e-496b-aa3b-a4067f0d07fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037894985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3037894985 |
| Directory | /workspace/7.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.160576311 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1522188705 ps |
| CPU time | 2.11 seconds |
| Started | May 26 02:37:36 PM PDT 24 |
| Finished | May 26 02:37:38 PM PDT 24 |
| Peak memory | 183908 kb |
| Host | smart-8fda05a0-6964-411e-adab-8a075b5252f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160576311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_ timer_same_csr_outstanding.160576311 |
| Directory | /workspace/7.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.795746577 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 358436844 ps |
| CPU time | 2 seconds |
| Started | May 26 02:37:37 PM PDT 24 |
| Finished | May 26 02:37:39 PM PDT 24 |
| Peak memory | 198448 kb |
| Host | smart-5193665c-e0c2-4955-8cb7-6b13f49b419a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795746577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.795746577 |
| Directory | /workspace/7.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1998335967 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 8076245247 ps |
| CPU time | 6.29 seconds |
| Started | May 26 02:37:37 PM PDT 24 |
| Finished | May 26 02:37:45 PM PDT 24 |
| Peak memory | 198084 kb |
| Host | smart-c35ba9f4-9bc6-423e-a856-b91bd156fb07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998335967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl _intg_err.1998335967 |
| Directory | /workspace/7.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.222911957 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 453787719 ps |
| CPU time | 0.95 seconds |
| Started | May 26 02:37:36 PM PDT 24 |
| Finished | May 26 02:37:38 PM PDT 24 |
| Peak memory | 197460 kb |
| Host | smart-ad812447-57f4-452e-84f2-047afac95edc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222911957 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.222911957 |
| Directory | /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3891229307 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 525122335 ps |
| CPU time | 1.01 seconds |
| Started | May 26 02:37:37 PM PDT 24 |
| Finished | May 26 02:37:40 PM PDT 24 |
| Peak memory | 183760 kb |
| Host | smart-c7f5fa28-5777-4855-ba57-ac41e9c547f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891229307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3891229307 |
| Directory | /workspace/8.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3195369677 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 279173811 ps |
| CPU time | 0.84 seconds |
| Started | May 26 02:37:38 PM PDT 24 |
| Finished | May 26 02:37:40 PM PDT 24 |
| Peak memory | 183644 kb |
| Host | smart-31f3db8e-5352-4ba1-a807-976da77f3ef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195369677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3195369677 |
| Directory | /workspace/8.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.865761845 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3000302558 ps |
| CPU time | 2.6 seconds |
| Started | May 26 02:37:38 PM PDT 24 |
| Finished | May 26 02:37:42 PM PDT 24 |
| Peak memory | 194616 kb |
| Host | smart-ce4e0074-d53d-4ca4-b480-95101f27a9e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865761845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_ timer_same_csr_outstanding.865761845 |
| Directory | /workspace/8.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2739796793 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 543961554 ps |
| CPU time | 1.47 seconds |
| Started | May 26 02:37:37 PM PDT 24 |
| Finished | May 26 02:37:39 PM PDT 24 |
| Peak memory | 198644 kb |
| Host | smart-06ad9dd3-faf1-4752-a5ab-3fd19bf6c3d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739796793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2739796793 |
| Directory | /workspace/8.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.61427214 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 620342430 ps |
| CPU time | 1.26 seconds |
| Started | May 26 02:37:46 PM PDT 24 |
| Finished | May 26 02:37:48 PM PDT 24 |
| Peak memory | 196852 kb |
| Host | smart-d5c2fd7c-676a-4fd9-970d-9e32ca95c0e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61427214 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.61427214 |
| Directory | /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.94016089 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 322686101 ps |
| CPU time | 1.07 seconds |
| Started | May 26 02:37:44 PM PDT 24 |
| Finished | May 26 02:37:46 PM PDT 24 |
| Peak memory | 193228 kb |
| Host | smart-c94fd1bf-695c-4aaf-aa89-a85a3e915421 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94016089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.94016089 |
| Directory | /workspace/9.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.342255925 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 393197072 ps |
| CPU time | 1.06 seconds |
| Started | May 26 02:37:43 PM PDT 24 |
| Finished | May 26 02:37:45 PM PDT 24 |
| Peak memory | 183604 kb |
| Host | smart-00815086-a2a9-4b79-a136-b65ae4818028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342255925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.342255925 |
| Directory | /workspace/9.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1551767438 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2828664756 ps |
| CPU time | 6.17 seconds |
| Started | May 26 02:37:43 PM PDT 24 |
| Finished | May 26 02:37:50 PM PDT 24 |
| Peak memory | 194400 kb |
| Host | smart-c7b0fb76-0523-4f62-97ce-30869aa22df6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551767438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon _timer_same_csr_outstanding.1551767438 |
| Directory | /workspace/9.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.132357717 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 535508356 ps |
| CPU time | 1.11 seconds |
| Started | May 26 02:37:36 PM PDT 24 |
| Finished | May 26 02:37:38 PM PDT 24 |
| Peak memory | 198328 kb |
| Host | smart-c69b131f-36a7-4e22-8bff-c4946fb9efd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132357717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.132357717 |
| Directory | /workspace/9.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2775769901 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 8914205219 ps |
| CPU time | 3.31 seconds |
| Started | May 26 02:37:37 PM PDT 24 |
| Finished | May 26 02:37:41 PM PDT 24 |
| Peak memory | 198056 kb |
| Host | smart-13c60259-875d-43ad-b0a0-791e5c6d88bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775769901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl _intg_err.2775769901 |
| Directory | /workspace/9.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.aon_timer_prescaler.2919383667 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 18285377795 ps |
| CPU time | 27.59 seconds |
| Started | May 26 01:54:10 PM PDT 24 |
| Finished | May 26 01:54:39 PM PDT 24 |
| Peak memory | 191892 kb |
| Host | smart-025f13c1-37a7-434e-bbfa-b6273a4b6533 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2919383667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2919383667 |
| Directory | /workspace/0.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/0.aon_timer_smoke.2971757905 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 437683149 ps |
| CPU time | 1.22 seconds |
| Started | May 26 01:54:15 PM PDT 24 |
| Finished | May 26 01:54:18 PM PDT 24 |
| Peak memory | 191820 kb |
| Host | smart-4de0fcba-a44d-4b73-b90c-97561dfb537a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2971757905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2971757905 |
| Directory | /workspace/0.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/1.aon_timer_prescaler.3410050752 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 36465479859 ps |
| CPU time | 54.7 seconds |
| Started | May 26 01:54:27 PM PDT 24 |
| Finished | May 26 01:55:22 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-ff18deb0-d49a-4447-aed4-7fed1702c577 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3410050752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3410050752 |
| Directory | /workspace/1.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/1.aon_timer_sec_cm.850211679 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3899471371 ps |
| CPU time | 3.83 seconds |
| Started | May 26 01:54:12 PM PDT 24 |
| Finished | May 26 01:54:17 PM PDT 24 |
| Peak memory | 215264 kb |
| Host | smart-27523880-acb3-4d42-814d-b8e93845bb37 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850211679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.850211679 |
| Directory | /workspace/1.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/1.aon_timer_smoke.1226294263 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 500464162 ps |
| CPU time | 0.63 seconds |
| Started | May 26 01:54:15 PM PDT 24 |
| Finished | May 26 01:54:17 PM PDT 24 |
| Peak memory | 191820 kb |
| Host | smart-554d682e-a157-46d1-b8b4-407c7255d608 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1226294263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1226294263 |
| Directory | /workspace/1.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2321899354 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 15769810018 ps |
| CPU time | 124.05 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:56:21 PM PDT 24 |
| Peak memory | 206892 kb |
| Host | smart-0ddaa5e7-52a1-4928-9443-61d4d3c0700f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321899354 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2321899354 |
| Directory | /workspace/1.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.aon_timer_jump.2322378954 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 509291187 ps |
| CPU time | 0.74 seconds |
| Started | May 26 01:54:26 PM PDT 24 |
| Finished | May 26 01:54:27 PM PDT 24 |
| Peak memory | 196504 kb |
| Host | smart-b71cf522-3231-4fa2-80da-67ac72e8f574 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322378954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2322378954 |
| Directory | /workspace/10.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/10.aon_timer_prescaler.3159046963 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 31185821492 ps |
| CPU time | 49.33 seconds |
| Started | May 26 01:54:15 PM PDT 24 |
| Finished | May 26 01:55:06 PM PDT 24 |
| Peak memory | 191892 kb |
| Host | smart-efcb5258-0845-42d2-8c53-780214e4781c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159046963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3159046963 |
| Directory | /workspace/10.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/10.aon_timer_smoke.2333545104 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 475910618 ps |
| CPU time | 1.28 seconds |
| Started | May 26 01:54:29 PM PDT 24 |
| Finished | May 26 01:54:31 PM PDT 24 |
| Peak memory | 191772 kb |
| Host | smart-1586ba54-583c-472a-b311-8169050fb5bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2333545104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2333545104 |
| Directory | /workspace/10.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/11.aon_timer_prescaler.1474201917 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2772105056 ps |
| CPU time | 5.46 seconds |
| Started | May 26 01:54:21 PM PDT 24 |
| Finished | May 26 01:54:28 PM PDT 24 |
| Peak memory | 191912 kb |
| Host | smart-56943c05-54b4-454c-a41f-17a1e4e61cac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1474201917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1474201917 |
| Directory | /workspace/11.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/11.aon_timer_smoke.2656111113 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 571534386 ps |
| CPU time | 1.54 seconds |
| Started | May 26 01:54:20 PM PDT 24 |
| Finished | May 26 01:54:23 PM PDT 24 |
| Peak memory | 191768 kb |
| Host | smart-72ec9964-e38e-458c-9a0f-34b4bcf72c08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656111113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2656111113 |
| Directory | /workspace/11.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/12.aon_timer_prescaler.1116819218 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6862013314 ps |
| CPU time | 3.35 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:54:21 PM PDT 24 |
| Peak memory | 191892 kb |
| Host | smart-cadf5d14-5df2-4d3c-8dd9-a0a75af20590 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1116819218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1116819218 |
| Directory | /workspace/12.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/12.aon_timer_smoke.1188696328 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 388312452 ps |
| CPU time | 0.72 seconds |
| Started | May 26 01:54:18 PM PDT 24 |
| Finished | May 26 01:54:20 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-8d9aad97-92c6-4b1b-a225-ecbfa0d1cda5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188696328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1188696328 |
| Directory | /workspace/12.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/13.aon_timer_prescaler.132070139 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 27982334940 ps |
| CPU time | 38.02 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:54:56 PM PDT 24 |
| Peak memory | 191944 kb |
| Host | smart-c9f5cbd7-9bbb-413f-bf5b-9cc488ed9a93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132070139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.132070139 |
| Directory | /workspace/13.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/13.aon_timer_smoke.3263629890 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 537954077 ps |
| CPU time | 1.5 seconds |
| Started | May 26 01:54:23 PM PDT 24 |
| Finished | May 26 01:54:26 PM PDT 24 |
| Peak memory | 191756 kb |
| Host | smart-b18b70b9-b1f4-4c85-92b2-e3350e4fda03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263629890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3263629890 |
| Directory | /workspace/13.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/14.aon_timer_prescaler.262509586 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 27070112381 ps |
| CPU time | 37.34 seconds |
| Started | May 26 01:54:43 PM PDT 24 |
| Finished | May 26 01:55:21 PM PDT 24 |
| Peak memory | 191968 kb |
| Host | smart-33a42224-a181-4a6f-9653-3d0f67e57560 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262509586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.262509586 |
| Directory | /workspace/14.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/14.aon_timer_smoke.10271033 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 467141624 ps |
| CPU time | 1.26 seconds |
| Started | May 26 01:54:30 PM PDT 24 |
| Finished | May 26 01:54:33 PM PDT 24 |
| Peak memory | 191804 kb |
| Host | smart-5fe9a161-0292-41d2-abd4-d50d1656dba5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10271033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.10271033 |
| Directory | /workspace/14.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/15.aon_timer_prescaler.2240874996 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 56575594448 ps |
| CPU time | 44.54 seconds |
| Started | May 26 01:54:25 PM PDT 24 |
| Finished | May 26 01:55:10 PM PDT 24 |
| Peak memory | 191836 kb |
| Host | smart-11c70b09-530a-40f3-98c0-7cc00c80775e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2240874996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2240874996 |
| Directory | /workspace/15.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/15.aon_timer_smoke.3392456931 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 549398099 ps |
| CPU time | 0.82 seconds |
| Started | May 26 01:54:30 PM PDT 24 |
| Finished | May 26 01:54:32 PM PDT 24 |
| Peak memory | 196352 kb |
| Host | smart-94631da7-aced-416b-88ee-d7b705b4cd21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3392456931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3392456931 |
| Directory | /workspace/15.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/16.aon_timer_prescaler.3462499995 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 61518000409 ps |
| CPU time | 95.01 seconds |
| Started | May 26 01:54:35 PM PDT 24 |
| Finished | May 26 01:56:11 PM PDT 24 |
| Peak memory | 191884 kb |
| Host | smart-451be663-df3e-49a9-a1b0-ffe81c3837b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462499995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3462499995 |
| Directory | /workspace/16.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/16.aon_timer_smoke.4114073836 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 412798808 ps |
| CPU time | 1.17 seconds |
| Started | May 26 01:54:35 PM PDT 24 |
| Finished | May 26 01:54:36 PM PDT 24 |
| Peak memory | 191840 kb |
| Host | smart-0bcfc206-2803-4dd0-b998-08762084356c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4114073836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.4114073836 |
| Directory | /workspace/16.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1514801106 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 14608349477 ps |
| CPU time | 108.38 seconds |
| Started | May 26 01:54:35 PM PDT 24 |
| Finished | May 26 01:56:24 PM PDT 24 |
| Peak memory | 206780 kb |
| Host | smart-510d5b62-156b-418a-afa9-632e81f42dc8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514801106 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1514801106 |
| Directory | /workspace/16.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.aon_timer_prescaler.1401030671 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 13286212141 ps |
| CPU time | 20.66 seconds |
| Started | May 26 01:54:35 PM PDT 24 |
| Finished | May 26 01:54:56 PM PDT 24 |
| Peak memory | 191932 kb |
| Host | smart-8b5654ec-ee11-4574-b08c-9d3fdde02083 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1401030671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1401030671 |
| Directory | /workspace/17.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/17.aon_timer_smoke.385024775 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 446486458 ps |
| CPU time | 0.86 seconds |
| Started | May 26 01:54:31 PM PDT 24 |
| Finished | May 26 01:54:33 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-c90bcd0c-fcc6-40d3-8760-41fb9b32c2c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=385024775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.385024775 |
| Directory | /workspace/17.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/18.aon_timer_prescaler.3707216762 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 9974829408 ps |
| CPU time | 8.41 seconds |
| Started | May 26 01:54:29 PM PDT 24 |
| Finished | May 26 01:54:39 PM PDT 24 |
| Peak memory | 191840 kb |
| Host | smart-9bbfa530-833f-4e37-b698-af62dd9cce46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3707216762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3707216762 |
| Directory | /workspace/18.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/18.aon_timer_smoke.265149737 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 453891331 ps |
| CPU time | 0.66 seconds |
| Started | May 26 01:54:28 PM PDT 24 |
| Finished | May 26 01:54:29 PM PDT 24 |
| Peak memory | 191756 kb |
| Host | smart-4afe84d0-ed32-4a44-89d8-c700fc66fa02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265149737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.265149737 |
| Directory | /workspace/18.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/19.aon_timer_prescaler.2697064013 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 19663133782 ps |
| CPU time | 16.28 seconds |
| Started | May 26 01:54:36 PM PDT 24 |
| Finished | May 26 01:54:53 PM PDT 24 |
| Peak memory | 191864 kb |
| Host | smart-a6209331-577d-4fa9-890d-455071d6c8e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697064013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2697064013 |
| Directory | /workspace/19.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/19.aon_timer_smoke.3201619284 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 555962279 ps |
| CPU time | 1.56 seconds |
| Started | May 26 01:54:30 PM PDT 24 |
| Finished | May 26 01:54:33 PM PDT 24 |
| Peak memory | 191812 kb |
| Host | smart-6f9ac92f-a23a-4a3e-b56e-db4bf765b4f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3201619284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3201619284 |
| Directory | /workspace/19.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/2.aon_timer_prescaler.350559469 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 17698621241 ps |
| CPU time | 7.13 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:54:24 PM PDT 24 |
| Peak memory | 191892 kb |
| Host | smart-98ca4ad5-9f4d-44ae-804e-f49e98627440 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350559469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.350559469 |
| Directory | /workspace/2.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/2.aon_timer_sec_cm.3491865711 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7693413247 ps |
| CPU time | 6.68 seconds |
| Started | May 26 01:54:12 PM PDT 24 |
| Finished | May 26 01:54:21 PM PDT 24 |
| Peak memory | 215744 kb |
| Host | smart-87ff8342-a15f-4c11-8312-c622571b630e |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491865711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3491865711 |
| Directory | /workspace/2.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/2.aon_timer_smoke.1296110685 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 481649597 ps |
| CPU time | 0.94 seconds |
| Started | May 26 01:54:15 PM PDT 24 |
| Finished | May 26 01:54:17 PM PDT 24 |
| Peak memory | 191820 kb |
| Host | smart-208586a4-8acf-48a3-92b6-9caff324a797 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296110685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1296110685 |
| Directory | /workspace/2.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/20.aon_timer_prescaler.1124183977 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 26977352004 ps |
| CPU time | 37.03 seconds |
| Started | May 26 01:54:27 PM PDT 24 |
| Finished | May 26 01:55:05 PM PDT 24 |
| Peak memory | 191932 kb |
| Host | smart-a89214af-67d4-46a3-ad62-036935b41c62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1124183977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1124183977 |
| Directory | /workspace/20.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/20.aon_timer_smoke.62687671 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 465312165 ps |
| CPU time | 0.73 seconds |
| Started | May 26 01:54:33 PM PDT 24 |
| Finished | May 26 01:54:34 PM PDT 24 |
| Peak memory | 191712 kb |
| Host | smart-ee2a27ec-ae5b-4033-9fb8-4b41e8f5ddd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62687671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.62687671 |
| Directory | /workspace/20.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/21.aon_timer_prescaler.2618077314 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 899680334 ps |
| CPU time | 1.98 seconds |
| Started | May 26 01:54:28 PM PDT 24 |
| Finished | May 26 01:54:31 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-096212e2-cbc7-4077-ae5c-9b2f8ad9e23c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618077314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2618077314 |
| Directory | /workspace/21.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/21.aon_timer_smoke.3224254060 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 362367988 ps |
| CPU time | 1.06 seconds |
| Started | May 26 01:54:29 PM PDT 24 |
| Finished | May 26 01:54:32 PM PDT 24 |
| Peak memory | 191784 kb |
| Host | smart-0816d704-2084-4af2-a62d-0226aa91b43c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3224254060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3224254060 |
| Directory | /workspace/21.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/22.aon_timer_jump.1108657780 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 413147091 ps |
| CPU time | 0.75 seconds |
| Started | May 26 01:54:31 PM PDT 24 |
| Finished | May 26 01:54:33 PM PDT 24 |
| Peak memory | 196460 kb |
| Host | smart-a0d70bde-4ae0-4205-9491-afa805abe038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108657780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1108657780 |
| Directory | /workspace/22.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/22.aon_timer_prescaler.3705626442 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 976677351 ps |
| CPU time | 0.97 seconds |
| Started | May 26 01:54:36 PM PDT 24 |
| Finished | May 26 01:54:38 PM PDT 24 |
| Peak memory | 191828 kb |
| Host | smart-c2a63404-f630-4a5b-9944-fe7141203784 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705626442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3705626442 |
| Directory | /workspace/22.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/22.aon_timer_smoke.803950276 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 385589760 ps |
| CPU time | 1.31 seconds |
| Started | May 26 01:54:23 PM PDT 24 |
| Finished | May 26 01:54:26 PM PDT 24 |
| Peak memory | 191812 kb |
| Host | smart-5a9fb78b-c6a9-4be4-94f5-4923213a37a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=803950276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.803950276 |
| Directory | /workspace/22.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/23.aon_timer_jump.3944120110 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 667702930 ps |
| CPU time | 0.75 seconds |
| Started | May 26 01:54:29 PM PDT 24 |
| Finished | May 26 01:54:31 PM PDT 24 |
| Peak memory | 196624 kb |
| Host | smart-d2406ee2-d0ec-4750-af22-34c33e6ccda0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944120110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3944120110 |
| Directory | /workspace/23.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/23.aon_timer_prescaler.789486171 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 20882705089 ps |
| CPU time | 8.74 seconds |
| Started | May 26 01:54:31 PM PDT 24 |
| Finished | May 26 01:54:41 PM PDT 24 |
| Peak memory | 191904 kb |
| Host | smart-bdfdbc30-d4a5-40e6-a342-44a5957fee54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789486171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.789486171 |
| Directory | /workspace/23.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/23.aon_timer_smoke.2785132435 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 494014922 ps |
| CPU time | 0.67 seconds |
| Started | May 26 01:54:31 PM PDT 24 |
| Finished | May 26 01:54:33 PM PDT 24 |
| Peak memory | 191800 kb |
| Host | smart-f65a3bfa-3b4d-4577-999a-46e5a5813a8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785132435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2785132435 |
| Directory | /workspace/23.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/24.aon_timer_jump.3696184591 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 564929993 ps |
| CPU time | 1.56 seconds |
| Started | May 26 01:54:30 PM PDT 24 |
| Finished | May 26 01:54:33 PM PDT 24 |
| Peak memory | 196388 kb |
| Host | smart-2de8a212-aa84-4bab-9467-50261bb65517 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696184591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3696184591 |
| Directory | /workspace/24.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/24.aon_timer_prescaler.351933864 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 18472761635 ps |
| CPU time | 15.36 seconds |
| Started | May 26 01:54:44 PM PDT 24 |
| Finished | May 26 01:55:00 PM PDT 24 |
| Peak memory | 191952 kb |
| Host | smart-370cdc86-d62e-4a7f-954a-75950281f7e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=351933864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.351933864 |
| Directory | /workspace/24.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/24.aon_timer_smoke.3757577408 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 536983750 ps |
| CPU time | 0.82 seconds |
| Started | May 26 01:54:30 PM PDT 24 |
| Finished | May 26 01:54:32 PM PDT 24 |
| Peak memory | 191716 kb |
| Host | smart-058347bb-8ea3-465d-b0e5-d449f1872cc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757577408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3757577408 |
| Directory | /workspace/24.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/25.aon_timer_prescaler.1667286497 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 50029239397 ps |
| CPU time | 75.87 seconds |
| Started | May 26 01:54:39 PM PDT 24 |
| Finished | May 26 01:55:56 PM PDT 24 |
| Peak memory | 191924 kb |
| Host | smart-6a2227ef-5c7c-4b30-8a02-4adac1fce758 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1667286497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1667286497 |
| Directory | /workspace/25.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/25.aon_timer_smoke.1871433491 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 439947289 ps |
| CPU time | 0.93 seconds |
| Started | May 26 01:54:40 PM PDT 24 |
| Finished | May 26 01:54:42 PM PDT 24 |
| Peak memory | 191852 kb |
| Host | smart-8e3f9516-f791-4295-93df-5af00fa4d5fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871433491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1871433491 |
| Directory | /workspace/25.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/25.aon_timer_stress_all.3944884203 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 85091880335 ps |
| CPU time | 31.73 seconds |
| Started | May 26 01:54:44 PM PDT 24 |
| Finished | May 26 01:55:17 PM PDT 24 |
| Peak memory | 191800 kb |
| Host | smart-07ebe460-c169-43af-976f-b354c36a0076 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944884203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_ all.3944884203 |
| Directory | /workspace/25.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.aon_timer_prescaler.2903636421 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 5376222318 ps |
| CPU time | 9.44 seconds |
| Started | May 26 01:54:37 PM PDT 24 |
| Finished | May 26 01:54:47 PM PDT 24 |
| Peak memory | 191920 kb |
| Host | smart-a43e19ad-7bd7-488e-ac5c-67f9ffe52133 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903636421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2903636421 |
| Directory | /workspace/26.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/26.aon_timer_smoke.1040240783 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 534712847 ps |
| CPU time | 1.28 seconds |
| Started | May 26 01:54:35 PM PDT 24 |
| Finished | May 26 01:54:37 PM PDT 24 |
| Peak memory | 191820 kb |
| Host | smart-012d0557-84ba-4378-9cbd-28de1363928e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040240783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1040240783 |
| Directory | /workspace/26.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/27.aon_timer_prescaler.1631067306 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2428049814 ps |
| CPU time | 4.6 seconds |
| Started | May 26 01:54:40 PM PDT 24 |
| Finished | May 26 01:54:45 PM PDT 24 |
| Peak memory | 191932 kb |
| Host | smart-2df6d21f-d813-47a0-866f-ecf98cb026f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631067306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1631067306 |
| Directory | /workspace/27.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/27.aon_timer_smoke.624209261 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 394368741 ps |
| CPU time | 1.27 seconds |
| Started | May 26 01:54:40 PM PDT 24 |
| Finished | May 26 01:54:42 PM PDT 24 |
| Peak memory | 191764 kb |
| Host | smart-73689017-07e9-49fb-baeb-eb12ad74c0e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624209261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.624209261 |
| Directory | /workspace/27.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/28.aon_timer_prescaler.2699109991 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 28044700041 ps |
| CPU time | 41.95 seconds |
| Started | May 26 01:54:40 PM PDT 24 |
| Finished | May 26 01:55:23 PM PDT 24 |
| Peak memory | 191864 kb |
| Host | smart-ef4e5566-f078-4e18-a66b-e4357f18a815 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2699109991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2699109991 |
| Directory | /workspace/28.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/28.aon_timer_smoke.145979828 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 375209702 ps |
| CPU time | 1.14 seconds |
| Started | May 26 01:54:39 PM PDT 24 |
| Finished | May 26 01:54:41 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-7611f127-3f3d-402c-8d5a-3cf5b73821a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=145979828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.145979828 |
| Directory | /workspace/28.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/29.aon_timer_prescaler.1394928435 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 25354560176 ps |
| CPU time | 33.31 seconds |
| Started | May 26 01:54:45 PM PDT 24 |
| Finished | May 26 01:55:19 PM PDT 24 |
| Peak memory | 191864 kb |
| Host | smart-83b39bbb-3e5b-463b-8ab9-030756b2d79c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394928435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1394928435 |
| Directory | /workspace/29.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/29.aon_timer_smoke.108560069 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 565315263 ps |
| CPU time | 1.4 seconds |
| Started | May 26 01:54:40 PM PDT 24 |
| Finished | May 26 01:54:42 PM PDT 24 |
| Peak memory | 191784 kb |
| Host | smart-01b4858d-762a-464d-bc94-1725cd6164fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108560069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.108560069 |
| Directory | /workspace/29.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/3.aon_timer_prescaler.4270778888 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 8115343850 ps |
| CPU time | 12.2 seconds |
| Started | May 26 01:54:23 PM PDT 24 |
| Finished | May 26 01:54:36 PM PDT 24 |
| Peak memory | 191912 kb |
| Host | smart-81765f60-8586-46b1-a3ee-b17b646ea1f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4270778888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.4270778888 |
| Directory | /workspace/3.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/3.aon_timer_sec_cm.1404864930 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7708108736 ps |
| CPU time | 6.84 seconds |
| Started | May 26 01:54:20 PM PDT 24 |
| Finished | May 26 01:54:28 PM PDT 24 |
| Peak memory | 215672 kb |
| Host | smart-12128d35-a240-472a-9fd1-18a10a15346f |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404864930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1404864930 |
| Directory | /workspace/3.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/3.aon_timer_smoke.2492171766 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 365266855 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:54:23 PM PDT 24 |
| Finished | May 26 01:54:25 PM PDT 24 |
| Peak memory | 191788 kb |
| Host | smart-5fa2d9cf-748e-42a1-a4cd-0e3c33679f72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492171766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2492171766 |
| Directory | /workspace/3.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/30.aon_timer_prescaler.736340574 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 28468725183 ps |
| CPU time | 36.44 seconds |
| Started | May 26 01:54:45 PM PDT 24 |
| Finished | May 26 01:55:23 PM PDT 24 |
| Peak memory | 191852 kb |
| Host | smart-17b06e19-9ddf-4916-9e2f-a1f372081ddc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736340574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.736340574 |
| Directory | /workspace/30.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/30.aon_timer_smoke.756744135 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 455049806 ps |
| CPU time | 0.8 seconds |
| Started | May 26 01:54:40 PM PDT 24 |
| Finished | May 26 01:54:42 PM PDT 24 |
| Peak memory | 191784 kb |
| Host | smart-8d5be35c-3edd-4d66-83ad-088aab3cc401 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756744135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.756744135 |
| Directory | /workspace/30.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/31.aon_timer_prescaler.1015526804 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 48774551018 ps |
| CPU time | 11.95 seconds |
| Started | May 26 01:54:42 PM PDT 24 |
| Finished | May 26 01:54:55 PM PDT 24 |
| Peak memory | 191952 kb |
| Host | smart-962a2cc0-9351-4a02-96bc-1cfdda15304c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1015526804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1015526804 |
| Directory | /workspace/31.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/31.aon_timer_smoke.295567540 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 653339972 ps |
| CPU time | 0.64 seconds |
| Started | May 26 01:54:39 PM PDT 24 |
| Finished | May 26 01:54:41 PM PDT 24 |
| Peak memory | 191996 kb |
| Host | smart-ad8de404-7ff4-40fe-8e03-dbdd08577ddd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295567540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.295567540 |
| Directory | /workspace/31.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/32.aon_timer_prescaler.513478096 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 22455777111 ps |
| CPU time | 34.61 seconds |
| Started | May 26 01:54:45 PM PDT 24 |
| Finished | May 26 01:55:21 PM PDT 24 |
| Peak memory | 191908 kb |
| Host | smart-cc226e30-e259-4358-acaf-bebfd4741378 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513478096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.513478096 |
| Directory | /workspace/32.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/32.aon_timer_smoke.3018061181 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 541382249 ps |
| CPU time | 1.12 seconds |
| Started | May 26 01:54:37 PM PDT 24 |
| Finished | May 26 01:54:39 PM PDT 24 |
| Peak memory | 191820 kb |
| Host | smart-d76ee23e-ea99-49c4-8257-f613157705d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018061181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3018061181 |
| Directory | /workspace/32.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/33.aon_timer_prescaler.79939058 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 2118326789 ps |
| CPU time | 1.68 seconds |
| Started | May 26 01:54:50 PM PDT 24 |
| Finished | May 26 01:54:52 PM PDT 24 |
| Peak memory | 191772 kb |
| Host | smart-e7283a65-5e86-45c7-a770-ca6f73fbbd16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79939058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.79939058 |
| Directory | /workspace/33.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/33.aon_timer_smoke.3454540890 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 417425920 ps |
| CPU time | 1.28 seconds |
| Started | May 26 01:54:46 PM PDT 24 |
| Finished | May 26 01:54:48 PM PDT 24 |
| Peak memory | 191812 kb |
| Host | smart-f9b59245-e107-4f1b-b748-8e3084810955 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3454540890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3454540890 |
| Directory | /workspace/33.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/34.aon_timer_smoke.3629170927 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 471709987 ps |
| CPU time | 0.78 seconds |
| Started | May 26 01:54:40 PM PDT 24 |
| Finished | May 26 01:54:42 PM PDT 24 |
| Peak memory | 191796 kb |
| Host | smart-535eff1b-160e-461c-b142-b4e5c7437a1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629170927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3629170927 |
| Directory | /workspace/34.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/35.aon_timer_prescaler.4088964646 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 27346239553 ps |
| CPU time | 4.59 seconds |
| Started | May 26 01:54:50 PM PDT 24 |
| Finished | May 26 01:54:56 PM PDT 24 |
| Peak memory | 191852 kb |
| Host | smart-4c82b83c-022a-4481-96a3-4af499418ac6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4088964646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4088964646 |
| Directory | /workspace/35.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/35.aon_timer_smoke.1527435440 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 537528689 ps |
| CPU time | 0.61 seconds |
| Started | May 26 01:54:52 PM PDT 24 |
| Finished | May 26 01:54:53 PM PDT 24 |
| Peak memory | 191824 kb |
| Host | smart-6c49f786-d37f-4828-b40e-5245c6dc04f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527435440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1527435440 |
| Directory | /workspace/35.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/36.aon_timer_prescaler.237088818 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 30998808857 ps |
| CPU time | 11.22 seconds |
| Started | May 26 01:54:48 PM PDT 24 |
| Finished | May 26 01:55:00 PM PDT 24 |
| Peak memory | 191932 kb |
| Host | smart-8ecdb17c-6b3a-4077-b7b2-10dcb8fa9537 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=237088818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.237088818 |
| Directory | /workspace/36.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/36.aon_timer_smoke.178006908 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 670314508 ps |
| CPU time | 0.65 seconds |
| Started | May 26 01:54:44 PM PDT 24 |
| Finished | May 26 01:54:46 PM PDT 24 |
| Peak memory | 191820 kb |
| Host | smart-c7bc5cb2-7f7a-41dd-a6b7-c35cb0a65510 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=178006908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.178006908 |
| Directory | /workspace/36.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/37.aon_timer_prescaler.3939572907 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 11167235237 ps |
| CPU time | 3.83 seconds |
| Started | May 26 01:54:50 PM PDT 24 |
| Finished | May 26 01:54:55 PM PDT 24 |
| Peak memory | 191904 kb |
| Host | smart-77bf5e27-214c-4f60-8dc4-98f3c29a8db9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3939572907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3939572907 |
| Directory | /workspace/37.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/37.aon_timer_smoke.2582297065 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 360187464 ps |
| CPU time | 1.24 seconds |
| Started | May 26 01:54:48 PM PDT 24 |
| Finished | May 26 01:54:50 PM PDT 24 |
| Peak memory | 191792 kb |
| Host | smart-973c07bf-08e2-4043-8e8d-7b4e5adcb26d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582297065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2582297065 |
| Directory | /workspace/37.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/38.aon_timer_prescaler.1859916273 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 14208024109 ps |
| CPU time | 1.77 seconds |
| Started | May 26 01:54:48 PM PDT 24 |
| Finished | May 26 01:54:51 PM PDT 24 |
| Peak memory | 191836 kb |
| Host | smart-17fdad3d-8d66-429f-9014-299d50754c19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859916273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1859916273 |
| Directory | /workspace/38.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/38.aon_timer_smoke.3090348402 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 621881069 ps |
| CPU time | 0.85 seconds |
| Started | May 26 01:54:44 PM PDT 24 |
| Finished | May 26 01:54:45 PM PDT 24 |
| Peak memory | 191744 kb |
| Host | smart-a1b7b219-2965-4c47-a8cd-435c660702c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090348402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3090348402 |
| Directory | /workspace/38.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/39.aon_timer_prescaler.3424696309 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 11514011602 ps |
| CPU time | 3.88 seconds |
| Started | May 26 01:54:45 PM PDT 24 |
| Finished | May 26 01:54:50 PM PDT 24 |
| Peak memory | 191852 kb |
| Host | smart-57678e6f-4550-46d0-85ee-8d84dc2460b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424696309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3424696309 |
| Directory | /workspace/39.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/39.aon_timer_smoke.2365727549 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 555700235 ps |
| CPU time | 0.8 seconds |
| Started | May 26 01:54:44 PM PDT 24 |
| Finished | May 26 01:54:46 PM PDT 24 |
| Peak memory | 191772 kb |
| Host | smart-100a0af6-2076-4670-af08-c7fb8d407285 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2365727549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2365727549 |
| Directory | /workspace/39.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/4.aon_timer_prescaler.3862025714 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 20537930681 ps |
| CPU time | 8.59 seconds |
| Started | May 26 01:54:11 PM PDT 24 |
| Finished | May 26 01:54:22 PM PDT 24 |
| Peak memory | 191840 kb |
| Host | smart-ebbae12d-727d-4654-98dd-036eb75c45cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3862025714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3862025714 |
| Directory | /workspace/4.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/4.aon_timer_sec_cm.1038152441 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8791626909 ps |
| CPU time | 3.12 seconds |
| Started | May 26 01:54:23 PM PDT 24 |
| Finished | May 26 01:54:27 PM PDT 24 |
| Peak memory | 215644 kb |
| Host | smart-24672ecf-895a-49df-aa02-8def733d8e14 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038152441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1038152441 |
| Directory | /workspace/4.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/4.aon_timer_smoke.3955132403 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 601467098 ps |
| CPU time | 1.06 seconds |
| Started | May 26 01:54:11 PM PDT 24 |
| Finished | May 26 01:54:14 PM PDT 24 |
| Peak memory | 191756 kb |
| Host | smart-841d1c41-c6b6-4916-b21f-f30ea3498e35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3955132403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3955132403 |
| Directory | /workspace/4.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/40.aon_timer_prescaler.3056980370 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 50307023587 ps |
| CPU time | 5.84 seconds |
| Started | May 26 01:54:47 PM PDT 24 |
| Finished | May 26 01:54:54 PM PDT 24 |
| Peak memory | 191924 kb |
| Host | smart-191e94b0-f4d3-4fe8-a9b5-e71356a6ec8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3056980370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3056980370 |
| Directory | /workspace/40.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/40.aon_timer_smoke.3986907871 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 472423970 ps |
| CPU time | 0.92 seconds |
| Started | May 26 01:54:43 PM PDT 24 |
| Finished | May 26 01:54:45 PM PDT 24 |
| Peak memory | 191716 kb |
| Host | smart-3f995c68-bddf-42fa-89a3-21759651882b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986907871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3986907871 |
| Directory | /workspace/40.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/41.aon_timer_prescaler.4257542634 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 17907966205 ps |
| CPU time | 6.39 seconds |
| Started | May 26 01:54:51 PM PDT 24 |
| Finished | May 26 01:54:58 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-ec0e5485-efb2-4ca1-8cff-76abdb3f1efe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4257542634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.4257542634 |
| Directory | /workspace/41.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/41.aon_timer_smoke.4061503380 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 539935306 ps |
| CPU time | 1.35 seconds |
| Started | May 26 01:54:53 PM PDT 24 |
| Finished | May 26 01:54:56 PM PDT 24 |
| Peak memory | 191776 kb |
| Host | smart-7947419f-2759-4ea0-b1d7-d21504485b71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061503380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.4061503380 |
| Directory | /workspace/41.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/42.aon_timer_prescaler.1918071196 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8268923207 ps |
| CPU time | 13.82 seconds |
| Started | May 26 01:54:55 PM PDT 24 |
| Finished | May 26 01:55:10 PM PDT 24 |
| Peak memory | 191892 kb |
| Host | smart-b3cffe16-bbcb-4d09-a0d7-f830fc4df859 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1918071196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1918071196 |
| Directory | /workspace/42.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/42.aon_timer_smoke.3928030245 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 600933211 ps |
| CPU time | 0.63 seconds |
| Started | May 26 01:54:56 PM PDT 24 |
| Finished | May 26 01:54:57 PM PDT 24 |
| Peak memory | 191824 kb |
| Host | smart-e99d76cb-39a8-486c-99f8-de6a5a160997 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3928030245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3928030245 |
| Directory | /workspace/42.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/43.aon_timer_prescaler.2520287210 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 20587741788 ps |
| CPU time | 15.39 seconds |
| Started | May 26 01:54:55 PM PDT 24 |
| Finished | May 26 01:55:11 PM PDT 24 |
| Peak memory | 191912 kb |
| Host | smart-f1f235c8-9515-4aa0-a06b-dcad038328a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2520287210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2520287210 |
| Directory | /workspace/43.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/43.aon_timer_smoke.1153518588 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 435546267 ps |
| CPU time | 0.75 seconds |
| Started | May 26 01:54:57 PM PDT 24 |
| Finished | May 26 01:54:59 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-f723c7a0-985d-4f4e-a273-fbf5be38d95e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153518588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1153518588 |
| Directory | /workspace/43.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/44.aon_timer_jump.575179608 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 599955631 ps |
| CPU time | 1.02 seconds |
| Started | May 26 01:54:53 PM PDT 24 |
| Finished | May 26 01:54:55 PM PDT 24 |
| Peak memory | 196508 kb |
| Host | smart-a0af525c-a7df-403e-b6a5-c9ebef60171d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575179608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.575179608 |
| Directory | /workspace/44.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/44.aon_timer_prescaler.2618058630 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 14747767906 ps |
| CPU time | 6.37 seconds |
| Started | May 26 01:54:57 PM PDT 24 |
| Finished | May 26 01:55:05 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-bc027776-15bc-4eff-96d1-9e022f625e62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618058630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2618058630 |
| Directory | /workspace/44.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/44.aon_timer_smoke.1914040634 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 622783610 ps |
| CPU time | 0.96 seconds |
| Started | May 26 01:54:55 PM PDT 24 |
| Finished | May 26 01:54:57 PM PDT 24 |
| Peak memory | 191772 kb |
| Host | smart-2f035daf-2411-482f-a0d0-37d4a6364535 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1914040634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1914040634 |
| Directory | /workspace/44.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/45.aon_timer_prescaler.3680459540 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 5357552640 ps |
| CPU time | 8.53 seconds |
| Started | May 26 01:54:57 PM PDT 24 |
| Finished | May 26 01:55:07 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-dfb19df0-54c1-4eb6-baae-4ebf3117f1a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3680459540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3680459540 |
| Directory | /workspace/45.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/45.aon_timer_smoke.3247109644 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 504438741 ps |
| CPU time | 0.78 seconds |
| Started | May 26 01:54:50 PM PDT 24 |
| Finished | May 26 01:54:52 PM PDT 24 |
| Peak memory | 191800 kb |
| Host | smart-790964ce-d391-4afc-a3d2-618208462b5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3247109644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3247109644 |
| Directory | /workspace/45.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/46.aon_timer_prescaler.2905807056 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 21277170417 ps |
| CPU time | 4.69 seconds |
| Started | May 26 01:54:56 PM PDT 24 |
| Finished | May 26 01:55:02 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-c5bb94b3-501b-4142-a7f6-e4e0a36b362b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905807056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2905807056 |
| Directory | /workspace/46.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/46.aon_timer_smoke.3194064537 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 553971285 ps |
| CPU time | 1.29 seconds |
| Started | May 26 01:54:54 PM PDT 24 |
| Finished | May 26 01:54:56 PM PDT 24 |
| Peak memory | 191792 kb |
| Host | smart-48431f6c-3673-4066-a354-462a5071941b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3194064537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3194064537 |
| Directory | /workspace/46.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/47.aon_timer_prescaler.880560852 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13775576521 ps |
| CPU time | 4.95 seconds |
| Started | May 26 01:54:55 PM PDT 24 |
| Finished | May 26 01:55:01 PM PDT 24 |
| Peak memory | 191900 kb |
| Host | smart-74f43b2b-439a-4897-920a-205fc2f319c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=880560852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.880560852 |
| Directory | /workspace/47.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/47.aon_timer_smoke.3869567186 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 407898975 ps |
| CPU time | 1.18 seconds |
| Started | May 26 01:54:58 PM PDT 24 |
| Finished | May 26 01:55:00 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-110df37f-322d-48f3-8307-0dcc8b7b59ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3869567186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3869567186 |
| Directory | /workspace/47.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/48.aon_timer_prescaler.3233306065 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 14189772871 ps |
| CPU time | 20.81 seconds |
| Started | May 26 01:54:56 PM PDT 24 |
| Finished | May 26 01:55:18 PM PDT 24 |
| Peak memory | 191892 kb |
| Host | smart-cf6f25ac-8733-4ad6-98c9-a8ee74a361c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3233306065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3233306065 |
| Directory | /workspace/48.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/48.aon_timer_smoke.913381956 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 554192962 ps |
| CPU time | 0.87 seconds |
| Started | May 26 01:55:02 PM PDT 24 |
| Finished | May 26 01:55:04 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-4ebbf794-e986-4834-9fb2-6d79ff2603b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=913381956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.913381956 |
| Directory | /workspace/48.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/49.aon_timer_jump.3356264290 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 531995627 ps |
| CPU time | 0.98 seconds |
| Started | May 26 01:55:01 PM PDT 24 |
| Finished | May 26 01:55:03 PM PDT 24 |
| Peak memory | 196420 kb |
| Host | smart-b6a0b176-69d5-4069-aef0-641d02297a79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3356264290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3356264290 |
| Directory | /workspace/49.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/49.aon_timer_prescaler.275608068 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 8491513934 ps |
| CPU time | 14.49 seconds |
| Started | May 26 01:55:01 PM PDT 24 |
| Finished | May 26 01:55:16 PM PDT 24 |
| Peak memory | 191940 kb |
| Host | smart-35106621-6ad0-496d-a6eb-644d5b18b7a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275608068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.275608068 |
| Directory | /workspace/49.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/49.aon_timer_smoke.2266844740 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 414579864 ps |
| CPU time | 0.8 seconds |
| Started | May 26 01:55:04 PM PDT 24 |
| Finished | May 26 01:55:06 PM PDT 24 |
| Peak memory | 191768 kb |
| Host | smart-3149df50-bbaa-485f-b562-fb8ddeb066cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266844740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2266844740 |
| Directory | /workspace/49.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/5.aon_timer_prescaler.1376179259 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 22436641357 ps |
| CPU time | 18.73 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:54:36 PM PDT 24 |
| Peak memory | 191904 kb |
| Host | smart-305fcf40-246e-45d7-bd5f-1426f81c7eb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376179259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1376179259 |
| Directory | /workspace/5.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/5.aon_timer_smoke.337015157 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 458812915 ps |
| CPU time | 0.73 seconds |
| Started | May 26 01:54:24 PM PDT 24 |
| Finished | May 26 01:54:26 PM PDT 24 |
| Peak memory | 191784 kb |
| Host | smart-885e0b59-1bd7-4e59-b557-6d497ac027d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=337015157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.337015157 |
| Directory | /workspace/5.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/6.aon_timer_prescaler.1907587422 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29061628871 ps |
| CPU time | 20.99 seconds |
| Started | May 26 01:54:24 PM PDT 24 |
| Finished | May 26 01:54:45 PM PDT 24 |
| Peak memory | 191880 kb |
| Host | smart-2dc176c6-0189-4d3b-8d7a-d8aac503e216 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907587422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1907587422 |
| Directory | /workspace/6.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/6.aon_timer_smoke.2450003923 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 421636348 ps |
| CPU time | 0.75 seconds |
| Started | May 26 01:54:13 PM PDT 24 |
| Finished | May 26 01:54:15 PM PDT 24 |
| Peak memory | 191772 kb |
| Host | smart-5278edbe-3145-4702-856c-04dee4bd36bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2450003923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2450003923 |
| Directory | /workspace/6.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/7.aon_timer_prescaler.2697502542 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 24967350963 ps |
| CPU time | 41.44 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:54:59 PM PDT 24 |
| Peak memory | 191892 kb |
| Host | smart-a2d6500b-77bb-4e15-bbd7-59945cf4af39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697502542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2697502542 |
| Directory | /workspace/7.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/7.aon_timer_smoke.677365581 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 478742358 ps |
| CPU time | 0.75 seconds |
| Started | May 26 01:54:25 PM PDT 24 |
| Finished | May 26 01:54:27 PM PDT 24 |
| Peak memory | 191800 kb |
| Host | smart-e6b4fb2e-cf3f-419e-ab81-8b443b9114ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677365581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.677365581 |
| Directory | /workspace/7.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/8.aon_timer_prescaler.3008899269 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 56000452617 ps |
| CPU time | 86.37 seconds |
| Started | May 26 01:54:25 PM PDT 24 |
| Finished | May 26 01:55:52 PM PDT 24 |
| Peak memory | 191904 kb |
| Host | smart-214af63a-5119-4946-8e79-a34b15d06951 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008899269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3008899269 |
| Directory | /workspace/8.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/8.aon_timer_smoke.339723027 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 467716842 ps |
| CPU time | 0.63 seconds |
| Started | May 26 01:54:18 PM PDT 24 |
| Finished | May 26 01:54:19 PM PDT 24 |
| Peak memory | 191828 kb |
| Host | smart-778efb40-257b-45b3-8408-69ddb349f5a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339723027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.339723027 |
| Directory | /workspace/8.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/9.aon_timer_prescaler.1919927612 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 3405501346 ps |
| CPU time | 1.47 seconds |
| Started | May 26 01:54:18 PM PDT 24 |
| Finished | May 26 01:54:20 PM PDT 24 |
| Peak memory | 191884 kb |
| Host | smart-ecf8a1b4-c12b-46de-82ea-c3618af112b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1919927612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1919927612 |
| Directory | /workspace/9.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/9.aon_timer_smoke.4166473864 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 447257680 ps |
| CPU time | 1.16 seconds |
| Started | May 26 01:54:16 PM PDT 24 |
| Finished | May 26 01:54:23 PM PDT 24 |
| Peak memory | 191812 kb |
| Host | smart-c50c3a5e-8311-4403-948d-bde383847906 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166473864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.4166473864 |
| Directory | /workspace/9.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1764109265 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 33569191853 ps |
| CPU time | 276.12 seconds |
| Started | May 26 01:54:25 PM PDT 24 |
| Finished | May 26 01:59:01 PM PDT 24 |
| Peak memory | 206768 kb |
| Host | smart-30deda4e-db08-4c78-8d51-af7d4ffbd23b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764109265 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1764109265 |
| Directory | /workspace/9.aon_timer_stress_all_with_rand_reset/latest |
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