Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	29213	1		T1	12		T2	12		T4	12
bark[1]	319	1		T3	14		T8	21		T180	14
bark[2]	956	1		T8	302		T32	14		T44	236
bark[3]	464	1		T39	21		T119	28		T166	21
bark[4]	585	1		T170	79		T142	35		T166	19
bark[5]	535	1		T12	14		T27	14		T154	21
bark[6]	542	1		T39	44		T40	134		T170	21
bark[7]	186	1		T40	21		T119	21		T118	14
bark[8]	420	1		T50	26		T91	26		T186	39
bark[9]	356	1		T16	21		T122	30		T192	14
bark[10]	314	1		T45	21		T68	21		T85	21
bark[11]	850	1		T205	113		T89	21		T50	213
bark[12]	437	1		T40	107		T96	14		T25	14
bark[13]	315	1		T41	21		T101	21		T26	14
bark[14]	633	1		T41	7		T137	21		T136	14
bark[15]	791	1		T8	226		T39	21		T41	283
bark[16]	554	1		T44	104		T50	21		T85	21
bark[17]	496	1		T8	26		T39	170		T151	21
bark[18]	221	1		T9	14		T101	21		T144	21
bark[19]	224	1		T5	30		T11	21		T42	47
bark[20]	642	1		T39	21		T40	182		T119	21
bark[21]	588	1		T48	14		T170	21		T188	14
bark[22]	393	1		T6	49		T8	26		T42	26
bark[23]	435	1		T6	120		T122	102		T134	21
bark[24]	698	1		T11	61		T16	21		T39	21
bark[25]	596	1		T25	21		T103	30		T116	42
bark[26]	369	1		T41	21		T99	14		T50	71
bark[27]	410	1		T16	30		T198	14		T158	14
bark[28]	235	1		T119	21		T154	21		T159	21
bark[29]	182	1		T39	21		T42	49		T182	19
bark[30]	499	1		T5	39		T7	26		T101	26
bark[31]	622	1		T5	88		T110	14		T165	14
bark_0	4354	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	28336	1		T1	11		T2	11		T4	11
bite[1]	427	1		T195	13		T186	21		T145	13
bite[2]	795	1		T12	13		T39	169		T89	21
bite[3]	449	1		T5	30		T16	21		T101	26
bite[4]	76	1		T21	21		T91	21		T109	13
bite[5]	544	1		T3	13		T11	61		T110	13
bite[6]	754	1		T6	119		T99	13		T21	105
bite[7]	356	1		T11	21		T40	21		T118	21
bite[8]	329	1		T40	25		T24	13		T103	21
bite[9]	565	1		T166	18		T205	113		T118	21
bite[10]	1020	1		T16	21		T41	23		T42	48
bite[11]	602	1		T119	21		T44	235		T182	18
bite[12]	516	1		T8	301		T160	70		T90	21
bite[13]	507	1		T40	106		T25	21		T67	31
bite[14]	584	1		T180	13		T42	46		T44	103
bite[15]	539	1		T32	13		T39	21		T160	39
bite[16]	177	1		T5	88		T39	21		T69	21
bite[17]	340	1		T9	13		T40	146		T101	21
bite[18]	185	1		T142	55		T67	58		T143	21
bite[19]	650	1		T8	246		T40	35		T137	57
bite[20]	788	1		T40	25		T25	13		T45	6
bite[21]	830	1		T40	107		T96	13		T25	42
bite[22]	331	1		T6	48		T170	21		T165	13
bite[23]	397	1		T39	21		T41	21		T26	13
bite[24]	552	1		T119	42		T170	79		T158	13
bite[25]	372	1		T7	25		T39	43		T41	66
bite[26]	788	1		T101	21		T45	21		T137	21
bite[27]	262	1		T16	30		T39	21		T134	21
bite[28]	296	1		T8	26		T39	21		T170	21
bite[29]	159	1		T5	39		T160	51		T179	21
bite[30]	716	1		T8	25		T48	13		T41	282
bite[31]	420	1		T122	102		T166	21		T116	21
bite_0	4772	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	48434	1		T1	19		T2	19		T3	21

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1401	1		T8	61		T39	69		T40	37
prescale[1]	508	1		T6	2		T7	20		T44	80
prescale[2]	1059	1		T5	19		T7	2		T39	132
prescale[3]	1036	1		T5	9		T7	67		T39	19
prescale[4]	965	1		T8	33		T39	40		T41	35
prescale[5]	652	1		T8	58		T16	23		T39	35
prescale[6]	1425	1		T6	30		T41	141		T21	23
prescale[7]	677	1		T4	9		T6	2		T8	48
prescale[8]	689	1		T25	24		T43	2		T137	45
prescale[9]	539	1		T7	18		T11	19		T40	33
prescale[10]	580	1		T16	41		T39	2		T41	2
prescale[11]	650	1		T1	9		T8	154		T40	63
prescale[12]	404	1		T43	2		T137	19		T50	19
prescale[13]	557	1		T6	2		T7	40		T47	9
prescale[14]	494	1		T7	90		T8	37		T41	37
prescale[15]	502	1		T40	2		T21	19		T45	23
prescale[16]	359	1		T40	65		T41	40		T44	2
prescale[17]	619	1		T7	19		T40	58		T41	2
prescale[18]	1299	1		T7	39		T162	67		T206	9
prescale[19]	483	1		T97	9		T25	24		T119	28
prescale[20]	654	1		T8	121		T101	49		T42	2
prescale[21]	837	1		T5	38		T7	175		T8	2
prescale[22]	394	1		T8	2		T11	23		T41	82
prescale[23]	569	1		T10	9		T11	28		T101	19
prescale[24]	1022	1		T7	2		T40	38		T43	44
prescale[25]	906	1		T7	82		T8	93		T11	19
prescale[26]	525	1		T7	37		T16	37		T42	2
prescale[27]	415	1		T7	21		T11	40		T40	52
prescale[28]	851	1		T5	37		T8	28		T16	19
prescale[29]	1136	1		T5	19		T49	9		T41	78
prescale[30]	588	1		T40	21		T41	2		T101	9
prescale[31]	1181	1		T2	9		T11	28		T39	19
prescale_0	24458	1		T1	10		T2	10		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	36857	1		T1	19		T2	9		T3	9
auto[1]	11577	1		T2	10		T3	12		T5	86

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	48434	1		T1	19		T2	19		T3	21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	28896	1		T1	14		T2	14		T3	1
wkup[1]	292	1		T50	21		T143	21		T129	26
wkup[2]	290	1		T3	15		T7	42		T8	21
wkup[3]	305	1		T7	30		T44	42		T182	20
wkup[4]	209	1		T8	21		T43	21		T119	21
wkup[5]	379	1		T11	21		T40	35		T24	15
wkup[6]	315	1		T39	21		T41	21		T170	21
wkup[7]	247	1		T42	21		T43	26		T45	21
wkup[8]	125	1		T11	21		T69	15		T144	21
wkup[9]	191	1		T5	30		T25	21		T142	35
wkup[10]	177	1		T5	21		T16	30		T44	21
wkup[11]	350	1		T45	21		T137	21		T154	21
wkup[12]	147	1		T6	8		T7	26		T44	21
wkup[13]	222	1		T32	15		T160	21		T132	21
wkup[14]	384	1		T7	15		T8	42		T40	51
wkup[15]	262	1		T43	21		T44	26		T45	8
wkup[16]	112	1		T156	15		T50	26		T131	21
wkup[17]	301	1		T41	21		T21	21		T118	21
wkup[18]	286	1		T42	21		T119	21		T44	56
wkup[19]	342	1		T25	21		T26	15		T44	21
wkup[20]	132	1		T7	30		T50	30		T113	30
wkup[21]	260	1		T41	21		T44	21		T69	21
wkup[22]	188	1		T142	21		T162	21		T134	21
wkup[23]	312	1		T6	26		T39	21		T40	26
wkup[24]	132	1		T7	21		T192	15		T126	30
wkup[25]	218	1		T7	21		T8	21		T50	15
wkup[26]	257	1		T7	26		T119	21		T142	21
wkup[27]	369	1		T7	21		T41	21		T43	26
wkup[28]	263	1		T41	21		T110	15		T170	21
wkup[29]	333	1		T39	30		T41	15		T69	30
wkup[30]	185	1		T25	21		T154	21		T69	30
wkup[31]	228	1		T44	47		T162	30		T177	15
wkup[32]	430	1		T39	21		T44	26		T69	51
wkup[33]	290	1		T9	15		T44	15		T89	26
wkup[34]	241	1		T43	8		T119	29		T89	21
wkup[35]	189	1		T119	21		T154	21		T67	21
wkup[36]	300	1		T41	51		T69	31		T144	21
wkup[37]	414	1		T7	26		T39	30		T25	15
wkup[38]	283	1		T39	42		T41	26		T89	21
wkup[39]	222	1		T41	21		T45	15		T205	26
wkup[40]	302	1		T7	21		T8	21		T39	42
wkup[41]	315	1		T5	30		T39	21		T40	21
wkup[42]	236	1		T8	21		T44	21		T182	21
wkup[43]	283	1		T8	21		T50	36		T69	21
wkup[44]	146	1		T41	21		T188	15		T50	42
wkup[45]	152	1		T8	20		T44	21		T159	15
wkup[46]	529	1		T8	21		T39	20		T40	21
wkup[47]	155	1		T8	21		T154	21		T143	35
wkup[48]	298	1		T44	21		T137	21		T166	20
wkup[49]	222	1		T48	15		T40	30		T43	21
wkup[50]	203	1		T40	42		T21	21		T68	21
wkup[51]	237	1		T6	30		T50	21		T116	21
wkup[52]	277	1		T7	21		T41	8		T136	15
wkup[53]	238	1		T41	21		T44	21		T166	30
wkup[54]	149	1		T40	21		T27	15		T143	21
wkup[55]	308	1		T8	21		T11	21		T16	21
wkup[56]	271	1		T39	21		T21	21		T50	21
wkup[57]	236	1		T5	21		T8	42		T41	8
wkup[58]	275	1		T39	21		T44	31		T50	26
wkup[59]	255	1		T99	15		T101	21		T25	21
wkup[60]	99	1		T142	21		T198	15		T162	21
wkup[61]	250	1		T8	21		T103	26		T90	21
wkup[62]	323	1		T16	21		T96	15		T101	26
wkup[63]	223	1		T12	15		T39	47		T44	26
wkup_0	3374	1		T1	5		T2	5		T3	5