Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.06 99.33 93.67 100.00 98.40 99.51 49.44


Total test records in report: 419
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T34 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.617977441 May 28 01:46:55 PM PDT 24 May 28 01:47:01 PM PDT 24 8288469199 ps
T288 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1999685573 May 28 01:47:34 PM PDT 24 May 28 01:47:39 PM PDT 24 394940573 ps
T35 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1221655941 May 28 01:47:12 PM PDT 24 May 28 01:47:22 PM PDT 24 2839812163 ps
T51 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4156297726 May 28 01:47:33 PM PDT 24 May 28 01:47:38 PM PDT 24 490926824 ps
T38 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.109909878 May 28 01:46:45 PM PDT 24 May 28 01:46:49 PM PDT 24 1412295243 ps
T207 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2618334715 May 28 01:46:56 PM PDT 24 May 28 01:46:59 PM PDT 24 448063489 ps
T289 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3201336225 May 28 01:46:43 PM PDT 24 May 28 01:46:48 PM PDT 24 489968618 ps
T290 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3197857073 May 28 01:47:33 PM PDT 24 May 28 01:47:38 PM PDT 24 313068513 ps
T291 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2938853128 May 28 01:46:40 PM PDT 24 May 28 01:46:47 PM PDT 24 414748792 ps
T52 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.215157496 May 28 01:46:58 PM PDT 24 May 28 01:47:15 PM PDT 24 8450777762 ps
T292 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2718666323 May 28 01:46:47 PM PDT 24 May 28 01:46:49 PM PDT 24 368839170 ps
T208 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4221099513 May 28 01:47:14 PM PDT 24 May 28 01:47:17 PM PDT 24 415528454 ps
T53 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2459769091 May 28 01:46:57 PM PDT 24 May 28 01:47:00 PM PDT 24 384320034 ps
T76 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1702512641 May 28 01:47:11 PM PDT 24 May 28 01:47:16 PM PDT 24 2041472025 ps
T293 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.154401231 May 28 01:47:28 PM PDT 24 May 28 01:47:30 PM PDT 24 386711510 ps
T294 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2500272583 May 28 01:47:11 PM PDT 24 May 28 01:47:13 PM PDT 24 599875725 ps
T77 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1563823742 May 28 01:46:43 PM PDT 24 May 28 01:46:52 PM PDT 24 2105592132 ps
T295 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3700247015 May 28 01:47:11 PM PDT 24 May 28 01:47:15 PM PDT 24 550568042 ps
T296 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1886512814 May 28 01:47:35 PM PDT 24 May 28 01:47:40 PM PDT 24 379501489 ps
T297 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3171692828 May 28 01:47:08 PM PDT 24 May 28 01:47:10 PM PDT 24 475223382 ps
T298 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1657387433 May 28 01:47:33 PM PDT 24 May 28 01:47:37 PM PDT 24 360362969 ps
T299 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3754933369 May 28 01:47:14 PM PDT 24 May 28 01:47:17 PM PDT 24 484809383 ps
T300 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2528228242 May 28 01:47:29 PM PDT 24 May 28 01:47:32 PM PDT 24 303451182 ps
T301 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1836695070 May 28 01:47:10 PM PDT 24 May 28 01:47:15 PM PDT 24 869956194 ps
T302 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.875687606 May 28 01:47:35 PM PDT 24 May 28 01:47:41 PM PDT 24 387290875 ps
T303 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3098691166 May 28 01:47:29 PM PDT 24 May 28 01:47:32 PM PDT 24 616324874 ps
T304 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.426974743 May 28 01:47:34 PM PDT 24 May 28 01:47:39 PM PDT 24 473546459 ps
T36 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2509387944 May 28 01:46:41 PM PDT 24 May 28 01:46:53 PM PDT 24 4686817127 ps
T305 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.336389519 May 28 01:47:35 PM PDT 24 May 28 01:47:40 PM PDT 24 482122578 ps
T78 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3219602594 May 28 01:47:33 PM PDT 24 May 28 01:47:39 PM PDT 24 2495178164 ps
T79 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.676858355 May 28 01:47:10 PM PDT 24 May 28 01:47:19 PM PDT 24 2259161582 ps
T306 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1577566274 May 28 01:46:28 PM PDT 24 May 28 01:46:43 PM PDT 24 396247217 ps
T307 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3429939628 May 28 01:46:42 PM PDT 24 May 28 01:46:48 PM PDT 24 392465852 ps
T308 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2455707415 May 28 01:47:05 PM PDT 24 May 28 01:47:07 PM PDT 24 496247438 ps
T37 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1222518557 May 28 01:47:30 PM PDT 24 May 28 01:47:38 PM PDT 24 8702909209 ps
T54 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1255017016 May 28 01:47:10 PM PDT 24 May 28 01:47:13 PM PDT 24 496555819 ps
T55 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.192741851 May 28 01:46:45 PM PDT 24 May 28 01:46:48 PM PDT 24 515283104 ps
T309 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3474710308 May 28 01:46:57 PM PDT 24 May 28 01:47:02 PM PDT 24 326527768 ps
T310 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3888101536 May 28 01:47:04 PM PDT 24 May 28 01:47:06 PM PDT 24 483365478 ps
T200 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3984207608 May 28 01:47:12 PM PDT 24 May 28 01:47:20 PM PDT 24 4346790710 ps
T311 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3339737467 May 28 01:46:47 PM PDT 24 May 28 01:46:50 PM PDT 24 764495524 ps
T312 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1662559599 May 28 01:47:19 PM PDT 24 May 28 01:47:21 PM PDT 24 403642775 ps
T201 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3025141110 May 28 01:46:57 PM PDT 24 May 28 01:47:04 PM PDT 24 8052628144 ps
T313 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3418900254 May 28 01:47:31 PM PDT 24 May 28 01:47:34 PM PDT 24 583215174 ps
T314 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.367211483 May 28 01:47:11 PM PDT 24 May 28 01:47:13 PM PDT 24 522132194 ps
T315 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4194966637 May 28 01:47:32 PM PDT 24 May 28 01:47:35 PM PDT 24 434219819 ps
T316 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.347742726 May 28 01:47:35 PM PDT 24 May 28 01:47:41 PM PDT 24 408047334 ps
T317 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3514688227 May 28 01:47:32 PM PDT 24 May 28 01:47:36 PM PDT 24 392992662 ps
T318 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.755108684 May 28 01:46:47 PM PDT 24 May 28 01:46:50 PM PDT 24 405768936 ps
T319 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.459547629 May 28 01:46:59 PM PDT 24 May 28 01:47:01 PM PDT 24 380465340 ps
T320 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.4188929152 May 28 01:47:35 PM PDT 24 May 28 01:47:41 PM PDT 24 468088999 ps
T80 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3645638347 May 28 01:47:34 PM PDT 24 May 28 01:47:44 PM PDT 24 2774000709 ps
T321 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1235597657 May 28 01:47:10 PM PDT 24 May 28 01:47:13 PM PDT 24 539408648 ps
T322 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1566072934 May 28 01:47:09 PM PDT 24 May 28 01:47:14 PM PDT 24 4551813771 ps
T323 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2595788726 May 28 01:47:30 PM PDT 24 May 28 01:47:34 PM PDT 24 768064529 ps
T81 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3973308071 May 28 01:47:05 PM PDT 24 May 28 01:47:10 PM PDT 24 2089684007 ps
T82 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1954910263 May 28 01:46:56 PM PDT 24 May 28 01:47:04 PM PDT 24 2945206466 ps
T203 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2021184541 May 28 01:47:34 PM PDT 24 May 28 01:47:42 PM PDT 24 4067208169 ps
T324 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1869719560 May 28 01:47:33 PM PDT 24 May 28 01:47:38 PM PDT 24 528939690 ps
T325 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.936377041 May 28 01:47:10 PM PDT 24 May 28 01:47:13 PM PDT 24 382137892 ps
T83 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4125942610 May 28 01:47:09 PM PDT 24 May 28 01:47:12 PM PDT 24 2633094369 ps
T326 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.977268017 May 28 01:47:33 PM PDT 24 May 28 01:47:38 PM PDT 24 433185647 ps
T327 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1094943156 May 28 01:46:42 PM PDT 24 May 28 01:46:47 PM PDT 24 298460201 ps
T328 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3027444549 May 28 01:47:09 PM PDT 24 May 28 01:47:13 PM PDT 24 4308427819 ps
T329 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3651255962 May 28 01:47:30 PM PDT 24 May 28 01:47:32 PM PDT 24 510129407 ps
T330 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3130147481 May 28 01:46:55 PM PDT 24 May 28 01:46:58 PM PDT 24 532859778 ps
T56 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4135343406 May 28 01:47:31 PM PDT 24 May 28 01:47:34 PM PDT 24 497686613 ps
T331 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3781790683 May 28 01:47:09 PM PDT 24 May 28 01:47:12 PM PDT 24 543995951 ps
T332 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.171987479 May 28 01:47:30 PM PDT 24 May 28 01:47:32 PM PDT 24 301722847 ps
T333 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2780436649 May 28 01:46:45 PM PDT 24 May 28 01:46:48 PM PDT 24 411569029 ps
T84 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3117883729 May 28 01:47:28 PM PDT 24 May 28 01:47:35 PM PDT 24 1958810332 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2568740490 May 28 01:46:48 PM PDT 24 May 28 01:46:51 PM PDT 24 392049863 ps
T334 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1545312338 May 28 01:46:42 PM PDT 24 May 28 01:46:50 PM PDT 24 14541853154 ps
T335 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4113098048 May 28 01:47:11 PM PDT 24 May 28 01:47:16 PM PDT 24 2093295427 ps
T336 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1679924445 May 28 01:47:14 PM PDT 24 May 28 01:47:17 PM PDT 24 454279832 ps
T337 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2053531077 May 28 01:47:34 PM PDT 24 May 28 01:47:39 PM PDT 24 386073467 ps
T338 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1058931127 May 28 01:47:34 PM PDT 24 May 28 01:47:39 PM PDT 24 499916940 ps
T58 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.570722102 May 28 01:47:09 PM PDT 24 May 28 01:47:12 PM PDT 24 417857202 ps
T339 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.264150129 May 28 01:47:30 PM PDT 24 May 28 01:47:33 PM PDT 24 425528993 ps
T340 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1732490797 May 28 01:47:32 PM PDT 24 May 28 01:47:37 PM PDT 24 505097612 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.952263824 May 28 01:46:29 PM PDT 24 May 28 01:46:44 PM PDT 24 507343325 ps
T341 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4127875603 May 28 01:47:09 PM PDT 24 May 28 01:47:13 PM PDT 24 551008654 ps
T342 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2731966224 May 28 01:46:56 PM PDT 24 May 28 01:47:00 PM PDT 24 1202982100 ps
T343 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2643198280 May 28 01:46:30 PM PDT 24 May 28 01:46:45 PM PDT 24 1196063000 ps
T344 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.858184053 May 28 01:47:04 PM PDT 24 May 28 01:47:10 PM PDT 24 7016099060 ps
T345 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1037118923 May 28 01:47:32 PM PDT 24 May 28 01:47:37 PM PDT 24 2327284544 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.673386319 May 28 01:46:44 PM PDT 24 May 28 01:46:49 PM PDT 24 897570188 ps
T346 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3364096717 May 28 01:47:09 PM PDT 24 May 28 01:47:13 PM PDT 24 458039654 ps
T347 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2234452996 May 28 01:47:15 PM PDT 24 May 28 01:47:17 PM PDT 24 582762151 ps
T348 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.571817733 May 28 01:47:33 PM PDT 24 May 28 01:47:37 PM PDT 24 380239951 ps
T349 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3450813543 May 28 01:47:31 PM PDT 24 May 28 01:47:35 PM PDT 24 538004196 ps
T350 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1374654882 May 28 01:47:35 PM PDT 24 May 28 01:47:41 PM PDT 24 2862580851 ps
T351 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3052556237 May 28 01:47:15 PM PDT 24 May 28 01:47:18 PM PDT 24 338709242 ps
T75 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3918217476 May 28 01:47:28 PM PDT 24 May 28 01:47:30 PM PDT 24 351494589 ps
T352 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1814206255 May 28 01:47:33 PM PDT 24 May 28 01:47:38 PM PDT 24 380728851 ps
T353 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2192801630 May 28 01:46:56 PM PDT 24 May 28 01:47:00 PM PDT 24 405961607 ps
T71 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.199003918 May 28 01:46:41 PM PDT 24 May 28 01:46:46 PM PDT 24 463944670 ps
T354 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2494522464 May 28 01:47:34 PM PDT 24 May 28 01:47:38 PM PDT 24 392740336 ps
T355 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2432839314 May 28 01:46:57 PM PDT 24 May 28 01:47:00 PM PDT 24 467984006 ps
T356 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1094072852 May 28 01:46:41 PM PDT 24 May 28 01:46:46 PM PDT 24 375284284 ps
T357 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1717794787 May 28 01:46:30 PM PDT 24 May 28 01:46:44 PM PDT 24 406135176 ps
T358 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3280004266 May 28 01:47:33 PM PDT 24 May 28 01:47:37 PM PDT 24 347732778 ps
T359 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1246670787 May 28 01:47:30 PM PDT 24 May 28 01:47:33 PM PDT 24 540232694 ps
T360 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1644557187 May 28 01:47:14 PM PDT 24 May 28 01:47:18 PM PDT 24 2270225155 ps
T361 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.262227922 May 28 01:46:42 PM PDT 24 May 28 01:46:47 PM PDT 24 310026135 ps
T72 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.755280665 May 28 01:47:09 PM PDT 24 May 28 01:47:11 PM PDT 24 426476417 ps
T362 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3413899715 May 28 01:47:30 PM PDT 24 May 28 01:47:32 PM PDT 24 275749256 ps
T363 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.926051706 May 28 01:47:38 PM PDT 24 May 28 01:47:43 PM PDT 24 579996322 ps
T364 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2210406551 May 28 01:47:31 PM PDT 24 May 28 01:47:35 PM PDT 24 441627997 ps
T365 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2777530351 May 28 01:47:34 PM PDT 24 May 28 01:47:39 PM PDT 24 382263606 ps
T366 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2760355373 May 28 01:47:29 PM PDT 24 May 28 01:47:33 PM PDT 24 4531987763 ps
T367 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.760057596 May 28 01:47:33 PM PDT 24 May 28 01:47:38 PM PDT 24 643794688 ps
T368 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.948634672 May 28 01:47:34 PM PDT 24 May 28 01:47:40 PM PDT 24 1609257570 ps
T369 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2624654610 May 28 01:47:09 PM PDT 24 May 28 01:47:13 PM PDT 24 1309096983 ps
T370 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.821101038 May 28 01:47:05 PM PDT 24 May 28 01:47:10 PM PDT 24 4232649172 ps
T371 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4071563440 May 28 01:46:56 PM PDT 24 May 28 01:46:59 PM PDT 24 420645070 ps
T372 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2218924923 May 28 01:46:56 PM PDT 24 May 28 01:47:00 PM PDT 24 1310104377 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3262235367 May 28 01:46:31 PM PDT 24 May 28 01:46:57 PM PDT 24 8083924201 ps
T374 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1604793850 May 28 01:47:30 PM PDT 24 May 28 01:47:32 PM PDT 24 533522699 ps
T375 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.419215703 May 28 01:47:11 PM PDT 24 May 28 01:47:15 PM PDT 24 486644033 ps
T376 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1505076159 May 28 01:47:15 PM PDT 24 May 28 01:47:17 PM PDT 24 419931256 ps
T73 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3847146790 May 28 01:46:43 PM PDT 24 May 28 01:46:47 PM PDT 24 542505373 ps
T377 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3781247472 May 28 01:47:34 PM PDT 24 May 28 01:47:39 PM PDT 24 428461917 ps
T378 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3772945597 May 28 01:47:11 PM PDT 24 May 28 01:47:15 PM PDT 24 421517354 ps
T379 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1006655879 May 28 01:47:10 PM PDT 24 May 28 01:47:13 PM PDT 24 582174569 ps
T380 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3082610213 May 28 01:47:05 PM PDT 24 May 28 01:47:07 PM PDT 24 530546502 ps
T381 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2018694053 May 28 01:47:34 PM PDT 24 May 28 01:47:39 PM PDT 24 293948208 ps
T382 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2688651596 May 28 01:46:57 PM PDT 24 May 28 01:47:00 PM PDT 24 385782289 ps
T383 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1411522258 May 28 01:47:14 PM PDT 24 May 28 01:47:30 PM PDT 24 8878846347 ps
T384 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.28466898 May 28 01:47:15 PM PDT 24 May 28 01:47:17 PM PDT 24 295338568 ps
T385 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1208778617 May 28 01:47:36 PM PDT 24 May 28 01:47:41 PM PDT 24 295037328 ps
T386 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1551138751 May 28 01:47:12 PM PDT 24 May 28 01:47:22 PM PDT 24 8137718054 ps
T387 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3640934507 May 28 01:46:31 PM PDT 24 May 28 01:46:46 PM PDT 24 501511462 ps
T388 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1836272705 May 28 01:47:34 PM PDT 24 May 28 01:47:42 PM PDT 24 8554526470 ps
T389 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1901553627 May 28 01:47:32 PM PDT 24 May 28 01:47:36 PM PDT 24 401703614 ps
T204 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1108362012 May 28 01:47:28 PM PDT 24 May 28 01:47:42 PM PDT 24 8237734597 ps
T390 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.10889581 May 28 01:46:43 PM PDT 24 May 28 01:46:49 PM PDT 24 9382415506 ps
T391 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3947738464 May 28 01:46:56 PM PDT 24 May 28 01:46:59 PM PDT 24 488291334 ps
T392 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.656406646 May 28 01:47:03 PM PDT 24 May 28 01:47:05 PM PDT 24 534397630 ps
T393 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2907958218 May 28 01:46:42 PM PDT 24 May 28 01:46:47 PM PDT 24 552739670 ps
T394 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.265003301 May 28 01:47:04 PM PDT 24 May 28 01:47:06 PM PDT 24 531031337 ps
T395 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.166503775 May 28 01:47:10 PM PDT 24 May 28 01:47:14 PM PDT 24 1051368011 ps
T396 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3968662892 May 28 01:46:29 PM PDT 24 May 28 01:46:44 PM PDT 24 497671974 ps
T397 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2645608158 May 28 01:47:02 PM PDT 24 May 28 01:47:09 PM PDT 24 2416599212 ps
T398 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3231336174 May 28 01:46:42 PM PDT 24 May 28 01:46:47 PM PDT 24 313609595 ps
T399 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.332852563 May 28 01:46:42 PM PDT 24 May 28 01:46:47 PM PDT 24 833879714 ps
T400 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1616286375 May 28 01:47:30 PM PDT 24 May 28 01:47:33 PM PDT 24 519197762 ps
T401 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2160575208 May 28 01:47:32 PM PDT 24 May 28 01:47:36 PM PDT 24 455459094 ps
T402 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.117085099 May 28 01:47:12 PM PDT 24 May 28 01:47:15 PM PDT 24 339337572 ps
T403 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.110140833 May 28 01:47:31 PM PDT 24 May 28 01:47:47 PM PDT 24 8988978077 ps
T74 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2277388157 May 28 01:46:55 PM PDT 24 May 28 01:46:57 PM PDT 24 681929122 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2685851249 May 28 01:47:02 PM PDT 24 May 28 01:47:04 PM PDT 24 317123598 ps
T405 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3495804110 May 28 01:47:30 PM PDT 24 May 28 01:47:33 PM PDT 24 373013159 ps
T406 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3658440765 May 28 01:47:14 PM PDT 24 May 28 01:47:17 PM PDT 24 477836989 ps
T61 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1991123056 May 28 01:46:31 PM PDT 24 May 28 01:46:48 PM PDT 24 6419524458 ps
T407 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.614009794 May 28 01:47:09 PM PDT 24 May 28 01:47:11 PM PDT 24 585313954 ps
T408 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3878916716 May 28 01:47:19 PM PDT 24 May 28 01:47:27 PM PDT 24 4333789414 ps
T409 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3419374115 May 28 01:46:48 PM PDT 24 May 28 01:46:51 PM PDT 24 2397864691 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1823477286 May 28 01:47:08 PM PDT 24 May 28 01:47:12 PM PDT 24 4565318959 ps
T411 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2412616868 May 28 01:46:43 PM PDT 24 May 28 01:46:51 PM PDT 24 2462054249 ps
T412 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.308439814 May 28 01:46:55 PM PDT 24 May 28 01:46:58 PM PDT 24 278095873 ps
T413 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1037079520 May 28 01:47:19 PM PDT 24 May 28 01:47:22 PM PDT 24 484391925 ps
T414 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2053941079 May 28 01:47:03 PM PDT 24 May 28 01:47:05 PM PDT 24 825798993 ps
T415 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1238717009 May 28 01:47:29 PM PDT 24 May 28 01:47:32 PM PDT 24 434746465 ps
T416 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2068875398 May 28 01:46:58 PM PDT 24 May 28 01:47:01 PM PDT 24 270066671 ps
T202 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.269567546 May 28 01:46:56 PM PDT 24 May 28 01:47:03 PM PDT 24 7479915919 ps
T417 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2870082520 May 28 01:46:42 PM PDT 24 May 28 01:46:48 PM PDT 24 601828846 ps
T418 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1372533540 May 28 01:46:55 PM PDT 24 May 28 01:46:57 PM PDT 24 418498003 ps
T419 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2368859314 May 28 01:47:33 PM PDT 24 May 28 01:47:38 PM PDT 24 399791276 ps

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1092787176
Short name T8
Test name
Test status
Simulation time 84756793267 ps
CPU time 173.02 seconds
Started May 28 01:11:33 PM PDT 24
Finished May 28 01:14:34 PM PDT 24
Peak memory 207860 kb
Host smart-4b57ac94-af73-4589-a5fb-d8c39a113db1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092787176 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1092787176
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3091544824
Short name T11
Test name
Test status
Simulation time 161324642048 ps
CPU time 31.17 seconds
Started May 28 01:10:50 PM PDT 24
Finished May 28 01:11:24 PM PDT 24
Peak memory 192936 kb
Host smart-1440e651-03ad-4d4c-a5a7-5025b5c15535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091544824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3091544824
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.347804234
Short name T44
Test name
Test status
Simulation time 437225021034 ps
CPU time 449.11 seconds
Started May 28 01:11:22 PM PDT 24
Finished May 28 01:18:55 PM PDT 24
Peak memory 202908 kb
Host smart-ba9c27d4-3fdc-46ea-b98e-5bab20633f01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347804234 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.347804234
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.617977441
Short name T34
Test name
Test status
Simulation time 8288469199 ps
CPU time 4.13 seconds
Started May 28 01:46:55 PM PDT 24
Finished May 28 01:47:01 PM PDT 24
Peak memory 198096 kb
Host smart-657de74e-78f3-4431-85c5-74dc445aed09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617977441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.617977441
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3902434285
Short name T50
Test name
Test status
Simulation time 75430498594 ps
CPU time 486.91 seconds
Started May 28 01:10:57 PM PDT 24
Finished May 28 01:19:06 PM PDT 24
Peak memory 200456 kb
Host smart-4593e245-8795-4013-af74-5d3672617e67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902434285 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3902434285
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2202560538
Short name T39
Test name
Test status
Simulation time 267070514683 ps
CPU time 731.4 seconds
Started May 28 01:10:40 PM PDT 24
Finished May 28 01:22:55 PM PDT 24
Peak memory 207160 kb
Host smart-ab160adf-8260-4cb0-82b1-a78a3686f222
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202560538 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2202560538
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2673732945
Short name T90
Test name
Test status
Simulation time 132236115944 ps
CPU time 511.57 seconds
Started May 28 01:10:56 PM PDT 24
Finished May 28 01:19:29 PM PDT 24
Peak memory 211824 kb
Host smart-ce44e018-57e5-4e9e-8453-28f31cac986c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673732945 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2673732945
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.664751319
Short name T91
Test name
Test status
Simulation time 71366844907 ps
CPU time 535.14 seconds
Started May 28 01:10:53 PM PDT 24
Finished May 28 01:19:50 PM PDT 24
Peak memory 203360 kb
Host smart-58259bf3-cba3-486f-a440-edc5cc24813e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664751319 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.664751319
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.768714744
Short name T93
Test name
Test status
Simulation time 185721477268 ps
CPU time 218.1 seconds
Started May 28 01:11:32 PM PDT 24
Finished May 28 01:15:19 PM PDT 24
Peak memory 208428 kb
Host smart-acbfcb11-c8fa-4ff6-8021-c76d892a82b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768714744 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.768714744
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3079875435
Short name T92
Test name
Test status
Simulation time 765448757053 ps
CPU time 430.08 seconds
Started May 28 01:10:57 PM PDT 24
Finished May 28 01:18:10 PM PDT 24
Peak memory 202992 kb
Host smart-2569d9ef-814e-4640-8e50-0ace648455e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079875435 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3079875435
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.346710108
Short name T143
Test name
Test status
Simulation time 325588996724 ps
CPU time 335.26 seconds
Started May 28 01:10:59 PM PDT 24
Finished May 28 01:16:37 PM PDT 24
Peak memory 201992 kb
Host smart-9f4ade5c-e398-40c9-821d-a370363c7ad8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346710108 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.346710108
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3040898201
Short name T18
Test name
Test status
Simulation time 3718688422 ps
CPU time 3.57 seconds
Started May 28 01:10:41 PM PDT 24
Finished May 28 01:10:49 PM PDT 24
Peak memory 215252 kb
Host smart-f4cc37c7-54cf-4f23-8262-08e18fe020b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040898201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3040898201
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.821667119
Short name T135
Test name
Test status
Simulation time 42809074207 ps
CPU time 431.43 seconds
Started May 28 01:11:02 PM PDT 24
Finished May 28 01:18:17 PM PDT 24
Peak memory 200656 kb
Host smart-aadf9534-70b7-4c83-b1a2-abd4d3cff843
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821667119 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.821667119
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.768343033
Short name T123
Test name
Test status
Simulation time 54592393486 ps
CPU time 475.16 seconds
Started May 28 01:11:13 PM PDT 24
Finished May 28 01:19:10 PM PDT 24
Peak memory 213364 kb
Host smart-659880df-e706-4638-89c5-e96297ac51b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768343033 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.768343033
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1434604990
Short name T126
Test name
Test status
Simulation time 97877286535 ps
CPU time 1107.8 seconds
Started May 28 01:10:46 PM PDT 24
Finished May 28 01:29:18 PM PDT 24
Peak memory 211504 kb
Host smart-f5c83883-6cca-4052-9d8d-f71d289754af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434604990 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1434604990
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2523634190
Short name T132
Test name
Test status
Simulation time 174016602277 ps
CPU time 298.05 seconds
Started May 28 01:11:04 PM PDT 24
Finished May 28 01:16:05 PM PDT 24
Peak memory 209880 kb
Host smart-60fe1179-1076-479b-bcb5-04a08d4f2cfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523634190 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2523634190
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2418616061
Short name T115
Test name
Test status
Simulation time 230985950111 ps
CPU time 414.82 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:18:30 PM PDT 24
Peak memory 206844 kb
Host smart-9e87d807-d6ed-4206-bae7-3ed1a55066a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418616061 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2418616061
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.391676280
Short name T41
Test name
Test status
Simulation time 98842510155 ps
CPU time 749.54 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:24:01 PM PDT 24
Peak memory 206572 kb
Host smart-9113044d-7efe-4995-b61b-7cfb6e7709e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391676280 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.391676280
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.4012952165
Short name T120
Test name
Test status
Simulation time 32258463675 ps
CPU time 334.48 seconds
Started May 28 01:11:01 PM PDT 24
Finished May 28 01:16:39 PM PDT 24
Peak memory 206856 kb
Host smart-4a40b0f4-fdcf-408a-b7c1-b2526478ca43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012952165 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.4012952165
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3408684073
Short name T150
Test name
Test status
Simulation time 100698652896 ps
CPU time 163.99 seconds
Started May 28 01:11:22 PM PDT 24
Finished May 28 01:14:09 PM PDT 24
Peak memory 191888 kb
Host smart-11b92ec1-feac-4bda-9113-4b21238cc681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408684073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3408684073
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1100085002
Short name T107
Test name
Test status
Simulation time 145440287679 ps
CPU time 51.58 seconds
Started May 28 01:10:45 PM PDT 24
Finished May 28 01:11:41 PM PDT 24
Peak memory 192864 kb
Host smart-13fb4e17-76d2-4403-abbe-1bef3db468c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100085002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1100085002
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.4243427293
Short name T104
Test name
Test status
Simulation time 110484682020 ps
CPU time 44.94 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:12:24 PM PDT 24
Peak memory 191916 kb
Host smart-78ce7145-1f9b-4340-a2e6-52c329144df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243427293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.4243427293
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.253537500
Short name T87
Test name
Test status
Simulation time 61941090630 ps
CPU time 461.67 seconds
Started May 28 01:10:57 PM PDT 24
Finished May 28 01:18:41 PM PDT 24
Peak memory 201340 kb
Host smart-a381551d-54be-4232-b85d-29e7b038bc6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253537500 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.253537500
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3284588833
Short name T154
Test name
Test status
Simulation time 740768701645 ps
CPU time 174.6 seconds
Started May 28 01:11:09 PM PDT 24
Finished May 28 01:14:06 PM PDT 24
Peak memory 192576 kb
Host smart-f0cf771a-06cd-4d5b-9eab-e2c390a837e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284588833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3284588833
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.215120515
Short name T6
Test name
Test status
Simulation time 22706015877 ps
CPU time 224.21 seconds
Started May 28 01:11:01 PM PDT 24
Finished May 28 01:14:48 PM PDT 24
Peak memory 206848 kb
Host smart-6e14591c-ee74-453a-8683-144eb4ed245c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215120515 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.215120515
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3656295228
Short name T106
Test name
Test status
Simulation time 32021796060 ps
CPU time 46.49 seconds
Started May 28 01:10:58 PM PDT 24
Finished May 28 01:11:47 PM PDT 24
Peak memory 184600 kb
Host smart-d89cafed-0ae8-46a5-bc44-c5b09c17d58d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656295228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3656295228
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3360344718
Short name T113
Test name
Test status
Simulation time 61987293975 ps
CPU time 307.88 seconds
Started May 28 01:11:23 PM PDT 24
Finished May 28 01:16:35 PM PDT 24
Peak memory 208248 kb
Host smart-cae2eaaf-d61b-4a54-881b-3fbee11d34e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360344718 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3360344718
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2515255246
Short name T103
Test name
Test status
Simulation time 158750267673 ps
CPU time 62.84 seconds
Started May 28 01:11:01 PM PDT 24
Finished May 28 01:12:07 PM PDT 24
Peak memory 192732 kb
Host smart-f8043ba9-a2bf-4709-8cce-83b6b1a4404c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515255246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2515255246
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.255660902
Short name T163
Test name
Test status
Simulation time 78765684331 ps
CPU time 30.22 seconds
Started May 28 01:11:00 PM PDT 24
Finished May 28 01:11:33 PM PDT 24
Peak memory 192424 kb
Host smart-d778f2fe-7b74-478e-83d7-89b4ba106ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255660902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.255660902
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3207697968
Short name T116
Test name
Test status
Simulation time 305892429817 ps
CPU time 133.11 seconds
Started May 28 01:11:27 PM PDT 24
Finished May 28 01:13:50 PM PDT 24
Peak memory 183980 kb
Host smart-e6b3ee14-2486-4446-8907-aeb3400079aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207697968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3207697968
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3330824887
Short name T118
Test name
Test status
Simulation time 182824948802 ps
CPU time 143.78 seconds
Started May 28 01:11:04 PM PDT 24
Finished May 28 01:13:31 PM PDT 24
Peak memory 192564 kb
Host smart-7bcc1544-e43a-4e92-ad0d-d1139d78dd9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330824887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3330824887
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2514552713
Short name T129
Test name
Test status
Simulation time 215440910486 ps
CPU time 47.27 seconds
Started May 28 01:10:41 PM PDT 24
Finished May 28 01:11:32 PM PDT 24
Peak memory 192300 kb
Host smart-095aa970-4235-404a-a123-8f3ac97fb909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514552713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2514552713
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3780084598
Short name T152
Test name
Test status
Simulation time 56788436799 ps
CPU time 455.23 seconds
Started May 28 01:11:04 PM PDT 24
Finished May 28 01:18:43 PM PDT 24
Peak memory 201016 kb
Host smart-5e32e878-bd5b-416b-9719-db61253c7158
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780084598 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3780084598
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2076948796
Short name T108
Test name
Test status
Simulation time 279128653252 ps
CPU time 179.09 seconds
Started May 28 01:10:51 PM PDT 24
Finished May 28 01:13:54 PM PDT 24
Peak memory 192844 kb
Host smart-dd281be3-477a-4c95-bc3c-30356a5923ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076948796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2076948796
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2041333109
Short name T105
Test name
Test status
Simulation time 90521266058 ps
CPU time 55.28 seconds
Started May 28 01:11:03 PM PDT 24
Finished May 28 01:12:02 PM PDT 24
Peak memory 192508 kb
Host smart-13f5e946-df69-453b-a14e-944d791c162c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041333109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2041333109
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.248422745
Short name T40
Test name
Test status
Simulation time 310104282696 ps
CPU time 616.17 seconds
Started May 28 01:11:06 PM PDT 24
Finished May 28 01:21:25 PM PDT 24
Peak memory 205172 kb
Host smart-dd051140-dde9-4a8e-9838-178d39ac7d38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248422745 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.248422745
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2604604009
Short name T102
Test name
Test status
Simulation time 60845643005 ps
CPU time 26.24 seconds
Started May 28 01:11:23 PM PDT 24
Finished May 28 01:11:55 PM PDT 24
Peak memory 192852 kb
Host smart-637965ee-e872-4364-9122-ac87622c5e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604604009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2604604009
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2716908611
Short name T88
Test name
Test status
Simulation time 364703239246 ps
CPU time 390.29 seconds
Started May 28 01:10:47 PM PDT 24
Finished May 28 01:17:21 PM PDT 24
Peak memory 202224 kb
Host smart-b518b11e-68ed-4385-bb0c-d39844f424e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716908611 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2716908611
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.944439232
Short name T101
Test name
Test status
Simulation time 146441259820 ps
CPU time 197.4 seconds
Started May 28 01:10:51 PM PDT 24
Finished May 28 01:14:12 PM PDT 24
Peak memory 191832 kb
Host smart-b03ab880-8374-4dc9-814b-c9915c670e40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944439232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.944439232
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1104420097
Short name T124
Test name
Test status
Simulation time 41408065584 ps
CPU time 226.2 seconds
Started May 28 01:10:52 PM PDT 24
Finished May 28 01:14:42 PM PDT 24
Peak memory 198624 kb
Host smart-242aa355-5d8e-4f57-b92f-589576b26a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104420097 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1104420097
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.712732146
Short name T122
Test name
Test status
Simulation time 485487882561 ps
CPU time 629.25 seconds
Started May 28 01:11:01 PM PDT 24
Finished May 28 01:21:34 PM PDT 24
Peak memory 191860 kb
Host smart-af665c1d-7673-4912-a838-3083de3cc6a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712732146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.712732146
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2495374410
Short name T160
Test name
Test status
Simulation time 70101987470 ps
CPU time 57.23 seconds
Started May 28 01:11:06 PM PDT 24
Finished May 28 01:12:07 PM PDT 24
Peak memory 192480 kb
Host smart-d9a1d837-35b2-4dac-a633-46d29424caa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495374410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2495374410
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2294564853
Short name T86
Test name
Test status
Simulation time 116855754043 ps
CPU time 283.69 seconds
Started May 28 01:10:38 PM PDT 24
Finished May 28 01:15:26 PM PDT 24
Peak memory 198544 kb
Host smart-a1605aa6-bb27-4fa5-a3cd-a578101567cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294564853 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2294564853
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3406850900
Short name T114
Test name
Test status
Simulation time 159197353599 ps
CPU time 127.92 seconds
Started May 28 01:10:51 PM PDT 24
Finished May 28 01:13:02 PM PDT 24
Peak memory 192928 kb
Host smart-f6685fff-bdbd-4bc4-9339-ad2d856edaac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406850900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3406850900
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.90602721
Short name T85
Test name
Test status
Simulation time 193921730967 ps
CPU time 495.25 seconds
Started May 28 01:10:58 PM PDT 24
Finished May 28 01:19:15 PM PDT 24
Peak memory 212076 kb
Host smart-c1b19bfb-852f-4fbf-bfb7-7d7b625d00ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90602721 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.90602721
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2877122401
Short name T134
Test name
Test status
Simulation time 34207413983 ps
CPU time 24.29 seconds
Started May 28 01:11:22 PM PDT 24
Finished May 28 01:11:49 PM PDT 24
Peak memory 192864 kb
Host smart-4f811a35-8034-4f58-a9b9-db64b4fce05d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877122401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2877122401
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1558978861
Short name T148
Test name
Test status
Simulation time 41378544757 ps
CPU time 235.79 seconds
Started May 28 01:10:37 PM PDT 24
Finished May 28 01:14:36 PM PDT 24
Peak memory 206832 kb
Host smart-86d71588-e72d-410c-b61f-d00defc6ce07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558978861 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1558978861
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1160946736
Short name T131
Test name
Test status
Simulation time 28985251877 ps
CPU time 24.54 seconds
Started May 28 01:11:06 PM PDT 24
Finished May 28 01:11:34 PM PDT 24
Peak memory 192484 kb
Host smart-a35ac83d-e615-4e32-a3ed-e67cc91b20bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160946736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1160946736
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3064021184
Short name T119
Test name
Test status
Simulation time 160415224691 ps
CPU time 100.07 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:13:11 PM PDT 24
Peak memory 192640 kb
Host smart-e2d96cf3-e3c4-4c72-9700-4feea2f885ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064021184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3064021184
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2874539312
Short name T137
Test name
Test status
Simulation time 106289160460 ps
CPU time 43.32 seconds
Started May 28 01:11:08 PM PDT 24
Finished May 28 01:11:54 PM PDT 24
Peak memory 191828 kb
Host smart-92e8f3a5-3850-4d52-95fe-0460747dae3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874539312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2874539312
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.932437708
Short name T144
Test name
Test status
Simulation time 154943167455 ps
CPU time 217.6 seconds
Started May 28 01:11:06 PM PDT 24
Finished May 28 01:14:47 PM PDT 24
Peak memory 200460 kb
Host smart-6e104e1e-a11b-47e3-afdf-ca882816dfcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932437708 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.932437708
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1874948233
Short name T169
Test name
Test status
Simulation time 352503397430 ps
CPU time 510.25 seconds
Started May 28 01:11:04 PM PDT 24
Finished May 28 01:19:37 PM PDT 24
Peak memory 192564 kb
Host smart-2bc75666-4db9-4707-8a04-38278f81756e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874948233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1874948233
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.470391173
Short name T43
Test name
Test status
Simulation time 135557140190 ps
CPU time 803.23 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:24:54 PM PDT 24
Peak memory 209116 kb
Host smart-22b60499-3cf2-44ae-949a-a1fd9c9aae74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470391173 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.470391173
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3847146790
Short name T73
Test name
Test status
Simulation time 542505373 ps
CPU time 0.7 seconds
Started May 28 01:46:43 PM PDT 24
Finished May 28 01:46:47 PM PDT 24
Peak memory 193068 kb
Host smart-64b1dbb6-bc07-48ea-a886-336da9ac8239
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847146790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3847146790
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1563823742
Short name T77
Test name
Test status
Simulation time 2105592132 ps
CPU time 4.94 seconds
Started May 28 01:46:43 PM PDT 24
Finished May 28 01:46:52 PM PDT 24
Peak memory 194264 kb
Host smart-3553ee70-11fc-438c-af77-ed45fd7ff8ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563823742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1563823742
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.927276750
Short name T67
Test name
Test status
Simulation time 133270260934 ps
CPU time 16.34 seconds
Started May 28 01:10:44 PM PDT 24
Finished May 28 01:11:04 PM PDT 24
Peak memory 191912 kb
Host smart-c2cb097b-e8b2-4ac5-a3c3-92bed64e3750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927276750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.927276750
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3147744013
Short name T21
Test name
Test status
Simulation time 92838366753 ps
CPU time 70.52 seconds
Started May 28 01:10:52 PM PDT 24
Finished May 28 01:12:06 PM PDT 24
Peak memory 192304 kb
Host smart-f2329fe5-77ce-4ae5-8c5d-027eef48eabc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147744013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3147744013
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.631935081
Short name T25
Test name
Test status
Simulation time 156347132957 ps
CPU time 30.22 seconds
Started May 28 01:10:58 PM PDT 24
Finished May 28 01:11:31 PM PDT 24
Peak memory 184008 kb
Host smart-091f389d-aba8-4899-9353-2e5232d46409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631935081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.631935081
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2823350792
Short name T142
Test name
Test status
Simulation time 196849807504 ps
CPU time 181.58 seconds
Started May 28 01:11:03 PM PDT 24
Finished May 28 01:14:08 PM PDT 24
Peak memory 192748 kb
Host smart-0952dfee-5a2b-47f3-9a89-543a6e5bf00d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823350792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2823350792
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1678195439
Short name T170
Test name
Test status
Simulation time 57913747312 ps
CPU time 25.93 seconds
Started May 28 01:11:25 PM PDT 24
Finished May 28 01:11:59 PM PDT 24
Peak memory 191824 kb
Host smart-8055cb59-00f8-4de8-8920-710259a0f017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678195439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1678195439
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.4248567541
Short name T45
Test name
Test status
Simulation time 257120227061 ps
CPU time 690.66 seconds
Started May 28 01:11:23 PM PDT 24
Finished May 28 01:22:59 PM PDT 24
Peak memory 214536 kb
Host smart-a10161b4-e877-4822-9c52-5c6364c9f1b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248567541 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.4248567541
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.4198302343
Short name T7
Test name
Test status
Simulation time 237517547960 ps
CPU time 1230.73 seconds
Started May 28 01:11:03 PM PDT 24
Finished May 28 01:31:37 PM PDT 24
Peak memory 215036 kb
Host smart-41d2edba-6b44-466c-9573-c95f6f049c45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198302343 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.4198302343
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2179774994
Short name T147
Test name
Test status
Simulation time 184479953157 ps
CPU time 251.34 seconds
Started May 28 01:11:00 PM PDT 24
Finished May 28 01:15:14 PM PDT 24
Peak memory 191844 kb
Host smart-c345d938-2b70-4a56-834d-70bf79bd55c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179774994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2179774994
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2875548266
Short name T162
Test name
Test status
Simulation time 25518822671 ps
CPU time 195.29 seconds
Started May 28 01:11:07 PM PDT 24
Finished May 28 01:14:25 PM PDT 24
Peak memory 206768 kb
Host smart-0e34fa0e-1bc5-43e0-8f44-c245d3dba872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875548266 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2875548266
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2073995047
Short name T5
Test name
Test status
Simulation time 331797731919 ps
CPU time 513.63 seconds
Started May 28 01:11:04 PM PDT 24
Finished May 28 01:19:41 PM PDT 24
Peak memory 184528 kb
Host smart-da225003-1eed-4925-a194-0c352b1b992f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073995047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2073995047
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2344301262
Short name T133
Test name
Test status
Simulation time 378746517107 ps
CPU time 603.19 seconds
Started May 28 01:10:58 PM PDT 24
Finished May 28 01:21:03 PM PDT 24
Peak memory 191852 kb
Host smart-dfabed37-4f3f-4b6a-9e01-111497624a6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344301262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2344301262
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.661650900
Short name T89
Test name
Test status
Simulation time 223604261614 ps
CPU time 428.41 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:18:44 PM PDT 24
Peak memory 202816 kb
Host smart-68c6856f-c78a-439d-a142-12c61687de00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661650900 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.661650900
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.905626445
Short name T156
Test name
Test status
Simulation time 522188796 ps
CPU time 0.83 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:32 PM PDT 24
Peak memory 196376 kb
Host smart-e432ebe4-d27b-4ebc-aedd-2e951e4add44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905626445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.905626445
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2750005873
Short name T166
Test name
Test status
Simulation time 128434896560 ps
CPU time 109.16 seconds
Started May 28 01:11:27 PM PDT 24
Finished May 28 01:13:26 PM PDT 24
Peak memory 191920 kb
Host smart-95aa95db-8f9f-4d27-8991-81e040576721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750005873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2750005873
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2372505925
Short name T121
Test name
Test status
Simulation time 17621634200 ps
CPU time 184.98 seconds
Started May 28 01:10:45 PM PDT 24
Finished May 28 01:13:54 PM PDT 24
Peak memory 206880 kb
Host smart-1323304f-d3f8-4875-9476-3e40623d8efd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372505925 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2372505925
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3396346435
Short name T26
Test name
Test status
Simulation time 582571359 ps
CPU time 0.85 seconds
Started May 28 01:10:41 PM PDT 24
Finished May 28 01:10:46 PM PDT 24
Peak memory 196392 kb
Host smart-38b5bf08-c963-4d32-8c2d-e415f8ecbeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396346435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3396346435
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.89656166
Short name T149
Test name
Test status
Simulation time 398124313989 ps
CPU time 138.39 seconds
Started May 28 01:10:52 PM PDT 24
Finished May 28 01:13:13 PM PDT 24
Peak memory 192328 kb
Host smart-bc6bae63-c9a0-4a62-ba49-104f762ecb70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89656166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_al
l.89656166
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2331828972
Short name T125
Test name
Test status
Simulation time 344175961243 ps
CPU time 61.94 seconds
Started May 28 01:10:48 PM PDT 24
Finished May 28 01:11:53 PM PDT 24
Peak memory 191828 kb
Host smart-99e481a0-b842-4ac9-ad4f-142df993c9ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331828972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2331828972
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.895657985
Short name T153
Test name
Test status
Simulation time 544112773 ps
CPU time 0.68 seconds
Started May 28 01:10:45 PM PDT 24
Finished May 28 01:10:50 PM PDT 24
Peak memory 196436 kb
Host smart-a5c6675f-4df6-4073-9d88-a8fc43714205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895657985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.895657985
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1512992298
Short name T24
Test name
Test status
Simulation time 580309068 ps
CPU time 0.74 seconds
Started May 28 01:11:07 PM PDT 24
Finished May 28 01:11:10 PM PDT 24
Peak memory 196356 kb
Host smart-2800dc33-0886-42e7-b83d-9611fdf3581e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512992298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1512992298
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1706967865
Short name T146
Test name
Test status
Simulation time 509023581 ps
CPU time 0.66 seconds
Started May 28 01:11:01 PM PDT 24
Finished May 28 01:11:05 PM PDT 24
Peak memory 196344 kb
Host smart-41e5d8dd-4070-4def-9d90-3522b2bdf6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706967865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1706967865
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.4252907069
Short name T128
Test name
Test status
Simulation time 375969889815 ps
CPU time 152.8 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:14:08 PM PDT 24
Peak memory 191912 kb
Host smart-6700347a-81f1-4089-8fe4-7439f329e197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252907069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.4252907069
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1357471766
Short name T167
Test name
Test status
Simulation time 12594115628 ps
CPU time 128.69 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:13:49 PM PDT 24
Peak memory 214824 kb
Host smart-cbbbec8c-2357-4465-abd6-47ad89365fc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357471766 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1357471766
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3227749753
Short name T136
Test name
Test status
Simulation time 336727540 ps
CPU time 1.17 seconds
Started May 28 01:10:51 PM PDT 24
Finished May 28 01:10:55 PM PDT 24
Peak memory 196420 kb
Host smart-c40c89b4-47a9-4c98-a386-5a9ab20629de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227749753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3227749753
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.454720181
Short name T140
Test name
Test status
Simulation time 491871963 ps
CPU time 1.1 seconds
Started May 28 01:10:42 PM PDT 24
Finished May 28 01:10:47 PM PDT 24
Peak memory 196356 kb
Host smart-c4c2bc65-97a6-454f-a378-016e53fdd23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454720181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.454720181
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1938864118
Short name T99
Test name
Test status
Simulation time 417790120 ps
CPU time 1 seconds
Started May 28 01:11:06 PM PDT 24
Finished May 28 01:11:10 PM PDT 24
Peak memory 196348 kb
Host smart-40a6a5a4-8887-4d1d-858d-8434473c3e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938864118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1938864118
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2275170096
Short name T111
Test name
Test status
Simulation time 109293279592 ps
CPU time 39.32 seconds
Started May 28 01:10:30 PM PDT 24
Finished May 28 01:11:12 PM PDT 24
Peak memory 192316 kb
Host smart-f34fc51e-4c6d-44f1-bdfe-caf0c6da01c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275170096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2275170096
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2621321627
Short name T164
Test name
Test status
Simulation time 532075916 ps
CPU time 1.41 seconds
Started May 28 01:11:06 PM PDT 24
Finished May 28 01:11:10 PM PDT 24
Peak memory 196556 kb
Host smart-060adbd0-2d34-4e89-b1a4-75ee575d70b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621321627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2621321627
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.128276060
Short name T110
Test name
Test status
Simulation time 456298759 ps
CPU time 0.82 seconds
Started May 28 01:11:00 PM PDT 24
Finished May 28 01:11:04 PM PDT 24
Peak memory 196252 kb
Host smart-54819bcd-3dbb-4797-8a6e-b6d22bd3d215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128276060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.128276060
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.325097525
Short name T68
Test name
Test status
Simulation time 12589844423 ps
CPU time 86.03 seconds
Started May 28 01:11:05 PM PDT 24
Finished May 28 01:12:34 PM PDT 24
Peak memory 206808 kb
Host smart-87eaf2c9-0606-4757-bd23-d4c4bacbdba2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325097525 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.325097525
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2537153304
Short name T63
Test name
Test status
Simulation time 535276061 ps
CPU time 0.97 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:11:36 PM PDT 24
Peak memory 196436 kb
Host smart-3635bf2b-fedc-4ea1-8bee-6efb5d73bd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537153304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2537153304
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3145197208
Short name T158
Test name
Test status
Simulation time 506124887 ps
CPU time 0.84 seconds
Started May 28 01:10:43 PM PDT 24
Finished May 28 01:10:47 PM PDT 24
Peak memory 196436 kb
Host smart-bf8af612-b69b-4e9f-8960-e28fc15bed34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145197208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3145197208
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3167333213
Short name T16
Test name
Test status
Simulation time 65488931641 ps
CPU time 40.72 seconds
Started May 28 01:10:46 PM PDT 24
Finished May 28 01:11:31 PM PDT 24
Peak memory 191924 kb
Host smart-8669bb07-7370-4c85-9f1a-10c955b03531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167333213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3167333213
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3983973377
Short name T186
Test name
Test status
Simulation time 226860113126 ps
CPU time 109.4 seconds
Started May 28 01:10:48 PM PDT 24
Finished May 28 01:12:41 PM PDT 24
Peak memory 192632 kb
Host smart-9682477a-5a40-48c9-9a43-d57bc319617e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983973377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3983973377
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2576202855
Short name T117
Test name
Test status
Simulation time 383021180 ps
CPU time 0.92 seconds
Started May 28 01:10:49 PM PDT 24
Finished May 28 01:10:53 PM PDT 24
Peak memory 196360 kb
Host smart-8f761a55-9d34-400c-91a5-453cf7861efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576202855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2576202855
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2382646488
Short name T32
Test name
Test status
Simulation time 490760392 ps
CPU time 1.35 seconds
Started May 28 01:10:46 PM PDT 24
Finished May 28 01:10:51 PM PDT 24
Peak memory 196448 kb
Host smart-46655c56-2607-45c9-96f0-dc9f7dd86fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382646488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2382646488
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.4122543111
Short name T141
Test name
Test status
Simulation time 387682021 ps
CPU time 0.78 seconds
Started May 28 01:11:25 PM PDT 24
Finished May 28 01:11:34 PM PDT 24
Peak memory 196348 kb
Host smart-2976f62d-d06e-447f-8c72-8d49fac425ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122543111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.4122543111
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3689831852
Short name T179
Test name
Test status
Simulation time 206072879955 ps
CPU time 71.32 seconds
Started May 28 01:10:45 PM PDT 24
Finished May 28 01:12:00 PM PDT 24
Peak memory 191916 kb
Host smart-de34c958-d91b-4c02-b6f4-6e4ae48b710f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689831852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3689831852
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1701219220
Short name T127
Test name
Test status
Simulation time 511023470 ps
CPU time 0.78 seconds
Started May 28 01:10:57 PM PDT 24
Finished May 28 01:11:00 PM PDT 24
Peak memory 196288 kb
Host smart-b723aef0-26de-41a5-a79e-28d7350e505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701219220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1701219220
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2677014350
Short name T109
Test name
Test status
Simulation time 502845516 ps
CPU time 0.67 seconds
Started May 28 01:11:04 PM PDT 24
Finished May 28 01:11:08 PM PDT 24
Peak memory 196448 kb
Host smart-1baf5904-cf17-4c96-8f06-c92506a32e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677014350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2677014350
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1381601844
Short name T161
Test name
Test status
Simulation time 358947066 ps
CPU time 1.13 seconds
Started May 28 01:11:00 PM PDT 24
Finished May 28 01:11:04 PM PDT 24
Peak memory 196340 kb
Host smart-4c7f869b-b747-468e-8511-d9273d3792b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381601844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1381601844
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2571019963
Short name T165
Test name
Test status
Simulation time 546461169 ps
CPU time 0.88 seconds
Started May 28 01:11:05 PM PDT 24
Finished May 28 01:11:09 PM PDT 24
Peak memory 196436 kb
Host smart-5772c8ec-9bf2-4665-8f78-c1864dc70a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571019963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2571019963
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.308612036
Short name T168
Test name
Test status
Simulation time 36124023354 ps
CPU time 106.54 seconds
Started May 28 01:10:45 PM PDT 24
Finished May 28 01:12:35 PM PDT 24
Peak memory 214752 kb
Host smart-e2aba781-a1f6-4241-bb74-b685bc2d9ac4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308612036 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.308612036
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.4154724934
Short name T12
Test name
Test status
Simulation time 361353677 ps
CPU time 1.1 seconds
Started May 28 01:11:07 PM PDT 24
Finished May 28 01:11:11 PM PDT 24
Peak memory 196500 kb
Host smart-8d65aba8-ea6d-4bf1-b4ac-05f152ec671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154724934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.4154724934
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2419386679
Short name T184
Test name
Test status
Simulation time 41967256344 ps
CPU time 483.87 seconds
Started May 28 01:11:02 PM PDT 24
Finished May 28 01:19:10 PM PDT 24
Peak memory 209216 kb
Host smart-7a5addbd-f22a-4544-a898-07242a37d807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419386679 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2419386679
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3015041602
Short name T139
Test name
Test status
Simulation time 251599041128 ps
CPU time 419.13 seconds
Started May 28 01:10:39 PM PDT 24
Finished May 28 01:17:42 PM PDT 24
Peak memory 192420 kb
Host smart-5d1db076-c487-4023-a30a-a19c6ed59c61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015041602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3015041602
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.990535867
Short name T112
Test name
Test status
Simulation time 432469188 ps
CPU time 1.16 seconds
Started May 28 01:11:04 PM PDT 24
Finished May 28 01:11:09 PM PDT 24
Peak memory 196432 kb
Host smart-b106b5f0-9bed-46df-82f0-83abf26ff77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990535867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.990535867
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3945358093
Short name T155
Test name
Test status
Simulation time 195532552792 ps
CPU time 26.52 seconds
Started May 28 01:11:07 PM PDT 24
Finished May 28 01:11:36 PM PDT 24
Peak memory 191916 kb
Host smart-4eed36ed-8f8d-4906-8c1c-eba6b7fffbf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945358093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3945358093
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1979135710
Short name T157
Test name
Test status
Simulation time 354286526 ps
CPU time 1 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:30 PM PDT 24
Peak memory 196312 kb
Host smart-37d38a33-1dce-464b-a167-a55023dd2524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979135710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1979135710
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.37918241
Short name T151
Test name
Test status
Simulation time 146035817152 ps
CPU time 223.35 seconds
Started May 28 01:10:45 PM PDT 24
Finished May 28 01:14:32 PM PDT 24
Peak memory 191760 kb
Host smart-dd94a535-6004-4ccf-b212-cf5cd03087cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37918241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all
.37918241
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.73512144
Short name T145
Test name
Test status
Simulation time 681639147 ps
CPU time 0.67 seconds
Started May 28 01:10:43 PM PDT 24
Finished May 28 01:10:48 PM PDT 24
Peak memory 196368 kb
Host smart-888eeb8d-5f4e-4e40-9837-d98075b63d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73512144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.73512144
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2403376648
Short name T178
Test name
Test status
Simulation time 363027362 ps
CPU time 0.71 seconds
Started May 28 01:10:51 PM PDT 24
Finished May 28 01:10:55 PM PDT 24
Peak memory 196400 kb
Host smart-2b6c86de-f657-4ef6-a49d-c2be6adae095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403376648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2403376648
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.770288473
Short name T182
Test name
Test status
Simulation time 299979188877 ps
CPU time 376.01 seconds
Started May 28 01:11:02 PM PDT 24
Finished May 28 01:17:22 PM PDT 24
Peak memory 192020 kb
Host smart-2a376b9d-15e5-4f3f-a1e2-d08915b7a0a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770288473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.770288473
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2377274763
Short name T42
Test name
Test status
Simulation time 37387231075 ps
CPU time 396.37 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:18:07 PM PDT 24
Peak memory 207912 kb
Host smart-0cd0bef3-d130-4154-b868-897348335c49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377274763 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2377274763
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.523510136
Short name T159
Test name
Test status
Simulation time 39077333098 ps
CPU time 35.24 seconds
Started May 28 01:10:35 PM PDT 24
Finished May 28 01:11:13 PM PDT 24
Peak memory 206748 kb
Host smart-43d1248a-5f32-4485-8ebe-36c9cad3f239
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523510136 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.523510136
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3291467293
Short name T3
Test name
Test status
Simulation time 599943568 ps
CPU time 0.78 seconds
Started May 28 01:10:47 PM PDT 24
Finished May 28 01:10:52 PM PDT 24
Peak memory 196432 kb
Host smart-dc673be0-c404-4bd8-ba7b-45afd1090034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291467293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3291467293
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.522330725
Short name T188
Test name
Test status
Simulation time 368962298 ps
CPU time 1.11 seconds
Started May 28 01:10:57 PM PDT 24
Finished May 28 01:11:01 PM PDT 24
Peak memory 196308 kb
Host smart-3b4a5088-9f2a-41eb-8f91-9279e2db0b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522330725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.522330725
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1738811209
Short name T48
Test name
Test status
Simulation time 475651930 ps
CPU time 1.34 seconds
Started May 28 01:10:54 PM PDT 24
Finished May 28 01:10:57 PM PDT 24
Peak memory 196276 kb
Host smart-f3e5f704-7912-4e43-bcdc-3b334e7762cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738811209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1738811209
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2310613285
Short name T69
Test name
Test status
Simulation time 148744119317 ps
CPU time 289.52 seconds
Started May 28 01:10:47 PM PDT 24
Finished May 28 01:15:41 PM PDT 24
Peak memory 201424 kb
Host smart-1ec81291-3cb3-439d-943c-a3efcceec788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310613285 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2310613285
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1353506524
Short name T192
Test name
Test status
Simulation time 481932300 ps
CPU time 0.74 seconds
Started May 28 01:10:34 PM PDT 24
Finished May 28 01:10:37 PM PDT 24
Peak memory 196412 kb
Host smart-f68a6ad2-7f23-4cf4-a7fe-a446a98d8907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353506524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1353506524
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.727982734
Short name T173
Test name
Test status
Simulation time 561382979 ps
CPU time 0.79 seconds
Started May 28 01:11:01 PM PDT 24
Finished May 28 01:11:05 PM PDT 24
Peak memory 196324 kb
Host smart-368eadcb-d70b-417b-aad9-8f996f37f4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727982734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.727982734
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.888805765
Short name T181
Test name
Test status
Simulation time 98319249101 ps
CPU time 39.89 seconds
Started May 28 01:10:57 PM PDT 24
Finished May 28 01:11:40 PM PDT 24
Peak memory 191836 kb
Host smart-5649171f-a5b3-47a0-b679-2309f7c4ec4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888805765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.888805765
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2638260068
Short name T138
Test name
Test status
Simulation time 419968576 ps
CPU time 0.75 seconds
Started May 28 01:11:05 PM PDT 24
Finished May 28 01:11:09 PM PDT 24
Peak memory 196352 kb
Host smart-803846c7-747e-4e4c-8fa9-945a2b0a1f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638260068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2638260068
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1956473929
Short name T130
Test name
Test status
Simulation time 38811437546 ps
CPU time 149.75 seconds
Started May 28 01:11:04 PM PDT 24
Finished May 28 01:13:37 PM PDT 24
Peak memory 206848 kb
Host smart-5fe2a5b8-5e7d-4ad7-9706-db5de6f7cfc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956473929 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1956473929
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2462357119
Short name T198
Test name
Test status
Simulation time 598208460 ps
CPU time 0.79 seconds
Started May 28 01:10:39 PM PDT 24
Finished May 28 01:10:44 PM PDT 24
Peak memory 196364 kb
Host smart-a0cda1f2-71d8-4eee-be8a-adedeb730067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462357119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2462357119
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.750823986
Short name T176
Test name
Test status
Simulation time 540823006 ps
CPU time 0.65 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:31 PM PDT 24
Peak memory 196364 kb
Host smart-572fe485-4922-41a4-8810-404f8e7d2673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750823986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.750823986
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3617543643
Short name T191
Test name
Test status
Simulation time 590796717 ps
CPU time 0.75 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:32 PM PDT 24
Peak memory 196184 kb
Host smart-163f7be4-b4bd-4c04-a443-85bcda0c1da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617543643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3617543643
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2647824237
Short name T177
Test name
Test status
Simulation time 416179881 ps
CPU time 0.78 seconds
Started May 28 01:11:23 PM PDT 24
Finished May 28 01:11:30 PM PDT 24
Peak memory 196664 kb
Host smart-ddceb1ae-e477-4e6a-8dd9-39d94218df04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647824237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2647824237
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3586458325
Short name T194
Test name
Test status
Simulation time 489720144 ps
CPU time 1 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:11:36 PM PDT 24
Peak memory 196416 kb
Host smart-72525d36-8d8e-498d-8a5b-2784cae6dc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586458325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3586458325
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.353975370
Short name T9
Test name
Test status
Simulation time 542147711 ps
CPU time 1.35 seconds
Started May 28 01:10:46 PM PDT 24
Finished May 28 01:10:51 PM PDT 24
Peak memory 196264 kb
Host smart-3f0a2135-24e7-4213-9a4a-4ba64b0e80df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353975370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.353975370
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1108362012
Short name T204
Test name
Test status
Simulation time 8237734597 ps
CPU time 12.68 seconds
Started May 28 01:47:28 PM PDT 24
Finished May 28 01:47:42 PM PDT 24
Peak memory 198124 kb
Host smart-5d8612c8-5777-4dcf-858a-486d68e85a22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108362012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1108362012
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.269567546
Short name T202
Test name
Test status
Simulation time 7479915919 ps
CPU time 5.25 seconds
Started May 28 01:46:56 PM PDT 24
Finished May 28 01:47:03 PM PDT 24
Peak memory 198100 kb
Host smart-4c4d3c57-eb93-4b8b-9e5b-cd691285398a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269567546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.269567546
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.830573585
Short name T175
Test name
Test status
Simulation time 189376145282 ps
CPU time 302.34 seconds
Started May 28 01:10:46 PM PDT 24
Finished May 28 01:15:52 PM PDT 24
Peak memory 193032 kb
Host smart-38dde3d6-6089-4592-8e2e-ce17f90f3f21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830573585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.830573585
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3863204157
Short name T180
Test name
Test status
Simulation time 598645840 ps
CPU time 0.86 seconds
Started May 28 01:11:02 PM PDT 24
Finished May 28 01:11:06 PM PDT 24
Peak memory 196416 kb
Host smart-6741c338-8e77-4de8-bd77-c8f3aee4d4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863204157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3863204157
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1996499671
Short name T190
Test name
Test status
Simulation time 407901756 ps
CPU time 1.29 seconds
Started May 28 01:10:57 PM PDT 24
Finished May 28 01:11:01 PM PDT 24
Peak memory 196328 kb
Host smart-dd083d68-ca97-4026-ba35-26b60fafefa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996499671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1996499671
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3813102061
Short name T96
Test name
Test status
Simulation time 622494907 ps
CPU time 0.82 seconds
Started May 28 01:10:51 PM PDT 24
Finished May 28 01:10:55 PM PDT 24
Peak memory 196324 kb
Host smart-3bd26751-ecf9-4f83-83da-967d9cfdcac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813102061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3813102061
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.4067204793
Short name T172
Test name
Test status
Simulation time 617740852 ps
CPU time 1.17 seconds
Started May 28 01:11:00 PM PDT 24
Finished May 28 01:11:04 PM PDT 24
Peak memory 196676 kb
Host smart-cd36049a-8ec5-4f9a-81e7-80c8176770dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067204793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.4067204793
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3537780946
Short name T185
Test name
Test status
Simulation time 468402610 ps
CPU time 0.81 seconds
Started May 28 01:11:08 PM PDT 24
Finished May 28 01:11:11 PM PDT 24
Peak memory 196408 kb
Host smart-3787bf23-cf6b-49e4-be15-e3f07db3154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537780946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3537780946
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.702547097
Short name T187
Test name
Test status
Simulation time 574156583 ps
CPU time 1.07 seconds
Started May 28 01:11:27 PM PDT 24
Finished May 28 01:11:38 PM PDT 24
Peak memory 196412 kb
Host smart-77c7ca7b-1a8a-4795-9216-e9a31c1c4d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702547097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.702547097
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2495920114
Short name T196
Test name
Test status
Simulation time 414986413488 ps
CPU time 249.26 seconds
Started May 28 01:10:43 PM PDT 24
Finished May 28 01:14:57 PM PDT 24
Peak memory 191840 kb
Host smart-34213e81-bd2a-48f3-93ac-d19a62810a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495920114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2495920114
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2201290811
Short name T171
Test name
Test status
Simulation time 359092239926 ps
CPU time 139.9 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:13:55 PM PDT 24
Peak memory 191916 kb
Host smart-f2bb1f28-99b9-4157-ab08-c13ec6c5f802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201290811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2201290811
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.212236734
Short name T197
Test name
Test status
Simulation time 571117952 ps
CPU time 1 seconds
Started May 28 01:11:28 PM PDT 24
Finished May 28 01:11:39 PM PDT 24
Peak memory 196380 kb
Host smart-1a6a04b4-20ee-4451-b114-fafd90e331c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212236734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.212236734
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.41538088
Short name T195
Test name
Test status
Simulation time 436779311 ps
CPU time 0.97 seconds
Started May 28 01:10:53 PM PDT 24
Finished May 28 01:10:57 PM PDT 24
Peak memory 196396 kb
Host smart-42e64347-1de1-4d40-9f60-68daab1eccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41538088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.41538088
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1991123056
Short name T61
Test name
Test status
Simulation time 6419524458 ps
CPU time 4.37 seconds
Started May 28 01:46:31 PM PDT 24
Finished May 28 01:46:48 PM PDT 24
Peak memory 192304 kb
Host smart-d3587d7a-cca4-4686-b4ab-788f9a4acc97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991123056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1991123056
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2643198280
Short name T343
Test name
Test status
Simulation time 1196063000 ps
CPU time 1.56 seconds
Started May 28 01:46:30 PM PDT 24
Finished May 28 01:46:45 PM PDT 24
Peak memory 183748 kb
Host smart-f497be30-a38b-413d-bf77-9bf995fa7a46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643198280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2643198280
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2907958218
Short name T393
Test name
Test status
Simulation time 552739670 ps
CPU time 0.85 seconds
Started May 28 01:46:42 PM PDT 24
Finished May 28 01:46:47 PM PDT 24
Peak memory 195824 kb
Host smart-56bedbe9-2281-4f7d-9235-e405c833d69d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907958218 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2907958218
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.952263824
Short name T59
Test name
Test status
Simulation time 507343325 ps
CPU time 0.8 seconds
Started May 28 01:46:29 PM PDT 24
Finished May 28 01:46:44 PM PDT 24
Peak memory 193144 kb
Host smart-5a05dbb3-1498-4253-a972-704327fef8b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952263824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.952263824
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3968662892
Short name T396
Test name
Test status
Simulation time 497671974 ps
CPU time 1.28 seconds
Started May 28 01:46:29 PM PDT 24
Finished May 28 01:46:44 PM PDT 24
Peak memory 183592 kb
Host smart-3c0275b8-b78f-490f-89ed-c3464d0c269e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968662892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3968662892
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1717794787
Short name T357
Test name
Test status
Simulation time 406135176 ps
CPU time 0.64 seconds
Started May 28 01:46:30 PM PDT 24
Finished May 28 01:46:44 PM PDT 24
Peak memory 183572 kb
Host smart-c61a878a-236c-4ab3-bc71-a8ad1c57d0a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717794787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1717794787
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1577566274
Short name T306
Test name
Test status
Simulation time 396247217 ps
CPU time 0.58 seconds
Started May 28 01:46:28 PM PDT 24
Finished May 28 01:46:43 PM PDT 24
Peak memory 183644 kb
Host smart-2cd4db0b-955d-441d-bb78-0ed534d05d35
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577566274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1577566274
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3640934507
Short name T387
Test name
Test status
Simulation time 501511462 ps
CPU time 2.12 seconds
Started May 28 01:46:31 PM PDT 24
Finished May 28 01:46:46 PM PDT 24
Peak memory 198428 kb
Host smart-2464d852-477b-4e42-b907-d450fdae40a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640934507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3640934507
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3262235367
Short name T373
Test name
Test status
Simulation time 8083924201 ps
CPU time 13.41 seconds
Started May 28 01:46:31 PM PDT 24
Finished May 28 01:46:57 PM PDT 24
Peak memory 197976 kb
Host smart-90a36a02-14f1-49a3-b199-087d485e9386
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262235367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3262235367
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2870082520
Short name T417
Test name
Test status
Simulation time 601828846 ps
CPU time 1.54 seconds
Started May 28 01:46:42 PM PDT 24
Finished May 28 01:46:48 PM PDT 24
Peak memory 183688 kb
Host smart-058c9183-18a2-4295-b59a-41dbb40c3699
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870082520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2870082520
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.673386319
Short name T60
Test name
Test status
Simulation time 897570188 ps
CPU time 2.12 seconds
Started May 28 01:46:44 PM PDT 24
Finished May 28 01:46:49 PM PDT 24
Peak memory 195200 kb
Host smart-76d3d3f7-ea2d-471d-9dab-c25d904bb7cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673386319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.673386319
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.109909878
Short name T38
Test name
Test status
Simulation time 1412295243 ps
CPU time 1.09 seconds
Started May 28 01:46:45 PM PDT 24
Finished May 28 01:46:49 PM PDT 24
Peak memory 192876 kb
Host smart-9ecfd33e-cbd5-49b9-8b86-729e28f433e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109909878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.109909878
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.332852563
Short name T399
Test name
Test status
Simulation time 833879714 ps
CPU time 0.77 seconds
Started May 28 01:46:42 PM PDT 24
Finished May 28 01:46:47 PM PDT 24
Peak memory 197300 kb
Host smart-4d201492-951a-420c-b04c-080e49bc37b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332852563 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.332852563
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.192741851
Short name T55
Test name
Test status
Simulation time 515283104 ps
CPU time 0.73 seconds
Started May 28 01:46:45 PM PDT 24
Finished May 28 01:46:48 PM PDT 24
Peak memory 183532 kb
Host smart-9aae7d58-1828-4e20-a44d-aa9cade9e5b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192741851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.192741851
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1094943156
Short name T327
Test name
Test status
Simulation time 298460201 ps
CPU time 0.69 seconds
Started May 28 01:46:42 PM PDT 24
Finished May 28 01:46:47 PM PDT 24
Peak memory 183592 kb
Host smart-e9babfce-7288-4249-8f7b-576058c8263c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094943156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1094943156
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3201336225
Short name T289
Test name
Test status
Simulation time 489968618 ps
CPU time 1.25 seconds
Started May 28 01:46:43 PM PDT 24
Finished May 28 01:46:48 PM PDT 24
Peak memory 183512 kb
Host smart-de6de29a-f800-407d-a642-d3e123cc7c3a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201336225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3201336225
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3231336174
Short name T398
Test name
Test status
Simulation time 313609595 ps
CPU time 0.61 seconds
Started May 28 01:46:42 PM PDT 24
Finished May 28 01:46:47 PM PDT 24
Peak memory 183648 kb
Host smart-58c50a27-1fa8-4326-99c6-82eb149e4dc4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231336174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3231336174
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3419374115
Short name T409
Test name
Test status
Simulation time 2397864691 ps
CPU time 1.47 seconds
Started May 28 01:46:48 PM PDT 24
Finished May 28 01:46:51 PM PDT 24
Peak memory 183680 kb
Host smart-a9000d09-3d76-49b3-a5e5-677623816cf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419374115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3419374115
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.755108684
Short name T318
Test name
Test status
Simulation time 405768936 ps
CPU time 1.48 seconds
Started May 28 01:46:47 PM PDT 24
Finished May 28 01:46:50 PM PDT 24
Peak memory 198356 kb
Host smart-f31b1f77-8cbc-4aa3-9241-b0479a85e2cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755108684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.755108684
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.10889581
Short name T390
Test name
Test status
Simulation time 9382415506 ps
CPU time 1.91 seconds
Started May 28 01:46:43 PM PDT 24
Finished May 28 01:46:49 PM PDT 24
Peak memory 198044 kb
Host smart-90d1937b-f277-4f2c-b663-1d8a4042f510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10889581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_i
ntg_err.10889581
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4221099513
Short name T208
Test name
Test status
Simulation time 415528454 ps
CPU time 0.82 seconds
Started May 28 01:47:14 PM PDT 24
Finished May 28 01:47:17 PM PDT 24
Peak memory 195520 kb
Host smart-8069b97b-f217-48f0-bc60-a91657e4d313
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221099513 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.4221099513
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2234452996
Short name T347
Test name
Test status
Simulation time 582762151 ps
CPU time 0.77 seconds
Started May 28 01:47:15 PM PDT 24
Finished May 28 01:47:17 PM PDT 24
Peak memory 193000 kb
Host smart-0b9c8c91-bd14-4fd6-ae60-62bcafc283a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234452996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2234452996
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1662559599
Short name T312
Test name
Test status
Simulation time 403642775 ps
CPU time 1.13 seconds
Started May 28 01:47:19 PM PDT 24
Finished May 28 01:47:21 PM PDT 24
Peak memory 183552 kb
Host smart-5bb5b337-8a58-40dd-81f1-480fc5cd65f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662559599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1662559599
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2624654610
Short name T369
Test name
Test status
Simulation time 1309096983 ps
CPU time 1.44 seconds
Started May 28 01:47:09 PM PDT 24
Finished May 28 01:47:13 PM PDT 24
Peak memory 192888 kb
Host smart-f58a98a5-8df4-4a3d-8c62-2482426f0f05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624654610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2624654610
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.419215703
Short name T375
Test name
Test status
Simulation time 486644033 ps
CPU time 2.27 seconds
Started May 28 01:47:11 PM PDT 24
Finished May 28 01:47:15 PM PDT 24
Peak memory 198452 kb
Host smart-e56d0d1f-5b33-4de4-b52b-988c703095d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419215703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.419215703
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1551138751
Short name T386
Test name
Test status
Simulation time 8137718054 ps
CPU time 7.51 seconds
Started May 28 01:47:12 PM PDT 24
Finished May 28 01:47:22 PM PDT 24
Peak memory 198016 kb
Host smart-9d64f2bf-87d3-4090-9cfc-6874de5a430b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551138751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1551138751
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1006655879
Short name T379
Test name
Test status
Simulation time 582174569 ps
CPU time 0.84 seconds
Started May 28 01:47:10 PM PDT 24
Finished May 28 01:47:13 PM PDT 24
Peak memory 195424 kb
Host smart-ed7460b3-51f5-4879-b7ef-1b288e30c246
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006655879 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1006655879
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.570722102
Short name T58
Test name
Test status
Simulation time 417857202 ps
CPU time 1.25 seconds
Started May 28 01:47:09 PM PDT 24
Finished May 28 01:47:12 PM PDT 24
Peak memory 191992 kb
Host smart-9b9b0e66-12da-4f67-8198-2caaeadeec76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570722102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.570722102
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2401266548
Short name T283
Test name
Test status
Simulation time 405706289 ps
CPU time 1.16 seconds
Started May 28 01:47:15 PM PDT 24
Finished May 28 01:47:18 PM PDT 24
Peak memory 183648 kb
Host smart-1d172cd4-7dae-4fa2-b550-76eedfb3939d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401266548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2401266548
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4113098048
Short name T335
Test name
Test status
Simulation time 2093295427 ps
CPU time 3.29 seconds
Started May 28 01:47:11 PM PDT 24
Finished May 28 01:47:16 PM PDT 24
Peak memory 194352 kb
Host smart-a55c69d9-eabb-4b60-ad60-7148d6144f74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113098048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.4113098048
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3700247015
Short name T295
Test name
Test status
Simulation time 550568042 ps
CPU time 2.47 seconds
Started May 28 01:47:11 PM PDT 24
Finished May 28 01:47:15 PM PDT 24
Peak memory 198480 kb
Host smart-1d04bbfe-cb49-4bdd-b124-8ccda027327f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700247015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3700247015
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1823477286
Short name T410
Test name
Test status
Simulation time 4565318959 ps
CPU time 2.48 seconds
Started May 28 01:47:08 PM PDT 24
Finished May 28 01:47:12 PM PDT 24
Peak memory 197640 kb
Host smart-2ef87338-2c97-4e86-8613-397dc015d52c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823477286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1823477286
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3781790683
Short name T331
Test name
Test status
Simulation time 543995951 ps
CPU time 0.87 seconds
Started May 28 01:47:09 PM PDT 24
Finished May 28 01:47:12 PM PDT 24
Peak memory 196152 kb
Host smart-9e086206-79bd-41e5-bf5b-25808041ef4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781790683 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3781790683
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3171692828
Short name T297
Test name
Test status
Simulation time 475223382 ps
CPU time 1.06 seconds
Started May 28 01:47:08 PM PDT 24
Finished May 28 01:47:10 PM PDT 24
Peak memory 191992 kb
Host smart-583d1cca-29e7-4426-8452-d17c73743ca8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171692828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3171692828
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1679924445
Short name T336
Test name
Test status
Simulation time 454279832 ps
CPU time 0.86 seconds
Started May 28 01:47:14 PM PDT 24
Finished May 28 01:47:17 PM PDT 24
Peak memory 183648 kb
Host smart-04ee2a1c-152f-42cf-9a14-b0b6d744490f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679924445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1679924445
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.676858355
Short name T79
Test name
Test status
Simulation time 2259161582 ps
CPU time 7.68 seconds
Started May 28 01:47:10 PM PDT 24
Finished May 28 01:47:19 PM PDT 24
Peak memory 193048 kb
Host smart-b956cb0c-cab7-42f1-a805-dbb069a42be2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676858355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.676858355
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3772945597
Short name T378
Test name
Test status
Simulation time 421517354 ps
CPU time 1.72 seconds
Started May 28 01:47:11 PM PDT 24
Finished May 28 01:47:15 PM PDT 24
Peak memory 198504 kb
Host smart-9a43dba7-e6c6-4515-b17f-6902120bd14d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772945597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3772945597
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1411522258
Short name T383
Test name
Test status
Simulation time 8878846347 ps
CPU time 13.77 seconds
Started May 28 01:47:14 PM PDT 24
Finished May 28 01:47:30 PM PDT 24
Peak memory 197928 kb
Host smart-1291e1e5-8eee-446f-a53d-ae6617948c1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411522258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1411522258
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1235597657
Short name T321
Test name
Test status
Simulation time 539408648 ps
CPU time 0.87 seconds
Started May 28 01:47:10 PM PDT 24
Finished May 28 01:47:13 PM PDT 24
Peak memory 196848 kb
Host smart-06d9f763-782b-45d6-b440-43319eb3dce7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235597657 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1235597657
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.755280665
Short name T72
Test name
Test status
Simulation time 426476417 ps
CPU time 1.31 seconds
Started May 28 01:47:09 PM PDT 24
Finished May 28 01:47:11 PM PDT 24
Peak memory 193004 kb
Host smart-ef7efab8-2e44-41a0-b3cb-1fd164f41a6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755280665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.755280665
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.117085099
Short name T402
Test name
Test status
Simulation time 339337572 ps
CPU time 0.66 seconds
Started May 28 01:47:12 PM PDT 24
Finished May 28 01:47:15 PM PDT 24
Peak memory 183596 kb
Host smart-c1e8bb58-d2db-4a5b-a56c-2ea9bb857546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117085099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.117085099
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1644557187
Short name T360
Test name
Test status
Simulation time 2270225155 ps
CPU time 1.58 seconds
Started May 28 01:47:14 PM PDT 24
Finished May 28 01:47:18 PM PDT 24
Peak memory 183924 kb
Host smart-c067e344-3b4c-4454-b299-e5f3b8815211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644557187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1644557187
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1836695070
Short name T301
Test name
Test status
Simulation time 869956194 ps
CPU time 2.5 seconds
Started May 28 01:47:10 PM PDT 24
Finished May 28 01:47:15 PM PDT 24
Peak memory 198444 kb
Host smart-3f4e0c5d-ec6d-43f9-b71a-0d98c23ae703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836695070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1836695070
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3878916716
Short name T408
Test name
Test status
Simulation time 4333789414 ps
CPU time 6.74 seconds
Started May 28 01:47:19 PM PDT 24
Finished May 28 01:47:27 PM PDT 24
Peak memory 197036 kb
Host smart-f192452b-9ab7-4bfa-9b26-d805dd815750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878916716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3878916716
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.760057596
Short name T367
Test name
Test status
Simulation time 643794688 ps
CPU time 0.96 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:38 PM PDT 24
Peak memory 196236 kb
Host smart-6291a966-1d67-473c-8222-ea37637dd4ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760057596 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.760057596
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1616286375
Short name T400
Test name
Test status
Simulation time 519197762 ps
CPU time 1.4 seconds
Started May 28 01:47:30 PM PDT 24
Finished May 28 01:47:33 PM PDT 24
Peak memory 183728 kb
Host smart-68c9a8be-badf-4f46-9d9b-809530aba969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616286375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1616286375
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.154401231
Short name T293
Test name
Test status
Simulation time 386711510 ps
CPU time 1.08 seconds
Started May 28 01:47:28 PM PDT 24
Finished May 28 01:47:30 PM PDT 24
Peak memory 183648 kb
Host smart-2b8c39e4-f309-4537-9941-0497c926516f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154401231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.154401231
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.948634672
Short name T368
Test name
Test status
Simulation time 1609257570 ps
CPU time 2.07 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:40 PM PDT 24
Peak memory 192888 kb
Host smart-4895fca4-4e93-442c-a39a-52a60db74c78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948634672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.948634672
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1037079520
Short name T413
Test name
Test status
Simulation time 484391925 ps
CPU time 1.87 seconds
Started May 28 01:47:19 PM PDT 24
Finished May 28 01:47:22 PM PDT 24
Peak memory 197760 kb
Host smart-376b90ae-c0f6-4e63-b1ba-68e37dca788c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037079520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1037079520
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2247427984
Short name T33
Test name
Test status
Simulation time 416853422 ps
CPU time 1.26 seconds
Started May 28 01:47:38 PM PDT 24
Finished May 28 01:47:43 PM PDT 24
Peak memory 196284 kb
Host smart-f1dd3fcb-bed5-4739-a738-cff24d49735a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247427984 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2247427984
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3450813543
Short name T349
Test name
Test status
Simulation time 538004196 ps
CPU time 1.05 seconds
Started May 28 01:47:31 PM PDT 24
Finished May 28 01:47:35 PM PDT 24
Peak memory 193016 kb
Host smart-e8ea1593-ce41-4c5d-a3d5-1468f00f8658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450813543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3450813543
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2018694053
Short name T381
Test name
Test status
Simulation time 293948208 ps
CPU time 1.08 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:39 PM PDT 24
Peak memory 183644 kb
Host smart-186c15b3-0cf0-4fe9-ad39-b1fea7d29c8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018694053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2018694053
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3117883729
Short name T84
Test name
Test status
Simulation time 1958810332 ps
CPU time 6.96 seconds
Started May 28 01:47:28 PM PDT 24
Finished May 28 01:47:35 PM PDT 24
Peak memory 193900 kb
Host smart-092c44a8-3146-4d83-8239-8524a9c7d103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117883729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3117883729
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1246670787
Short name T359
Test name
Test status
Simulation time 540232694 ps
CPU time 1.46 seconds
Started May 28 01:47:30 PM PDT 24
Finished May 28 01:47:33 PM PDT 24
Peak memory 198444 kb
Host smart-ec6523d5-daab-4bef-80e9-53940a4ef5c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246670787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1246670787
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1222518557
Short name T37
Test name
Test status
Simulation time 8702909209 ps
CPU time 5.66 seconds
Started May 28 01:47:30 PM PDT 24
Finished May 28 01:47:38 PM PDT 24
Peak memory 198348 kb
Host smart-19008ea1-5878-4adf-9ad7-5dd7dec8a838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222518557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1222518557
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3514688227
Short name T317
Test name
Test status
Simulation time 392992662 ps
CPU time 1.21 seconds
Started May 28 01:47:32 PM PDT 24
Finished May 28 01:47:36 PM PDT 24
Peak memory 195436 kb
Host smart-0cf576f4-135d-4b2d-ba66-5a620bab384e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514688227 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3514688227
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.336389519
Short name T305
Test name
Test status
Simulation time 482122578 ps
CPU time 0.9 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:40 PM PDT 24
Peak memory 193148 kb
Host smart-e15d268e-ccf1-4ded-9ef3-36d1d3bc3950
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336389519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.336389519
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1208778617
Short name T385
Test name
Test status
Simulation time 295037328 ps
CPU time 0.71 seconds
Started May 28 01:47:36 PM PDT 24
Finished May 28 01:47:41 PM PDT 24
Peak memory 183648 kb
Host smart-c4b2e93a-c2b0-4148-a590-9dff65ccacda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208778617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1208778617
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3219602594
Short name T78
Test name
Test status
Simulation time 2495178164 ps
CPU time 3.28 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:39 PM PDT 24
Peak memory 193776 kb
Host smart-59ba2675-1aab-4f27-a8e9-c4e208866f0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219602594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3219602594
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2595788726
Short name T323
Test name
Test status
Simulation time 768064529 ps
CPU time 2.35 seconds
Started May 28 01:47:30 PM PDT 24
Finished May 28 01:47:34 PM PDT 24
Peak memory 198452 kb
Host smart-ee4f399e-14a9-45f6-b210-b11d9bded87d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595788726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2595788726
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.110140833
Short name T403
Test name
Test status
Simulation time 8988978077 ps
CPU time 14.06 seconds
Started May 28 01:47:31 PM PDT 24
Finished May 28 01:47:47 PM PDT 24
Peak memory 198024 kb
Host smart-1bd33147-6d09-4c65-8477-6a1030a34778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110140833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.110140833
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3495804110
Short name T405
Test name
Test status
Simulation time 373013159 ps
CPU time 0.91 seconds
Started May 28 01:47:30 PM PDT 24
Finished May 28 01:47:33 PM PDT 24
Peak memory 195392 kb
Host smart-60b5f34c-2bad-4089-98ee-131354f6baf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495804110 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3495804110
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4156297726
Short name T51
Test name
Test status
Simulation time 490926824 ps
CPU time 0.95 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:38 PM PDT 24
Peak memory 183804 kb
Host smart-c1c8af2e-bc92-466c-b108-32f8378653c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156297726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.4156297726
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3413899715
Short name T362
Test name
Test status
Simulation time 275749256 ps
CPU time 0.74 seconds
Started May 28 01:47:30 PM PDT 24
Finished May 28 01:47:32 PM PDT 24
Peak memory 183644 kb
Host smart-71a7f6a3-8910-4ac9-a057-1635065067d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413899715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3413899715
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3645638347
Short name T80
Test name
Test status
Simulation time 2774000709 ps
CPU time 6.14 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:44 PM PDT 24
Peak memory 194400 kb
Host smart-36815a42-b438-489b-a96f-b68626fb1e74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645638347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3645638347
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.926051706
Short name T363
Test name
Test status
Simulation time 579996322 ps
CPU time 1.54 seconds
Started May 28 01:47:38 PM PDT 24
Finished May 28 01:47:43 PM PDT 24
Peak memory 198440 kb
Host smart-167f6fb9-539f-4a70-93aa-c3a3b3b06015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926051706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.926051706
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2021184541
Short name T203
Test name
Test status
Simulation time 4067208169 ps
CPU time 3.92 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:42 PM PDT 24
Peak memory 196156 kb
Host smart-d43331e9-06ec-4082-9142-3233d1ddc129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021184541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2021184541
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3418900254
Short name T313
Test name
Test status
Simulation time 583215174 ps
CPU time 1.69 seconds
Started May 28 01:47:31 PM PDT 24
Finished May 28 01:47:34 PM PDT 24
Peak memory 196412 kb
Host smart-8f0f04da-8aed-4bef-a441-741bfd026771
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418900254 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3418900254
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4135343406
Short name T56
Test name
Test status
Simulation time 497686613 ps
CPU time 0.96 seconds
Started May 28 01:47:31 PM PDT 24
Finished May 28 01:47:34 PM PDT 24
Peak memory 183708 kb
Host smart-8432e254-29c7-48c4-89c8-2c4f89958a97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135343406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.4135343406
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.171987479
Short name T332
Test name
Test status
Simulation time 301722847 ps
CPU time 0.66 seconds
Started May 28 01:47:30 PM PDT 24
Finished May 28 01:47:32 PM PDT 24
Peak memory 183596 kb
Host smart-1be37913-ffd3-4285-b294-a0725028206a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171987479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.171987479
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1037118923
Short name T345
Test name
Test status
Simulation time 2327284544 ps
CPU time 2.19 seconds
Started May 28 01:47:32 PM PDT 24
Finished May 28 01:47:37 PM PDT 24
Peak memory 194964 kb
Host smart-3109635a-035c-4204-8c89-79cbcf8e74de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037118923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1037118923
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2160575208
Short name T401
Test name
Test status
Simulation time 455459094 ps
CPU time 1.2 seconds
Started May 28 01:47:32 PM PDT 24
Finished May 28 01:47:36 PM PDT 24
Peak memory 198364 kb
Host smart-c93388ae-556e-4fb2-8239-83ecb108a1bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160575208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2160575208
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1836272705
Short name T388
Test name
Test status
Simulation time 8554526470 ps
CPU time 3.7 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:42 PM PDT 24
Peak memory 198100 kb
Host smart-5c0c98fa-594a-459e-bf39-bebaa8f7d8b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836272705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1836272705
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.875687606
Short name T302
Test name
Test status
Simulation time 387290875 ps
CPU time 1.32 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:41 PM PDT 24
Peak memory 196416 kb
Host smart-c78bf400-5599-44c4-9a97-40ebc438a614
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875687606 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.875687606
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3918217476
Short name T75
Test name
Test status
Simulation time 351494589 ps
CPU time 0.71 seconds
Started May 28 01:47:28 PM PDT 24
Finished May 28 01:47:30 PM PDT 24
Peak memory 193172 kb
Host smart-8cd7d805-2b02-45ca-995c-c8d83a8827d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918217476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3918217476
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1657387433
Short name T298
Test name
Test status
Simulation time 360362969 ps
CPU time 1.19 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:37 PM PDT 24
Peak memory 183644 kb
Host smart-66c0109a-e280-4f5a-9432-542371c8c66b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657387433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1657387433
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1374654882
Short name T350
Test name
Test status
Simulation time 2862580851 ps
CPU time 2.03 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:41 PM PDT 24
Peak memory 194700 kb
Host smart-d9bebf87-2dbc-4ad9-bcea-8b587aeb67d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374654882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1374654882
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3098691166
Short name T303
Test name
Test status
Simulation time 616324874 ps
CPU time 1.5 seconds
Started May 28 01:47:29 PM PDT 24
Finished May 28 01:47:32 PM PDT 24
Peak memory 198424 kb
Host smart-225b23fd-66ce-4543-9a8b-ec3cdf8e0933
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098691166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3098691166
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2760355373
Short name T366
Test name
Test status
Simulation time 4531987763 ps
CPU time 2.48 seconds
Started May 28 01:47:29 PM PDT 24
Finished May 28 01:47:33 PM PDT 24
Peak memory 197744 kb
Host smart-8e2e4a98-1407-4194-8801-d51abf2b4424
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760355373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2760355373
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2568740490
Short name T57
Test name
Test status
Simulation time 392049863 ps
CPU time 0.8 seconds
Started May 28 01:46:48 PM PDT 24
Finished May 28 01:46:51 PM PDT 24
Peak memory 183620 kb
Host smart-5ad9ef4a-b250-4740-8c5f-5fc9abc79f8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568740490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2568740490
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1545312338
Short name T334
Test name
Test status
Simulation time 14541853154 ps
CPU time 3.83 seconds
Started May 28 01:46:42 PM PDT 24
Finished May 28 01:46:50 PM PDT 24
Peak memory 192120 kb
Host smart-2f1dc327-3280-4f63-9762-ab2630cd6145
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545312338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1545312338
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3339737467
Short name T311
Test name
Test status
Simulation time 764495524 ps
CPU time 1.14 seconds
Started May 28 01:46:47 PM PDT 24
Finished May 28 01:46:50 PM PDT 24
Peak memory 183620 kb
Host smart-136c41f7-8937-42ab-bef7-6bf940459625
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339737467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3339737467
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2780436649
Short name T333
Test name
Test status
Simulation time 411569029 ps
CPU time 0.77 seconds
Started May 28 01:46:45 PM PDT 24
Finished May 28 01:46:48 PM PDT 24
Peak memory 195320 kb
Host smart-fa85db4e-ded1-4750-951b-366e5574c874
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780436649 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2780436649
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.199003918
Short name T71
Test name
Test status
Simulation time 463944670 ps
CPU time 0.66 seconds
Started May 28 01:46:41 PM PDT 24
Finished May 28 01:46:46 PM PDT 24
Peak memory 183788 kb
Host smart-f404a943-6f98-4059-a8a0-e377fb0f95a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199003918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.199003918
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2718666323
Short name T292
Test name
Test status
Simulation time 368839170 ps
CPU time 0.61 seconds
Started May 28 01:46:47 PM PDT 24
Finished May 28 01:46:49 PM PDT 24
Peak memory 183552 kb
Host smart-39ff75d8-0a78-40bb-86e7-e053af863513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718666323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2718666323
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.262227922
Short name T361
Test name
Test status
Simulation time 310026135 ps
CPU time 0.71 seconds
Started May 28 01:46:42 PM PDT 24
Finished May 28 01:46:47 PM PDT 24
Peak memory 183548 kb
Host smart-d4ce7ce0-cc94-4329-9144-66d55ebe2076
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262227922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.262227922
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1094072852
Short name T356
Test name
Test status
Simulation time 375284284 ps
CPU time 0.61 seconds
Started May 28 01:46:41 PM PDT 24
Finished May 28 01:46:46 PM PDT 24
Peak memory 183640 kb
Host smart-0d7fa840-10a8-4114-9b3c-8087a6b5a7a2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094072852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1094072852
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2412616868
Short name T411
Test name
Test status
Simulation time 2462054249 ps
CPU time 4.67 seconds
Started May 28 01:46:43 PM PDT 24
Finished May 28 01:46:51 PM PDT 24
Peak memory 194604 kb
Host smart-23d315ff-e908-4cc0-a9b5-adff026315fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412616868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2412616868
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2938853128
Short name T291
Test name
Test status
Simulation time 414748792 ps
CPU time 1.36 seconds
Started May 28 01:46:40 PM PDT 24
Finished May 28 01:46:47 PM PDT 24
Peak memory 198452 kb
Host smart-6c7b2b43-3dea-41aa-be3f-8b43fc1063fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938853128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2938853128
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2509387944
Short name T36
Test name
Test status
Simulation time 4686817127 ps
CPU time 7.42 seconds
Started May 28 01:46:41 PM PDT 24
Finished May 28 01:46:53 PM PDT 24
Peak memory 197520 kb
Host smart-c6a5af6c-5cc4-415e-bb52-99c925133c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509387944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2509387944
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2494522464
Short name T354
Test name
Test status
Simulation time 392740336 ps
CPU time 0.6 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:38 PM PDT 24
Peak memory 183600 kb
Host smart-17795c0b-c1a9-4672-b9ea-e87ca647319c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494522464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2494522464
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.4188929152
Short name T320
Test name
Test status
Simulation time 468088999 ps
CPU time 1.24 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:41 PM PDT 24
Peak memory 183648 kb
Host smart-4bd8bb94-9769-497d-aadf-1f3d25663e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188929152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.4188929152
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1886512814
Short name T296
Test name
Test status
Simulation time 379501489 ps
CPU time 0.6 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:40 PM PDT 24
Peak memory 183644 kb
Host smart-9ef9e228-248f-479e-bc1d-7c0014624cc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886512814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1886512814
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2053531077
Short name T337
Test name
Test status
Simulation time 386073467 ps
CPU time 1.02 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:39 PM PDT 24
Peak memory 183648 kb
Host smart-1d75bc5b-e528-4e8b-a6b1-2c6a0c4e97e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053531077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2053531077
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1814206255
Short name T352
Test name
Test status
Simulation time 380728851 ps
CPU time 1.19 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:38 PM PDT 24
Peak memory 183620 kb
Host smart-f1e7a064-77f3-433b-a668-4346bd4065cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814206255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1814206255
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2777530351
Short name T365
Test name
Test status
Simulation time 382263606 ps
CPU time 0.73 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:39 PM PDT 24
Peak memory 183648 kb
Host smart-0879d17e-c756-4284-b8ae-678439c492f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777530351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2777530351
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4194966637
Short name T315
Test name
Test status
Simulation time 434219819 ps
CPU time 0.97 seconds
Started May 28 01:47:32 PM PDT 24
Finished May 28 01:47:35 PM PDT 24
Peak memory 183628 kb
Host smart-bc14153b-07f9-410c-94dd-90e6255ec76d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194966637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4194966637
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3804324554
Short name T285
Test name
Test status
Simulation time 423470753 ps
CPU time 0.69 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:38 PM PDT 24
Peak memory 183648 kb
Host smart-2bbda5f6-edcd-41bf-8e04-7d55b11d940f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804324554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3804324554
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3197857073
Short name T290
Test name
Test status
Simulation time 313068513 ps
CPU time 1.01 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:38 PM PDT 24
Peak memory 183620 kb
Host smart-bf44b61d-2b43-4696-a74f-6d2e3fd9d019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197857073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3197857073
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2528228242
Short name T300
Test name
Test status
Simulation time 303451182 ps
CPU time 1 seconds
Started May 28 01:47:29 PM PDT 24
Finished May 28 01:47:32 PM PDT 24
Peak memory 183596 kb
Host smart-467ad6ad-727b-425d-97bd-73406cc74848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528228242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2528228242
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1372533540
Short name T418
Test name
Test status
Simulation time 418498003 ps
CPU time 0.81 seconds
Started May 28 01:46:55 PM PDT 24
Finished May 28 01:46:57 PM PDT 24
Peak memory 183732 kb
Host smart-3528a6cc-11c8-49e1-a5c6-90d18090b6e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372533540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1372533540
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.215157496
Short name T52
Test name
Test status
Simulation time 8450777762 ps
CPU time 14.91 seconds
Started May 28 01:46:58 PM PDT 24
Finished May 28 01:47:15 PM PDT 24
Peak memory 192132 kb
Host smart-b09edca5-ef66-4fe1-994e-a89a39a1cf62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215157496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.215157496
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2053941079
Short name T414
Test name
Test status
Simulation time 825798993 ps
CPU time 1.23 seconds
Started May 28 01:47:03 PM PDT 24
Finished May 28 01:47:05 PM PDT 24
Peak memory 183808 kb
Host smart-453a284e-556b-480f-8734-dbcccacbfb79
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053941079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2053941079
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.656406646
Short name T392
Test name
Test status
Simulation time 534397630 ps
CPU time 0.89 seconds
Started May 28 01:47:03 PM PDT 24
Finished May 28 01:47:05 PM PDT 24
Peak memory 196216 kb
Host smart-a4890b78-a04c-44b6-ad31-f467038a460b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656406646 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.656406646
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3130147481
Short name T330
Test name
Test status
Simulation time 532859778 ps
CPU time 1.32 seconds
Started May 28 01:46:55 PM PDT 24
Finished May 28 01:46:58 PM PDT 24
Peak memory 191992 kb
Host smart-3b3804b2-1675-4c37-84b7-d46cbe11ff0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130147481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3130147481
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4071563440
Short name T371
Test name
Test status
Simulation time 420645070 ps
CPU time 1.16 seconds
Started May 28 01:46:56 PM PDT 24
Finished May 28 01:46:59 PM PDT 24
Peak memory 183644 kb
Host smart-6d7782f9-7664-4b5e-b57f-900029b7a5d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071563440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.4071563440
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2685851249
Short name T404
Test name
Test status
Simulation time 317123598 ps
CPU time 0.94 seconds
Started May 28 01:47:02 PM PDT 24
Finished May 28 01:47:04 PM PDT 24
Peak memory 183568 kb
Host smart-f4cd08aa-57c5-4670-b01d-868aa344308d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685851249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2685851249
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2688651596
Short name T382
Test name
Test status
Simulation time 385782289 ps
CPU time 0.66 seconds
Started May 28 01:46:57 PM PDT 24
Finished May 28 01:47:00 PM PDT 24
Peak memory 183824 kb
Host smart-b29be4a5-5391-4c98-a90b-bfa04ec904c6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688651596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2688651596
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3973308071
Short name T81
Test name
Test status
Simulation time 2089684007 ps
CPU time 4.72 seconds
Started May 28 01:47:05 PM PDT 24
Finished May 28 01:47:10 PM PDT 24
Peak memory 193248 kb
Host smart-6d745e8a-5a8a-4e86-b94a-23f934465cd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973308071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3973308071
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3429939628
Short name T307
Test name
Test status
Simulation time 392465852 ps
CPU time 1.66 seconds
Started May 28 01:46:42 PM PDT 24
Finished May 28 01:46:48 PM PDT 24
Peak memory 198456 kb
Host smart-025b2a7b-a953-42af-9cf2-345e3cfa498b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429939628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3429939628
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1901553627
Short name T389
Test name
Test status
Simulation time 401703614 ps
CPU time 1.15 seconds
Started May 28 01:47:32 PM PDT 24
Finished May 28 01:47:36 PM PDT 24
Peak memory 183644 kb
Host smart-2cd0d847-0880-41de-a4f5-982b10bb1701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901553627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1901553627
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2210406551
Short name T364
Test name
Test status
Simulation time 441627997 ps
CPU time 1.36 seconds
Started May 28 01:47:31 PM PDT 24
Finished May 28 01:47:35 PM PDT 24
Peak memory 183668 kb
Host smart-edac7dd0-51d1-4c79-b475-ab060794f379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210406551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2210406551
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1999685573
Short name T288
Test name
Test status
Simulation time 394940573 ps
CPU time 0.98 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:39 PM PDT 24
Peak memory 183596 kb
Host smart-6e68330c-cd83-4a0a-8c36-efa3529b9180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999685573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1999685573
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1238717009
Short name T415
Test name
Test status
Simulation time 434746465 ps
CPU time 0.76 seconds
Started May 28 01:47:29 PM PDT 24
Finished May 28 01:47:32 PM PDT 24
Peak memory 183648 kb
Host smart-599278fe-65ea-4fd5-9af2-75fe94799183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238717009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1238717009
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.447403251
Short name T287
Test name
Test status
Simulation time 400141625 ps
CPU time 1.1 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:39 PM PDT 24
Peak memory 183608 kb
Host smart-2e043f37-d588-4f0f-8684-adccefc61d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447403251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.447403251
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3781247472
Short name T377
Test name
Test status
Simulation time 428461917 ps
CPU time 1.19 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:39 PM PDT 24
Peak memory 183568 kb
Host smart-f9d5d7c8-2567-44a4-97f4-dce6a7a833c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781247472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3781247472
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.426974743
Short name T304
Test name
Test status
Simulation time 473546459 ps
CPU time 0.67 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:39 PM PDT 24
Peak memory 183352 kb
Host smart-be2ddf18-af2c-476e-8235-e00bd7137894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426974743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.426974743
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.571817733
Short name T348
Test name
Test status
Simulation time 380239951 ps
CPU time 0.66 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:37 PM PDT 24
Peak memory 183584 kb
Host smart-c9bc1900-1d91-4da6-8922-417023cba06c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571817733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.571817733
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1058931127
Short name T338
Test name
Test status
Simulation time 499916940 ps
CPU time 0.98 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:39 PM PDT 24
Peak memory 183596 kb
Host smart-a6be3199-22a6-47cf-afdd-f64be8a5bc1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058931127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1058931127
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.102144737
Short name T284
Test name
Test status
Simulation time 372574715 ps
CPU time 1.19 seconds
Started May 28 01:47:32 PM PDT 24
Finished May 28 01:47:36 PM PDT 24
Peak memory 183628 kb
Host smart-16ba9a10-f13b-4452-87f6-f1d23723a61c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102144737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.102144737
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2277388157
Short name T74
Test name
Test status
Simulation time 681929122 ps
CPU time 1.72 seconds
Started May 28 01:46:55 PM PDT 24
Finished May 28 01:46:57 PM PDT 24
Peak memory 183808 kb
Host smart-5280c214-039a-466b-96d4-0ae233f188a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277388157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2277388157
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.858184053
Short name T344
Test name
Test status
Simulation time 7016099060 ps
CPU time 5.62 seconds
Started May 28 01:47:04 PM PDT 24
Finished May 28 01:47:10 PM PDT 24
Peak memory 192148 kb
Host smart-1957f571-a146-48b5-bf3a-91a90b9539b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858184053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.858184053
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2731966224
Short name T342
Test name
Test status
Simulation time 1202982100 ps
CPU time 2.3 seconds
Started May 28 01:46:56 PM PDT 24
Finished May 28 01:47:00 PM PDT 24
Peak memory 192900 kb
Host smart-f0885382-72db-4e17-a634-a955f1bf6e02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731966224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2731966224
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2618334715
Short name T207
Test name
Test status
Simulation time 448063489 ps
CPU time 1.25 seconds
Started May 28 01:46:56 PM PDT 24
Finished May 28 01:46:59 PM PDT 24
Peak memory 195840 kb
Host smart-71de6d1d-2503-4e84-8123-f27524b2c475
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618334715 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2618334715
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.459547629
Short name T319
Test name
Test status
Simulation time 380465340 ps
CPU time 0.85 seconds
Started May 28 01:46:59 PM PDT 24
Finished May 28 01:47:01 PM PDT 24
Peak memory 183668 kb
Host smart-fd5ba214-4ea6-4665-8e54-e856d1b9df80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459547629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.459547629
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2192801630
Short name T353
Test name
Test status
Simulation time 405961607 ps
CPU time 1.21 seconds
Started May 28 01:46:56 PM PDT 24
Finished May 28 01:47:00 PM PDT 24
Peak memory 183628 kb
Host smart-9a6b6e91-97cf-46fc-8a79-bef0fef149df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192801630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2192801630
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3888101536
Short name T310
Test name
Test status
Simulation time 483365478 ps
CPU time 0.62 seconds
Started May 28 01:47:04 PM PDT 24
Finished May 28 01:47:06 PM PDT 24
Peak memory 183568 kb
Host smart-cf47300c-44ba-484b-8f88-b9fe1d3889bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888101536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3888101536
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2068875398
Short name T416
Test name
Test status
Simulation time 270066671 ps
CPU time 0.78 seconds
Started May 28 01:46:58 PM PDT 24
Finished May 28 01:47:01 PM PDT 24
Peak memory 183596 kb
Host smart-9799427f-5c56-4007-a8e8-f2776da144eb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068875398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2068875398
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1954910263
Short name T82
Test name
Test status
Simulation time 2945206466 ps
CPU time 6.76 seconds
Started May 28 01:46:56 PM PDT 24
Finished May 28 01:47:04 PM PDT 24
Peak memory 195092 kb
Host smart-261f0335-a47f-40f6-a0cb-a5ab16dd245b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954910263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1954910263
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3082610213
Short name T380
Test name
Test status
Simulation time 530546502 ps
CPU time 1.64 seconds
Started May 28 01:47:05 PM PDT 24
Finished May 28 01:47:07 PM PDT 24
Peak memory 198452 kb
Host smart-112a39f2-ba67-45fc-8543-097aa2f96c88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082610213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3082610213
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3025141110
Short name T201
Test name
Test status
Simulation time 8052628144 ps
CPU time 4.33 seconds
Started May 28 01:46:57 PM PDT 24
Finished May 28 01:47:04 PM PDT 24
Peak memory 198156 kb
Host smart-b5dded76-a186-4b6c-8649-3f624cb812e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025141110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3025141110
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3280004266
Short name T358
Test name
Test status
Simulation time 347732778 ps
CPU time 0.81 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:37 PM PDT 24
Peak memory 183644 kb
Host smart-6f48b953-c57c-497b-918a-62611d0b6bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280004266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3280004266
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.77265658
Short name T286
Test name
Test status
Simulation time 523434896 ps
CPU time 0.94 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:37 PM PDT 24
Peak memory 183644 kb
Host smart-8811d044-761a-422b-b6a3-fd901fd8dc67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77265658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.77265658
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3651255962
Short name T329
Test name
Test status
Simulation time 510129407 ps
CPU time 0.67 seconds
Started May 28 01:47:30 PM PDT 24
Finished May 28 01:47:32 PM PDT 24
Peak memory 183664 kb
Host smart-ddd5742d-9362-4518-8721-f2a50fde47ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651255962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3651255962
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2368859314
Short name T419
Test name
Test status
Simulation time 399791276 ps
CPU time 1.19 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:38 PM PDT 24
Peak memory 183620 kb
Host smart-0809c1f2-dfe1-4e33-88dc-1ad66cef9131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368859314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2368859314
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1732490797
Short name T340
Test name
Test status
Simulation time 505097612 ps
CPU time 0.74 seconds
Started May 28 01:47:32 PM PDT 24
Finished May 28 01:47:37 PM PDT 24
Peak memory 183600 kb
Host smart-24652111-81e8-4198-826c-4bf0b7470533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732490797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1732490797
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.347742726
Short name T316
Test name
Test status
Simulation time 408047334 ps
CPU time 0.9 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:41 PM PDT 24
Peak memory 183596 kb
Host smart-24d171d0-8b76-493d-ba18-e214d45532d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347742726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.347742726
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1869719560
Short name T324
Test name
Test status
Simulation time 528939690 ps
CPU time 0.78 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:38 PM PDT 24
Peak memory 183644 kb
Host smart-bb244c55-a695-4235-84aa-4977cab70f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869719560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1869719560
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.264150129
Short name T339
Test name
Test status
Simulation time 425528993 ps
CPU time 0.87 seconds
Started May 28 01:47:30 PM PDT 24
Finished May 28 01:47:33 PM PDT 24
Peak memory 183628 kb
Host smart-e998862c-b2c2-4231-9498-e3468dac6c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264150129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.264150129
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1604793850
Short name T374
Test name
Test status
Simulation time 533522699 ps
CPU time 0.71 seconds
Started May 28 01:47:30 PM PDT 24
Finished May 28 01:47:32 PM PDT 24
Peak memory 183628 kb
Host smart-0eaf133f-341a-4c9d-b594-7b2d78aed8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604793850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1604793850
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.977268017
Short name T326
Test name
Test status
Simulation time 433185647 ps
CPU time 1.22 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:38 PM PDT 24
Peak memory 183648 kb
Host smart-3e2d70a8-2b2c-4c4f-a4ca-78ec69bfa1a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977268017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.977268017
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.265003301
Short name T394
Test name
Test status
Simulation time 531031337 ps
CPU time 0.92 seconds
Started May 28 01:47:04 PM PDT 24
Finished May 28 01:47:06 PM PDT 24
Peak memory 197144 kb
Host smart-b4579089-3341-4607-bb19-751c866ec7ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265003301 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.265003301
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2459769091
Short name T53
Test name
Test status
Simulation time 384320034 ps
CPU time 0.82 seconds
Started May 28 01:46:57 PM PDT 24
Finished May 28 01:47:00 PM PDT 24
Peak memory 183788 kb
Host smart-529731b7-b8bd-4d68-a2c4-f9a7d01dc977
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459769091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2459769091
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2455707415
Short name T308
Test name
Test status
Simulation time 496247438 ps
CPU time 1.35 seconds
Started May 28 01:47:05 PM PDT 24
Finished May 28 01:47:07 PM PDT 24
Peak memory 183644 kb
Host smart-f7a21ab2-bc35-4bf1-8f95-9a07a6951ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455707415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2455707415
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2218924923
Short name T372
Test name
Test status
Simulation time 1310104377 ps
CPU time 1.25 seconds
Started May 28 01:46:56 PM PDT 24
Finished May 28 01:47:00 PM PDT 24
Peak memory 183636 kb
Host smart-9e1f2130-8e7c-4bd6-adf3-f68782824446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218924923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2218924923
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2432839314
Short name T355
Test name
Test status
Simulation time 467984006 ps
CPU time 1 seconds
Started May 28 01:46:57 PM PDT 24
Finished May 28 01:47:00 PM PDT 24
Peak memory 196760 kb
Host smart-296ea6e8-17fb-436b-9f80-49b3cfcda8be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432839314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2432839314
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3754933369
Short name T299
Test name
Test status
Simulation time 484809383 ps
CPU time 0.88 seconds
Started May 28 01:47:14 PM PDT 24
Finished May 28 01:47:17 PM PDT 24
Peak memory 196356 kb
Host smart-9d6cde97-c8b5-41d2-a40c-96a16f85c707
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754933369 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3754933369
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3947738464
Short name T391
Test name
Test status
Simulation time 488291334 ps
CPU time 1.32 seconds
Started May 28 01:46:56 PM PDT 24
Finished May 28 01:46:59 PM PDT 24
Peak memory 183716 kb
Host smart-2252d186-6994-4252-a9cd-1d1e7c42fe99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947738464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3947738464
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.308439814
Short name T412
Test name
Test status
Simulation time 278095873 ps
CPU time 0.94 seconds
Started May 28 01:46:55 PM PDT 24
Finished May 28 01:46:58 PM PDT 24
Peak memory 183612 kb
Host smart-7cf3bdb0-be1f-4123-9d9a-dd74065b231b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308439814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.308439814
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2645608158
Short name T397
Test name
Test status
Simulation time 2416599212 ps
CPU time 6.63 seconds
Started May 28 01:47:02 PM PDT 24
Finished May 28 01:47:09 PM PDT 24
Peak memory 183868 kb
Host smart-5286405b-01be-4b62-b9bf-d42be736323f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645608158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2645608158
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3474710308
Short name T309
Test name
Test status
Simulation time 326527768 ps
CPU time 2.41 seconds
Started May 28 01:46:57 PM PDT 24
Finished May 28 01:47:02 PM PDT 24
Peak memory 198480 kb
Host smart-a7fc7d07-ec0a-4277-9b16-144399b4d44e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474710308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3474710308
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.821101038
Short name T370
Test name
Test status
Simulation time 4232649172 ps
CPU time 3.89 seconds
Started May 28 01:47:05 PM PDT 24
Finished May 28 01:47:10 PM PDT 24
Peak memory 197824 kb
Host smart-05af75eb-0983-4307-bf6a-1380825cacd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821101038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.821101038
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.614009794
Short name T407
Test name
Test status
Simulation time 585313954 ps
CPU time 1.03 seconds
Started May 28 01:47:09 PM PDT 24
Finished May 28 01:47:11 PM PDT 24
Peak memory 197568 kb
Host smart-80a9ff91-2e36-431e-945b-b35bf1cfc8a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614009794 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.614009794
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3658440765
Short name T406
Test name
Test status
Simulation time 477836989 ps
CPU time 0.72 seconds
Started May 28 01:47:14 PM PDT 24
Finished May 28 01:47:17 PM PDT 24
Peak memory 191928 kb
Host smart-52fa0810-7305-486f-93b7-5c193509c991
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658440765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3658440765
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.367211483
Short name T314
Test name
Test status
Simulation time 522132194 ps
CPU time 0.62 seconds
Started May 28 01:47:11 PM PDT 24
Finished May 28 01:47:13 PM PDT 24
Peak memory 183648 kb
Host smart-becb5703-8213-43da-87cf-eadb47667c14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367211483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.367211483
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1702512641
Short name T76
Test name
Test status
Simulation time 2041472025 ps
CPU time 3.1 seconds
Started May 28 01:47:11 PM PDT 24
Finished May 28 01:47:16 PM PDT 24
Peak memory 194328 kb
Host smart-d2142333-627d-47ed-99cc-ef79fcd0955a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702512641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1702512641
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3364096717
Short name T346
Test name
Test status
Simulation time 458039654 ps
CPU time 2.33 seconds
Started May 28 01:47:09 PM PDT 24
Finished May 28 01:47:13 PM PDT 24
Peak memory 198344 kb
Host smart-890c3089-4e6c-476e-8ea9-36cf89e9563a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364096717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3364096717
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3984207608
Short name T200
Test name
Test status
Simulation time 4346790710 ps
CPU time 6.61 seconds
Started May 28 01:47:12 PM PDT 24
Finished May 28 01:47:20 PM PDT 24
Peak memory 197464 kb
Host smart-df21429b-2b7e-4406-86a7-ebc6d3f4bca5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984207608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3984207608
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2500272583
Short name T294
Test name
Test status
Simulation time 599875725 ps
CPU time 0.88 seconds
Started May 28 01:47:11 PM PDT 24
Finished May 28 01:47:13 PM PDT 24
Peak memory 196044 kb
Host smart-573624c5-2db7-4689-a994-5739d7430dc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500272583 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2500272583
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3052556237
Short name T351
Test name
Test status
Simulation time 338709242 ps
CPU time 1.09 seconds
Started May 28 01:47:15 PM PDT 24
Finished May 28 01:47:18 PM PDT 24
Peak memory 183980 kb
Host smart-9f503329-2a80-4afd-ba39-e8b537f0aef8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052556237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3052556237
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.28466898
Short name T384
Test name
Test status
Simulation time 295338568 ps
CPU time 0.75 seconds
Started May 28 01:47:15 PM PDT 24
Finished May 28 01:47:17 PM PDT 24
Peak memory 183584 kb
Host smart-1df85166-2146-4b5f-9902-0c64320d4da8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28466898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.28466898
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1221655941
Short name T35
Test name
Test status
Simulation time 2839812163 ps
CPU time 7.45 seconds
Started May 28 01:47:12 PM PDT 24
Finished May 28 01:47:22 PM PDT 24
Peak memory 194140 kb
Host smart-afa6f5b6-1c8a-4d9f-99b7-718264b98104
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221655941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1221655941
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.166503775
Short name T395
Test name
Test status
Simulation time 1051368011 ps
CPU time 2.38 seconds
Started May 28 01:47:10 PM PDT 24
Finished May 28 01:47:14 PM PDT 24
Peak memory 198476 kb
Host smart-21128dfa-34e2-413b-a7c3-d86be580e10c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166503775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.166503775
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1566072934
Short name T322
Test name
Test status
Simulation time 4551813771 ps
CPU time 3.2 seconds
Started May 28 01:47:09 PM PDT 24
Finished May 28 01:47:14 PM PDT 24
Peak memory 197712 kb
Host smart-3c511717-8e8f-404e-8fde-6673229a7dec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566072934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1566072934
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.936377041
Short name T325
Test name
Test status
Simulation time 382137892 ps
CPU time 1.19 seconds
Started May 28 01:47:10 PM PDT 24
Finished May 28 01:47:13 PM PDT 24
Peak memory 195712 kb
Host smart-84777583-b43b-40da-b01c-dd61e2028ba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936377041 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.936377041
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1255017016
Short name T54
Test name
Test status
Simulation time 496555819 ps
CPU time 0.78 seconds
Started May 28 01:47:10 PM PDT 24
Finished May 28 01:47:13 PM PDT 24
Peak memory 192160 kb
Host smart-099d94ef-df31-44cc-83c8-b66ed2e18411
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255017016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1255017016
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1505076159
Short name T376
Test name
Test status
Simulation time 419931256 ps
CPU time 0.66 seconds
Started May 28 01:47:15 PM PDT 24
Finished May 28 01:47:17 PM PDT 24
Peak memory 183636 kb
Host smart-642d1cec-28da-49b0-83a7-61223dda430a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505076159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1505076159
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4125942610
Short name T83
Test name
Test status
Simulation time 2633094369 ps
CPU time 2.55 seconds
Started May 28 01:47:09 PM PDT 24
Finished May 28 01:47:12 PM PDT 24
Peak memory 193896 kb
Host smart-7bbb426f-cc5f-418a-8432-5b3318881ac8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125942610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.4125942610
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4127875603
Short name T341
Test name
Test status
Simulation time 551008654 ps
CPU time 2.36 seconds
Started May 28 01:47:09 PM PDT 24
Finished May 28 01:47:13 PM PDT 24
Peak memory 198404 kb
Host smart-98068b0a-4b9c-46fe-9e6d-fc53bdf0cce0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127875603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.4127875603
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3027444549
Short name T328
Test name
Test status
Simulation time 4308427819 ps
CPU time 2.45 seconds
Started May 28 01:47:09 PM PDT 24
Finished May 28 01:47:13 PM PDT 24
Peak memory 197488 kb
Host smart-fae46a3a-051b-4008-81ca-edb40509c129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027444549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3027444549
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3973351793
Short name T270
Test name
Test status
Simulation time 58674625914 ps
CPU time 21.66 seconds
Started May 28 01:10:36 PM PDT 24
Finished May 28 01:11:00 PM PDT 24
Peak memory 191820 kb
Host smart-cd115beb-ebde-44a0-8829-cace60d7168b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973351793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3973351793
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.668677653
Short name T240
Test name
Test status
Simulation time 485867917 ps
CPU time 0.77 seconds
Started May 28 01:10:47 PM PDT 24
Finished May 28 01:10:52 PM PDT 24
Peak memory 191692 kb
Host smart-33a9d5c5-c99c-4468-998e-78b296c60dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668677653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.668677653
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3564234940
Short name T244
Test name
Test status
Simulation time 37033108004 ps
CPU time 14.96 seconds
Started May 28 01:10:39 PM PDT 24
Finished May 28 01:10:58 PM PDT 24
Peak memory 191828 kb
Host smart-30131e60-0219-4a94-8a8e-f3ed49b3abc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564234940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3564234940
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1751975077
Short name T13
Test name
Test status
Simulation time 4271058607 ps
CPU time 7.53 seconds
Started May 28 01:10:40 PM PDT 24
Finished May 28 01:10:51 PM PDT 24
Peak memory 215320 kb
Host smart-57e71f31-941e-428d-a1e9-5ae8d1ab71ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751975077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1751975077
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2446916255
Short name T237
Test name
Test status
Simulation time 380722073 ps
CPU time 0.73 seconds
Started May 28 01:10:41 PM PDT 24
Finished May 28 01:10:46 PM PDT 24
Peak memory 191752 kb
Host smart-74299d8e-9e6f-4386-9b63-721898c3e306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446916255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2446916255
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1886609847
Short name T174
Test name
Test status
Simulation time 585800171 ps
CPU time 1.45 seconds
Started May 28 01:10:58 PM PDT 24
Finished May 28 01:11:02 PM PDT 24
Peak memory 196384 kb
Host smart-6c0762eb-f7f1-497d-a10e-d0444821dd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886609847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1886609847
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1426237279
Short name T272
Test name
Test status
Simulation time 1554337604 ps
CPU time 1.85 seconds
Started May 28 01:10:59 PM PDT 24
Finished May 28 01:11:03 PM PDT 24
Peak memory 191704 kb
Host smart-0421d39c-7cf1-43d5-95c7-b4eb3d39e920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426237279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1426237279
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3654545655
Short name T210
Test name
Test status
Simulation time 473965713 ps
CPU time 0.84 seconds
Started May 28 01:10:58 PM PDT 24
Finished May 28 01:11:01 PM PDT 24
Peak memory 191820 kb
Host smart-899bbef5-bb2d-48f1-b503-52d99e48a6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654545655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3654545655
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.837460342
Short name T248
Test name
Test status
Simulation time 5580213517 ps
CPU time 2.76 seconds
Started May 28 01:10:44 PM PDT 24
Finished May 28 01:10:50 PM PDT 24
Peak memory 191904 kb
Host smart-62fe1302-6ec0-4358-9139-dae98b2e5c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837460342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.837460342
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.129695317
Short name T278
Test name
Test status
Simulation time 502127871 ps
CPU time 1.26 seconds
Started May 28 01:10:52 PM PDT 24
Finished May 28 01:10:56 PM PDT 24
Peak memory 191700 kb
Host smart-49c777a1-77ef-4415-aee4-0ca2fc2c902c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129695317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.129695317
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.169982338
Short name T226
Test name
Test status
Simulation time 6623536514 ps
CPU time 6.09 seconds
Started May 28 01:10:47 PM PDT 24
Finished May 28 01:10:57 PM PDT 24
Peak memory 191832 kb
Host smart-ea29c231-2b7f-4655-b438-1b49e8a4225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169982338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.169982338
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1763522113
Short name T224
Test name
Test status
Simulation time 585123760 ps
CPU time 1.64 seconds
Started May 28 01:10:49 PM PDT 24
Finished May 28 01:10:54 PM PDT 24
Peak memory 191820 kb
Host smart-f23f2ba7-07cd-4999-b965-08a078ac90e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763522113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1763522113
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3695019799
Short name T271
Test name
Test status
Simulation time 14305190127 ps
CPU time 6.97 seconds
Started May 28 01:10:47 PM PDT 24
Finished May 28 01:10:58 PM PDT 24
Peak memory 191824 kb
Host smart-50e6cdc4-c3c6-4a31-82b1-0321b7c4e70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695019799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3695019799
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2491521109
Short name T275
Test name
Test status
Simulation time 489660887 ps
CPU time 0.78 seconds
Started May 28 01:10:45 PM PDT 24
Finished May 28 01:10:50 PM PDT 24
Peak memory 191712 kb
Host smart-c77b8924-ed74-4774-a5ed-5ee16da5163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491521109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2491521109
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.34874476
Short name T223
Test name
Test status
Simulation time 28128852779 ps
CPU time 11.58 seconds
Started May 28 01:10:51 PM PDT 24
Finished May 28 01:11:05 PM PDT 24
Peak memory 191820 kb
Host smart-0f374895-dc36-4703-b60b-864265ab337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34874476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.34874476
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.501939796
Short name T253
Test name
Test status
Simulation time 609968276 ps
CPU time 0.98 seconds
Started May 28 01:10:47 PM PDT 24
Finished May 28 01:10:52 PM PDT 24
Peak memory 191700 kb
Host smart-c48f6b2d-2a94-4467-9b52-4e283ffcc6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501939796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.501939796
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3423659247
Short name T265
Test name
Test status
Simulation time 25560835297 ps
CPU time 11.66 seconds
Started May 28 01:10:40 PM PDT 24
Finished May 28 01:10:56 PM PDT 24
Peak memory 191912 kb
Host smart-d9879f2a-8cb6-4ce8-862e-cddd76c6d630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423659247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3423659247
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.403722198
Short name T23
Test name
Test status
Simulation time 485857108 ps
CPU time 0.88 seconds
Started May 28 01:10:49 PM PDT 24
Finished May 28 01:10:54 PM PDT 24
Peak memory 191784 kb
Host smart-823b3841-c327-4b14-b813-323bbe902aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403722198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.403722198
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1503113618
Short name T236
Test name
Test status
Simulation time 13878417573 ps
CPU time 5.66 seconds
Started May 28 01:10:48 PM PDT 24
Finished May 28 01:10:57 PM PDT 24
Peak memory 191904 kb
Host smart-e1663ed9-f9dd-4965-9f1a-5c431ccf2088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503113618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1503113618
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2351389877
Short name T269
Test name
Test status
Simulation time 700036956 ps
CPU time 0.67 seconds
Started May 28 01:10:42 PM PDT 24
Finished May 28 01:10:46 PM PDT 24
Peak memory 191660 kb
Host smart-632a3c02-4404-4348-87fb-01fb864edacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351389877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2351389877
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2594003428
Short name T211
Test name
Test status
Simulation time 29312185339 ps
CPU time 23.94 seconds
Started May 28 01:10:45 PM PDT 24
Finished May 28 01:11:13 PM PDT 24
Peak memory 191820 kb
Host smart-9b7566bc-c810-4526-9b58-7744b16d2433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594003428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2594003428
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.157820390
Short name T274
Test name
Test status
Simulation time 655587340 ps
CPU time 0.65 seconds
Started May 28 01:10:51 PM PDT 24
Finished May 28 01:10:55 PM PDT 24
Peak memory 191696 kb
Host smart-08348029-2524-490f-b6b4-8096828cfda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157820390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.157820390
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.579228324
Short name T280
Test name
Test status
Simulation time 27271870625 ps
CPU time 37.52 seconds
Started May 28 01:11:01 PM PDT 24
Finished May 28 01:11:41 PM PDT 24
Peak memory 191820 kb
Host smart-8f38d812-ebe4-413c-94d4-d5f5ef257638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579228324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.579228324
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3799967506
Short name T214
Test name
Test status
Simulation time 583642157 ps
CPU time 0.93 seconds
Started May 28 01:10:45 PM PDT 24
Finished May 28 01:10:50 PM PDT 24
Peak memory 191712 kb
Host smart-51de4db2-80da-4769-b0c1-dd92e9f4e219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799967506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3799967506
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2140183143
Short name T216
Test name
Test status
Simulation time 51226800404 ps
CPU time 86.73 seconds
Started May 28 01:10:51 PM PDT 24
Finished May 28 01:12:21 PM PDT 24
Peak memory 191820 kb
Host smart-3369c78e-393b-4c2c-ac6d-e36b886dbc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140183143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2140183143
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.999934366
Short name T209
Test name
Test status
Simulation time 576327852 ps
CPU time 0.83 seconds
Started May 28 01:10:49 PM PDT 24
Finished May 28 01:10:53 PM PDT 24
Peak memory 191736 kb
Host smart-98e96b7e-dcfb-4db8-a119-1f2024605eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999934366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.999934366
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3407210144
Short name T49
Test name
Test status
Simulation time 38018473015 ps
CPU time 54.55 seconds
Started May 28 01:10:37 PM PDT 24
Finished May 28 01:11:35 PM PDT 24
Peak memory 191860 kb
Host smart-0f74edad-14b9-47d1-8d13-f415becf9e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407210144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3407210144
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.4036183080
Short name T15
Test name
Test status
Simulation time 4208569076 ps
CPU time 2.22 seconds
Started May 28 01:10:40 PM PDT 24
Finished May 28 01:10:46 PM PDT 24
Peak memory 215296 kb
Host smart-6f993486-71dc-42d6-94b2-21379218c6bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036183080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.4036183080
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3990208922
Short name T249
Test name
Test status
Simulation time 640487064 ps
CPU time 0.82 seconds
Started May 28 01:10:53 PM PDT 24
Finished May 28 01:10:56 PM PDT 24
Peak memory 191696 kb
Host smart-06d7429c-386c-4c8a-874e-841a76f10fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990208922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3990208922
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3390357833
Short name T258
Test name
Test status
Simulation time 34562074767 ps
CPU time 8.19 seconds
Started May 28 01:10:54 PM PDT 24
Finished May 28 01:11:05 PM PDT 24
Peak memory 191908 kb
Host smart-bf0d0e2b-966b-45c6-82db-a394e7faf9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390357833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3390357833
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3793394579
Short name T254
Test name
Test status
Simulation time 416281397 ps
CPU time 1.18 seconds
Started May 28 01:10:43 PM PDT 24
Finished May 28 01:10:48 PM PDT 24
Peak memory 191612 kb
Host smart-c5f4859d-d642-498e-a5e0-c976d3fc57f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793394579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3793394579
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1829949190
Short name T266
Test name
Test status
Simulation time 21568324573 ps
CPU time 5.7 seconds
Started May 28 01:10:57 PM PDT 24
Finished May 28 01:11:05 PM PDT 24
Peak memory 191908 kb
Host smart-7f3c6c05-ae96-43aa-9ea2-2734b9788752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829949190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1829949190
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2851934265
Short name T264
Test name
Test status
Simulation time 470121366 ps
CPU time 1.24 seconds
Started May 28 01:10:54 PM PDT 24
Finished May 28 01:10:58 PM PDT 24
Peak memory 191708 kb
Host smart-c557d93d-2f30-4a7f-a57c-59b087b0081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851934265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2851934265
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2485446929
Short name T225
Test name
Test status
Simulation time 9511544473 ps
CPU time 14.1 seconds
Started May 28 01:10:57 PM PDT 24
Finished May 28 01:11:14 PM PDT 24
Peak memory 191908 kb
Host smart-327797eb-6874-4d57-a996-7534744fad63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485446929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2485446929
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.4155603786
Short name T247
Test name
Test status
Simulation time 590109773 ps
CPU time 0.83 seconds
Started May 28 01:10:51 PM PDT 24
Finished May 28 01:10:55 PM PDT 24
Peak memory 192044 kb
Host smart-c432a103-4cb6-4fec-b756-5deff3a4c7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155603786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4155603786
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.321228528
Short name T228
Test name
Test status
Simulation time 23992548516 ps
CPU time 38.02 seconds
Started May 28 01:11:03 PM PDT 24
Finished May 28 01:11:44 PM PDT 24
Peak memory 192176 kb
Host smart-4b58b8a1-02bc-4725-bd53-0b0127b7d8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321228528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.321228528
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2136569161
Short name T279
Test name
Test status
Simulation time 401560480 ps
CPU time 1 seconds
Started May 28 01:10:47 PM PDT 24
Finished May 28 01:10:52 PM PDT 24
Peak memory 191700 kb
Host smart-991d518a-1288-4f06-aafd-3e72e1bfcf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136569161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2136569161
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1731630855
Short name T213
Test name
Test status
Simulation time 37005162055 ps
CPU time 5.17 seconds
Started May 28 01:11:05 PM PDT 24
Finished May 28 01:11:13 PM PDT 24
Peak memory 191908 kb
Host smart-08bd143a-9a2b-47c5-a0da-49419f307b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731630855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1731630855
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3623294376
Short name T227
Test name
Test status
Simulation time 546014410 ps
CPU time 1.41 seconds
Started May 28 01:10:41 PM PDT 24
Finished May 28 01:10:46 PM PDT 24
Peak memory 191704 kb
Host smart-f24a15fb-a8b4-440b-8487-2574965c12f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623294376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3623294376
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3054751920
Short name T98
Test name
Test status
Simulation time 34748994631 ps
CPU time 11.05 seconds
Started May 28 01:11:00 PM PDT 24
Finished May 28 01:11:14 PM PDT 24
Peak memory 191888 kb
Host smart-8c52d0f4-6fd6-466b-a4d8-e0d357ae3ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054751920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3054751920
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1959905399
Short name T20
Test name
Test status
Simulation time 461645671 ps
CPU time 0.77 seconds
Started May 28 01:10:49 PM PDT 24
Finished May 28 01:10:54 PM PDT 24
Peak memory 191708 kb
Host smart-4242c6b0-a35c-4e9c-a245-1e70dc561bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959905399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1959905399
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3069420301
Short name T1
Test name
Test status
Simulation time 22292363658 ps
CPU time 16.61 seconds
Started May 28 01:10:59 PM PDT 24
Finished May 28 01:11:18 PM PDT 24
Peak memory 191824 kb
Host smart-63f5845e-c6c5-4f4b-9af1-7bec9879b0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069420301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3069420301
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1437286136
Short name T250
Test name
Test status
Simulation time 377197066 ps
CPU time 0.65 seconds
Started May 28 01:11:00 PM PDT 24
Finished May 28 01:11:04 PM PDT 24
Peak memory 191772 kb
Host smart-7f48c1e4-dce5-4d44-b94a-6fdd2ded5e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437286136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1437286136
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3225306318
Short name T47
Test name
Test status
Simulation time 27000888171 ps
CPU time 9.06 seconds
Started May 28 01:11:01 PM PDT 24
Finished May 28 01:11:14 PM PDT 24
Peak memory 191788 kb
Host smart-f8ba7238-1f38-4766-b009-bb64a28471fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225306318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3225306318
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1535988976
Short name T31
Test name
Test status
Simulation time 441891734 ps
CPU time 1.26 seconds
Started May 28 01:11:09 PM PDT 24
Finished May 28 01:11:13 PM PDT 24
Peak memory 191768 kb
Host smart-1d7801e0-fe69-41b0-aecb-68d8a5c87894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535988976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1535988976
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3766641467
Short name T255
Test name
Test status
Simulation time 35729057660 ps
CPU time 15.57 seconds
Started May 28 01:10:59 PM PDT 24
Finished May 28 01:11:16 PM PDT 24
Peak memory 191824 kb
Host smart-626711d1-6753-4494-a110-b4dfb998b0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766641467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3766641467
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2314230908
Short name T22
Test name
Test status
Simulation time 408182485 ps
CPU time 0.92 seconds
Started May 28 01:11:02 PM PDT 24
Finished May 28 01:11:06 PM PDT 24
Peak memory 191788 kb
Host smart-14e911f6-f181-4c7f-85d5-32e2c2a9fb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314230908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2314230908
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2368524009
Short name T206
Test name
Test status
Simulation time 24073694949 ps
CPU time 2.61 seconds
Started May 28 01:11:05 PM PDT 24
Finished May 28 01:11:10 PM PDT 24
Peak memory 191824 kb
Host smart-03818b6b-4c79-43c9-8e78-0e481d1a8e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368524009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2368524009
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2205357938
Short name T257
Test name
Test status
Simulation time 602642294 ps
CPU time 0.82 seconds
Started May 28 01:11:03 PM PDT 24
Finished May 28 01:11:07 PM PDT 24
Peak memory 191752 kb
Host smart-6cdc60bf-13a6-475e-8b11-86b7a2ff1f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205357938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2205357938
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1060107261
Short name T215
Test name
Test status
Simulation time 51500520778 ps
CPU time 17.06 seconds
Started May 28 01:10:34 PM PDT 24
Finished May 28 01:10:53 PM PDT 24
Peak memory 191752 kb
Host smart-c4e7d02d-8c6e-4707-94ea-7e5c7ba37db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060107261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1060107261
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1587390884
Short name T14
Test name
Test status
Simulation time 7975622876 ps
CPU time 3.64 seconds
Started May 28 01:10:39 PM PDT 24
Finished May 28 01:10:46 PM PDT 24
Peak memory 215616 kb
Host smart-5ea44e96-9fad-4946-a95f-7d2b87d035f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587390884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1587390884
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2846077679
Short name T243
Test name
Test status
Simulation time 474831731 ps
CPU time 0.71 seconds
Started May 28 01:10:36 PM PDT 24
Finished May 28 01:10:40 PM PDT 24
Peak memory 191700 kb
Host smart-b0b7b236-c3d4-41cb-8192-48ccbc4153cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846077679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2846077679
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1983523004
Short name T64
Test name
Test status
Simulation time 61606600473 ps
CPU time 5.61 seconds
Started May 28 01:10:58 PM PDT 24
Finished May 28 01:11:06 PM PDT 24
Peak memory 191832 kb
Host smart-5e4525fe-8b07-4689-81e2-2e3f60a18fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983523004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1983523004
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3944845452
Short name T28
Test name
Test status
Simulation time 430540883 ps
CPU time 0.74 seconds
Started May 28 01:10:55 PM PDT 24
Finished May 28 01:10:58 PM PDT 24
Peak memory 191716 kb
Host smart-39c90863-7360-4aa9-9d27-ebee94884901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944845452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3944845452
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3846425655
Short name T259
Test name
Test status
Simulation time 18187434885 ps
CPU time 3.16 seconds
Started May 28 01:11:02 PM PDT 24
Finished May 28 01:11:09 PM PDT 24
Peak memory 191808 kb
Host smart-b2f594d8-4287-43b6-9fbd-b51e6622045c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846425655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3846425655
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2988743269
Short name T251
Test name
Test status
Simulation time 590788818 ps
CPU time 1.52 seconds
Started May 28 01:11:00 PM PDT 24
Finished May 28 01:11:05 PM PDT 24
Peak memory 191772 kb
Host smart-b31b0426-cfd5-47e6-9e0d-fd60178dc25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988743269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2988743269
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1948115852
Short name T193
Test name
Test status
Simulation time 509801296 ps
CPU time 0.83 seconds
Started May 28 01:11:00 PM PDT 24
Finished May 28 01:11:04 PM PDT 24
Peak memory 196352 kb
Host smart-0c914052-9857-4a31-8dd3-5c63e8e18b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948115852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1948115852
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.261632088
Short name T256
Test name
Test status
Simulation time 1283714005 ps
CPU time 2.45 seconds
Started May 28 01:11:06 PM PDT 24
Finished May 28 01:11:11 PM PDT 24
Peak memory 191804 kb
Host smart-f33c3e33-52eb-4774-94d9-817bc9b68c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261632088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.261632088
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.614631900
Short name T218
Test name
Test status
Simulation time 384256223 ps
CPU time 0.88 seconds
Started May 28 01:11:00 PM PDT 24
Finished May 28 01:11:04 PM PDT 24
Peak memory 191784 kb
Host smart-a203052b-377f-4000-930e-c9634a999983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614631900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.614631900
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2676545704
Short name T199
Test name
Test status
Simulation time 496408147 ps
CPU time 0.87 seconds
Started May 28 01:11:07 PM PDT 24
Finished May 28 01:11:11 PM PDT 24
Peak memory 196380 kb
Host smart-25b6cf4f-1d7d-4a93-aefe-f87401e513d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676545704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2676545704
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.564796648
Short name T66
Test name
Test status
Simulation time 37789991204 ps
CPU time 21.78 seconds
Started May 28 01:11:06 PM PDT 24
Finished May 28 01:11:31 PM PDT 24
Peak memory 192176 kb
Host smart-5beb4a1f-255a-424a-87ba-60c624204279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564796648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.564796648
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1425348015
Short name T235
Test name
Test status
Simulation time 580021797 ps
CPU time 1.37 seconds
Started May 28 01:11:04 PM PDT 24
Finished May 28 01:11:09 PM PDT 24
Peak memory 191788 kb
Host smart-3d312d6e-2c82-49fa-b8b1-792e817778e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425348015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1425348015
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.467027464
Short name T261
Test name
Test status
Simulation time 19442103757 ps
CPU time 8.56 seconds
Started May 28 01:10:59 PM PDT 24
Finished May 28 01:11:11 PM PDT 24
Peak memory 191936 kb
Host smart-9059f95e-819e-410a-a51a-e2e747a6dee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467027464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.467027464
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3436738875
Short name T246
Test name
Test status
Simulation time 442610887 ps
CPU time 1.27 seconds
Started May 28 01:10:59 PM PDT 24
Finished May 28 01:11:04 PM PDT 24
Peak memory 191716 kb
Host smart-0fb4df9f-e51d-431d-aa11-2bd6564827fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436738875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3436738875
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3363482206
Short name T2
Test name
Test status
Simulation time 40875217904 ps
CPU time 11.91 seconds
Started May 28 01:11:00 PM PDT 24
Finished May 28 01:11:15 PM PDT 24
Peak memory 191912 kb
Host smart-eabf2acb-7231-461a-b602-6c547ca82e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363482206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3363482206
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1614437525
Short name T100
Test name
Test status
Simulation time 587141689 ps
CPU time 1.48 seconds
Started May 28 01:11:06 PM PDT 24
Finished May 28 01:11:11 PM PDT 24
Peak memory 191704 kb
Host smart-d81e81cd-9ffe-4d01-bd49-ceebc97da845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614437525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1614437525
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.4142338253
Short name T222
Test name
Test status
Simulation time 59362572976 ps
CPU time 32.87 seconds
Started May 28 01:11:05 PM PDT 24
Finished May 28 01:11:41 PM PDT 24
Peak memory 191824 kb
Host smart-5e0d6638-6b58-427a-8af2-3e691b7a404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142338253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.4142338253
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.719955608
Short name T19
Test name
Test status
Simulation time 514364764 ps
CPU time 1.4 seconds
Started May 28 01:11:04 PM PDT 24
Finished May 28 01:11:09 PM PDT 24
Peak memory 191820 kb
Host smart-7074088f-a5ad-4948-b069-792057eb7c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719955608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.719955608
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2256552392
Short name T252
Test name
Test status
Simulation time 11224513527 ps
CPU time 4.84 seconds
Started May 28 01:11:06 PM PDT 24
Finished May 28 01:11:14 PM PDT 24
Peak memory 191908 kb
Host smart-2face809-ea82-4eaf-be8e-1e40d56f314d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256552392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2256552392
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2778087743
Short name T263
Test name
Test status
Simulation time 615362998 ps
CPU time 1.09 seconds
Started May 28 01:11:12 PM PDT 24
Finished May 28 01:11:14 PM PDT 24
Peak memory 191792 kb
Host smart-03ae66ee-4e1d-4275-a79a-a05ed25556a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778087743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2778087743
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3487704336
Short name T183
Test name
Test status
Simulation time 342141289 ps
CPU time 1.13 seconds
Started May 28 01:11:28 PM PDT 24
Finished May 28 01:11:39 PM PDT 24
Peak memory 196316 kb
Host smart-35e5eecc-628d-4a4a-a4bb-1405bf132feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487704336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3487704336
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.549065652
Short name T245
Test name
Test status
Simulation time 3393832644 ps
CPU time 5.69 seconds
Started May 28 01:11:21 PM PDT 24
Finished May 28 01:11:28 PM PDT 24
Peak memory 191832 kb
Host smart-be467572-7064-4c1e-9214-c2a5976a1c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549065652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.549065652
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.4034910940
Short name T233
Test name
Test status
Simulation time 418071419 ps
CPU time 0.96 seconds
Started May 28 01:11:03 PM PDT 24
Finished May 28 01:11:07 PM PDT 24
Peak memory 191708 kb
Host smart-f548c9ee-c2e0-43e4-adef-7ee8078126a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034910940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4034910940
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3438290537
Short name T97
Test name
Test status
Simulation time 36926939332 ps
CPU time 15.47 seconds
Started May 28 01:11:22 PM PDT 24
Finished May 28 01:11:41 PM PDT 24
Peak memory 191944 kb
Host smart-ee336d86-bca6-4cb8-93d4-c26619a5ca94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438290537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3438290537
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3514579635
Short name T238
Test name
Test status
Simulation time 541429323 ps
CPU time 1.54 seconds
Started May 28 01:11:20 PM PDT 24
Finished May 28 01:11:24 PM PDT 24
Peak memory 191772 kb
Host smart-5243889f-282e-4412-89ed-9fd97f15eb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514579635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3514579635
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.932369870
Short name T221
Test name
Test status
Simulation time 41066569667 ps
CPU time 6.65 seconds
Started May 28 01:10:47 PM PDT 24
Finished May 28 01:10:58 PM PDT 24
Peak memory 191820 kb
Host smart-6109a702-15fe-400e-b929-ac8710b974cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932369870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.932369870
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2888608230
Short name T17
Test name
Test status
Simulation time 8483915669 ps
CPU time 4.23 seconds
Started May 28 01:10:47 PM PDT 24
Finished May 28 01:10:55 PM PDT 24
Peak memory 215776 kb
Host smart-303c42c6-8cf6-44b6-a364-3d1e7b1fc37a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888608230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2888608230
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3020851592
Short name T29
Test name
Test status
Simulation time 435882621 ps
CPU time 0.93 seconds
Started May 28 01:10:49 PM PDT 24
Finished May 28 01:10:53 PM PDT 24
Peak memory 191708 kb
Host smart-d0daeac0-d282-4cb7-8005-16d0545b34f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020851592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3020851592
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3561300245
Short name T62
Test name
Test status
Simulation time 40007902815 ps
CPU time 16.62 seconds
Started May 28 01:11:21 PM PDT 24
Finished May 28 01:11:40 PM PDT 24
Peak memory 191820 kb
Host smart-9787be06-1959-4f22-b5b6-b93d581cc24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561300245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3561300245
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.772248333
Short name T230
Test name
Test status
Simulation time 472125888 ps
CPU time 0.77 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:32 PM PDT 24
Peak memory 191528 kb
Host smart-f4da2105-e4f9-4d40-8110-b35a5d427e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772248333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.772248333
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.4010021367
Short name T65
Test name
Test status
Simulation time 33303982311 ps
CPU time 8.71 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:39 PM PDT 24
Peak memory 191788 kb
Host smart-2fd3f718-697b-4dff-921b-d9e67066425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010021367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.4010021367
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3874169721
Short name T217
Test name
Test status
Simulation time 368911523 ps
CPU time 0.88 seconds
Started May 28 01:11:23 PM PDT 24
Finished May 28 01:11:30 PM PDT 24
Peak memory 196708 kb
Host smart-c9837c6b-5284-4190-ac6e-92015b1f96a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874169721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3874169721
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3030812706
Short name T262
Test name
Test status
Simulation time 5574992952 ps
CPU time 8.7 seconds
Started May 28 01:11:23 PM PDT 24
Finished May 28 01:11:35 PM PDT 24
Peak memory 191832 kb
Host smart-93fee684-21d8-43f5-bbc9-c1854f74ca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030812706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3030812706
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2870766134
Short name T267
Test name
Test status
Simulation time 445970028 ps
CPU time 0.73 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:11:36 PM PDT 24
Peak memory 191680 kb
Host smart-230e510d-b708-49b0-babd-8e6aac3dd5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870766134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2870766134
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3189153213
Short name T260
Test name
Test status
Simulation time 14538485489 ps
CPU time 4.55 seconds
Started May 28 01:11:20 PM PDT 24
Finished May 28 01:11:26 PM PDT 24
Peak memory 191828 kb
Host smart-134364b9-8c20-4b45-a52a-6666b9470ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189153213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3189153213
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3924030533
Short name T220
Test name
Test status
Simulation time 485497193 ps
CPU time 0.75 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:30 PM PDT 24
Peak memory 191792 kb
Host smart-2ae0e670-2283-4a2d-b2be-ab0d7461c612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924030533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3924030533
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.25102211
Short name T231
Test name
Test status
Simulation time 24906372961 ps
CPU time 9.49 seconds
Started May 28 01:11:23 PM PDT 24
Finished May 28 01:11:36 PM PDT 24
Peak memory 191904 kb
Host smart-9d1c7285-1319-4bae-8f1d-4ec8f9478b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25102211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.25102211
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2319945940
Short name T46
Test name
Test status
Simulation time 591558605 ps
CPU time 1.5 seconds
Started May 28 01:11:21 PM PDT 24
Finished May 28 01:11:24 PM PDT 24
Peak memory 191784 kb
Host smart-a6b9131e-7d86-4eb7-8482-63b58710de05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319945940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2319945940
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.906738318
Short name T212
Test name
Test status
Simulation time 57518247818 ps
CPU time 21.8 seconds
Started May 28 01:11:25 PM PDT 24
Finished May 28 01:11:54 PM PDT 24
Peak memory 191888 kb
Host smart-244ec404-9998-489a-94cd-d294bdc67f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906738318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.906738318
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1162295760
Short name T277
Test name
Test status
Simulation time 422540755 ps
CPU time 1.29 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:32 PM PDT 24
Peak memory 191788 kb
Host smart-228b588e-6f65-456e-897d-83faa228e1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162295760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1162295760
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2770405363
Short name T234
Test name
Test status
Simulation time 31833108584 ps
CPU time 43.68 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:12:13 PM PDT 24
Peak memory 191824 kb
Host smart-049e6dd9-133f-4ab2-8721-94365657eb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770405363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2770405363
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.208474606
Short name T239
Test name
Test status
Simulation time 605569050 ps
CPU time 1.1 seconds
Started May 28 01:11:25 PM PDT 24
Finished May 28 01:11:33 PM PDT 24
Peak memory 191656 kb
Host smart-ceaf3462-e2b5-4aae-96c5-f19b463b1cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208474606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.208474606
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2379656845
Short name T95
Test name
Test status
Simulation time 22905151834 ps
CPU time 36.84 seconds
Started May 28 01:11:25 PM PDT 24
Finished May 28 01:12:08 PM PDT 24
Peak memory 191864 kb
Host smart-09ced2fc-2cb8-47a5-a1ec-8c4b9b24a0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379656845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2379656845
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2588627018
Short name T94
Test name
Test status
Simulation time 453383821 ps
CPU time 0.73 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:32 PM PDT 24
Peak memory 191792 kb
Host smart-a95ad8c9-bebf-4f2d-8d68-bab97851fc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588627018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2588627018
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3232032813
Short name T205
Test name
Test status
Simulation time 30071711835 ps
CPU time 10.13 seconds
Started May 28 01:11:25 PM PDT 24
Finished May 28 01:11:43 PM PDT 24
Peak memory 191816 kb
Host smart-6a7027dd-a6a6-418e-91a1-1fe149b87899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232032813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3232032813
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2335766793
Short name T70
Test name
Test status
Simulation time 31106534258 ps
CPU time 9.53 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:40 PM PDT 24
Peak memory 191816 kb
Host smart-92ba7351-fd9a-4ef4-842a-82c848376a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335766793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2335766793
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3786718944
Short name T241
Test name
Test status
Simulation time 591625916 ps
CPU time 0.81 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:11:36 PM PDT 24
Peak memory 191616 kb
Host smart-c9b40be9-a671-48b3-8c0e-c6aa37baa825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786718944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3786718944
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2053272709
Short name T27
Test name
Test status
Simulation time 426331544 ps
CPU time 0.8 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:32 PM PDT 24
Peak memory 196356 kb
Host smart-ae263387-7ab9-4600-8a61-abe21f438d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053272709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2053272709
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1602642795
Short name T282
Test name
Test status
Simulation time 18471278839 ps
CPU time 18.22 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:50 PM PDT 24
Peak memory 191896 kb
Host smart-e8f53d2d-bae4-43a5-86fe-da5fe43b37cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602642795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1602642795
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2138255883
Short name T30
Test name
Test status
Simulation time 478634958 ps
CPU time 1.31 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:11:36 PM PDT 24
Peak memory 191696 kb
Host smart-6535b5ad-6354-4ba1-b716-0a2f280ff69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138255883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2138255883
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.803114177
Short name T281
Test name
Test status
Simulation time 4509424066 ps
CPU time 2.37 seconds
Started May 28 01:10:47 PM PDT 24
Finished May 28 01:10:52 PM PDT 24
Peak memory 191908 kb
Host smart-5273dd1c-1c25-44ba-80dc-308ba437e6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803114177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.803114177
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1816522774
Short name T242
Test name
Test status
Simulation time 482175118 ps
CPU time 0.72 seconds
Started May 28 01:10:53 PM PDT 24
Finished May 28 01:10:56 PM PDT 24
Peak memory 191708 kb
Host smart-5d9441c7-301f-4eac-b807-c1c2f35f9050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816522774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1816522774
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3679892488
Short name T189
Test name
Test status
Simulation time 525582149 ps
CPU time 0.79 seconds
Started May 28 01:10:50 PM PDT 24
Finished May 28 01:10:54 PM PDT 24
Peak memory 196316 kb
Host smart-2ad956da-8ee9-4657-907d-806f0d99a13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679892488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3679892488
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3221925499
Short name T4
Test name
Test status
Simulation time 14011657677 ps
CPU time 5.6 seconds
Started May 28 01:10:46 PM PDT 24
Finished May 28 01:10:56 PM PDT 24
Peak memory 191912 kb
Host smart-d7ef71e5-ff61-4015-a98a-bafbba144fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221925499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3221925499
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1560053667
Short name T229
Test name
Test status
Simulation time 587819015 ps
CPU time 0.94 seconds
Started May 28 01:10:38 PM PDT 24
Finished May 28 01:10:43 PM PDT 24
Peak memory 191716 kb
Host smart-51343a12-0bf1-4d7a-97ee-b19deaee109b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560053667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1560053667
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.4172981533
Short name T273
Test name
Test status
Simulation time 36226348248 ps
CPU time 64.13 seconds
Started May 28 01:10:42 PM PDT 24
Finished May 28 01:11:50 PM PDT 24
Peak memory 191912 kb
Host smart-6b15a637-48b5-4646-abca-b336bb12174b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172981533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.4172981533
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3515220799
Short name T268
Test name
Test status
Simulation time 617024411 ps
CPU time 0.85 seconds
Started May 28 01:10:48 PM PDT 24
Finished May 28 01:10:53 PM PDT 24
Peak memory 191756 kb
Host smart-990768d6-21e4-4f4c-b17d-b6ca18e15caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515220799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3515220799
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1207219868
Short name T232
Test name
Test status
Simulation time 7177203564 ps
CPU time 5.56 seconds
Started May 28 01:11:01 PM PDT 24
Finished May 28 01:11:10 PM PDT 24
Peak memory 191876 kb
Host smart-378deff6-ad4e-4bec-bec9-8d8f840d796f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207219868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1207219868
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3709416416
Short name T219
Test name
Test status
Simulation time 612232252 ps
CPU time 0.82 seconds
Started May 28 01:10:58 PM PDT 24
Finished May 28 01:11:01 PM PDT 24
Peak memory 191704 kb
Host smart-0fea584f-a9a1-4086-bb22-54f9c01cd4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709416416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3709416416
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3294685732
Short name T10
Test name
Test status
Simulation time 30699081744 ps
CPU time 12.81 seconds
Started May 28 01:10:46 PM PDT 24
Finished May 28 01:11:02 PM PDT 24
Peak memory 191908 kb
Host smart-c5f5c463-b0ec-4d43-b282-49387f0be423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294685732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3294685732
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2150991125
Short name T276
Test name
Test status
Simulation time 551054998 ps
CPU time 1.02 seconds
Started May 28 01:10:59 PM PDT 24
Finished May 28 01:11:03 PM PDT 24
Peak memory 191712 kb
Host smart-b6ba64a2-55aa-4512-be68-568c0ee31676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150991125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2150991125
Directory /workspace/9.aon_timer_smoke/latest
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