Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.11 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 5 168 97.11


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 31107 1 T2 11 T3 1023 T4 12
bark[1] 672 1 T11 53 T29 53 T39 65
bark[2] 478 1 T152 30 T123 14 T78 21
bark[3] 194 1 T3 21 T5 26 T20 21
bark[4] 1297 1 T3 21 T39 229 T21 21
bark[5] 193 1 T101 14 T104 26 T106 21
bark[6] 248 1 T43 21 T96 14 T143 21
bark[7] 205 1 T27 14 T129 60 T111 21
bark[8] 459 1 T120 21 T104 62 T78 47
bark[9] 254 1 T5 7 T6 14 T20 21
bark[10] 1008 1 T9 21 T29 55 T96 21
bark[11] 2175 1 T7 1415 T10 42 T43 21
bark[12] 843 1 T11 28 T38 21 T30 14
bark[13] 82 1 T120 21 T121 14 T82 26
bark[14] 473 1 T28 21 T152 21 T169 47
bark[15] 777 1 T43 40 T102 21 T104 26
bark[16] 87 1 T39 21 T121 45 T107 21
bark[17] 280 1 T12 83 T38 21 T39 21
bark[18] 618 1 T1 14 T10 21 T30 21
bark[19] 336 1 T28 52 T87 96 T77 21
bark[20] 797 1 T29 21 T30 84 T43 21
bark[21] 321 1 T38 77 T122 102 T77 44
bark[22] 569 1 T8 148 T89 21 T140 14
bark[23] 326 1 T127 14 T125 26 T111 44
bark[24] 867 1 T142 14 T129 14 T136 536
bark[25] 700 1 T145 14 T99 21 T133 58
bark[26] 385 1 T5 201 T44 14 T71 21
bark[27] 358 1 T39 235 T102 39 T136 21
bark[28] 1083 1 T40 184 T136 21 T126 158
bark[29] 119 1 T36 14 T123 21 T133 7
bark[30] 830 1 T30 21 T102 54 T187 14
bark[31] 360 1 T9 21 T11 21 T143 21
bark_0 4379 1 T1 7 T2 7 T3 87


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 31040 1 T1 13 T2 10 T3 950
bite[1] 638 1 T11 21 T89 21 T123 21
bite[2] 132 1 T117 13 T126 21 T100 77
bite[3] 329 1 T39 21 T40 183 T96 21
bite[4] 670 1 T12 82 T99 21 T79 268
bite[5] 609 1 T10 21 T30 63 T20 21
bite[6] 419 1 T87 63 T79 61 T136 21
bite[7] 269 1 T38 64 T21 21 T108 13
bite[8] 440 1 T71 21 T122 81 T79 171
bite[9] 480 1 T5 6 T30 13 T96 13
bite[10] 1680 1 T3 21 T7 1414 T11 53
bite[11] 450 1 T38 21 T43 21 T133 57
bite[12] 635 1 T136 50 T172 13 T119 13
bite[13] 518 1 T43 39 T122 21 T99 13
bite[14] 452 1 T29 27 T43 21 T71 21
bite[15] 832 1 T39 462 T122 21 T120 21
bite[16] 192 1 T19 21 T22 4 T142 13
bite[17] 280 1 T143 21 T133 73 T78 30
bite[18] 861 1 T71 139 T87 21 T176 13
bite[19] 515 1 T9 21 T28 21 T30 21
bite[20] 433 1 T3 21 T9 21 T102 40
bite[21] 799 1 T30 21 T123 13 T133 6
bite[22] 270 1 T43 21 T20 21 T187 13
bite[23] 577 1 T71 21 T102 13 T140 13
bite[24] 347 1 T11 27 T44 13 T36 13
bite[25] 793 1 T8 147 T39 21 T18 13
bite[26] 584 1 T27 13 T29 21 T125 46
bite[27] 705 1 T6 13 T39 64 T43 21
bite[28] 229 1 T30 21 T117 63 T131 13
bite[29] 666 1 T5 225 T30 21 T154 13
bite[30] 754 1 T3 64 T104 62 T180 21
bite[31] 401 1 T10 42 T28 51 T29 52
bite_0 4881 1 T1 8 T2 8 T3 96


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 52880 1 T1 21 T2 18 T3 1152


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1445 1 T7 151 T8 79 T29 37
prescale[1] 1810 1 T5 67 T7 51 T8 24
prescale[2] 687 1 T7 58 T29 9 T43 19
prescale[3] 1025 1 T3 2 T8 28 T9 29
prescale[4] 1525 1 T3 133 T7 131 T8 19
prescale[5] 1222 1 T7 77 T10 28 T89 19
prescale[6] 687 1 T3 4 T7 139 T29 2
prescale[7] 500 1 T7 19 T38 19 T71 19
prescale[8] 815 1 T3 72 T7 19 T8 19
prescale[9] 951 1 T7 135 T38 63 T39 19
prescale[10] 918 1 T3 83 T9 23 T28 19
prescale[11] 859 1 T8 2 T9 19 T29 49
prescale[12] 1212 1 T3 40 T7 33 T8 20
prescale[13] 761 1 T7 28 T89 9 T71 19
prescale[14] 575 1 T7 40 T9 37 T12 19
prescale[15] 561 1 T5 2 T7 74 T10 28
prescale[16] 940 1 T3 85 T7 244 T12 19
prescale[17] 807 1 T5 177 T8 22 T29 2
prescale[18] 529 1 T5 2 T7 126 T89 28
prescale[19] 666 1 T7 19 T9 23 T39 103
prescale[20] 768 1 T3 51 T10 19 T12 64
prescale[21] 745 1 T3 2 T7 19 T11 60
prescale[22] 820 1 T3 142 T8 2 T9 19
prescale[23] 1374 1 T3 24 T7 19 T9 19
prescale[24] 855 1 T3 48 T7 40 T9 19
prescale[25] 640 1 T7 40 T38 53 T22 2
prescale[26] 505 1 T7 37 T12 14 T39 2
prescale[27] 612 1 T42 9 T40 2 T20 32
prescale[28] 918 1 T3 2 T4 9 T7 19
prescale[29] 1008 1 T9 19 T12 19 T30 76
prescale[30] 493 1 T3 2 T5 2 T10 19
prescale[31] 977 1 T7 2 T28 28 T29 66
prescale_0 24670 1 T1 21 T2 18 T3 462


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 40274 1 T1 9 T2 18 T3 1008
auto[1] 12606 1 T1 12 T3 144 T5 85


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 52880 1 T1 21 T2 18 T3 1152


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 31140 1 T1 1 T2 13 T3 621
wkup[1] 430 1 T12 21 T44 15 T29 21
wkup[2] 300 1 T3 21 T11 21 T39 21
wkup[3] 226 1 T20 21 T71 21 T129 21
wkup[4] 315 1 T28 30 T71 21 T123 26
wkup[5] 167 1 T7 21 T79 21 T126 47
wkup[6] 242 1 T30 21 T39 21 T78 21
wkup[7] 324 1 T29 30 T104 26 T99 21
wkup[8] 343 1 T38 21 T21 21 T79 21
wkup[9] 222 1 T1 15 T7 21 T96 15
wkup[10] 338 1 T3 21 T7 42 T39 42
wkup[11] 113 1 T22 6 T133 21 T72 21
wkup[12] 421 1 T5 8 T7 21 T152 21
wkup[13] 294 1 T7 35 T29 42 T133 21
wkup[14] 375 1 T5 30 T38 15 T43 21
wkup[15] 403 1 T5 21 T8 21 T12 30
wkup[16] 404 1 T7 21 T38 21 T152 21
wkup[17] 128 1 T7 26 T107 21 T81 30
wkup[18] 226 1 T28 21 T18 15 T143 21
wkup[19] 220 1 T71 39 T123 21 T72 21
wkup[20] 368 1 T29 30 T39 21 T161 15
wkup[21] 318 1 T29 21 T39 21 T20 21
wkup[22] 228 1 T3 21 T7 30 T122 21
wkup[23] 333 1 T3 42 T40 42 T136 21
wkup[24] 99 1 T11 21 T38 21 T77 21
wkup[25] 377 1 T29 35 T39 42 T43 21
wkup[26] 240 1 T7 21 T78 21 T136 6
wkup[27] 215 1 T29 8 T71 21 T169 21
wkup[28] 268 1 T27 15 T78 21 T72 42
wkup[29] 228 1 T30 21 T127 15 T79 21
wkup[30] 216 1 T12 21 T39 21 T43 15
wkup[31] 212 1 T3 21 T5 21 T9 21
wkup[32] 358 1 T38 21 T133 21 T136 30
wkup[33] 345 1 T7 19 T30 21 T71 30
wkup[34] 297 1 T3 21 T29 21 T40 21
wkup[35] 295 1 T102 21 T169 21 T184 21
wkup[36] 289 1 T3 21 T71 21 T123 21
wkup[37] 369 1 T10 21 T39 39 T142 15
wkup[38] 272 1 T28 21 T122 21 T87 21
wkup[39] 167 1 T89 21 T77 35 T144 21
wkup[40] 344 1 T3 42 T176 15 T79 21
wkup[41] 298 1 T3 21 T5 21 T7 21
wkup[42] 274 1 T3 21 T7 56 T9 21
wkup[43] 385 1 T39 47 T117 21 T136 77
wkup[44] 215 1 T10 42 T12 21 T29 26
wkup[45] 179 1 T6 15 T38 21 T39 42
wkup[46] 314 1 T38 21 T39 21 T21 42
wkup[47] 305 1 T7 21 T36 15 T136 63
wkup[48] 229 1 T7 47 T10 21 T30 21
wkup[49] 308 1 T3 60 T39 21 T102 15
wkup[50] 299 1 T3 21 T39 21 T40 21
wkup[51] 506 1 T3 42 T29 21 T40 26
wkup[52] 155 1 T39 15 T136 26 T72 21
wkup[53] 445 1 T39 47 T108 15 T104 26
wkup[54] 202 1 T19 21 T169 21 T77 44
wkup[55] 171 1 T3 21 T96 21 T79 15
wkup[56] 431 1 T7 42 T11 29 T19 30
wkup[57] 422 1 T3 30 T7 21 T39 21
wkup[58] 263 1 T40 8 T123 15 T77 30
wkup[59] 414 1 T3 15 T7 56 T39 21
wkup[60] 331 1 T89 21 T43 47 T71 8
wkup[61] 346 1 T39 21 T43 21 T21 21
wkup[62] 212 1 T3 21 T30 21 T39 21
wkup[63] 210 1 T101 15 T187 15 T79 21
wkup_0 3497 1 T1 5 T2 5 T3 69

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