| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 90.21 | 99.33 | 93.67 | 100.00 | 98.40 | 99.51 | 50.34 |
| T35 | /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3033522756 | May 30 02:55:35 PM PDT 24 | May 30 02:55:38 PM PDT 24 | 574364576 ps | ||
| T31 | /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3797859654 | May 30 02:55:05 PM PDT 24 | May 30 02:55:09 PM PDT 24 | 7969020011 ps | ||
| T288 | /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1859876614 | May 30 02:55:42 PM PDT 24 | May 30 02:55:45 PM PDT 24 | 303057287 ps | ||
| T32 | /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3220376099 | May 30 02:55:57 PM PDT 24 | May 30 02:56:01 PM PDT 24 | 532264446 ps | ||
| T33 | /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1957932372 | May 30 02:55:26 PM PDT 24 | May 30 02:55:31 PM PDT 24 | 4107902882 ps | ||
| T289 | /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1302389936 | May 30 02:55:55 PM PDT 24 | May 30 02:55:59 PM PDT 24 | 459779585 ps | ||
| T46 | /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2716731898 | May 30 02:55:45 PM PDT 24 | May 30 02:55:47 PM PDT 24 | 482350440 ps | ||
| T62 | /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3932046145 | May 30 02:54:53 PM PDT 24 | May 30 02:55:01 PM PDT 24 | 2108019381 ps | ||
| T290 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2320310402 | May 30 02:55:27 PM PDT 24 | May 30 02:55:29 PM PDT 24 | 385361327 ps | ||
| T291 | /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.755576297 | May 30 02:56:39 PM PDT 24 | May 30 02:56:41 PM PDT 24 | 323007256 ps | ||
| T47 | /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.637419864 | May 30 02:56:24 PM PDT 24 | May 30 02:56:27 PM PDT 24 | 415505498 ps | ||
| T63 | /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1491508082 | May 30 02:55:45 PM PDT 24 | May 30 02:55:50 PM PDT 24 | 1895151026 ps | ||
| T48 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.568400196 | May 30 02:55:25 PM PDT 24 | May 30 02:55:27 PM PDT 24 | 354856209 ps | ||
| T292 | /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1026407884 | May 30 02:56:09 PM PDT 24 | May 30 02:56:11 PM PDT 24 | 396838695 ps | ||
| T34 | /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1226082805 | May 30 02:55:57 PM PDT 24 | May 30 02:56:04 PM PDT 24 | 4417448048 ps | ||
| T293 | /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2182807571 | May 30 02:55:38 PM PDT 24 | May 30 02:55:41 PM PDT 24 | 480602820 ps | ||
| T294 | /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.64613689 | May 30 02:55:44 PM PDT 24 | May 30 02:55:46 PM PDT 24 | 419134126 ps | ||
| T295 | /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2163827380 | May 30 02:56:24 PM PDT 24 | May 30 02:56:27 PM PDT 24 | 280623861 ps | ||
| T296 | /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.401175471 | May 30 02:55:44 PM PDT 24 | May 30 02:55:47 PM PDT 24 | 482848396 ps | ||
| T297 | /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3175945383 | May 30 02:56:22 PM PDT 24 | May 30 02:56:24 PM PDT 24 | 488056024 ps | ||
| T298 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3740741251 | May 30 02:54:52 PM PDT 24 | May 30 02:54:54 PM PDT 24 | 298252471 ps | ||
| T194 | /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2614166723 | May 30 02:54:51 PM PDT 24 | May 30 02:55:04 PM PDT 24 | 8077803377 ps | ||
| T299 | /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3155054009 | May 30 02:56:24 PM PDT 24 | May 30 02:56:28 PM PDT 24 | 394109612 ps | ||
| T49 | /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.437413821 | May 30 02:55:46 PM PDT 24 | May 30 02:55:49 PM PDT 24 | 531118437 ps | ||
| T300 | /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4173481864 | May 30 02:56:12 PM PDT 24 | May 30 02:56:14 PM PDT 24 | 338542752 ps | ||
| T64 | /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1556912355 | May 30 02:55:36 PM PDT 24 | May 30 02:55:38 PM PDT 24 | 505130876 ps | ||
| T301 | /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.371222262 | May 30 02:55:37 PM PDT 24 | May 30 02:55:41 PM PDT 24 | 549001548 ps | ||
| T302 | /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.932232654 | May 30 02:55:44 PM PDT 24 | May 30 02:55:47 PM PDT 24 | 310691481 ps | ||
| T192 | /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3192016007 | May 30 02:55:37 PM PDT 24 | May 30 02:55:47 PM PDT 24 | 4487051332 ps | ||
| T303 | /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2169731397 | May 30 02:56:00 PM PDT 24 | May 30 02:56:02 PM PDT 24 | 354916437 ps | ||
| T65 | /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4082035350 | May 30 02:55:48 PM PDT 24 | May 30 02:55:52 PM PDT 24 | 2384807965 ps | ||
| T304 | /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1207205707 | May 30 02:56:22 PM PDT 24 | May 30 02:56:24 PM PDT 24 | 289230087 ps | ||
| T195 | /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3052720624 | May 30 02:56:22 PM PDT 24 | May 30 02:56:36 PM PDT 24 | 8204436328 ps | ||
| T66 | /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3843069469 | May 30 02:55:45 PM PDT 24 | May 30 02:55:48 PM PDT 24 | 974317199 ps | ||
| T305 | /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3088296412 | May 30 02:55:37 PM PDT 24 | May 30 02:55:40 PM PDT 24 | 597711209 ps | ||
| T306 | /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2345247017 | May 30 02:54:51 PM PDT 24 | May 30 02:54:53 PM PDT 24 | 278342432 ps | ||
| T67 | /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2854142853 | May 30 02:56:14 PM PDT 24 | May 30 02:56:18 PM PDT 24 | 3002410305 ps | ||
| T307 | /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3138472745 | May 30 02:55:57 PM PDT 24 | May 30 02:56:01 PM PDT 24 | 481780469 ps | ||
| T308 | /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3730085877 | May 30 02:55:45 PM PDT 24 | May 30 02:55:47 PM PDT 24 | 319968337 ps | ||
| T309 | /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2674172410 | May 30 02:56:39 PM PDT 24 | May 30 02:56:42 PM PDT 24 | 428445478 ps | ||
| T310 | /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3174309327 | May 30 02:56:22 PM PDT 24 | May 30 02:56:25 PM PDT 24 | 412396949 ps | ||
| T68 | /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.148196567 | May 30 02:56:23 PM PDT 24 | May 30 02:56:28 PM PDT 24 | 1412447664 ps | ||
| T311 | /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2740621946 | May 30 02:56:23 PM PDT 24 | May 30 02:56:26 PM PDT 24 | 386111139 ps | ||
| T312 | /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2652702632 | May 30 02:56:10 PM PDT 24 | May 30 02:56:15 PM PDT 24 | 4213290407 ps | ||
| T313 | /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.104580167 | May 30 02:55:44 PM PDT 24 | May 30 02:55:47 PM PDT 24 | 487539103 ps | ||
| T69 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3554408731 | May 30 02:55:27 PM PDT 24 | May 30 02:55:30 PM PDT 24 | 542096581 ps | ||
| T314 | /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1189832306 | May 30 02:55:38 PM PDT 24 | May 30 02:55:41 PM PDT 24 | 310321172 ps | ||
| T315 | /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3621782078 | May 30 02:56:26 PM PDT 24 | May 30 02:56:30 PM PDT 24 | 551246748 ps | ||
| T316 | /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1282578135 | May 30 02:56:13 PM PDT 24 | May 30 02:56:16 PM PDT 24 | 411849200 ps | ||
| T50 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.734200145 | May 30 02:54:51 PM PDT 24 | May 30 02:54:53 PM PDT 24 | 515361963 ps | ||
| T317 | /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2674122079 | May 30 02:56:22 PM PDT 24 | May 30 02:56:25 PM PDT 24 | 352914250 ps | ||
| T318 | /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2726986224 | May 30 02:56:21 PM PDT 24 | May 30 02:56:37 PM PDT 24 | 8325598451 ps | ||
| T51 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1370566077 | May 30 02:55:35 PM PDT 24 | May 30 02:55:38 PM PDT 24 | 448845291 ps | ||
| T319 | /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1223648091 | May 30 02:56:24 PM PDT 24 | May 30 02:56:27 PM PDT 24 | 367443905 ps | ||
| T320 | /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3694637699 | May 30 02:54:51 PM PDT 24 | May 30 02:54:53 PM PDT 24 | 296618515 ps | ||
| T321 | /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1772517856 | May 30 02:55:36 PM PDT 24 | May 30 02:55:40 PM PDT 24 | 4590338395 ps | ||
| T70 | /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3422012333 | May 30 02:55:56 PM PDT 24 | May 30 02:56:03 PM PDT 24 | 2535481789 ps | ||
| T322 | /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2928018686 | May 30 02:56:24 PM PDT 24 | May 30 02:56:27 PM PDT 24 | 384534211 ps | ||
| T323 | /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1098104342 | May 30 02:55:56 PM PDT 24 | May 30 02:55:59 PM PDT 24 | 567464659 ps | ||
| T324 | /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3397659720 | May 30 02:56:24 PM PDT 24 | May 30 02:56:28 PM PDT 24 | 489286604 ps | ||
| T325 | /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1042703714 | May 30 02:55:57 PM PDT 24 | May 30 02:56:00 PM PDT 24 | 347545015 ps | ||
| T326 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2388927482 | May 30 02:54:54 PM PDT 24 | May 30 02:54:57 PM PDT 24 | 691373758 ps | ||
| T327 | /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.354933844 | May 30 02:56:22 PM PDT 24 | May 30 02:56:26 PM PDT 24 | 481916495 ps | ||
| T328 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3929221350 | May 30 02:55:05 PM PDT 24 | May 30 02:55:07 PM PDT 24 | 828569910 ps | ||
| T52 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2389246062 | May 30 02:55:06 PM PDT 24 | May 30 02:55:08 PM PDT 24 | 524205945 ps | ||
| T329 | /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.221961327 | May 30 02:56:11 PM PDT 24 | May 30 02:56:14 PM PDT 24 | 2052420580 ps | ||
| T330 | /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.395543241 | May 30 02:55:28 PM PDT 24 | May 30 02:55:30 PM PDT 24 | 421968850 ps | ||
| T331 | /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2827387709 | May 30 02:56:40 PM PDT 24 | May 30 02:56:43 PM PDT 24 | 420069264 ps | ||
| T332 | /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1062781848 | May 30 02:56:21 PM PDT 24 | May 30 02:56:23 PM PDT 24 | 994898177 ps | ||
| T333 | /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4066294177 | May 30 02:56:11 PM PDT 24 | May 30 02:56:14 PM PDT 24 | 558729245 ps | ||
| T334 | /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.750406910 | May 30 02:56:21 PM PDT 24 | May 30 02:56:23 PM PDT 24 | 522011207 ps | ||
| T335 | /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1760033819 | May 30 02:56:21 PM PDT 24 | May 30 02:56:23 PM PDT 24 | 436709287 ps | ||
| T336 | /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.222147392 | May 30 02:55:45 PM PDT 24 | May 30 02:55:49 PM PDT 24 | 1335609822 ps | ||
| T337 | /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1888468381 | May 30 02:55:58 PM PDT 24 | May 30 02:56:01 PM PDT 24 | 393788688 ps | ||
| T338 | /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2945550221 | May 30 02:56:24 PM PDT 24 | May 30 02:56:27 PM PDT 24 | 500897265 ps | ||
| T339 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1743071244 | May 30 02:55:06 PM PDT 24 | May 30 02:55:08 PM PDT 24 | 996792666 ps | ||
| T340 | /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4294501440 | May 30 02:56:26 PM PDT 24 | May 30 02:56:29 PM PDT 24 | 391631457 ps | ||
| T341 | /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1874286316 | May 30 02:55:35 PM PDT 24 | May 30 02:55:39 PM PDT 24 | 529347971 ps | ||
| T342 | /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2335026143 | May 30 02:55:04 PM PDT 24 | May 30 02:55:06 PM PDT 24 | 377762353 ps | ||
| T189 | /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.616398510 | May 30 02:55:59 PM PDT 24 | May 30 02:56:06 PM PDT 24 | 8269319201 ps | ||
| T55 | /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1865683599 | May 30 02:56:13 PM PDT 24 | May 30 02:56:16 PM PDT 24 | 453125755 ps | ||
| T343 | /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1870105325 | May 30 02:55:06 PM PDT 24 | May 30 02:55:09 PM PDT 24 | 1240236902 ps | ||
| T344 | /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2982312895 | May 30 02:55:57 PM PDT 24 | May 30 02:56:01 PM PDT 24 | 541620964 ps | ||
| T193 | /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1456110137 | May 30 02:56:13 PM PDT 24 | May 30 02:56:22 PM PDT 24 | 4179380957 ps | ||
| T345 | /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3027483208 | May 30 02:55:44 PM PDT 24 | May 30 02:55:51 PM PDT 24 | 4224216220 ps | ||
| T346 | /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4250405766 | May 30 02:56:12 PM PDT 24 | May 30 02:56:15 PM PDT 24 | 436444214 ps | ||
| T347 | /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.46323711 | May 30 02:56:21 PM PDT 24 | May 30 02:56:24 PM PDT 24 | 869025032 ps | ||
| T61 | /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.858862251 | May 30 02:56:12 PM PDT 24 | May 30 02:56:14 PM PDT 24 | 533953654 ps | ||
| T348 | /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1675990628 | May 30 02:56:22 PM PDT 24 | May 30 02:56:25 PM PDT 24 | 406052306 ps | ||
| T349 | /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.658898063 | May 30 02:55:27 PM PDT 24 | May 30 02:55:31 PM PDT 24 | 452915959 ps | ||
| T350 | /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1158830369 | May 30 02:55:05 PM PDT 24 | May 30 02:55:07 PM PDT 24 | 353739387 ps | ||
| T351 | /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.942326150 | May 30 02:55:45 PM PDT 24 | May 30 02:55:48 PM PDT 24 | 652486089 ps | ||
| T352 | /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4161872914 | May 30 02:55:48 PM PDT 24 | May 30 02:55:50 PM PDT 24 | 438353016 ps | ||
| T56 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2985657632 | May 30 02:55:26 PM PDT 24 | May 30 02:55:29 PM PDT 24 | 1142493245 ps | ||
| T353 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.820310043 | May 30 02:55:06 PM PDT 24 | May 30 02:55:08 PM PDT 24 | 338632459 ps | ||
| T57 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1470380385 | May 30 02:55:05 PM PDT 24 | May 30 02:55:27 PM PDT 24 | 7337178704 ps | ||
| T354 | /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.516649462 | May 30 02:54:52 PM PDT 24 | May 30 02:54:55 PM PDT 24 | 493048425 ps | ||
| T355 | /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3930708443 | May 30 02:56:11 PM PDT 24 | May 30 02:56:14 PM PDT 24 | 572797429 ps | ||
| T190 | /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3083378828 | May 30 02:55:58 PM PDT 24 | May 30 02:56:08 PM PDT 24 | 4513322945 ps | ||
| T356 | /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2005496199 | May 30 02:55:25 PM PDT 24 | May 30 02:55:27 PM PDT 24 | 512882801 ps | ||
| T357 | /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3296567236 | May 30 02:55:26 PM PDT 24 | May 30 02:55:34 PM PDT 24 | 4235050169 ps | ||
| T358 | /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1598592270 | May 30 02:56:24 PM PDT 24 | May 30 02:56:27 PM PDT 24 | 285616934 ps | ||
| T359 | /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1143752991 | May 30 02:55:55 PM PDT 24 | May 30 02:56:00 PM PDT 24 | 467879121 ps | ||
| T360 | /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.561284665 | May 30 02:56:13 PM PDT 24 | May 30 02:56:16 PM PDT 24 | 876006355 ps | ||
| T361 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4229525157 | May 30 02:54:51 PM PDT 24 | May 30 02:54:54 PM PDT 24 | 461644274 ps | ||
| T362 | /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1251017495 | May 30 02:56:12 PM PDT 24 | May 30 02:56:14 PM PDT 24 | 405693788 ps | ||
| T363 | /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2636080686 | May 30 02:55:05 PM PDT 24 | May 30 02:55:07 PM PDT 24 | 446281455 ps | ||
| T364 | /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2564121302 | May 30 02:56:22 PM PDT 24 | May 30 02:56:25 PM PDT 24 | 324639239 ps | ||
| T58 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3067926643 | May 30 02:55:08 PM PDT 24 | May 30 02:55:10 PM PDT 24 | 455886144 ps | ||
| T365 | /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.70398765 | May 30 02:56:14 PM PDT 24 | May 30 02:56:17 PM PDT 24 | 448628369 ps | ||
| T366 | /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.594050366 | May 30 02:55:26 PM PDT 24 | May 30 02:55:28 PM PDT 24 | 1502698891 ps | ||
| T367 | /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1060307048 | May 30 02:56:38 PM PDT 24 | May 30 02:56:40 PM PDT 24 | 507185844 ps | ||
| T368 | /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1041749782 | May 30 02:56:39 PM PDT 24 | May 30 02:56:41 PM PDT 24 | 399025809 ps | ||
| T369 | /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4049856396 | May 30 02:56:11 PM PDT 24 | May 30 02:56:14 PM PDT 24 | 4188198433 ps | ||
| T370 | /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4083138200 | May 30 02:56:24 PM PDT 24 | May 30 02:56:27 PM PDT 24 | 306108504 ps | ||
| T371 | /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3613360146 | May 30 02:56:24 PM PDT 24 | May 30 02:56:27 PM PDT 24 | 333358379 ps | ||
| T372 | /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2657979907 | May 30 02:54:51 PM PDT 24 | May 30 02:54:53 PM PDT 24 | 464019128 ps | ||
| T373 | /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1740130836 | May 30 02:55:45 PM PDT 24 | May 30 02:55:48 PM PDT 24 | 551234782 ps | ||
| T374 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1572519405 | May 30 02:55:35 PM PDT 24 | May 30 02:55:37 PM PDT 24 | 429612059 ps | ||
| T375 | /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2590194056 | May 30 02:55:45 PM PDT 24 | May 30 02:55:48 PM PDT 24 | 304856668 ps | ||
| T376 | /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1957943974 | May 30 02:55:35 PM PDT 24 | May 30 02:55:38 PM PDT 24 | 292259100 ps | ||
| T377 | /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1224368099 | May 30 02:55:37 PM PDT 24 | May 30 02:55:47 PM PDT 24 | 4235445802 ps | ||
| T378 | /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3641689172 | May 30 02:55:07 PM PDT 24 | May 30 02:55:09 PM PDT 24 | 435224063 ps | ||
| T379 | /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.224066018 | May 30 02:55:06 PM PDT 24 | May 30 02:55:08 PM PDT 24 | 393307081 ps | ||
| T380 | /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3426605541 | May 30 02:55:45 PM PDT 24 | May 30 02:55:49 PM PDT 24 | 410630517 ps | ||
| T381 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.262988089 | May 30 02:55:25 PM PDT 24 | May 30 02:55:27 PM PDT 24 | 534773400 ps | ||
| T382 | /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.12752229 | May 30 02:56:41 PM PDT 24 | May 30 02:56:43 PM PDT 24 | 291189343 ps | ||
| T383 | /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.950849246 | May 30 02:56:13 PM PDT 24 | May 30 02:56:15 PM PDT 24 | 345228500 ps | ||
| T59 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3788260423 | May 30 02:55:35 PM PDT 24 | May 30 02:55:39 PM PDT 24 | 500504462 ps | ||
| T384 | /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3151246008 | May 30 02:55:58 PM PDT 24 | May 30 02:56:03 PM PDT 24 | 407908130 ps | ||
| T385 | /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.100321338 | May 30 02:55:26 PM PDT 24 | May 30 02:55:28 PM PDT 24 | 413654886 ps | ||
| T386 | /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1286465445 | May 30 02:55:25 PM PDT 24 | May 30 02:55:27 PM PDT 24 | 493780492 ps | ||
| T387 | /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.747572581 | May 30 02:55:38 PM PDT 24 | May 30 02:55:42 PM PDT 24 | 2508037053 ps | ||
| T388 | /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.127880523 | May 30 02:55:59 PM PDT 24 | May 30 02:56:08 PM PDT 24 | 3852327658 ps | ||
| T60 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3966384619 | May 30 02:55:27 PM PDT 24 | May 30 02:55:38 PM PDT 24 | 6921118115 ps | ||
| T389 | /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3952825848 | May 30 02:56:21 PM PDT 24 | May 30 02:56:23 PM PDT 24 | 533585124 ps | ||
| T390 | /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2730229255 | May 30 02:56:13 PM PDT 24 | May 30 02:56:16 PM PDT 24 | 3076664354 ps | ||
| T391 | /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3319602214 | May 30 02:56:23 PM PDT 24 | May 30 02:56:26 PM PDT 24 | 416194991 ps | ||
| T392 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.447690548 | May 30 02:55:35 PM PDT 24 | May 30 02:55:48 PM PDT 24 | 7121461731 ps | ||
| T393 | /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1201917365 | May 30 02:55:56 PM PDT 24 | May 30 02:55:59 PM PDT 24 | 432685794 ps | ||
| T394 | /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3091101949 | May 30 02:56:12 PM PDT 24 | May 30 02:56:14 PM PDT 24 | 304766492 ps | ||
| T395 | /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2280127412 | May 30 02:55:57 PM PDT 24 | May 30 02:56:01 PM PDT 24 | 382994478 ps | ||
| T396 | /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.327997228 | May 30 02:55:44 PM PDT 24 | May 30 02:55:47 PM PDT 24 | 472118162 ps | ||
| T397 | /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4177963023 | May 30 02:55:28 PM PDT 24 | May 30 02:55:30 PM PDT 24 | 272696958 ps | ||
| T398 | /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2802447372 | May 30 02:55:57 PM PDT 24 | May 30 02:56:03 PM PDT 24 | 2445243489 ps | ||
| T53 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3502356831 | May 30 02:54:53 PM PDT 24 | May 30 02:55:00 PM PDT 24 | 1116134239 ps | ||
| T399 | /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1949288257 | May 30 02:55:05 PM PDT 24 | May 30 02:55:08 PM PDT 24 | 503652506 ps | ||
| T400 | /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3950137083 | May 30 02:55:26 PM PDT 24 | May 30 02:55:28 PM PDT 24 | 336590561 ps | ||
| T401 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4233576981 | May 30 02:55:28 PM PDT 24 | May 30 02:55:30 PM PDT 24 | 562542034 ps | ||
| T402 | /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2453630368 | May 30 02:54:54 PM PDT 24 | May 30 02:55:03 PM PDT 24 | 4281229676 ps | ||
| T403 | /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3692448885 | May 30 02:54:50 PM PDT 24 | May 30 02:54:54 PM PDT 24 | 663685868 ps | ||
| T54 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.850289247 | May 30 02:55:09 PM PDT 24 | May 30 02:55:16 PM PDT 24 | 3219434994 ps | ||
| T404 | /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.506262271 | May 30 02:55:36 PM PDT 24 | May 30 02:55:40 PM PDT 24 | 492684906 ps | ||
| T405 | /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3384769762 | May 30 02:56:23 PM PDT 24 | May 30 02:56:26 PM PDT 24 | 461465882 ps | ||
| T406 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.921226179 | May 30 02:55:35 PM PDT 24 | May 30 02:55:39 PM PDT 24 | 863408898 ps | ||
| T407 | /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3836440890 | May 30 02:55:37 PM PDT 24 | May 30 02:55:41 PM PDT 24 | 486986611 ps | ||
| T408 | /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.912253841 | May 30 02:56:22 PM PDT 24 | May 30 02:56:24 PM PDT 24 | 377015818 ps | ||
| T409 | /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3041547918 | May 30 02:56:11 PM PDT 24 | May 30 02:56:14 PM PDT 24 | 416711184 ps | ||
| T410 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2957640013 | May 30 02:55:06 PM PDT 24 | May 30 02:55:08 PM PDT 24 | 446540440 ps | ||
| T411 | /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3064995160 | May 30 02:55:45 PM PDT 24 | May 30 02:55:51 PM PDT 24 | 8201007758 ps | ||
| T191 | /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2654064226 | May 30 02:55:44 PM PDT 24 | May 30 02:55:49 PM PDT 24 | 3965540914 ps | ||
| T412 | /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2705795090 | May 30 02:56:23 PM PDT 24 | May 30 02:56:26 PM PDT 24 | 474624903 ps | ||
| T413 | /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3389405911 | May 30 02:56:26 PM PDT 24 | May 30 02:56:30 PM PDT 24 | 548650791 ps | ||
| T414 | /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3828582298 | May 30 02:55:58 PM PDT 24 | May 30 02:56:02 PM PDT 24 | 1207890952 ps | ||
| T415 | /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1588189172 | May 30 02:55:56 PM PDT 24 | May 30 02:55:59 PM PDT 24 | 517151652 ps | ||
| T416 | /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4221571298 | May 30 02:55:28 PM PDT 24 | May 30 02:55:30 PM PDT 24 | 538106795 ps | ||
| T417 | /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3862665140 | May 30 02:55:37 PM PDT 24 | May 30 02:55:42 PM PDT 24 | 1416203811 ps | ||
| T418 | /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3011200198 | May 30 02:55:05 PM PDT 24 | May 30 02:55:07 PM PDT 24 | 456402576 ps | ||
| T419 | /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3212679511 | May 30 02:55:35 PM PDT 24 | May 30 02:55:42 PM PDT 24 | 2050152544 ps | ||
| T420 | /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3574367077 | May 30 02:55:27 PM PDT 24 | May 30 02:55:31 PM PDT 24 | 2294160537 ps | ||
| T421 | /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.680375249 | May 30 02:55:59 PM PDT 24 | May 30 02:56:03 PM PDT 24 | 546225640 ps | ||
| T422 | /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2976950712 | May 30 02:56:24 PM PDT 24 | May 30 02:56:27 PM PDT 24 | 483448840 ps | ||
| T423 | /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3142027683 | May 30 02:56:13 PM PDT 24 | May 30 02:56:16 PM PDT 24 | 773895022 ps |
| Test location | /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1866626679 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 160620855144 ps |
| CPU time | 1231.21 seconds |
| Started | May 30 02:49:12 PM PDT 24 |
| Finished | May 30 03:09:46 PM PDT 24 |
| Peak memory | 212848 kb |
| Host | smart-43b92ff1-f68c-49f6-b097-96f674bccf19 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866626679 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1866626679 |
| Directory | /workspace/29.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.aon_timer_stress_all.3291208354 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 44129825919 ps |
| CPU time | 28.51 seconds |
| Started | May 30 02:49:18 PM PDT 24 |
| Finished | May 30 02:49:48 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-a3361129-b7b6-4e0d-86f1-f77657364757 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291208354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_ all.3291208354 |
| Directory | /workspace/33.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3797859654 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7969020011 ps |
| CPU time | 3.15 seconds |
| Started | May 30 02:55:05 PM PDT 24 |
| Finished | May 30 02:55:09 PM PDT 24 |
| Peak memory | 197944 kb |
| Host | smart-b81b0372-8589-4878-9197-c7ab2ea099ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797859654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl _intg_err.3797859654 |
| Directory | /workspace/2.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2461249075 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 437733570469 ps |
| CPU time | 439.33 seconds |
| Started | May 30 02:48:51 PM PDT 24 |
| Finished | May 30 02:56:14 PM PDT 24 |
| Peak memory | 211036 kb |
| Host | smart-07607b4e-ebef-4c45-b9be-cc8a35d823e9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461249075 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2461249075 |
| Directory | /workspace/5.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2016855888 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 86746360987 ps |
| CPU time | 369.38 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:55:06 PM PDT 24 |
| Peak memory | 210440 kb |
| Host | smart-6c55875f-96cd-41db-a9d7-bb9a0d72b39c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016855888 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2016855888 |
| Directory | /workspace/8.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3548451901 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 168503236999 ps |
| CPU time | 439.26 seconds |
| Started | May 30 02:48:30 PM PDT 24 |
| Finished | May 30 02:55:52 PM PDT 24 |
| Peak memory | 206828 kb |
| Host | smart-b71b3581-d766-48a3-aa3d-0f45af9480d5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548451901 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3548451901 |
| Directory | /workspace/0.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.680158210 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 144852933204 ps |
| CPU time | 616.45 seconds |
| Started | May 30 02:49:17 PM PDT 24 |
| Finished | May 30 02:59:36 PM PDT 24 |
| Peak memory | 205476 kb |
| Host | smart-f0d3d89e-0afc-4b43-9b46-1a655b9e503c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680158210 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.680158210 |
| Directory | /workspace/31.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.4262206652 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 393204315462 ps |
| CPU time | 683.46 seconds |
| Started | May 30 02:49:12 PM PDT 24 |
| Finished | May 30 03:00:39 PM PDT 24 |
| Peak memory | 207212 kb |
| Host | smart-78c6ca5f-a0b4-48ee-a859-f8d2459cb234 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262206652 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.4262206652 |
| Directory | /workspace/28.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3945687007 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 117400605148 ps |
| CPU time | 228.7 seconds |
| Started | May 30 02:49:24 PM PDT 24 |
| Finished | May 30 02:53:15 PM PDT 24 |
| Peak memory | 208744 kb |
| Host | smart-71888a8f-6a4c-479e-aafe-48b778a8bc71 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945687007 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3945687007 |
| Directory | /workspace/39.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1784046378 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 535150300417 ps |
| CPU time | 424.96 seconds |
| Started | May 30 02:49:20 PM PDT 24 |
| Finished | May 30 02:56:28 PM PDT 24 |
| Peak memory | 203328 kb |
| Host | smart-5aa6ebd7-4273-4221-974b-94b1194a9e72 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784046378 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1784046378 |
| Directory | /workspace/32.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1718636260 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 51215064244 ps |
| CPU time | 367.68 seconds |
| Started | May 30 02:49:20 PM PDT 24 |
| Finished | May 30 02:55:30 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-084159bb-2888-4053-89e7-a60bdfb128ef |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718636260 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1718636260 |
| Directory | /workspace/40.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.aon_timer_sec_cm.2503184107 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4304380519 ps |
| CPU time | 2.5 seconds |
| Started | May 30 02:48:30 PM PDT 24 |
| Finished | May 30 02:48:34 PM PDT 24 |
| Peak memory | 215756 kb |
| Host | smart-21a6abd7-8cf3-4797-bad5-2bd7cc631ab0 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503184107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2503184107 |
| Directory | /workspace/1.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/8.aon_timer_stress_all.4260231913 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 120598019736 ps |
| CPU time | 42.34 seconds |
| Started | May 30 02:48:53 PM PDT 24 |
| Finished | May 30 02:49:39 PM PDT 24 |
| Peak memory | 193016 kb |
| Host | smart-c72a18c3-4d3a-4f2c-98a5-dd92e3a996e9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260231913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a ll.4260231913 |
| Directory | /workspace/8.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.aon_timer_stress_all.2249150390 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 42251975958 ps |
| CPU time | 17.82 seconds |
| Started | May 30 02:49:29 PM PDT 24 |
| Finished | May 30 02:49:49 PM PDT 24 |
| Peak memory | 192812 kb |
| Host | smart-bbd9b6db-8559-4049-9c5e-c5e28e52c4f2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249150390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_ all.2249150390 |
| Directory | /workspace/37.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2962269838 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 147466570587 ps |
| CPU time | 839.85 seconds |
| Started | May 30 02:49:29 PM PDT 24 |
| Finished | May 30 03:03:32 PM PDT 24 |
| Peak memory | 208376 kb |
| Host | smart-3aa4e117-8983-4693-b2cd-714b9381bcfd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962269838 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2962269838 |
| Directory | /workspace/48.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.aon_timer_stress_all.196915963 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 32035732939 ps |
| CPU time | 51.89 seconds |
| Started | May 30 02:49:31 PM PDT 24 |
| Finished | May 30 02:50:26 PM PDT 24 |
| Peak memory | 192996 kb |
| Host | smart-ab7b37d1-6e8b-445c-b252-a1460bfac3a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196915963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a ll.196915963 |
| Directory | /workspace/48.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/10.aon_timer_stress_all.2067183486 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 150552583250 ps |
| CPU time | 103.39 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:50:40 PM PDT 24 |
| Peak memory | 193076 kb |
| Host | smart-e8931842-74dc-4598-8514-99c4fe8145e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067183486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_ all.2067183486 |
| Directory | /workspace/10.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1587620081 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 217607283105 ps |
| CPU time | 250.21 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:53:18 PM PDT 24 |
| Peak memory | 200884 kb |
| Host | smart-00818eb8-ce46-4462-bfca-158fca01a35d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587620081 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1587620081 |
| Directory | /workspace/11.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.aon_timer_stress_all.3956790894 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 405455195478 ps |
| CPU time | 285.75 seconds |
| Started | May 30 02:48:32 PM PDT 24 |
| Finished | May 30 02:53:19 PM PDT 24 |
| Peak memory | 191860 kb |
| Host | smart-cb3f3f9c-d9cc-439c-a587-cfeab9eea590 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956790894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a ll.3956790894 |
| Directory | /workspace/1.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.aon_timer_stress_all.2850246913 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 188797451904 ps |
| CPU time | 73.77 seconds |
| Started | May 30 02:49:35 PM PDT 24 |
| Finished | May 30 02:50:50 PM PDT 24 |
| Peak memory | 192592 kb |
| Host | smart-f443e3c3-2cd8-4c21-a0ce-08907614d0a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850246913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_ all.2850246913 |
| Directory | /workspace/47.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.924514445 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 353158760673 ps |
| CPU time | 606.9 seconds |
| Started | May 30 02:49:05 PM PDT 24 |
| Finished | May 30 02:59:13 PM PDT 24 |
| Peak memory | 204728 kb |
| Host | smart-260f97a7-9b53-438f-b37e-c4e6ac22734f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924514445 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.924514445 |
| Directory | /workspace/23.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2859636135 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 102532271589 ps |
| CPU time | 553.37 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:58:09 PM PDT 24 |
| Peak memory | 213000 kb |
| Host | smart-e93425c4-600f-46f1-bbfe-0b09fbfff9dc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859636135 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2859636135 |
| Directory | /workspace/7.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1298585650 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 32613571748 ps |
| CPU time | 229.3 seconds |
| Started | May 30 02:49:29 PM PDT 24 |
| Finished | May 30 02:53:21 PM PDT 24 |
| Peak memory | 198680 kb |
| Host | smart-72c4f936-c67f-4298-9f5b-8a9bd2b34fac |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298585650 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1298585650 |
| Directory | /workspace/36.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.aon_timer_stress_all.1611881790 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 98647914253 ps |
| CPU time | 74.79 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:50:26 PM PDT 24 |
| Peak memory | 191924 kb |
| Host | smart-f6cd5fd7-baa3-48de-b403-4102e7fe4a00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611881790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_ all.1611881790 |
| Directory | /workspace/24.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/28.aon_timer_stress_all.3229600648 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 151706907559 ps |
| CPU time | 221.93 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:52:56 PM PDT 24 |
| Peak memory | 191904 kb |
| Host | smart-599a1af6-6a74-4740-84c5-cbc453789b7c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229600648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_ all.3229600648 |
| Directory | /workspace/28.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.4205653627 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 48445871105 ps |
| CPU time | 106.02 seconds |
| Started | May 30 02:49:36 PM PDT 24 |
| Finished | May 30 02:51:24 PM PDT 24 |
| Peak memory | 198652 kb |
| Host | smart-ccc2bf0d-6dcd-408e-8594-c0f50431e7ab |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205653627 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.4205653627 |
| Directory | /workspace/44.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.aon_timer_stress_all.2721918945 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 266495236606 ps |
| CPU time | 91.59 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:50:47 PM PDT 24 |
| Peak memory | 191760 kb |
| Host | smart-2358c916-ab2c-4b75-b0fa-757eb41e6de9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721918945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_ all.2721918945 |
| Directory | /workspace/19.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1508180585 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 20811310540 ps |
| CPU time | 129.23 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:51:23 PM PDT 24 |
| Peak memory | 206820 kb |
| Host | smart-15b7c1af-dded-4432-a78c-64af382dea0e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508180585 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1508180585 |
| Directory | /workspace/27.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1370566077 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 448845291 ps |
| CPU time | 1.24 seconds |
| Started | May 30 02:55:35 PM PDT 24 |
| Finished | May 30 02:55:38 PM PDT 24 |
| Peak memory | 193360 kb |
| Host | smart-328e2c0d-6d81-43b5-8bb1-b051ef8a54b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370566077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1370566077 |
| Directory | /workspace/4.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/default/12.aon_timer_stress_all.482365324 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 280948609215 ps |
| CPU time | 474.1 seconds |
| Started | May 30 02:49:05 PM PDT 24 |
| Finished | May 30 02:57:01 PM PDT 24 |
| Peak memory | 192608 kb |
| Host | smart-1e62fe1f-3451-4261-98c2-cab6249d9b78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482365324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a ll.482365324 |
| Directory | /workspace/12.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3811762400 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 54278288892 ps |
| CPU time | 199.95 seconds |
| Started | May 30 02:49:36 PM PDT 24 |
| Finished | May 30 02:52:57 PM PDT 24 |
| Peak memory | 198692 kb |
| Host | smart-e852ad17-eca5-4583-a75d-824e153211f1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811762400 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3811762400 |
| Directory | /workspace/49.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3110307610 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 287960360049 ps |
| CPU time | 599.03 seconds |
| Started | May 30 02:49:05 PM PDT 24 |
| Finished | May 30 02:59:06 PM PDT 24 |
| Peak memory | 206872 kb |
| Host | smart-7fca2ee8-08e4-4b8d-88d9-808c2269b366 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110307610 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3110307610 |
| Directory | /workspace/12.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2295020448 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 54825472071 ps |
| CPU time | 449.61 seconds |
| Started | May 30 02:49:18 PM PDT 24 |
| Finished | May 30 02:56:50 PM PDT 24 |
| Peak memory | 206852 kb |
| Host | smart-aafafab9-de5c-4ba2-a436-febc44614ea9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295020448 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2295020448 |
| Directory | /workspace/43.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.691113226 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 388921255006 ps |
| CPU time | 248.18 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:53:22 PM PDT 24 |
| Peak memory | 208688 kb |
| Host | smart-69d65447-52f3-4670-a199-c9efb444f581 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691113226 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.691113226 |
| Directory | /workspace/16.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.aon_timer_stress_all.3594561778 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 271058661283 ps |
| CPU time | 322.08 seconds |
| Started | May 30 02:48:53 PM PDT 24 |
| Finished | May 30 02:54:19 PM PDT 24 |
| Peak memory | 192588 kb |
| Host | smart-3aa4b4e6-ba61-4605-92d4-63e98dc0e621 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594561778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a ll.3594561778 |
| Directory | /workspace/6.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/43.aon_timer_stress_all.1374744252 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3921353639 ps |
| CPU time | 2.37 seconds |
| Started | May 30 02:49:26 PM PDT 24 |
| Finished | May 30 02:49:31 PM PDT 24 |
| Peak memory | 191940 kb |
| Host | smart-eecb39eb-1154-464c-a560-b66a95bbe2c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374744252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_ all.1374744252 |
| Directory | /workspace/43.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/3.aon_timer_stress_all.587958228 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 120145920488 ps |
| CPU time | 184.9 seconds |
| Started | May 30 02:48:50 PM PDT 24 |
| Finished | May 30 02:51:55 PM PDT 24 |
| Peak memory | 191956 kb |
| Host | smart-a2632e53-c16e-4d8a-9639-ac765703671a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587958228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al l.587958228 |
| Directory | /workspace/3.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/34.aon_timer_stress_all.4056938814 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 110284015218 ps |
| CPU time | 170.79 seconds |
| Started | May 30 02:49:26 PM PDT 24 |
| Finished | May 30 02:52:20 PM PDT 24 |
| Peak memory | 198308 kb |
| Host | smart-517047aa-56f1-487d-a7dc-cb91f1cab03b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056938814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_ all.4056938814 |
| Directory | /workspace/34.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.aon_timer_stress_all.3561061965 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 465182530189 ps |
| CPU time | 726.14 seconds |
| Started | May 30 02:49:29 PM PDT 24 |
| Finished | May 30 03:01:38 PM PDT 24 |
| Peak memory | 192492 kb |
| Host | smart-22097ad5-968d-4b43-8027-306ec91548f1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561061965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_ all.3561061965 |
| Directory | /workspace/45.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/17.aon_timer_stress_all.3088227723 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 241135279922 ps |
| CPU time | 95.68 seconds |
| Started | May 30 02:49:12 PM PDT 24 |
| Finished | May 30 02:50:51 PM PDT 24 |
| Peak memory | 192488 kb |
| Host | smart-45817066-f65c-4c6a-9270-c81561c45c24 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088227723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_ all.3088227723 |
| Directory | /workspace/17.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3425297540 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 465254083012 ps |
| CPU time | 776.2 seconds |
| Started | May 30 02:48:50 PM PDT 24 |
| Finished | May 30 03:01:49 PM PDT 24 |
| Peak memory | 213908 kb |
| Host | smart-8d962199-62b7-4f3b-b925-2e12137e16c5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425297540 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3425297540 |
| Directory | /workspace/4.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.aon_timer_stress_all.3429312753 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 49100230311 ps |
| CPU time | 19.56 seconds |
| Started | May 30 02:49:37 PM PDT 24 |
| Finished | May 30 02:49:57 PM PDT 24 |
| Peak memory | 184068 kb |
| Host | smart-51c737db-8ea5-4f5b-b08b-0f5491497f2b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429312753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_ all.3429312753 |
| Directory | /workspace/46.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3472614636 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 27419067060 ps |
| CPU time | 290.84 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:54:03 PM PDT 24 |
| Peak memory | 206836 kb |
| Host | smart-b229da5a-96bc-44d6-8fa8-f65fb88e837d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472614636 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3472614636 |
| Directory | /workspace/18.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3392724292 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 22367624934 ps |
| CPU time | 93.81 seconds |
| Started | May 30 02:48:53 PM PDT 24 |
| Finished | May 30 02:50:31 PM PDT 24 |
| Peak memory | 206876 kb |
| Host | smart-beb7f963-b79b-47ab-9d24-80773be593a2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392724292 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3392724292 |
| Directory | /workspace/6.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1035911373 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 12061840669 ps |
| CPU time | 67.36 seconds |
| Started | May 30 02:48:29 PM PDT 24 |
| Finished | May 30 02:49:38 PM PDT 24 |
| Peak memory | 206884 kb |
| Host | smart-912f1015-5052-49ca-aa05-199d867e9b82 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035911373 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1035911373 |
| Directory | /workspace/1.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3628253984 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 167819830303 ps |
| CPU time | 364.9 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:55:16 PM PDT 24 |
| Peak memory | 206856 kb |
| Host | smart-5db10c58-9a83-41b5-b415-1bdf642fa1e5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628253984 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3628253984 |
| Directory | /workspace/24.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2184049270 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 39685187419 ps |
| CPU time | 332.45 seconds |
| Started | May 30 02:49:20 PM PDT 24 |
| Finished | May 30 02:54:55 PM PDT 24 |
| Peak memory | 198908 kb |
| Host | smart-2adec6b6-f958-47d2-81a9-d2a0e3912ee9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184049270 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2184049270 |
| Directory | /workspace/30.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3925336962 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 313458550394 ps |
| CPU time | 1239.58 seconds |
| Started | May 30 02:49:26 PM PDT 24 |
| Finished | May 30 03:10:09 PM PDT 24 |
| Peak memory | 215072 kb |
| Host | smart-6145515f-edfe-4e75-9220-88a90a3ffc98 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925336962 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3925336962 |
| Directory | /workspace/34.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.176803471 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 29904716709 ps |
| CPU time | 237.62 seconds |
| Started | May 30 02:48:50 PM PDT 24 |
| Finished | May 30 02:52:50 PM PDT 24 |
| Peak memory | 206928 kb |
| Host | smart-dad0d266-403e-41c2-8a6f-cc04c7be7042 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176803471 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.176803471 |
| Directory | /workspace/10.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2180415337 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 68105219741 ps |
| CPU time | 559.6 seconds |
| Started | May 30 02:49:08 PM PDT 24 |
| Finished | May 30 02:58:31 PM PDT 24 |
| Peak memory | 206916 kb |
| Host | smart-77c04ee8-f7d4-42c3-9c59-87e35d380a91 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180415337 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2180415337 |
| Directory | /workspace/26.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.aon_timer_stress_all.2078020909 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 87361686555 ps |
| CPU time | 140.21 seconds |
| Started | May 30 02:49:24 PM PDT 24 |
| Finished | May 30 02:51:46 PM PDT 24 |
| Peak memory | 192412 kb |
| Host | smart-f099ffee-de60-4e8a-b62b-af45fb05075e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078020909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_ all.2078020909 |
| Directory | /workspace/35.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/38.aon_timer_stress_all.1925625441 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 30911613554 ps |
| CPU time | 13.79 seconds |
| Started | May 30 02:49:20 PM PDT 24 |
| Finished | May 30 02:49:36 PM PDT 24 |
| Peak memory | 191920 kb |
| Host | smart-77136565-865a-41d0-9110-8eaa42612954 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925625441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_ all.1925625441 |
| Directory | /workspace/38.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2797892230 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 124044117914 ps |
| CPU time | 269.55 seconds |
| Started | May 30 02:49:18 PM PDT 24 |
| Finished | May 30 02:53:50 PM PDT 24 |
| Peak memory | 206924 kb |
| Host | smart-6c5235f9-e4fd-4a97-bb27-30efdb18cda0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797892230 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2797892230 |
| Directory | /workspace/41.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.689628772 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 77013711100 ps |
| CPU time | 291.15 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:53:47 PM PDT 24 |
| Peak memory | 209188 kb |
| Host | smart-31d60b50-e663-4bb8-88ef-8b145ad7fda4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689628772 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.689628772 |
| Directory | /workspace/2.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.aon_timer_stress_all.3050224646 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 134119975883 ps |
| CPU time | 110.87 seconds |
| Started | May 30 02:48:51 PM PDT 24 |
| Finished | May 30 02:50:44 PM PDT 24 |
| Peak memory | 191864 kb |
| Host | smart-8db7abb7-75f8-4be1-8fb8-dfc8c798de24 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050224646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a ll.3050224646 |
| Directory | /workspace/5.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/36.aon_timer_stress_all.2972853138 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 178047529660 ps |
| CPU time | 63.12 seconds |
| Started | May 30 02:49:25 PM PDT 24 |
| Finished | May 30 02:50:30 PM PDT 24 |
| Peak memory | 192512 kb |
| Host | smart-3dba3ba5-4053-466c-8729-9a9c681a361a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972853138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_ all.2972853138 |
| Directory | /workspace/36.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/42.aon_timer_stress_all.2901528123 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 287644837980 ps |
| CPU time | 423.72 seconds |
| Started | May 30 02:49:18 PM PDT 24 |
| Finished | May 30 02:56:24 PM PDT 24 |
| Peak memory | 192628 kb |
| Host | smart-635fc197-95d6-4ea2-8821-1af75d6ce7ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901528123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_ all.2901528123 |
| Directory | /workspace/42.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/9.aon_timer_stress_all.3271693775 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 128953477368 ps |
| CPU time | 46.66 seconds |
| Started | May 30 02:48:50 PM PDT 24 |
| Finished | May 30 02:49:38 PM PDT 24 |
| Peak memory | 191960 kb |
| Host | smart-408af267-cf67-4406-b324-b641caf35124 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271693775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a ll.3271693775 |
| Directory | /workspace/9.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/14.aon_timer_stress_all.2357729699 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 286408787167 ps |
| CPU time | 107.84 seconds |
| Started | May 30 02:49:07 PM PDT 24 |
| Finished | May 30 02:50:58 PM PDT 24 |
| Peak memory | 191940 kb |
| Host | smart-8d5a31cb-00b3-4955-a56f-f8d6027b1a5e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357729699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_ all.2357729699 |
| Directory | /workspace/14.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2088447785 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 145283837888 ps |
| CPU time | 262.41 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:53:37 PM PDT 24 |
| Peak memory | 200260 kb |
| Host | smart-8366ebd7-2476-4046-82ec-b139ea6e4b74 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088447785 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2088447785 |
| Directory | /workspace/19.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1650149492 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 85920585504 ps |
| CPU time | 212.9 seconds |
| Started | May 30 02:49:19 PM PDT 24 |
| Finished | May 30 02:52:55 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-b31db8fb-6a09-4bbf-816c-5a98e5028f8e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650149492 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1650149492 |
| Directory | /workspace/35.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.aon_timer_jump.4290812740 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 604035797 ps |
| CPU time | 0.74 seconds |
| Started | May 30 02:48:53 PM PDT 24 |
| Finished | May 30 02:48:58 PM PDT 24 |
| Peak memory | 196528 kb |
| Host | smart-39bf263c-533e-40af-a6e8-3b883bd67004 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290812740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.4290812740 |
| Directory | /workspace/10.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/13.aon_timer_jump.1159523608 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 352355672 ps |
| CPU time | 1.19 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:49:10 PM PDT 24 |
| Peak memory | 196444 kb |
| Host | smart-a0355713-ab89-4b5e-8d87-86d36923e58c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1159523608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1159523608 |
| Directory | /workspace/13.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/20.aon_timer_jump.3509904089 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 489400700 ps |
| CPU time | 0.75 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:16 PM PDT 24 |
| Peak memory | 196472 kb |
| Host | smart-32f032cf-d0c1-4fbc-ad30-7d7376a09fe6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3509904089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3509904089 |
| Directory | /workspace/20.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/22.aon_timer_stress_all.446402966 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 367854080948 ps |
| CPU time | 564.13 seconds |
| Started | May 30 02:49:08 PM PDT 24 |
| Finished | May 30 02:58:35 PM PDT 24 |
| Peak memory | 192816 kb |
| Host | smart-92d67e1b-8814-4102-8309-925c57acb1ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446402966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a ll.446402966 |
| Directory | /workspace/22.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/30.aon_timer_stress_all.810839183 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 134078279541 ps |
| CPU time | 40.12 seconds |
| Started | May 30 02:49:19 PM PDT 24 |
| Finished | May 30 02:50:02 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-e547d191-469d-4258-80a3-2b4b418e09c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810839183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a ll.810839183 |
| Directory | /workspace/30.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/31.aon_timer_stress_all.107411466 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 70862202463 ps |
| CPU time | 18.72 seconds |
| Started | May 30 02:49:17 PM PDT 24 |
| Finished | May 30 02:49:38 PM PDT 24 |
| Peak memory | 192432 kb |
| Host | smart-7315b9aa-5161-42c8-8ec2-876525a21a0b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107411466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a ll.107411466 |
| Directory | /workspace/31.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/49.aon_timer_stress_all.1638854778 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 80459526154 ps |
| CPU time | 67.54 seconds |
| Started | May 30 02:49:38 PM PDT 24 |
| Finished | May 30 02:50:47 PM PDT 24 |
| Peak memory | 192336 kb |
| Host | smart-d334e5a2-174c-4f8e-9cd5-cb5a8f231226 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638854778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_ all.1638854778 |
| Directory | /workspace/49.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.597985128 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 46011528556 ps |
| CPU time | 134.89 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:51:11 PM PDT 24 |
| Peak memory | 198584 kb |
| Host | smart-ffe356c3-06ae-4aac-8709-f1bc4401c50b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597985128 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.597985128 |
| Directory | /workspace/9.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.aon_timer_stress_all.2937484833 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 267989022402 ps |
| CPU time | 65.71 seconds |
| Started | May 30 02:48:29 PM PDT 24 |
| Finished | May 30 02:49:37 PM PDT 24 |
| Peak memory | 191936 kb |
| Host | smart-0f2834ca-a606-40ea-8607-f5e06457a902 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937484833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a ll.2937484833 |
| Directory | /workspace/0.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/15.aon_timer_stress_all.3284827094 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 150882270896 ps |
| CPU time | 54.44 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:50:06 PM PDT 24 |
| Peak memory | 191924 kb |
| Host | smart-05457959-3aae-486b-aa2d-ccfee0aafa1a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284827094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_ all.3284827094 |
| Directory | /workspace/15.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/34.aon_timer_jump.513949699 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 371253255 ps |
| CPU time | 0.87 seconds |
| Started | May 30 02:49:19 PM PDT 24 |
| Finished | May 30 02:49:23 PM PDT 24 |
| Peak memory | 196408 kb |
| Host | smart-fd56ed19-e3a4-4675-8e8b-b8cc8b542d11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513949699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.513949699 |
| Directory | /workspace/34.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/35.aon_timer_jump.1858521264 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 623340996 ps |
| CPU time | 0.65 seconds |
| Started | May 30 02:49:24 PM PDT 24 |
| Finished | May 30 02:49:27 PM PDT 24 |
| Peak memory | 196216 kb |
| Host | smart-d0bbe640-0393-49a2-af08-262f2bf32214 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858521264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1858521264 |
| Directory | /workspace/35.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/44.aon_timer_jump.1870363792 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 547295350 ps |
| CPU time | 1.09 seconds |
| Started | May 30 02:49:28 PM PDT 24 |
| Finished | May 30 02:49:32 PM PDT 24 |
| Peak memory | 196424 kb |
| Host | smart-a51efbf1-2684-49de-a75b-61bfe10723b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870363792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1870363792 |
| Directory | /workspace/44.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/6.aon_timer_jump.3466640966 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 492215349 ps |
| CPU time | 0.88 seconds |
| Started | May 30 02:48:51 PM PDT 24 |
| Finished | May 30 02:48:55 PM PDT 24 |
| Peak memory | 196528 kb |
| Host | smart-011bbe73-56d5-41b9-b915-630786126557 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466640966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3466640966 |
| Directory | /workspace/6.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/11.aon_timer_jump.1251697924 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 417710634 ps |
| CPU time | 1.25 seconds |
| Started | May 30 02:49:05 PM PDT 24 |
| Finished | May 30 02:49:08 PM PDT 24 |
| Peak memory | 196420 kb |
| Host | smart-2cbd74a6-70f4-4414-a0be-2013c9938724 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1251697924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1251697924 |
| Directory | /workspace/11.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.396903648 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 133102510827 ps |
| CPU time | 595.85 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:59:08 PM PDT 24 |
| Peak memory | 212548 kb |
| Host | smart-8b33fd8b-6bad-4800-87b7-fc8306718215 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396903648 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.396903648 |
| Directory | /workspace/15.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/18.aon_timer_stress_all.3915169185 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 151373883076 ps |
| CPU time | 54.92 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:50:09 PM PDT 24 |
| Peak memory | 191888 kb |
| Host | smart-8c88c7d7-1be3-43e7-9ad0-820c9af0c7ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915169185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_ all.3915169185 |
| Directory | /workspace/18.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/2.aon_timer_stress_all.3965526287 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 101770622546 ps |
| CPU time | 167.9 seconds |
| Started | May 30 02:48:53 PM PDT 24 |
| Finished | May 30 02:51:45 PM PDT 24 |
| Peak memory | 192584 kb |
| Host | smart-3cda3238-c11d-4991-8dbc-d45d8c988bb9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965526287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a ll.3965526287 |
| Directory | /workspace/2.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/21.aon_timer_jump.529022073 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 462751460 ps |
| CPU time | 1.36 seconds |
| Started | May 30 02:49:05 PM PDT 24 |
| Finished | May 30 02:49:08 PM PDT 24 |
| Peak memory | 196384 kb |
| Host | smart-b5f1304e-cc42-40e6-b303-1576af40fe2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=529022073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.529022073 |
| Directory | /workspace/21.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/25.aon_timer_stress_all.3889530497 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 167645486350 ps |
| CPU time | 234.56 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:53:08 PM PDT 24 |
| Peak memory | 193012 kb |
| Host | smart-9ec04e49-6ff3-4a0b-b2bc-c17ee0a27d92 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889530497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_ all.3889530497 |
| Directory | /workspace/25.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1762369619 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 23878322518 ps |
| CPU time | 87.12 seconds |
| Started | May 30 02:48:51 PM PDT 24 |
| Finished | May 30 02:50:22 PM PDT 24 |
| Peak memory | 214244 kb |
| Host | smart-3b7ff066-935b-4ab3-874b-e0b671d5fc01 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762369619 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1762369619 |
| Directory | /workspace/3.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.aon_timer_jump.234334473 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 488751683 ps |
| CPU time | 0.77 seconds |
| Started | May 30 02:49:29 PM PDT 24 |
| Finished | May 30 02:49:33 PM PDT 24 |
| Peak memory | 196516 kb |
| Host | smart-cf94c4b9-0419-430b-b31b-9d6707e00aaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234334473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.234334473 |
| Directory | /workspace/36.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/7.aon_timer_stress_all.4234623221 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 85882304265 ps |
| CPU time | 49.81 seconds |
| Started | May 30 02:48:51 PM PDT 24 |
| Finished | May 30 02:49:44 PM PDT 24 |
| Peak memory | 191920 kb |
| Host | smart-b4f66e8e-785e-448b-9afb-3d114d8f715a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234623221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a ll.4234623221 |
| Directory | /workspace/7.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/16.aon_timer_jump.949140077 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 409282358 ps |
| CPU time | 0.76 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:49:13 PM PDT 24 |
| Peak memory | 196428 kb |
| Host | smart-a24fa252-80f4-40ce-b34b-1f616d6000bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=949140077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.949140077 |
| Directory | /workspace/16.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/17.aon_timer_jump.1005557107 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 511382874 ps |
| CPU time | 1.34 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:49:14 PM PDT 24 |
| Peak memory | 196544 kb |
| Host | smart-f4be5f74-046e-4fe9-ba84-7c491d8b8f20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005557107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1005557107 |
| Directory | /workspace/17.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2977144712 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 41133906795 ps |
| CPU time | 274.37 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:53:48 PM PDT 24 |
| Peak memory | 198612 kb |
| Host | smart-bf97ac7f-4609-496d-bd76-154ebc3872a1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977144712 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2977144712 |
| Directory | /workspace/20.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.aon_timer_jump.3809768010 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 370444773 ps |
| CPU time | 1.15 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:49:08 PM PDT 24 |
| Peak memory | 196444 kb |
| Host | smart-76b0b0bf-3d78-4f61-87cf-ef118e0f2753 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3809768010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3809768010 |
| Directory | /workspace/22.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/23.aon_timer_stress_all.321105109 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 287104234602 ps |
| CPU time | 209.68 seconds |
| Started | May 30 02:49:08 PM PDT 24 |
| Finished | May 30 02:52:40 PM PDT 24 |
| Peak memory | 192336 kb |
| Host | smart-f9fd9ebf-d3b5-4783-9e1e-f8dad5d4e5ff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321105109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a ll.321105109 |
| Directory | /workspace/23.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/24.aon_timer_jump.3891218063 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 561034457 ps |
| CPU time | 1.04 seconds |
| Started | May 30 02:49:07 PM PDT 24 |
| Finished | May 30 02:49:11 PM PDT 24 |
| Peak memory | 196436 kb |
| Host | smart-d2048cf9-da50-4508-b711-39834a293d62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891218063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3891218063 |
| Directory | /workspace/24.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1813891903 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 21135497457 ps |
| CPU time | 78.91 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:50:32 PM PDT 24 |
| Peak memory | 215012 kb |
| Host | smart-73451164-d4b8-4bb5-a345-b056149cb63a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813891903 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1813891903 |
| Directory | /workspace/25.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.aon_timer_jump.3943596429 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 433537755 ps |
| CPU time | 0.79 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:49:14 PM PDT 24 |
| Peak memory | 196272 kb |
| Host | smart-d3755450-9acf-4cf6-a865-716072db17a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3943596429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3943596429 |
| Directory | /workspace/27.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/27.aon_timer_stress_all.692373781 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 421036795290 ps |
| CPU time | 174.69 seconds |
| Started | May 30 02:49:12 PM PDT 24 |
| Finished | May 30 02:52:10 PM PDT 24 |
| Peak memory | 191940 kb |
| Host | smart-02a4809b-d9b2-40ba-a9bd-70af6283923b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692373781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a ll.692373781 |
| Directory | /workspace/27.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/32.aon_timer_jump.3438685439 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 506081382 ps |
| CPU time | 0.66 seconds |
| Started | May 30 02:49:19 PM PDT 24 |
| Finished | May 30 02:49:23 PM PDT 24 |
| Peak memory | 196404 kb |
| Host | smart-9c379201-4c1a-4f2a-87f2-4ed5fd7cc559 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438685439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3438685439 |
| Directory | /workspace/32.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/32.aon_timer_stress_all.1301461461 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 41027582605 ps |
| CPU time | 13.83 seconds |
| Started | May 30 02:49:23 PM PDT 24 |
| Finished | May 30 02:49:38 PM PDT 24 |
| Peak memory | 198180 kb |
| Host | smart-b5d69a4e-2a00-4b5c-b23d-4ea8533eaf62 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301461461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_ all.1301461461 |
| Directory | /workspace/32.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/40.aon_timer_jump.687150483 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 430658719 ps |
| CPU time | 0.91 seconds |
| Started | May 30 02:49:18 PM PDT 24 |
| Finished | May 30 02:49:22 PM PDT 24 |
| Peak memory | 196496 kb |
| Host | smart-e7919f62-691c-46e0-aed5-a39d30096d47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687150483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.687150483 |
| Directory | /workspace/40.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/41.aon_timer_stress_all.3201508264 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 238271844014 ps |
| CPU time | 57.08 seconds |
| Started | May 30 02:49:26 PM PDT 24 |
| Finished | May 30 02:50:25 PM PDT 24 |
| Peak memory | 192624 kb |
| Host | smart-6d420313-111d-4f9d-bbb2-80836a7424a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201508264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_ all.3201508264 |
| Directory | /workspace/41.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.aon_timer_jump.2560803 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 366785950 ps |
| CPU time | 0.89 seconds |
| Started | May 30 02:49:27 PM PDT 24 |
| Finished | May 30 02:49:30 PM PDT 24 |
| Peak memory | 196444 kb |
| Host | smart-9553b6b1-4fd2-4585-94f7-3ee66ebd5ea5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2560803 |
| Directory | /workspace/45.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/12.aon_timer_jump.4290671322 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 443241687 ps |
| CPU time | 1.25 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:49:09 PM PDT 24 |
| Peak memory | 196464 kb |
| Host | smart-657fb5fb-e439-4f7d-86cd-9cf5e006f9aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290671322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.4290671322 |
| Directory | /workspace/12.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.205454125 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 43374185933 ps |
| CPU time | 306.99 seconds |
| Started | May 30 02:49:07 PM PDT 24 |
| Finished | May 30 02:54:17 PM PDT 24 |
| Peak memory | 206932 kb |
| Host | smart-06a95078-d27e-4a07-942b-bdfa7366643c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205454125 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.205454125 |
| Directory | /workspace/13.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1001762770 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 29275206582 ps |
| CPU time | 223.29 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:52:55 PM PDT 24 |
| Peak memory | 207000 kb |
| Host | smart-0efd82a1-2841-427e-b81e-039d71660081 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001762770 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1001762770 |
| Directory | /workspace/17.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.aon_timer_jump.4186584398 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 354754951 ps |
| CPU time | 0.7 seconds |
| Started | May 30 02:48:30 PM PDT 24 |
| Finished | May 30 02:48:33 PM PDT 24 |
| Peak memory | 196456 kb |
| Host | smart-14b50f54-23a5-4b48-af28-9277b2c07865 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186584398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4186584398 |
| Directory | /workspace/2.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/20.aon_timer_stress_all.181104647 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 250367745210 ps |
| CPU time | 95.4 seconds |
| Started | May 30 02:49:07 PM PDT 24 |
| Finished | May 30 02:50:45 PM PDT 24 |
| Peak memory | 192964 kb |
| Host | smart-38646691-e502-4c5a-90a3-ad4db8b72208 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181104647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a ll.181104647 |
| Directory | /workspace/20.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/21.aon_timer_stress_all.289689404 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 218384817306 ps |
| CPU time | 87.32 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:50:35 PM PDT 24 |
| Peak memory | 192944 kb |
| Host | smart-2f1c04fa-8372-40c2-bb64-e76f1ab1cf61 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289689404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a ll.289689404 |
| Directory | /workspace/21.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/29.aon_timer_stress_all.2457392773 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 124421985306 ps |
| CPU time | 23.87 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:49:38 PM PDT 24 |
| Peak memory | 192908 kb |
| Host | smart-41a580a0-1f9b-4db7-b050-a28def25d3ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457392773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_ all.2457392773 |
| Directory | /workspace/29.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.aon_timer_jump.1792153724 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 494542895 ps |
| CPU time | 0.94 seconds |
| Started | May 30 02:49:29 PM PDT 24 |
| Finished | May 30 02:49:33 PM PDT 24 |
| Peak memory | 196432 kb |
| Host | smart-08405b69-95b6-4252-a17c-5464395d417b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1792153724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1792153724 |
| Directory | /workspace/37.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/4.aon_timer_stress_all.794941143 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 115546855245 ps |
| CPU time | 178.67 seconds |
| Started | May 30 02:48:53 PM PDT 24 |
| Finished | May 30 02:51:56 PM PDT 24 |
| Peak memory | 191968 kb |
| Host | smart-69041a05-35ea-45d9-8c4b-6701ee55344d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794941143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al l.794941143 |
| Directory | /workspace/4.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/42.aon_timer_jump.392778897 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 536248797 ps |
| CPU time | 0.68 seconds |
| Started | May 30 02:49:26 PM PDT 24 |
| Finished | May 30 02:49:29 PM PDT 24 |
| Peak memory | 196416 kb |
| Host | smart-d47291a2-cd60-482b-b483-792307e8883a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392778897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.392778897 |
| Directory | /workspace/42.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/44.aon_timer_stress_all.3221447674 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 412452107587 ps |
| CPU time | 379.16 seconds |
| Started | May 30 02:49:30 PM PDT 24 |
| Finished | May 30 02:55:52 PM PDT 24 |
| Peak memory | 184068 kb |
| Host | smart-9ceddc36-7fd3-4233-82b8-25c51967f51b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221447674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_ all.3221447674 |
| Directory | /workspace/44.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/46.aon_timer_jump.3736969004 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 539088494 ps |
| CPU time | 1.41 seconds |
| Started | May 30 02:49:28 PM PDT 24 |
| Finished | May 30 02:49:31 PM PDT 24 |
| Peak memory | 196452 kb |
| Host | smart-3a5b0644-a077-489e-b91b-5af67452d928 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3736969004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3736969004 |
| Directory | /workspace/46.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/49.aon_timer_jump.3622795640 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 513777910 ps |
| CPU time | 1.07 seconds |
| Started | May 30 02:49:38 PM PDT 24 |
| Finished | May 30 02:49:41 PM PDT 24 |
| Peak memory | 195372 kb |
| Host | smart-90fd64ca-84ec-4d18-af7e-bb8f4deb98de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622795640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3622795640 |
| Directory | /workspace/49.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/9.aon_timer_jump.757722356 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 576732703 ps |
| CPU time | 0.8 seconds |
| Started | May 30 02:48:51 PM PDT 24 |
| Finished | May 30 02:48:56 PM PDT 24 |
| Peak memory | 196404 kb |
| Host | smart-d797b342-2299-4852-8151-9fcafbded1bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=757722356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.757722356 |
| Directory | /workspace/9.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/11.aon_timer_stress_all.338312500 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 178631839286 ps |
| CPU time | 125.19 seconds |
| Started | May 30 02:49:07 PM PDT 24 |
| Finished | May 30 02:51:16 PM PDT 24 |
| Peak memory | 192648 kb |
| Host | smart-58db028d-6fc1-43d2-98b6-92e3f61fcbd8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338312500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a ll.338312500 |
| Directory | /workspace/11.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1539342406 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 61093528220 ps |
| CPU time | 341.9 seconds |
| Started | May 30 02:49:07 PM PDT 24 |
| Finished | May 30 02:54:52 PM PDT 24 |
| Peak memory | 200460 kb |
| Host | smart-105dc1f2-1baf-443e-a8b9-1ab9e1a89ed1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539342406 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1539342406 |
| Directory | /workspace/14.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.aon_timer_stress_all.2595228351 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 123482209868 ps |
| CPU time | 187.99 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:52:21 PM PDT 24 |
| Peak memory | 192964 kb |
| Host | smart-fa2f1b23-0059-47d8-9a1a-72018f87e6bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595228351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_ all.2595228351 |
| Directory | /workspace/16.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3689852934 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 99671643144 ps |
| CPU time | 284.01 seconds |
| Started | May 30 02:49:07 PM PDT 24 |
| Finished | May 30 02:53:53 PM PDT 24 |
| Peak memory | 206848 kb |
| Host | smart-0f488c6a-360c-4eea-a5f1-e58ffdaa8e7a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689852934 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3689852934 |
| Directory | /workspace/22.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.aon_timer_jump.2841002195 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 550176290 ps |
| CPU time | 1.38 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:49:10 PM PDT 24 |
| Peak memory | 196440 kb |
| Host | smart-c935922e-6ee7-4a9a-85d8-752f6015093d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2841002195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2841002195 |
| Directory | /workspace/23.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/28.aon_timer_jump.376083838 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 485034840 ps |
| CPU time | 1.31 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:49:15 PM PDT 24 |
| Peak memory | 196408 kb |
| Host | smart-bae3f701-a475-4132-9827-1e3f281a1446 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376083838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.376083838 |
| Directory | /workspace/28.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/39.aon_timer_jump.285340350 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 532311307 ps |
| CPU time | 1.39 seconds |
| Started | May 30 02:49:25 PM PDT 24 |
| Finished | May 30 02:49:28 PM PDT 24 |
| Peak memory | 196428 kb |
| Host | smart-43fc55eb-1e77-4047-a572-64a77e2eda50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=285340350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.285340350 |
| Directory | /workspace/39.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.668571464 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 17681453143 ps |
| CPU time | 88.84 seconds |
| Started | May 30 02:49:35 PM PDT 24 |
| Finished | May 30 02:51:05 PM PDT 24 |
| Peak memory | 206880 kb |
| Host | smart-4f64d4c4-4a3e-44b3-a39d-692e101ec194 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668571464 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.668571464 |
| Directory | /workspace/46.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.aon_timer_jump.1383928492 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 442901216 ps |
| CPU time | 1.3 seconds |
| Started | May 30 02:49:36 PM PDT 24 |
| Finished | May 30 02:49:38 PM PDT 24 |
| Peak memory | 196476 kb |
| Host | smart-d2ab89c1-5ee0-4dd5-ba64-c28351f32816 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1383928492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1383928492 |
| Directory | /workspace/48.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/13.aon_timer_stress_all.2229763986 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 136866627640 ps |
| CPU time | 56.29 seconds |
| Started | May 30 02:49:07 PM PDT 24 |
| Finished | May 30 02:50:05 PM PDT 24 |
| Peak memory | 191940 kb |
| Host | smart-4137b9ea-36cc-46a5-97b0-33221a488ea2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229763986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_ all.2229763986 |
| Directory | /workspace/13.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3911333428 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 15370797600 ps |
| CPU time | 76.24 seconds |
| Started | May 30 02:49:29 PM PDT 24 |
| Finished | May 30 02:50:48 PM PDT 24 |
| Peak memory | 199024 kb |
| Host | smart-6f555295-2de4-4a1d-8c5d-f17b8613bb22 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911333428 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3911333428 |
| Directory | /workspace/37.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.aon_timer_jump.67811785 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 365419184 ps |
| CPU time | 1.17 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:48:57 PM PDT 24 |
| Peak memory | 196436 kb |
| Host | smart-eceef8b8-b852-4963-a9d1-9c59a78cc427 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67811785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.67811785 |
| Directory | /workspace/4.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/40.aon_timer_stress_all.305706936 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 201399649834 ps |
| CPU time | 304.94 seconds |
| Started | May 30 02:49:20 PM PDT 24 |
| Finished | May 30 02:54:28 PM PDT 24 |
| Peak memory | 184076 kb |
| Host | smart-d5041bb0-56b2-4b4b-9189-0b5832dca3ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305706936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a ll.305706936 |
| Directory | /workspace/40.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/5.aon_timer_jump.2117454360 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 388425729 ps |
| CPU time | 1.18 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:48:58 PM PDT 24 |
| Peak memory | 196376 kb |
| Host | smart-c31584db-22bc-4cab-bb57-7eaa7d7a47d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117454360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2117454360 |
| Directory | /workspace/5.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/8.aon_timer_jump.490294611 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 607052890 ps |
| CPU time | 0.83 seconds |
| Started | May 30 02:48:53 PM PDT 24 |
| Finished | May 30 02:48:58 PM PDT 24 |
| Peak memory | 196456 kb |
| Host | smart-4346051b-c82c-4a6f-b823-1f2b2a605bed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490294611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.490294611 |
| Directory | /workspace/8.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/0.aon_timer_jump.1657106205 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 585327426 ps |
| CPU time | 0.8 seconds |
| Started | May 30 02:48:33 PM PDT 24 |
| Finished | May 30 02:48:35 PM PDT 24 |
| Peak memory | 196456 kb |
| Host | smart-ce012eed-6f98-44b8-ba96-134c8fd9107b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657106205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1657106205 |
| Directory | /workspace/0.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/14.aon_timer_jump.1155934979 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 399258277 ps |
| CPU time | 1.33 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:49:10 PM PDT 24 |
| Peak memory | 196500 kb |
| Host | smart-db644d1c-0326-4526-9e2f-b21eea939ab0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155934979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1155934979 |
| Directory | /workspace/14.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/19.aon_timer_jump.1747653247 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 527655667 ps |
| CPU time | 1.49 seconds |
| Started | May 30 02:49:12 PM PDT 24 |
| Finished | May 30 02:49:17 PM PDT 24 |
| Peak memory | 196472 kb |
| Host | smart-7c078f67-1118-4402-a1c8-96fc20bd8782 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1747653247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1747653247 |
| Directory | /workspace/19.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/30.aon_timer_jump.1532415797 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 419719918 ps |
| CPU time | 0.65 seconds |
| Started | May 30 02:49:21 PM PDT 24 |
| Finished | May 30 02:49:24 PM PDT 24 |
| Peak memory | 196420 kb |
| Host | smart-f4931e50-7d2c-458b-b655-b20c2104ad56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532415797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1532415797 |
| Directory | /workspace/30.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/31.aon_timer_jump.2454913002 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 625879861 ps |
| CPU time | 0.8 seconds |
| Started | May 30 02:49:20 PM PDT 24 |
| Finished | May 30 02:49:24 PM PDT 24 |
| Peak memory | 196436 kb |
| Host | smart-9a857230-73fd-41aa-a500-d9e53b32c65f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2454913002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2454913002 |
| Directory | /workspace/31.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/43.aon_timer_jump.3386127729 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 541102203 ps |
| CPU time | 1.4 seconds |
| Started | May 30 02:49:26 PM PDT 24 |
| Finished | May 30 02:49:30 PM PDT 24 |
| Peak memory | 196500 kb |
| Host | smart-b9617915-801d-4c30-879b-3dba6c98e062 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3386127729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3386127729 |
| Directory | /workspace/43.aon_timer_jump/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3083378828 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4513322945 ps |
| CPU time | 7.96 seconds |
| Started | May 30 02:55:58 PM PDT 24 |
| Finished | May 30 02:56:08 PM PDT 24 |
| Peak memory | 197544 kb |
| Host | smart-fbc08185-1c7a-473c-a577-3212ccc405e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083378828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t l_intg_err.3083378828 |
| Directory | /workspace/11.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/1.aon_timer_jump.3714649983 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 579078981 ps |
| CPU time | 0.79 seconds |
| Started | May 30 02:48:29 PM PDT 24 |
| Finished | May 30 02:48:31 PM PDT 24 |
| Peak memory | 196432 kb |
| Host | smart-229136e9-0859-4203-be3c-7d4f2298f663 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714649983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3714649983 |
| Directory | /workspace/1.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/25.aon_timer_jump.1872323837 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 612144401 ps |
| CPU time | 1.62 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:16 PM PDT 24 |
| Peak memory | 196384 kb |
| Host | smart-9ac953ce-2a71-4d4f-a117-26c62557746d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1872323837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1872323837 |
| Directory | /workspace/25.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/3.aon_timer_jump.2233428389 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 547792794 ps |
| CPU time | 1.32 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:48:58 PM PDT 24 |
| Peak memory | 196440 kb |
| Host | smart-7a5236ed-904f-4e16-a6dd-3a837726358e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233428389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2233428389 |
| Directory | /workspace/3.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/33.aon_timer_jump.1582902939 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 599396738 ps |
| CPU time | 1.5 seconds |
| Started | May 30 02:49:25 PM PDT 24 |
| Finished | May 30 02:49:28 PM PDT 24 |
| Peak memory | 196460 kb |
| Host | smart-5497e4e8-622c-4ed9-8409-0ae9df4ad7e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582902939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1582902939 |
| Directory | /workspace/33.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/41.aon_timer_jump.644198305 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 495334473 ps |
| CPU time | 1 seconds |
| Started | May 30 02:49:19 PM PDT 24 |
| Finished | May 30 02:49:23 PM PDT 24 |
| Peak memory | 196528 kb |
| Host | smart-9e4a30a2-b12e-4556-b2d2-b76f3c7226b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=644198305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.644198305 |
| Directory | /workspace/41.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/47.aon_timer_jump.1957537974 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 519020854 ps |
| CPU time | 1.33 seconds |
| Started | May 30 02:49:28 PM PDT 24 |
| Finished | May 30 02:49:32 PM PDT 24 |
| Peak memory | 196500 kb |
| Host | smart-f2cd1c45-5358-4a39-adb6-52d3c1dd59cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957537974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1957537974 |
| Directory | /workspace/47.aon_timer_jump/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.734200145 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 515361963 ps |
| CPU time | 1.12 seconds |
| Started | May 30 02:54:51 PM PDT 24 |
| Finished | May 30 02:54:53 PM PDT 24 |
| Peak memory | 183704 kb |
| Host | smart-058a6d65-6044-422c-bdb4-3ad1226c0d78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734200145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al iasing.734200145 |
| Directory | /workspace/0.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3502356831 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1116134239 ps |
| CPU time | 4.81 seconds |
| Started | May 30 02:54:53 PM PDT 24 |
| Finished | May 30 02:55:00 PM PDT 24 |
| Peak memory | 195540 kb |
| Host | smart-02a0643f-6867-4151-b651-ce965e44e151 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502356831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b it_bash.3502356831 |
| Directory | /workspace/0.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2388927482 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 691373758 ps |
| CPU time | 0.82 seconds |
| Started | May 30 02:54:54 PM PDT 24 |
| Finished | May 30 02:54:57 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-b79875e1-4835-41f7-b23e-143b8c0514b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388927482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h w_reset.2388927482 |
| Directory | /workspace/0.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4229525157 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 461644274 ps |
| CPU time | 0.81 seconds |
| Started | May 30 02:54:51 PM PDT 24 |
| Finished | May 30 02:54:54 PM PDT 24 |
| Peak memory | 195504 kb |
| Host | smart-d3f9b8cd-644e-47c3-8a09-177a4d16e3d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229525157 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.4229525157 |
| Directory | /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3740741251 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 298252471 ps |
| CPU time | 1.07 seconds |
| Started | May 30 02:54:52 PM PDT 24 |
| Finished | May 30 02:54:54 PM PDT 24 |
| Peak memory | 193004 kb |
| Host | smart-08ac3950-f95a-47ff-815e-4a42c93a44ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740741251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3740741251 |
| Directory | /workspace/0.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2345247017 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 278342432 ps |
| CPU time | 1.07 seconds |
| Started | May 30 02:54:51 PM PDT 24 |
| Finished | May 30 02:54:53 PM PDT 24 |
| Peak memory | 183612 kb |
| Host | smart-6b9df778-c54d-4ab0-878f-966013242373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345247017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2345247017 |
| Directory | /workspace/0.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3694637699 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 296618515 ps |
| CPU time | 0.6 seconds |
| Started | May 30 02:54:51 PM PDT 24 |
| Finished | May 30 02:54:53 PM PDT 24 |
| Peak memory | 183580 kb |
| Host | smart-32a512cf-79f7-40f3-ac10-849052bd9e10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694637699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t imer_mem_partial_access.3694637699 |
| Directory | /workspace/0.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2657979907 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 464019128 ps |
| CPU time | 0.58 seconds |
| Started | May 30 02:54:51 PM PDT 24 |
| Finished | May 30 02:54:53 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-2811fe0a-49a8-41d1-9081-8027a740e79f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657979907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w alk.2657979907 |
| Directory | /workspace/0.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3932046145 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2108019381 ps |
| CPU time | 6.35 seconds |
| Started | May 30 02:54:53 PM PDT 24 |
| Finished | May 30 02:55:01 PM PDT 24 |
| Peak memory | 191884 kb |
| Host | smart-8bb34b18-6c91-4cb0-a436-11b2eed8141d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932046145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon _timer_same_csr_outstanding.3932046145 |
| Directory | /workspace/0.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.516649462 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 493048425 ps |
| CPU time | 1.91 seconds |
| Started | May 30 02:54:52 PM PDT 24 |
| Finished | May 30 02:54:55 PM PDT 24 |
| Peak memory | 198480 kb |
| Host | smart-052bca44-467c-4e97-93b2-1527a9184be7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516649462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.516649462 |
| Directory | /workspace/0.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2614166723 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 8077803377 ps |
| CPU time | 12.27 seconds |
| Started | May 30 02:54:51 PM PDT 24 |
| Finished | May 30 02:55:04 PM PDT 24 |
| Peak memory | 198040 kb |
| Host | smart-cd99d557-70a0-4260-a44c-831800c17ea8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614166723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl _intg_err.2614166723 |
| Directory | /workspace/0.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2389246062 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 524205945 ps |
| CPU time | 0.99 seconds |
| Started | May 30 02:55:06 PM PDT 24 |
| Finished | May 30 02:55:08 PM PDT 24 |
| Peak memory | 194244 kb |
| Host | smart-600eeccd-0dcb-49fe-925d-1dd7bd2814a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389246062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a liasing.2389246062 |
| Directory | /workspace/1.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.850289247 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3219434994 ps |
| CPU time | 5.99 seconds |
| Started | May 30 02:55:09 PM PDT 24 |
| Finished | May 30 02:55:16 PM PDT 24 |
| Peak memory | 192116 kb |
| Host | smart-6d8230be-dc38-4de4-9ff2-04aac5c765c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850289247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi t_bash.850289247 |
| Directory | /workspace/1.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1743071244 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 996792666 ps |
| CPU time | 0.97 seconds |
| Started | May 30 02:55:06 PM PDT 24 |
| Finished | May 30 02:55:08 PM PDT 24 |
| Peak memory | 183780 kb |
| Host | smart-43761a85-28ae-4b6a-a718-4cf8d57fb1d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743071244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h w_reset.1743071244 |
| Directory | /workspace/1.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.820310043 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 338632459 ps |
| CPU time | 0.86 seconds |
| Started | May 30 02:55:06 PM PDT 24 |
| Finished | May 30 02:55:08 PM PDT 24 |
| Peak memory | 195404 kb |
| Host | smart-19f47e87-f0f8-423a-a208-45f5f78b1ed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820310043 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.820310043 |
| Directory | /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3067926643 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 455886144 ps |
| CPU time | 1 seconds |
| Started | May 30 02:55:08 PM PDT 24 |
| Finished | May 30 02:55:10 PM PDT 24 |
| Peak memory | 193008 kb |
| Host | smart-13ecc3db-01ee-47e8-9466-1f6884898259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067926643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3067926643 |
| Directory | /workspace/1.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2636080686 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 446281455 ps |
| CPU time | 1.2 seconds |
| Started | May 30 02:55:05 PM PDT 24 |
| Finished | May 30 02:55:07 PM PDT 24 |
| Peak memory | 183724 kb |
| Host | smart-39a2b3f5-217c-4f51-9fa0-32b0da9d60c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636080686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2636080686 |
| Directory | /workspace/1.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.224066018 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 393307081 ps |
| CPU time | 0.69 seconds |
| Started | May 30 02:55:06 PM PDT 24 |
| Finished | May 30 02:55:08 PM PDT 24 |
| Peak memory | 183564 kb |
| Host | smart-bf935df4-080d-4559-958e-fd57330b5f7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224066018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti mer_mem_partial_access.224066018 |
| Directory | /workspace/1.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1158830369 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 353739387 ps |
| CPU time | 0.65 seconds |
| Started | May 30 02:55:05 PM PDT 24 |
| Finished | May 30 02:55:07 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-42d6f11b-b221-4782-908a-cad0b8064719 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158830369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w alk.1158830369 |
| Directory | /workspace/1.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1870105325 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1240236902 ps |
| CPU time | 1.44 seconds |
| Started | May 30 02:55:06 PM PDT 24 |
| Finished | May 30 02:55:09 PM PDT 24 |
| Peak memory | 193164 kb |
| Host | smart-6f8370fd-daa6-4ed2-a66e-fdbe81e15b38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870105325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon _timer_same_csr_outstanding.1870105325 |
| Directory | /workspace/1.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3692448885 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 663685868 ps |
| CPU time | 2.16 seconds |
| Started | May 30 02:54:50 PM PDT 24 |
| Finished | May 30 02:54:54 PM PDT 24 |
| Peak memory | 198508 kb |
| Host | smart-19d3ec25-63ae-431a-9762-abbac6ae1dbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692448885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3692448885 |
| Directory | /workspace/1.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2453630368 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 4281229676 ps |
| CPU time | 6.88 seconds |
| Started | May 30 02:54:54 PM PDT 24 |
| Finished | May 30 02:55:03 PM PDT 24 |
| Peak memory | 196524 kb |
| Host | smart-e09135b3-32c1-412d-a0a1-b5cb4c4bb050 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453630368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl _intg_err.2453630368 |
| Directory | /workspace/1.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.932232654 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 310691481 ps |
| CPU time | 1.1 seconds |
| Started | May 30 02:55:44 PM PDT 24 |
| Finished | May 30 02:55:47 PM PDT 24 |
| Peak memory | 195652 kb |
| Host | smart-f72f17fd-0f8c-4bdb-a7b3-cfa96f563e97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932232654 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.932232654 |
| Directory | /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.327997228 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 472118162 ps |
| CPU time | 1.3 seconds |
| Started | May 30 02:55:44 PM PDT 24 |
| Finished | May 30 02:55:47 PM PDT 24 |
| Peak memory | 183860 kb |
| Host | smart-294423a0-ea3f-4418-ab5b-3dbd8fd73611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327997228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.327997228 |
| Directory | /workspace/10.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2590194056 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 304856668 ps |
| CPU time | 0.68 seconds |
| Started | May 30 02:55:45 PM PDT 24 |
| Finished | May 30 02:55:48 PM PDT 24 |
| Peak memory | 183588 kb |
| Host | smart-74d8c6dd-d6c3-4979-ac40-1897a9ff72c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590194056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2590194056 |
| Directory | /workspace/10.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3843069469 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 974317199 ps |
| CPU time | 0.94 seconds |
| Started | May 30 02:55:45 PM PDT 24 |
| Finished | May 30 02:55:48 PM PDT 24 |
| Peak memory | 183796 kb |
| Host | smart-4798b233-171c-4cee-a129-d5ed2696529e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843069469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao n_timer_same_csr_outstanding.3843069469 |
| Directory | /workspace/10.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.104580167 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 487539103 ps |
| CPU time | 2.12 seconds |
| Started | May 30 02:55:44 PM PDT 24 |
| Finished | May 30 02:55:47 PM PDT 24 |
| Peak memory | 198480 kb |
| Host | smart-f1ae36b8-6f64-4123-bb79-9f7d0c28e3bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104580167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.104580167 |
| Directory | /workspace/10.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3027483208 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4224216220 ps |
| CPU time | 6.12 seconds |
| Started | May 30 02:55:44 PM PDT 24 |
| Finished | May 30 02:55:51 PM PDT 24 |
| Peak memory | 197864 kb |
| Host | smart-9dd9b253-4ba7-4a7a-bd00-f3f37078bbd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027483208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t l_intg_err.3027483208 |
| Directory | /workspace/10.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3138472745 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 481780469 ps |
| CPU time | 0.88 seconds |
| Started | May 30 02:55:57 PM PDT 24 |
| Finished | May 30 02:56:01 PM PDT 24 |
| Peak memory | 195320 kb |
| Host | smart-0cc75d8d-1b95-4de6-b356-a51a53ccebcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138472745 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3138472745 |
| Directory | /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1098104342 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 567464659 ps |
| CPU time | 0.85 seconds |
| Started | May 30 02:55:56 PM PDT 24 |
| Finished | May 30 02:55:59 PM PDT 24 |
| Peak memory | 192964 kb |
| Host | smart-8aa3cf39-c493-4b21-9cdc-2e9caa5989f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098104342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1098104342 |
| Directory | /workspace/11.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2982312895 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 541620964 ps |
| CPU time | 0.76 seconds |
| Started | May 30 02:55:57 PM PDT 24 |
| Finished | May 30 02:56:01 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-8b124b52-8667-4a05-9988-ce1a979a9f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982312895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2982312895 |
| Directory | /workspace/11.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3422012333 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2535481789 ps |
| CPU time | 5.1 seconds |
| Started | May 30 02:55:56 PM PDT 24 |
| Finished | May 30 02:56:03 PM PDT 24 |
| Peak memory | 192932 kb |
| Host | smart-b92a7675-789c-444b-b721-631c5c51bbde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422012333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao n_timer_same_csr_outstanding.3422012333 |
| Directory | /workspace/11.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1143752991 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 467879121 ps |
| CPU time | 2.17 seconds |
| Started | May 30 02:55:55 PM PDT 24 |
| Finished | May 30 02:56:00 PM PDT 24 |
| Peak memory | 198428 kb |
| Host | smart-e324a3fb-a7a5-4334-acd5-6d375ea5986f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143752991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1143752991 |
| Directory | /workspace/11.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3220376099 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 532264446 ps |
| CPU time | 1.13 seconds |
| Started | May 30 02:55:57 PM PDT 24 |
| Finished | May 30 02:56:01 PM PDT 24 |
| Peak memory | 197000 kb |
| Host | smart-edf3a37e-88bb-4068-809e-3d72bf2d1c23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220376099 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3220376099 |
| Directory | /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1042703714 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 347545015 ps |
| CPU time | 1.17 seconds |
| Started | May 30 02:55:57 PM PDT 24 |
| Finished | May 30 02:56:00 PM PDT 24 |
| Peak memory | 192144 kb |
| Host | smart-12108660-45a1-4dfb-a1f3-18758e75fadd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042703714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1042703714 |
| Directory | /workspace/12.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1201917365 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 432685794 ps |
| CPU time | 0.66 seconds |
| Started | May 30 02:55:56 PM PDT 24 |
| Finished | May 30 02:55:59 PM PDT 24 |
| Peak memory | 183620 kb |
| Host | smart-cee81f70-bf3b-475c-a752-2692f5333247 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201917365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1201917365 |
| Directory | /workspace/12.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2802447372 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2445243489 ps |
| CPU time | 3.5 seconds |
| Started | May 30 02:55:57 PM PDT 24 |
| Finished | May 30 02:56:03 PM PDT 24 |
| Peak memory | 194432 kb |
| Host | smart-c408119f-8fe8-41e1-aa51-13509e6c26e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802447372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao n_timer_same_csr_outstanding.2802447372 |
| Directory | /workspace/12.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1302389936 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 459779585 ps |
| CPU time | 1.76 seconds |
| Started | May 30 02:55:55 PM PDT 24 |
| Finished | May 30 02:55:59 PM PDT 24 |
| Peak memory | 198428 kb |
| Host | smart-75141fda-ac9c-43d4-9662-47dce413957a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302389936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1302389936 |
| Directory | /workspace/12.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1226082805 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4417448048 ps |
| CPU time | 4.56 seconds |
| Started | May 30 02:55:57 PM PDT 24 |
| Finished | May 30 02:56:04 PM PDT 24 |
| Peak memory | 197628 kb |
| Host | smart-89f79df9-3785-495c-bad0-6a55a171022c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226082805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t l_intg_err.1226082805 |
| Directory | /workspace/12.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2169731397 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 354916437 ps |
| CPU time | 0.75 seconds |
| Started | May 30 02:56:00 PM PDT 24 |
| Finished | May 30 02:56:02 PM PDT 24 |
| Peak memory | 195148 kb |
| Host | smart-178474dd-923a-4eb1-9de5-aeb82d7f0f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169731397 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2169731397 |
| Directory | /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2280127412 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 382994478 ps |
| CPU time | 1.21 seconds |
| Started | May 30 02:55:57 PM PDT 24 |
| Finished | May 30 02:56:01 PM PDT 24 |
| Peak memory | 193100 kb |
| Host | smart-20ef6a6d-0210-455e-8c2a-2933c592a5c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280127412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2280127412 |
| Directory | /workspace/13.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1588189172 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 517151652 ps |
| CPU time | 0.72 seconds |
| Started | May 30 02:55:56 PM PDT 24 |
| Finished | May 30 02:55:59 PM PDT 24 |
| Peak memory | 183596 kb |
| Host | smart-55bc3854-1ee8-4932-88e0-afbe1c93a39f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588189172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1588189172 |
| Directory | /workspace/13.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3828582298 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1207890952 ps |
| CPU time | 1.19 seconds |
| Started | May 30 02:55:58 PM PDT 24 |
| Finished | May 30 02:56:02 PM PDT 24 |
| Peak memory | 192896 kb |
| Host | smart-bcefbbf3-ee93-42a3-b0cd-36e4c0770952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828582298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao n_timer_same_csr_outstanding.3828582298 |
| Directory | /workspace/13.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.680375249 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 546225640 ps |
| CPU time | 1.81 seconds |
| Started | May 30 02:55:59 PM PDT 24 |
| Finished | May 30 02:56:03 PM PDT 24 |
| Peak memory | 198404 kb |
| Host | smart-81cf25da-5434-4de9-95d0-c408a533843a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680375249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.680375249 |
| Directory | /workspace/13.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.127880523 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3852327658 ps |
| CPU time | 6.67 seconds |
| Started | May 30 02:55:59 PM PDT 24 |
| Finished | May 30 02:56:08 PM PDT 24 |
| Peak memory | 197408 kb |
| Host | smart-e893d127-4d69-4734-8647-e0a0c1a30480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127880523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl _intg_err.127880523 |
| Directory | /workspace/13.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1251017495 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 405693788 ps |
| CPU time | 1.27 seconds |
| Started | May 30 02:56:12 PM PDT 24 |
| Finished | May 30 02:56:14 PM PDT 24 |
| Peak memory | 195792 kb |
| Host | smart-0d229177-0e46-4ec4-9d7c-cfc31b21c114 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251017495 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1251017495 |
| Directory | /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4250405766 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 436444214 ps |
| CPU time | 1.3 seconds |
| Started | May 30 02:56:12 PM PDT 24 |
| Finished | May 30 02:56:15 PM PDT 24 |
| Peak memory | 193104 kb |
| Host | smart-b77f590a-3f93-4198-8a1d-217571369711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250405766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.4250405766 |
| Directory | /workspace/14.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1888468381 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 393788688 ps |
| CPU time | 1.21 seconds |
| Started | May 30 02:55:58 PM PDT 24 |
| Finished | May 30 02:56:01 PM PDT 24 |
| Peak memory | 183628 kb |
| Host | smart-26f411e3-d7a8-4eca-ad28-d061e04ead24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888468381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1888468381 |
| Directory | /workspace/14.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2730229255 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 3076664354 ps |
| CPU time | 1.96 seconds |
| Started | May 30 02:56:13 PM PDT 24 |
| Finished | May 30 02:56:16 PM PDT 24 |
| Peak memory | 194888 kb |
| Host | smart-07ad7c97-fe02-4f0c-b6c0-3069f33f0fd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730229255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao n_timer_same_csr_outstanding.2730229255 |
| Directory | /workspace/14.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3151246008 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 407908130 ps |
| CPU time | 2.38 seconds |
| Started | May 30 02:55:58 PM PDT 24 |
| Finished | May 30 02:56:03 PM PDT 24 |
| Peak memory | 198404 kb |
| Host | smart-d686f04e-fd75-429b-80a8-322f0a4f4a5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151246008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3151246008 |
| Directory | /workspace/14.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.616398510 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 8269319201 ps |
| CPU time | 4.71 seconds |
| Started | May 30 02:55:59 PM PDT 24 |
| Finished | May 30 02:56:06 PM PDT 24 |
| Peak memory | 197824 kb |
| Host | smart-03f9188e-fe4d-415a-864a-c028b6cefb5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616398510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl _intg_err.616398510 |
| Directory | /workspace/14.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3142027683 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 773895022 ps |
| CPU time | 0.97 seconds |
| Started | May 30 02:56:13 PM PDT 24 |
| Finished | May 30 02:56:16 PM PDT 24 |
| Peak memory | 198360 kb |
| Host | smart-d6d33266-d0eb-4584-a54b-dae250c10999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142027683 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3142027683 |
| Directory | /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1865683599 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 453125755 ps |
| CPU time | 0.75 seconds |
| Started | May 30 02:56:13 PM PDT 24 |
| Finished | May 30 02:56:16 PM PDT 24 |
| Peak memory | 193068 kb |
| Host | smart-6adbdfd1-3ba3-47e0-ae0c-ab469defde0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865683599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1865683599 |
| Directory | /workspace/15.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1026407884 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 396838695 ps |
| CPU time | 1.16 seconds |
| Started | May 30 02:56:09 PM PDT 24 |
| Finished | May 30 02:56:11 PM PDT 24 |
| Peak memory | 183700 kb |
| Host | smart-42d82940-3e42-4502-9cf8-8787f8c1eb92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026407884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1026407884 |
| Directory | /workspace/15.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2854142853 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3002410305 ps |
| CPU time | 2.75 seconds |
| Started | May 30 02:56:14 PM PDT 24 |
| Finished | May 30 02:56:18 PM PDT 24 |
| Peak memory | 191984 kb |
| Host | smart-70ea0baa-0595-45e1-b8e1-6e36d3436958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854142853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao n_timer_same_csr_outstanding.2854142853 |
| Directory | /workspace/15.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1282578135 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 411849200 ps |
| CPU time | 1.76 seconds |
| Started | May 30 02:56:13 PM PDT 24 |
| Finished | May 30 02:56:16 PM PDT 24 |
| Peak memory | 198464 kb |
| Host | smart-c5f93a8c-d756-498d-9d59-b18830a31e19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282578135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1282578135 |
| Directory | /workspace/15.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4049856396 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 4188198433 ps |
| CPU time | 1.64 seconds |
| Started | May 30 02:56:11 PM PDT 24 |
| Finished | May 30 02:56:14 PM PDT 24 |
| Peak memory | 197564 kb |
| Host | smart-be485742-c8f5-4137-9e81-c767925cc8e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049856396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t l_intg_err.4049856396 |
| Directory | /workspace/15.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4173481864 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 338542752 ps |
| CPU time | 1.18 seconds |
| Started | May 30 02:56:12 PM PDT 24 |
| Finished | May 30 02:56:14 PM PDT 24 |
| Peak memory | 195428 kb |
| Host | smart-384c2f0a-9832-40a7-941c-725cc3246183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173481864 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.4173481864 |
| Directory | /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3041547918 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 416711184 ps |
| CPU time | 1.19 seconds |
| Started | May 30 02:56:11 PM PDT 24 |
| Finished | May 30 02:56:14 PM PDT 24 |
| Peak memory | 183748 kb |
| Host | smart-92bc3b99-e145-4176-a613-06ad22c10f08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041547918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3041547918 |
| Directory | /workspace/16.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3091101949 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 304766492 ps |
| CPU time | 1.04 seconds |
| Started | May 30 02:56:12 PM PDT 24 |
| Finished | May 30 02:56:14 PM PDT 24 |
| Peak memory | 183644 kb |
| Host | smart-c7ccc620-a2b1-4ea6-9df1-0ea592cdda52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091101949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3091101949 |
| Directory | /workspace/16.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.561284665 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 876006355 ps |
| CPU time | 1.72 seconds |
| Started | May 30 02:56:13 PM PDT 24 |
| Finished | May 30 02:56:16 PM PDT 24 |
| Peak memory | 192920 kb |
| Host | smart-86312681-a1c3-44e5-87f2-32ea10590548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561284665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon _timer_same_csr_outstanding.561284665 |
| Directory | /workspace/16.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4066294177 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 558729245 ps |
| CPU time | 1.39 seconds |
| Started | May 30 02:56:11 PM PDT 24 |
| Finished | May 30 02:56:14 PM PDT 24 |
| Peak memory | 198448 kb |
| Host | smart-539e8734-8eef-45d8-b526-27c09dadbec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066294177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4066294177 |
| Directory | /workspace/16.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2652702632 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 4213290407 ps |
| CPU time | 3.49 seconds |
| Started | May 30 02:56:10 PM PDT 24 |
| Finished | May 30 02:56:15 PM PDT 24 |
| Peak memory | 197356 kb |
| Host | smart-a8060aae-fea0-439d-97a7-0d9bb54a4074 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652702632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t l_intg_err.2652702632 |
| Directory | /workspace/16.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3930708443 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 572797429 ps |
| CPU time | 1.5 seconds |
| Started | May 30 02:56:11 PM PDT 24 |
| Finished | May 30 02:56:14 PM PDT 24 |
| Peak memory | 195856 kb |
| Host | smart-7c62e1a3-70a0-4d31-b212-ccf86ab15851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930708443 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3930708443 |
| Directory | /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.858862251 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 533953654 ps |
| CPU time | 0.72 seconds |
| Started | May 30 02:56:12 PM PDT 24 |
| Finished | May 30 02:56:14 PM PDT 24 |
| Peak memory | 192976 kb |
| Host | smart-bf07bec6-9794-4981-af20-3fa7e59ce03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858862251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.858862251 |
| Directory | /workspace/17.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.950849246 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 345228500 ps |
| CPU time | 0.67 seconds |
| Started | May 30 02:56:13 PM PDT 24 |
| Finished | May 30 02:56:15 PM PDT 24 |
| Peak memory | 183612 kb |
| Host | smart-02885425-6d99-43cf-a58b-9a5d2158a131 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950849246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.950849246 |
| Directory | /workspace/17.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.221961327 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2052420580 ps |
| CPU time | 2.17 seconds |
| Started | May 30 02:56:11 PM PDT 24 |
| Finished | May 30 02:56:14 PM PDT 24 |
| Peak memory | 194280 kb |
| Host | smart-8518f2b4-970b-4bce-bc01-e1ff44db0032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221961327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon _timer_same_csr_outstanding.221961327 |
| Directory | /workspace/17.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.70398765 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 448628369 ps |
| CPU time | 1.64 seconds |
| Started | May 30 02:56:14 PM PDT 24 |
| Finished | May 30 02:56:17 PM PDT 24 |
| Peak memory | 198368 kb |
| Host | smart-4a5f3a09-2c60-4e8e-a6c1-aa128b51e8ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70398765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.70398765 |
| Directory | /workspace/17.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1456110137 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 4179380957 ps |
| CPU time | 7.79 seconds |
| Started | May 30 02:56:13 PM PDT 24 |
| Finished | May 30 02:56:22 PM PDT 24 |
| Peak memory | 197780 kb |
| Host | smart-adfa5174-caa7-4ef3-8952-4e089486e65f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456110137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t l_intg_err.1456110137 |
| Directory | /workspace/17.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2705795090 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 474624903 ps |
| CPU time | 0.9 seconds |
| Started | May 30 02:56:23 PM PDT 24 |
| Finished | May 30 02:56:26 PM PDT 24 |
| Peak memory | 196676 kb |
| Host | smart-dd466698-187f-4421-a556-7463eeebdc9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705795090 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2705795090 |
| Directory | /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.637419864 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 415505498 ps |
| CPU time | 0.86 seconds |
| Started | May 30 02:56:24 PM PDT 24 |
| Finished | May 30 02:56:27 PM PDT 24 |
| Peak memory | 193156 kb |
| Host | smart-cd2a5491-e0ea-463d-88e8-4ec59edea4bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637419864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.637419864 |
| Directory | /workspace/18.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3319602214 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 416194991 ps |
| CPU time | 0.65 seconds |
| Started | May 30 02:56:23 PM PDT 24 |
| Finished | May 30 02:56:26 PM PDT 24 |
| Peak memory | 183652 kb |
| Host | smart-a0f7f73a-e756-4925-8149-eb7c49921112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319602214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3319602214 |
| Directory | /workspace/18.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.148196567 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1412447664 ps |
| CPU time | 3.36 seconds |
| Started | May 30 02:56:23 PM PDT 24 |
| Finished | May 30 02:56:28 PM PDT 24 |
| Peak memory | 193736 kb |
| Host | smart-40ea03b1-15a8-4f5b-82a8-805dcdc38955 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148196567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon _timer_same_csr_outstanding.148196567 |
| Directory | /workspace/18.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.46323711 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 869025032 ps |
| CPU time | 1.86 seconds |
| Started | May 30 02:56:21 PM PDT 24 |
| Finished | May 30 02:56:24 PM PDT 24 |
| Peak memory | 198460 kb |
| Host | smart-196c770a-e941-4eaa-9b5d-58a13901a324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46323711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.46323711 |
| Directory | /workspace/18.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3052720624 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 8204436328 ps |
| CPU time | 12.23 seconds |
| Started | May 30 02:56:22 PM PDT 24 |
| Finished | May 30 02:56:36 PM PDT 24 |
| Peak memory | 197948 kb |
| Host | smart-63dc11e2-301a-4d91-a100-1b74a1c0c0a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052720624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t l_intg_err.3052720624 |
| Directory | /workspace/18.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3621782078 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 551246748 ps |
| CPU time | 1.52 seconds |
| Started | May 30 02:56:26 PM PDT 24 |
| Finished | May 30 02:56:30 PM PDT 24 |
| Peak memory | 196508 kb |
| Host | smart-899ebd57-fd06-4844-bab2-9713250bc7c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621782078 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3621782078 |
| Directory | /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2976950712 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 483448840 ps |
| CPU time | 0.89 seconds |
| Started | May 30 02:56:24 PM PDT 24 |
| Finished | May 30 02:56:27 PM PDT 24 |
| Peak memory | 191960 kb |
| Host | smart-1be120d7-d0cb-4c85-bb12-da4065609f73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976950712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2976950712 |
| Directory | /workspace/19.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2740621946 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 386111139 ps |
| CPU time | 0.68 seconds |
| Started | May 30 02:56:23 PM PDT 24 |
| Finished | May 30 02:56:26 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-e616a921-7514-4274-bd2b-1f2cf6613d58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740621946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2740621946 |
| Directory | /workspace/19.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1062781848 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 994898177 ps |
| CPU time | 1.39 seconds |
| Started | May 30 02:56:21 PM PDT 24 |
| Finished | May 30 02:56:23 PM PDT 24 |
| Peak memory | 193400 kb |
| Host | smart-b48fbf19-026e-4028-ba37-01e5cad22aee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062781848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao n_timer_same_csr_outstanding.1062781848 |
| Directory | /workspace/19.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3389405911 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 548650791 ps |
| CPU time | 2.19 seconds |
| Started | May 30 02:56:26 PM PDT 24 |
| Finished | May 30 02:56:30 PM PDT 24 |
| Peak memory | 198440 kb |
| Host | smart-8cfc17ff-d6be-407d-96c0-86c3fcc4c926 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389405911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3389405911 |
| Directory | /workspace/19.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2726986224 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 8325598451 ps |
| CPU time | 14.94 seconds |
| Started | May 30 02:56:21 PM PDT 24 |
| Finished | May 30 02:56:37 PM PDT 24 |
| Peak memory | 198128 kb |
| Host | smart-f8f8b7d7-a5e3-44e3-aa0e-dd43f6399145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726986224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t l_intg_err.2726986224 |
| Directory | /workspace/19.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4233576981 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 562542034 ps |
| CPU time | 0.94 seconds |
| Started | May 30 02:55:28 PM PDT 24 |
| Finished | May 30 02:55:30 PM PDT 24 |
| Peak memory | 183648 kb |
| Host | smart-ba3a5f73-db83-47bb-abc2-c904a9920dd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233576981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a liasing.4233576981 |
| Directory | /workspace/2.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1470380385 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 7337178704 ps |
| CPU time | 20.94 seconds |
| Started | May 30 02:55:05 PM PDT 24 |
| Finished | May 30 02:55:27 PM PDT 24 |
| Peak memory | 192144 kb |
| Host | smart-fa6e7bcc-5d10-415d-bd86-a59d0957b4ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470380385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b it_bash.1470380385 |
| Directory | /workspace/2.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3929221350 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 828569910 ps |
| CPU time | 0.67 seconds |
| Started | May 30 02:55:05 PM PDT 24 |
| Finished | May 30 02:55:07 PM PDT 24 |
| Peak memory | 183728 kb |
| Host | smart-c478d199-e47d-4935-97ee-fe2a8ad8a779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929221350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h w_reset.3929221350 |
| Directory | /workspace/2.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.262988089 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 534773400 ps |
| CPU time | 1.02 seconds |
| Started | May 30 02:55:25 PM PDT 24 |
| Finished | May 30 02:55:27 PM PDT 24 |
| Peak memory | 196128 kb |
| Host | smart-590c4db4-f9ec-4bbb-89d3-8b752b5500d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262988089 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.262988089 |
| Directory | /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2957640013 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 446540440 ps |
| CPU time | 0.93 seconds |
| Started | May 30 02:55:06 PM PDT 24 |
| Finished | May 30 02:55:08 PM PDT 24 |
| Peak memory | 193932 kb |
| Host | smart-6afbaa27-8a2d-4c54-bfb2-049cd941e05b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957640013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2957640013 |
| Directory | /workspace/2.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2335026143 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 377762353 ps |
| CPU time | 0.7 seconds |
| Started | May 30 02:55:04 PM PDT 24 |
| Finished | May 30 02:55:06 PM PDT 24 |
| Peak memory | 183652 kb |
| Host | smart-b65f524d-2678-4a91-8e76-ad617e0670d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335026143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2335026143 |
| Directory | /workspace/2.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3641689172 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 435224063 ps |
| CPU time | 1.15 seconds |
| Started | May 30 02:55:07 PM PDT 24 |
| Finished | May 30 02:55:09 PM PDT 24 |
| Peak memory | 183580 kb |
| Host | smart-61a15a11-23df-4aac-925c-e42541916b05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641689172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t imer_mem_partial_access.3641689172 |
| Directory | /workspace/2.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3011200198 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 456402576 ps |
| CPU time | 0.57 seconds |
| Started | May 30 02:55:05 PM PDT 24 |
| Finished | May 30 02:55:07 PM PDT 24 |
| Peak memory | 183604 kb |
| Host | smart-cf2fbc9c-e0ba-4c05-9506-056eaddea277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011200198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w alk.3011200198 |
| Directory | /workspace/2.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.594050366 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1502698891 ps |
| CPU time | 1.17 seconds |
| Started | May 30 02:55:26 PM PDT 24 |
| Finished | May 30 02:55:28 PM PDT 24 |
| Peak memory | 192892 kb |
| Host | smart-18d3c500-2068-41c8-b573-5d2d0abdb316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594050366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ timer_same_csr_outstanding.594050366 |
| Directory | /workspace/2.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1949288257 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 503652506 ps |
| CPU time | 2.38 seconds |
| Started | May 30 02:55:05 PM PDT 24 |
| Finished | May 30 02:55:08 PM PDT 24 |
| Peak memory | 198456 kb |
| Host | smart-2b9011e8-52f0-4b7b-8965-de15b12b1489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949288257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1949288257 |
| Directory | /workspace/2.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2945550221 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 500897265 ps |
| CPU time | 0.75 seconds |
| Started | May 30 02:56:24 PM PDT 24 |
| Finished | May 30 02:56:27 PM PDT 24 |
| Peak memory | 183624 kb |
| Host | smart-714caf75-1443-45ed-bd06-2ff3d452f187 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945550221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2945550221 |
| Directory | /workspace/20.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3952825848 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 533585124 ps |
| CPU time | 0.78 seconds |
| Started | May 30 02:56:21 PM PDT 24 |
| Finished | May 30 02:56:23 PM PDT 24 |
| Peak memory | 183644 kb |
| Host | smart-7bf1ff3d-406a-4afd-8683-60b5d8270f0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952825848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3952825848 |
| Directory | /workspace/21.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1662020852 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 332110577 ps |
| CPU time | 0.65 seconds |
| Started | May 30 02:56:22 PM PDT 24 |
| Finished | May 30 02:56:25 PM PDT 24 |
| Peak memory | 183596 kb |
| Host | smart-76d5c0d8-3c26-4eda-9e20-d7a54e8a7934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662020852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1662020852 |
| Directory | /workspace/22.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2674122079 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 352914250 ps |
| CPU time | 1.14 seconds |
| Started | May 30 02:56:22 PM PDT 24 |
| Finished | May 30 02:56:25 PM PDT 24 |
| Peak memory | 183648 kb |
| Host | smart-be4a51bd-b7cd-4848-9fa6-81b4d73f6a9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674122079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2674122079 |
| Directory | /workspace/23.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3174309327 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 412396949 ps |
| CPU time | 1.18 seconds |
| Started | May 30 02:56:22 PM PDT 24 |
| Finished | May 30 02:56:25 PM PDT 24 |
| Peak memory | 183624 kb |
| Host | smart-6f88311b-66ab-4b71-b48f-0b8f1b852580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174309327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3174309327 |
| Directory | /workspace/24.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1207205707 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 289230087 ps |
| CPU time | 0.79 seconds |
| Started | May 30 02:56:22 PM PDT 24 |
| Finished | May 30 02:56:24 PM PDT 24 |
| Peak memory | 183608 kb |
| Host | smart-f6daea0f-4a83-42e9-8eae-0652e6e43c69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207205707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1207205707 |
| Directory | /workspace/25.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3384769762 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 461465882 ps |
| CPU time | 0.71 seconds |
| Started | May 30 02:56:23 PM PDT 24 |
| Finished | May 30 02:56:26 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-d2125147-f22d-40e1-b1b2-4c88f3a49f20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384769762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3384769762 |
| Directory | /workspace/26.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4294501440 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 391631457 ps |
| CPU time | 0.65 seconds |
| Started | May 30 02:56:26 PM PDT 24 |
| Finished | May 30 02:56:29 PM PDT 24 |
| Peak memory | 183608 kb |
| Host | smart-ba07a95e-1446-4071-815b-83cf532a7f71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294501440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.4294501440 |
| Directory | /workspace/27.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.912253841 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 377015818 ps |
| CPU time | 1.04 seconds |
| Started | May 30 02:56:22 PM PDT 24 |
| Finished | May 30 02:56:24 PM PDT 24 |
| Peak memory | 183652 kb |
| Host | smart-a084c514-f7c4-45b3-a35a-d61dd8d36a01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912253841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.912253841 |
| Directory | /workspace/28.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4083138200 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 306108504 ps |
| CPU time | 0.7 seconds |
| Started | May 30 02:56:24 PM PDT 24 |
| Finished | May 30 02:56:27 PM PDT 24 |
| Peak memory | 183660 kb |
| Host | smart-9a8a9ec0-9ed7-4ddb-ac21-e267157bfcfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083138200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4083138200 |
| Directory | /workspace/29.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.568400196 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 354856209 ps |
| CPU time | 1.22 seconds |
| Started | May 30 02:55:25 PM PDT 24 |
| Finished | May 30 02:55:27 PM PDT 24 |
| Peak memory | 193168 kb |
| Host | smart-5553673d-3e1b-4cee-912a-4029f98763e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568400196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al iasing.568400196 |
| Directory | /workspace/3.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3966384619 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 6921118115 ps |
| CPU time | 10.04 seconds |
| Started | May 30 02:55:27 PM PDT 24 |
| Finished | May 30 02:55:38 PM PDT 24 |
| Peak memory | 192148 kb |
| Host | smart-13be2b38-a313-4b67-a700-0622a7d3cfec |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966384619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b it_bash.3966384619 |
| Directory | /workspace/3.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2985657632 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1142493245 ps |
| CPU time | 2.44 seconds |
| Started | May 30 02:55:26 PM PDT 24 |
| Finished | May 30 02:55:29 PM PDT 24 |
| Peak memory | 183680 kb |
| Host | smart-02cfa0d1-afaa-458f-a128-dd4a0485f0aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985657632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h w_reset.2985657632 |
| Directory | /workspace/3.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2320310402 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 385361327 ps |
| CPU time | 1.16 seconds |
| Started | May 30 02:55:27 PM PDT 24 |
| Finished | May 30 02:55:29 PM PDT 24 |
| Peak memory | 195524 kb |
| Host | smart-f7673848-1ab1-484c-ac88-1124275d6dbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320310402 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2320310402 |
| Directory | /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3554408731 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 542096581 ps |
| CPU time | 1.37 seconds |
| Started | May 30 02:55:27 PM PDT 24 |
| Finished | May 30 02:55:30 PM PDT 24 |
| Peak memory | 193000 kb |
| Host | smart-e2db9e92-8e40-4f28-9392-37d5e91f242a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554408731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3554408731 |
| Directory | /workspace/3.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3950137083 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 336590561 ps |
| CPU time | 0.6 seconds |
| Started | May 30 02:55:26 PM PDT 24 |
| Finished | May 30 02:55:28 PM PDT 24 |
| Peak memory | 183612 kb |
| Host | smart-6f663fbd-c029-41ed-88ac-4892bc9cc2dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950137083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3950137083 |
| Directory | /workspace/3.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4221571298 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 538106795 ps |
| CPU time | 0.59 seconds |
| Started | May 30 02:55:28 PM PDT 24 |
| Finished | May 30 02:55:30 PM PDT 24 |
| Peak memory | 183504 kb |
| Host | smart-de4a121e-e239-4eb3-9eec-6f0bb3b32706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221571298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t imer_mem_partial_access.4221571298 |
| Directory | /workspace/3.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2005496199 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 512882801 ps |
| CPU time | 1.26 seconds |
| Started | May 30 02:55:25 PM PDT 24 |
| Finished | May 30 02:55:27 PM PDT 24 |
| Peak memory | 183628 kb |
| Host | smart-1dae437c-a3e9-4c73-a07d-c2750d22e6e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005496199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w alk.2005496199 |
| Directory | /workspace/3.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3574367077 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2294160537 ps |
| CPU time | 2.5 seconds |
| Started | May 30 02:55:27 PM PDT 24 |
| Finished | May 30 02:55:31 PM PDT 24 |
| Peak memory | 194880 kb |
| Host | smart-01c404b1-a91f-4825-8348-33d9a4e5a332 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574367077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon _timer_same_csr_outstanding.3574367077 |
| Directory | /workspace/3.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.395543241 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 421968850 ps |
| CPU time | 1 seconds |
| Started | May 30 02:55:28 PM PDT 24 |
| Finished | May 30 02:55:30 PM PDT 24 |
| Peak memory | 198032 kb |
| Host | smart-573aee6e-e710-4891-a82b-40d58ea1d1a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395543241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.395543241 |
| Directory | /workspace/3.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3296567236 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 4235050169 ps |
| CPU time | 7.74 seconds |
| Started | May 30 02:55:26 PM PDT 24 |
| Finished | May 30 02:55:34 PM PDT 24 |
| Peak memory | 197560 kb |
| Host | smart-3cb48269-07c7-4418-b896-c517cd967567 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296567236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl _intg_err.3296567236 |
| Directory | /workspace/3.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1760033819 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 436709287 ps |
| CPU time | 1.17 seconds |
| Started | May 30 02:56:21 PM PDT 24 |
| Finished | May 30 02:56:23 PM PDT 24 |
| Peak memory | 183720 kb |
| Host | smart-b7882a2f-1251-46e0-91bc-d1ed68f7b7d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760033819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1760033819 |
| Directory | /workspace/30.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3155054009 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 394109612 ps |
| CPU time | 1.16 seconds |
| Started | May 30 02:56:24 PM PDT 24 |
| Finished | May 30 02:56:28 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-c48fb964-ec3a-48b0-8637-6767404ccd05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155054009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3155054009 |
| Directory | /workspace/31.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1675990628 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 406052306 ps |
| CPU time | 0.69 seconds |
| Started | May 30 02:56:22 PM PDT 24 |
| Finished | May 30 02:56:25 PM PDT 24 |
| Peak memory | 183624 kb |
| Host | smart-ebcbe0d2-c79c-4b36-91a4-4a0b7caedd32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675990628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1675990628 |
| Directory | /workspace/32.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.750406910 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 522011207 ps |
| CPU time | 0.77 seconds |
| Started | May 30 02:56:21 PM PDT 24 |
| Finished | May 30 02:56:23 PM PDT 24 |
| Peak memory | 183632 kb |
| Host | smart-407d3b51-dc79-4d69-bdfd-78c067b202d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750406910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.750406910 |
| Directory | /workspace/33.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2564121302 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 324639239 ps |
| CPU time | 0.76 seconds |
| Started | May 30 02:56:22 PM PDT 24 |
| Finished | May 30 02:56:25 PM PDT 24 |
| Peak memory | 183652 kb |
| Host | smart-c8e17155-6c07-4feb-9826-2531805f14ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564121302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2564121302 |
| Directory | /workspace/34.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3301380037 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 387095046 ps |
| CPU time | 1.14 seconds |
| Started | May 30 02:56:23 PM PDT 24 |
| Finished | May 30 02:56:26 PM PDT 24 |
| Peak memory | 183644 kb |
| Host | smart-e973438f-227f-479a-af45-d97e400a4fa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301380037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3301380037 |
| Directory | /workspace/35.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.354933844 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 481916495 ps |
| CPU time | 0.98 seconds |
| Started | May 30 02:56:22 PM PDT 24 |
| Finished | May 30 02:56:26 PM PDT 24 |
| Peak memory | 183644 kb |
| Host | smart-7af4c7b4-c36e-451c-a237-b34cdc6f91ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354933844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.354933844 |
| Directory | /workspace/36.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3397659720 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 489286604 ps |
| CPU time | 1.36 seconds |
| Started | May 30 02:56:24 PM PDT 24 |
| Finished | May 30 02:56:28 PM PDT 24 |
| Peak memory | 183620 kb |
| Host | smart-605a1d02-520c-433d-b082-e14d204b7c91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397659720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3397659720 |
| Directory | /workspace/37.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2928018686 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 384534211 ps |
| CPU time | 0.61 seconds |
| Started | May 30 02:56:24 PM PDT 24 |
| Finished | May 30 02:56:27 PM PDT 24 |
| Peak memory | 182728 kb |
| Host | smart-47817c79-9fb3-4514-9d5f-e380796d111f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928018686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2928018686 |
| Directory | /workspace/38.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1598592270 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 285616934 ps |
| CPU time | 0.98 seconds |
| Started | May 30 02:56:24 PM PDT 24 |
| Finished | May 30 02:56:27 PM PDT 24 |
| Peak memory | 183568 kb |
| Host | smart-a9967031-e6e7-43b0-aab5-1e7f4f3a1e0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598592270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1598592270 |
| Directory | /workspace/39.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3788260423 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 500504462 ps |
| CPU time | 1.58 seconds |
| Started | May 30 02:55:35 PM PDT 24 |
| Finished | May 30 02:55:39 PM PDT 24 |
| Peak memory | 183704 kb |
| Host | smart-50aa1499-faf4-490f-9db4-168229edb4a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788260423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a liasing.3788260423 |
| Directory | /workspace/4.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.447690548 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 7121461731 ps |
| CPU time | 11.32 seconds |
| Started | May 30 02:55:35 PM PDT 24 |
| Finished | May 30 02:55:48 PM PDT 24 |
| Peak memory | 192100 kb |
| Host | smart-e37d516a-96fa-44b2-9987-b4ad9ca3d76a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447690548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi t_bash.447690548 |
| Directory | /workspace/4.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.921226179 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 863408898 ps |
| CPU time | 1.84 seconds |
| Started | May 30 02:55:35 PM PDT 24 |
| Finished | May 30 02:55:39 PM PDT 24 |
| Peak memory | 183712 kb |
| Host | smart-8fe7588a-47a5-4c9e-b176-9543cbf6af2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921226179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw _reset.921226179 |
| Directory | /workspace/4.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1572519405 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 429612059 ps |
| CPU time | 0.85 seconds |
| Started | May 30 02:55:35 PM PDT 24 |
| Finished | May 30 02:55:37 PM PDT 24 |
| Peak memory | 195432 kb |
| Host | smart-da7174d8-e315-4185-8b4d-13617ff59106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572519405 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1572519405 |
| Directory | /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4177963023 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 272696958 ps |
| CPU time | 1.01 seconds |
| Started | May 30 02:55:28 PM PDT 24 |
| Finished | May 30 02:55:30 PM PDT 24 |
| Peak memory | 183588 kb |
| Host | smart-51754bf1-44a7-4ad3-a27c-95f6efa6eb6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177963023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.4177963023 |
| Directory | /workspace/4.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1286465445 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 493780492 ps |
| CPU time | 1.29 seconds |
| Started | May 30 02:55:25 PM PDT 24 |
| Finished | May 30 02:55:27 PM PDT 24 |
| Peak memory | 183612 kb |
| Host | smart-c511260e-f3a4-402a-b8e3-aa52c0d39553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286465445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t imer_mem_partial_access.1286465445 |
| Directory | /workspace/4.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.100321338 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 413654886 ps |
| CPU time | 0.83 seconds |
| Started | May 30 02:55:26 PM PDT 24 |
| Finished | May 30 02:55:28 PM PDT 24 |
| Peak memory | 183604 kb |
| Host | smart-958c7e9c-17ef-4597-ac27-a0bc884e9ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100321338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa lk.100321338 |
| Directory | /workspace/4.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3212679511 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2050152544 ps |
| CPU time | 4.18 seconds |
| Started | May 30 02:55:35 PM PDT 24 |
| Finished | May 30 02:55:42 PM PDT 24 |
| Peak memory | 183788 kb |
| Host | smart-66f501ed-e927-47af-bdc0-ddf591fb2be1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212679511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon _timer_same_csr_outstanding.3212679511 |
| Directory | /workspace/4.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.658898063 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 452915959 ps |
| CPU time | 2.77 seconds |
| Started | May 30 02:55:27 PM PDT 24 |
| Finished | May 30 02:55:31 PM PDT 24 |
| Peak memory | 198372 kb |
| Host | smart-8b177ece-2e26-4014-85ec-00c6ca350025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658898063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.658898063 |
| Directory | /workspace/4.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1957932372 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4107902882 ps |
| CPU time | 4.18 seconds |
| Started | May 30 02:55:26 PM PDT 24 |
| Finished | May 30 02:55:31 PM PDT 24 |
| Peak memory | 197408 kb |
| Host | smart-193648f9-0967-42e8-9bd0-147fc52b7b5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957932372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl _intg_err.1957932372 |
| Directory | /workspace/4.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3175945383 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 488056024 ps |
| CPU time | 0.86 seconds |
| Started | May 30 02:56:22 PM PDT 24 |
| Finished | May 30 02:56:24 PM PDT 24 |
| Peak memory | 183652 kb |
| Host | smart-f82be309-790f-461e-8ac6-37e976f3dc38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175945383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3175945383 |
| Directory | /workspace/40.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3613360146 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 333358379 ps |
| CPU time | 1.03 seconds |
| Started | May 30 02:56:24 PM PDT 24 |
| Finished | May 30 02:56:27 PM PDT 24 |
| Peak memory | 183640 kb |
| Host | smart-c05114d8-5dc1-4cd9-9462-08464964bbc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613360146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3613360146 |
| Directory | /workspace/41.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1223648091 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 367443905 ps |
| CPU time | 0.58 seconds |
| Started | May 30 02:56:24 PM PDT 24 |
| Finished | May 30 02:56:27 PM PDT 24 |
| Peak memory | 183568 kb |
| Host | smart-06d0e7dd-de29-4198-93a2-f699b5381a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223648091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1223648091 |
| Directory | /workspace/42.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2163827380 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 280623861 ps |
| CPU time | 0.66 seconds |
| Started | May 30 02:56:24 PM PDT 24 |
| Finished | May 30 02:56:27 PM PDT 24 |
| Peak memory | 182680 kb |
| Host | smart-f48a1f0b-71a1-4797-98be-c805b921c48e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163827380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2163827380 |
| Directory | /workspace/43.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2827387709 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 420069264 ps |
| CPU time | 1.21 seconds |
| Started | May 30 02:56:40 PM PDT 24 |
| Finished | May 30 02:56:43 PM PDT 24 |
| Peak memory | 183612 kb |
| Host | smart-01080689-1bc8-4080-a5ea-1f4796eb4b54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827387709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2827387709 |
| Directory | /workspace/44.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2674172410 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 428445478 ps |
| CPU time | 1.18 seconds |
| Started | May 30 02:56:39 PM PDT 24 |
| Finished | May 30 02:56:42 PM PDT 24 |
| Peak memory | 183652 kb |
| Host | smart-841f0e96-b48b-49a8-b0d1-bfb404d399b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674172410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2674172410 |
| Directory | /workspace/45.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.755576297 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 323007256 ps |
| CPU time | 1.08 seconds |
| Started | May 30 02:56:39 PM PDT 24 |
| Finished | May 30 02:56:41 PM PDT 24 |
| Peak memory | 183632 kb |
| Host | smart-0e6cf52a-37fa-4007-808c-0f2bee24e08b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755576297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.755576297 |
| Directory | /workspace/46.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1060307048 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 507185844 ps |
| CPU time | 0.7 seconds |
| Started | May 30 02:56:38 PM PDT 24 |
| Finished | May 30 02:56:40 PM PDT 24 |
| Peak memory | 183624 kb |
| Host | smart-6d9c4709-c46d-4a56-b3c8-e8eb690fd746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060307048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1060307048 |
| Directory | /workspace/47.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.12752229 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 291189343 ps |
| CPU time | 0.82 seconds |
| Started | May 30 02:56:41 PM PDT 24 |
| Finished | May 30 02:56:43 PM PDT 24 |
| Peak memory | 183608 kb |
| Host | smart-ab67924e-c0b3-43e5-aff7-f9e4bf2f0e31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12752229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.12752229 |
| Directory | /workspace/48.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1041749782 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 399025809 ps |
| CPU time | 0.72 seconds |
| Started | May 30 02:56:39 PM PDT 24 |
| Finished | May 30 02:56:41 PM PDT 24 |
| Peak memory | 183652 kb |
| Host | smart-427bea24-7645-4414-b06e-2c763745bcff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041749782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1041749782 |
| Directory | /workspace/49.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3836440890 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 486986611 ps |
| CPU time | 1.37 seconds |
| Started | May 30 02:55:37 PM PDT 24 |
| Finished | May 30 02:55:41 PM PDT 24 |
| Peak memory | 194944 kb |
| Host | smart-756ebfbe-b98b-4ab2-979b-40123fba544c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836440890 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3836440890 |
| Directory | /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3033522756 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 574364576 ps |
| CPU time | 0.75 seconds |
| Started | May 30 02:55:35 PM PDT 24 |
| Finished | May 30 02:55:38 PM PDT 24 |
| Peak memory | 193152 kb |
| Host | smart-27f2d049-bd43-4f79-ad37-2547558a8475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033522756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3033522756 |
| Directory | /workspace/5.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1957943974 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 292259100 ps |
| CPU time | 0.93 seconds |
| Started | May 30 02:55:35 PM PDT 24 |
| Finished | May 30 02:55:38 PM PDT 24 |
| Peak memory | 183600 kb |
| Host | smart-2fe0cb94-951a-4a03-82e4-b336a8e9c7dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957943974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1957943974 |
| Directory | /workspace/5.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3862665140 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1416203811 ps |
| CPU time | 2.55 seconds |
| Started | May 30 02:55:37 PM PDT 24 |
| Finished | May 30 02:55:42 PM PDT 24 |
| Peak memory | 183716 kb |
| Host | smart-11b590be-157f-4733-a186-6d46d9b6d2d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862665140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon _timer_same_csr_outstanding.3862665140 |
| Directory | /workspace/5.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1874286316 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 529347971 ps |
| CPU time | 2.36 seconds |
| Started | May 30 02:55:35 PM PDT 24 |
| Finished | May 30 02:55:39 PM PDT 24 |
| Peak memory | 198476 kb |
| Host | smart-d041be6b-75c9-4f2a-8bc0-733641de8274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874286316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1874286316 |
| Directory | /workspace/5.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3192016007 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4487051332 ps |
| CPU time | 8.38 seconds |
| Started | May 30 02:55:37 PM PDT 24 |
| Finished | May 30 02:55:47 PM PDT 24 |
| Peak memory | 196492 kb |
| Host | smart-9d5baa6d-97b4-49f4-8963-0bc1413eba2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192016007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl _intg_err.3192016007 |
| Directory | /workspace/5.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3088296412 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 597711209 ps |
| CPU time | 0.88 seconds |
| Started | May 30 02:55:37 PM PDT 24 |
| Finished | May 30 02:55:40 PM PDT 24 |
| Peak memory | 195800 kb |
| Host | smart-eea9a18e-681d-4269-9f09-ca9f66df58f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088296412 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3088296412 |
| Directory | /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1556912355 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 505130876 ps |
| CPU time | 0.66 seconds |
| Started | May 30 02:55:36 PM PDT 24 |
| Finished | May 30 02:55:38 PM PDT 24 |
| Peak memory | 192992 kb |
| Host | smart-28ff4c0e-280a-4c89-a918-1f075d687c62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556912355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1556912355 |
| Directory | /workspace/6.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2182807571 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 480602820 ps |
| CPU time | 1.27 seconds |
| Started | May 30 02:55:38 PM PDT 24 |
| Finished | May 30 02:55:41 PM PDT 24 |
| Peak memory | 183584 kb |
| Host | smart-e4e73030-50fb-46d2-9530-d99bba95e608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182807571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2182807571 |
| Directory | /workspace/6.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.747572581 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2508037053 ps |
| CPU time | 2.5 seconds |
| Started | May 30 02:55:38 PM PDT 24 |
| Finished | May 30 02:55:42 PM PDT 24 |
| Peak memory | 194304 kb |
| Host | smart-2ad0ba93-8691-4c1d-8e92-89fdd40de5eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747572581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_ timer_same_csr_outstanding.747572581 |
| Directory | /workspace/6.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.506262271 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 492684906 ps |
| CPU time | 1.46 seconds |
| Started | May 30 02:55:36 PM PDT 24 |
| Finished | May 30 02:55:40 PM PDT 24 |
| Peak memory | 198376 kb |
| Host | smart-854075ec-3426-4bd7-ac10-04d6583a3eb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506262271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.506262271 |
| Directory | /workspace/6.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1772517856 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4590338395 ps |
| CPU time | 2.23 seconds |
| Started | May 30 02:55:36 PM PDT 24 |
| Finished | May 30 02:55:40 PM PDT 24 |
| Peak memory | 196712 kb |
| Host | smart-b4501186-cbfd-49c4-ab8e-9581dad5aad6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772517856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl _intg_err.1772517856 |
| Directory | /workspace/6.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.64613689 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 419134126 ps |
| CPU time | 1.04 seconds |
| Started | May 30 02:55:44 PM PDT 24 |
| Finished | May 30 02:55:46 PM PDT 24 |
| Peak memory | 195288 kb |
| Host | smart-1dbab718-fa81-4023-9038-e9442dace23b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64613689 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.64613689 |
| Directory | /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4161872914 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 438353016 ps |
| CPU time | 0.72 seconds |
| Started | May 30 02:55:48 PM PDT 24 |
| Finished | May 30 02:55:50 PM PDT 24 |
| Peak memory | 183772 kb |
| Host | smart-eb5dc404-1164-485a-8e59-0ff13d4b0537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161872914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.4161872914 |
| Directory | /workspace/7.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1189832306 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 310321172 ps |
| CPU time | 0.96 seconds |
| Started | May 30 02:55:38 PM PDT 24 |
| Finished | May 30 02:55:41 PM PDT 24 |
| Peak memory | 183632 kb |
| Host | smart-e44f7f94-ad7b-41ca-b547-2b88d1722bac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189832306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1189832306 |
| Directory | /workspace/7.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1491508082 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1895151026 ps |
| CPU time | 3.28 seconds |
| Started | May 30 02:55:45 PM PDT 24 |
| Finished | May 30 02:55:50 PM PDT 24 |
| Peak memory | 194840 kb |
| Host | smart-5fd94e33-aab3-49aa-b5e4-083098f1620f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491508082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon _timer_same_csr_outstanding.1491508082 |
| Directory | /workspace/7.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.371222262 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 549001548 ps |
| CPU time | 1.5 seconds |
| Started | May 30 02:55:37 PM PDT 24 |
| Finished | May 30 02:55:41 PM PDT 24 |
| Peak memory | 198296 kb |
| Host | smart-74dbbf81-9ccf-4708-8225-f6f5b8ec5cb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371222262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.371222262 |
| Directory | /workspace/7.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1224368099 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4235445802 ps |
| CPU time | 7.26 seconds |
| Started | May 30 02:55:37 PM PDT 24 |
| Finished | May 30 02:55:47 PM PDT 24 |
| Peak memory | 197428 kb |
| Host | smart-e4b0bba3-7e66-4780-b7f5-b6a03eb4683f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224368099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl _intg_err.1224368099 |
| Directory | /workspace/7.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1740130836 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 551234782 ps |
| CPU time | 0.99 seconds |
| Started | May 30 02:55:45 PM PDT 24 |
| Finished | May 30 02:55:48 PM PDT 24 |
| Peak memory | 198256 kb |
| Host | smart-2bd2e16e-1d6f-4c64-99a4-20ee3b61aba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740130836 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1740130836 |
| Directory | /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2716731898 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 482350440 ps |
| CPU time | 0.92 seconds |
| Started | May 30 02:55:45 PM PDT 24 |
| Finished | May 30 02:55:47 PM PDT 24 |
| Peak memory | 192980 kb |
| Host | smart-0311f8b1-3356-4c35-a285-b2aa600db6e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716731898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2716731898 |
| Directory | /workspace/8.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.401175471 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 482848396 ps |
| CPU time | 0.62 seconds |
| Started | May 30 02:55:44 PM PDT 24 |
| Finished | May 30 02:55:47 PM PDT 24 |
| Peak memory | 183628 kb |
| Host | smart-10d64578-53a8-42f7-a28a-9314d0f6b715 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401175471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.401175471 |
| Directory | /workspace/8.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4082035350 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2384807965 ps |
| CPU time | 2.25 seconds |
| Started | May 30 02:55:48 PM PDT 24 |
| Finished | May 30 02:55:52 PM PDT 24 |
| Peak memory | 193968 kb |
| Host | smart-61356f1b-188d-4560-b94e-8efe8742e6d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082035350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon _timer_same_csr_outstanding.4082035350 |
| Directory | /workspace/8.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1859876614 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 303057287 ps |
| CPU time | 1.46 seconds |
| Started | May 30 02:55:42 PM PDT 24 |
| Finished | May 30 02:55:45 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-cfb02b97-eee5-4f1b-b0d0-d36dc7136d64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859876614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1859876614 |
| Directory | /workspace/8.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3064995160 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 8201007758 ps |
| CPU time | 4.13 seconds |
| Started | May 30 02:55:45 PM PDT 24 |
| Finished | May 30 02:55:51 PM PDT 24 |
| Peak memory | 198132 kb |
| Host | smart-4caf7172-fde2-4aec-8161-8da4b9b3d11e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064995160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl _intg_err.3064995160 |
| Directory | /workspace/8.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.942326150 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 652486089 ps |
| CPU time | 0.93 seconds |
| Started | May 30 02:55:45 PM PDT 24 |
| Finished | May 30 02:55:48 PM PDT 24 |
| Peak memory | 196404 kb |
| Host | smart-54357b84-4f34-488c-8978-7a8c979cf123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942326150 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.942326150 |
| Directory | /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.437413821 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 531118437 ps |
| CPU time | 1.44 seconds |
| Started | May 30 02:55:46 PM PDT 24 |
| Finished | May 30 02:55:49 PM PDT 24 |
| Peak memory | 193076 kb |
| Host | smart-ffb45563-a8e9-4dfb-a462-a3fd4a409c25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437413821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.437413821 |
| Directory | /workspace/9.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3730085877 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 319968337 ps |
| CPU time | 0.94 seconds |
| Started | May 30 02:55:45 PM PDT 24 |
| Finished | May 30 02:55:47 PM PDT 24 |
| Peak memory | 183620 kb |
| Host | smart-4df7d714-6046-4bc7-92e6-aa9e88533531 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730085877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3730085877 |
| Directory | /workspace/9.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.222147392 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1335609822 ps |
| CPU time | 1.7 seconds |
| Started | May 30 02:55:45 PM PDT 24 |
| Finished | May 30 02:55:49 PM PDT 24 |
| Peak memory | 183856 kb |
| Host | smart-0f6246f3-53cb-4fb7-9af0-fcd889ddaa9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222147392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_ timer_same_csr_outstanding.222147392 |
| Directory | /workspace/9.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3426605541 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 410630517 ps |
| CPU time | 2.9 seconds |
| Started | May 30 02:55:45 PM PDT 24 |
| Finished | May 30 02:55:49 PM PDT 24 |
| Peak memory | 198460 kb |
| Host | smart-af2958f4-d77b-4dd5-95cb-5d6cf0cdaee1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426605541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3426605541 |
| Directory | /workspace/9.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2654064226 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 3965540914 ps |
| CPU time | 3.52 seconds |
| Started | May 30 02:55:44 PM PDT 24 |
| Finished | May 30 02:55:49 PM PDT 24 |
| Peak memory | 197896 kb |
| Host | smart-33948840-1962-44a7-9e82-6c8446d0d321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654064226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl _intg_err.2654064226 |
| Directory | /workspace/9.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.aon_timer_prescaler.3567445680 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 54340179108 ps |
| CPU time | 93.27 seconds |
| Started | May 30 02:48:28 PM PDT 24 |
| Finished | May 30 02:50:03 PM PDT 24 |
| Peak memory | 191924 kb |
| Host | smart-02a34dec-a5f6-4fa7-ad88-7e4c0567c8a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567445680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3567445680 |
| Directory | /workspace/0.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/0.aon_timer_sec_cm.1407313020 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4392566415 ps |
| CPU time | 7.24 seconds |
| Started | May 30 02:48:30 PM PDT 24 |
| Finished | May 30 02:48:40 PM PDT 24 |
| Peak memory | 215596 kb |
| Host | smart-e0113d59-cfd8-4bec-ade0-0724683fb7ae |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407313020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1407313020 |
| Directory | /workspace/0.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/0.aon_timer_smoke.258649358 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 584639577 ps |
| CPU time | 1.46 seconds |
| Started | May 30 02:48:32 PM PDT 24 |
| Finished | May 30 02:48:35 PM PDT 24 |
| Peak memory | 191792 kb |
| Host | smart-4b828038-12ba-4d25-b5a4-21fb26999617 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258649358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.258649358 |
| Directory | /workspace/0.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/1.aon_timer_prescaler.628362582 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 33749611108 ps |
| CPU time | 13.7 seconds |
| Started | May 30 02:48:31 PM PDT 24 |
| Finished | May 30 02:48:47 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-1269a48e-ee8f-4032-9b76-9af7a0c66a78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628362582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.628362582 |
| Directory | /workspace/1.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/1.aon_timer_smoke.1089722301 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 479048888 ps |
| CPU time | 0.92 seconds |
| Started | May 30 02:48:30 PM PDT 24 |
| Finished | May 30 02:48:33 PM PDT 24 |
| Peak memory | 191776 kb |
| Host | smart-bdf2f3f9-4daa-43aa-b666-ab12aa7b4173 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089722301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1089722301 |
| Directory | /workspace/1.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/10.aon_timer_prescaler.2571693457 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 19408478355 ps |
| CPU time | 12.79 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:49:08 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-7e0ee9fe-257c-43c1-a4b0-4faf45280400 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2571693457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2571693457 |
| Directory | /workspace/10.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/10.aon_timer_smoke.3292268282 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 406616529 ps |
| CPU time | 1.28 seconds |
| Started | May 30 02:48:51 PM PDT 24 |
| Finished | May 30 02:48:56 PM PDT 24 |
| Peak memory | 191756 kb |
| Host | smart-b8b1a8cc-42ac-46da-ab72-2b5a7d32a277 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292268282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3292268282 |
| Directory | /workspace/10.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/11.aon_timer_prescaler.1556142695 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1950353662 ps |
| CPU time | 1.22 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:48:58 PM PDT 24 |
| Peak memory | 191824 kb |
| Host | smart-4f3b167f-ab42-4108-9c34-644588ffb8ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1556142695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1556142695 |
| Directory | /workspace/11.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/11.aon_timer_smoke.980902758 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 575953037 ps |
| CPU time | 0.82 seconds |
| Started | May 30 02:48:50 PM PDT 24 |
| Finished | May 30 02:48:51 PM PDT 24 |
| Peak memory | 191868 kb |
| Host | smart-a37bcb6b-6c25-4881-a90a-474238602bc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980902758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.980902758 |
| Directory | /workspace/11.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/12.aon_timer_prescaler.2190077032 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 29783354376 ps |
| CPU time | 10.57 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:49:19 PM PDT 24 |
| Peak memory | 191932 kb |
| Host | smart-bb1e35b7-6e64-4c14-a7d1-af7c2952c462 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190077032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2190077032 |
| Directory | /workspace/12.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/12.aon_timer_smoke.147381619 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 531647180 ps |
| CPU time | 0.67 seconds |
| Started | May 30 02:49:07 PM PDT 24 |
| Finished | May 30 02:49:10 PM PDT 24 |
| Peak memory | 191780 kb |
| Host | smart-2302ecf9-0c89-4296-9c41-706ca42cb449 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=147381619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.147381619 |
| Directory | /workspace/12.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/13.aon_timer_prescaler.2040271177 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 27062638636 ps |
| CPU time | 20.47 seconds |
| Started | May 30 02:49:08 PM PDT 24 |
| Finished | May 30 02:49:31 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-2428cfc4-c096-406c-8ed0-4685eb2da311 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040271177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2040271177 |
| Directory | /workspace/13.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/13.aon_timer_smoke.1825450609 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 606950045 ps |
| CPU time | 0.68 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:49:09 PM PDT 24 |
| Peak memory | 191796 kb |
| Host | smart-887d2ee4-0a3f-46f1-b88b-63d8b83cd1bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825450609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1825450609 |
| Directory | /workspace/13.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/14.aon_timer_prescaler.6194147 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 36287899515 ps |
| CPU time | 61.58 seconds |
| Started | May 30 02:49:03 PM PDT 24 |
| Finished | May 30 02:50:06 PM PDT 24 |
| Peak memory | 191924 kb |
| Host | smart-1d91e7fe-47e4-4ab0-8502-155ccb291213 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6194147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.6194147 |
| Directory | /workspace/14.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/14.aon_timer_smoke.817585759 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 417311392 ps |
| CPU time | 0.7 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:49:08 PM PDT 24 |
| Peak memory | 191792 kb |
| Host | smart-d61c8b87-5066-4606-86ca-76c4d1868300 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=817585759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.817585759 |
| Directory | /workspace/14.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/15.aon_timer_jump.916529137 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 527274459 ps |
| CPU time | 1.34 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:15 PM PDT 24 |
| Peak memory | 196392 kb |
| Host | smart-8c665c0b-01ee-4540-b440-bf589be94814 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916529137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.916529137 |
| Directory | /workspace/15.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/15.aon_timer_prescaler.167798124 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 11156398946 ps |
| CPU time | 9.55 seconds |
| Started | May 30 02:49:07 PM PDT 24 |
| Finished | May 30 02:49:19 PM PDT 24 |
| Peak memory | 191936 kb |
| Host | smart-0f3fe3a2-2580-430b-9699-3d6a1d02cbd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167798124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.167798124 |
| Directory | /workspace/15.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/15.aon_timer_smoke.724228801 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 555630888 ps |
| CPU time | 1.51 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:49:13 PM PDT 24 |
| Peak memory | 191756 kb |
| Host | smart-94899c29-3ca1-433a-ae9c-921895b949ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724228801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.724228801 |
| Directory | /workspace/15.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/16.aon_timer_prescaler.1997176619 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 31432314746 ps |
| CPU time | 12.76 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:49:25 PM PDT 24 |
| Peak memory | 191972 kb |
| Host | smart-c517daaa-22fa-4274-bbba-ab9bdddb1077 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997176619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1997176619 |
| Directory | /workspace/16.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/16.aon_timer_smoke.1717302912 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 476877934 ps |
| CPU time | 1.32 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:49:15 PM PDT 24 |
| Peak memory | 191864 kb |
| Host | smart-57d5eaac-23bb-4c7c-b564-acb6f7af596e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717302912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1717302912 |
| Directory | /workspace/16.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/17.aon_timer_prescaler.2388266539 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 14025175829 ps |
| CPU time | 18.88 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:33 PM PDT 24 |
| Peak memory | 191932 kb |
| Host | smart-b5f36a98-67a8-41ec-9295-bc35f2adb46e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388266539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2388266539 |
| Directory | /workspace/17.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/17.aon_timer_smoke.2225689547 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 560566632 ps |
| CPU time | 1.25 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:49:14 PM PDT 24 |
| Peak memory | 191816 kb |
| Host | smart-f35c09eb-ec34-429e-a91b-8dc1f7efb734 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2225689547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2225689547 |
| Directory | /workspace/17.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/18.aon_timer_jump.2075743201 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 577315921 ps |
| CPU time | 0.64 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:15 PM PDT 24 |
| Peak memory | 196484 kb |
| Host | smart-56452b7b-7440-4194-8299-71a8cd5a560b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075743201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2075743201 |
| Directory | /workspace/18.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/18.aon_timer_prescaler.3700560591 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 19107234281 ps |
| CPU time | 27.2 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:49:41 PM PDT 24 |
| Peak memory | 191884 kb |
| Host | smart-f3c3246a-0a1d-4a11-a6ac-cf61dc95264c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700560591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3700560591 |
| Directory | /workspace/18.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/18.aon_timer_smoke.134690649 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 476590982 ps |
| CPU time | 1.07 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:15 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-ba03db71-3f1c-4f20-b84b-14a20480ea76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=134690649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.134690649 |
| Directory | /workspace/18.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/19.aon_timer_prescaler.1550285130 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 20500242093 ps |
| CPU time | 14.68 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:29 PM PDT 24 |
| Peak memory | 191884 kb |
| Host | smart-68797aa9-21a4-453b-bf1a-a137ca3e9fbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550285130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1550285130 |
| Directory | /workspace/19.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/19.aon_timer_smoke.3519590869 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 489457368 ps |
| CPU time | 1.39 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:16 PM PDT 24 |
| Peak memory | 191736 kb |
| Host | smart-34c840cb-768c-4279-8e3b-8a8b006d8d42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3519590869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3519590869 |
| Directory | /workspace/19.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/2.aon_timer_prescaler.627546104 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 44105820461 ps |
| CPU time | 10.84 seconds |
| Started | May 30 02:48:31 PM PDT 24 |
| Finished | May 30 02:48:44 PM PDT 24 |
| Peak memory | 191940 kb |
| Host | smart-95210904-7364-4f44-9c64-a933db522d95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627546104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.627546104 |
| Directory | /workspace/2.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/2.aon_timer_sec_cm.3895059202 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7903496763 ps |
| CPU time | 9.68 seconds |
| Started | May 30 02:48:51 PM PDT 24 |
| Finished | May 30 02:49:04 PM PDT 24 |
| Peak memory | 215744 kb |
| Host | smart-4bae8866-5f35-4de0-adca-e15fac3c4830 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895059202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3895059202 |
| Directory | /workspace/2.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/2.aon_timer_smoke.2830268059 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 465620616 ps |
| CPU time | 1.3 seconds |
| Started | May 30 02:48:28 PM PDT 24 |
| Finished | May 30 02:48:31 PM PDT 24 |
| Peak memory | 191792 kb |
| Host | smart-aea61072-50c1-4b97-be3f-3fce4340a1fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830268059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2830268059 |
| Directory | /workspace/2.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/20.aon_timer_prescaler.2475094954 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 3989322581 ps |
| CPU time | 1.48 seconds |
| Started | May 30 02:49:08 PM PDT 24 |
| Finished | May 30 02:49:13 PM PDT 24 |
| Peak memory | 191908 kb |
| Host | smart-0aeb2da0-b633-444a-ae82-34f5ec581288 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2475094954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2475094954 |
| Directory | /workspace/20.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/20.aon_timer_smoke.2318466939 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 466771747 ps |
| CPU time | 0.96 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:49:13 PM PDT 24 |
| Peak memory | 191788 kb |
| Host | smart-b2948750-3041-4030-8864-ae599e5cd5ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2318466939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2318466939 |
| Directory | /workspace/20.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/21.aon_timer_prescaler.1042099432 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 48747039253 ps |
| CPU time | 5.55 seconds |
| Started | May 30 02:49:12 PM PDT 24 |
| Finished | May 30 02:49:21 PM PDT 24 |
| Peak memory | 191920 kb |
| Host | smart-e5809bf4-6d77-46ba-8b5c-f8baccaaed5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042099432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1042099432 |
| Directory | /workspace/21.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/21.aon_timer_smoke.233617243 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 416897703 ps |
| CPU time | 0.94 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:15 PM PDT 24 |
| Peak memory | 191776 kb |
| Host | smart-9dce5d74-93b8-458b-b4b3-6d7dfdcce2a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233617243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.233617243 |
| Directory | /workspace/21.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3651819626 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 124900720460 ps |
| CPU time | 150.04 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:51:37 PM PDT 24 |
| Peak memory | 208172 kb |
| Host | smart-e74d59bd-82e4-4c07-b577-5db8e71732eb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651819626 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3651819626 |
| Directory | /workspace/21.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.aon_timer_prescaler.2350463224 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 60245368693 ps |
| CPU time | 13.41 seconds |
| Started | May 30 02:49:07 PM PDT 24 |
| Finished | May 30 02:49:23 PM PDT 24 |
| Peak memory | 191908 kb |
| Host | smart-b722f29d-1e2e-4378-a41b-0a78dba2aedc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350463224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2350463224 |
| Directory | /workspace/22.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/22.aon_timer_smoke.230215830 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 488579860 ps |
| CPU time | 0.93 seconds |
| Started | May 30 02:49:08 PM PDT 24 |
| Finished | May 30 02:49:11 PM PDT 24 |
| Peak memory | 191816 kb |
| Host | smart-fbfae390-1a13-4b02-8b8c-ea3c1f6aa3a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=230215830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.230215830 |
| Directory | /workspace/22.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/23.aon_timer_prescaler.2505491693 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 43706011280 ps |
| CPU time | 45.24 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:49:54 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-1cc433dc-5401-42c1-bcec-4a00acf06437 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505491693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2505491693 |
| Directory | /workspace/23.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/23.aon_timer_smoke.760282941 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 416440855 ps |
| CPU time | 0.72 seconds |
| Started | May 30 02:49:06 PM PDT 24 |
| Finished | May 30 02:49:08 PM PDT 24 |
| Peak memory | 191792 kb |
| Host | smart-57a653a8-5cd2-419f-bb39-a0a0a04ea93b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760282941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.760282941 |
| Directory | /workspace/23.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/24.aon_timer_prescaler.3703376873 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 59391174325 ps |
| CPU time | 83.25 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:50:36 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-cb5311d4-4e7b-4edd-ba50-24853a0b324d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703376873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3703376873 |
| Directory | /workspace/24.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/24.aon_timer_smoke.159535202 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 600986612 ps |
| CPU time | 0.81 seconds |
| Started | May 30 02:49:05 PM PDT 24 |
| Finished | May 30 02:49:07 PM PDT 24 |
| Peak memory | 191776 kb |
| Host | smart-b648f037-78ca-430f-ba32-502199caf608 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159535202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.159535202 |
| Directory | /workspace/24.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/25.aon_timer_prescaler.36317935 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 33199723200 ps |
| CPU time | 48.95 seconds |
| Started | May 30 02:49:12 PM PDT 24 |
| Finished | May 30 02:50:04 PM PDT 24 |
| Peak memory | 191896 kb |
| Host | smart-c427139f-4ae2-4c23-ba35-299faf63041c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36317935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.36317935 |
| Directory | /workspace/25.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/25.aon_timer_smoke.920309683 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 392741123 ps |
| CPU time | 0.81 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:49:13 PM PDT 24 |
| Peak memory | 191756 kb |
| Host | smart-442628bc-92b5-4632-948d-ce8da05a02b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920309683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.920309683 |
| Directory | /workspace/25.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/26.aon_timer_jump.2599305375 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 515405495 ps |
| CPU time | 0.95 seconds |
| Started | May 30 02:49:08 PM PDT 24 |
| Finished | May 30 02:49:12 PM PDT 24 |
| Peak memory | 196540 kb |
| Host | smart-98677b33-82ba-4ebb-9a37-6adedae8fa2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599305375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2599305375 |
| Directory | /workspace/26.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/26.aon_timer_prescaler.152939227 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 33385892934 ps |
| CPU time | 24.8 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:49:38 PM PDT 24 |
| Peak memory | 191900 kb |
| Host | smart-11eb9fec-708b-4621-b568-7720e9dc80c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=152939227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.152939227 |
| Directory | /workspace/26.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/26.aon_timer_smoke.2460542229 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 588182421 ps |
| CPU time | 1.04 seconds |
| Started | May 30 02:49:08 PM PDT 24 |
| Finished | May 30 02:49:12 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-cc99a077-402d-47f9-9aca-517e0b9efc90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2460542229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2460542229 |
| Directory | /workspace/26.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/27.aon_timer_prescaler.1478790192 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 31456995938 ps |
| CPU time | 47.73 seconds |
| Started | May 30 02:49:09 PM PDT 24 |
| Finished | May 30 02:50:00 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-39dbeeea-5f4e-423a-add2-bce609a8e82c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1478790192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1478790192 |
| Directory | /workspace/27.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/27.aon_timer_smoke.2411769454 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 523941005 ps |
| CPU time | 0.6 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:49:13 PM PDT 24 |
| Peak memory | 191812 kb |
| Host | smart-e9cfb3d1-8ca2-4694-8954-90f3f901dfb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2411769454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2411769454 |
| Directory | /workspace/27.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/28.aon_timer_prescaler.2083764953 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 53195268116 ps |
| CPU time | 16.02 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:31 PM PDT 24 |
| Peak memory | 191856 kb |
| Host | smart-a3b6f2e5-d9bd-4dba-959a-549277d96fa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083764953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2083764953 |
| Directory | /workspace/28.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/28.aon_timer_smoke.3190644754 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 726739858 ps |
| CPU time | 0.68 seconds |
| Started | May 30 02:49:07 PM PDT 24 |
| Finished | May 30 02:49:10 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-c99822cc-499a-4612-acf8-ec00c36b75dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190644754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3190644754 |
| Directory | /workspace/28.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/29.aon_timer_jump.3064052478 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 554988310 ps |
| CPU time | 0.75 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:15 PM PDT 24 |
| Peak memory | 196360 kb |
| Host | smart-88113bd9-4a44-476a-88da-ad121eaac132 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064052478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3064052478 |
| Directory | /workspace/29.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/29.aon_timer_prescaler.2860030557 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 545730858 ps |
| CPU time | 1.34 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:16 PM PDT 24 |
| Peak memory | 191744 kb |
| Host | smart-5c20e133-4e83-4ad8-a7b8-d0662f100cba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2860030557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2860030557 |
| Directory | /workspace/29.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/29.aon_timer_smoke.1312282847 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 509988015 ps |
| CPU time | 0.62 seconds |
| Started | May 30 02:49:12 PM PDT 24 |
| Finished | May 30 02:49:16 PM PDT 24 |
| Peak memory | 191748 kb |
| Host | smart-aabf6baf-27ed-4610-b6dd-546d39f6bc26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1312282847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1312282847 |
| Directory | /workspace/29.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/3.aon_timer_prescaler.796335120 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 35637168715 ps |
| CPU time | 50.87 seconds |
| Started | May 30 02:48:54 PM PDT 24 |
| Finished | May 30 02:49:49 PM PDT 24 |
| Peak memory | 191900 kb |
| Host | smart-ec78a190-7e27-409c-8d4a-aa776679208c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796335120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.796335120 |
| Directory | /workspace/3.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/3.aon_timer_sec_cm.1808185125 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4431213515 ps |
| CPU time | 7.7 seconds |
| Started | May 30 02:48:50 PM PDT 24 |
| Finished | May 30 02:49:01 PM PDT 24 |
| Peak memory | 215568 kb |
| Host | smart-8a75f7e4-bafe-4c3d-97f1-0687f13f125b |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808185125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1808185125 |
| Directory | /workspace/3.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/3.aon_timer_smoke.2657426553 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 406340292 ps |
| CPU time | 0.77 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:48:57 PM PDT 24 |
| Peak memory | 191784 kb |
| Host | smart-ad112bf7-5473-4d4a-8bbc-f3220404155d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2657426553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2657426553 |
| Directory | /workspace/3.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/30.aon_timer_prescaler.1866721643 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 14354309324 ps |
| CPU time | 6.31 seconds |
| Started | May 30 02:49:11 PM PDT 24 |
| Finished | May 30 02:49:21 PM PDT 24 |
| Peak memory | 191920 kb |
| Host | smart-8fa2ce2a-7236-44d2-b961-3be2ed3821fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1866721643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1866721643 |
| Directory | /workspace/30.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/30.aon_timer_smoke.42776870 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 427149500 ps |
| CPU time | 0.66 seconds |
| Started | May 30 02:49:10 PM PDT 24 |
| Finished | May 30 02:49:14 PM PDT 24 |
| Peak memory | 191756 kb |
| Host | smart-da347321-5ea3-42f0-9809-95697bccdf35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42776870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.42776870 |
| Directory | /workspace/30.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/31.aon_timer_prescaler.455303877 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 24771032247 ps |
| CPU time | 8.25 seconds |
| Started | May 30 02:49:18 PM PDT 24 |
| Finished | May 30 02:49:29 PM PDT 24 |
| Peak memory | 191920 kb |
| Host | smart-6a8a2397-8874-4f7f-9449-af254f70b64a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455303877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.455303877 |
| Directory | /workspace/31.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/31.aon_timer_smoke.854977001 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 565290990 ps |
| CPU time | 1.53 seconds |
| Started | May 30 02:49:21 PM PDT 24 |
| Finished | May 30 02:49:25 PM PDT 24 |
| Peak memory | 191756 kb |
| Host | smart-8d34d9e6-12c7-413e-bc59-7495404ab777 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854977001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.854977001 |
| Directory | /workspace/31.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/32.aon_timer_prescaler.2833213710 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 6091252023 ps |
| CPU time | 10.16 seconds |
| Started | May 30 02:49:18 PM PDT 24 |
| Finished | May 30 02:49:30 PM PDT 24 |
| Peak memory | 191992 kb |
| Host | smart-d286734f-bdf6-4761-adcb-ec11328e51cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2833213710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2833213710 |
| Directory | /workspace/32.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/32.aon_timer_smoke.2193060412 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 546127001 ps |
| CPU time | 0.93 seconds |
| Started | May 30 02:49:20 PM PDT 24 |
| Finished | May 30 02:49:24 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-3f5f8e1c-429d-4e88-8cc3-2069750a4811 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2193060412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2193060412 |
| Directory | /workspace/32.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/33.aon_timer_prescaler.111277984 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 11077278063 ps |
| CPU time | 3.93 seconds |
| Started | May 30 02:49:25 PM PDT 24 |
| Finished | May 30 02:49:32 PM PDT 24 |
| Peak memory | 191896 kb |
| Host | smart-4dcdc5fc-d292-4bcc-adee-c98d3a0a3800 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111277984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.111277984 |
| Directory | /workspace/33.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/33.aon_timer_smoke.3666800834 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 410219942 ps |
| CPU time | 0.71 seconds |
| Started | May 30 02:49:18 PM PDT 24 |
| Finished | May 30 02:49:22 PM PDT 24 |
| Peak memory | 191780 kb |
| Host | smart-389d44df-d090-420c-9ed3-80d62fd9da3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666800834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3666800834 |
| Directory | /workspace/33.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/34.aon_timer_prescaler.300391000 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 25029982808 ps |
| CPU time | 20.99 seconds |
| Started | May 30 02:49:20 PM PDT 24 |
| Finished | May 30 02:49:44 PM PDT 24 |
| Peak memory | 191904 kb |
| Host | smart-4cac8903-236f-4df4-a81d-ec298875339b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=300391000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.300391000 |
| Directory | /workspace/34.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/34.aon_timer_smoke.3985633370 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 463384198 ps |
| CPU time | 1.14 seconds |
| Started | May 30 02:49:19 PM PDT 24 |
| Finished | May 30 02:49:23 PM PDT 24 |
| Peak memory | 191756 kb |
| Host | smart-1e8202d9-cd9b-4d0b-898d-8a252410875b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3985633370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3985633370 |
| Directory | /workspace/34.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/35.aon_timer_prescaler.2038015317 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 9942418162 ps |
| CPU time | 4.6 seconds |
| Started | May 30 02:49:26 PM PDT 24 |
| Finished | May 30 02:49:34 PM PDT 24 |
| Peak memory | 191936 kb |
| Host | smart-63ce2e95-6201-4200-a4e1-c5b092716f67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038015317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2038015317 |
| Directory | /workspace/35.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/35.aon_timer_smoke.1272131545 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 470006260 ps |
| CPU time | 1 seconds |
| Started | May 30 02:49:19 PM PDT 24 |
| Finished | May 30 02:49:23 PM PDT 24 |
| Peak memory | 191756 kb |
| Host | smart-cad414db-0a29-4752-8a09-0faa932e63e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272131545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1272131545 |
| Directory | /workspace/35.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/36.aon_timer_prescaler.591313913 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 21552434302 ps |
| CPU time | 9.07 seconds |
| Started | May 30 02:49:20 PM PDT 24 |
| Finished | May 30 02:49:32 PM PDT 24 |
| Peak memory | 191888 kb |
| Host | smart-0c95b171-05c7-49cd-bb5c-f47bf6104e1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591313913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.591313913 |
| Directory | /workspace/36.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/36.aon_timer_smoke.1982849676 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 448902805 ps |
| CPU time | 0.63 seconds |
| Started | May 30 02:49:20 PM PDT 24 |
| Finished | May 30 02:49:23 PM PDT 24 |
| Peak memory | 191820 kb |
| Host | smart-6ae96603-91ce-437c-952b-80193c0d9c1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982849676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1982849676 |
| Directory | /workspace/36.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/37.aon_timer_prescaler.3839034027 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 32743547595 ps |
| CPU time | 13.74 seconds |
| Started | May 30 02:49:29 PM PDT 24 |
| Finished | May 30 02:49:46 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-c4cc20fc-5e5e-48a4-a9b3-00c581958712 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839034027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3839034027 |
| Directory | /workspace/37.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/37.aon_timer_smoke.209005513 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 403321984 ps |
| CPU time | 0.72 seconds |
| Started | May 30 02:49:25 PM PDT 24 |
| Finished | May 30 02:49:28 PM PDT 24 |
| Peak memory | 191796 kb |
| Host | smart-dc96ad72-fc58-4848-861b-2d56bb74550b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=209005513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.209005513 |
| Directory | /workspace/37.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/38.aon_timer_jump.1017125415 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 455873707 ps |
| CPU time | 1.24 seconds |
| Started | May 30 02:49:34 PM PDT 24 |
| Finished | May 30 02:49:36 PM PDT 24 |
| Peak memory | 196408 kb |
| Host | smart-118f31ca-f543-473a-9787-124b5ea7a78f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017125415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1017125415 |
| Directory | /workspace/38.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/38.aon_timer_prescaler.2074965920 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 56228390773 ps |
| CPU time | 11.41 seconds |
| Started | May 30 02:49:23 PM PDT 24 |
| Finished | May 30 02:49:36 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-d5a41643-1abd-4320-956c-20968c349853 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2074965920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2074965920 |
| Directory | /workspace/38.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/38.aon_timer_smoke.584611525 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 593973237 ps |
| CPU time | 0.79 seconds |
| Started | May 30 02:49:41 PM PDT 24 |
| Finished | May 30 02:49:43 PM PDT 24 |
| Peak memory | 191796 kb |
| Host | smart-f922b2ad-b278-4ae4-b4bf-053d4a9bbf41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=584611525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.584611525 |
| Directory | /workspace/38.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/39.aon_timer_prescaler.1608415700 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 35989882270 ps |
| CPU time | 28.01 seconds |
| Started | May 30 02:49:25 PM PDT 24 |
| Finished | May 30 02:49:55 PM PDT 24 |
| Peak memory | 191936 kb |
| Host | smart-2594b4bb-2257-4a45-85a8-50a67fa48627 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608415700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1608415700 |
| Directory | /workspace/39.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/39.aon_timer_smoke.1214524860 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 510689783 ps |
| CPU time | 1.35 seconds |
| Started | May 30 02:49:20 PM PDT 24 |
| Finished | May 30 02:49:24 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-9a57a5ad-d08b-44bf-bb42-50644b23a7cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214524860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1214524860 |
| Directory | /workspace/39.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/4.aon_timer_prescaler.4036950412 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 31254068872 ps |
| CPU time | 10.85 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:49:07 PM PDT 24 |
| Peak memory | 191912 kb |
| Host | smart-328d4b7d-8530-4e01-9d68-287fd1ff7a3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036950412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.4036950412 |
| Directory | /workspace/4.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/4.aon_timer_sec_cm.127389723 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3651040909 ps |
| CPU time | 2.05 seconds |
| Started | May 30 02:48:53 PM PDT 24 |
| Finished | May 30 02:48:59 PM PDT 24 |
| Peak memory | 215380 kb |
| Host | smart-801ce05b-5854-41c3-89dc-74204c7c05c7 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127389723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.127389723 |
| Directory | /workspace/4.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/4.aon_timer_smoke.2110431814 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 363308311 ps |
| CPU time | 1.16 seconds |
| Started | May 30 02:48:53 PM PDT 24 |
| Finished | May 30 02:48:58 PM PDT 24 |
| Peak memory | 191816 kb |
| Host | smart-154ab798-43a4-4098-b7a3-1c70f8fd2abb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110431814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2110431814 |
| Directory | /workspace/4.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/40.aon_timer_prescaler.3961653297 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 23880693815 ps |
| CPU time | 31.99 seconds |
| Started | May 30 02:49:26 PM PDT 24 |
| Finished | May 30 02:50:00 PM PDT 24 |
| Peak memory | 191936 kb |
| Host | smart-a821d4cd-98a7-4c76-abe0-1f24988083f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3961653297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3961653297 |
| Directory | /workspace/40.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/40.aon_timer_smoke.3202966364 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 556471492 ps |
| CPU time | 0.77 seconds |
| Started | May 30 02:49:25 PM PDT 24 |
| Finished | May 30 02:49:28 PM PDT 24 |
| Peak memory | 191816 kb |
| Host | smart-2590f34e-94d2-4234-ad2d-93f5828aa530 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202966364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3202966364 |
| Directory | /workspace/40.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/41.aon_timer_prescaler.1860918705 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 18597686476 ps |
| CPU time | 27.53 seconds |
| Started | May 30 02:49:18 PM PDT 24 |
| Finished | May 30 02:49:48 PM PDT 24 |
| Peak memory | 191900 kb |
| Host | smart-d64aa36c-36ce-4a77-8b4f-d51c2f878b49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860918705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1860918705 |
| Directory | /workspace/41.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/41.aon_timer_smoke.738774789 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 568265162 ps |
| CPU time | 0.76 seconds |
| Started | May 30 02:49:18 PM PDT 24 |
| Finished | May 30 02:49:22 PM PDT 24 |
| Peak memory | 191812 kb |
| Host | smart-00c73b3e-0f39-4060-b02b-ec94b445f4c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738774789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.738774789 |
| Directory | /workspace/41.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/42.aon_timer_prescaler.823904850 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 23199511480 ps |
| CPU time | 36.55 seconds |
| Started | May 30 02:49:21 PM PDT 24 |
| Finished | May 30 02:50:00 PM PDT 24 |
| Peak memory | 191920 kb |
| Host | smart-0c3b04c5-f5ef-4150-a11c-7fe335f8f677 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=823904850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.823904850 |
| Directory | /workspace/42.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/42.aon_timer_smoke.3853871892 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 477417619 ps |
| CPU time | 1.25 seconds |
| Started | May 30 02:49:17 PM PDT 24 |
| Finished | May 30 02:49:20 PM PDT 24 |
| Peak memory | 191820 kb |
| Host | smart-b244859c-976d-45db-8af0-ef368756c309 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3853871892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3853871892 |
| Directory | /workspace/42.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/43.aon_timer_prescaler.1616888624 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 44580504717 ps |
| CPU time | 58.8 seconds |
| Started | May 30 02:49:25 PM PDT 24 |
| Finished | May 30 02:50:26 PM PDT 24 |
| Peak memory | 191896 kb |
| Host | smart-744a0de0-859b-489e-afa0-ff325c9a9154 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616888624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1616888624 |
| Directory | /workspace/43.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/43.aon_timer_smoke.764135990 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 647987926 ps |
| CPU time | 0.7 seconds |
| Started | May 30 02:49:18 PM PDT 24 |
| Finished | May 30 02:49:21 PM PDT 24 |
| Peak memory | 191812 kb |
| Host | smart-ed7f564c-8518-4f7e-bc48-213ad9045102 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=764135990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.764135990 |
| Directory | /workspace/43.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/44.aon_timer_prescaler.2590470835 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 32537830279 ps |
| CPU time | 44.96 seconds |
| Started | May 30 02:49:28 PM PDT 24 |
| Finished | May 30 02:50:15 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-8f8ccb4f-22f3-4296-801c-66fb4c31bc9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590470835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2590470835 |
| Directory | /workspace/44.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/44.aon_timer_smoke.2792687642 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 588515196 ps |
| CPU time | 1.18 seconds |
| Started | May 30 02:49:26 PM PDT 24 |
| Finished | May 30 02:49:30 PM PDT 24 |
| Peak memory | 191816 kb |
| Host | smart-c536fea8-d768-4950-b17e-14bff76f1a78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2792687642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2792687642 |
| Directory | /workspace/44.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/45.aon_timer_prescaler.2092961382 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2598698017 ps |
| CPU time | 1.54 seconds |
| Started | May 30 02:49:38 PM PDT 24 |
| Finished | May 30 02:49:41 PM PDT 24 |
| Peak memory | 190740 kb |
| Host | smart-68db4020-a2ff-445d-acc2-ff62f858d158 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092961382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2092961382 |
| Directory | /workspace/45.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/45.aon_timer_smoke.429068755 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 606433699 ps |
| CPU time | 0.67 seconds |
| Started | May 30 02:49:29 PM PDT 24 |
| Finished | May 30 02:49:33 PM PDT 24 |
| Peak memory | 191812 kb |
| Host | smart-bee5d53a-a879-459d-9bd9-5ac0d76ec2e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=429068755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.429068755 |
| Directory | /workspace/45.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/46.aon_timer_prescaler.3730187171 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 25216189288 ps |
| CPU time | 10.5 seconds |
| Started | May 30 02:49:29 PM PDT 24 |
| Finished | May 30 02:49:42 PM PDT 24 |
| Peak memory | 191936 kb |
| Host | smart-e5687ec7-afa0-47fb-99b7-7e4f7eae7d5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730187171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3730187171 |
| Directory | /workspace/46.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/46.aon_timer_smoke.323060504 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 581157380 ps |
| CPU time | 1.15 seconds |
| Started | May 30 02:49:30 PM PDT 24 |
| Finished | May 30 02:49:34 PM PDT 24 |
| Peak memory | 191768 kb |
| Host | smart-a9b071a8-d005-4377-8839-2d02c1f1bb37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323060504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.323060504 |
| Directory | /workspace/46.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/47.aon_timer_prescaler.3550190608 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 13161698058 ps |
| CPU time | 19.87 seconds |
| Started | May 30 02:49:28 PM PDT 24 |
| Finished | May 30 02:49:51 PM PDT 24 |
| Peak memory | 191936 kb |
| Host | smart-5e16228b-412e-43e1-9169-385b66c0bec0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550190608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3550190608 |
| Directory | /workspace/47.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/47.aon_timer_smoke.922858963 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 495205172 ps |
| CPU time | 1.27 seconds |
| Started | May 30 02:49:36 PM PDT 24 |
| Finished | May 30 02:49:39 PM PDT 24 |
| Peak memory | 191828 kb |
| Host | smart-9b35cf5b-1e1c-44ce-98f5-05d6a9d1719b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=922858963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.922858963 |
| Directory | /workspace/47.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/48.aon_timer_prescaler.4135417056 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 13628898587 ps |
| CPU time | 3.52 seconds |
| Started | May 30 02:49:38 PM PDT 24 |
| Finished | May 30 02:49:43 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-6309be20-dfc1-42c5-bb13-b2258949e1a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4135417056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4135417056 |
| Directory | /workspace/48.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/48.aon_timer_smoke.3636142618 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 368150900 ps |
| CPU time | 1.04 seconds |
| Started | May 30 02:49:31 PM PDT 24 |
| Finished | May 30 02:49:35 PM PDT 24 |
| Peak memory | 191768 kb |
| Host | smart-90f81faf-9e69-4f8e-b5cf-6dfbdce5615a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3636142618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3636142618 |
| Directory | /workspace/48.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/49.aon_timer_prescaler.3551229458 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 8375599397 ps |
| CPU time | 14.27 seconds |
| Started | May 30 02:49:38 PM PDT 24 |
| Finished | May 30 02:49:54 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-ef2b86c1-62ed-434d-b252-7bf372384d7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3551229458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3551229458 |
| Directory | /workspace/49.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/49.aon_timer_smoke.354557160 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 493491905 ps |
| CPU time | 1.19 seconds |
| Started | May 30 02:49:28 PM PDT 24 |
| Finished | May 30 02:49:31 PM PDT 24 |
| Peak memory | 191812 kb |
| Host | smart-8e8220a7-8e10-43e8-b6cf-900debef8abc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=354557160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.354557160 |
| Directory | /workspace/49.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/5.aon_timer_prescaler.1130193511 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 830072216 ps |
| CPU time | 1.03 seconds |
| Started | May 30 02:48:51 PM PDT 24 |
| Finished | May 30 02:48:54 PM PDT 24 |
| Peak memory | 191816 kb |
| Host | smart-baf4c23b-5e98-41bb-98e6-a1dc338d7289 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130193511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1130193511 |
| Directory | /workspace/5.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/5.aon_timer_smoke.1976907257 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 362007698 ps |
| CPU time | 1.21 seconds |
| Started | May 30 02:48:50 PM PDT 24 |
| Finished | May 30 02:48:53 PM PDT 24 |
| Peak memory | 191772 kb |
| Host | smart-91315991-a5cd-46b4-be1e-e6ae312d6a68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1976907257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1976907257 |
| Directory | /workspace/5.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/6.aon_timer_prescaler.2672996867 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 29804412732 ps |
| CPU time | 45.15 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:49:40 PM PDT 24 |
| Peak memory | 191912 kb |
| Host | smart-08e82605-d7ba-48d0-b811-5f34db6a8688 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2672996867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2672996867 |
| Directory | /workspace/6.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/6.aon_timer_smoke.4242363315 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 351780387 ps |
| CPU time | 1.07 seconds |
| Started | May 30 02:48:53 PM PDT 24 |
| Finished | May 30 02:48:59 PM PDT 24 |
| Peak memory | 191808 kb |
| Host | smart-9e65990a-3d73-4082-8b26-69a356ea0a83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4242363315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.4242363315 |
| Directory | /workspace/6.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/7.aon_timer_jump.1269039850 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 390088569 ps |
| CPU time | 0.68 seconds |
| Started | May 30 02:48:50 PM PDT 24 |
| Finished | May 30 02:48:53 PM PDT 24 |
| Peak memory | 196516 kb |
| Host | smart-d6bcf9b3-c816-4b93-82fd-43a2325b51f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1269039850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1269039850 |
| Directory | /workspace/7.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/7.aon_timer_prescaler.2258997479 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 37133079183 ps |
| CPU time | 11.69 seconds |
| Started | May 30 02:48:51 PM PDT 24 |
| Finished | May 30 02:49:07 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-def1d08b-a07a-4dd6-b19e-408b65417780 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258997479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2258997479 |
| Directory | /workspace/7.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/7.aon_timer_smoke.3521090592 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 442006207 ps |
| CPU time | 1.17 seconds |
| Started | May 30 02:48:50 PM PDT 24 |
| Finished | May 30 02:48:54 PM PDT 24 |
| Peak memory | 191812 kb |
| Host | smart-f8738f3f-3086-4ee4-ba94-d7bb153af9f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521090592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3521090592 |
| Directory | /workspace/7.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/8.aon_timer_prescaler.4041006748 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 14524551819 ps |
| CPU time | 5.8 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:49:02 PM PDT 24 |
| Peak memory | 191916 kb |
| Host | smart-bf633a23-ae47-4535-8229-226d4dc82031 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4041006748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.4041006748 |
| Directory | /workspace/8.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/8.aon_timer_smoke.3606191760 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 508386502 ps |
| CPU time | 1.28 seconds |
| Started | May 30 02:48:51 PM PDT 24 |
| Finished | May 30 02:48:56 PM PDT 24 |
| Peak memory | 191792 kb |
| Host | smart-61f6bddf-9cb6-4318-86e7-f2cc1f7838ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606191760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3606191760 |
| Directory | /workspace/8.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/9.aon_timer_prescaler.2412137869 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 33229180935 ps |
| CPU time | 11.5 seconds |
| Started | May 30 02:48:53 PM PDT 24 |
| Finished | May 30 02:49:08 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-be55343a-d008-4090-8f86-339a756aa212 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2412137869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2412137869 |
| Directory | /workspace/9.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/9.aon_timer_smoke.647997411 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 554819049 ps |
| CPU time | 0.74 seconds |
| Started | May 30 02:48:52 PM PDT 24 |
| Finished | May 30 02:48:57 PM PDT 24 |
| Peak memory | 191804 kb |
| Host | smart-bd8959f0-0df1-43ef-be05-73090b8086fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=647997411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.647997411 |
| Directory | /workspace/9.aon_timer_smoke/latest |
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