Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	29928	1		T1	12		T2	12		T3	12
bark[1]	398	1		T22	21		T110	14		T112	21
bark[2]	201	1		T73	39		T193	14		T93	66
bark[3]	1402	1		T4	14		T102	30		T96	300
bark[4]	728	1		T20	21		T164	21		T167	21
bark[5]	1189	1		T11	266		T16	7		T31	78
bark[6]	373	1		T20	68		T29	14		T127	45
bark[7]	930	1		T44	14		T164	41		T102	21
bark[8]	314	1		T7	14		T190	14		T112	21
bark[9]	814	1		T16	21		T20	21		T127	26
bark[10]	747	1		T120	14		T58	7		T73	30
bark[11]	385	1		T20	28		T161	14		T122	14
bark[12]	432	1		T11	21		T184	14		T96	102
bark[13]	275	1		T167	21		T178	69		T52	21
bark[14]	992	1		T129	21		T27	71		T116	21
bark[15]	284	1		T167	42		T96	21		T51	7
bark[16]	765	1		T141	21		T164	21		T180	32
bark[17]	604	1		T27	246		T116	60		T95	31
bark[18]	432	1		T22	26		T35	7		T141	21
bark[19]	504	1		T141	14		T96	21		T52	30
bark[20]	347	1		T28	14		T43	7		T165	21
bark[21]	920	1		T164	21		T27	53		T95	21
bark[22]	555	1		T164	45		T43	241		T178	40
bark[23]	252	1		T11	21		T16	74		T145	21
bark[24]	225	1		T136	21		T108	21		T127	14
bark[25]	606	1		T22	21		T141	21		T31	94
bark[26]	400	1		T141	40		T31	77		T191	14
bark[27]	328	1		T21	21		T47	14		T32	14
bark[28]	994	1		T16	290		T31	120		T96	21
bark[29]	539	1		T102	21		T108	51		T113	21
bark[30]	250	1		T20	26		T48	14		T30	14
bark[31]	471	1		T106	31		T59	52		T74	21
bark_0	4630	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	30248	1		T1	11		T2	11		T3	11
bite[1]	301	1		T16	6		T141	21		T102	51
bite[2]	350	1		T4	13		T141	13		T102	21
bite[3]	257	1		T20	68		T164	21		T123	21
bite[4]	149	1		T172	13		T53	13		T111	56
bite[5]	913	1		T27	70		T110	13		T108	30
bite[6]	596	1		T11	21		T141	40		T164	21
bite[7]	284	1		T5	13		T44	13		T116	60
bite[8]	888	1		T20	27		T21	21		T22	21
bite[9]	686	1		T164	40		T184	13		T96	6
bite[10]	332	1		T35	6		T167	42		T155	22
bite[11]	105	1		T164	21		T129	21		T95	21
bite[12]	798	1		T167	21		T95	21		T165	60
bite[13]	603	1		T153	21		T127	13		T74	82
bite[14]	397	1		T145	39		T106	25		T50	154
bite[15]	784	1		T31	77		T178	55		T131	26
bite[16]	448	1		T120	13		T27	245		T95	31
bite[17]	528	1		T20	21		T30	13		T122	13
bite[18]	716	1		T47	13		T164	66		T96	299
bite[19]	408	1		T20	21		T180	21		T167	21
bite[20]	768	1		T11	21		T141	21		T31	119
bite[21]	799	1		T16	21		T55	21		T56	21
bite[22]	154	1		T27	52		T190	13		T112	21
bite[23]	723	1		T20	26		T55	27		T74	25
bite[24]	295	1		T161	13		T29	13		T32	13
bite[25]	244	1		T31	76		T94	21		T124	64
bite[26]	813	1		T16	73		T51	6		T52	30
bite[27]	266	1		T149	13		T96	21		T98	21
bite[28]	1024	1		T11	265		T22	21		T43	6
bite[29]	1158	1		T54	13		T56	67		T98	21
bite[30]	420	1		T102	21		T180	31		T96	25
bite[31]	669	1		T48	13		T28	13		T191	13
bite_0	5090	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	52214	1		T1	19		T2	19		T3	19

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1106	1		T11	27		T16	37		T23	19
prescale[1]	1026	1		T11	73		T21	44		T141	19
prescale[2]	1272	1		T16	38		T102	40		T41	72
prescale[3]	866	1		T23	45		T31	2		T41	47
prescale[4]	1095	1		T11	58		T16	72		T42	43
prescale[5]	769	1		T11	28		T16	50		T95	54
prescale[6]	798	1		T16	42		T22	28		T31	24
prescale[7]	734	1		T16	2		T23	40		T202	9
prescale[8]	425	1		T45	9		T102	9		T42	2
prescale[9]	948	1		T11	143		T16	2		T20	19
prescale[10]	904	1		T11	254		T12	20		T21	37
prescale[11]	662	1		T11	55		T16	81		T20	32
prescale[12]	719	1		T22	19		T42	19		T95	40
prescale[13]	552	1		T203	9		T26	9		T31	2
prescale[14]	1007	1		T10	9		T35	23		T153	42
prescale[15]	750	1		T11	139		T16	2		T35	2
prescale[16]	1305	1		T23	19		T35	212		T141	19
prescale[17]	368	1		T12	2		T20	87		T22	23
prescale[18]	567	1		T23	37		T141	19		T116	9
prescale[19]	552	1		T1	9		T12	2		T41	2
prescale[20]	771	1		T180	38		T41	81		T43	28
prescale[21]	1343	1		T3	9		T23	9		T21	58
prescale[22]	643	1		T16	2		T27	2		T31	2
prescale[23]	667	1		T12	2		T16	19		T23	9
prescale[24]	455	1		T13	9		T16	125		T23	2
prescale[25]	960	1		T2	9		T16	2		T116	37
prescale[26]	975	1		T6	9		T11	85		T21	33
prescale[27]	1015	1		T11	22		T21	19		T35	9
prescale[28]	638	1		T11	86		T12	2		T16	24
prescale[29]	607	1		T16	2		T129	46		T31	23
prescale[30]	531	1		T16	40		T23	2		T43	46
prescale[31]	930	1		T11	19		T14	9		T16	37
prescale_0	26254	1		T1	10		T2	10		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40331	1		T1	9		T2	9		T3	19
auto[1]	11883	1		T1	10		T2	10		T4	12

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	52214	1		T1	19		T2	19		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	31106	1		T1	14		T2	14		T3	14
wkup[1]	486	1		T16	21		T129	35		T102	21
wkup[2]	329	1		T35	21		T184	15		T96	21
wkup[3]	273	1		T7	15		T35	21		T102	21
wkup[4]	316	1		T11	21		T43	8		T127	41
wkup[5]	284	1		T131	26		T49	21		T51	15
wkup[6]	251	1		T164	21		T31	26		T95	21
wkup[7]	224	1		T11	21		T12	26		T16	15
wkup[8]	294	1		T16	21		T27	21		T180	21
wkup[9]	282	1		T22	26		T31	21		T42	30
wkup[10]	344	1		T16	30		T23	26		T20	42
wkup[11]	260	1		T149	15		T95	31		T96	27
wkup[12]	242	1		T11	21		T16	26		T23	30
wkup[13]	289	1		T35	21		T116	21		T167	21
wkup[14]	212	1		T4	15		T102	30		T43	8
wkup[15]	237	1		T95	21		T96	21		T97	21
wkup[16]	110	1		T178	21		T49	26		T50	21
wkup[17]	292	1		T16	21		T48	15		T142	15
wkup[18]	371	1		T20	21		T116	21		T43	21
wkup[19]	128	1		T16	8		T97	21		T93	21
wkup[20]	367	1		T11	21		T12	30		T16	15
wkup[21]	169	1		T95	8		T96	21		T52	21
wkup[22]	202	1		T28	15		T53	21		T113	8
wkup[23]	393	1		T11	51		T23	21		T20	26
wkup[24]	486	1		T16	21		T27	40		T95	30
wkup[25]	271	1		T161	15		T97	26		T106	30
wkup[26]	228	1		T31	21		T32	15		T136	21
wkup[27]	210	1		T35	21		T141	21		T106	26
wkup[28]	236	1		T11	21		T20	29		T190	15
wkup[29]	340	1		T16	21		T21	21		T116	21
wkup[30]	258	1		T35	26		T27	21		T52	30
wkup[31]	231	1		T31	26		T153	21		T96	44
wkup[32]	236	1		T96	21		T56	49		T75	21
wkup[33]	181	1		T164	21		T31	21		T145	21
wkup[34]	364	1		T27	57		T31	21		T116	21
wkup[35]	290	1		T11	21		T129	21		T95	21
wkup[36]	354	1		T22	21		T27	26		T43	21
wkup[37]	380	1		T120	15		T27	15		T31	26
wkup[38]	295	1		T145	21		T50	21		T55	21
wkup[39]	128	1		T11	21		T96	21		T97	21
wkup[40]	285	1		T16	21		T22	21		T164	26
wkup[41]	292	1		T20	26		T145	39		T118	21
wkup[42]	381	1		T47	15		T141	15		T31	40
wkup[43]	311	1		T12	21		T16	21		T35	8
wkup[44]	275	1		T49	21		T52	26		T58	21
wkup[45]	337	1		T5	15		T20	21		T51	8
wkup[46]	246	1		T164	21		T27	21		T43	21
wkup[47]	151	1		T116	21		T43	21		T136	26
wkup[48]	166	1		T11	21		T122	15		T43	21
wkup[49]	483	1		T21	42		T164	42		T41	52
wkup[50]	280	1		T31	30		T42	21		T96	21
wkup[51]	280	1		T43	21		T136	21		T112	21
wkup[52]	325	1		T11	26		T131	26		T166	21
wkup[53]	198	1		T11	21		T97	30		T57	21
wkup[54]	356	1		T16	21		T129	15		T137	15
wkup[55]	182	1		T11	21		T141	21		T27	21
wkup[56]	248	1		T44	15		T16	42		T141	21
wkup[57]	306	1		T11	21		T141	21		T180	21
wkup[58]	233	1		T97	26		T172	15		T53	21
wkup[59]	357	1		T16	21		T35	21		T41	44
wkup[60]	196	1		T11	21		T23	21		T96	21
wkup[61]	218	1		T11	21		T97	21		T178	15
wkup[62]	239	1		T16	42		T29	15		T43	26
wkup[63]	355	1		T16	21		T95	21		T96	21
wkup_0	3565	1		T1	5		T2	5		T3	5