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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.75 99.33 93.67 100.00 98.40 99.51 47.60


Total test records in report: 427
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T121 /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1957787687 Jun 02 02:22:15 PM PDT 24 Jun 02 02:31:46 PM PDT 24 953097702356 ps
T285 /workspace/coverage/default/21.aon_timer_smoke.2233518873 Jun 02 02:22:35 PM PDT 24 Jun 02 02:22:36 PM PDT 24 491145819 ps
T286 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1091107138 Jun 02 02:24:32 PM PDT 24 Jun 02 02:24:34 PM PDT 24 342273258 ps
T287 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.523305163 Jun 02 02:24:28 PM PDT 24 Jun 02 02:24:29 PM PDT 24 550617960 ps
T288 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1794313576 Jun 02 02:24:27 PM PDT 24 Jun 02 02:24:29 PM PDT 24 490928446 ps
T36 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1981405848 Jun 02 02:24:34 PM PDT 24 Jun 02 02:24:41 PM PDT 24 4492299418 ps
T289 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1132862723 Jun 02 02:23:59 PM PDT 24 Jun 02 02:24:01 PM PDT 24 474882455 ps
T37 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.817216340 Jun 02 02:24:43 PM PDT 24 Jun 02 02:24:49 PM PDT 24 2690056618 ps
T40 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2417202675 Jun 02 02:24:27 PM PDT 24 Jun 02 02:24:29 PM PDT 24 531953797 ps
T205 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1405895502 Jun 02 02:24:31 PM PDT 24 Jun 02 02:24:32 PM PDT 24 408419667 ps
T38 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3005700439 Jun 02 02:24:18 PM PDT 24 Jun 02 02:24:22 PM PDT 24 8704419830 ps
T206 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3719523750 Jun 02 02:24:04 PM PDT 24 Jun 02 02:24:06 PM PDT 24 7240089367 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1463243266 Jun 02 02:24:13 PM PDT 24 Jun 02 02:24:15 PM PDT 24 756804393 ps
T290 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1652971150 Jun 02 02:24:04 PM PDT 24 Jun 02 02:24:06 PM PDT 24 513866200 ps
T204 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1446028653 Jun 02 02:24:02 PM PDT 24 Jun 02 02:24:03 PM PDT 24 421459958 ps
T84 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2088012698 Jun 02 02:24:19 PM PDT 24 Jun 02 02:24:20 PM PDT 24 1168454442 ps
T85 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2359548583 Jun 02 02:24:28 PM PDT 24 Jun 02 02:24:32 PM PDT 24 2885861894 ps
T291 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2157357547 Jun 02 02:24:27 PM PDT 24 Jun 02 02:24:29 PM PDT 24 510651851 ps
T39 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2724060945 Jun 02 02:24:03 PM PDT 24 Jun 02 02:24:07 PM PDT 24 7775876297 ps
T63 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2912076059 Jun 02 02:24:04 PM PDT 24 Jun 02 02:24:05 PM PDT 24 437797269 ps
T292 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1949180271 Jun 02 02:24:43 PM PDT 24 Jun 02 02:24:44 PM PDT 24 472600181 ps
T200 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1843904894 Jun 02 02:24:10 PM PDT 24 Jun 02 02:24:14 PM PDT 24 8374327920 ps
T293 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1593164574 Jun 02 02:24:30 PM PDT 24 Jun 02 02:24:32 PM PDT 24 456422863 ps
T201 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2611903525 Jun 02 02:24:27 PM PDT 24 Jun 02 02:24:29 PM PDT 24 4530084520 ps
T294 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.670879272 Jun 02 02:24:03 PM PDT 24 Jun 02 02:24:05 PM PDT 24 596675391 ps
T295 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2900176357 Jun 02 02:24:53 PM PDT 24 Jun 02 02:24:54 PM PDT 24 566859468 ps
T64 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2489836943 Jun 02 02:24:44 PM PDT 24 Jun 02 02:24:46 PM PDT 24 369944132 ps
T296 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.483591573 Jun 02 02:24:48 PM PDT 24 Jun 02 02:24:51 PM PDT 24 733200034 ps
T65 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3401099739 Jun 02 02:23:49 PM PDT 24 Jun 02 02:23:50 PM PDT 24 381146454 ps
T297 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.765454783 Jun 02 02:23:58 PM PDT 24 Jun 02 02:23:59 PM PDT 24 494928603 ps
T298 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2040568350 Jun 02 02:24:54 PM PDT 24 Jun 02 02:24:56 PM PDT 24 365432456 ps
T299 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2566369621 Jun 02 02:23:54 PM PDT 24 Jun 02 02:23:55 PM PDT 24 315335850 ps
T300 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1015362817 Jun 02 02:24:34 PM PDT 24 Jun 02 02:24:36 PM PDT 24 522706455 ps
T301 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.827856888 Jun 02 02:24:49 PM PDT 24 Jun 02 02:24:50 PM PDT 24 286917701 ps
T86 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4233167645 Jun 02 02:24:24 PM PDT 24 Jun 02 02:24:26 PM PDT 24 1181561107 ps
T302 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1332083220 Jun 02 02:24:48 PM PDT 24 Jun 02 02:24:50 PM PDT 24 472076468 ps
T303 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.156894766 Jun 02 02:24:30 PM PDT 24 Jun 02 02:24:32 PM PDT 24 452453888 ps
T304 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1537527142 Jun 02 02:24:43 PM PDT 24 Jun 02 02:24:44 PM PDT 24 315864763 ps
T305 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1516429394 Jun 02 02:23:48 PM PDT 24 Jun 02 02:23:51 PM PDT 24 537918145 ps
T66 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2286616799 Jun 02 02:24:02 PM PDT 24 Jun 02 02:24:03 PM PDT 24 523738856 ps
T306 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3119001537 Jun 02 02:24:30 PM PDT 24 Jun 02 02:24:34 PM PDT 24 8089730912 ps
T307 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.157033541 Jun 02 02:24:25 PM PDT 24 Jun 02 02:24:26 PM PDT 24 320421328 ps
T77 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.623694057 Jun 02 02:23:48 PM PDT 24 Jun 02 02:23:49 PM PDT 24 491127073 ps
T198 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3907693840 Jun 02 02:24:50 PM PDT 24 Jun 02 02:24:56 PM PDT 24 4105655909 ps
T308 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3444011633 Jun 02 02:24:32 PM PDT 24 Jun 02 02:24:36 PM PDT 24 4351978950 ps
T309 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2794293050 Jun 02 02:24:55 PM PDT 24 Jun 02 02:24:56 PM PDT 24 355336844 ps
T310 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2221638875 Jun 02 02:24:55 PM PDT 24 Jun 02 02:24:56 PM PDT 24 414639447 ps
T311 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.386639754 Jun 02 02:24:30 PM PDT 24 Jun 02 02:24:32 PM PDT 24 785141374 ps
T312 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1612916032 Jun 02 02:24:51 PM PDT 24 Jun 02 02:24:52 PM PDT 24 547664874 ps
T313 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1962077851 Jun 02 02:24:18 PM PDT 24 Jun 02 02:24:22 PM PDT 24 436125918 ps
T314 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4029204825 Jun 02 02:24:26 PM PDT 24 Jun 02 02:24:29 PM PDT 24 423121616 ps
T87 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.472531799 Jun 02 02:24:49 PM PDT 24 Jun 02 02:24:52 PM PDT 24 1365676397 ps
T88 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2191776423 Jun 02 02:24:44 PM PDT 24 Jun 02 02:24:46 PM PDT 24 1045824830 ps
T89 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.168551857 Jun 02 02:24:37 PM PDT 24 Jun 02 02:24:44 PM PDT 24 2431400486 ps
T315 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2915256132 Jun 02 02:23:49 PM PDT 24 Jun 02 02:23:51 PM PDT 24 4749395550 ps
T316 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.865071558 Jun 02 02:24:43 PM PDT 24 Jun 02 02:24:45 PM PDT 24 1195681786 ps
T317 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3516808507 Jun 02 02:24:24 PM PDT 24 Jun 02 02:24:35 PM PDT 24 8141697198 ps
T318 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1009444065 Jun 02 02:24:27 PM PDT 24 Jun 02 02:24:28 PM PDT 24 405780248 ps
T319 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2157055897 Jun 02 02:24:00 PM PDT 24 Jun 02 02:24:01 PM PDT 24 368128450 ps
T320 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1841390336 Jun 02 02:24:28 PM PDT 24 Jun 02 02:24:30 PM PDT 24 530577049 ps
T321 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1924662798 Jun 02 02:24:16 PM PDT 24 Jun 02 02:24:18 PM PDT 24 1312136631 ps
T322 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4220954717 Jun 02 02:24:10 PM PDT 24 Jun 02 02:24:12 PM PDT 24 379984431 ps
T323 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3050187972 Jun 02 02:23:54 PM PDT 24 Jun 02 02:23:56 PM PDT 24 370425883 ps
T324 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.164813365 Jun 02 02:24:55 PM PDT 24 Jun 02 02:24:56 PM PDT 24 364818681 ps
T83 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.778379686 Jun 02 02:24:41 PM PDT 24 Jun 02 02:24:42 PM PDT 24 457637193 ps
T325 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1984597231 Jun 02 02:24:27 PM PDT 24 Jun 02 02:24:29 PM PDT 24 368867383 ps
T326 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2297555381 Jun 02 02:24:40 PM PDT 24 Jun 02 02:24:42 PM PDT 24 833378763 ps
T327 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.631488612 Jun 02 02:24:24 PM PDT 24 Jun 02 02:24:25 PM PDT 24 428828218 ps
T328 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1909297091 Jun 02 02:24:12 PM PDT 24 Jun 02 02:24:13 PM PDT 24 426839386 ps
T329 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.883423817 Jun 02 02:24:38 PM PDT 24 Jun 02 02:24:39 PM PDT 24 531577573 ps
T330 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2850787347 Jun 02 02:24:15 PM PDT 24 Jun 02 02:24:16 PM PDT 24 513704998 ps
T331 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3806126067 Jun 02 02:24:37 PM PDT 24 Jun 02 02:24:38 PM PDT 24 405794413 ps
T332 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2752459240 Jun 02 02:24:19 PM PDT 24 Jun 02 02:24:20 PM PDT 24 582264454 ps
T333 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1854915811 Jun 02 02:24:49 PM PDT 24 Jun 02 02:24:51 PM PDT 24 414523756 ps
T81 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1311588704 Jun 02 02:24:33 PM PDT 24 Jun 02 02:24:34 PM PDT 24 391150311 ps
T334 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2722906247 Jun 02 02:24:26 PM PDT 24 Jun 02 02:24:27 PM PDT 24 1180393976 ps
T335 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1112588263 Jun 02 02:23:48 PM PDT 24 Jun 02 02:23:49 PM PDT 24 403630744 ps
T336 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.568140553 Jun 02 02:24:53 PM PDT 24 Jun 02 02:24:54 PM PDT 24 362086217 ps
T337 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1682406327 Jun 02 02:24:43 PM PDT 24 Jun 02 02:24:45 PM PDT 24 683262366 ps
T82 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1024294787 Jun 02 02:24:28 PM PDT 24 Jun 02 02:24:29 PM PDT 24 502218065 ps
T338 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2575995543 Jun 02 02:24:33 PM PDT 24 Jun 02 02:24:37 PM PDT 24 1917252144 ps
T339 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3447628561 Jun 02 02:23:53 PM PDT 24 Jun 02 02:23:54 PM PDT 24 343513651 ps
T340 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2325100334 Jun 02 02:24:08 PM PDT 24 Jun 02 02:24:15 PM PDT 24 3910022514 ps
T341 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2462756134 Jun 02 02:24:43 PM PDT 24 Jun 02 02:24:46 PM PDT 24 4229156949 ps
T342 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1140223648 Jun 02 02:24:10 PM PDT 24 Jun 02 02:24:19 PM PDT 24 7102618311 ps
T343 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2494748381 Jun 02 02:24:54 PM PDT 24 Jun 02 02:24:55 PM PDT 24 363320653 ps
T344 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2469554966 Jun 02 02:24:04 PM PDT 24 Jun 02 02:24:06 PM PDT 24 2141417824 ps
T345 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.785526357 Jun 02 02:23:55 PM PDT 24 Jun 02 02:23:56 PM PDT 24 971673312 ps
T346 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2851220546 Jun 02 02:24:15 PM PDT 24 Jun 02 02:24:16 PM PDT 24 452508227 ps
T347 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3843684816 Jun 02 02:24:40 PM PDT 24 Jun 02 02:24:42 PM PDT 24 509695358 ps
T348 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4236361312 Jun 02 02:24:38 PM PDT 24 Jun 02 02:24:47 PM PDT 24 8552528386 ps
T78 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2133480624 Jun 02 02:23:49 PM PDT 24 Jun 02 02:23:54 PM PDT 24 3193442767 ps
T349 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3336585354 Jun 02 02:24:24 PM PDT 24 Jun 02 02:24:27 PM PDT 24 656037213 ps
T350 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.383027097 Jun 02 02:24:15 PM PDT 24 Jun 02 02:24:24 PM PDT 24 6874225134 ps
T351 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3281432401 Jun 02 02:24:53 PM PDT 24 Jun 02 02:24:54 PM PDT 24 441052079 ps
T352 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.102920772 Jun 02 02:24:15 PM PDT 24 Jun 02 02:24:17 PM PDT 24 2432674147 ps
T353 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2946898415 Jun 02 02:24:51 PM PDT 24 Jun 02 02:24:52 PM PDT 24 358996981 ps
T354 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1215741425 Jun 02 02:24:13 PM PDT 24 Jun 02 02:24:14 PM PDT 24 479158884 ps
T355 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2359310840 Jun 02 02:24:54 PM PDT 24 Jun 02 02:24:55 PM PDT 24 421560283 ps
T356 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.100620758 Jun 02 02:24:33 PM PDT 24 Jun 02 02:24:37 PM PDT 24 2091798175 ps
T357 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3982900711 Jun 02 02:23:52 PM PDT 24 Jun 02 02:23:54 PM PDT 24 917975478 ps
T358 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1000711949 Jun 02 02:24:18 PM PDT 24 Jun 02 02:24:22 PM PDT 24 8175233480 ps
T359 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3628828920 Jun 02 02:24:19 PM PDT 24 Jun 02 02:24:21 PM PDT 24 482009952 ps
T360 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3585175748 Jun 02 02:24:09 PM PDT 24 Jun 02 02:24:11 PM PDT 24 2250086768 ps
T361 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.934741877 Jun 02 02:24:10 PM PDT 24 Jun 02 02:24:11 PM PDT 24 341890290 ps
T362 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.880906788 Jun 02 02:24:34 PM PDT 24 Jun 02 02:24:36 PM PDT 24 426214788 ps
T363 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4008818380 Jun 02 02:23:50 PM PDT 24 Jun 02 02:23:51 PM PDT 24 423461548 ps
T364 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2949846489 Jun 02 02:23:59 PM PDT 24 Jun 02 02:24:00 PM PDT 24 509833984 ps
T365 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.605627595 Jun 02 02:24:48 PM PDT 24 Jun 02 02:24:50 PM PDT 24 449773852 ps
T366 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.161553271 Jun 02 02:24:53 PM PDT 24 Jun 02 02:24:54 PM PDT 24 322423421 ps
T367 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.662979179 Jun 02 02:24:25 PM PDT 24 Jun 02 02:24:26 PM PDT 24 545090904 ps
T368 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3407134572 Jun 02 02:24:54 PM PDT 24 Jun 02 02:24:55 PM PDT 24 483919707 ps
T369 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4224787860 Jun 02 02:24:49 PM PDT 24 Jun 02 02:24:50 PM PDT 24 378213760 ps
T370 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.357143043 Jun 02 02:24:03 PM PDT 24 Jun 02 02:24:05 PM PDT 24 2316524506 ps
T371 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.271731287 Jun 02 02:24:24 PM PDT 24 Jun 02 02:24:26 PM PDT 24 378695906 ps
T79 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2914433789 Jun 02 02:23:55 PM PDT 24 Jun 02 02:24:03 PM PDT 24 3013472907 ps
T372 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3466532341 Jun 02 02:24:41 PM PDT 24 Jun 02 02:24:44 PM PDT 24 523573128 ps
T373 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2006169036 Jun 02 02:24:53 PM PDT 24 Jun 02 02:24:55 PM PDT 24 394515420 ps
T374 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.30712692 Jun 02 02:24:54 PM PDT 24 Jun 02 02:24:54 PM PDT 24 317620877 ps
T375 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3809722127 Jun 02 02:24:19 PM PDT 24 Jun 02 02:24:20 PM PDT 24 505672997 ps
T199 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3196075078 Jun 02 02:24:18 PM PDT 24 Jun 02 02:24:21 PM PDT 24 4847867234 ps
T376 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2725074840 Jun 02 02:24:42 PM PDT 24 Jun 02 02:24:44 PM PDT 24 1756340914 ps
T377 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2006249513 Jun 02 02:23:49 PM PDT 24 Jun 02 02:23:50 PM PDT 24 600387643 ps
T80 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3394510726 Jun 02 02:24:14 PM PDT 24 Jun 02 02:24:16 PM PDT 24 525373587 ps
T378 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.784882685 Jun 02 02:24:33 PM PDT 24 Jun 02 02:24:35 PM PDT 24 462999735 ps
T379 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3994281987 Jun 02 02:24:45 PM PDT 24 Jun 02 02:24:46 PM PDT 24 499010599 ps
T380 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2178042932 Jun 02 02:24:09 PM PDT 24 Jun 02 02:24:10 PM PDT 24 521891368 ps
T381 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1581096263 Jun 02 02:23:54 PM PDT 24 Jun 02 02:23:55 PM PDT 24 370373276 ps
T67 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2989901372 Jun 02 02:24:42 PM PDT 24 Jun 02 02:24:43 PM PDT 24 314284530 ps
T382 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2070418276 Jun 02 02:24:52 PM PDT 24 Jun 02 02:24:53 PM PDT 24 389752901 ps
T383 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3792596921 Jun 02 02:24:28 PM PDT 24 Jun 02 02:24:31 PM PDT 24 4533578914 ps
T384 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3134519829 Jun 02 02:24:49 PM PDT 24 Jun 02 02:24:50 PM PDT 24 555717858 ps
T385 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2191163973 Jun 02 02:23:54 PM PDT 24 Jun 02 02:23:57 PM PDT 24 4321424065 ps
T386 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2050956358 Jun 02 02:24:13 PM PDT 24 Jun 02 02:24:15 PM PDT 24 491655848 ps
T387 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2052316249 Jun 02 02:24:22 PM PDT 24 Jun 02 02:24:23 PM PDT 24 495444788 ps
T388 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3771568968 Jun 02 02:24:28 PM PDT 24 Jun 02 02:24:30 PM PDT 24 798045641 ps
T389 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3835718837 Jun 02 02:24:03 PM PDT 24 Jun 02 02:24:05 PM PDT 24 590783148 ps
T390 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1771475075 Jun 02 02:24:55 PM PDT 24 Jun 02 02:24:57 PM PDT 24 439245327 ps
T391 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1378691939 Jun 02 02:23:51 PM PDT 24 Jun 02 02:23:53 PM PDT 24 307977107 ps
T392 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3626574708 Jun 02 02:23:58 PM PDT 24 Jun 02 02:23:59 PM PDT 24 472155396 ps
T393 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.569169484 Jun 02 02:24:10 PM PDT 24 Jun 02 02:24:12 PM PDT 24 349286933 ps
T394 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3669091649 Jun 02 02:24:49 PM PDT 24 Jun 02 02:24:51 PM PDT 24 475883479 ps
T395 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2313256280 Jun 02 02:24:49 PM PDT 24 Jun 02 02:24:50 PM PDT 24 463532636 ps
T396 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2732501265 Jun 02 02:24:17 PM PDT 24 Jun 02 02:24:19 PM PDT 24 355929756 ps
T397 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1145422807 Jun 02 02:24:43 PM PDT 24 Jun 02 02:24:45 PM PDT 24 493093561 ps
T398 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.858188427 Jun 02 02:24:51 PM PDT 24 Jun 02 02:24:52 PM PDT 24 437744128 ps
T399 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3014010739 Jun 02 02:24:55 PM PDT 24 Jun 02 02:24:56 PM PDT 24 309369768 ps
T400 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4163597849 Jun 02 02:23:54 PM PDT 24 Jun 02 02:23:55 PM PDT 24 310229561 ps
T401 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3066179221 Jun 02 02:24:10 PM PDT 24 Jun 02 02:24:13 PM PDT 24 483452322 ps
T402 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1990943692 Jun 02 02:24:53 PM PDT 24 Jun 02 02:24:54 PM PDT 24 433747173 ps
T403 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1823622862 Jun 02 02:24:38 PM PDT 24 Jun 02 02:24:39 PM PDT 24 487409546 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.538588615 Jun 02 02:24:09 PM PDT 24 Jun 02 02:24:10 PM PDT 24 863060017 ps
T405 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.169961652 Jun 02 02:24:44 PM PDT 24 Jun 02 02:24:48 PM PDT 24 7815784107 ps
T406 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.531336819 Jun 02 02:24:13 PM PDT 24 Jun 02 02:24:13 PM PDT 24 449120997 ps
T407 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1488325053 Jun 02 02:24:29 PM PDT 24 Jun 02 02:24:32 PM PDT 24 2306322264 ps
T408 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1309661200 Jun 02 02:24:26 PM PDT 24 Jun 02 02:24:41 PM PDT 24 8154069661 ps
T409 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.534363960 Jun 02 02:24:37 PM PDT 24 Jun 02 02:24:43 PM PDT 24 4221720201 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.186655673 Jun 02 02:24:27 PM PDT 24 Jun 02 02:24:29 PM PDT 24 533254585 ps
T411 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2193541445 Jun 02 02:24:49 PM PDT 24 Jun 02 02:24:51 PM PDT 24 512839636 ps
T412 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4068598315 Jun 02 02:24:27 PM PDT 24 Jun 02 02:24:30 PM PDT 24 412176031 ps
T413 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3471646168 Jun 02 02:24:09 PM PDT 24 Jun 02 02:24:10 PM PDT 24 520899695 ps
T414 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.951746982 Jun 02 02:24:47 PM PDT 24 Jun 02 02:24:49 PM PDT 24 307205425 ps
T68 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4013651207 Jun 02 02:24:38 PM PDT 24 Jun 02 02:24:39 PM PDT 24 444073457 ps
T415 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3359684968 Jun 02 02:24:40 PM PDT 24 Jun 02 02:24:41 PM PDT 24 491629209 ps
T416 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.993612182 Jun 02 02:24:25 PM PDT 24 Jun 02 02:24:26 PM PDT 24 316864975 ps
T417 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2099328463 Jun 02 02:24:50 PM PDT 24 Jun 02 02:24:51 PM PDT 24 345153158 ps
T418 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.4172083826 Jun 02 02:24:33 PM PDT 24 Jun 02 02:24:36 PM PDT 24 522989073 ps
T419 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2919458995 Jun 02 02:24:48 PM PDT 24 Jun 02 02:24:49 PM PDT 24 432733446 ps
T420 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3003476251 Jun 02 02:24:02 PM PDT 24 Jun 02 02:24:03 PM PDT 24 739723627 ps
T421 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2536626302 Jun 02 02:24:13 PM PDT 24 Jun 02 02:24:15 PM PDT 24 511561495 ps
T422 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.15603247 Jun 02 02:24:29 PM PDT 24 Jun 02 02:24:31 PM PDT 24 305089870 ps
T423 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1582773496 Jun 02 02:24:44 PM PDT 24 Jun 02 02:24:47 PM PDT 24 522863566 ps
T424 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.917502043 Jun 02 02:24:58 PM PDT 24 Jun 02 02:24:59 PM PDT 24 307037021 ps
T425 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3316330766 Jun 02 02:24:37 PM PDT 24 Jun 02 02:24:39 PM PDT 24 403851047 ps
T426 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3606361251 Jun 02 02:24:53 PM PDT 24 Jun 02 02:24:54 PM PDT 24 283735212 ps
T69 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3440348983 Jun 02 02:24:09 PM PDT 24 Jun 02 02:24:10 PM PDT 24 536568669 ps
T427 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1727669654 Jun 02 02:24:28 PM PDT 24 Jun 02 02:24:31 PM PDT 24 918046031 ps

Test location /workspace/coverage/default/39.aon_timer_prescaler.2107303495
Short name T3
Test name
Test status
Simulation time 28413353516 ps
CPU time 42.83 seconds
Started Jun 02 02:23:26 PM PDT 24
Finished Jun 02 02:24:10 PM PDT 24
Peak memory 191892 kb
Host smart-a54d99e9-d281-44d8-adab-70091013f435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107303495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2107303495
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.765387705
Short name T11
Test name
Test status
Simulation time 862522575726 ps
CPU time 323.94 seconds
Started Jun 02 02:22:24 PM PDT 24
Finished Jun 02 02:27:49 PM PDT 24
Peak memory 206824 kb
Host smart-9fda55a5-c382-498c-bc41-2de661401cc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765387705 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.765387705
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3005700439
Short name T38
Test name
Test status
Simulation time 8704419830 ps
CPU time 3.81 seconds
Started Jun 02 02:24:18 PM PDT 24
Finished Jun 02 02:24:22 PM PDT 24
Peak memory 197820 kb
Host smart-8ce09018-d7d3-4e6b-af57-8a2af705a023
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005700439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3005700439
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2477206886
Short name T20
Test name
Test status
Simulation time 60908977265 ps
CPU time 20.54 seconds
Started Jun 02 02:23:17 PM PDT 24
Finished Jun 02 02:23:38 PM PDT 24
Peak memory 192596 kb
Host smart-71a13412-779f-43fc-89d4-8de01faf610d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477206886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2477206886
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2205069609
Short name T58
Test name
Test status
Simulation time 99507440427 ps
CPU time 529.72 seconds
Started Jun 02 02:23:17 PM PDT 24
Finished Jun 02 02:32:07 PM PDT 24
Peak memory 204684 kb
Host smart-bd02a68f-e6d1-4816-9c6e-60fad040aaeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205069609 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2205069609
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3060222378
Short name T96
Test name
Test status
Simulation time 188146453727 ps
CPU time 313.64 seconds
Started Jun 02 02:23:11 PM PDT 24
Finished Jun 02 02:28:25 PM PDT 24
Peak memory 201564 kb
Host smart-740b1352-6a88-4e26-ad02-a9eb6750977b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060222378 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3060222378
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2459576876
Short name T74
Test name
Test status
Simulation time 584136210665 ps
CPU time 240.4 seconds
Started Jun 02 02:23:47 PM PDT 24
Finished Jun 02 02:27:47 PM PDT 24
Peak memory 208684 kb
Host smart-2ec370d4-b729-48cf-89ee-6a88cfdc9be3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459576876 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2459576876
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2674694943
Short name T61
Test name
Test status
Simulation time 564080592926 ps
CPU time 983.65 seconds
Started Jun 02 02:23:41 PM PDT 24
Finished Jun 02 02:40:05 PM PDT 24
Peak memory 209916 kb
Host smart-b85f721f-544a-4aaf-b17b-cf923b60d0ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674694943 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2674694943
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1113010659
Short name T98
Test name
Test status
Simulation time 77327715268 ps
CPU time 590.24 seconds
Started Jun 02 02:23:35 PM PDT 24
Finished Jun 02 02:33:26 PM PDT 24
Peak memory 214956 kb
Host smart-e7ad20a4-5256-4e8f-ba50-d521a80da77c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113010659 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1113010659
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2010861369
Short name T113
Test name
Test status
Simulation time 179481286745 ps
CPU time 541.89 seconds
Started Jun 02 02:21:43 PM PDT 24
Finished Jun 02 02:30:45 PM PDT 24
Peak memory 213004 kb
Host smart-dedafdcb-c9b6-4c84-8840-44dc78503b58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010861369 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2010861369
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3690524326
Short name T92
Test name
Test status
Simulation time 250430742620 ps
CPU time 472.62 seconds
Started Jun 02 02:22:10 PM PDT 24
Finished Jun 02 02:30:03 PM PDT 24
Peak memory 204128 kb
Host smart-3805d282-2171-4d26-a6ef-fc9425a32653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690524326 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3690524326
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3590014903
Short name T94
Test name
Test status
Simulation time 278104489268 ps
CPU time 826.84 seconds
Started Jun 02 02:23:29 PM PDT 24
Finished Jun 02 02:37:16 PM PDT 24
Peak memory 215032 kb
Host smart-0597e4c4-3a0c-41a8-b53d-b6cfe553f7b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590014903 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3590014903
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2103484378
Short name T19
Test name
Test status
Simulation time 7873682684 ps
CPU time 3.71 seconds
Started Jun 02 02:21:17 PM PDT 24
Finished Jun 02 02:21:21 PM PDT 24
Peak memory 215728 kb
Host smart-425a44b4-4fd5-4e3e-8e54-84ce3b6eaccf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103484378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2103484378
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.4176274025
Short name T118
Test name
Test status
Simulation time 60774919508 ps
CPU time 114.75 seconds
Started Jun 02 02:23:04 PM PDT 24
Finished Jun 02 02:24:59 PM PDT 24
Peak memory 198604 kb
Host smart-d770fad4-1bee-4629-96be-ca653509499c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176274025 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.4176274025
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3802211850
Short name T43
Test name
Test status
Simulation time 554340653675 ps
CPU time 489.07 seconds
Started Jun 02 02:23:32 PM PDT 24
Finished Jun 02 02:31:41 PM PDT 24
Peak memory 211588 kb
Host smart-5dd0390a-e852-4dbc-af31-203f0c4d2b20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802211850 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3802211850
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1548765858
Short name T101
Test name
Test status
Simulation time 177450173208 ps
CPU time 44.35 seconds
Started Jun 02 02:23:37 PM PDT 24
Finished Jun 02 02:24:22 PM PDT 24
Peak memory 192964 kb
Host smart-809ecb92-5b3f-44cc-a7b5-21d09631f975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548765858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1548765858
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.902580016
Short name T111
Test name
Test status
Simulation time 80641983503 ps
CPU time 24.9 seconds
Started Jun 02 02:23:32 PM PDT 24
Finished Jun 02 02:23:58 PM PDT 24
Peak memory 192512 kb
Host smart-f1bac8ba-4a76-4aa5-aaf8-4994b22cb8c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902580016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.902580016
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3540588869
Short name T141
Test name
Test status
Simulation time 133313970765 ps
CPU time 45.53 seconds
Started Jun 02 02:22:34 PM PDT 24
Finished Jun 02 02:23:20 PM PDT 24
Peak memory 192480 kb
Host smart-56331434-e474-4d01-929d-342e16d3913b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540588869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3540588869
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3790351143
Short name T16
Test name
Test status
Simulation time 161877419687 ps
CPU time 777.43 seconds
Started Jun 02 02:22:53 PM PDT 24
Finished Jun 02 02:35:51 PM PDT 24
Peak memory 208836 kb
Host smart-4ad44358-57fb-44c3-8887-9273187709ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790351143 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3790351143
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2958236154
Short name T160
Test name
Test status
Simulation time 45962199857 ps
CPU time 479.12 seconds
Started Jun 02 02:22:49 PM PDT 24
Finished Jun 02 02:30:49 PM PDT 24
Peak memory 201048 kb
Host smart-b6f7a91e-9ab1-49d9-b96c-c66fd53853af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958236154 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2958236154
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3369589492
Short name T134
Test name
Test status
Simulation time 22829755117 ps
CPU time 92.87 seconds
Started Jun 02 02:23:39 PM PDT 24
Finished Jun 02 02:25:12 PM PDT 24
Peak memory 206832 kb
Host smart-5839f3b5-216a-4545-95bc-aa9278f5a06a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369589492 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3369589492
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3374469514
Short name T105
Test name
Test status
Simulation time 185437757990 ps
CPU time 379.84 seconds
Started Jun 02 02:22:58 PM PDT 24
Finished Jun 02 02:29:19 PM PDT 24
Peak memory 210448 kb
Host smart-be06e90d-1a41-4b4e-94ea-eec1119a6d5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374469514 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3374469514
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1522861375
Short name T97
Test name
Test status
Simulation time 304236141784 ps
CPU time 321.68 seconds
Started Jun 02 02:23:15 PM PDT 24
Finished Jun 02 02:28:37 PM PDT 24
Peak memory 200396 kb
Host smart-bcd0c227-3cc7-4542-bb55-7b0cd979b2b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522861375 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1522861375
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2482531560
Short name T73
Test name
Test status
Simulation time 79910243564 ps
CPU time 71.56 seconds
Started Jun 02 02:22:50 PM PDT 24
Finished Jun 02 02:24:02 PM PDT 24
Peak memory 192920 kb
Host smart-9baa32a4-ede5-4fbb-81f3-9e5c7a37b94a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482531560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2482531560
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.192433345
Short name T109
Test name
Test status
Simulation time 63252599795 ps
CPU time 25.11 seconds
Started Jun 02 02:23:00 PM PDT 24
Finished Jun 02 02:23:25 PM PDT 24
Peak memory 192008 kb
Host smart-dcb17249-4bf3-44eb-9908-53479dac3127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192433345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.192433345
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3097738093
Short name T102
Test name
Test status
Simulation time 286623485728 ps
CPU time 78.39 seconds
Started Jun 02 02:23:41 PM PDT 24
Finished Jun 02 02:25:00 PM PDT 24
Peak memory 191908 kb
Host smart-bc4123bd-218c-454d-8cd1-f5cea181d9e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097738093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3097738093
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3345375025
Short name T124
Test name
Test status
Simulation time 276761963712 ps
CPU time 183.22 seconds
Started Jun 02 02:23:06 PM PDT 24
Finished Jun 02 02:26:09 PM PDT 24
Peak memory 191892 kb
Host smart-584ea4b9-ed29-40bf-928c-9c6f403f2abe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345375025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3345375025
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2009382677
Short name T125
Test name
Test status
Simulation time 40247105190 ps
CPU time 429.99 seconds
Started Jun 02 02:23:49 PM PDT 24
Finished Jun 02 02:30:59 PM PDT 24
Peak memory 208568 kb
Host smart-f5be3005-d0f6-45dc-83cc-fb71b53faf59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009382677 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2009382677
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3401099739
Short name T65
Test name
Test status
Simulation time 381146454 ps
CPU time 0.77 seconds
Started Jun 02 02:23:49 PM PDT 24
Finished Jun 02 02:23:50 PM PDT 24
Peak memory 183664 kb
Host smart-cabc2ca3-8682-4700-8c39-18ceb3496945
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401099739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3401099739
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2971418094
Short name T95
Test name
Test status
Simulation time 126446145256 ps
CPU time 252.26 seconds
Started Jun 02 02:23:14 PM PDT 24
Finished Jun 02 02:27:26 PM PDT 24
Peak memory 200928 kb
Host smart-c91ca6b3-cb61-4433-9c11-74b196c27997
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971418094 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2971418094
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1802742825
Short name T106
Test name
Test status
Simulation time 18832402346 ps
CPU time 156.51 seconds
Started Jun 02 02:23:10 PM PDT 24
Finished Jun 02 02:25:47 PM PDT 24
Peak memory 198636 kb
Host smart-575b61ab-1a01-435c-a65e-2009c88152b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802742825 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1802742825
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.429068127
Short name T52
Test name
Test status
Simulation time 30803765473 ps
CPU time 67.77 seconds
Started Jun 02 02:22:03 PM PDT 24
Finished Jun 02 02:23:11 PM PDT 24
Peak memory 206800 kb
Host smart-c3b9291a-56f9-4ae4-927b-b902e2e8ff22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429068127 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.429068127
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1065966147
Short name T56
Test name
Test status
Simulation time 203248689405 ps
CPU time 302.67 seconds
Started Jun 02 02:23:24 PM PDT 24
Finished Jun 02 02:28:27 PM PDT 24
Peak memory 208188 kb
Host smart-e12f37a5-d5ca-4c8a-b0c0-5ebe39179406
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065966147 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1065966147
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1500852638
Short name T132
Test name
Test status
Simulation time 271452346388 ps
CPU time 45.15 seconds
Started Jun 02 02:22:17 PM PDT 24
Finished Jun 02 02:23:03 PM PDT 24
Peak memory 192680 kb
Host smart-babb22a3-6aeb-4b3f-89b5-846116222b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500852638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1500852638
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1361469749
Short name T59
Test name
Test status
Simulation time 488937369455 ps
CPU time 853.76 seconds
Started Jun 02 02:22:43 PM PDT 24
Finished Jun 02 02:36:57 PM PDT 24
Peak memory 214972 kb
Host smart-0882ff21-7b0a-4d0c-b57e-fde9f3d72bc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361469749 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1361469749
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2339732849
Short name T143
Test name
Test status
Simulation time 10557839476 ps
CPU time 23.45 seconds
Started Jun 02 02:21:29 PM PDT 24
Finished Jun 02 02:21:53 PM PDT 24
Peak memory 198652 kb
Host smart-2a8baa37-42c9-4ba0-8608-7b7bd2a66cfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339732849 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2339732849
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2360429159
Short name T152
Test name
Test status
Simulation time 55873440940 ps
CPU time 94.49 seconds
Started Jun 02 02:22:54 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 192672 kb
Host smart-a5583f4a-e6dd-4b5e-8d9b-ca90e1339802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360429159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2360429159
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.4018873569
Short name T133
Test name
Test status
Simulation time 21004632267 ps
CPU time 152.68 seconds
Started Jun 02 02:23:44 PM PDT 24
Finished Jun 02 02:26:17 PM PDT 24
Peak memory 214292 kb
Host smart-89edcf40-ce38-4a65-a535-2566a14c45d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018873569 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.4018873569
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1780233175
Short name T158
Test name
Test status
Simulation time 106951336968 ps
CPU time 284.84 seconds
Started Jun 02 02:21:49 PM PDT 24
Finished Jun 02 02:26:34 PM PDT 24
Peak memory 201388 kb
Host smart-63753b63-e589-4d4b-a6c9-5d1e53d2d65f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780233175 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1780233175
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1957787687
Short name T121
Test name
Test status
Simulation time 953097702356 ps
CPU time 570.49 seconds
Started Jun 02 02:22:15 PM PDT 24
Finished Jun 02 02:31:46 PM PDT 24
Peak memory 204888 kb
Host smart-2e4a7d0b-836b-4b01-becb-01fd30eac9af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957787687 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1957787687
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3510056914
Short name T119
Test name
Test status
Simulation time 52111876793 ps
CPU time 135.52 seconds
Started Jun 02 02:21:16 PM PDT 24
Finished Jun 02 02:23:31 PM PDT 24
Peak memory 198600 kb
Host smart-53a87c85-a7d8-4709-86f0-f9acb0c26b7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510056914 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3510056914
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3949684350
Short name T123
Test name
Test status
Simulation time 233487800560 ps
CPU time 92.5 seconds
Started Jun 02 02:22:42 PM PDT 24
Finished Jun 02 02:24:15 PM PDT 24
Peak memory 192572 kb
Host smart-6f89bce6-4f28-422d-9dc5-b18feb292598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949684350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3949684350
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2149877237
Short name T50
Test name
Test status
Simulation time 167266267065 ps
CPU time 365.79 seconds
Started Jun 02 02:22:43 PM PDT 24
Finished Jun 02 02:28:49 PM PDT 24
Peak memory 206828 kb
Host smart-00d98222-6d8b-4184-80b3-e4256cfe1038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149877237 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2149877237
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1119775798
Short name T116
Test name
Test status
Simulation time 697461223809 ps
CPU time 1068.63 seconds
Started Jun 02 02:23:06 PM PDT 24
Finished Jun 02 02:40:55 PM PDT 24
Peak memory 192320 kb
Host smart-304c469f-c8d4-4f41-9918-265703313142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119775798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1119775798
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1987443694
Short name T136
Test name
Test status
Simulation time 16132727195 ps
CPU time 123.04 seconds
Started Jun 02 02:23:23 PM PDT 24
Finished Jun 02 02:25:26 PM PDT 24
Peak memory 198668 kb
Host smart-299ee64b-35d9-41a9-bf63-367aa141380f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987443694 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1987443694
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1039626207
Short name T31
Test name
Test status
Simulation time 93232682452 ps
CPU time 221.64 seconds
Started Jun 02 02:21:24 PM PDT 24
Finished Jun 02 02:25:06 PM PDT 24
Peak memory 208544 kb
Host smart-0b4ec4be-b286-435e-a78e-f04724507486
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039626207 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1039626207
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2706384826
Short name T115
Test name
Test status
Simulation time 255932167437 ps
CPU time 380.78 seconds
Started Jun 02 02:23:04 PM PDT 24
Finished Jun 02 02:29:25 PM PDT 24
Peak memory 193020 kb
Host smart-1e5a9cae-f4ac-4459-b09c-ce6ef90b9fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706384826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2706384826
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.117858330
Short name T103
Test name
Test status
Simulation time 127779696113 ps
CPU time 55.65 seconds
Started Jun 02 02:21:43 PM PDT 24
Finished Jun 02 02:22:39 PM PDT 24
Peak memory 191896 kb
Host smart-4e65b3f5-bff1-47a4-ada4-866df263b4fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117858330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.117858330
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1599906623
Short name T114
Test name
Test status
Simulation time 24352969053 ps
CPU time 15.09 seconds
Started Jun 02 02:21:56 PM PDT 24
Finished Jun 02 02:22:11 PM PDT 24
Peak memory 206824 kb
Host smart-aa06caad-37ef-4af4-9734-0bab93153cfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599906623 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1599906623
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2383166673
Short name T127
Test name
Test status
Simulation time 220895208482 ps
CPU time 336.75 seconds
Started Jun 02 02:22:16 PM PDT 24
Finished Jun 02 02:27:53 PM PDT 24
Peak memory 192972 kb
Host smart-22917823-13ec-4e65-ad1c-fc10f5ceb0c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383166673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2383166673
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1332924058
Short name T60
Test name
Test status
Simulation time 80888854966 ps
CPU time 773.05 seconds
Started Jun 02 02:23:05 PM PDT 24
Finished Jun 02 02:35:59 PM PDT 24
Peak memory 214168 kb
Host smart-df69975e-2e4e-42ad-86ce-29533a1a0a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332924058 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1332924058
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.4060594898
Short name T22
Test name
Test status
Simulation time 161395173102 ps
CPU time 56.36 seconds
Started Jun 02 02:23:28 PM PDT 24
Finished Jun 02 02:24:24 PM PDT 24
Peak memory 191856 kb
Host smart-b149adc4-44f3-4caa-88d2-d04f8a9db645
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060594898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.4060594898
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.552963212
Short name T135
Test name
Test status
Simulation time 480487187271 ps
CPU time 368.6 seconds
Started Jun 02 02:22:22 PM PDT 24
Finished Jun 02 02:28:31 PM PDT 24
Peak memory 192552 kb
Host smart-294cb469-48c5-4b49-83a2-a28df2c8e619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552963212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.552963212
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3892883855
Short name T75
Test name
Test status
Simulation time 63786251288 ps
CPU time 134.1 seconds
Started Jun 02 02:23:42 PM PDT 24
Finished Jun 02 02:25:56 PM PDT 24
Peak memory 206800 kb
Host smart-cdb1e5e7-1047-46df-8ecb-3410c3372f22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892883855 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3892883855
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3262371041
Short name T112
Test name
Test status
Simulation time 264064307029 ps
CPU time 338 seconds
Started Jun 02 02:23:49 PM PDT 24
Finished Jun 02 02:29:27 PM PDT 24
Peak memory 191888 kb
Host smart-27965145-2ceb-4976-bf35-2130a9d90019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262371041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3262371041
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.4124169359
Short name T128
Test name
Test status
Simulation time 186394488943 ps
CPU time 81.33 seconds
Started Jun 02 02:23:49 PM PDT 24
Finished Jun 02 02:25:11 PM PDT 24
Peak memory 192568 kb
Host smart-3cbc6ea4-a8c0-4cee-9d58-3d7e685955ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124169359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.4124169359
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.824909303
Short name T104
Test name
Test status
Simulation time 315511961883 ps
CPU time 174.56 seconds
Started Jun 02 02:22:11 PM PDT 24
Finished Jun 02 02:25:06 PM PDT 24
Peak memory 191904 kb
Host smart-34fc1062-a4cc-4656-b170-7ee6d07cdd25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824909303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.824909303
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3672120383
Short name T145
Test name
Test status
Simulation time 435806758993 ps
CPU time 295.65 seconds
Started Jun 02 02:22:33 PM PDT 24
Finished Jun 02 02:27:29 PM PDT 24
Peak memory 192248 kb
Host smart-8db3801b-eeeb-4017-8172-67614c319506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672120383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3672120383
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1348144350
Short name T144
Test name
Test status
Simulation time 389169173995 ps
CPU time 94.45 seconds
Started Jun 02 02:22:29 PM PDT 24
Finished Jun 02 02:24:04 PM PDT 24
Peak memory 191916 kb
Host smart-185db8d2-9b2b-4cbb-8996-dfabc5948ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348144350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1348144350
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.277088435
Short name T49
Test name
Test status
Simulation time 64119640399 ps
CPU time 133.46 seconds
Started Jun 02 02:22:34 PM PDT 24
Finished Jun 02 02:24:48 PM PDT 24
Peak memory 206796 kb
Host smart-b420bab8-564e-4035-bea5-f3c7f479acee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277088435 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.277088435
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1250032592
Short name T139
Test name
Test status
Simulation time 77231596554 ps
CPU time 170.44 seconds
Started Jun 02 02:23:27 PM PDT 24
Finished Jun 02 02:26:18 PM PDT 24
Peak memory 207208 kb
Host smart-78cbdef5-bb28-4422-af17-16aaed4b6aa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250032592 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1250032592
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2474455796
Short name T53
Test name
Test status
Simulation time 124400724448 ps
CPU time 102.43 seconds
Started Jun 02 02:21:49 PM PDT 24
Finished Jun 02 02:23:32 PM PDT 24
Peak memory 191916 kb
Host smart-bed1714c-7e23-4d3c-a205-4a2f29896ed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474455796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2474455796
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1115400808
Short name T108
Test name
Test status
Simulation time 11807232399 ps
CPU time 4.94 seconds
Started Jun 02 02:22:33 PM PDT 24
Finished Jun 02 02:22:38 PM PDT 24
Peak memory 183964 kb
Host smart-a9078e8b-f8bd-43d4-80d9-395232074d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115400808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1115400808
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1995362163
Short name T30
Test name
Test status
Simulation time 429535316 ps
CPU time 1.33 seconds
Started Jun 02 02:23:33 PM PDT 24
Finished Jun 02 02:23:35 PM PDT 24
Peak memory 196376 kb
Host smart-23d2bdd8-51c5-43cb-9bfc-7291cc8dbc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995362163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1995362163
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3757482049
Short name T165
Test name
Test status
Simulation time 334869122388 ps
CPU time 63.48 seconds
Started Jun 02 02:21:24 PM PDT 24
Finished Jun 02 02:22:28 PM PDT 24
Peak memory 192600 kb
Host smart-cb2212c9-ddab-4d17-bd59-6bbedd9a64ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757482049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3757482049
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1969548224
Short name T122
Test name
Test status
Simulation time 750772486 ps
CPU time 0.63 seconds
Started Jun 02 02:22:33 PM PDT 24
Finished Jun 02 02:22:34 PM PDT 24
Peak memory 196272 kb
Host smart-9ab43f06-c614-4a24-a4a2-97ba7dc07095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969548224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1969548224
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2518648153
Short name T150
Test name
Test status
Simulation time 74606537224 ps
CPU time 107.88 seconds
Started Jun 02 02:21:29 PM PDT 24
Finished Jun 02 02:23:18 PM PDT 24
Peak memory 191880 kb
Host smart-eefbfe16-6e89-4638-a61f-8fee9f14b678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518648153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2518648153
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1302125744
Short name T147
Test name
Test status
Simulation time 552665560 ps
CPU time 0.92 seconds
Started Jun 02 02:22:34 PM PDT 24
Finished Jun 02 02:22:36 PM PDT 24
Peak memory 196440 kb
Host smart-19973aef-d88e-4641-8aee-c82d73272f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302125744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1302125744
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3916214819
Short name T100
Test name
Test status
Simulation time 247569985160 ps
CPU time 87.28 seconds
Started Jun 02 02:22:36 PM PDT 24
Finished Jun 02 02:24:03 PM PDT 24
Peak memory 191840 kb
Host smart-901c460c-ddd1-44a4-bbed-34a0374fb769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916214819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3916214819
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.80594526
Short name T154
Test name
Test status
Simulation time 363727502 ps
CPU time 1.1 seconds
Started Jun 02 02:22:41 PM PDT 24
Finished Jun 02 02:22:43 PM PDT 24
Peak memory 196460 kb
Host smart-ac3383b1-08c9-4f0e-a97c-8cb543a74459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80594526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.80594526
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.546276467
Short name T126
Test name
Test status
Simulation time 406223406 ps
CPU time 0.73 seconds
Started Jun 02 02:23:05 PM PDT 24
Finished Jun 02 02:23:06 PM PDT 24
Peak memory 196484 kb
Host smart-1c952c5a-3761-4e57-9c60-b83777066a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546276467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.546276467
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1352647105
Short name T131
Test name
Test status
Simulation time 107635356612 ps
CPU time 173.84 seconds
Started Jun 02 02:23:20 PM PDT 24
Finished Jun 02 02:26:15 PM PDT 24
Peak memory 192640 kb
Host smart-8939071b-a003-4d6e-b605-f749c1354b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352647105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1352647105
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2769873143
Short name T129
Test name
Test status
Simulation time 371437879719 ps
CPU time 139.41 seconds
Started Jun 02 02:21:57 PM PDT 24
Finished Jun 02 02:24:16 PM PDT 24
Peak memory 191876 kb
Host smart-8b0937d9-5930-4736-806b-c4afb38d2f85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769873143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2769873143
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1582619726
Short name T29
Test name
Test status
Simulation time 431867517 ps
CPU time 1.19 seconds
Started Jun 02 02:22:47 PM PDT 24
Finished Jun 02 02:22:49 PM PDT 24
Peak memory 196492 kb
Host smart-951ee0ad-8f7a-4ec7-b555-5a771aa92689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582619726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1582619726
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1262617154
Short name T157
Test name
Test status
Simulation time 193089107914 ps
CPU time 335.57 seconds
Started Jun 02 02:21:36 PM PDT 24
Finished Jun 02 02:27:12 PM PDT 24
Peak memory 184056 kb
Host smart-72fc25d3-d569-4109-ab93-d8d80e6a28df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262617154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1262617154
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2104293850
Short name T148
Test name
Test status
Simulation time 446561340 ps
CPU time 0.92 seconds
Started Jun 02 02:23:15 PM PDT 24
Finished Jun 02 02:23:16 PM PDT 24
Peak memory 196516 kb
Host smart-26cea18c-395f-4f58-90ba-d7e5715a8bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104293850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2104293850
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3231279479
Short name T120
Test name
Test status
Simulation time 430676283 ps
CPU time 0.77 seconds
Started Jun 02 02:23:11 PM PDT 24
Finished Jun 02 02:23:12 PM PDT 24
Peak memory 196512 kb
Host smart-bd865a10-d140-44fb-9a83-b3e502e632eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231279479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3231279479
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2262495803
Short name T176
Test name
Test status
Simulation time 178547468999 ps
CPU time 299.18 seconds
Started Jun 02 02:23:14 PM PDT 24
Finished Jun 02 02:28:14 PM PDT 24
Peak memory 192976 kb
Host smart-2e6d7e6d-3063-41b9-b9ab-e11d278fddad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262495803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2262495803
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2240859323
Short name T149
Test name
Test status
Simulation time 589144952 ps
CPU time 1.02 seconds
Started Jun 02 02:23:23 PM PDT 24
Finished Jun 02 02:23:24 PM PDT 24
Peak memory 196488 kb
Host smart-d55665b6-6ad5-4b05-acb9-f4a1d6210325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240859323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2240859323
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.583968918
Short name T57
Test name
Test status
Simulation time 189432122754 ps
CPU time 47.25 seconds
Started Jun 02 02:23:23 PM PDT 24
Finished Jun 02 02:24:11 PM PDT 24
Peak memory 192656 kb
Host smart-34858552-5de3-4cd1-8850-bebdddbe9a34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583968918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.583968918
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1926118760
Short name T99
Test name
Test status
Simulation time 48119818188 ps
CPU time 70.15 seconds
Started Jun 02 02:21:42 PM PDT 24
Finished Jun 02 02:22:52 PM PDT 24
Peak memory 191828 kb
Host smart-896e12d3-f158-4fd8-a267-deef1127fd07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926118760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1926118760
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1805197953
Short name T5
Test name
Test status
Simulation time 414680397 ps
CPU time 1.22 seconds
Started Jun 02 02:23:37 PM PDT 24
Finished Jun 02 02:23:39 PM PDT 24
Peak memory 196416 kb
Host smart-d89f97a9-e300-4881-9447-a9ae5cce3d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805197953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1805197953
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1458069171
Short name T107
Test name
Test status
Simulation time 73658157364 ps
CPU time 112.81 seconds
Started Jun 02 02:23:36 PM PDT 24
Finished Jun 02 02:25:29 PM PDT 24
Peak memory 191928 kb
Host smart-ab65721e-4f23-4a33-848b-bb53e0cfbf79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458069171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1458069171
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3788397964
Short name T137
Test name
Test status
Simulation time 593357880 ps
CPU time 0.81 seconds
Started Jun 02 02:21:23 PM PDT 24
Finished Jun 02 02:21:24 PM PDT 24
Peak memory 196404 kb
Host smart-8149c92a-23b2-48cb-9eb5-799436d5ed62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788397964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3788397964
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1904329799
Short name T27
Test name
Test status
Simulation time 277917734046 ps
CPU time 617.16 seconds
Started Jun 02 02:22:29 PM PDT 24
Finished Jun 02 02:32:46 PM PDT 24
Peak memory 204760 kb
Host smart-69bd3f23-bad9-479e-8c22-bb1bb0bbd9a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904329799 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1904329799
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3363060831
Short name T93
Test name
Test status
Simulation time 22219827987 ps
CPU time 237.49 seconds
Started Jun 02 02:22:36 PM PDT 24
Finished Jun 02 02:26:34 PM PDT 24
Peak memory 198632 kb
Host smart-183e26a6-a7ad-4e33-ac78-15aeba5b4fe5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363060831 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3363060831
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.463247697
Short name T130
Test name
Test status
Simulation time 383328948 ps
CPU time 1.21 seconds
Started Jun 02 02:23:04 PM PDT 24
Finished Jun 02 02:23:05 PM PDT 24
Peak memory 196452 kb
Host smart-91712736-3209-4b0d-935d-fdb7aea51113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463247697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.463247697
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2438631243
Short name T51
Test name
Test status
Simulation time 41658947446 ps
CPU time 352.96 seconds
Started Jun 02 02:23:00 PM PDT 24
Finished Jun 02 02:28:53 PM PDT 24
Peak memory 206840 kb
Host smart-b1290fe8-10ae-4d85-8396-22c800460609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438631243 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2438631243
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1288677288
Short name T164
Test name
Test status
Simulation time 65777776260 ps
CPU time 95.84 seconds
Started Jun 02 02:23:10 PM PDT 24
Finished Jun 02 02:24:46 PM PDT 24
Peak memory 193056 kb
Host smart-c6cb6f6b-5982-481f-b46b-76f19d954320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288677288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1288677288
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.732306217
Short name T28
Test name
Test status
Simulation time 535823765 ps
CPU time 0.96 seconds
Started Jun 02 02:23:16 PM PDT 24
Finished Jun 02 02:23:17 PM PDT 24
Peak memory 196432 kb
Host smart-218f3399-eb14-46e4-9523-204844584b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732306217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.732306217
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2248730399
Short name T163
Test name
Test status
Simulation time 20956975543 ps
CPU time 170.38 seconds
Started Jun 02 02:21:42 PM PDT 24
Finished Jun 02 02:24:33 PM PDT 24
Peak memory 213340 kb
Host smart-1e03281d-c4f0-47bd-883b-f62127778cba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248730399 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2248730399
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2553144421
Short name T178
Test name
Test status
Simulation time 222813239647 ps
CPU time 328.06 seconds
Started Jun 02 02:21:19 PM PDT 24
Finished Jun 02 02:26:47 PM PDT 24
Peak memory 191900 kb
Host smart-22310a96-a1fb-42af-9501-4c9da61b0c97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553144421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2553144421
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3098275526
Short name T110
Test name
Test status
Simulation time 624280919 ps
CPU time 0.73 seconds
Started Jun 02 02:22:09 PM PDT 24
Finished Jun 02 02:22:10 PM PDT 24
Peak memory 196456 kb
Host smart-47eb46d0-285c-4c5e-991c-b5124f272545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098275526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3098275526
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2830854881
Short name T35
Test name
Test status
Simulation time 88895140219 ps
CPU time 176.17 seconds
Started Jun 02 02:22:16 PM PDT 24
Finished Jun 02 02:25:13 PM PDT 24
Peak memory 206764 kb
Host smart-457a5839-72ba-410e-bbe1-b689ca1ddcb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830854881 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2830854881
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1162735203
Short name T23
Test name
Test status
Simulation time 56001001413 ps
CPU time 159.07 seconds
Started Jun 02 02:22:21 PM PDT 24
Finished Jun 02 02:25:00 PM PDT 24
Peak memory 206776 kb
Host smart-34f4ee2d-62d2-442a-bb78-c2e938cb2089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162735203 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1162735203
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3146297766
Short name T146
Test name
Test status
Simulation time 501011161 ps
CPU time 1.47 seconds
Started Jun 02 02:22:29 PM PDT 24
Finished Jun 02 02:22:31 PM PDT 24
Peak memory 196512 kb
Host smart-b62f3b2f-1f1c-40f4-ad2c-b1aa77fcaca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146297766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3146297766
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1700526672
Short name T32
Test name
Test status
Simulation time 561906874 ps
CPU time 1.16 seconds
Started Jun 02 02:22:37 PM PDT 24
Finished Jun 02 02:22:39 PM PDT 24
Peak memory 196480 kb
Host smart-f7574ef5-372d-488f-b685-9ccd34788f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700526672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1700526672
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2625615297
Short name T12
Test name
Test status
Simulation time 20767787786 ps
CPU time 163.17 seconds
Started Jun 02 02:22:44 PM PDT 24
Finished Jun 02 02:25:27 PM PDT 24
Peak memory 206780 kb
Host smart-2a039348-1c75-4f10-b2a7-2f7bc9f046c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625615297 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2625615297
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2420865960
Short name T177
Test name
Test status
Simulation time 52619393776 ps
CPU time 619.53 seconds
Started Jun 02 02:22:49 PM PDT 24
Finished Jun 02 02:33:09 PM PDT 24
Peak memory 202912 kb
Host smart-5aff902a-ca66-4b00-aaeb-91b3c1a376ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420865960 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2420865960
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1183310564
Short name T54
Test name
Test status
Simulation time 394077138 ps
CPU time 0.67 seconds
Started Jun 02 02:22:54 PM PDT 24
Finished Jun 02 02:22:56 PM PDT 24
Peak memory 196472 kb
Host smart-3adb7177-32db-4e22-901f-19b97c053531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183310564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1183310564
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1821328905
Short name T48
Test name
Test status
Simulation time 565077581 ps
CPU time 0.81 seconds
Started Jun 02 02:23:20 PM PDT 24
Finished Jun 02 02:23:21 PM PDT 24
Peak memory 196444 kb
Host smart-03619c92-2da4-4741-a2b3-272b878bce93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821328905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1821328905
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1053672262
Short name T138
Test name
Test status
Simulation time 474951601 ps
CPU time 1.29 seconds
Started Jun 02 02:23:49 PM PDT 24
Finished Jun 02 02:23:51 PM PDT 24
Peak memory 196436 kb
Host smart-694adabf-8b30-4001-8377-56f173d290b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053672262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1053672262
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2893241748
Short name T4
Test name
Test status
Simulation time 472667732 ps
CPU time 0.77 seconds
Started Jun 02 02:22:59 PM PDT 24
Finished Jun 02 02:23:00 PM PDT 24
Peak memory 196404 kb
Host smart-0f9a9458-75ea-442d-b94b-b6418236403d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893241748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2893241748
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3512619545
Short name T7
Test name
Test status
Simulation time 368832241 ps
CPU time 1.27 seconds
Started Jun 02 02:23:06 PM PDT 24
Finished Jun 02 02:23:07 PM PDT 24
Peak memory 196444 kb
Host smart-7d6dc642-d8f2-40f1-ad1f-541a996f0fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512619545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3512619545
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1109281911
Short name T153
Test name
Test status
Simulation time 274636072380 ps
CPU time 359.26 seconds
Started Jun 02 02:23:28 PM PDT 24
Finished Jun 02 02:29:28 PM PDT 24
Peak memory 192764 kb
Host smart-db3e1434-f17d-4bbf-809e-8a546cfae32b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109281911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1109281911
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1176984134
Short name T140
Test name
Test status
Simulation time 120425380675 ps
CPU time 157.51 seconds
Started Jun 02 02:23:45 PM PDT 24
Finished Jun 02 02:26:23 PM PDT 24
Peak memory 184032 kb
Host smart-80596333-6484-42fe-9180-d2530a10135f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176984134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1176984134
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1030689412
Short name T159
Test name
Test status
Simulation time 98811795639 ps
CPU time 139.21 seconds
Started Jun 02 02:22:03 PM PDT 24
Finished Jun 02 02:24:22 PM PDT 24
Peak memory 191872 kb
Host smart-340a6a2b-1c82-4348-8b7d-4b20684e2ed1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030689412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1030689412
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_jump.280912891
Short name T171
Test name
Test status
Simulation time 533488571 ps
CPU time 0.8 seconds
Started Jun 02 02:21:18 PM PDT 24
Finished Jun 02 02:21:19 PM PDT 24
Peak memory 196496 kb
Host smart-b755012b-d13c-4917-a9f5-397308d589f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280912891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.280912891
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2014478932
Short name T55
Test name
Test status
Simulation time 18875261282 ps
CPU time 7.72 seconds
Started Jun 02 02:22:02 PM PDT 24
Finished Jun 02 02:22:10 PM PDT 24
Peak memory 191896 kb
Host smart-b202c405-f5ad-4107-8ac1-abd05a239ea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014478932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2014478932
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3907696796
Short name T186
Test name
Test status
Simulation time 126938389136 ps
CPU time 13.95 seconds
Started Jun 02 02:22:42 PM PDT 24
Finished Jun 02 02:22:56 PM PDT 24
Peak memory 192316 kb
Host smart-90b923cf-d6fc-4678-af29-e9327d48ae28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907696796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3907696796
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3247325201
Short name T151
Test name
Test status
Simulation time 60042390866 ps
CPU time 6.29 seconds
Started Jun 02 02:23:00 PM PDT 24
Finished Jun 02 02:23:06 PM PDT 24
Peak memory 192112 kb
Host smart-ec10d83a-00c7-4d87-b49d-b60f6f08107a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247325201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3247325201
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2982530020
Short name T173
Test name
Test status
Simulation time 543885829 ps
CPU time 0.81 seconds
Started Jun 02 02:23:33 PM PDT 24
Finished Jun 02 02:23:34 PM PDT 24
Peak memory 196388 kb
Host smart-e9aa05f4-3cd0-4497-9d03-0c0fa7efc322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982530020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2982530020
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3678692041
Short name T183
Test name
Test status
Simulation time 266901399225 ps
CPU time 221.52 seconds
Started Jun 02 02:23:39 PM PDT 24
Finished Jun 02 02:27:21 PM PDT 24
Peak memory 184108 kb
Host smart-ddc5999d-03de-4bff-9a29-e0453d1a8276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678692041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3678692041
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1699017562
Short name T142
Test name
Test status
Simulation time 395712332 ps
CPU time 0.78 seconds
Started Jun 02 02:22:02 PM PDT 24
Finished Jun 02 02:22:03 PM PDT 24
Peak memory 196640 kb
Host smart-f5f6aac1-69e9-4c22-8d19-d2ec9415e5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699017562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1699017562
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2185864066
Short name T195
Test name
Test status
Simulation time 440163396 ps
CPU time 1.25 seconds
Started Jun 02 02:22:33 PM PDT 24
Finished Jun 02 02:22:34 PM PDT 24
Peak memory 196280 kb
Host smart-240fc330-0678-4fdf-982f-ad247a20a603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185864066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2185864066
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3298044449
Short name T189
Test name
Test status
Simulation time 585435548 ps
CPU time 0.8 seconds
Started Jun 02 02:22:29 PM PDT 24
Finished Jun 02 02:22:30 PM PDT 24
Peak memory 196372 kb
Host smart-4c701b67-efd1-420f-b6c4-b73888048421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298044449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3298044449
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3503498886
Short name T175
Test name
Test status
Simulation time 574325514 ps
CPU time 0.97 seconds
Started Jun 02 02:22:42 PM PDT 24
Finished Jun 02 02:22:43 PM PDT 24
Peak memory 196624 kb
Host smart-03039759-1fb6-47e8-a1a4-6a423674093f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503498886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3503498886
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3480112245
Short name T166
Test name
Test status
Simulation time 116894812619 ps
CPU time 89.02 seconds
Started Jun 02 02:22:42 PM PDT 24
Finished Jun 02 02:24:12 PM PDT 24
Peak memory 192928 kb
Host smart-ea136854-c930-44b7-8abd-d1ca24435658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480112245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3480112245
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2479431933
Short name T187
Test name
Test status
Simulation time 510100597 ps
CPU time 1.4 seconds
Started Jun 02 02:22:43 PM PDT 24
Finished Jun 02 02:22:45 PM PDT 24
Peak memory 196440 kb
Host smart-09193c09-1175-49f5-bc7d-08821ca7f5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479431933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2479431933
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1361927905
Short name T192
Test name
Test status
Simulation time 419860130 ps
CPU time 1.18 seconds
Started Jun 02 02:21:30 PM PDT 24
Finished Jun 02 02:21:32 PM PDT 24
Peak memory 196464 kb
Host smart-2deeae19-cff8-4813-aff2-71c10265e7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361927905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1361927905
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2940021089
Short name T191
Test name
Test status
Simulation time 430930653 ps
CPU time 1.21 seconds
Started Jun 02 02:23:11 PM PDT 24
Finished Jun 02 02:23:13 PM PDT 24
Peak memory 196360 kb
Host smart-78759cd5-da00-40cc-95b2-484097a364be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940021089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2940021089
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.643816754
Short name T156
Test name
Test status
Simulation time 131221905276 ps
CPU time 54.86 seconds
Started Jun 02 02:23:23 PM PDT 24
Finished Jun 02 02:24:18 PM PDT 24
Peak memory 192940 kb
Host smart-dce8d578-8b51-419f-b22b-cd6d6b3e8545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643816754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.643816754
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3726170715
Short name T181
Test name
Test status
Simulation time 507391732 ps
CPU time 0.83 seconds
Started Jun 02 02:23:26 PM PDT 24
Finished Jun 02 02:23:28 PM PDT 24
Peak memory 196484 kb
Host smart-6d3e20fb-79e5-4047-9532-6f9d00ae31f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726170715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3726170715
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.65883929
Short name T174
Test name
Test status
Simulation time 572156209 ps
CPU time 1.05 seconds
Started Jun 02 02:23:41 PM PDT 24
Finished Jun 02 02:23:42 PM PDT 24
Peak memory 196376 kb
Host smart-b0020687-7aa5-46e3-9fd3-9e5a036210ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65883929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.65883929
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1794404259
Short name T70
Test name
Test status
Simulation time 433033400 ps
CPU time 0.73 seconds
Started Jun 02 02:23:44 PM PDT 24
Finished Jun 02 02:23:45 PM PDT 24
Peak memory 196396 kb
Host smart-4c386fb0-dc5b-4ad5-9443-edfd5a40c388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794404259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1794404259
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1563771755
Short name T44
Test name
Test status
Simulation time 487846583 ps
CPU time 1.31 seconds
Started Jun 02 02:22:04 PM PDT 24
Finished Jun 02 02:22:05 PM PDT 24
Peak memory 196372 kb
Host smart-97230634-2c0c-4e8c-9bd8-a6a49862ce7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563771755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1563771755
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3516808507
Short name T317
Test name
Test status
Simulation time 8141697198 ps
CPU time 10.51 seconds
Started Jun 02 02:24:24 PM PDT 24
Finished Jun 02 02:24:35 PM PDT 24
Peak memory 198008 kb
Host smart-2b1eb6a7-4b94-4632-b957-73f0cb4eea6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516808507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3516808507
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3023220829
Short name T42
Test name
Test status
Simulation time 41198764064 ps
CPU time 169.11 seconds
Started Jun 02 02:22:04 PM PDT 24
Finished Jun 02 02:24:53 PM PDT 24
Peak memory 206812 kb
Host smart-01c88f6f-dd01-4892-9385-5f58478ce549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023220829 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3023220829
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2021392399
Short name T185
Test name
Test status
Simulation time 452516633 ps
CPU time 0.66 seconds
Started Jun 02 02:22:11 PM PDT 24
Finished Jun 02 02:22:12 PM PDT 24
Peak memory 196392 kb
Host smart-e0c355c3-db77-4044-9b49-a73d93cf3db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021392399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2021392399
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.24859898
Short name T188
Test name
Test status
Simulation time 32815313610 ps
CPU time 275.66 seconds
Started Jun 02 02:22:08 PM PDT 24
Finished Jun 02 02:26:44 PM PDT 24
Peak memory 206820 kb
Host smart-31bb621b-4d0e-4a3c-ab02-9039b59c1489
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24859898 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.24859898
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3362157591
Short name T161
Test name
Test status
Simulation time 345251906 ps
CPU time 0.98 seconds
Started Jun 02 02:22:16 PM PDT 24
Finished Jun 02 02:22:17 PM PDT 24
Peak memory 196388 kb
Host smart-f7d26817-907b-474a-94e0-09e8637623cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362157591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3362157591
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.410944601
Short name T179
Test name
Test status
Simulation time 435223161 ps
CPU time 0.72 seconds
Started Jun 02 02:22:16 PM PDT 24
Finished Jun 02 02:22:17 PM PDT 24
Peak memory 196468 kb
Host smart-cba90b58-1c70-4f77-910f-eb1f88fbfb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410944601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.410944601
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3579631776
Short name T21
Test name
Test status
Simulation time 452501021864 ps
CPU time 336.23 seconds
Started Jun 02 02:22:27 PM PDT 24
Finished Jun 02 02:28:04 PM PDT 24
Peak memory 191872 kb
Host smart-8a7b6a5e-d26a-4d07-b318-8c782072e7b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579631776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3579631776
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.4224230662
Short name T41
Test name
Test status
Simulation time 832718027786 ps
CPU time 512.21 seconds
Started Jun 02 02:22:28 PM PDT 24
Finished Jun 02 02:31:01 PM PDT 24
Peak memory 212312 kb
Host smart-bf753afd-f7db-433b-9f3c-064a761bffa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224230662 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.4224230662
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3127626902
Short name T168
Test name
Test status
Simulation time 467583550 ps
CPU time 0.74 seconds
Started Jun 02 02:21:23 PM PDT 24
Finished Jun 02 02:21:24 PM PDT 24
Peak memory 196352 kb
Host smart-b77e4383-f4e7-4688-a120-370d56b8693e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127626902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3127626902
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.916921229
Short name T167
Test name
Test status
Simulation time 229263568013 ps
CPU time 356.85 seconds
Started Jun 02 02:22:53 PM PDT 24
Finished Jun 02 02:28:51 PM PDT 24
Peak memory 192332 kb
Host smart-6c8219fb-28da-4608-843f-033868d29f53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916921229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.916921229
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.4175011638
Short name T194
Test name
Test status
Simulation time 499518197 ps
CPU time 0.99 seconds
Started Jun 02 02:23:02 PM PDT 24
Finished Jun 02 02:23:03 PM PDT 24
Peak memory 196460 kb
Host smart-849ba5a3-dd87-4b10-8972-4c9f9c6b62eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175011638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.4175011638
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2533823154
Short name T155
Test name
Test status
Simulation time 4683753998 ps
CPU time 2.51 seconds
Started Jun 02 02:23:10 PM PDT 24
Finished Jun 02 02:23:13 PM PDT 24
Peak memory 191884 kb
Host smart-073794bb-c83a-44ed-b844-f055fc8beb5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533823154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2533823154
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1986936417
Short name T197
Test name
Test status
Simulation time 492769939 ps
CPU time 0.94 seconds
Started Jun 02 02:21:36 PM PDT 24
Finished Jun 02 02:21:38 PM PDT 24
Peak memory 196348 kb
Host smart-b2d7cd59-2a78-432e-85f7-9d1628840c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986936417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1986936417
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4274123799
Short name T184
Test name
Test status
Simulation time 431519818 ps
CPU time 0.89 seconds
Started Jun 02 02:23:36 PM PDT 24
Finished Jun 02 02:23:37 PM PDT 24
Peak memory 196364 kb
Host smart-697b8f4a-d0f2-4b0f-ba80-ec0df229f118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274123799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4274123799
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2132704155
Short name T169
Test name
Test status
Simulation time 589356517 ps
CPU time 0.8 seconds
Started Jun 02 02:21:47 PM PDT 24
Finished Jun 02 02:21:49 PM PDT 24
Peak memory 196572 kb
Host smart-1697a31c-4fd0-42e3-8b35-a27aa113d2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132704155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2132704155
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.529296629
Short name T182
Test name
Test status
Simulation time 424916795 ps
CPU time 1.23 seconds
Started Jun 02 02:21:50 PM PDT 24
Finished Jun 02 02:21:51 PM PDT 24
Peak memory 196340 kb
Host smart-153c0d31-37a1-451b-ba6c-46edb30d0ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529296629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.529296629
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1834003892
Short name T47
Test name
Test status
Simulation time 501560818 ps
CPU time 1.41 seconds
Started Jun 02 02:21:50 PM PDT 24
Finished Jun 02 02:21:52 PM PDT 24
Peak memory 196456 kb
Host smart-919f608b-788d-439b-b10a-aee0b7b542e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834003892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1834003892
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.623694057
Short name T77
Test name
Test status
Simulation time 491127073 ps
CPU time 0.98 seconds
Started Jun 02 02:23:48 PM PDT 24
Finished Jun 02 02:23:49 PM PDT 24
Peak memory 194452 kb
Host smart-890cff7c-9eb2-469a-8de1-605893acd6c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623694057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.623694057
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2133480624
Short name T78
Test name
Test status
Simulation time 3193442767 ps
CPU time 4.74 seconds
Started Jun 02 02:23:49 PM PDT 24
Finished Jun 02 02:23:54 PM PDT 24
Peak memory 192048 kb
Host smart-1d335d87-f9a5-4841-afa3-db87cd6369c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133480624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2133480624
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2006249513
Short name T377
Test name
Test status
Simulation time 600387643 ps
CPU time 0.79 seconds
Started Jun 02 02:23:49 PM PDT 24
Finished Jun 02 02:23:50 PM PDT 24
Peak memory 183740 kb
Host smart-5a3f5025-1732-4979-a9f2-129d2ef1774f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006249513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2006249513
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2949846489
Short name T364
Test name
Test status
Simulation time 509833984 ps
CPU time 1.26 seconds
Started Jun 02 02:23:59 PM PDT 24
Finished Jun 02 02:24:00 PM PDT 24
Peak memory 195656 kb
Host smart-857422d4-7836-4f80-aed0-6b47f4c81cd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949846489 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2949846489
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1112588263
Short name T335
Test name
Test status
Simulation time 403630744 ps
CPU time 0.86 seconds
Started Jun 02 02:23:48 PM PDT 24
Finished Jun 02 02:23:49 PM PDT 24
Peak memory 183520 kb
Host smart-94862a31-3f6c-46b9-b4bb-602145565194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112588263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1112588263
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4008818380
Short name T363
Test name
Test status
Simulation time 423461548 ps
CPU time 0.55 seconds
Started Jun 02 02:23:50 PM PDT 24
Finished Jun 02 02:23:51 PM PDT 24
Peak memory 183492 kb
Host smart-6860dbea-627f-41df-9a3f-e5031611f816
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008818380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.4008818380
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1378691939
Short name T391
Test name
Test status
Simulation time 307977107 ps
CPU time 1.02 seconds
Started Jun 02 02:23:51 PM PDT 24
Finished Jun 02 02:23:53 PM PDT 24
Peak memory 183568 kb
Host smart-70a46ae5-0bb9-4296-a95e-c0dd3b88e3ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378691939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1378691939
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.785526357
Short name T345
Test name
Test status
Simulation time 971673312 ps
CPU time 1.28 seconds
Started Jun 02 02:23:55 PM PDT 24
Finished Jun 02 02:23:56 PM PDT 24
Peak memory 183964 kb
Host smart-9e8a98ce-14d6-42c9-92e0-bcc3abf7b920
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785526357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.785526357
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1516429394
Short name T305
Test name
Test status
Simulation time 537918145 ps
CPU time 3.02 seconds
Started Jun 02 02:23:48 PM PDT 24
Finished Jun 02 02:23:51 PM PDT 24
Peak memory 198392 kb
Host smart-5c0bc551-1a44-4ee7-b86f-33cf40984b42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516429394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1516429394
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2915256132
Short name T315
Test name
Test status
Simulation time 4749395550 ps
CPU time 1.39 seconds
Started Jun 02 02:23:49 PM PDT 24
Finished Jun 02 02:23:51 PM PDT 24
Peak memory 196700 kb
Host smart-2d656ed2-949b-4135-9637-8a08d54cb3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915256132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2915256132
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2286616799
Short name T66
Test name
Test status
Simulation time 523738856 ps
CPU time 0.88 seconds
Started Jun 02 02:24:02 PM PDT 24
Finished Jun 02 02:24:03 PM PDT 24
Peak memory 192976 kb
Host smart-5fb7776e-3858-4bbc-86a2-545443e47c0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286616799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2286616799
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2914433789
Short name T79
Test name
Test status
Simulation time 3013472907 ps
CPU time 7.51 seconds
Started Jun 02 02:23:55 PM PDT 24
Finished Jun 02 02:24:03 PM PDT 24
Peak memory 195644 kb
Host smart-b0a298fa-9cdc-42a0-9cf5-e7cf8d590370
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914433789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2914433789
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3982900711
Short name T357
Test name
Test status
Simulation time 917975478 ps
CPU time 2.01 seconds
Started Jun 02 02:23:52 PM PDT 24
Finished Jun 02 02:23:54 PM PDT 24
Peak memory 193100 kb
Host smart-804bd24e-20fe-43c7-a614-4dc414b55fc4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982900711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3982900711
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1446028653
Short name T204
Test name
Test status
Simulation time 421459958 ps
CPU time 0.88 seconds
Started Jun 02 02:24:02 PM PDT 24
Finished Jun 02 02:24:03 PM PDT 24
Peak memory 196072 kb
Host smart-23575875-f461-49af-8a6c-36059d25428b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446028653 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1446028653
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1581096263
Short name T381
Test name
Test status
Simulation time 370373276 ps
CPU time 0.83 seconds
Started Jun 02 02:23:54 PM PDT 24
Finished Jun 02 02:23:55 PM PDT 24
Peak memory 192924 kb
Host smart-5c211b6d-7d47-41c1-9dfb-62c1b53c251e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581096263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1581096263
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3447628561
Short name T339
Test name
Test status
Simulation time 343513651 ps
CPU time 0.68 seconds
Started Jun 02 02:23:53 PM PDT 24
Finished Jun 02 02:23:54 PM PDT 24
Peak memory 183576 kb
Host smart-38ac6f5f-9621-4b62-b7ae-d2dee6f8c5af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447628561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3447628561
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2566369621
Short name T299
Test name
Test status
Simulation time 315335850 ps
CPU time 0.74 seconds
Started Jun 02 02:23:54 PM PDT 24
Finished Jun 02 02:23:55 PM PDT 24
Peak memory 183488 kb
Host smart-2ac375ec-bbe7-4c07-bce9-efd9837280b2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566369621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2566369621
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4163597849
Short name T400
Test name
Test status
Simulation time 310229561 ps
CPU time 0.76 seconds
Started Jun 02 02:23:54 PM PDT 24
Finished Jun 02 02:23:55 PM PDT 24
Peak memory 183564 kb
Host smart-d2cafc3b-7aa5-4961-819e-4110f1e55cf4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163597849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.4163597849
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.357143043
Short name T370
Test name
Test status
Simulation time 2316524506 ps
CPU time 1.5 seconds
Started Jun 02 02:24:03 PM PDT 24
Finished Jun 02 02:24:05 PM PDT 24
Peak memory 193784 kb
Host smart-189b24f4-4ba8-4e8f-babb-825fe1df5b2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357143043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.357143043
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3050187972
Short name T323
Test name
Test status
Simulation time 370425883 ps
CPU time 1.81 seconds
Started Jun 02 02:23:54 PM PDT 24
Finished Jun 02 02:23:56 PM PDT 24
Peak memory 198340 kb
Host smart-0d89ceb1-78d1-4b40-8de3-fcffea401977
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050187972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3050187972
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2191163973
Short name T385
Test name
Test status
Simulation time 4321424065 ps
CPU time 2.38 seconds
Started Jun 02 02:23:54 PM PDT 24
Finished Jun 02 02:23:57 PM PDT 24
Peak memory 197660 kb
Host smart-4eb5c647-acdf-4ad2-9c27-07c84cbbcb3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191163973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2191163973
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1405895502
Short name T205
Test name
Test status
Simulation time 408419667 ps
CPU time 1.2 seconds
Started Jun 02 02:24:31 PM PDT 24
Finished Jun 02 02:24:32 PM PDT 24
Peak memory 195888 kb
Host smart-d6786f21-3233-473c-9500-ebaf36a2dd17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405895502 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1405895502
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1593164574
Short name T293
Test name
Test status
Simulation time 456422863 ps
CPU time 0.78 seconds
Started Jun 02 02:24:30 PM PDT 24
Finished Jun 02 02:24:32 PM PDT 24
Peak memory 192928 kb
Host smart-c4ae4530-b8a9-4e32-8254-56377ae5286a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593164574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1593164574
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1794313576
Short name T288
Test name
Test status
Simulation time 490928446 ps
CPU time 1.36 seconds
Started Jun 02 02:24:27 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 183564 kb
Host smart-34453a29-f222-4aa8-8b43-04b474a6f9dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794313576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1794313576
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1727669654
Short name T427
Test name
Test status
Simulation time 918046031 ps
CPU time 2.29 seconds
Started Jun 02 02:24:28 PM PDT 24
Finished Jun 02 02:24:31 PM PDT 24
Peak memory 193072 kb
Host smart-fe5979ca-98ff-427d-96b0-00801a9c3e2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727669654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1727669654
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4029204825
Short name T314
Test name
Test status
Simulation time 423121616 ps
CPU time 2.22 seconds
Started Jun 02 02:24:26 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 198376 kb
Host smart-e56064e1-7e10-45aa-adc8-5d778c4a90ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029204825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.4029204825
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.156894766
Short name T303
Test name
Test status
Simulation time 452453888 ps
CPU time 1.37 seconds
Started Jun 02 02:24:30 PM PDT 24
Finished Jun 02 02:24:32 PM PDT 24
Peak memory 196116 kb
Host smart-ead289a2-6476-46a1-b8da-50a482a4fa19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156894766 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.156894766
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.186655673
Short name T410
Test name
Test status
Simulation time 533254585 ps
CPU time 1.01 seconds
Started Jun 02 02:24:27 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 193292 kb
Host smart-fad55fd4-fe5d-495a-a269-49268072739f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186655673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.186655673
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.523305163
Short name T287
Test name
Test status
Simulation time 550617960 ps
CPU time 0.61 seconds
Started Jun 02 02:24:28 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 183516 kb
Host smart-5d9284da-ea93-4300-a165-fb62e06c5a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523305163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.523305163
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1488325053
Short name T407
Test name
Test status
Simulation time 2306322264 ps
CPU time 2.48 seconds
Started Jun 02 02:24:29 PM PDT 24
Finished Jun 02 02:24:32 PM PDT 24
Peak memory 193840 kb
Host smart-dc2eb0d2-e744-47e7-9cbe-8092443097bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488325053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1488325053
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.386639754
Short name T311
Test name
Test status
Simulation time 785141374 ps
CPU time 1.37 seconds
Started Jun 02 02:24:30 PM PDT 24
Finished Jun 02 02:24:32 PM PDT 24
Peak memory 198336 kb
Host smart-90dfe71b-0134-4a4b-b57e-381975f13379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386639754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.386639754
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3792596921
Short name T383
Test name
Test status
Simulation time 4533578914 ps
CPU time 2.5 seconds
Started Jun 02 02:24:28 PM PDT 24
Finished Jun 02 02:24:31 PM PDT 24
Peak memory 196592 kb
Host smart-9753dcae-66a3-4988-a84c-d52f86793ed7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792596921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3792596921
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1015362817
Short name T300
Test name
Test status
Simulation time 522706455 ps
CPU time 1.33 seconds
Started Jun 02 02:24:34 PM PDT 24
Finished Jun 02 02:24:36 PM PDT 24
Peak memory 195328 kb
Host smart-42529be7-6e5f-4dd1-a3f5-0e7feec32244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015362817 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1015362817
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1024294787
Short name T82
Test name
Test status
Simulation time 502218065 ps
CPU time 0.72 seconds
Started Jun 02 02:24:28 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 183652 kb
Host smart-a1dc24d6-40b4-408f-95cc-6de3b1bb0f72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024294787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1024294787
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2157357547
Short name T291
Test name
Test status
Simulation time 510651851 ps
CPU time 1.22 seconds
Started Jun 02 02:24:27 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 183512 kb
Host smart-ee0fb7db-388b-4fc0-84f0-662c7aa3d890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157357547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2157357547
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.100620758
Short name T356
Test name
Test status
Simulation time 2091798175 ps
CPU time 3.66 seconds
Started Jun 02 02:24:33 PM PDT 24
Finished Jun 02 02:24:37 PM PDT 24
Peak memory 194400 kb
Host smart-ef142bf0-5638-46bb-ba58-d2e268c51b52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100620758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.100620758
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3771568968
Short name T388
Test name
Test status
Simulation time 798045641 ps
CPU time 2.06 seconds
Started Jun 02 02:24:28 PM PDT 24
Finished Jun 02 02:24:30 PM PDT 24
Peak memory 198328 kb
Host smart-2822dc46-c95b-4b47-bdbd-3fae4ed3e3e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771568968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3771568968
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3119001537
Short name T306
Test name
Test status
Simulation time 8089730912 ps
CPU time 4 seconds
Started Jun 02 02:24:30 PM PDT 24
Finished Jun 02 02:24:34 PM PDT 24
Peak memory 197808 kb
Host smart-7da5faf7-fdae-4de4-a4d0-e1b0999bd4ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119001537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3119001537
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.784882685
Short name T378
Test name
Test status
Simulation time 462999735 ps
CPU time 0.91 seconds
Started Jun 02 02:24:33 PM PDT 24
Finished Jun 02 02:24:35 PM PDT 24
Peak memory 196040 kb
Host smart-50a4b9d7-96e1-493b-b193-ec62ba8adf7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784882685 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.784882685
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1311588704
Short name T81
Test name
Test status
Simulation time 391150311 ps
CPU time 0.71 seconds
Started Jun 02 02:24:33 PM PDT 24
Finished Jun 02 02:24:34 PM PDT 24
Peak memory 183672 kb
Host smart-230b6609-123d-42db-96a2-63d95ba27431
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311588704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1311588704
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1091107138
Short name T286
Test name
Test status
Simulation time 342273258 ps
CPU time 0.63 seconds
Started Jun 02 02:24:32 PM PDT 24
Finished Jun 02 02:24:34 PM PDT 24
Peak memory 183544 kb
Host smart-03bffbb8-9f82-439d-9973-90779057e1b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091107138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1091107138
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2575995543
Short name T338
Test name
Test status
Simulation time 1917252144 ps
CPU time 3.47 seconds
Started Jun 02 02:24:33 PM PDT 24
Finished Jun 02 02:24:37 PM PDT 24
Peak memory 194172 kb
Host smart-8e78b8a2-2f3e-419a-9954-816b7c7ad40e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575995543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2575995543
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.4172083826
Short name T418
Test name
Test status
Simulation time 522989073 ps
CPU time 3.17 seconds
Started Jun 02 02:24:33 PM PDT 24
Finished Jun 02 02:24:36 PM PDT 24
Peak memory 198280 kb
Host smart-6ac7679f-2d1c-44b4-85ea-3c9f781566d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172083826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.4172083826
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3444011633
Short name T308
Test name
Test status
Simulation time 4351978950 ps
CPU time 2.64 seconds
Started Jun 02 02:24:32 PM PDT 24
Finished Jun 02 02:24:36 PM PDT 24
Peak memory 197336 kb
Host smart-77460666-380f-4a15-8e85-780c415b8ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444011633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3444011633
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3843684816
Short name T347
Test name
Test status
Simulation time 509695358 ps
CPU time 0.95 seconds
Started Jun 02 02:24:40 PM PDT 24
Finished Jun 02 02:24:42 PM PDT 24
Peak memory 196232 kb
Host smart-5d44bd77-b27f-4795-96de-7dd857bcb5ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843684816 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3843684816
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4013651207
Short name T68
Test name
Test status
Simulation time 444073457 ps
CPU time 0.74 seconds
Started Jun 02 02:24:38 PM PDT 24
Finished Jun 02 02:24:39 PM PDT 24
Peak memory 192932 kb
Host smart-cdb4098e-7fa1-46f8-a218-14cfaef7bd49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013651207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.4013651207
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3806126067
Short name T331
Test name
Test status
Simulation time 405794413 ps
CPU time 0.63 seconds
Started Jun 02 02:24:37 PM PDT 24
Finished Jun 02 02:24:38 PM PDT 24
Peak memory 183540 kb
Host smart-cc43b26b-56dd-4245-9112-a670e4fed9a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806126067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3806126067
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2191776423
Short name T88
Test name
Test status
Simulation time 1045824830 ps
CPU time 1.09 seconds
Started Jun 02 02:24:44 PM PDT 24
Finished Jun 02 02:24:46 PM PDT 24
Peak memory 193316 kb
Host smart-c90a7611-c7ce-4185-93ad-6e0422a97413
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191776423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2191776423
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.880906788
Short name T362
Test name
Test status
Simulation time 426214788 ps
CPU time 1.47 seconds
Started Jun 02 02:24:34 PM PDT 24
Finished Jun 02 02:24:36 PM PDT 24
Peak memory 198292 kb
Host smart-a4322022-c8d5-4f93-91d7-09c4ca6c39c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880906788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.880906788
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1981405848
Short name T36
Test name
Test status
Simulation time 4492299418 ps
CPU time 6.8 seconds
Started Jun 02 02:24:34 PM PDT 24
Finished Jun 02 02:24:41 PM PDT 24
Peak memory 197468 kb
Host smart-1cc7fff6-0d64-4958-bed4-512cb7ffa393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981405848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1981405848
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.883423817
Short name T329
Test name
Test status
Simulation time 531577573 ps
CPU time 0.92 seconds
Started Jun 02 02:24:38 PM PDT 24
Finished Jun 02 02:24:39 PM PDT 24
Peak memory 196696 kb
Host smart-cceb6fb0-fdc9-4bf8-abc1-e944e31cd146
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883423817 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.883423817
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1145422807
Short name T397
Test name
Test status
Simulation time 493093561 ps
CPU time 1.34 seconds
Started Jun 02 02:24:43 PM PDT 24
Finished Jun 02 02:24:45 PM PDT 24
Peak memory 193828 kb
Host smart-4270d5f2-bf4a-4ecd-b6ef-3f66e02cd527
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145422807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1145422807
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1823622862
Short name T403
Test name
Test status
Simulation time 487409546 ps
CPU time 0.75 seconds
Started Jun 02 02:24:38 PM PDT 24
Finished Jun 02 02:24:39 PM PDT 24
Peak memory 183560 kb
Host smart-c43fdae7-2257-4ba3-88d6-ab350a05c52f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823622862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1823622862
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.168551857
Short name T89
Test name
Test status
Simulation time 2431400486 ps
CPU time 6.53 seconds
Started Jun 02 02:24:37 PM PDT 24
Finished Jun 02 02:24:44 PM PDT 24
Peak memory 194268 kb
Host smart-b6dc4a44-2eaf-4cc3-9d44-23dc01c60fe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168551857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.168551857
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1682406327
Short name T337
Test name
Test status
Simulation time 683262366 ps
CPU time 1.59 seconds
Started Jun 02 02:24:43 PM PDT 24
Finished Jun 02 02:24:45 PM PDT 24
Peak memory 198416 kb
Host smart-0c8e0d02-6eee-41d7-b51e-119866e7ad7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682406327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1682406327
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4236361312
Short name T348
Test name
Test status
Simulation time 8552528386 ps
CPU time 8.01 seconds
Started Jun 02 02:24:38 PM PDT 24
Finished Jun 02 02:24:47 PM PDT 24
Peak memory 197864 kb
Host smart-3e98167a-4f77-401b-a0a4-3e5f30596eca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236361312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.4236361312
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3359684968
Short name T415
Test name
Test status
Simulation time 491629209 ps
CPU time 1.11 seconds
Started Jun 02 02:24:40 PM PDT 24
Finished Jun 02 02:24:41 PM PDT 24
Peak memory 196424 kb
Host smart-e44a9306-5923-4734-91cf-2b3154843ae5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359684968 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3359684968
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.778379686
Short name T83
Test name
Test status
Simulation time 457637193 ps
CPU time 0.79 seconds
Started Jun 02 02:24:41 PM PDT 24
Finished Jun 02 02:24:42 PM PDT 24
Peak memory 193160 kb
Host smart-5747ba43-78a1-4e4c-80e8-8d1d17ed0c8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778379686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.778379686
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3316330766
Short name T425
Test name
Test status
Simulation time 403851047 ps
CPU time 1.18 seconds
Started Jun 02 02:24:37 PM PDT 24
Finished Jun 02 02:24:39 PM PDT 24
Peak memory 183524 kb
Host smart-a9558f3f-fe17-4677-95de-742988f4de77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316330766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3316330766
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.817216340
Short name T37
Test name
Test status
Simulation time 2690056618 ps
CPU time 4.6 seconds
Started Jun 02 02:24:43 PM PDT 24
Finished Jun 02 02:24:49 PM PDT 24
Peak memory 193856 kb
Host smart-86b68ed3-8b59-4839-bf2e-b3300be9e889
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817216340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.817216340
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2297555381
Short name T326
Test name
Test status
Simulation time 833378763 ps
CPU time 2.06 seconds
Started Jun 02 02:24:40 PM PDT 24
Finished Jun 02 02:24:42 PM PDT 24
Peak memory 198656 kb
Host smart-ba55ca0d-a9b7-4250-b774-44fa43d83265
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297555381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2297555381
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.534363960
Short name T409
Test name
Test status
Simulation time 4221720201 ps
CPU time 4.58 seconds
Started Jun 02 02:24:37 PM PDT 24
Finished Jun 02 02:24:43 PM PDT 24
Peak memory 197732 kb
Host smart-5c2c2a17-69a5-4ff8-936f-4768f75fdbf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534363960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.534363960
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1949180271
Short name T292
Test name
Test status
Simulation time 472600181 ps
CPU time 0.98 seconds
Started Jun 02 02:24:43 PM PDT 24
Finished Jun 02 02:24:44 PM PDT 24
Peak memory 195388 kb
Host smart-3ef726b9-28ec-4482-bad9-e8c6dfce3dd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949180271 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1949180271
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2989901372
Short name T67
Test name
Test status
Simulation time 314284530 ps
CPU time 0.8 seconds
Started Jun 02 02:24:42 PM PDT 24
Finished Jun 02 02:24:43 PM PDT 24
Peak memory 183700 kb
Host smart-35833506-2cf8-4d04-9f8d-fbcc780a8462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989901372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2989901372
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3994281987
Short name T379
Test name
Test status
Simulation time 499010599 ps
CPU time 0.86 seconds
Started Jun 02 02:24:45 PM PDT 24
Finished Jun 02 02:24:46 PM PDT 24
Peak memory 183532 kb
Host smart-a308f7aa-fe03-4aa8-944a-c8fcff533d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994281987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3994281987
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.865071558
Short name T316
Test name
Test status
Simulation time 1195681786 ps
CPU time 1.43 seconds
Started Jun 02 02:24:43 PM PDT 24
Finished Jun 02 02:24:45 PM PDT 24
Peak memory 192832 kb
Host smart-13726330-6c42-4bcb-b2f9-6f3672c33272
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865071558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.865071558
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3466532341
Short name T372
Test name
Test status
Simulation time 523573128 ps
CPU time 1.53 seconds
Started Jun 02 02:24:41 PM PDT 24
Finished Jun 02 02:24:44 PM PDT 24
Peak memory 198364 kb
Host smart-4d0a0333-b4eb-40fb-9208-88cc1aad1b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466532341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3466532341
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.169961652
Short name T405
Test name
Test status
Simulation time 7815784107 ps
CPU time 3.6 seconds
Started Jun 02 02:24:44 PM PDT 24
Finished Jun 02 02:24:48 PM PDT 24
Peak memory 197908 kb
Host smart-15615c42-3ddb-4744-943a-438b5aa177a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169961652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.169961652
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1537527142
Short name T304
Test name
Test status
Simulation time 315864763 ps
CPU time 1.11 seconds
Started Jun 02 02:24:43 PM PDT 24
Finished Jun 02 02:24:44 PM PDT 24
Peak memory 196092 kb
Host smart-900225b6-f0a9-4952-9bba-ab161ec8a459
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537527142 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1537527142
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2489836943
Short name T64
Test name
Test status
Simulation time 369944132 ps
CPU time 1.2 seconds
Started Jun 02 02:24:44 PM PDT 24
Finished Jun 02 02:24:46 PM PDT 24
Peak memory 193100 kb
Host smart-78961208-b081-4def-88f6-78c26a971594
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489836943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2489836943
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1854915811
Short name T333
Test name
Test status
Simulation time 414523756 ps
CPU time 0.69 seconds
Started Jun 02 02:24:49 PM PDT 24
Finished Jun 02 02:24:51 PM PDT 24
Peak memory 183524 kb
Host smart-df03d340-fc7f-4d0a-8a85-6bb6050d6a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854915811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1854915811
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2725074840
Short name T376
Test name
Test status
Simulation time 1756340914 ps
CPU time 1.21 seconds
Started Jun 02 02:24:42 PM PDT 24
Finished Jun 02 02:24:44 PM PDT 24
Peak memory 194296 kb
Host smart-2bf58e75-5c2e-4f2c-a842-5c464da79e25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725074840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2725074840
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1582773496
Short name T423
Test name
Test status
Simulation time 522863566 ps
CPU time 2.33 seconds
Started Jun 02 02:24:44 PM PDT 24
Finished Jun 02 02:24:47 PM PDT 24
Peak memory 198372 kb
Host smart-ca78d5a6-59aa-4e69-842f-339e00994b12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582773496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1582773496
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2462756134
Short name T341
Test name
Test status
Simulation time 4229156949 ps
CPU time 1.49 seconds
Started Jun 02 02:24:43 PM PDT 24
Finished Jun 02 02:24:46 PM PDT 24
Peak memory 196568 kb
Host smart-e3b9c16b-c376-4714-840a-71802ff84784
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462756134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2462756134
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1612916032
Short name T312
Test name
Test status
Simulation time 547664874 ps
CPU time 0.93 seconds
Started Jun 02 02:24:51 PM PDT 24
Finished Jun 02 02:24:52 PM PDT 24
Peak memory 198236 kb
Host smart-c2fca913-2992-4696-afe9-fa8d613ea40b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612916032 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1612916032
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4224787860
Short name T369
Test name
Test status
Simulation time 378213760 ps
CPU time 0.73 seconds
Started Jun 02 02:24:49 PM PDT 24
Finished Jun 02 02:24:50 PM PDT 24
Peak memory 192960 kb
Host smart-cc1a9897-e4af-444a-be4e-ff9e1558ec5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224787860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.4224787860
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3134519829
Short name T384
Test name
Test status
Simulation time 555717858 ps
CPU time 0.65 seconds
Started Jun 02 02:24:49 PM PDT 24
Finished Jun 02 02:24:50 PM PDT 24
Peak memory 183572 kb
Host smart-d0550eeb-a5da-488c-a6e6-926a0d19de35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134519829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3134519829
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.472531799
Short name T87
Test name
Test status
Simulation time 1365676397 ps
CPU time 3.31 seconds
Started Jun 02 02:24:49 PM PDT 24
Finished Jun 02 02:24:52 PM PDT 24
Peak memory 193252 kb
Host smart-c90ef1b7-737c-432f-9ed2-2f62ffe90f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472531799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.472531799
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.483591573
Short name T296
Test name
Test status
Simulation time 733200034 ps
CPU time 2.42 seconds
Started Jun 02 02:24:48 PM PDT 24
Finished Jun 02 02:24:51 PM PDT 24
Peak memory 198340 kb
Host smart-59c6f246-d798-4c3f-85e8-8b99be8d40e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483591573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.483591573
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3907693840
Short name T198
Test name
Test status
Simulation time 4105655909 ps
CPU time 5.97 seconds
Started Jun 02 02:24:50 PM PDT 24
Finished Jun 02 02:24:56 PM PDT 24
Peak memory 197596 kb
Host smart-bc447f80-9d23-4ffd-bfbf-5a3ba6410eaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907693840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3907693840
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2912076059
Short name T63
Test name
Test status
Simulation time 437797269 ps
CPU time 1.38 seconds
Started Jun 02 02:24:04 PM PDT 24
Finished Jun 02 02:24:05 PM PDT 24
Peak memory 193064 kb
Host smart-be6eb6ed-08f9-4d36-9bd2-245a8785f475
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912076059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2912076059
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3719523750
Short name T206
Test name
Test status
Simulation time 7240089367 ps
CPU time 2 seconds
Started Jun 02 02:24:04 PM PDT 24
Finished Jun 02 02:24:06 PM PDT 24
Peak memory 192192 kb
Host smart-dc03a9e9-752e-4c92-a6b9-b4a21559cb91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719523750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3719523750
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3003476251
Short name T420
Test name
Test status
Simulation time 739723627 ps
CPU time 0.88 seconds
Started Jun 02 02:24:02 PM PDT 24
Finished Jun 02 02:24:03 PM PDT 24
Peak memory 183688 kb
Host smart-e782b24b-8557-44f9-92f6-617ab24000a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003476251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3003476251
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1652971150
Short name T290
Test name
Test status
Simulation time 513866200 ps
CPU time 1.41 seconds
Started Jun 02 02:24:04 PM PDT 24
Finished Jun 02 02:24:06 PM PDT 24
Peak memory 194940 kb
Host smart-2384e7b2-cdf8-486d-8c16-29b6f089e692
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652971150 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1652971150
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.765454783
Short name T297
Test name
Test status
Simulation time 494928603 ps
CPU time 0.62 seconds
Started Jun 02 02:23:58 PM PDT 24
Finished Jun 02 02:23:59 PM PDT 24
Peak memory 183732 kb
Host smart-fed43cd7-2aa5-4b59-a93e-02bb10d70244
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765454783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.765454783
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3626574708
Short name T392
Test name
Test status
Simulation time 472155396 ps
CPU time 0.71 seconds
Started Jun 02 02:23:58 PM PDT 24
Finished Jun 02 02:23:59 PM PDT 24
Peak memory 183588 kb
Host smart-d1b7e4d0-d134-4f06-95ff-cc4ba6491c4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626574708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3626574708
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2157055897
Short name T319
Test name
Test status
Simulation time 368128450 ps
CPU time 0.82 seconds
Started Jun 02 02:24:00 PM PDT 24
Finished Jun 02 02:24:01 PM PDT 24
Peak memory 183500 kb
Host smart-7ab81ecd-4379-40cb-87f3-5d9f0ef73196
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157055897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2157055897
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1132862723
Short name T289
Test name
Test status
Simulation time 474882455 ps
CPU time 1.24 seconds
Started Jun 02 02:23:59 PM PDT 24
Finished Jun 02 02:24:01 PM PDT 24
Peak memory 183520 kb
Host smart-55225054-ebd3-491b-8699-c3d9da5631a2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132862723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1132862723
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2469554966
Short name T344
Test name
Test status
Simulation time 2141417824 ps
CPU time 1.44 seconds
Started Jun 02 02:24:04 PM PDT 24
Finished Jun 02 02:24:06 PM PDT 24
Peak memory 191848 kb
Host smart-3df57300-5043-4f1f-8977-05eed8dc8377
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469554966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2469554966
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.670879272
Short name T294
Test name
Test status
Simulation time 596675391 ps
CPU time 1.58 seconds
Started Jun 02 02:24:03 PM PDT 24
Finished Jun 02 02:24:05 PM PDT 24
Peak memory 198360 kb
Host smart-e8071a35-79f5-48d2-9c92-009a53250c28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670879272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.670879272
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2724060945
Short name T39
Test name
Test status
Simulation time 7775876297 ps
CPU time 3.86 seconds
Started Jun 02 02:24:03 PM PDT 24
Finished Jun 02 02:24:07 PM PDT 24
Peak memory 197888 kb
Host smart-be18124a-f5f5-439c-90cf-cbccc1f60f06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724060945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2724060945
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3669091649
Short name T394
Test name
Test status
Simulation time 475883479 ps
CPU time 1.31 seconds
Started Jun 02 02:24:49 PM PDT 24
Finished Jun 02 02:24:51 PM PDT 24
Peak memory 183772 kb
Host smart-bc6b50cc-aed0-4b25-b5ea-a832998bd0e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669091649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3669091649
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2313256280
Short name T395
Test name
Test status
Simulation time 463532636 ps
CPU time 0.72 seconds
Started Jun 02 02:24:49 PM PDT 24
Finished Jun 02 02:24:50 PM PDT 24
Peak memory 183568 kb
Host smart-f08f89f3-3c02-4a79-a788-fa650c443a15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313256280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2313256280
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.951746982
Short name T414
Test name
Test status
Simulation time 307205425 ps
CPU time 1 seconds
Started Jun 02 02:24:47 PM PDT 24
Finished Jun 02 02:24:49 PM PDT 24
Peak memory 183544 kb
Host smart-154c0aca-6026-47a6-8132-9cb4a99227c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951746982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.951746982
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.827856888
Short name T301
Test name
Test status
Simulation time 286917701 ps
CPU time 0.97 seconds
Started Jun 02 02:24:49 PM PDT 24
Finished Jun 02 02:24:50 PM PDT 24
Peak memory 183524 kb
Host smart-de3fab13-17d0-4c4f-91c4-c50ff4a7ba75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827856888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.827856888
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2919458995
Short name T419
Test name
Test status
Simulation time 432733446 ps
CPU time 0.7 seconds
Started Jun 02 02:24:48 PM PDT 24
Finished Jun 02 02:24:49 PM PDT 24
Peak memory 183576 kb
Host smart-bacff059-3018-4d83-b522-4aaebdb08f1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919458995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2919458995
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.858188427
Short name T398
Test name
Test status
Simulation time 437744128 ps
CPU time 0.69 seconds
Started Jun 02 02:24:51 PM PDT 24
Finished Jun 02 02:24:52 PM PDT 24
Peak memory 183532 kb
Host smart-d1e3c4c8-0d1c-4af5-8d13-b3c866214a5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858188427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.858188427
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2193541445
Short name T411
Test name
Test status
Simulation time 512839636 ps
CPU time 1.35 seconds
Started Jun 02 02:24:49 PM PDT 24
Finished Jun 02 02:24:51 PM PDT 24
Peak memory 183564 kb
Host smart-58cc90bd-f74c-4597-95e0-aac427ea841a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193541445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2193541445
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2070418276
Short name T382
Test name
Test status
Simulation time 389752901 ps
CPU time 0.84 seconds
Started Jun 02 02:24:52 PM PDT 24
Finished Jun 02 02:24:53 PM PDT 24
Peak memory 183532 kb
Host smart-f1f2d00f-2d7d-4695-994d-be9866b8c694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070418276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2070418276
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.605627595
Short name T365
Test name
Test status
Simulation time 449773852 ps
CPU time 1.19 seconds
Started Jun 02 02:24:48 PM PDT 24
Finished Jun 02 02:24:50 PM PDT 24
Peak memory 183540 kb
Host smart-c75ef725-be0a-4c73-8b9b-9f1ba00eb48b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605627595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.605627595
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2946898415
Short name T353
Test name
Test status
Simulation time 358996981 ps
CPU time 0.66 seconds
Started Jun 02 02:24:51 PM PDT 24
Finished Jun 02 02:24:52 PM PDT 24
Peak memory 183568 kb
Host smart-412cc12f-5903-42c2-b95a-92153a0ea2cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946898415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2946898415
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3440348983
Short name T69
Test name
Test status
Simulation time 536568669 ps
CPU time 1.01 seconds
Started Jun 02 02:24:09 PM PDT 24
Finished Jun 02 02:24:10 PM PDT 24
Peak memory 183624 kb
Host smart-68f6006e-b826-4d07-bf7a-92868a71a481
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440348983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3440348983
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1140223648
Short name T342
Test name
Test status
Simulation time 7102618311 ps
CPU time 8.74 seconds
Started Jun 02 02:24:10 PM PDT 24
Finished Jun 02 02:24:19 PM PDT 24
Peak memory 192060 kb
Host smart-bdd292d1-d169-463f-9e9e-bebda0b25ba1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140223648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1140223648
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.538588615
Short name T404
Test name
Test status
Simulation time 863060017 ps
CPU time 0.71 seconds
Started Jun 02 02:24:09 PM PDT 24
Finished Jun 02 02:24:10 PM PDT 24
Peak memory 183604 kb
Host smart-71362474-3734-4996-a767-9224502410f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538588615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.538588615
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4220954717
Short name T322
Test name
Test status
Simulation time 379984431 ps
CPU time 1.23 seconds
Started Jun 02 02:24:10 PM PDT 24
Finished Jun 02 02:24:12 PM PDT 24
Peak memory 196240 kb
Host smart-be0327eb-336b-4eec-92e5-37b1c270066e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220954717 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.4220954717
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.569169484
Short name T393
Test name
Test status
Simulation time 349286933 ps
CPU time 1.06 seconds
Started Jun 02 02:24:10 PM PDT 24
Finished Jun 02 02:24:12 PM PDT 24
Peak memory 192880 kb
Host smart-2b89204a-2b98-4384-8fb1-128b90d75657
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569169484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.569169484
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3471646168
Short name T413
Test name
Test status
Simulation time 520899695 ps
CPU time 0.71 seconds
Started Jun 02 02:24:09 PM PDT 24
Finished Jun 02 02:24:10 PM PDT 24
Peak memory 183536 kb
Host smart-09b3cd4c-783a-4969-b991-bcf7c359ba22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471646168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3471646168
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.934741877
Short name T361
Test name
Test status
Simulation time 341890290 ps
CPU time 0.61 seconds
Started Jun 02 02:24:10 PM PDT 24
Finished Jun 02 02:24:11 PM PDT 24
Peak memory 183436 kb
Host smart-9e2dd8d1-40f6-46c5-af58-231355361a04
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934741877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.934741877
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2178042932
Short name T380
Test name
Test status
Simulation time 521891368 ps
CPU time 0.97 seconds
Started Jun 02 02:24:09 PM PDT 24
Finished Jun 02 02:24:10 PM PDT 24
Peak memory 183576 kb
Host smart-ef1fc357-b5ff-4e25-9738-3c9585c54d45
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178042932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2178042932
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3585175748
Short name T360
Test name
Test status
Simulation time 2250086768 ps
CPU time 1.44 seconds
Started Jun 02 02:24:09 PM PDT 24
Finished Jun 02 02:24:11 PM PDT 24
Peak memory 194256 kb
Host smart-cc8c622b-1283-4bda-b796-e9eb3b3da485
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585175748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3585175748
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3835718837
Short name T389
Test name
Test status
Simulation time 590783148 ps
CPU time 1.24 seconds
Started Jun 02 02:24:03 PM PDT 24
Finished Jun 02 02:24:05 PM PDT 24
Peak memory 198224 kb
Host smart-402230e3-a656-4787-9737-8b186ed4ed86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835718837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3835718837
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1843904894
Short name T200
Test name
Test status
Simulation time 8374327920 ps
CPU time 3.66 seconds
Started Jun 02 02:24:10 PM PDT 24
Finished Jun 02 02:24:14 PM PDT 24
Peak memory 197984 kb
Host smart-a3c10037-b564-46f6-8aa4-c5fb1bada218
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843904894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1843904894
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1332083220
Short name T302
Test name
Test status
Simulation time 472076468 ps
CPU time 1.21 seconds
Started Jun 02 02:24:48 PM PDT 24
Finished Jun 02 02:24:50 PM PDT 24
Peak memory 183508 kb
Host smart-0067fd5e-90d2-4980-9ed3-f7d20907e6f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332083220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1332083220
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2099328463
Short name T417
Test name
Test status
Simulation time 345153158 ps
CPU time 0.76 seconds
Started Jun 02 02:24:50 PM PDT 24
Finished Jun 02 02:24:51 PM PDT 24
Peak memory 183520 kb
Host smart-e2e45adb-f752-4d09-9b24-f2cb2e616eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099328463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2099328463
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3606361251
Short name T426
Test name
Test status
Simulation time 283735212 ps
CPU time 0.95 seconds
Started Jun 02 02:24:53 PM PDT 24
Finished Jun 02 02:24:54 PM PDT 24
Peak memory 183520 kb
Host smart-fdb276fa-730b-4759-a3ef-8dd80993081a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606361251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3606361251
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2494748381
Short name T343
Test name
Test status
Simulation time 363320653 ps
CPU time 1.14 seconds
Started Jun 02 02:24:54 PM PDT 24
Finished Jun 02 02:24:55 PM PDT 24
Peak memory 183568 kb
Host smart-f2b5d459-47c3-4154-a923-bd41cb9570a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494748381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2494748381
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1990943692
Short name T402
Test name
Test status
Simulation time 433747173 ps
CPU time 0.86 seconds
Started Jun 02 02:24:53 PM PDT 24
Finished Jun 02 02:24:54 PM PDT 24
Peak memory 183572 kb
Host smart-8b33ce31-34f3-496b-9a78-0670f1bbd24d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990943692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1990943692
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1771475075
Short name T390
Test name
Test status
Simulation time 439245327 ps
CPU time 1.27 seconds
Started Jun 02 02:24:55 PM PDT 24
Finished Jun 02 02:24:57 PM PDT 24
Peak memory 182588 kb
Host smart-7f9bdcf7-7dfb-427c-8fee-681f8221cbae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771475075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1771475075
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2006169036
Short name T373
Test name
Test status
Simulation time 394515420 ps
CPU time 1.15 seconds
Started Jun 02 02:24:53 PM PDT 24
Finished Jun 02 02:24:55 PM PDT 24
Peak memory 183556 kb
Host smart-d887e1ee-18f5-4665-b960-416d6894b20a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006169036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2006169036
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2900176357
Short name T295
Test name
Test status
Simulation time 566859468 ps
CPU time 0.6 seconds
Started Jun 02 02:24:53 PM PDT 24
Finished Jun 02 02:24:54 PM PDT 24
Peak memory 183500 kb
Host smart-630dfc7e-4353-4a14-80ef-bf5d09bae411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900176357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2900176357
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3014010739
Short name T399
Test name
Test status
Simulation time 309369768 ps
CPU time 0.64 seconds
Started Jun 02 02:24:55 PM PDT 24
Finished Jun 02 02:24:56 PM PDT 24
Peak memory 183532 kb
Host smart-a65fc824-e4ae-453e-ab9a-3d032e24995a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014010739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3014010739
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2794293050
Short name T309
Test name
Test status
Simulation time 355336844 ps
CPU time 0.85 seconds
Started Jun 02 02:24:55 PM PDT 24
Finished Jun 02 02:24:56 PM PDT 24
Peak memory 183516 kb
Host smart-dcfdd38a-e7ce-4aeb-a065-b23a259e31b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794293050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2794293050
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2050956358
Short name T386
Test name
Test status
Simulation time 491655848 ps
CPU time 1.53 seconds
Started Jun 02 02:24:13 PM PDT 24
Finished Jun 02 02:24:15 PM PDT 24
Peak memory 194164 kb
Host smart-c221628b-b448-4f69-9084-65d385834e7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050956358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2050956358
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.383027097
Short name T350
Test name
Test status
Simulation time 6874225134 ps
CPU time 8.57 seconds
Started Jun 02 02:24:15 PM PDT 24
Finished Jun 02 02:24:24 PM PDT 24
Peak memory 192068 kb
Host smart-9b3710c1-c1a5-486a-9fb5-570eab5e0c46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383027097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.383027097
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1463243266
Short name T62
Test name
Test status
Simulation time 756804393 ps
CPU time 1.01 seconds
Started Jun 02 02:24:13 PM PDT 24
Finished Jun 02 02:24:15 PM PDT 24
Peak memory 191884 kb
Host smart-2281c9aa-1749-40be-b394-48679f2e07d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463243266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1463243266
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2536626302
Short name T421
Test name
Test status
Simulation time 511561495 ps
CPU time 1.39 seconds
Started Jun 02 02:24:13 PM PDT 24
Finished Jun 02 02:24:15 PM PDT 24
Peak memory 195836 kb
Host smart-4a1bd1c5-13f8-4c55-98f5-a0852120d385
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536626302 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2536626302
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3394510726
Short name T80
Test name
Test status
Simulation time 525373587 ps
CPU time 1.02 seconds
Started Jun 02 02:24:14 PM PDT 24
Finished Jun 02 02:24:16 PM PDT 24
Peak memory 192844 kb
Host smart-ad9bca93-297a-4107-9a59-6a5c79e6da80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394510726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3394510726
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.531336819
Short name T406
Test name
Test status
Simulation time 449120997 ps
CPU time 0.68 seconds
Started Jun 02 02:24:13 PM PDT 24
Finished Jun 02 02:24:13 PM PDT 24
Peak memory 183560 kb
Host smart-a71ebe80-a4d0-4957-8cdb-057727c353bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531336819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.531336819
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2732501265
Short name T396
Test name
Test status
Simulation time 355929756 ps
CPU time 1.06 seconds
Started Jun 02 02:24:17 PM PDT 24
Finished Jun 02 02:24:19 PM PDT 24
Peak memory 183392 kb
Host smart-9b82ce21-3cd8-4d92-82ef-3821f27b550f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732501265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2732501265
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2850787347
Short name T330
Test name
Test status
Simulation time 513704998 ps
CPU time 0.94 seconds
Started Jun 02 02:24:15 PM PDT 24
Finished Jun 02 02:24:16 PM PDT 24
Peak memory 183536 kb
Host smart-7eda3588-a3f9-435e-9898-c5a5d49c4a20
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850787347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2850787347
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.102920772
Short name T352
Test name
Test status
Simulation time 2432674147 ps
CPU time 1.32 seconds
Started Jun 02 02:24:15 PM PDT 24
Finished Jun 02 02:24:17 PM PDT 24
Peak memory 183740 kb
Host smart-2d96e6ba-1c45-4d00-9f96-bf118125e77d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102920772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.102920772
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3066179221
Short name T401
Test name
Test status
Simulation time 483452322 ps
CPU time 2.37 seconds
Started Jun 02 02:24:10 PM PDT 24
Finished Jun 02 02:24:13 PM PDT 24
Peak memory 198356 kb
Host smart-5b0dba47-12d0-4c10-bc9a-1766754eae52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066179221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3066179221
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2325100334
Short name T340
Test name
Test status
Simulation time 3910022514 ps
CPU time 6.71 seconds
Started Jun 02 02:24:08 PM PDT 24
Finished Jun 02 02:24:15 PM PDT 24
Peak memory 197408 kb
Host smart-1838a3fb-2014-4582-a4a1-871b992d9834
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325100334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2325100334
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.164813365
Short name T324
Test name
Test status
Simulation time 364818681 ps
CPU time 0.66 seconds
Started Jun 02 02:24:55 PM PDT 24
Finished Jun 02 02:24:56 PM PDT 24
Peak memory 182632 kb
Host smart-43145fe9-584c-41cc-b6fd-ecf3e166afea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164813365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.164813365
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2359310840
Short name T355
Test name
Test status
Simulation time 421560283 ps
CPU time 0.59 seconds
Started Jun 02 02:24:54 PM PDT 24
Finished Jun 02 02:24:55 PM PDT 24
Peak memory 183528 kb
Host smart-ff813c7a-5c28-4d18-81ef-fed6c3c8921e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359310840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2359310840
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.30712692
Short name T374
Test name
Test status
Simulation time 317620877 ps
CPU time 0.66 seconds
Started Jun 02 02:24:54 PM PDT 24
Finished Jun 02 02:24:54 PM PDT 24
Peak memory 183824 kb
Host smart-260bc44c-88e5-483e-9202-8ae007f7ee4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30712692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.30712692
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.161553271
Short name T366
Test name
Test status
Simulation time 322423421 ps
CPU time 0.72 seconds
Started Jun 02 02:24:53 PM PDT 24
Finished Jun 02 02:24:54 PM PDT 24
Peak memory 183552 kb
Host smart-7277862e-a38a-4528-9f81-5c893dfacf55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161553271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.161553271
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.568140553
Short name T336
Test name
Test status
Simulation time 362086217 ps
CPU time 1.12 seconds
Started Jun 02 02:24:53 PM PDT 24
Finished Jun 02 02:24:54 PM PDT 24
Peak memory 183576 kb
Host smart-d690bb4d-541b-4b97-b763-f36ec866da37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568140553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.568140553
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3407134572
Short name T368
Test name
Test status
Simulation time 483919707 ps
CPU time 0.74 seconds
Started Jun 02 02:24:54 PM PDT 24
Finished Jun 02 02:24:55 PM PDT 24
Peak memory 183560 kb
Host smart-b4f3b514-9585-4669-92ac-2f053ce812b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407134572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3407134572
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3281432401
Short name T351
Test name
Test status
Simulation time 441052079 ps
CPU time 0.83 seconds
Started Jun 02 02:24:53 PM PDT 24
Finished Jun 02 02:24:54 PM PDT 24
Peak memory 183500 kb
Host smart-0a4c5b51-9f1a-4b1f-967a-9e6c72285074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281432401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3281432401
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2221638875
Short name T310
Test name
Test status
Simulation time 414639447 ps
CPU time 1.21 seconds
Started Jun 02 02:24:55 PM PDT 24
Finished Jun 02 02:24:56 PM PDT 24
Peak memory 183568 kb
Host smart-7a7ba065-8566-46e7-b458-9181afd3e382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221638875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2221638875
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2040568350
Short name T298
Test name
Test status
Simulation time 365432456 ps
CPU time 1.06 seconds
Started Jun 02 02:24:54 PM PDT 24
Finished Jun 02 02:24:56 PM PDT 24
Peak memory 183520 kb
Host smart-62efdaa0-0e51-419d-bfb9-a832bb36d6e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040568350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2040568350
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.917502043
Short name T424
Test name
Test status
Simulation time 307037021 ps
CPU time 0.65 seconds
Started Jun 02 02:24:58 PM PDT 24
Finished Jun 02 02:24:59 PM PDT 24
Peak memory 183516 kb
Host smart-ba49b0c0-1b18-423a-bfe1-037fe7dc63c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917502043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.917502043
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3809722127
Short name T375
Test name
Test status
Simulation time 505672997 ps
CPU time 0.69 seconds
Started Jun 02 02:24:19 PM PDT 24
Finished Jun 02 02:24:20 PM PDT 24
Peak memory 195832 kb
Host smart-aa871f12-256f-42da-a537-107f93bb472b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809722127 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3809722127
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2851220546
Short name T346
Test name
Test status
Simulation time 452508227 ps
CPU time 0.76 seconds
Started Jun 02 02:24:15 PM PDT 24
Finished Jun 02 02:24:16 PM PDT 24
Peak memory 192976 kb
Host smart-c04a7dee-4605-43dd-a854-4176d5358357
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851220546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2851220546
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1909297091
Short name T328
Test name
Test status
Simulation time 426839386 ps
CPU time 0.86 seconds
Started Jun 02 02:24:12 PM PDT 24
Finished Jun 02 02:24:13 PM PDT 24
Peak memory 183824 kb
Host smart-5b4f1dc3-a111-4714-ae48-fd09b4c2b4e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909297091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1909297091
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1924662798
Short name T321
Test name
Test status
Simulation time 1312136631 ps
CPU time 1.7 seconds
Started Jun 02 02:24:16 PM PDT 24
Finished Jun 02 02:24:18 PM PDT 24
Peak memory 192808 kb
Host smart-15d0cca5-026b-4bcd-b223-d4f3054642d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924662798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1924662798
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1215741425
Short name T354
Test name
Test status
Simulation time 479158884 ps
CPU time 1.35 seconds
Started Jun 02 02:24:13 PM PDT 24
Finished Jun 02 02:24:14 PM PDT 24
Peak memory 198364 kb
Host smart-cc8849d0-3f13-4433-9c02-894e392c050a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215741425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1215741425
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1000711949
Short name T358
Test name
Test status
Simulation time 8175233480 ps
CPU time 3.86 seconds
Started Jun 02 02:24:18 PM PDT 24
Finished Jun 02 02:24:22 PM PDT 24
Peak memory 197792 kb
Host smart-63754fce-7caa-4340-9253-94afa9ef7b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000711949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1000711949
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2752459240
Short name T332
Test name
Test status
Simulation time 582264454 ps
CPU time 1.11 seconds
Started Jun 02 02:24:19 PM PDT 24
Finished Jun 02 02:24:20 PM PDT 24
Peak memory 196448 kb
Host smart-95559034-c3ac-4e63-97d6-307a49d5cce9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752459240 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2752459240
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.157033541
Short name T307
Test name
Test status
Simulation time 320421328 ps
CPU time 0.66 seconds
Started Jun 02 02:24:25 PM PDT 24
Finished Jun 02 02:24:26 PM PDT 24
Peak memory 192876 kb
Host smart-d46f978a-7cc1-434f-b51b-c7b5d536dc0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157033541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.157033541
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2052316249
Short name T387
Test name
Test status
Simulation time 495444788 ps
CPU time 0.74 seconds
Started Jun 02 02:24:22 PM PDT 24
Finished Jun 02 02:24:23 PM PDT 24
Peak memory 183576 kb
Host smart-4627bc23-1651-4ca5-a8f2-179688533b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052316249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2052316249
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2088012698
Short name T84
Test name
Test status
Simulation time 1168454442 ps
CPU time 1.01 seconds
Started Jun 02 02:24:19 PM PDT 24
Finished Jun 02 02:24:20 PM PDT 24
Peak memory 192804 kb
Host smart-175f3695-9de7-451c-91e1-ed42dc5b90de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088012698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2088012698
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3628828920
Short name T359
Test name
Test status
Simulation time 482009952 ps
CPU time 1.17 seconds
Started Jun 02 02:24:19 PM PDT 24
Finished Jun 02 02:24:21 PM PDT 24
Peak memory 198072 kb
Host smart-be910dfc-2813-463e-b72e-f39b74a635c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628828920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3628828920
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1984597231
Short name T325
Test name
Test status
Simulation time 368867383 ps
CPU time 0.84 seconds
Started Jun 02 02:24:27 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 195712 kb
Host smart-388ad627-7984-43ed-b29a-ffe913afb953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984597231 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1984597231
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.662979179
Short name T367
Test name
Test status
Simulation time 545090904 ps
CPU time 1.46 seconds
Started Jun 02 02:24:25 PM PDT 24
Finished Jun 02 02:24:26 PM PDT 24
Peak memory 192576 kb
Host smart-04bc7c91-58dc-4aba-b96a-1b879b6a8eb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662979179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.662979179
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.993612182
Short name T416
Test name
Test status
Simulation time 316864975 ps
CPU time 0.98 seconds
Started Jun 02 02:24:25 PM PDT 24
Finished Jun 02 02:24:26 PM PDT 24
Peak memory 183364 kb
Host smart-4c143213-9403-402c-9ce6-316eec463619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993612182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.993612182
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4233167645
Short name T86
Test name
Test status
Simulation time 1181561107 ps
CPU time 2.17 seconds
Started Jun 02 02:24:24 PM PDT 24
Finished Jun 02 02:24:26 PM PDT 24
Peak memory 193596 kb
Host smart-ec6b434b-57ff-431c-9376-f38e696ba9e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233167645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.4233167645
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1962077851
Short name T313
Test name
Test status
Simulation time 436125918 ps
CPU time 3.05 seconds
Started Jun 02 02:24:18 PM PDT 24
Finished Jun 02 02:24:22 PM PDT 24
Peak memory 198344 kb
Host smart-a6a60eec-89d3-442e-912e-46f96b309b67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962077851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1962077851
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3196075078
Short name T199
Test name
Test status
Simulation time 4847867234 ps
CPU time 2.22 seconds
Started Jun 02 02:24:18 PM PDT 24
Finished Jun 02 02:24:21 PM PDT 24
Peak memory 197616 kb
Host smart-b0f6a6ac-b54e-452b-9961-31b8c1a5a680
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196075078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3196075078
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1841390336
Short name T320
Test name
Test status
Simulation time 530577049 ps
CPU time 0.92 seconds
Started Jun 02 02:24:28 PM PDT 24
Finished Jun 02 02:24:30 PM PDT 24
Peak memory 196312 kb
Host smart-de608d96-89c7-4cb9-85f0-0884136a0696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841390336 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1841390336
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2417202675
Short name T40
Test name
Test status
Simulation time 531953797 ps
CPU time 1.36 seconds
Started Jun 02 02:24:27 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 193040 kb
Host smart-72231b7d-641f-45ef-aa48-a96c4bc0f03e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417202675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2417202675
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.631488612
Short name T327
Test name
Test status
Simulation time 428828218 ps
CPU time 0.61 seconds
Started Jun 02 02:24:24 PM PDT 24
Finished Jun 02 02:24:25 PM PDT 24
Peak memory 183572 kb
Host smart-c9283b51-b1f6-4d8f-9edc-0e6633935fd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631488612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.631488612
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2722906247
Short name T334
Test name
Test status
Simulation time 1180393976 ps
CPU time 1.31 seconds
Started Jun 02 02:24:26 PM PDT 24
Finished Jun 02 02:24:27 PM PDT 24
Peak memory 191828 kb
Host smart-ea1a8a91-f538-49c8-860a-53a07e50477f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722906247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2722906247
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3336585354
Short name T349
Test name
Test status
Simulation time 656037213 ps
CPU time 2.18 seconds
Started Jun 02 02:24:24 PM PDT 24
Finished Jun 02 02:24:27 PM PDT 24
Peak memory 198388 kb
Host smart-d94f7349-8f40-4415-bb4d-2b6f7360d183
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336585354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3336585354
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2611903525
Short name T201
Test name
Test status
Simulation time 4530084520 ps
CPU time 1.33 seconds
Started Jun 02 02:24:27 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 196544 kb
Host smart-44e05570-a7a9-49de-8679-4daae60bb2ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611903525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2611903525
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1009444065
Short name T318
Test name
Test status
Simulation time 405780248 ps
CPU time 0.95 seconds
Started Jun 02 02:24:27 PM PDT 24
Finished Jun 02 02:24:28 PM PDT 24
Peak memory 196864 kb
Host smart-af58c7c4-f009-4de9-b4e7-fec31c6467cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009444065 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1009444065
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.271731287
Short name T371
Test name
Test status
Simulation time 378695906 ps
CPU time 1.19 seconds
Started Jun 02 02:24:24 PM PDT 24
Finished Jun 02 02:24:26 PM PDT 24
Peak memory 183672 kb
Host smart-8992d7f9-5dd0-4105-b410-934572e1df46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271731287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.271731287
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.15603247
Short name T422
Test name
Test status
Simulation time 305089870 ps
CPU time 1.02 seconds
Started Jun 02 02:24:29 PM PDT 24
Finished Jun 02 02:24:31 PM PDT 24
Peak memory 183580 kb
Host smart-f715bc88-c7b9-4e72-8fba-0d48abeeb267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15603247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.15603247
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2359548583
Short name T85
Test name
Test status
Simulation time 2885861894 ps
CPU time 3.33 seconds
Started Jun 02 02:24:28 PM PDT 24
Finished Jun 02 02:24:32 PM PDT 24
Peak memory 191848 kb
Host smart-9b325b3b-cf90-4fb1-99d3-dbec88a33130
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359548583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2359548583
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4068598315
Short name T412
Test name
Test status
Simulation time 412176031 ps
CPU time 2.01 seconds
Started Jun 02 02:24:27 PM PDT 24
Finished Jun 02 02:24:30 PM PDT 24
Peak memory 198328 kb
Host smart-290af6a2-90ba-406d-8240-a15298e0af9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068598315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.4068598315
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1309661200
Short name T408
Test name
Test status
Simulation time 8154069661 ps
CPU time 14.23 seconds
Started Jun 02 02:24:26 PM PDT 24
Finished Jun 02 02:24:41 PM PDT 24
Peak memory 197868 kb
Host smart-dc020840-46db-4876-862b-fee785645f62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309661200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1309661200
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2908866669
Short name T253
Test name
Test status
Simulation time 48224913112 ps
CPU time 63.16 seconds
Started Jun 02 02:21:17 PM PDT 24
Finished Jun 02 02:22:21 PM PDT 24
Peak memory 191876 kb
Host smart-5fcaf759-b04d-4f7c-8270-516afc0b6e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908866669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2908866669
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3205024322
Short name T254
Test name
Test status
Simulation time 364998344 ps
CPU time 1.05 seconds
Started Jun 02 02:21:17 PM PDT 24
Finished Jun 02 02:21:19 PM PDT 24
Peak memory 191800 kb
Host smart-fc0c679f-1b48-4495-b58d-f44f175a880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205024322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3205024322
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2536088608
Short name T219
Test name
Test status
Simulation time 4424243800 ps
CPU time 2.29 seconds
Started Jun 02 02:21:18 PM PDT 24
Finished Jun 02 02:21:20 PM PDT 24
Peak memory 191832 kb
Host smart-6eccd598-c461-4985-b2af-05103ef05ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536088608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2536088608
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.365605831
Short name T24
Test name
Test status
Simulation time 8327484987 ps
CPU time 12.39 seconds
Started Jun 02 02:21:24 PM PDT 24
Finished Jun 02 02:21:37 PM PDT 24
Peak memory 215692 kb
Host smart-b523512d-e77b-493a-a194-ee1583b5f7df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365605831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.365605831
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.4083474820
Short name T33
Test name
Test status
Simulation time 362921117 ps
CPU time 1.2 seconds
Started Jun 02 02:21:19 PM PDT 24
Finished Jun 02 02:21:21 PM PDT 24
Peak memory 191772 kb
Host smart-2e87b9f1-0b17-437a-9284-ed3ad9355555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083474820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.4083474820
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1197122790
Short name T14
Test name
Test status
Simulation time 60556551322 ps
CPU time 25.24 seconds
Started Jun 02 02:22:02 PM PDT 24
Finished Jun 02 02:22:28 PM PDT 24
Peak memory 191896 kb
Host smart-d3407a56-b4ce-4e9c-9a2a-d771e6c7ae55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197122790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1197122790
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3923542557
Short name T282
Test name
Test status
Simulation time 398567996 ps
CPU time 0.83 seconds
Started Jun 02 02:22:03 PM PDT 24
Finished Jun 02 02:22:04 PM PDT 24
Peak memory 191772 kb
Host smart-89f06d86-0e2b-4adb-810e-31bb4c3af3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923542557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3923542557
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2338870185
Short name T230
Test name
Test status
Simulation time 41287893111 ps
CPU time 18.18 seconds
Started Jun 02 02:22:11 PM PDT 24
Finished Jun 02 02:22:30 PM PDT 24
Peak memory 191888 kb
Host smart-f52e36b5-3154-4ebd-94cc-9133aafa0f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338870185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2338870185
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3901398454
Short name T216
Test name
Test status
Simulation time 430569058 ps
CPU time 0.88 seconds
Started Jun 02 02:22:09 PM PDT 24
Finished Jun 02 02:22:10 PM PDT 24
Peak memory 191772 kb
Host smart-1926fb83-7bbf-4b19-a214-311ca6c20906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901398454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3901398454
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1782969012
Short name T255
Test name
Test status
Simulation time 53980188640 ps
CPU time 38.35 seconds
Started Jun 02 02:22:15 PM PDT 24
Finished Jun 02 02:22:53 PM PDT 24
Peak memory 191816 kb
Host smart-1df89790-5ea6-4194-9cd9-2a4899e8010c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782969012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1782969012
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1592834172
Short name T270
Test name
Test status
Simulation time 518578180 ps
CPU time 1 seconds
Started Jun 02 02:22:09 PM PDT 24
Finished Jun 02 02:22:11 PM PDT 24
Peak memory 191764 kb
Host smart-fa2df75c-422f-4a0c-af77-b4301fc8d08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592834172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1592834172
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2422903300
Short name T243
Test name
Test status
Simulation time 20924057332 ps
CPU time 3.69 seconds
Started Jun 02 02:22:22 PM PDT 24
Finished Jun 02 02:22:26 PM PDT 24
Peak memory 191816 kb
Host smart-32b35b0c-17de-44f8-9c71-cae6f1cec362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422903300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2422903300
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.4126674085
Short name T268
Test name
Test status
Simulation time 479537674 ps
CPU time 0.78 seconds
Started Jun 02 02:22:16 PM PDT 24
Finished Jun 02 02:22:17 PM PDT 24
Peak memory 191716 kb
Host smart-821657cf-538a-48fc-be51-913b8765b9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126674085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.4126674085
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1997803294
Short name T274
Test name
Test status
Simulation time 10182805491 ps
CPU time 4.74 seconds
Started Jun 02 02:22:15 PM PDT 24
Finished Jun 02 02:22:21 PM PDT 24
Peak memory 191848 kb
Host smart-2ae726b4-1d3d-4b67-adf1-fb69e74123e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997803294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1997803294
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3291384921
Short name T15
Test name
Test status
Simulation time 538334480 ps
CPU time 0.97 seconds
Started Jun 02 02:22:18 PM PDT 24
Finished Jun 02 02:22:19 PM PDT 24
Peak memory 191784 kb
Host smart-accb2c94-a322-491a-9b86-378949c75fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291384921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3291384921
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.923026134
Short name T276
Test name
Test status
Simulation time 33553363077 ps
CPU time 24.94 seconds
Started Jun 02 02:22:22 PM PDT 24
Finished Jun 02 02:22:47 PM PDT 24
Peak memory 191936 kb
Host smart-964f485f-49ea-40a5-9f2d-a4102505ce4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923026134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.923026134
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.4284072582
Short name T226
Test name
Test status
Simulation time 595318251 ps
CPU time 0.68 seconds
Started Jun 02 02:22:21 PM PDT 24
Finished Jun 02 02:22:22 PM PDT 24
Peak memory 191688 kb
Host smart-fb65260d-a1ef-431a-9644-5873bf4fe064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284072582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.4284072582
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.4106829114
Short name T203
Test name
Test status
Simulation time 17061036036 ps
CPU time 26.97 seconds
Started Jun 02 02:22:32 PM PDT 24
Finished Jun 02 02:23:00 PM PDT 24
Peak memory 191804 kb
Host smart-a1567352-a391-4585-908c-a63553a9e44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106829114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.4106829114
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.4096284004
Short name T34
Test name
Test status
Simulation time 509213422 ps
CPU time 1.2 seconds
Started Jun 02 02:22:32 PM PDT 24
Finished Jun 02 02:22:34 PM PDT 24
Peak memory 191696 kb
Host smart-daedb3b6-9c5a-4102-b7ae-ac9175e6a835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096284004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.4096284004
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3000362231
Short name T244
Test name
Test status
Simulation time 12669946744 ps
CPU time 1.7 seconds
Started Jun 02 02:22:28 PM PDT 24
Finished Jun 02 02:22:30 PM PDT 24
Peak memory 191912 kb
Host smart-f3c23906-5de9-4a3d-a86c-5905adf9d36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000362231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3000362231
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1787895112
Short name T252
Test name
Test status
Simulation time 552351919 ps
CPU time 1.39 seconds
Started Jun 02 02:22:28 PM PDT 24
Finished Jun 02 02:22:30 PM PDT 24
Peak memory 191920 kb
Host smart-937af9bd-f613-4d72-af97-8115d91b523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787895112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1787895112
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.675477096
Short name T242
Test name
Test status
Simulation time 19793642816 ps
CPU time 16.09 seconds
Started Jun 02 02:22:28 PM PDT 24
Finished Jun 02 02:22:44 PM PDT 24
Peak memory 191840 kb
Host smart-4cd92b6e-8e2d-405f-8e98-3b7e412f6679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675477096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.675477096
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.799295374
Short name T262
Test name
Test status
Simulation time 463646422 ps
CPU time 0.78 seconds
Started Jun 02 02:22:29 PM PDT 24
Finished Jun 02 02:22:30 PM PDT 24
Peak memory 191752 kb
Host smart-3b11cc58-6236-4c38-a104-fb2cb5a2f86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799295374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.799295374
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2548477235
Short name T2
Test name
Test status
Simulation time 49766472027 ps
CPU time 5.57 seconds
Started Jun 02 02:22:34 PM PDT 24
Finished Jun 02 02:22:40 PM PDT 24
Peak memory 191888 kb
Host smart-4d16cd41-6140-4d24-b400-1c717a6589c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548477235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2548477235
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.663491889
Short name T284
Test name
Test status
Simulation time 541831775 ps
CPU time 0.66 seconds
Started Jun 02 02:22:35 PM PDT 24
Finished Jun 02 02:22:36 PM PDT 24
Peak memory 191756 kb
Host smart-69cde8c7-dc9c-4335-b679-1815d73adffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663491889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.663491889
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1633164011
Short name T217
Test name
Test status
Simulation time 2112271910 ps
CPU time 2.42 seconds
Started Jun 02 02:21:24 PM PDT 24
Finished Jun 02 02:21:27 PM PDT 24
Peak memory 191772 kb
Host smart-bb050d80-6043-4c4e-9bd3-7a2522f6d22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633164011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1633164011
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.225802664
Short name T17
Test name
Test status
Simulation time 7754695190 ps
CPU time 12.9 seconds
Started Jun 02 02:21:31 PM PDT 24
Finished Jun 02 02:21:44 PM PDT 24
Peak memory 215652 kb
Host smart-1765f4bf-cae8-4b0b-b0b7-390f08ebcb56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225802664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.225802664
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2825295521
Short name T213
Test name
Test status
Simulation time 469803189 ps
CPU time 0.93 seconds
Started Jun 02 02:21:24 PM PDT 24
Finished Jun 02 02:21:25 PM PDT 24
Peak memory 191720 kb
Host smart-726ec8dd-e7f2-4a0d-914b-027489b66399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825295521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2825295521
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1362555181
Short name T239
Test name
Test status
Simulation time 21629804632 ps
CPU time 28.6 seconds
Started Jun 02 02:22:35 PM PDT 24
Finished Jun 02 02:23:04 PM PDT 24
Peak memory 191888 kb
Host smart-58188827-6a1f-4104-a6d5-1f864f31a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362555181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1362555181
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3508549726
Short name T90
Test name
Test status
Simulation time 540147724 ps
CPU time 0.78 seconds
Started Jun 02 02:22:35 PM PDT 24
Finished Jun 02 02:22:36 PM PDT 24
Peak memory 191712 kb
Host smart-28c80605-865d-4fef-a6c6-bcf1a8822846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508549726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3508549726
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.4138391801
Short name T248
Test name
Test status
Simulation time 29936440000 ps
CPU time 12.42 seconds
Started Jun 02 02:22:34 PM PDT 24
Finished Jun 02 02:22:47 PM PDT 24
Peak memory 191908 kb
Host smart-ddf380a0-c357-4bbd-8a62-5a4c58d73738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138391801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4138391801
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2233518873
Short name T285
Test name
Test status
Simulation time 491145819 ps
CPU time 1.28 seconds
Started Jun 02 02:22:35 PM PDT 24
Finished Jun 02 02:22:36 PM PDT 24
Peak memory 191788 kb
Host smart-7e9f7693-3761-49dd-af80-4d9416969fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233518873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2233518873
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3677738906
Short name T225
Test name
Test status
Simulation time 15735923882 ps
CPU time 27.43 seconds
Started Jun 02 02:22:42 PM PDT 24
Finished Jun 02 02:23:10 PM PDT 24
Peak memory 191888 kb
Host smart-0bd5e868-ce8d-4e1d-9ae3-98299143781b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677738906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3677738906
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.4171639626
Short name T257
Test name
Test status
Simulation time 562836466 ps
CPU time 0.79 seconds
Started Jun 02 02:22:41 PM PDT 24
Finished Jun 02 02:22:42 PM PDT 24
Peak memory 191732 kb
Host smart-9a4bda05-fa4b-49d5-b66d-a06f5489d919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171639626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4171639626
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2119058318
Short name T218
Test name
Test status
Simulation time 37663348683 ps
CPU time 24.37 seconds
Started Jun 02 02:22:46 PM PDT 24
Finished Jun 02 02:23:10 PM PDT 24
Peak memory 191912 kb
Host smart-1daa68d1-deb4-4c98-a7eb-37c9052d3c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119058318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2119058318
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1596254475
Short name T269
Test name
Test status
Simulation time 613410464 ps
CPU time 0.79 seconds
Started Jun 02 02:22:41 PM PDT 24
Finished Jun 02 02:22:43 PM PDT 24
Peak memory 191768 kb
Host smart-088ea1ba-5ce6-4eb0-93f0-bd475a55d58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596254475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1596254475
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2562720172
Short name T190
Test name
Test status
Simulation time 569734070 ps
CPU time 1.38 seconds
Started Jun 02 02:22:44 PM PDT 24
Finished Jun 02 02:22:46 PM PDT 24
Peak memory 196380 kb
Host smart-82c057de-aedf-4b69-88af-83f8f8faf245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562720172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2562720172
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.4130397401
Short name T233
Test name
Test status
Simulation time 37859065120 ps
CPU time 14.82 seconds
Started Jun 02 02:22:42 PM PDT 24
Finished Jun 02 02:22:57 PM PDT 24
Peak memory 191836 kb
Host smart-dd6fd370-a581-4628-9432-62e1c7025555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130397401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.4130397401
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2102052478
Short name T249
Test name
Test status
Simulation time 521106663 ps
CPU time 0.76 seconds
Started Jun 02 02:22:42 PM PDT 24
Finished Jun 02 02:22:43 PM PDT 24
Peak memory 191768 kb
Host smart-56f2c688-91b5-4c06-8657-3e3796cc9af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102052478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2102052478
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3490189727
Short name T237
Test name
Test status
Simulation time 14756612885 ps
CPU time 8.92 seconds
Started Jun 02 02:22:45 PM PDT 24
Finished Jun 02 02:22:55 PM PDT 24
Peak memory 191896 kb
Host smart-b4473285-9b96-4f3f-a89c-bfe2e36fdab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490189727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3490189727
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1405966629
Short name T207
Test name
Test status
Simulation time 378194888 ps
CPU time 1.16 seconds
Started Jun 02 02:22:47 PM PDT 24
Finished Jun 02 02:22:49 PM PDT 24
Peak memory 191772 kb
Host smart-3f08e66f-a9f8-47f5-9b65-583d2558316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405966629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1405966629
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2089317949
Short name T259
Test name
Test status
Simulation time 6837851703 ps
CPU time 8.42 seconds
Started Jun 02 02:22:54 PM PDT 24
Finished Jun 02 02:23:03 PM PDT 24
Peak memory 191856 kb
Host smart-c701fd14-b08d-4a91-a674-de8c0210485c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089317949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2089317949
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.345313741
Short name T234
Test name
Test status
Simulation time 531111701 ps
CPU time 0.77 seconds
Started Jun 02 02:22:53 PM PDT 24
Finished Jun 02 02:22:54 PM PDT 24
Peak memory 191768 kb
Host smart-c65cc524-6ee5-4815-bf3c-44ebfac4e1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345313741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.345313741
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2909502594
Short name T281
Test name
Test status
Simulation time 34215579144 ps
CPU time 3.71 seconds
Started Jun 02 02:22:54 PM PDT 24
Finished Jun 02 02:22:58 PM PDT 24
Peak memory 191900 kb
Host smart-9a69d657-1363-4d3a-93aa-e24545d65f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909502594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2909502594
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2809457185
Short name T240
Test name
Test status
Simulation time 480415230 ps
CPU time 0.74 seconds
Started Jun 02 02:22:54 PM PDT 24
Finished Jun 02 02:22:55 PM PDT 24
Peak memory 191716 kb
Host smart-b73ae482-a329-46b1-9bde-46a6cd46a980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809457185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2809457185
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.361856445
Short name T6
Test name
Test status
Simulation time 34811671154 ps
CPU time 49.66 seconds
Started Jun 02 02:23:01 PM PDT 24
Finished Jun 02 02:23:51 PM PDT 24
Peak memory 191908 kb
Host smart-ada4ce53-fe34-473f-94cd-6147f31f7e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361856445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.361856445
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3403209885
Short name T261
Test name
Test status
Simulation time 514970450 ps
CPU time 1.41 seconds
Started Jun 02 02:22:59 PM PDT 24
Finished Jun 02 02:23:00 PM PDT 24
Peak memory 191688 kb
Host smart-fcd3eecf-ec1e-4d75-9def-4f2caf9a6d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403209885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3403209885
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2780426156
Short name T208
Test name
Test status
Simulation time 51497912200 ps
CPU time 81.79 seconds
Started Jun 02 02:23:00 PM PDT 24
Finished Jun 02 02:24:22 PM PDT 24
Peak memory 191848 kb
Host smart-421a0953-e4a4-4e1e-81ac-314a6414cdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780426156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2780426156
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.799757138
Short name T76
Test name
Test status
Simulation time 508067035 ps
CPU time 1.31 seconds
Started Jun 02 02:22:58 PM PDT 24
Finished Jun 02 02:23:00 PM PDT 24
Peak memory 191720 kb
Host smart-59dc5d3f-a653-414d-bebe-d6e429695c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799757138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.799757138
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.277577725
Short name T275
Test name
Test status
Simulation time 8253530132 ps
CPU time 4.21 seconds
Started Jun 02 02:21:30 PM PDT 24
Finished Jun 02 02:21:34 PM PDT 24
Peak memory 191876 kb
Host smart-5e841542-c5f4-4717-8c37-bdcd09f30f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277577725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.277577725
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.4188558259
Short name T25
Test name
Test status
Simulation time 8237204153 ps
CPU time 3.56 seconds
Started Jun 02 02:21:36 PM PDT 24
Finished Jun 02 02:21:40 PM PDT 24
Peak memory 215656 kb
Host smart-c5366cb4-9f08-4f2e-85a8-03a34a94b385
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188558259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.4188558259
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.102517886
Short name T278
Test name
Test status
Simulation time 402043429 ps
CPU time 1.22 seconds
Started Jun 02 02:21:30 PM PDT 24
Finished Jun 02 02:21:32 PM PDT 24
Peak memory 191776 kb
Host smart-bc9e89df-f1c2-43aa-b5c6-66b53d1d60af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102517886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.102517886
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.581751707
Short name T162
Test name
Test status
Simulation time 51210503564 ps
CPU time 203.01 seconds
Started Jun 02 02:21:31 PM PDT 24
Finished Jun 02 02:24:55 PM PDT 24
Peak memory 206720 kb
Host smart-e75bec53-c604-405f-84d9-a818b15e7cab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581751707 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.581751707
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1720521912
Short name T277
Test name
Test status
Simulation time 33124069013 ps
CPU time 13.32 seconds
Started Jun 02 02:23:10 PM PDT 24
Finished Jun 02 02:23:24 PM PDT 24
Peak memory 191912 kb
Host smart-bb1fb9ab-5d08-4624-b052-d5994edf7369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720521912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1720521912
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3002999911
Short name T220
Test name
Test status
Simulation time 365637674 ps
CPU time 0.85 seconds
Started Jun 02 02:22:59 PM PDT 24
Finished Jun 02 02:23:00 PM PDT 24
Peak memory 191804 kb
Host smart-90ef3084-fd3d-4c6c-ad0d-8d4b43b2fc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002999911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3002999911
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2037420209
Short name T273
Test name
Test status
Simulation time 52650831151 ps
CPU time 42.73 seconds
Started Jun 02 02:23:04 PM PDT 24
Finished Jun 02 02:23:47 PM PDT 24
Peak memory 191924 kb
Host smart-60122614-7151-40ea-b4a8-e65f45e89a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037420209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2037420209
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3863291129
Short name T264
Test name
Test status
Simulation time 432735628 ps
CPU time 1.17 seconds
Started Jun 02 02:23:06 PM PDT 24
Finished Jun 02 02:23:07 PM PDT 24
Peak memory 191756 kb
Host smart-931397d9-0fa1-427c-b1de-6881ed673620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863291129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3863291129
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1075742682
Short name T241
Test name
Test status
Simulation time 38195800865 ps
CPU time 55.67 seconds
Started Jun 02 02:23:06 PM PDT 24
Finished Jun 02 02:24:02 PM PDT 24
Peak memory 191876 kb
Host smart-957bd0cc-d323-4d17-a76d-1d82d2d03c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075742682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1075742682
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3840843778
Short name T212
Test name
Test status
Simulation time 596674967 ps
CPU time 0.66 seconds
Started Jun 02 02:23:05 PM PDT 24
Finished Jun 02 02:23:06 PM PDT 24
Peak memory 191780 kb
Host smart-a3f9f870-3523-4b7b-ace7-926795a41af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840843778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3840843778
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2096863162
Short name T10
Test name
Test status
Simulation time 18347263660 ps
CPU time 24.42 seconds
Started Jun 02 02:23:10 PM PDT 24
Finished Jun 02 02:23:35 PM PDT 24
Peak memory 191912 kb
Host smart-44f9451e-5509-441e-85fc-39fb69218363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096863162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2096863162
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1936080620
Short name T250
Test name
Test status
Simulation time 517444408 ps
CPU time 1.28 seconds
Started Jun 02 02:23:14 PM PDT 24
Finished Jun 02 02:23:15 PM PDT 24
Peak memory 191988 kb
Host smart-69954a38-aa3d-4564-968d-7500670b6d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936080620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1936080620
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3214523970
Short name T260
Test name
Test status
Simulation time 42671513485 ps
CPU time 39.72 seconds
Started Jun 02 02:23:14 PM PDT 24
Finished Jun 02 02:23:54 PM PDT 24
Peak memory 192132 kb
Host smart-176ad04f-9b1d-4a85-a50e-892adc8db7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214523970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3214523970
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1782522096
Short name T245
Test name
Test status
Simulation time 543595910 ps
CPU time 0.84 seconds
Started Jun 02 02:23:10 PM PDT 24
Finished Jun 02 02:23:11 PM PDT 24
Peak memory 191768 kb
Host smart-ec86abb9-b81b-47e2-904d-a93aa7bdb952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782522096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1782522096
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3582092591
Short name T211
Test name
Test status
Simulation time 47143658967 ps
CPU time 32.24 seconds
Started Jun 02 02:23:17 PM PDT 24
Finished Jun 02 02:23:49 PM PDT 24
Peak memory 191876 kb
Host smart-c1eb9850-55a7-49e4-b13b-f801ee82af9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582092591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3582092591
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1880104039
Short name T209
Test name
Test status
Simulation time 558892874 ps
CPU time 1.32 seconds
Started Jun 02 02:23:16 PM PDT 24
Finished Jun 02 02:23:18 PM PDT 24
Peak memory 191792 kb
Host smart-6f15d83f-e0d6-4f6f-9ba0-3d4cfd8fdaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880104039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1880104039
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2465903235
Short name T235
Test name
Test status
Simulation time 32292903067 ps
CPU time 53.49 seconds
Started Jun 02 02:23:16 PM PDT 24
Finished Jun 02 02:24:10 PM PDT 24
Peak memory 191832 kb
Host smart-e5079224-b4a8-4878-8f64-ec6744d60b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465903235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2465903235
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3856450864
Short name T214
Test name
Test status
Simulation time 575443796 ps
CPU time 1.33 seconds
Started Jun 02 02:23:16 PM PDT 24
Finished Jun 02 02:23:18 PM PDT 24
Peak memory 191804 kb
Host smart-3b5dfce2-f97c-4729-9d5d-221688f148b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856450864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3856450864
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3295903679
Short name T172
Test name
Test status
Simulation time 598953314 ps
CPU time 0.82 seconds
Started Jun 02 02:23:22 PM PDT 24
Finished Jun 02 02:23:23 PM PDT 24
Peak memory 196408 kb
Host smart-d68a4d5b-5235-4441-a0af-779c20b25349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295903679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3295903679
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1700003228
Short name T46
Test name
Test status
Simulation time 1660537070 ps
CPU time 1.33 seconds
Started Jun 02 02:23:23 PM PDT 24
Finished Jun 02 02:23:24 PM PDT 24
Peak memory 191696 kb
Host smart-4cd1fe92-35d1-4fcf-8b20-3d48c5bce1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700003228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1700003228
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2356824416
Short name T272
Test name
Test status
Simulation time 537351620 ps
CPU time 0.74 seconds
Started Jun 02 02:23:22 PM PDT 24
Finished Jun 02 02:23:23 PM PDT 24
Peak memory 191764 kb
Host smart-ff9526c9-3090-47c8-851f-582c506a012e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356824416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2356824416
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2953103614
Short name T202
Test name
Test status
Simulation time 15663717071 ps
CPU time 13.17 seconds
Started Jun 02 02:23:23 PM PDT 24
Finished Jun 02 02:23:37 PM PDT 24
Peak memory 191888 kb
Host smart-db0a1440-6a6b-4c30-8b14-b23af601b849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953103614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2953103614
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.86629301
Short name T8
Test name
Test status
Simulation time 595587294 ps
CPU time 0.84 seconds
Started Jun 02 02:23:23 PM PDT 24
Finished Jun 02 02:23:24 PM PDT 24
Peak memory 191784 kb
Host smart-6b2d84c7-59f5-45b0-8af0-a17f7764df0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86629301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.86629301
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2541989818
Short name T193
Test name
Test status
Simulation time 531485864 ps
CPU time 0.85 seconds
Started Jun 02 02:23:27 PM PDT 24
Finished Jun 02 02:23:29 PM PDT 24
Peak memory 196348 kb
Host smart-b21e8e1b-35a2-4263-a898-31c58471dea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541989818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2541989818
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1234113155
Short name T258
Test name
Test status
Simulation time 598422114 ps
CPU time 0.86 seconds
Started Jun 02 02:23:23 PM PDT 24
Finished Jun 02 02:23:24 PM PDT 24
Peak memory 191720 kb
Host smart-c9aedb60-c6e4-40ad-b431-2a503b704433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234113155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1234113155
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.853176095
Short name T231
Test name
Test status
Simulation time 15562917680 ps
CPU time 10.16 seconds
Started Jun 02 02:21:35 PM PDT 24
Finished Jun 02 02:21:46 PM PDT 24
Peak memory 191848 kb
Host smart-52f05f5b-ee6e-4468-8d0a-a9f21aeb03e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853176095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.853176095
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3960382174
Short name T18
Test name
Test status
Simulation time 7811050642 ps
CPU time 11.33 seconds
Started Jun 02 02:21:43 PM PDT 24
Finished Jun 02 02:21:54 PM PDT 24
Peak memory 215764 kb
Host smart-5c902a90-c960-4681-ba82-ef9248474277
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960382174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3960382174
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.822628008
Short name T246
Test name
Test status
Simulation time 426504999 ps
CPU time 1.28 seconds
Started Jun 02 02:21:36 PM PDT 24
Finished Jun 02 02:21:37 PM PDT 24
Peak memory 191772 kb
Host smart-02015497-7ff3-4376-8b66-5928b4ffe556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822628008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.822628008
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.4168716548
Short name T223
Test name
Test status
Simulation time 30524964070 ps
CPU time 11.34 seconds
Started Jun 02 02:23:28 PM PDT 24
Finished Jun 02 02:23:40 PM PDT 24
Peak memory 191876 kb
Host smart-f0f7e1d0-8d65-40d9-a9d7-d6e4620f80ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168716548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.4168716548
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.324174719
Short name T9
Test name
Test status
Simulation time 391459810 ps
CPU time 0.72 seconds
Started Jun 02 02:23:25 PM PDT 24
Finished Jun 02 02:23:26 PM PDT 24
Peak memory 191768 kb
Host smart-a1ad1d00-49f8-42d1-a654-7e457c521301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324174719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.324174719
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1103821622
Short name T1
Test name
Test status
Simulation time 24719236138 ps
CPU time 34.16 seconds
Started Jun 02 02:23:32 PM PDT 24
Finished Jun 02 02:24:06 PM PDT 24
Peak memory 191904 kb
Host smart-f637d7fd-ce9b-4a10-9d08-2075ce292b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103821622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1103821622
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.936213886
Short name T265
Test name
Test status
Simulation time 556426785 ps
CPU time 1 seconds
Started Jun 02 02:23:33 PM PDT 24
Finished Jun 02 02:23:34 PM PDT 24
Peak memory 191752 kb
Host smart-9e63888f-21de-47a1-87b3-98449c053bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936213886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.936213886
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1127407978
Short name T26
Test name
Test status
Simulation time 26066346624 ps
CPU time 9.84 seconds
Started Jun 02 02:23:32 PM PDT 24
Finished Jun 02 02:23:42 PM PDT 24
Peak memory 191896 kb
Host smart-2345c5ab-5e2b-48e1-ad95-443ba636d72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127407978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1127407978
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.4027719101
Short name T247
Test name
Test status
Simulation time 486520957 ps
CPU time 1.39 seconds
Started Jun 02 02:23:31 PM PDT 24
Finished Jun 02 02:23:33 PM PDT 24
Peak memory 191736 kb
Host smart-33729a2a-7423-4c40-badb-5e27810ac9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027719101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.4027719101
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2982741232
Short name T210
Test name
Test status
Simulation time 30123713813 ps
CPU time 23.65 seconds
Started Jun 02 02:23:37 PM PDT 24
Finished Jun 02 02:24:01 PM PDT 24
Peak memory 191888 kb
Host smart-9144808f-5a51-499b-af57-fecb867d7ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982741232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2982741232
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.130383857
Short name T263
Test name
Test status
Simulation time 463554156 ps
CPU time 1.22 seconds
Started Jun 02 02:23:37 PM PDT 24
Finished Jun 02 02:23:38 PM PDT 24
Peak memory 191740 kb
Host smart-867b6708-204a-4204-bbcb-e69bd465cc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130383857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.130383857
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2481869453
Short name T45
Test name
Test status
Simulation time 11183708649 ps
CPU time 16.9 seconds
Started Jun 02 02:23:37 PM PDT 24
Finished Jun 02 02:23:54 PM PDT 24
Peak memory 191872 kb
Host smart-c0759d13-8613-4e79-b277-85eed07d5c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481869453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2481869453
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2965516366
Short name T266
Test name
Test status
Simulation time 351295740 ps
CPU time 1.12 seconds
Started Jun 02 02:23:41 PM PDT 24
Finished Jun 02 02:23:42 PM PDT 24
Peak memory 191756 kb
Host smart-cc1f432e-f8f1-4b3d-9a82-6941b0490e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965516366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2965516366
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1252545905
Short name T229
Test name
Test status
Simulation time 61486521810 ps
CPU time 102.05 seconds
Started Jun 02 02:23:39 PM PDT 24
Finished Jun 02 02:25:22 PM PDT 24
Peak memory 191912 kb
Host smart-3d91522e-d0c4-416a-bd8a-250082a8ab46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252545905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1252545905
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1660067232
Short name T221
Test name
Test status
Simulation time 490252545 ps
CPU time 0.76 seconds
Started Jun 02 02:23:41 PM PDT 24
Finished Jun 02 02:23:42 PM PDT 24
Peak memory 191756 kb
Host smart-d70f0b6b-f756-4282-a9ce-6d6da7043361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660067232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1660067232
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.197560410
Short name T232
Test name
Test status
Simulation time 31067439464 ps
CPU time 49.1 seconds
Started Jun 02 02:23:42 PM PDT 24
Finished Jun 02 02:24:31 PM PDT 24
Peak memory 191808 kb
Host smart-b2aba88a-b306-4f7d-8bf5-8017de3d1d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197560410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.197560410
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1335145170
Short name T215
Test name
Test status
Simulation time 340080394 ps
CPU time 1.06 seconds
Started Jun 02 02:23:43 PM PDT 24
Finished Jun 02 02:23:45 PM PDT 24
Peak memory 191768 kb
Host smart-1a230733-dd12-4c88-96e5-5dba68f74dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335145170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1335145170
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2108593582
Short name T170
Test name
Test status
Simulation time 362196317 ps
CPU time 1.17 seconds
Started Jun 02 02:23:43 PM PDT 24
Finished Jun 02 02:23:44 PM PDT 24
Peak memory 196388 kb
Host smart-b91cbe99-a19b-4472-b325-a08b6093e174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108593582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2108593582
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2035575820
Short name T267
Test name
Test status
Simulation time 8108917049 ps
CPU time 3.94 seconds
Started Jun 02 02:23:42 PM PDT 24
Finished Jun 02 02:23:46 PM PDT 24
Peak memory 191832 kb
Host smart-13e16437-1e35-4926-897a-e55cf9758d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035575820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2035575820
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1742554582
Short name T228
Test name
Test status
Simulation time 605539800 ps
CPU time 0.78 seconds
Started Jun 02 02:23:41 PM PDT 24
Finished Jun 02 02:23:42 PM PDT 24
Peak memory 191736 kb
Host smart-478a75a0-1754-40e9-a7e1-f0ac4bbd4f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742554582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1742554582
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1237792702
Short name T180
Test name
Test status
Simulation time 150432524724 ps
CPU time 170.48 seconds
Started Jun 02 02:23:44 PM PDT 24
Finished Jun 02 02:26:35 PM PDT 24
Peak memory 192608 kb
Host smart-0f54acf0-36af-408f-8ab9-1bce42c71e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237792702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1237792702
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.491148631
Short name T117
Test name
Test status
Simulation time 508394481 ps
CPU time 1.33 seconds
Started Jun 02 02:23:48 PM PDT 24
Finished Jun 02 02:23:49 PM PDT 24
Peak memory 196384 kb
Host smart-7aaec664-42a0-407d-8516-75c2d8844f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491148631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.491148631
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1810161749
Short name T72
Test name
Test status
Simulation time 15976139672 ps
CPU time 7.08 seconds
Started Jun 02 02:23:49 PM PDT 24
Finished Jun 02 02:23:56 PM PDT 24
Peak memory 191888 kb
Host smart-df3e1f80-c9c5-4f4d-85bb-2f8ac226fd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810161749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1810161749
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2671946522
Short name T256
Test name
Test status
Simulation time 623693315 ps
CPU time 0.71 seconds
Started Jun 02 02:23:49 PM PDT 24
Finished Jun 02 02:23:50 PM PDT 24
Peak memory 191780 kb
Host smart-416210ba-0d97-4776-a05d-8bbb8e678a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671946522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2671946522
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3296713059
Short name T236
Test name
Test status
Simulation time 45991254177 ps
CPU time 4.56 seconds
Started Jun 02 02:23:48 PM PDT 24
Finished Jun 02 02:23:53 PM PDT 24
Peak memory 191924 kb
Host smart-708d4267-aa9c-47a2-b946-fce33b284abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296713059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3296713059
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3356080503
Short name T71
Test name
Test status
Simulation time 417022301 ps
CPU time 0.71 seconds
Started Jun 02 02:23:48 PM PDT 24
Finished Jun 02 02:23:49 PM PDT 24
Peak memory 191732 kb
Host smart-66537fb5-4dcb-40a6-868b-4b26af53264c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356080503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3356080503
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1785239454
Short name T13
Test name
Test status
Simulation time 47006267878 ps
CPU time 20.53 seconds
Started Jun 02 02:21:42 PM PDT 24
Finished Jun 02 02:22:02 PM PDT 24
Peak memory 191836 kb
Host smart-b2ddde58-b4b9-46ff-84b9-6a2d3dffcb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785239454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1785239454
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3831527428
Short name T227
Test name
Test status
Simulation time 403953338 ps
CPU time 0.67 seconds
Started Jun 02 02:21:45 PM PDT 24
Finished Jun 02 02:21:46 PM PDT 24
Peak memory 191728 kb
Host smart-4839d18c-5ef2-4275-95ab-bb115ca8c03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831527428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3831527428
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1141055608
Short name T280
Test name
Test status
Simulation time 59996811441 ps
CPU time 80.75 seconds
Started Jun 02 02:21:50 PM PDT 24
Finished Jun 02 02:23:11 PM PDT 24
Peak memory 191900 kb
Host smart-097f2e5e-9582-4b99-b41b-f90c669aef02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141055608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1141055608
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1430992739
Short name T279
Test name
Test status
Simulation time 601637519 ps
CPU time 0.67 seconds
Started Jun 02 02:21:42 PM PDT 24
Finished Jun 02 02:21:43 PM PDT 24
Peak memory 191760 kb
Host smart-48411496-7dba-4441-9032-97df84023992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430992739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1430992739
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.792180261
Short name T222
Test name
Test status
Simulation time 23280253244 ps
CPU time 35.55 seconds
Started Jun 02 02:21:50 PM PDT 24
Finished Jun 02 02:22:26 PM PDT 24
Peak memory 191900 kb
Host smart-260a958e-1d3e-4901-8f94-235aef92581d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792180261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.792180261
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3640295670
Short name T91
Test name
Test status
Simulation time 600044258 ps
CPU time 1.03 seconds
Started Jun 02 02:21:49 PM PDT 24
Finished Jun 02 02:21:51 PM PDT 24
Peak memory 191744 kb
Host smart-ec590e9c-fe22-4c0b-a041-096f30f05237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640295670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3640295670
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.74010201
Short name T196
Test name
Test status
Simulation time 467607012 ps
CPU time 0.79 seconds
Started Jun 02 02:21:55 PM PDT 24
Finished Jun 02 02:21:56 PM PDT 24
Peak memory 196324 kb
Host smart-7b31cf35-7a81-4610-b384-b1eb48fb32ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74010201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.74010201
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3096511632
Short name T224
Test name
Test status
Simulation time 33516711653 ps
CPU time 23.55 seconds
Started Jun 02 02:21:57 PM PDT 24
Finished Jun 02 02:22:21 PM PDT 24
Peak memory 192004 kb
Host smart-5ff3f040-6e8e-4666-ba15-4c64ea277f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096511632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3096511632
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1017231966
Short name T238
Test name
Test status
Simulation time 448871902 ps
CPU time 0.73 seconds
Started Jun 02 02:21:55 PM PDT 24
Finished Jun 02 02:21:56 PM PDT 24
Peak memory 191752 kb
Host smart-f1331125-df51-4c0f-8472-307cff195fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017231966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1017231966
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1498387244
Short name T271
Test name
Test status
Simulation time 65826156308 ps
CPU time 103.02 seconds
Started Jun 02 02:21:57 PM PDT 24
Finished Jun 02 02:23:41 PM PDT 24
Peak memory 198268 kb
Host smart-12e75001-3bef-4179-bcf8-d76439604564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498387244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1498387244
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1213560515
Short name T283
Test name
Test status
Simulation time 24689982720 ps
CPU time 41.05 seconds
Started Jun 02 02:21:55 PM PDT 24
Finished Jun 02 02:22:36 PM PDT 24
Peak memory 191924 kb
Host smart-90d892b9-0f78-477b-8486-dc572f55df29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213560515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1213560515
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.34278361
Short name T251
Test name
Test status
Simulation time 439178864 ps
CPU time 0.86 seconds
Started Jun 02 02:21:57 PM PDT 24
Finished Jun 02 02:21:58 PM PDT 24
Peak memory 191760 kb
Host smart-045d2f76-d6cd-4230-a18e-061b84dfcfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34278361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.34278361
Directory /workspace/9.aon_timer_smoke/latest
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