Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	0	34	100.00	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	26860	1		T1	164		T2	12		T3	469
bark[1]	763	1		T43	114		T30	232		T52	90
bark[2]	189	1		T5	112		T99	21		T94	14
bark[3]	423	1		T177	14		T90	23		T53	14
bark[4]	559	1		T26	67		T41	63		T67	21
bark[5]	416	1		T11	102		T28	14		T103	39
bark[6]	224	1		T11	21		T19	14		T42	21
bark[7]	384	1		T3	143		T11	21		T96	14
bark[8]	485	1		T26	31		T67	68		T82	21
bark[9]	923	1		T29	21		T90	21		T67	273
bark[10]	306	1		T29	14		T104	14		T30	26
bark[11]	358	1		T4	30		T90	44		T68	30
bark[12]	772	1		T41	239		T43	188		T48	14
bark[13]	339	1		T43	21		T30	21		T52	35
bark[14]	596	1		T45	14		T111	21		T90	40
bark[15]	449	1		T30	42		T163	21		T115	21
bark[16]	199	1		T4	39		T90	21		T118	26
bark[17]	533	1		T26	188		T90	21		T30	21
bark[18]	174	1		T4	21		T30	21		T109	21
bark[19]	223	1		T5	21		T9	14		T26	21
bark[20]	637	1		T10	14		T42	35		T30	30
bark[21]	834	1		T29	42		T26	91		T50	121
bark[22]	664	1		T90	39		T50	68		T93	264
bark[23]	280	1		T31	53		T25	14		T30	21
bark[24]	717	1		T13	114		T30	271		T46	21
bark[25]	447	1		T41	26		T47	61		T93	177
bark[26]	456	1		T43	65		T67	223		T115	21
bark[27]	485	1		T5	264		T8	14		T24	39
bark[28]	280	1		T24	98		T86	26		T126	21
bark[29]	338	1		T1	14		T5	26		T140	14
bark[30]	360	1		T1	30		T27	14		T93	21
bark[31]	817	1		T3	151		T5	235		T43	21
bark_0	4698	1		T1	7		T2	7		T3	73

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	26355	1		T1	164		T2	11		T3	455
bite[1]	818	1		T5	263		T8	13		T41	212
bite[2]	460	1		T5	21		T68	13		T86	21
bite[3]	526	1		T90	22		T47	60		T68	69
bite[4]	338	1		T4	39		T140	13		T67	21
bite[5]	281	1		T5	90		T13	26		T41	25
bite[6]	478	1		T26	253		T111	21		T90	42
bite[7]	454	1		T28	13		T13	113		T29	42
bite[8]	261	1		T47	147		T151	13		T116	13
bite[9]	330	1		T43	125		T30	26		T82	26
bite[10]	170	1		T4	21		T50	68		T162	21
bite[11]	701	1		T41	62		T104	13		T30	21
bite[12]	794	1		T1	13		T19	13		T52	125
bite[13]	394	1		T42	21		T43	85		T30	21
bite[14]	213	1		T1	30		T90	21		T43	21
bite[15]	303	1		T3	150		T5	21		T30	21
bite[16]	418	1		T45	13		T30	174		T76	70
bite[17]	741	1		T90	39		T43	83		T125	26
bite[18]	240	1		T5	26		T24	98		T30	30
bite[19]	240	1		T26	90		T90	40		T77	36
bite[20]	488	1		T26	21		T115	21		T120	25
bite[21]	1180	1		T30	21		T67	67		T128	13
bite[22]	850	1		T30	270		T67	222		T68	21
bite[23]	86	1		T90	21		T48	13		T53	13
bite[24]	248	1		T10	13		T25	13		T43	21
bite[25]	174	1		T177	13		T46	21		T149	43
bite[26]	269	1		T24	39		T68	30		T93	30
bite[27]	699	1		T9	13		T46	21		T82	40
bite[28]	744	1		T3	45		T11	42		T90	44
bite[29]	566	1		T3	96		T31	52		T30	21
bite[30]	491	1		T29	13		T46	30		T86	26
bite[31]	735	1		T43	187		T67	251		T77	4
bite_0	5143	1		T1	8		T2	8		T3	90

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	46188	1		T1	215		T2	19		T3	836

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	0	34	100.00

User Defined Bins for prescale_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale_max	24	1		T149	24		-	-		-	-
prescale[0]	1131	1		T5	19		T13	73		T31	90
prescale[1]	959	1		T5	160		T13	21		T41	24
prescale[2]	882	1		T5	86		T20	9		T41	60
prescale[3]	352	1		T13	2		T26	2		T41	2
prescale[4]	696	1		T3	19		T30	40		T47	2
prescale[5]	711	1		T1	37		T3	47		T26	2
prescale[6]	699	1		T1	42		T3	20		T41	2
prescale[7]	471	1		T1	47		T3	2		T5	61
prescale[8]	1234	1		T2	9		T3	49		T13	2
prescale[9]	483	1		T5	66		T30	24		T46	116
prescale[10]	670	1		T40	28		T30	41		T46	49
prescale[11]	347	1		T4	58		T31	19		T30	2
prescale[12]	800	1		T11	19		T40	2		T26	2
prescale[13]	875	1		T3	20		T5	2		T6	9
prescale[14]	770	1		T5	77		T41	19		T67	19
prescale[15]	864	1		T1	49		T3	35		T5	19
prescale[16]	674	1		T3	2		T7	9		T41	21
prescale[17]	369	1		T40	20		T111	40		T42	2
prescale[18]	659	1		T40	2		T41	2		T42	58
prescale[19]	771	1		T3	100		T31	78		T47	94
prescale[20]	616	1		T5	23		T31	2		T41	2
prescale[21]	854	1		T3	56		T5	79		T13	27
prescale[22]	928	1		T4	38		T5	249		T26	20
prescale[23]	525	1		T3	9		T13	2		T29	37
prescale[24]	605	1		T5	114		T13	2		T41	2
prescale[25]	666	1		T3	61		T5	60		T29	30
prescale[26]	496	1		T4	53		T31	24		T40	57
prescale[27]	580	1		T3	16		T4	19		T31	2
prescale[28]	558	1		T3	2		T5	66		T11	36
prescale[29]	801	1		T13	2		T184	9		T90	58
prescale[30]	257	1		T30	20		T50	38		T67	2
prescale[31]	1002	1		T1	23		T5	2		T13	40
prescale_0	23883	1		T1	17		T2	10		T3	398

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	34703	1		T1	184		T2	19		T3	666
auto[1]	11485	1		T1	31		T3	170		T4	124

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	46188	1		T1	215		T2	19		T3	836

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	27116	1		T1	165		T2	14		T3	542
wkup[1]	241	1		T5	35		T11	21		T26	21
wkup[2]	222	1		T40	21		T24	30		T26	30
wkup[3]	160	1		T31	35		T86	21		T118	26
wkup[4]	261	1		T13	21		T90	24		T30	60
wkup[5]	188	1		T5	21		T47	30		T93	26
wkup[6]	232	1		T41	21		T43	40		T30	30
wkup[7]	141	1		T30	21		T51	8		T93	21
wkup[8]	294	1		T3	21		T5	21		T90	21
wkup[9]	361	1		T31	35		T25	15		T30	21
wkup[10]	303	1		T9	15		T31	21		T26	21
wkup[11]	196	1		T3	26		T5	26		T30	30
wkup[12]	170	1		T30	21		T52	21		T86	47
wkup[13]	262	1		T13	30		T46	21		T148	21
wkup[14]	248	1		T43	30		T163	21		T82	21
wkup[15]	121	1		T5	21		T8	15		T29	21
wkup[16]	270	1		T30	41		T67	62		T86	21
wkup[17]	288	1		T1	30		T27	15		T30	21
wkup[18]	130	1		T82	26		T83	15		T129	26
wkup[19]	288	1		T5	21		T31	30		T43	26
wkup[20]	352	1		T1	15		T5	36		T43	51
wkup[21]	42	1		T78	21		T119	21		-	-
wkup[22]	342	1		T24	21		T90	21		T46	30
wkup[23]	386	1		T5	21		T30	72		T46	21
wkup[24]	271	1		T13	42		T43	26		T46	21
wkup[25]	227	1		T31	30		T43	21		T30	21
wkup[26]	274	1		T24	21		T93	21		T86	15
wkup[27]	133	1		T3	21		T93	21		T110	21
wkup[28]	217	1		T111	30		T46	26		T67	26
wkup[29]	129	1		T24	21		T42	15		T46	21
wkup[30]	223	1		T5	21		T26	31		T140	15
wkup[31]	220	1		T19	15		T52	21		T93	30
wkup[32]	170	1		T90	44		T42	21		T46	21
wkup[33]	165	1		T3	30		T90	21		T30	21
wkup[34]	227	1		T29	15		T30	21		T46	21
wkup[35]	403	1		T104	15		T43	50		T52	35
wkup[36]	270	1		T13	21		T90	21		T30	21
wkup[37]	285	1		T3	21		T5	42		T13	21
wkup[38]	158	1		T3	21		T47	21		T82	80
wkup[39]	192	1		T5	26		T42	21		T30	30
wkup[40]	261	1		T11	21		T31	21		T26	21
wkup[41]	347	1		T3	35		T11	21		T24	35
wkup[42]	359	1		T4	30		T45	15		T90	21
wkup[43]	258	1		T11	21		T42	21		T46	21
wkup[44]	396	1		T5	55		T30	81		T46	21
wkup[45]	313	1		T3	8		T13	21		T42	21
wkup[46]	199	1		T148	21		T78	26		T99	40
wkup[47]	155	1		T5	14		T26	21		T128	15
wkup[48]	228	1		T30	21		T46	21		T53	15
wkup[49]	260	1		T5	63		T10	15		T41	21
wkup[50]	276	1		T42	21		T76	21		T54	8
wkup[51]	250	1		T4	21		T13	21		T26	26
wkup[52]	317	1		T5	21		T29	21		T26	26
wkup[53]	203	1		T30	21		T47	21		T86	21
wkup[54]	297	1		T28	15		T43	21		T30	21
wkup[55]	234	1		T5	21		T111	21		T42	21
wkup[56]	218	1		T31	21		T26	21		T47	36
wkup[57]	212	1		T3	35		T4	21		T13	26
wkup[58]	176	1		T54	26		T115	21		T102	21
wkup[59]	263	1		T26	44		T67	21		T93	21
wkup[60]	369	1		T5	30		T90	21		T43	21
wkup[61]	263	1		T29	21		T40	21		T26	21
wkup[62]	143	1		T24	21		T50	21		T52	30
wkup[63]	344	1		T3	21		T11	21		T30	21
wkup_0	3669	1		T1	5		T2	5		T3	55