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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.68 99.33 93.67 100.00 98.40 99.51 47.16


Total test records in report: 420
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T32 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2118199099 Jun 04 12:59:22 PM PDT 24 Jun 04 12:59:24 PM PDT 24 507829695 ps
T39 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2236792525 Jun 04 12:59:27 PM PDT 24 Jun 04 12:59:29 PM PDT 24 432034567 ps
T281 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1527339764 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:33 PM PDT 24 450352179 ps
T282 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3461847929 Jun 04 12:59:39 PM PDT 24 Jun 04 12:59:43 PM PDT 24 339819281 ps
T283 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.982249501 Jun 04 12:59:37 PM PDT 24 Jun 04 12:59:39 PM PDT 24 307078167 ps
T185 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.232888797 Jun 04 12:59:30 PM PDT 24 Jun 04 12:59:33 PM PDT 24 433636098 ps
T284 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3374898639 Jun 04 12:59:36 PM PDT 24 Jun 04 12:59:38 PM PDT 24 463511998 ps
T285 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.254716489 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:35 PM PDT 24 841097556 ps
T286 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1920892500 Jun 04 12:59:33 PM PDT 24 Jun 04 12:59:36 PM PDT 24 360849708 ps
T33 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3181650726 Jun 04 12:59:21 PM PDT 24 Jun 04 12:59:24 PM PDT 24 924860126 ps
T186 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3454202082 Jun 04 12:59:35 PM PDT 24 Jun 04 12:59:37 PM PDT 24 563556296 ps
T34 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.223669743 Jun 04 12:59:30 PM PDT 24 Jun 04 12:59:38 PM PDT 24 3963537566 ps
T35 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1026443141 Jun 04 12:59:38 PM PDT 24 Jun 04 12:59:44 PM PDT 24 4088063677 ps
T287 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.690661720 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:21 PM PDT 24 436099020 ps
T288 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2153778958 Jun 04 12:59:32 PM PDT 24 Jun 04 12:59:35 PM PDT 24 368731830 ps
T289 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.115780360 Jun 04 12:59:32 PM PDT 24 Jun 04 12:59:36 PM PDT 24 483040031 ps
T290 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1806542370 Jun 04 12:59:21 PM PDT 24 Jun 04 12:59:23 PM PDT 24 540694341 ps
T36 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.211058599 Jun 04 12:59:16 PM PDT 24 Jun 04 12:59:30 PM PDT 24 8540952057 ps
T55 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2032924230 Jun 04 12:59:20 PM PDT 24 Jun 04 12:59:23 PM PDT 24 347296624 ps
T291 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3147884793 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:21 PM PDT 24 314467864 ps
T69 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.440234999 Jun 04 12:59:17 PM PDT 24 Jun 04 12:59:20 PM PDT 24 1298327608 ps
T70 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2436578789 Jun 04 12:59:20 PM PDT 24 Jun 04 12:59:23 PM PDT 24 1142771214 ps
T292 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1620909795 Jun 04 12:59:38 PM PDT 24 Jun 04 12:59:41 PM PDT 24 295871153 ps
T293 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1816286207 Jun 04 12:59:32 PM PDT 24 Jun 04 12:59:36 PM PDT 24 392493261 ps
T294 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2095487290 Jun 04 12:59:14 PM PDT 24 Jun 04 12:59:15 PM PDT 24 555222810 ps
T295 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3212932121 Jun 04 12:59:12 PM PDT 24 Jun 04 12:59:15 PM PDT 24 432600635 ps
T180 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3744882353 Jun 04 12:59:28 PM PDT 24 Jun 04 12:59:32 PM PDT 24 4627720190 ps
T296 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.740259556 Jun 04 12:59:30 PM PDT 24 Jun 04 12:59:34 PM PDT 24 414961893 ps
T297 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2459363253 Jun 04 12:59:24 PM PDT 24 Jun 04 12:59:27 PM PDT 24 522358685 ps
T56 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2517518835 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:33 PM PDT 24 478054239 ps
T298 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4079619182 Jun 04 12:59:35 PM PDT 24 Jun 04 12:59:38 PM PDT 24 511784556 ps
T181 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3096365946 Jun 04 12:59:20 PM PDT 24 Jun 04 12:59:34 PM PDT 24 8582906819 ps
T57 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3142820442 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:41 PM PDT 24 10227649249 ps
T299 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2768212728 Jun 04 12:59:08 PM PDT 24 Jun 04 12:59:11 PM PDT 24 710156024 ps
T182 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1097339278 Jun 04 12:59:36 PM PDT 24 Jun 04 12:59:43 PM PDT 24 8220213073 ps
T300 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2989930963 Jun 04 12:59:15 PM PDT 24 Jun 04 12:59:18 PM PDT 24 433920238 ps
T301 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3153600381 Jun 04 12:59:30 PM PDT 24 Jun 04 12:59:32 PM PDT 24 408865157 ps
T302 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2121728874 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:22 PM PDT 24 643174854 ps
T303 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3837451033 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:34 PM PDT 24 585387101 ps
T304 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.72846747 Jun 04 12:59:33 PM PDT 24 Jun 04 12:59:36 PM PDT 24 277820668 ps
T305 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2803392030 Jun 04 12:59:36 PM PDT 24 Jun 04 12:59:38 PM PDT 24 544866063 ps
T306 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3468900181 Jun 04 12:59:17 PM PDT 24 Jun 04 12:59:18 PM PDT 24 346061522 ps
T307 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4245077757 Jun 04 12:59:30 PM PDT 24 Jun 04 12:59:33 PM PDT 24 444212885 ps
T58 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1073804099 Jun 04 12:59:21 PM PDT 24 Jun 04 12:59:24 PM PDT 24 910215191 ps
T71 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2564831069 Jun 04 12:59:29 PM PDT 24 Jun 04 12:59:32 PM PDT 24 1791166712 ps
T308 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3720447630 Jun 04 12:59:14 PM PDT 24 Jun 04 12:59:17 PM PDT 24 478531693 ps
T309 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2406733672 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:34 PM PDT 24 568276832 ps
T72 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.170653762 Jun 04 12:59:13 PM PDT 24 Jun 04 12:59:15 PM PDT 24 1250773909 ps
T310 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.362928359 Jun 04 12:59:20 PM PDT 24 Jun 04 12:59:23 PM PDT 24 291920447 ps
T63 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1033595425 Jun 04 12:59:30 PM PDT 24 Jun 04 12:59:31 PM PDT 24 543416146 ps
T59 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.868260273 Jun 04 12:59:33 PM PDT 24 Jun 04 12:59:36 PM PDT 24 357638378 ps
T311 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1573584528 Jun 04 12:59:18 PM PDT 24 Jun 04 12:59:20 PM PDT 24 500728120 ps
T312 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1188210683 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:22 PM PDT 24 1148602676 ps
T313 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2864740 Jun 04 12:59:23 PM PDT 24 Jun 04 12:59:25 PM PDT 24 332178010 ps
T314 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.248768983 Jun 04 12:59:22 PM PDT 24 Jun 04 12:59:24 PM PDT 24 371747050 ps
T73 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2130360187 Jun 04 12:59:32 PM PDT 24 Jun 04 12:59:38 PM PDT 24 1350974206 ps
T315 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2288965545 Jun 04 12:59:21 PM PDT 24 Jun 04 12:59:23 PM PDT 24 417138671 ps
T316 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3731102153 Jun 04 12:59:34 PM PDT 24 Jun 04 12:59:37 PM PDT 24 476897178 ps
T317 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3878158981 Jun 04 12:59:18 PM PDT 24 Jun 04 12:59:20 PM PDT 24 479850262 ps
T318 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2530387698 Jun 04 12:59:39 PM PDT 24 Jun 04 12:59:42 PM PDT 24 444864814 ps
T319 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1200772965 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:23 PM PDT 24 495431319 ps
T320 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2392229564 Jun 04 12:59:34 PM PDT 24 Jun 04 12:59:37 PM PDT 24 378939575 ps
T321 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.422611741 Jun 04 12:59:22 PM PDT 24 Jun 04 12:59:25 PM PDT 24 504571047 ps
T322 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1719730613 Jun 04 12:59:44 PM PDT 24 Jun 04 12:59:47 PM PDT 24 661279347 ps
T323 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1673489619 Jun 04 12:59:21 PM PDT 24 Jun 04 12:59:23 PM PDT 24 925020384 ps
T324 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2480426453 Jun 04 12:59:34 PM PDT 24 Jun 04 12:59:37 PM PDT 24 448061105 ps
T74 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.448724379 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:41 PM PDT 24 2739371438 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2524067277 Jun 04 12:59:22 PM PDT 24 Jun 04 12:59:25 PM PDT 24 374470397 ps
T64 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3802092546 Jun 04 12:59:39 PM PDT 24 Jun 04 12:59:42 PM PDT 24 414739894 ps
T325 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2579223785 Jun 04 12:59:21 PM PDT 24 Jun 04 12:59:23 PM PDT 24 427525012 ps
T326 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4189940695 Jun 04 12:59:39 PM PDT 24 Jun 04 12:59:43 PM PDT 24 444234483 ps
T327 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1898590805 Jun 04 12:59:26 PM PDT 24 Jun 04 12:59:29 PM PDT 24 336525646 ps
T61 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3316665595 Jun 04 12:59:13 PM PDT 24 Jun 04 12:59:15 PM PDT 24 570186417 ps
T328 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2842141055 Jun 04 12:59:34 PM PDT 24 Jun 04 12:59:38 PM PDT 24 2041265230 ps
T329 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1432108981 Jun 04 12:59:33 PM PDT 24 Jun 04 12:59:38 PM PDT 24 371239343 ps
T330 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.144525837 Jun 04 12:59:34 PM PDT 24 Jun 04 12:59:37 PM PDT 24 379482943 ps
T331 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2415186087 Jun 04 12:59:43 PM PDT 24 Jun 04 12:59:46 PM PDT 24 512302802 ps
T332 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.692275537 Jun 04 12:59:30 PM PDT 24 Jun 04 12:59:36 PM PDT 24 2284980449 ps
T333 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3941570362 Jun 04 12:59:32 PM PDT 24 Jun 04 12:59:38 PM PDT 24 2247520380 ps
T334 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3915872688 Jun 04 12:59:34 PM PDT 24 Jun 04 12:59:37 PM PDT 24 299936541 ps
T335 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3202917396 Jun 04 12:59:32 PM PDT 24 Jun 04 12:59:36 PM PDT 24 504307244 ps
T336 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2290234293 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:34 PM PDT 24 891722409 ps
T337 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.587453262 Jun 04 12:59:12 PM PDT 24 Jun 04 12:59:14 PM PDT 24 434542157 ps
T338 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2164025244 Jun 04 12:59:37 PM PDT 24 Jun 04 12:59:39 PM PDT 24 293351052 ps
T339 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3319212745 Jun 04 12:59:33 PM PDT 24 Jun 04 12:59:36 PM PDT 24 538015462 ps
T340 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2810222406 Jun 04 12:59:30 PM PDT 24 Jun 04 12:59:33 PM PDT 24 2078192392 ps
T341 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2236713314 Jun 04 12:59:35 PM PDT 24 Jun 04 12:59:39 PM PDT 24 609229614 ps
T342 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1608048302 Jun 04 12:59:35 PM PDT 24 Jun 04 12:59:38 PM PDT 24 375149798 ps
T343 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1945773960 Jun 04 12:59:32 PM PDT 24 Jun 04 12:59:36 PM PDT 24 388786504 ps
T344 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4054201914 Jun 04 12:59:23 PM PDT 24 Jun 04 12:59:26 PM PDT 24 421717859 ps
T345 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1926598964 Jun 04 12:59:37 PM PDT 24 Jun 04 12:59:40 PM PDT 24 381900807 ps
T346 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4102202545 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:30 PM PDT 24 14265272560 ps
T347 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.4158475937 Jun 04 12:59:17 PM PDT 24 Jun 04 12:59:20 PM PDT 24 715043115 ps
T348 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4054282264 Jun 04 12:59:22 PM PDT 24 Jun 04 12:59:27 PM PDT 24 1498555664 ps
T349 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.888351978 Jun 04 12:59:26 PM PDT 24 Jun 04 12:59:28 PM PDT 24 290950307 ps
T350 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1158678314 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:26 PM PDT 24 1822353730 ps
T351 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1739189792 Jun 04 12:59:34 PM PDT 24 Jun 04 12:59:37 PM PDT 24 515996101 ps
T352 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3051626177 Jun 04 12:59:33 PM PDT 24 Jun 04 12:59:36 PM PDT 24 419488308 ps
T353 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1400489980 Jun 04 12:59:12 PM PDT 24 Jun 04 12:59:14 PM PDT 24 873299244 ps
T354 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2752549737 Jun 04 12:59:21 PM PDT 24 Jun 04 12:59:24 PM PDT 24 448172055 ps
T355 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.951385237 Jun 04 12:59:32 PM PDT 24 Jun 04 12:59:35 PM PDT 24 400888064 ps
T356 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1045854963 Jun 04 12:59:34 PM PDT 24 Jun 04 12:59:40 PM PDT 24 2287792618 ps
T357 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.845879915 Jun 04 12:59:30 PM PDT 24 Jun 04 12:59:37 PM PDT 24 8092753315 ps
T358 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1123781816 Jun 04 12:59:54 PM PDT 24 Jun 04 12:59:55 PM PDT 24 376426407 ps
T359 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4079392579 Jun 04 12:59:30 PM PDT 24 Jun 04 12:59:32 PM PDT 24 470052858 ps
T360 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2682712680 Jun 04 12:59:13 PM PDT 24 Jun 04 12:59:15 PM PDT 24 1356274406 ps
T361 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3943759317 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:21 PM PDT 24 317119050 ps
T362 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1434894705 Jun 04 12:59:37 PM PDT 24 Jun 04 12:59:40 PM PDT 24 457960979 ps
T363 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3414430635 Jun 04 12:59:26 PM PDT 24 Jun 04 12:59:31 PM PDT 24 470113789 ps
T364 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3240745518 Jun 04 12:59:36 PM PDT 24 Jun 04 12:59:39 PM PDT 24 449107576 ps
T365 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.486770687 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:34 PM PDT 24 562127573 ps
T366 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3780821933 Jun 04 12:59:22 PM PDT 24 Jun 04 12:59:25 PM PDT 24 435642719 ps
T367 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2906515281 Jun 04 12:59:39 PM PDT 24 Jun 04 12:59:41 PM PDT 24 410832498 ps
T368 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.393271180 Jun 04 12:59:38 PM PDT 24 Jun 04 12:59:50 PM PDT 24 268502965 ps
T369 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1962253587 Jun 04 12:59:17 PM PDT 24 Jun 04 12:59:22 PM PDT 24 8205447134 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3520720952 Jun 04 12:59:22 PM PDT 24 Jun 04 12:59:25 PM PDT 24 551016292 ps
T370 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3554150251 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:21 PM PDT 24 439272645 ps
T371 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1646039674 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:35 PM PDT 24 601043083 ps
T372 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1090699941 Jun 04 12:59:15 PM PDT 24 Jun 04 12:59:18 PM PDT 24 555106453 ps
T66 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2784225536 Jun 04 12:59:12 PM PDT 24 Jun 04 12:59:19 PM PDT 24 10179182277 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2922249533 Jun 04 12:59:15 PM PDT 24 Jun 04 12:59:17 PM PDT 24 408336941 ps
T183 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2612701631 Jun 04 12:59:20 PM PDT 24 Jun 04 12:59:26 PM PDT 24 8393609616 ps
T374 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1014986870 Jun 04 12:59:33 PM PDT 24 Jun 04 12:59:36 PM PDT 24 499811987 ps
T375 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3801977224 Jun 04 12:59:32 PM PDT 24 Jun 04 12:59:37 PM PDT 24 4158919458 ps
T376 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.767082314 Jun 04 12:59:20 PM PDT 24 Jun 04 12:59:25 PM PDT 24 2221947265 ps
T377 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.234359972 Jun 04 12:59:34 PM PDT 24 Jun 04 12:59:37 PM PDT 24 459696218 ps
T62 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4194707875 Jun 04 12:59:18 PM PDT 24 Jun 04 12:59:21 PM PDT 24 416349996 ps
T378 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1374598841 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:36 PM PDT 24 1909641072 ps
T379 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2423420532 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:35 PM PDT 24 1036314309 ps
T380 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2524091133 Jun 04 12:59:39 PM PDT 24 Jun 04 12:59:45 PM PDT 24 8402029746 ps
T381 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2711439460 Jun 04 12:59:43 PM PDT 24 Jun 04 12:59:51 PM PDT 24 4538528571 ps
T382 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1389631502 Jun 04 12:59:23 PM PDT 24 Jun 04 12:59:25 PM PDT 24 403421534 ps
T383 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3626708616 Jun 04 12:59:40 PM PDT 24 Jun 04 12:59:43 PM PDT 24 518750564 ps
T384 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2613079113 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:35 PM PDT 24 720694626 ps
T385 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.542508871 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:41 PM PDT 24 14148738387 ps
T386 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1658755595 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:35 PM PDT 24 434215365 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3435369030 Jun 04 12:59:18 PM PDT 24 Jun 04 12:59:20 PM PDT 24 454518106 ps
T388 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.459152212 Jun 04 12:59:17 PM PDT 24 Jun 04 12:59:18 PM PDT 24 574814131 ps
T389 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3771733075 Jun 04 12:59:30 PM PDT 24 Jun 04 12:59:37 PM PDT 24 8943762299 ps
T390 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2749886446 Jun 04 12:59:27 PM PDT 24 Jun 04 12:59:29 PM PDT 24 322267043 ps
T391 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2679106499 Jun 04 12:59:24 PM PDT 24 Jun 04 12:59:28 PM PDT 24 2956868100 ps
T392 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3826946679 Jun 04 12:59:38 PM PDT 24 Jun 04 12:59:41 PM PDT 24 470451521 ps
T393 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1832967450 Jun 04 12:59:20 PM PDT 24 Jun 04 12:59:23 PM PDT 24 560470012 ps
T394 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1253939925 Jun 04 12:59:11 PM PDT 24 Jun 04 12:59:14 PM PDT 24 413114656 ps
T395 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2139499792 Jun 04 12:59:33 PM PDT 24 Jun 04 12:59:36 PM PDT 24 356835748 ps
T396 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.54781815 Jun 04 12:59:17 PM PDT 24 Jun 04 12:59:19 PM PDT 24 431951716 ps
T397 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3886134197 Jun 04 12:59:35 PM PDT 24 Jun 04 12:59:51 PM PDT 24 8031391761 ps
T398 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.161567123 Jun 04 12:59:37 PM PDT 24 Jun 04 12:59:41 PM PDT 24 531642398 ps
T399 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1144735602 Jun 04 12:59:39 PM PDT 24 Jun 04 12:59:42 PM PDT 24 468752662 ps
T400 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4175681903 Jun 04 12:59:26 PM PDT 24 Jun 04 12:59:30 PM PDT 24 1330734698 ps
T401 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3147663904 Jun 04 12:59:22 PM PDT 24 Jun 04 12:59:26 PM PDT 24 4316731265 ps
T402 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4217855513 Jun 04 12:59:29 PM PDT 24 Jun 04 12:59:31 PM PDT 24 446176066 ps
T403 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.850643320 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:24 PM PDT 24 8243562066 ps
T404 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1077111422 Jun 04 12:59:13 PM PDT 24 Jun 04 12:59:22 PM PDT 24 4065193263 ps
T405 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3837179001 Jun 04 12:59:20 PM PDT 24 Jun 04 12:59:24 PM PDT 24 1508658899 ps
T406 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1691766667 Jun 04 12:59:28 PM PDT 24 Jun 04 12:59:43 PM PDT 24 8434384238 ps
T407 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1453661579 Jun 04 12:59:37 PM PDT 24 Jun 04 12:59:40 PM PDT 24 403467620 ps
T408 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.407720599 Jun 04 12:59:18 PM PDT 24 Jun 04 12:59:19 PM PDT 24 525388738 ps
T409 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3343578488 Jun 04 12:59:31 PM PDT 24 Jun 04 12:59:34 PM PDT 24 397351429 ps
T410 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1264917518 Jun 04 12:59:36 PM PDT 24 Jun 04 12:59:39 PM PDT 24 492938889 ps
T411 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3469341102 Jun 04 12:59:11 PM PDT 24 Jun 04 12:59:14 PM PDT 24 488007049 ps
T412 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.817428189 Jun 04 12:59:33 PM PDT 24 Jun 04 12:59:37 PM PDT 24 337197240 ps
T413 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1435467014 Jun 04 12:59:19 PM PDT 24 Jun 04 12:59:21 PM PDT 24 443247183 ps
T414 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1545410002 Jun 04 12:59:16 PM PDT 24 Jun 04 12:59:24 PM PDT 24 4032578544 ps
T415 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1133226657 Jun 04 12:59:20 PM PDT 24 Jun 04 12:59:23 PM PDT 24 365708481 ps
T416 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3127154738 Jun 04 12:59:34 PM PDT 24 Jun 04 12:59:44 PM PDT 24 2415859940 ps
T417 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2364290235 Jun 04 12:59:32 PM PDT 24 Jun 04 12:59:37 PM PDT 24 4489732923 ps
T418 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1887133388 Jun 04 12:59:38 PM PDT 24 Jun 04 12:59:41 PM PDT 24 455758282 ps
T419 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3023258706 Jun 04 12:59:18 PM PDT 24 Jun 04 12:59:20 PM PDT 24 465581377 ps
T420 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.863628348 Jun 04 12:59:22 PM PDT 24 Jun 04 12:59:24 PM PDT 24 286081331 ps

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3024537845
Short name T5
Test name
Test status
Simulation time 207696050951 ps
CPU time 447.75 seconds
Started Jun 04 01:28:59 PM PDT 24
Finished Jun 04 01:36:27 PM PDT 24
Peak memory 206836 kb
Host smart-72b4f506-9e4c-4b0d-8617-0e6ac17a8c8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024537845 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3024537845
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.501544115
Short name T31
Test name
Test status
Simulation time 33181817591 ps
CPU time 258.6 seconds
Started Jun 04 01:29:17 PM PDT 24
Finished Jun 04 01:33:36 PM PDT 24
Peak memory 198600 kb
Host smart-6e2c4d9f-33d0-4fe6-a5d5-66e6e0d35fe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501544115 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.501544115
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.211058599
Short name T36
Test name
Test status
Simulation time 8540952057 ps
CPU time 13 seconds
Started Jun 04 12:59:16 PM PDT 24
Finished Jun 04 12:59:30 PM PDT 24
Peak memory 197968 kb
Host smart-d879d66f-0b2d-47bf-a35f-072f84a115c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211058599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.211058599
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3080541050
Short name T43
Test name
Test status
Simulation time 82389952260 ps
CPU time 880.08 seconds
Started Jun 04 01:28:08 PM PDT 24
Finished Jun 04 01:42:49 PM PDT 24
Peak memory 215040 kb
Host smart-2d1e8db7-ee4e-48cb-b1ca-0a712e01135d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080541050 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3080541050
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2836381301
Short name T30
Test name
Test status
Simulation time 651060128221 ps
CPU time 409.42 seconds
Started Jun 04 01:30:16 PM PDT 24
Finished Jun 04 01:37:07 PM PDT 24
Peak memory 206884 kb
Host smart-5915346d-17d0-484c-b247-15d78d3b6695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836381301 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2836381301
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3581144184
Short name T4
Test name
Test status
Simulation time 215917123219 ps
CPU time 50.56 seconds
Started Jun 04 01:29:53 PM PDT 24
Finished Jun 04 01:30:44 PM PDT 24
Peak memory 191888 kb
Host smart-9b0db0c7-7964-4d7c-8d50-f1f1c8554a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581144184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3581144184
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1248432537
Short name T46
Test name
Test status
Simulation time 91512168053 ps
CPU time 502.37 seconds
Started Jun 04 01:28:59 PM PDT 24
Finished Jun 04 01:37:22 PM PDT 24
Peak memory 204180 kb
Host smart-8bea4d64-309f-4359-a065-76edbbbed801
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248432537 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1248432537
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.132283389
Short name T99
Test name
Test status
Simulation time 104350109033 ps
CPU time 84.09 seconds
Started Jun 04 01:29:51 PM PDT 24
Finished Jun 04 01:31:16 PM PDT 24
Peak memory 191936 kb
Host smart-350940b1-4356-4db4-bd8d-4d3ca2f22d31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132283389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.132283389
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3431017060
Short name T86
Test name
Test status
Simulation time 48671246184 ps
CPU time 394.57 seconds
Started Jun 04 01:30:14 PM PDT 24
Finished Jun 04 01:36:49 PM PDT 24
Peak memory 199980 kb
Host smart-903fa70f-37f6-4665-a67a-6ed4a03f3031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431017060 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3431017060
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1371331320
Short name T90
Test name
Test status
Simulation time 81930515009 ps
CPU time 113.03 seconds
Started Jun 04 01:29:55 PM PDT 24
Finished Jun 04 01:31:49 PM PDT 24
Peak memory 192608 kb
Host smart-870b3768-76f1-452b-ac8c-f567416d6d57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371331320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1371331320
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3181731305
Short name T82
Test name
Test status
Simulation time 276802807937 ps
CPU time 793.08 seconds
Started Jun 04 01:29:38 PM PDT 24
Finished Jun 04 01:42:52 PM PDT 24
Peak memory 206992 kb
Host smart-d7dbfc84-c373-4f39-af2c-645e6ab08dd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181731305 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3181731305
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.456929022
Short name T14
Test name
Test status
Simulation time 4243256022 ps
CPU time 7.48 seconds
Started Jun 04 01:28:09 PM PDT 24
Finished Jun 04 01:28:17 PM PDT 24
Peak memory 215308 kb
Host smart-25417c47-605a-4c88-8fae-b4db300c1aed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456929022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.456929022
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1144545448
Short name T93
Test name
Test status
Simulation time 94531694397 ps
CPU time 244.66 seconds
Started Jun 04 01:29:55 PM PDT 24
Finished Jun 04 01:34:00 PM PDT 24
Peak memory 206884 kb
Host smart-4040b2ed-44f1-425c-801e-b5e1abc53613
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144545448 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1144545448
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2262812018
Short name T97
Test name
Test status
Simulation time 97386102784 ps
CPU time 160.11 seconds
Started Jun 04 01:29:13 PM PDT 24
Finished Jun 04 01:31:53 PM PDT 24
Peak memory 193100 kb
Host smart-2f5df82c-5bc3-4cb0-b520-769de89ebc6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262812018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2262812018
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2647260944
Short name T26
Test name
Test status
Simulation time 69163759602 ps
CPU time 677.23 seconds
Started Jun 04 01:28:13 PM PDT 24
Finished Jun 04 01:39:30 PM PDT 24
Peak memory 214096 kb
Host smart-dc86f38d-01e1-4a25-a048-2905eb447b92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647260944 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2647260944
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.266333928
Short name T92
Test name
Test status
Simulation time 96453903968 ps
CPU time 155.83 seconds
Started Jun 04 01:29:02 PM PDT 24
Finished Jun 04 01:31:39 PM PDT 24
Peak memory 193016 kb
Host smart-d6a6314f-7abf-4d0e-a426-6ce6aa2aed21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266333928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.266333928
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.319692719
Short name T119
Test name
Test status
Simulation time 192245714022 ps
CPU time 394.06 seconds
Started Jun 04 01:28:13 PM PDT 24
Finished Jun 04 01:34:48 PM PDT 24
Peak memory 202528 kb
Host smart-716b7aec-56ff-4089-b392-f094dfe776ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319692719 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.319692719
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1228899530
Short name T67
Test name
Test status
Simulation time 233544505784 ps
CPU time 666.48 seconds
Started Jun 04 01:29:30 PM PDT 24
Finished Jun 04 01:40:37 PM PDT 24
Peak memory 214316 kb
Host smart-d1301b26-ef8f-4516-acd7-d7411d2bde0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228899530 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1228899530
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3788846417
Short name T115
Test name
Test status
Simulation time 4562299410 ps
CPU time 6.62 seconds
Started Jun 04 01:29:00 PM PDT 24
Finished Jun 04 01:29:07 PM PDT 24
Peak memory 192372 kb
Host smart-87384bda-bd31-4734-b7e8-e99524ac8e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788846417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3788846417
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1652391683
Short name T120
Test name
Test status
Simulation time 117864181044 ps
CPU time 352.47 seconds
Started Jun 04 01:29:01 PM PDT 24
Finished Jun 04 01:34:54 PM PDT 24
Peak memory 210704 kb
Host smart-781a5821-042f-47ea-9b81-95a264e09468
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652391683 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1652391683
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3777258067
Short name T87
Test name
Test status
Simulation time 431154105476 ps
CPU time 316.94 seconds
Started Jun 04 01:30:02 PM PDT 24
Finished Jun 04 01:35:19 PM PDT 24
Peak memory 184360 kb
Host smart-006433b0-3651-4608-8dcf-4e9ca6f4974e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777258067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3777258067
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.4120667076
Short name T114
Test name
Test status
Simulation time 438305233106 ps
CPU time 298.01 seconds
Started Jun 04 01:28:24 PM PDT 24
Finished Jun 04 01:33:23 PM PDT 24
Peak memory 192420 kb
Host smart-ca9adab2-2ec8-4df2-b3e0-3a68cb97fc34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120667076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.4120667076
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.4262735822
Short name T102
Test name
Test status
Simulation time 43833906662 ps
CPU time 17.63 seconds
Started Jun 04 01:29:08 PM PDT 24
Finished Jun 04 01:29:26 PM PDT 24
Peak memory 191920 kb
Host smart-0076f447-3c1f-4d9b-8fd6-b460e725ed7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262735822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.4262735822
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.219529875
Short name T78
Test name
Test status
Simulation time 195413520115 ps
CPU time 372.86 seconds
Started Jun 04 01:30:02 PM PDT 24
Finished Jun 04 01:36:16 PM PDT 24
Peak memory 206836 kb
Host smart-dbc6cbd7-e017-4e96-b7b5-c9c058423708
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219529875 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.219529875
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2830115943
Short name T122
Test name
Test status
Simulation time 111630853012 ps
CPU time 39.82 seconds
Started Jun 04 01:28:28 PM PDT 24
Finished Jun 04 01:29:09 PM PDT 24
Peak memory 192420 kb
Host smart-f063a441-47a5-47fe-afc3-6563a7bdca20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830115943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2830115943
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1364192491
Short name T68
Test name
Test status
Simulation time 230780273399 ps
CPU time 333.52 seconds
Started Jun 04 01:29:07 PM PDT 24
Finished Jun 04 01:34:41 PM PDT 24
Peak memory 193084 kb
Host smart-8f5b6242-a3c8-4186-b559-0395228f5f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364192491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1364192491
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2735845531
Short name T118
Test name
Test status
Simulation time 5113385183 ps
CPU time 4.47 seconds
Started Jun 04 01:29:38 PM PDT 24
Finished Jun 04 01:29:43 PM PDT 24
Peak memory 192924 kb
Host smart-6cba96b6-017e-4329-8eb5-1210fbac2fb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735845531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2735845531
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1033595425
Short name T63
Test name
Test status
Simulation time 543416146 ps
CPU time 0.68 seconds
Started Jun 04 12:59:30 PM PDT 24
Finished Jun 04 12:59:31 PM PDT 24
Peak memory 192896 kb
Host smart-46583a2b-ed21-43fe-ab96-089480e96dda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033595425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1033595425
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3521072025
Short name T131
Test name
Test status
Simulation time 17333957890 ps
CPU time 184.27 seconds
Started Jun 04 01:29:08 PM PDT 24
Finished Jun 04 01:32:13 PM PDT 24
Peak memory 198616 kb
Host smart-8a62f419-0659-46cc-b3da-fff87a179c4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521072025 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3521072025
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3473394749
Short name T103
Test name
Test status
Simulation time 73874544273 ps
CPU time 31.4 seconds
Started Jun 04 01:29:29 PM PDT 24
Finished Jun 04 01:30:01 PM PDT 24
Peak memory 192340 kb
Host smart-fc554dfc-70e1-400c-aeb3-5bd8e9ff838d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473394749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3473394749
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3006816355
Short name T52
Test name
Test status
Simulation time 31334144947 ps
CPU time 48.1 seconds
Started Jun 04 01:29:46 PM PDT 24
Finished Jun 04 01:30:35 PM PDT 24
Peak memory 192404 kb
Host smart-e9e5694b-09bd-4440-993c-28653fad3db3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006816355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3006816355
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.29812572
Short name T132
Test name
Test status
Simulation time 135504330202 ps
CPU time 126.65 seconds
Started Jun 04 01:30:01 PM PDT 24
Finished Jun 04 01:32:08 PM PDT 24
Peak memory 199344 kb
Host smart-58a22236-7116-483e-a66d-acbfc24a590f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29812572 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.29812572
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3610658609
Short name T143
Test name
Test status
Simulation time 69641179206 ps
CPU time 766.16 seconds
Started Jun 04 01:28:52 PM PDT 24
Finished Jun 04 01:41:39 PM PDT 24
Peak memory 214456 kb
Host smart-3f142304-3035-4c6b-b19f-4ea56d637a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610658609 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3610658609
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3569077870
Short name T125
Test name
Test status
Simulation time 398051913183 ps
CPU time 591.35 seconds
Started Jun 04 01:29:04 PM PDT 24
Finished Jun 04 01:38:56 PM PDT 24
Peak memory 191924 kb
Host smart-97dd7706-8343-49c8-ad6c-700f753e6929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569077870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3569077870
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1022455162
Short name T110
Test name
Test status
Simulation time 46979201168 ps
CPU time 378.48 seconds
Started Jun 04 01:29:33 PM PDT 24
Finished Jun 04 01:35:52 PM PDT 24
Peak memory 199508 kb
Host smart-ca0b6afc-7148-4760-bea6-258369698b08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022455162 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1022455162
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1059237166
Short name T88
Test name
Test status
Simulation time 62803280336 ps
CPU time 24.52 seconds
Started Jun 04 01:30:19 PM PDT 24
Finished Jun 04 01:30:44 PM PDT 24
Peak memory 191900 kb
Host smart-c2d4f9c3-2c66-41db-8ed7-cf7a8bdc5fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059237166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1059237166
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1318488267
Short name T13
Test name
Test status
Simulation time 234770109301 ps
CPU time 447.21 seconds
Started Jun 04 01:28:53 PM PDT 24
Finished Jun 04 01:36:22 PM PDT 24
Peak memory 203052 kb
Host smart-69e0a367-b2b7-44b2-a785-876d78b661ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318488267 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1318488267
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1512106539
Short name T91
Test name
Test status
Simulation time 259371160681 ps
CPU time 183.05 seconds
Started Jun 04 01:29:02 PM PDT 24
Finished Jun 04 01:32:06 PM PDT 24
Peak memory 191916 kb
Host smart-7cd9d85e-b255-44f5-937b-5373ed512360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512106539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1512106539
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1295614797
Short name T155
Test name
Test status
Simulation time 47187466733 ps
CPU time 208.58 seconds
Started Jun 04 01:28:37 PM PDT 24
Finished Jun 04 01:32:06 PM PDT 24
Peak memory 198844 kb
Host smart-b6bcb1d1-4373-4ea8-957c-55088cfc295d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295614797 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1295614797
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.367733111
Short name T95
Test name
Test status
Simulation time 48585892104 ps
CPU time 20.34 seconds
Started Jun 04 01:28:43 PM PDT 24
Finished Jun 04 01:29:04 PM PDT 24
Peak memory 192932 kb
Host smart-f48944ff-f748-4828-bd6f-3a4c0ab56b1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367733111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.367733111
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1082805055
Short name T42
Test name
Test status
Simulation time 96239299596 ps
CPU time 111.11 seconds
Started Jun 04 01:28:45 PM PDT 24
Finished Jun 04 01:30:37 PM PDT 24
Peak memory 207224 kb
Host smart-75571dcc-2299-470b-9c70-c80d4476f764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082805055 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1082805055
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2868275045
Short name T47
Test name
Test status
Simulation time 258280056419 ps
CPU time 642.66 seconds
Started Jun 04 01:29:13 PM PDT 24
Finished Jun 04 01:39:57 PM PDT 24
Peak memory 214184 kb
Host smart-8b9d4bab-7f3c-4382-88f7-320cc496844c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868275045 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2868275045
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.4056161430
Short name T106
Test name
Test status
Simulation time 163573006552 ps
CPU time 30.63 seconds
Started Jun 04 01:29:54 PM PDT 24
Finished Jun 04 01:30:25 PM PDT 24
Peak memory 193016 kb
Host smart-a35f5e73-6ed6-4830-90f1-5dca18d3b2ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056161430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.4056161430
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1890521545
Short name T126
Test name
Test status
Simulation time 113948883430 ps
CPU time 38.64 seconds
Started Jun 04 01:30:04 PM PDT 24
Finished Jun 04 01:30:43 PM PDT 24
Peak memory 191916 kb
Host smart-16674c69-98f6-43b5-9b15-e28218be68b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890521545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1890521545
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3397510532
Short name T129
Test name
Test status
Simulation time 31489715491 ps
CPU time 133.13 seconds
Started Jun 04 01:28:29 PM PDT 24
Finished Jun 04 01:30:43 PM PDT 24
Peak memory 215016 kb
Host smart-2b3bab7c-cc5c-46e0-9cab-73476537e609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397510532 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3397510532
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.531061748
Short name T153
Test name
Test status
Simulation time 126544585595 ps
CPU time 535.21 seconds
Started Jun 04 01:28:54 PM PDT 24
Finished Jun 04 01:37:51 PM PDT 24
Peak memory 212240 kb
Host smart-beab4412-d1f0-4a26-91eb-62675bffd9b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531061748 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.531061748
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2994119369
Short name T156
Test name
Test status
Simulation time 18908845660 ps
CPU time 137.3 seconds
Started Jun 04 01:29:40 PM PDT 24
Finished Jun 04 01:31:58 PM PDT 24
Peak memory 206876 kb
Host smart-38430257-ad49-46c7-aa09-2a08a54b050c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994119369 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2994119369
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2840406961
Short name T77
Test name
Test status
Simulation time 116367086566 ps
CPU time 925.19 seconds
Started Jun 04 01:29:29 PM PDT 24
Finished Jun 04 01:44:55 PM PDT 24
Peak memory 214976 kb
Host smart-da4094a8-3ff7-4236-a26b-3eb9111dc696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840406961 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2840406961
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2971073674
Short name T85
Test name
Test status
Simulation time 377420391693 ps
CPU time 33.56 seconds
Started Jun 04 01:28:06 PM PDT 24
Finished Jun 04 01:28:40 PM PDT 24
Peak memory 192940 kb
Host smart-cb36a2ad-1ac4-4095-a7f5-2e23a6dcec5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971073674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2971073674
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3560599507
Short name T89
Test name
Test status
Simulation time 94066458027 ps
CPU time 34.11 seconds
Started Jun 04 01:28:43 PM PDT 24
Finished Jun 04 01:29:18 PM PDT 24
Peak memory 184120 kb
Host smart-7d67cd96-9abe-4c06-beaf-68221a9b3187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560599507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3560599507
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3448167054
Short name T76
Test name
Test status
Simulation time 34703731852 ps
CPU time 292.65 seconds
Started Jun 04 01:28:42 PM PDT 24
Finished Jun 04 01:33:35 PM PDT 24
Peak memory 198584 kb
Host smart-ac10e51b-b9f5-464a-b62a-b56503edd6ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448167054 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3448167054
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3789720053
Short name T148
Test name
Test status
Simulation time 72465850340 ps
CPU time 203.94 seconds
Started Jun 04 01:29:36 PM PDT 24
Finished Jun 04 01:33:01 PM PDT 24
Peak memory 207568 kb
Host smart-15822c79-7119-4f4e-9a6a-0de30ab44e29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789720053 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3789720053
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.645524373
Short name T11
Test name
Test status
Simulation time 201322790489 ps
CPU time 271.47 seconds
Started Jun 04 01:30:10 PM PDT 24
Finished Jun 04 01:34:42 PM PDT 24
Peak memory 192920 kb
Host smart-e52f74e5-ab8e-4f7d-9f53-9457b742fc2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645524373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.645524373
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.4007018612
Short name T154
Test name
Test status
Simulation time 168150566352 ps
CPU time 477.98 seconds
Started Jun 04 01:29:48 PM PDT 24
Finished Jun 04 01:37:47 PM PDT 24
Peak memory 211960 kb
Host smart-4e8a7af2-2296-4971-8a65-c0866966fe52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007018612 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.4007018612
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2954238201
Short name T109
Test name
Test status
Simulation time 174841827242 ps
CPU time 34.87 seconds
Started Jun 04 01:28:20 PM PDT 24
Finished Jun 04 01:28:56 PM PDT 24
Peak memory 193032 kb
Host smart-1b69c9a7-3347-4a49-9403-a8194a6256ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954238201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2954238201
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2013293038
Short name T50
Test name
Test status
Simulation time 183238409771 ps
CPU time 307.24 seconds
Started Jun 04 01:29:14 PM PDT 24
Finished Jun 04 01:34:22 PM PDT 24
Peak memory 192560 kb
Host smart-e57f936c-3894-48fd-8ea2-bf1fb52731e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013293038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2013293038
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2459789486
Short name T124
Test name
Test status
Simulation time 331694523186 ps
CPU time 133.5 seconds
Started Jun 04 01:29:22 PM PDT 24
Finished Jun 04 01:31:36 PM PDT 24
Peak memory 191916 kb
Host smart-3113dfd3-6b62-4e22-ba58-4ce5134b925e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459789486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2459789486
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.358310044
Short name T147
Test name
Test status
Simulation time 186184606029 ps
CPU time 287.93 seconds
Started Jun 04 01:28:22 PM PDT 24
Finished Jun 04 01:33:11 PM PDT 24
Peak memory 214308 kb
Host smart-e7d82f04-59c0-4906-8e93-7f85cf07ed44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358310044 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.358310044
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1654327428
Short name T54
Test name
Test status
Simulation time 58812679680 ps
CPU time 302.46 seconds
Started Jun 04 01:29:18 PM PDT 24
Finished Jun 04 01:34:21 PM PDT 24
Peak memory 199452 kb
Host smart-186941e0-da3c-43ad-8f99-7fb30fbc5742
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654327428 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1654327428
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2896792610
Short name T3
Test name
Test status
Simulation time 248205466054 ps
CPU time 480.49 seconds
Started Jun 04 01:29:47 PM PDT 24
Finished Jun 04 01:37:49 PM PDT 24
Peak memory 214088 kb
Host smart-70218ae3-9c9f-4ece-9d5f-bfe3a8fcbaa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896792610 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2896792610
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1305292481
Short name T116
Test name
Test status
Simulation time 428952719 ps
CPU time 0.74 seconds
Started Jun 04 01:28:44 PM PDT 24
Finished Jun 04 01:28:45 PM PDT 24
Peak memory 196432 kb
Host smart-669322da-87da-42a0-a4cf-6616c511b628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305292481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1305292481
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2921120402
Short name T29
Test name
Test status
Simulation time 244627908689 ps
CPU time 85.05 seconds
Started Jun 04 01:29:01 PM PDT 24
Finished Jun 04 01:30:26 PM PDT 24
Peak memory 191884 kb
Host smart-00a8474b-45b8-49c2-b2d5-f14ee62b56a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921120402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2921120402
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1179490110
Short name T108
Test name
Test status
Simulation time 96386410651 ps
CPU time 153.86 seconds
Started Jun 04 01:29:08 PM PDT 24
Finished Jun 04 01:31:43 PM PDT 24
Peak memory 192948 kb
Host smart-d86f4086-9fa0-45a3-8d00-2f7eabe7cc7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179490110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1179490110
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1291506585
Short name T96
Test name
Test status
Simulation time 495289684 ps
CPU time 1.42 seconds
Started Jun 04 01:29:08 PM PDT 24
Finished Jun 04 01:29:11 PM PDT 24
Peak memory 196504 kb
Host smart-fb6dbe3a-9c4d-4013-ba57-9ec23f1aa6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291506585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1291506585
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.640820234
Short name T163
Test name
Test status
Simulation time 425302144039 ps
CPU time 168.34 seconds
Started Jun 04 01:28:36 PM PDT 24
Finished Jun 04 01:31:25 PM PDT 24
Peak memory 191932 kb
Host smart-e57899fa-d503-4953-8236-d1b2f953937f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640820234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.640820234
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3940978954
Short name T83
Test name
Test status
Simulation time 639041086 ps
CPU time 0.81 seconds
Started Jun 04 01:28:55 PM PDT 24
Finished Jun 04 01:28:57 PM PDT 24
Peak memory 196344 kb
Host smart-7916dbd1-55a6-454d-9c58-3f51a436e3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940978954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3940978954
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.4149859945
Short name T139
Test name
Test status
Simulation time 461009951 ps
CPU time 0.7 seconds
Started Jun 04 01:29:01 PM PDT 24
Finished Jun 04 01:29:02 PM PDT 24
Peak memory 196492 kb
Host smart-975e5a7d-22f0-4bd0-b98f-ebf3b84dd0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149859945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.4149859945
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1350083787
Short name T24
Test name
Test status
Simulation time 98554665892 ps
CPU time 69.76 seconds
Started Jun 04 01:28:24 PM PDT 24
Finished Jun 04 01:29:35 PM PDT 24
Peak memory 184312 kb
Host smart-1684c2db-2146-437a-8e78-ad8a4d9ad41f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350083787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1350083787
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2320386501
Short name T159
Test name
Test status
Simulation time 336650895759 ps
CPU time 524.06 seconds
Started Jun 04 01:29:37 PM PDT 24
Finished Jun 04 01:38:22 PM PDT 24
Peak memory 192404 kb
Host smart-349e10d2-b170-42d3-a3aa-803101afb5c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320386501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2320386501
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2776355393
Short name T142
Test name
Test status
Simulation time 246456006214 ps
CPU time 53.57 seconds
Started Jun 04 01:29:47 PM PDT 24
Finished Jun 04 01:30:42 PM PDT 24
Peak memory 192584 kb
Host smart-ab80df58-f3f0-4c65-861a-b5b92b7f4464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776355393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2776355393
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2488437080
Short name T162
Test name
Test status
Simulation time 196543707020 ps
CPU time 70.76 seconds
Started Jun 04 01:30:00 PM PDT 24
Finished Jun 04 01:31:11 PM PDT 24
Peak memory 192492 kb
Host smart-478ea83a-c4f1-4a3d-a24b-0031f1811c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488437080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2488437080
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3829380048
Short name T10
Test name
Test status
Simulation time 613255487 ps
CPU time 0.83 seconds
Started Jun 04 01:30:09 PM PDT 24
Finished Jun 04 01:30:11 PM PDT 24
Peak memory 196504 kb
Host smart-a85d4c57-9eef-4c38-b88d-c6a141c24e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829380048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3829380048
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3146887674
Short name T144
Test name
Test status
Simulation time 458419062 ps
CPU time 0.73 seconds
Started Jun 04 01:30:16 PM PDT 24
Finished Jun 04 01:30:18 PM PDT 24
Peak memory 196448 kb
Host smart-dc4e8dfc-e839-4399-889a-2b583bc45108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146887674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3146887674
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2355452488
Short name T121
Test name
Test status
Simulation time 548465440 ps
CPU time 0.87 seconds
Started Jun 04 01:30:16 PM PDT 24
Finished Jun 04 01:30:18 PM PDT 24
Peak memory 196528 kb
Host smart-1d4ca1fb-8113-4d64-8d23-c0273a41de2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355452488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2355452488
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1971813062
Short name T45
Test name
Test status
Simulation time 356780191 ps
CPU time 1.2 seconds
Started Jun 04 01:28:22 PM PDT 24
Finished Jun 04 01:28:24 PM PDT 24
Peak memory 196428 kb
Host smart-18e14073-6d92-4a00-8866-0121b0613858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971813062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1971813062
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1667975890
Short name T151
Test name
Test status
Simulation time 153466941636 ps
CPU time 73.96 seconds
Started Jun 04 01:28:54 PM PDT 24
Finished Jun 04 01:30:09 PM PDT 24
Peak memory 192616 kb
Host smart-7aaea155-1cb6-4f2f-a8a4-a8e5b94871c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667975890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1667975890
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2419028921
Short name T84
Test name
Test status
Simulation time 157231381344 ps
CPU time 65.38 seconds
Started Jun 04 01:29:22 PM PDT 24
Finished Jun 04 01:30:28 PM PDT 24
Peak memory 192956 kb
Host smart-a3ddd620-c106-4ffd-a5fc-e684a030885c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419028921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2419028921
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.4016460041
Short name T117
Test name
Test status
Simulation time 366235646 ps
CPU time 1.03 seconds
Started Jun 04 01:30:02 PM PDT 24
Finished Jun 04 01:30:04 PM PDT 24
Peak memory 196404 kb
Host smart-b1de119b-dd62-423f-b952-fb260c21acc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016460041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.4016460041
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2000237577
Short name T128
Test name
Test status
Simulation time 520972485 ps
CPU time 0.72 seconds
Started Jun 04 01:28:44 PM PDT 24
Finished Jun 04 01:28:45 PM PDT 24
Peak memory 196468 kb
Host smart-de37b2b9-a1de-4e43-9a17-ab33c51fd3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000237577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2000237577
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3679909103
Short name T113
Test name
Test status
Simulation time 76603573351 ps
CPU time 102.48 seconds
Started Jun 04 01:28:44 PM PDT 24
Finished Jun 04 01:30:27 PM PDT 24
Peak memory 184064 kb
Host smart-114ae693-d8c0-4e21-a4dd-35257ec8ea0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679909103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3679909103
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3861771704
Short name T127
Test name
Test status
Simulation time 387707598 ps
CPU time 0.69 seconds
Started Jun 04 01:28:06 PM PDT 24
Finished Jun 04 01:28:08 PM PDT 24
Peak memory 196332 kb
Host smart-285db3d1-7e55-41de-bc14-1d5a45147a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861771704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3861771704
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2376494148
Short name T8
Test name
Test status
Simulation time 501990098 ps
CPU time 0.79 seconds
Started Jun 04 01:28:59 PM PDT 24
Finished Jun 04 01:29:01 PM PDT 24
Peak memory 196460 kb
Host smart-4da136e5-2ba1-4760-8ca7-8af48e439631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376494148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2376494148
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2074882003
Short name T138
Test name
Test status
Simulation time 486360855 ps
CPU time 0.78 seconds
Started Jun 04 01:29:12 PM PDT 24
Finished Jun 04 01:29:13 PM PDT 24
Peak memory 196464 kb
Host smart-ddae0b10-9f0c-4981-b651-19e1a4186dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074882003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2074882003
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3120133828
Short name T161
Test name
Test status
Simulation time 55871464449 ps
CPU time 92.37 seconds
Started Jun 04 01:29:13 PM PDT 24
Finished Jun 04 01:30:45 PM PDT 24
Peak memory 191880 kb
Host smart-91c10169-0005-45ae-82ff-d9f847943557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120133828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3120133828
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.555178978
Short name T104
Test name
Test status
Simulation time 421058555 ps
CPU time 1.21 seconds
Started Jun 04 01:29:28 PM PDT 24
Finished Jun 04 01:29:30 PM PDT 24
Peak memory 196548 kb
Host smart-e76cd09c-11d0-4881-8c69-4dc87052e8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555178978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.555178978
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2637751946
Short name T141
Test name
Test status
Simulation time 426445192 ps
CPU time 0.93 seconds
Started Jun 04 01:28:13 PM PDT 24
Finished Jun 04 01:28:14 PM PDT 24
Peak memory 196444 kb
Host smart-3aad4d24-577e-4cab-a014-6ceb93a02935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637751946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2637751946
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1567102888
Short name T100
Test name
Test status
Simulation time 463857419 ps
CPU time 0.97 seconds
Started Jun 04 01:29:30 PM PDT 24
Finished Jun 04 01:29:31 PM PDT 24
Peak memory 196440 kb
Host smart-bbc752e5-3b0e-4856-a5d5-d4a36e670b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567102888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1567102888
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3314364198
Short name T135
Test name
Test status
Simulation time 499797290 ps
CPU time 1.3 seconds
Started Jun 04 01:29:29 PM PDT 24
Finished Jun 04 01:29:30 PM PDT 24
Peak memory 196428 kb
Host smart-7e29ed12-d946-425d-8386-906cc2fdae5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314364198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3314364198
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2323247902
Short name T130
Test name
Test status
Simulation time 395331782 ps
CPU time 1.23 seconds
Started Jun 04 01:29:37 PM PDT 24
Finished Jun 04 01:29:39 PM PDT 24
Peak memory 196512 kb
Host smart-cfd96dc0-fd10-411a-ac12-cc56825adb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323247902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2323247902
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2548027010
Short name T105
Test name
Test status
Simulation time 382729060 ps
CPU time 0.86 seconds
Started Jun 04 01:28:20 PM PDT 24
Finished Jun 04 01:28:22 PM PDT 24
Peak memory 196436 kb
Host smart-dbe5244a-263d-4cdc-be4a-86a8a95b0d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548027010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2548027010
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4058720534
Short name T137
Test name
Test status
Simulation time 358435846 ps
CPU time 0.71 seconds
Started Jun 04 01:29:53 PM PDT 24
Finished Jun 04 01:29:55 PM PDT 24
Peak memory 196448 kb
Host smart-6e7706a7-e6bf-4fc1-8e69-8f11a34ea8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058720534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4058720534
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4205360824
Short name T51
Test name
Test status
Simulation time 325282446252 ps
CPU time 252.03 seconds
Started Jun 04 01:29:53 PM PDT 24
Finished Jun 04 01:34:06 PM PDT 24
Peak memory 207072 kb
Host smart-0f483ad5-6368-44f1-bb67-ea3c8410c3e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205360824 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.4205360824
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.4105222613
Short name T133
Test name
Test status
Simulation time 461398239 ps
CPU time 0.72 seconds
Started Jun 04 01:28:30 PM PDT 24
Finished Jun 04 01:28:31 PM PDT 24
Peak memory 196460 kb
Host smart-e8346ba4-897e-4116-9c4a-c8ebd36c0fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105222613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.4105222613
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.225501088
Short name T25
Test name
Test status
Simulation time 419041761 ps
CPU time 1.21 seconds
Started Jun 04 01:28:29 PM PDT 24
Finished Jun 04 01:28:31 PM PDT 24
Peak memory 196496 kb
Host smart-5b8303de-39e8-4973-99bf-51a3f928bfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225501088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.225501088
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1313957600
Short name T1
Test name
Test status
Simulation time 184350463661 ps
CPU time 301.74 seconds
Started Jun 04 01:28:08 PM PDT 24
Finished Jun 04 01:33:11 PM PDT 24
Peak memory 191912 kb
Host smart-71a7c453-bc1a-402b-a36b-db04af864a69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313957600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1313957600
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1000980345
Short name T94
Test name
Test status
Simulation time 565890179 ps
CPU time 1.04 seconds
Started Jun 04 01:28:54 PM PDT 24
Finished Jun 04 01:28:56 PM PDT 24
Peak memory 196452 kb
Host smart-1ffd998e-25e1-4523-a442-66544012ab0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000980345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1000980345
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1330009989
Short name T111
Test name
Test status
Simulation time 78506558932 ps
CPU time 122.34 seconds
Started Jun 04 01:29:21 PM PDT 24
Finished Jun 04 01:31:25 PM PDT 24
Peak memory 198228 kb
Host smart-c106dacb-1594-4bcb-b511-ea053f299cbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330009989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1330009989
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2450220564
Short name T107
Test name
Test status
Simulation time 37078909975 ps
CPU time 13.69 seconds
Started Jun 04 01:29:49 PM PDT 24
Finished Jun 04 01:30:03 PM PDT 24
Peak memory 192544 kb
Host smart-9e518d0c-6d29-42c1-8f21-778921dc493f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450220564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2450220564
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.4149806662
Short name T123
Test name
Test status
Simulation time 447040489 ps
CPU time 0.77 seconds
Started Jun 04 01:28:07 PM PDT 24
Finished Jun 04 01:28:09 PM PDT 24
Peak memory 196516 kb
Host smart-ce4e10ec-c21d-4bef-857d-ba0e02428860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149806662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.4149806662
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2164229584
Short name T145
Test name
Test status
Simulation time 518483027 ps
CPU time 1.34 seconds
Started Jun 04 01:28:44 PM PDT 24
Finished Jun 04 01:28:46 PM PDT 24
Peak memory 196432 kb
Host smart-c33f3bbe-be87-4456-9adf-8d6a3ec77809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164229584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2164229584
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1182182314
Short name T112
Test name
Test status
Simulation time 488601546 ps
CPU time 0.73 seconds
Started Jun 04 01:29:00 PM PDT 24
Finished Jun 04 01:29:01 PM PDT 24
Peak memory 196424 kb
Host smart-50e230b1-2ace-49b6-8fe1-9b4e8805130d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182182314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1182182314
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2548546035
Short name T168
Test name
Test status
Simulation time 418381798877 ps
CPU time 156.38 seconds
Started Jun 04 01:28:13 PM PDT 24
Finished Jun 04 01:30:50 PM PDT 24
Peak memory 191920 kb
Host smart-063f4196-04c7-4dbd-b99b-cbe79c059f7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548546035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2548546035
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.722039040
Short name T40
Test name
Test status
Simulation time 243617791226 ps
CPU time 510.75 seconds
Started Jun 04 01:29:06 PM PDT 24
Finished Jun 04 01:37:38 PM PDT 24
Peak memory 206892 kb
Host smart-7fcebbbf-a35f-4f3b-a3cd-2def7adc89cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722039040 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.722039040
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.495150764
Short name T101
Test name
Test status
Simulation time 503869190 ps
CPU time 0.75 seconds
Started Jun 04 01:29:08 PM PDT 24
Finished Jun 04 01:29:10 PM PDT 24
Peak memory 196428 kb
Host smart-a1bd9831-ef9d-4567-8def-0ad286a7aa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495150764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.495150764
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3768207357
Short name T79
Test name
Test status
Simulation time 82170430577 ps
CPU time 169.53 seconds
Started Jun 04 01:29:30 PM PDT 24
Finished Jun 04 01:32:21 PM PDT 24
Peak memory 199708 kb
Host smart-e2f0a1b0-b6b5-4e63-97f9-cc7fddb6fa87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768207357 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3768207357
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1890460249
Short name T98
Test name
Test status
Simulation time 356430936 ps
CPU time 0.87 seconds
Started Jun 04 01:29:46 PM PDT 24
Finished Jun 04 01:29:47 PM PDT 24
Peak memory 196516 kb
Host smart-c53f0153-4b78-4fcd-b556-819719e5c591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890460249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1890460249
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3124305758
Short name T150
Test name
Test status
Simulation time 226801033777 ps
CPU time 494.93 seconds
Started Jun 04 01:30:03 PM PDT 24
Finished Jun 04 01:38:18 PM PDT 24
Peak memory 211656 kb
Host smart-dea20566-76c5-43c8-ba17-420caf7cb618
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124305758 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3124305758
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.4251885609
Short name T19
Test name
Test status
Simulation time 505535738 ps
CPU time 0.88 seconds
Started Jun 04 01:28:16 PM PDT 24
Finished Jun 04 01:28:18 PM PDT 24
Peak memory 196432 kb
Host smart-f175ce96-85a8-4018-95db-27648189b7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251885609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4251885609
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.647276083
Short name T140
Test name
Test status
Simulation time 501413702 ps
CPU time 1.24 seconds
Started Jun 04 01:29:16 PM PDT 24
Finished Jun 04 01:29:18 PM PDT 24
Peak memory 196440 kb
Host smart-6b41e4fa-7841-43fd-a497-de2573fa6c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647276083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.647276083
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3498099128
Short name T170
Test name
Test status
Simulation time 594238892 ps
CPU time 1.02 seconds
Started Jun 04 01:29:37 PM PDT 24
Finished Jun 04 01:29:39 PM PDT 24
Peak memory 196368 kb
Host smart-06bd146c-a71b-4604-b263-92f26122a26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498099128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3498099128
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2420358368
Short name T171
Test name
Test status
Simulation time 61451404066 ps
CPU time 48.78 seconds
Started Jun 04 01:29:37 PM PDT 24
Finished Jun 04 01:30:26 PM PDT 24
Peak memory 191932 kb
Host smart-4026b4a6-4d85-48b7-a042-1b63d710b185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420358368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2420358368
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.510978496
Short name T80
Test name
Test status
Simulation time 19526921566 ps
CPU time 136.49 seconds
Started Jun 04 01:29:47 PM PDT 24
Finished Jun 04 01:32:04 PM PDT 24
Peak memory 206876 kb
Host smart-9690ce64-e8d4-4817-8f31-2d7aca02e62d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510978496 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.510978496
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3013006565
Short name T149
Test name
Test status
Simulation time 123850927924 ps
CPU time 683.49 seconds
Started Jun 04 01:30:11 PM PDT 24
Finished Jun 04 01:41:35 PM PDT 24
Peak memory 214744 kb
Host smart-9abb1982-6ea1-4861-b0f7-68c6e8edb5c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013006565 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3013006565
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1097339278
Short name T182
Test name
Test status
Simulation time 8220213073 ps
CPU time 4.76 seconds
Started Jun 04 12:59:36 PM PDT 24
Finished Jun 04 12:59:43 PM PDT 24
Peak memory 197988 kb
Host smart-926fe6f5-c85e-409f-ad60-8050c5670c94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097339278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1097339278
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1815386968
Short name T172
Test name
Test status
Simulation time 47161997386 ps
CPU time 295.02 seconds
Started Jun 04 01:29:00 PM PDT 24
Finished Jun 04 01:33:56 PM PDT 24
Peak memory 207120 kb
Host smart-8d5ed430-7552-40fd-b4b8-10c70f95e42f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815386968 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1815386968
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.591005755
Short name T53
Test name
Test status
Simulation time 572673551 ps
CPU time 0.72 seconds
Started Jun 04 01:29:03 PM PDT 24
Finished Jun 04 01:29:04 PM PDT 24
Peak memory 196484 kb
Host smart-d2e617a6-7496-435c-8eeb-f086b089111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591005755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.591005755
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3014089800
Short name T9
Test name
Test status
Simulation time 457701521 ps
CPU time 1.2 seconds
Started Jun 04 01:29:14 PM PDT 24
Finished Jun 04 01:29:16 PM PDT 24
Peak memory 196368 kb
Host smart-39957ec9-5517-427e-b622-47d9518b2110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014089800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3014089800
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1109251937
Short name T173
Test name
Test status
Simulation time 554167923 ps
CPU time 0.84 seconds
Started Jun 04 01:29:22 PM PDT 24
Finished Jun 04 01:29:23 PM PDT 24
Peak memory 196432 kb
Host smart-f85db0a9-2d2f-4589-95e9-bae7067b395d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109251937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1109251937
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.4121812505
Short name T165
Test name
Test status
Simulation time 86093233775 ps
CPU time 164.65 seconds
Started Jun 04 01:29:20 PM PDT 24
Finished Jun 04 01:32:06 PM PDT 24
Peak memory 208044 kb
Host smart-fbf13da0-495a-437f-84ea-699f783beba9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121812505 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.4121812505
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2972975697
Short name T27
Test name
Test status
Simulation time 636528302 ps
CPU time 0.76 seconds
Started Jun 04 01:29:29 PM PDT 24
Finished Jun 04 01:29:31 PM PDT 24
Peak memory 196504 kb
Host smart-da5ad53b-2001-49b9-aa52-ab87a8126caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972975697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2972975697
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.935955745
Short name T167
Test name
Test status
Simulation time 459965540 ps
CPU time 1.28 seconds
Started Jun 04 01:29:47 PM PDT 24
Finished Jun 04 01:29:49 PM PDT 24
Peak memory 196380 kb
Host smart-21792cb8-ed8b-4bd7-8044-15585a69d227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935955745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.935955745
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1172475169
Short name T28
Test name
Test status
Simulation time 510829642 ps
CPU time 0.75 seconds
Started Jun 04 01:29:48 PM PDT 24
Finished Jun 04 01:29:49 PM PDT 24
Peak memory 196528 kb
Host smart-09645add-46dd-4f9f-9972-2cc8ddb95c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172475169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1172475169
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.53982136
Short name T174
Test name
Test status
Simulation time 613336539 ps
CPU time 1.54 seconds
Started Jun 04 01:29:53 PM PDT 24
Finished Jun 04 01:29:55 PM PDT 24
Peak memory 196500 kb
Host smart-dc5827b8-4b9a-411e-be01-575a624e383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53982136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.53982136
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2462189776
Short name T146
Test name
Test status
Simulation time 216110463573 ps
CPU time 306.49 seconds
Started Jun 04 01:30:10 PM PDT 24
Finished Jun 04 01:35:17 PM PDT 24
Peak memory 191880 kb
Host smart-8c8b2c65-a4ec-4aa7-9ba5-d7834e87772f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462189776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2462189776
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3290507596
Short name T160
Test name
Test status
Simulation time 78855783833 ps
CPU time 54.34 seconds
Started Jun 04 01:28:29 PM PDT 24
Finished Jun 04 01:29:24 PM PDT 24
Peak memory 191932 kb
Host smart-568fb3ca-e027-485a-965f-a8529be89382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290507596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3290507596
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1657523111
Short name T134
Test name
Test status
Simulation time 140770058770 ps
CPU time 56.58 seconds
Started Jun 04 01:28:53 PM PDT 24
Finished Jun 04 01:29:50 PM PDT 24
Peak memory 191928 kb
Host smart-7d06ebaa-0163-4c41-89d0-85a57cc4fd13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657523111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1657523111
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3806971523
Short name T177
Test name
Test status
Simulation time 444708516 ps
CPU time 1.04 seconds
Started Jun 04 01:29:07 PM PDT 24
Finished Jun 04 01:29:09 PM PDT 24
Peak memory 196416 kb
Host smart-75e1d9c6-0203-4ed3-9d55-6e263a4bee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806971523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3806971523
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2767441563
Short name T158
Test name
Test status
Simulation time 450081423 ps
CPU time 1.14 seconds
Started Jun 04 01:29:21 PM PDT 24
Finished Jun 04 01:29:23 PM PDT 24
Peak memory 196496 kb
Host smart-f85c08d5-2580-45be-9a14-8a1ef34adb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767441563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2767441563
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.438502976
Short name T136
Test name
Test status
Simulation time 452884331 ps
CPU time 0.93 seconds
Started Jun 04 01:29:20 PM PDT 24
Finished Jun 04 01:29:22 PM PDT 24
Peak memory 196428 kb
Host smart-95f0d9c0-8e5e-49eb-84e6-9b5758b1ee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438502976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.438502976
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.4260946896
Short name T81
Test name
Test status
Simulation time 32045693666 ps
CPU time 229.59 seconds
Started Jun 04 01:29:23 PM PDT 24
Finished Jun 04 01:33:13 PM PDT 24
Peak memory 206872 kb
Host smart-4364765a-fd89-4f69-8660-6b1016adda98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260946896 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.4260946896
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3847846731
Short name T157
Test name
Test status
Simulation time 408028331 ps
CPU time 1.19 seconds
Started Jun 04 01:30:02 PM PDT 24
Finished Jun 04 01:30:04 PM PDT 24
Peak memory 196488 kb
Host smart-b43bda4f-bed0-4e27-8371-0207628f1c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847846731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3847846731
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2914813359
Short name T166
Test name
Test status
Simulation time 344323631 ps
CPU time 1.12 seconds
Started Jun 04 01:30:02 PM PDT 24
Finished Jun 04 01:30:04 PM PDT 24
Peak memory 196396 kb
Host smart-4bbaa3f9-8539-4386-b899-e2e79ded8025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914813359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2914813359
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.460590690
Short name T41
Test name
Test status
Simulation time 86209921834 ps
CPU time 653.69 seconds
Started Jun 04 01:30:04 PM PDT 24
Finished Jun 04 01:40:58 PM PDT 24
Peak memory 214800 kb
Host smart-ccd231d9-4bcd-4726-9671-3bdb24959c12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460590690 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.460590690
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1695436311
Short name T169
Test name
Test status
Simulation time 526435375 ps
CPU time 1.03 seconds
Started Jun 04 01:30:09 PM PDT 24
Finished Jun 04 01:30:11 PM PDT 24
Peak memory 196412 kb
Host smart-c619d26e-2eb6-4e2c-a755-4eef60e1c656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695436311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1695436311
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1343409288
Short name T178
Test name
Test status
Simulation time 623730209 ps
CPU time 0.82 seconds
Started Jun 04 01:28:36 PM PDT 24
Finished Jun 04 01:28:38 PM PDT 24
Peak memory 196420 kb
Host smart-a28df6a2-2b06-4417-bf0d-764d90127582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343409288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1343409288
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2686091751
Short name T164
Test name
Test status
Simulation time 159745230326 ps
CPU time 346.91 seconds
Started Jun 04 01:28:41 PM PDT 24
Finished Jun 04 01:34:29 PM PDT 24
Peak memory 214940 kb
Host smart-dfb70990-a96d-4113-9a66-2eef9ab3af33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686091751 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2686091751
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4154342044
Short name T38
Test name
Test status
Simulation time 705970134 ps
CPU time 0.95 seconds
Started Jun 04 12:59:12 PM PDT 24
Finished Jun 04 12:59:15 PM PDT 24
Peak memory 183652 kb
Host smart-3c7a4d88-4439-46fc-90c0-1d4d088f24bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154342044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4154342044
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2784225536
Short name T66
Test name
Test status
Simulation time 10179182277 ps
CPU time 5.72 seconds
Started Jun 04 12:59:12 PM PDT 24
Finished Jun 04 12:59:19 PM PDT 24
Peak memory 192080 kb
Host smart-4be1a0a0-c7ed-4349-8b8e-c339fcbb5579
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784225536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2784225536
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1400489980
Short name T353
Test name
Test status
Simulation time 873299244 ps
CPU time 0.74 seconds
Started Jun 04 12:59:12 PM PDT 24
Finished Jun 04 12:59:14 PM PDT 24
Peak memory 183604 kb
Host smart-d005d44c-8d13-4658-984c-4934387dce0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400489980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1400489980
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1253939925
Short name T394
Test name
Test status
Simulation time 413114656 ps
CPU time 1.33 seconds
Started Jun 04 12:59:11 PM PDT 24
Finished Jun 04 12:59:14 PM PDT 24
Peak memory 196168 kb
Host smart-83c89eaa-223e-43e5-a069-a0bb515c637c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253939925 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1253939925
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3316665595
Short name T61
Test name
Test status
Simulation time 570186417 ps
CPU time 0.75 seconds
Started Jun 04 12:59:13 PM PDT 24
Finished Jun 04 12:59:15 PM PDT 24
Peak memory 183700 kb
Host smart-73b8389d-befc-4057-861a-17ad7a0f43ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316665595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3316665595
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2922249533
Short name T373
Test name
Test status
Simulation time 408336941 ps
CPU time 1.09 seconds
Started Jun 04 12:59:15 PM PDT 24
Finished Jun 04 12:59:17 PM PDT 24
Peak memory 183536 kb
Host smart-627bf369-6d1c-4a78-b7ff-791c5864e0e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922249533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2922249533
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3212932121
Short name T295
Test name
Test status
Simulation time 432600635 ps
CPU time 1.07 seconds
Started Jun 04 12:59:12 PM PDT 24
Finished Jun 04 12:59:15 PM PDT 24
Peak memory 183540 kb
Host smart-d144cbc9-9689-4c06-9cf8-28a5081359a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212932121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3212932121
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2095487290
Short name T294
Test name
Test status
Simulation time 555222810 ps
CPU time 0.58 seconds
Started Jun 04 12:59:14 PM PDT 24
Finished Jun 04 12:59:15 PM PDT 24
Peak memory 183528 kb
Host smart-0a42b335-1c60-459d-a5dd-0e1daf3df3c7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095487290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2095487290
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.170653762
Short name T72
Test name
Test status
Simulation time 1250773909 ps
CPU time 1.07 seconds
Started Jun 04 12:59:13 PM PDT 24
Finished Jun 04 12:59:15 PM PDT 24
Peak memory 183852 kb
Host smart-a65da2f5-857a-4e7a-a08f-c0524fdb576f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170653762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.170653762
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2768212728
Short name T299
Test name
Test status
Simulation time 710156024 ps
CPU time 1.95 seconds
Started Jun 04 12:59:08 PM PDT 24
Finished Jun 04 12:59:11 PM PDT 24
Peak memory 198360 kb
Host smart-4e94cc92-c7a9-4e17-9980-f12baacdca93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768212728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2768212728
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1077111422
Short name T404
Test name
Test status
Simulation time 4065193263 ps
CPU time 7.56 seconds
Started Jun 04 12:59:13 PM PDT 24
Finished Jun 04 12:59:22 PM PDT 24
Peak memory 197768 kb
Host smart-f6a06301-5b61-4934-8949-a89cf8e35b95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077111422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1077111422
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3878158981
Short name T317
Test name
Test status
Simulation time 479850262 ps
CPU time 1.71 seconds
Started Jun 04 12:59:18 PM PDT 24
Finished Jun 04 12:59:20 PM PDT 24
Peak memory 192984 kb
Host smart-3cc5bca5-6ad8-4401-9158-ab4a76117efc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878158981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3878158981
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3142820442
Short name T57
Test name
Test status
Simulation time 10227649249 ps
CPU time 21.31 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:41 PM PDT 24
Peak memory 192064 kb
Host smart-39f68b8c-a890-4c87-92e2-62ce262d1ab3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142820442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3142820442
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2682712680
Short name T360
Test name
Test status
Simulation time 1356274406 ps
CPU time 1.08 seconds
Started Jun 04 12:59:13 PM PDT 24
Finished Jun 04 12:59:15 PM PDT 24
Peak memory 192916 kb
Host smart-c2dc0540-d321-4b1c-b7d6-a741cfd34cb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682712680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2682712680
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.459152212
Short name T388
Test name
Test status
Simulation time 574814131 ps
CPU time 0.93 seconds
Started Jun 04 12:59:17 PM PDT 24
Finished Jun 04 12:59:18 PM PDT 24
Peak memory 196772 kb
Host smart-0fbcb60c-6ed3-494f-b4f4-c15adccf6bdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459152212 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.459152212
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3943759317
Short name T361
Test name
Test status
Simulation time 317119050 ps
CPU time 0.8 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:21 PM PDT 24
Peak memory 183884 kb
Host smart-fcf5fb1f-e7d8-4aec-b2fc-dced7731a735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943759317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3943759317
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.587453262
Short name T337
Test name
Test status
Simulation time 434542157 ps
CPU time 0.86 seconds
Started Jun 04 12:59:12 PM PDT 24
Finished Jun 04 12:59:14 PM PDT 24
Peak memory 183568 kb
Host smart-70d79ad7-8b28-45cf-aba2-6a999b6fbb4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587453262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.587453262
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3469341102
Short name T411
Test name
Test status
Simulation time 488007049 ps
CPU time 0.64 seconds
Started Jun 04 12:59:11 PM PDT 24
Finished Jun 04 12:59:14 PM PDT 24
Peak memory 183412 kb
Host smart-2b0fd9f8-7d36-49b9-874a-40fb2845a7c2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469341102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3469341102
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3720447630
Short name T308
Test name
Test status
Simulation time 478531693 ps
CPU time 1.31 seconds
Started Jun 04 12:59:14 PM PDT 24
Finished Jun 04 12:59:17 PM PDT 24
Peak memory 183536 kb
Host smart-81751a04-eefa-4a0d-9cc7-954ec2f2be5b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720447630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3720447630
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4054282264
Short name T348
Test name
Test status
Simulation time 1498555664 ps
CPU time 3.6 seconds
Started Jun 04 12:59:22 PM PDT 24
Finished Jun 04 12:59:27 PM PDT 24
Peak memory 193320 kb
Host smart-90489bbf-9ab9-4dfe-9b01-449411d4a419
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054282264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.4054282264
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1090699941
Short name T372
Test name
Test status
Simulation time 555106453 ps
CPU time 2.36 seconds
Started Jun 04 12:59:15 PM PDT 24
Finished Jun 04 12:59:18 PM PDT 24
Peak memory 198380 kb
Host smart-7b34d9d5-eb71-4487-8f84-04b20c58937e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090699941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1090699941
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4217855513
Short name T402
Test name
Test status
Simulation time 446176066 ps
CPU time 1.34 seconds
Started Jun 04 12:59:29 PM PDT 24
Finished Jun 04 12:59:31 PM PDT 24
Peak memory 195828 kb
Host smart-354498bf-dd4f-4309-8ebc-c0d28ad9621f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217855513 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.4217855513
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3026813069
Short name T279
Test name
Test status
Simulation time 374910560 ps
CPU time 0.83 seconds
Started Jun 04 12:59:34 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 183576 kb
Host smart-ab987ac2-53a0-4b9f-b1bc-fc18a3a13d2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026813069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3026813069
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3941570362
Short name T333
Test name
Test status
Simulation time 2247520380 ps
CPU time 3.66 seconds
Started Jun 04 12:59:32 PM PDT 24
Finished Jun 04 12:59:38 PM PDT 24
Peak memory 191900 kb
Host smart-c5a6a813-8431-40d7-a135-b3bd19e9a336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941570362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3941570362
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4175681903
Short name T400
Test name
Test status
Simulation time 1330734698 ps
CPU time 2.23 seconds
Started Jun 04 12:59:26 PM PDT 24
Finished Jun 04 12:59:30 PM PDT 24
Peak memory 198516 kb
Host smart-e5a38705-3250-4c6c-9bab-1c94090f344c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175681903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.4175681903
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1691766667
Short name T406
Test name
Test status
Simulation time 8434384238 ps
CPU time 13.99 seconds
Started Jun 04 12:59:28 PM PDT 24
Finished Jun 04 12:59:43 PM PDT 24
Peak memory 197936 kb
Host smart-4f6dce8b-f493-479a-beb2-6c1eb6a06357
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691766667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1691766667
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3731102153
Short name T316
Test name
Test status
Simulation time 476897178 ps
CPU time 1.09 seconds
Started Jun 04 12:59:34 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 196048 kb
Host smart-af6d695e-0736-4c7a-b83e-e0d33007ee3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731102153 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3731102153
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.868260273
Short name T59
Test name
Test status
Simulation time 357638378 ps
CPU time 1.11 seconds
Started Jun 04 12:59:33 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 193112 kb
Host smart-8e12fdc9-406e-4dad-9e8a-30a7efeba204
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868260273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.868260273
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.72846747
Short name T304
Test name
Test status
Simulation time 277820668 ps
CPU time 0.97 seconds
Started Jun 04 12:59:33 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 183556 kb
Host smart-f7c05fcb-117a-4bdb-93c2-96389365ea3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72846747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.72846747
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.692275537
Short name T332
Test name
Test status
Simulation time 2284980449 ps
CPU time 3.27 seconds
Started Jun 04 12:59:30 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 183772 kb
Host smart-0fe9d99b-4b68-4a6e-bbb2-80de906e9b0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692275537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.692275537
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2613079113
Short name T384
Test name
Test status
Simulation time 720694626 ps
CPU time 1.83 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:35 PM PDT 24
Peak memory 198352 kb
Host smart-d9fbb447-a4b9-47c5-bd25-1cf07ab44f11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613079113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2613079113
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3886134197
Short name T397
Test name
Test status
Simulation time 8031391761 ps
CPU time 14.11 seconds
Started Jun 04 12:59:35 PM PDT 24
Finished Jun 04 12:59:51 PM PDT 24
Peak memory 198084 kb
Host smart-efe3bd0c-a443-4849-b0dd-6edf2f528796
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886134197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3886134197
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3454202082
Short name T186
Test name
Test status
Simulation time 563556296 ps
CPU time 0.85 seconds
Started Jun 04 12:59:35 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 195844 kb
Host smart-89c2d152-8561-4f60-acd4-81f52900adf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454202082 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3454202082
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2236792525
Short name T39
Test name
Test status
Simulation time 432034567 ps
CPU time 1.05 seconds
Started Jun 04 12:59:27 PM PDT 24
Finished Jun 04 12:59:29 PM PDT 24
Peak memory 192920 kb
Host smart-75010bff-2929-4ea6-8816-81a8b994a125
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236792525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2236792525
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1658755595
Short name T386
Test name
Test status
Simulation time 434215365 ps
CPU time 1.19 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:35 PM PDT 24
Peak memory 183632 kb
Host smart-ded9ac35-5cc4-438c-829b-0e490b33e012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658755595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1658755595
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1045854963
Short name T356
Test name
Test status
Simulation time 2287792618 ps
CPU time 4.08 seconds
Started Jun 04 12:59:34 PM PDT 24
Finished Jun 04 12:59:40 PM PDT 24
Peak memory 194828 kb
Host smart-3e3b3047-841a-4856-94c5-83196652863c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045854963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1045854963
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.817428189
Short name T412
Test name
Test status
Simulation time 337197240 ps
CPU time 1.2 seconds
Started Jun 04 12:59:33 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 198240 kb
Host smart-5be4fd28-ca06-4344-a6ec-484cd0d3530b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817428189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.817428189
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3744882353
Short name T180
Test name
Test status
Simulation time 4627720190 ps
CPU time 2.9 seconds
Started Jun 04 12:59:28 PM PDT 24
Finished Jun 04 12:59:32 PM PDT 24
Peak memory 197668 kb
Host smart-9e3c92b1-8054-43ce-9255-ec57ef5a90f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744882353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3744882353
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3051626177
Short name T352
Test name
Test status
Simulation time 419488308 ps
CPU time 1.31 seconds
Started Jun 04 12:59:33 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 195608 kb
Host smart-0eb9602c-ffbc-4992-814b-f235364a3ef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051626177 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3051626177
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3153600381
Short name T301
Test name
Test status
Simulation time 408865157 ps
CPU time 0.74 seconds
Started Jun 04 12:59:30 PM PDT 24
Finished Jun 04 12:59:32 PM PDT 24
Peak memory 192988 kb
Host smart-16eb7e47-c9f5-4bbd-93e5-4db1ca78d4e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153600381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3153600381
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.951385237
Short name T355
Test name
Test status
Simulation time 400888064 ps
CPU time 0.69 seconds
Started Jun 04 12:59:32 PM PDT 24
Finished Jun 04 12:59:35 PM PDT 24
Peak memory 183588 kb
Host smart-2c4fc4fe-8e82-4aac-87f3-05dcf2ea615b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951385237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.951385237
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2130360187
Short name T73
Test name
Test status
Simulation time 1350974206 ps
CPU time 3.04 seconds
Started Jun 04 12:59:32 PM PDT 24
Finished Jun 04 12:59:38 PM PDT 24
Peak memory 183712 kb
Host smart-6090eaad-f2af-4f79-8882-c16944d7a440
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130360187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2130360187
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1432108981
Short name T329
Test name
Test status
Simulation time 371239343 ps
CPU time 2.24 seconds
Started Jun 04 12:59:33 PM PDT 24
Finished Jun 04 12:59:38 PM PDT 24
Peak memory 198400 kb
Host smart-77c18f56-a769-4db5-a7d4-02e76ac4afc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432108981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1432108981
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2364290235
Short name T417
Test name
Test status
Simulation time 4489732923 ps
CPU time 2.72 seconds
Started Jun 04 12:59:32 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 197336 kb
Host smart-2baf00f7-c592-45c4-846e-c932736b375d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364290235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2364290235
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.486770687
Short name T365
Test name
Test status
Simulation time 562127573 ps
CPU time 0.95 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:34 PM PDT 24
Peak memory 197408 kb
Host smart-9615f3c1-82ac-4d7a-bd79-a1fa1c6ead33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486770687 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.486770687
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2517518835
Short name T56
Test name
Test status
Simulation time 478054239 ps
CPU time 0.8 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:33 PM PDT 24
Peak memory 193860 kb
Host smart-db612e16-3603-4174-b5f6-f4ac8fdc3382
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517518835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2517518835
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.888351978
Short name T349
Test name
Test status
Simulation time 290950307 ps
CPU time 0.65 seconds
Started Jun 04 12:59:26 PM PDT 24
Finished Jun 04 12:59:28 PM PDT 24
Peak memory 183520 kb
Host smart-dcbf9fe9-a7ab-4007-a2f7-21f88591a347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888351978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.888351978
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2423420532
Short name T379
Test name
Test status
Simulation time 1036314309 ps
CPU time 1.26 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:35 PM PDT 24
Peak memory 193084 kb
Host smart-fe6de898-fee0-43d8-bc31-b34c5493784d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423420532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2423420532
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.161567123
Short name T398
Test name
Test status
Simulation time 531642398 ps
CPU time 2.32 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 12:59:41 PM PDT 24
Peak memory 198580 kb
Host smart-95c7417e-0e52-4bf3-8f2a-14680b7c8ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161567123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.161567123
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.223669743
Short name T34
Test name
Test status
Simulation time 3963537566 ps
CPU time 6.49 seconds
Started Jun 04 12:59:30 PM PDT 24
Finished Jun 04 12:59:38 PM PDT 24
Peak memory 197752 kb
Host smart-8efedf00-8464-4ecf-afb8-110866951296
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223669743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.223669743
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1646039674
Short name T371
Test name
Test status
Simulation time 601043083 ps
CPU time 1.13 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:35 PM PDT 24
Peak memory 195976 kb
Host smart-6d5bdfc4-85e5-4859-a529-29640b8a6ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646039674 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1646039674
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1144735602
Short name T399
Test name
Test status
Simulation time 468752662 ps
CPU time 0.94 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 12:59:42 PM PDT 24
Peak memory 192860 kb
Host smart-691395a5-609d-4c34-8686-f6cbcbb769ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144735602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1144735602
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2803392030
Short name T305
Test name
Test status
Simulation time 544866063 ps
CPU time 0.59 seconds
Started Jun 04 12:59:36 PM PDT 24
Finished Jun 04 12:59:38 PM PDT 24
Peak memory 183436 kb
Host smart-3d31ddb5-7e3d-45b5-971c-c947d2a1fbdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803392030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2803392030
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2810222406
Short name T340
Test name
Test status
Simulation time 2078192392 ps
CPU time 1.31 seconds
Started Jun 04 12:59:30 PM PDT 24
Finished Jun 04 12:59:33 PM PDT 24
Peak memory 193968 kb
Host smart-d3f452ec-41e4-4656-acdf-c507360c2441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810222406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2810222406
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3414430635
Short name T363
Test name
Test status
Simulation time 470113789 ps
CPU time 2.98 seconds
Started Jun 04 12:59:26 PM PDT 24
Finished Jun 04 12:59:31 PM PDT 24
Peak memory 198336 kb
Host smart-546392c8-a66f-4e71-82d8-5d25b5f8a2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414430635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3414430635
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3771733075
Short name T389
Test name
Test status
Simulation time 8943762299 ps
CPU time 5.31 seconds
Started Jun 04 12:59:30 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 197988 kb
Host smart-a60b3fa6-c51b-4727-ba64-79ba017c236e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771733075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3771733075
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4079392579
Short name T359
Test name
Test status
Simulation time 470052858 ps
CPU time 0.98 seconds
Started Jun 04 12:59:30 PM PDT 24
Finished Jun 04 12:59:32 PM PDT 24
Peak memory 195532 kb
Host smart-e29f2af2-8f7c-448b-a690-2fdb0a8e1f01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079392579 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.4079392579
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2530387698
Short name T318
Test name
Test status
Simulation time 444864814 ps
CPU time 0.74 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 12:59:42 PM PDT 24
Peak memory 192876 kb
Host smart-bd652403-0362-4055-97d7-c6ad9393caeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530387698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2530387698
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3319212745
Short name T339
Test name
Test status
Simulation time 538015462 ps
CPU time 0.57 seconds
Started Jun 04 12:59:33 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 183528 kb
Host smart-6b3f4caf-cebe-41ba-8e41-02eb6581cc70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319212745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3319212745
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2842141055
Short name T328
Test name
Test status
Simulation time 2041265230 ps
CPU time 1.66 seconds
Started Jun 04 12:59:34 PM PDT 24
Finished Jun 04 12:59:38 PM PDT 24
Peak memory 194140 kb
Host smart-527949ae-e069-4c73-bbd0-b8ded780f2b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842141055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2842141055
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.740259556
Short name T296
Test name
Test status
Simulation time 414961893 ps
CPU time 1.43 seconds
Started Jun 04 12:59:30 PM PDT 24
Finished Jun 04 12:59:34 PM PDT 24
Peak memory 198244 kb
Host smart-c34eb1a0-ed87-4dae-95c8-916c8b7f5e4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740259556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.740259556
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3801977224
Short name T375
Test name
Test status
Simulation time 4158919458 ps
CPU time 2.26 seconds
Started Jun 04 12:59:32 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 197772 kb
Host smart-66cc99f4-9743-4b84-a11c-0e0a47f5733a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801977224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3801977224
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.232888797
Short name T185
Test name
Test status
Simulation time 433636098 ps
CPU time 1.21 seconds
Started Jun 04 12:59:30 PM PDT 24
Finished Jun 04 12:59:33 PM PDT 24
Peak memory 195372 kb
Host smart-b1ed6c75-b1d9-4e4c-98ab-6c652b5d5c84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232888797 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.232888797
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.437868375
Short name T37
Test name
Test status
Simulation time 315615409 ps
CPU time 0.78 seconds
Started Jun 04 12:59:54 PM PDT 24
Finished Jun 04 12:59:56 PM PDT 24
Peak memory 192088 kb
Host smart-4a7f4037-d89a-4d1c-b1b5-d7d878ad3168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437868375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.437868375
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2480426453
Short name T324
Test name
Test status
Simulation time 448061105 ps
CPU time 0.68 seconds
Started Jun 04 12:59:34 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 183536 kb
Host smart-036e43d9-8c09-41df-8bd4-23343368657b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480426453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2480426453
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1374598841
Short name T378
Test name
Test status
Simulation time 1909641072 ps
CPU time 3.24 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 194204 kb
Host smart-c7fa3625-a6f2-472a-961b-b91029302b67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374598841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1374598841
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.588185717
Short name T278
Test name
Test status
Simulation time 979762312 ps
CPU time 2.35 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:35 PM PDT 24
Peak memory 198436 kb
Host smart-bcf3fb67-a69a-41b6-87c2-5c7dc33cf914
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588185717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.588185717
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1026443141
Short name T35
Test name
Test status
Simulation time 4088063677 ps
CPU time 4.04 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 12:59:44 PM PDT 24
Peak memory 197688 kb
Host smart-2db1a917-7501-4d2b-a706-a7d33361692a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026443141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1026443141
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1945773960
Short name T343
Test name
Test status
Simulation time 388786504 ps
CPU time 0.93 seconds
Started Jun 04 12:59:32 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 195372 kb
Host smart-a3476c89-e3f6-4c4e-971f-335aaf482ea9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945773960 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1945773960
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2139499792
Short name T395
Test name
Test status
Simulation time 356835748 ps
CPU time 1.12 seconds
Started Jun 04 12:59:33 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 192936 kb
Host smart-40100a15-ea82-471a-aa85-eced0833a33c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139499792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2139499792
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4079619182
Short name T298
Test name
Test status
Simulation time 511784556 ps
CPU time 0.93 seconds
Started Jun 04 12:59:35 PM PDT 24
Finished Jun 04 12:59:38 PM PDT 24
Peak memory 183496 kb
Host smart-89e0b2cb-55fa-413d-a5e3-a666491a92bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079619182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.4079619182
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3127154738
Short name T416
Test name
Test status
Simulation time 2415859940 ps
CPU time 8.21 seconds
Started Jun 04 12:59:34 PM PDT 24
Finished Jun 04 12:59:44 PM PDT 24
Peak memory 191848 kb
Host smart-2e3d1059-c3ab-42b4-9eb6-8c13e74b47cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127154738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3127154738
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1719730613
Short name T322
Test name
Test status
Simulation time 661279347 ps
CPU time 2.32 seconds
Started Jun 04 12:59:44 PM PDT 24
Finished Jun 04 12:59:47 PM PDT 24
Peak memory 198296 kb
Host smart-fd2ccea8-c610-4180-af05-4d31c23a52a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719730613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1719730613
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1264917518
Short name T410
Test name
Test status
Simulation time 492938889 ps
CPU time 1.03 seconds
Started Jun 04 12:59:36 PM PDT 24
Finished Jun 04 12:59:39 PM PDT 24
Peak memory 195036 kb
Host smart-2bb0759a-1686-4d6b-897e-181a18f80d39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264917518 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1264917518
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3343578488
Short name T409
Test name
Test status
Simulation time 397351429 ps
CPU time 0.87 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:34 PM PDT 24
Peak memory 192944 kb
Host smart-80fc1710-9a77-486c-940c-93f37bd8dc57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343578488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3343578488
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4245077757
Short name T307
Test name
Test status
Simulation time 444212885 ps
CPU time 1.26 seconds
Started Jun 04 12:59:30 PM PDT 24
Finished Jun 04 12:59:33 PM PDT 24
Peak memory 183564 kb
Host smart-2a8d50a3-71a3-4e18-98a1-b3e018c3bbe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245077757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.4245077757
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2564831069
Short name T71
Test name
Test status
Simulation time 1791166712 ps
CPU time 1.35 seconds
Started Jun 04 12:59:29 PM PDT 24
Finished Jun 04 12:59:32 PM PDT 24
Peak memory 194552 kb
Host smart-ace19062-692d-423a-8273-4d973e17132a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564831069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2564831069
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2236713314
Short name T341
Test name
Test status
Simulation time 609229614 ps
CPU time 2 seconds
Started Jun 04 12:59:35 PM PDT 24
Finished Jun 04 12:59:39 PM PDT 24
Peak memory 198224 kb
Host smart-8671ad24-f140-491f-884a-0224c0d43c9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236713314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2236713314
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2524091133
Short name T380
Test name
Test status
Simulation time 8402029746 ps
CPU time 4 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 12:59:45 PM PDT 24
Peak memory 198036 kb
Host smart-288c0028-b265-428d-9f02-dee037b7ed49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524091133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2524091133
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3520720952
Short name T65
Test name
Test status
Simulation time 551016292 ps
CPU time 1.22 seconds
Started Jun 04 12:59:22 PM PDT 24
Finished Jun 04 12:59:25 PM PDT 24
Peak memory 194184 kb
Host smart-0559bd8e-c2cb-4825-912c-97cbadd13fdb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520720952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3520720952
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4102202545
Short name T346
Test name
Test status
Simulation time 14265272560 ps
CPU time 9.71 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:30 PM PDT 24
Peak memory 192016 kb
Host smart-fecbbca4-d4ea-42d1-893c-8faa1e7f78c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102202545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.4102202545
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1188210683
Short name T312
Test name
Test status
Simulation time 1148602676 ps
CPU time 1.69 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:22 PM PDT 24
Peak memory 193128 kb
Host smart-7500ca6d-14a4-433d-94b4-69f3d4e21a90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188210683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1188210683
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3554150251
Short name T370
Test name
Test status
Simulation time 439272645 ps
CPU time 0.98 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:21 PM PDT 24
Peak memory 195516 kb
Host smart-9978a023-4043-4ab6-964e-6c8029631bc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554150251 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3554150251
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4194707875
Short name T62
Test name
Test status
Simulation time 416349996 ps
CPU time 1.18 seconds
Started Jun 04 12:59:18 PM PDT 24
Finished Jun 04 12:59:21 PM PDT 24
Peak memory 193128 kb
Host smart-e2add612-8b2f-466f-9748-706e9873a75c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194707875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.4194707875
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3147884793
Short name T291
Test name
Test status
Simulation time 314467864 ps
CPU time 0.97 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:21 PM PDT 24
Peak memory 183492 kb
Host smart-7ac2107a-98b8-4eed-b084-8b7d25d60fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147884793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3147884793
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3468900181
Short name T306
Test name
Test status
Simulation time 346061522 ps
CPU time 0.65 seconds
Started Jun 04 12:59:17 PM PDT 24
Finished Jun 04 12:59:18 PM PDT 24
Peak memory 183540 kb
Host smart-fb4e3110-83df-4fcc-9efc-37636b6dfa60
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468900181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3468900181
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2288965545
Short name T315
Test name
Test status
Simulation time 417138671 ps
CPU time 0.64 seconds
Started Jun 04 12:59:21 PM PDT 24
Finished Jun 04 12:59:23 PM PDT 24
Peak memory 183580 kb
Host smart-d3ed1c43-bb52-4623-b117-cf0d86d185f0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288965545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2288965545
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.767082314
Short name T376
Test name
Test status
Simulation time 2221947265 ps
CPU time 3.65 seconds
Started Jun 04 12:59:20 PM PDT 24
Finished Jun 04 12:59:25 PM PDT 24
Peak memory 183736 kb
Host smart-29813e97-2655-49b2-bf43-2a500ab5ced7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767082314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.767082314
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1200772965
Short name T319
Test name
Test status
Simulation time 495431319 ps
CPU time 2.83 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:23 PM PDT 24
Peak memory 198396 kb
Host smart-bcd516a6-0734-4fdb-a8d8-27ab45fb3ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200772965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1200772965
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1545410002
Short name T414
Test name
Test status
Simulation time 4032578544 ps
CPU time 6.76 seconds
Started Jun 04 12:59:16 PM PDT 24
Finished Jun 04 12:59:24 PM PDT 24
Peak memory 196524 kb
Host smart-e4bcb5f8-a09a-4c49-b6d2-025c3cfa36e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545410002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1545410002
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2153778958
Short name T288
Test name
Test status
Simulation time 368731830 ps
CPU time 0.85 seconds
Started Jun 04 12:59:32 PM PDT 24
Finished Jun 04 12:59:35 PM PDT 24
Peak memory 183568 kb
Host smart-04840d21-be02-4ce5-8994-5e79d1e35b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153778958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2153778958
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1887133388
Short name T418
Test name
Test status
Simulation time 455758282 ps
CPU time 0.6 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 12:59:41 PM PDT 24
Peak memory 183580 kb
Host smart-2e957853-10fa-40f2-a65c-b255857eb475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887133388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1887133388
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3915872688
Short name T334
Test name
Test status
Simulation time 299936541 ps
CPU time 0.78 seconds
Started Jun 04 12:59:34 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 183596 kb
Host smart-ee0ca583-2b02-4212-b4a9-d1740d572116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915872688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3915872688
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1453661579
Short name T407
Test name
Test status
Simulation time 403467620 ps
CPU time 0.73 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 12:59:40 PM PDT 24
Peak memory 183588 kb
Host smart-7d3d4d4d-ef34-4f1b-b45f-00d2e1eec4ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453661579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1453661579
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1816286207
Short name T293
Test name
Test status
Simulation time 392493261 ps
CPU time 1.03 seconds
Started Jun 04 12:59:32 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 183536 kb
Host smart-e1b77e16-372b-4953-b1fb-3dbcfc109109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816286207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1816286207
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4189940695
Short name T326
Test name
Test status
Simulation time 444234483 ps
CPU time 1.23 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 12:59:43 PM PDT 24
Peak memory 183588 kb
Host smart-7595f5ca-865c-4677-9d1e-9a2f6dbee369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189940695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.4189940695
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.234359972
Short name T377
Test name
Test status
Simulation time 459696218 ps
CPU time 0.68 seconds
Started Jun 04 12:59:34 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 183588 kb
Host smart-dd64f1e0-9bf1-442d-87ab-9e906e8c10fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234359972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.234359972
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.393271180
Short name T368
Test name
Test status
Simulation time 268502965 ps
CPU time 0.94 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 12:59:50 PM PDT 24
Peak memory 183556 kb
Host smart-131df98a-95ba-48be-ae87-fcd703f3a880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393271180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.393271180
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1608048302
Short name T342
Test name
Test status
Simulation time 375149798 ps
CPU time 0.74 seconds
Started Jun 04 12:59:35 PM PDT 24
Finished Jun 04 12:59:38 PM PDT 24
Peak memory 183752 kb
Host smart-10612f6e-7d5c-4b1d-9767-222eb7f1887f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608048302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1608048302
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1920892500
Short name T286
Test name
Test status
Simulation time 360849708 ps
CPU time 0.83 seconds
Started Jun 04 12:59:33 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 183596 kb
Host smart-46d6e299-9b01-46e6-8029-eb08e5ab9040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920892500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1920892500
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2524067277
Short name T60
Test name
Test status
Simulation time 374470397 ps
CPU time 1.23 seconds
Started Jun 04 12:59:22 PM PDT 24
Finished Jun 04 12:59:25 PM PDT 24
Peak memory 183636 kb
Host smart-8a84905e-e43c-4a0b-8170-85346594e0cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524067277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2524067277
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1073804099
Short name T58
Test name
Test status
Simulation time 910215191 ps
CPU time 1.66 seconds
Started Jun 04 12:59:21 PM PDT 24
Finished Jun 04 12:59:24 PM PDT 24
Peak memory 195424 kb
Host smart-de5384d0-9785-4492-95d6-d182eacbec63
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073804099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1073804099
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3181650726
Short name T33
Test name
Test status
Simulation time 924860126 ps
CPU time 1.96 seconds
Started Jun 04 12:59:21 PM PDT 24
Finished Jun 04 12:59:24 PM PDT 24
Peak memory 183588 kb
Host smart-ec6ca21d-d3f6-4f54-988b-350972c8d115
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181650726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3181650726
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.422611741
Short name T321
Test name
Test status
Simulation time 504571047 ps
CPU time 1.53 seconds
Started Jun 04 12:59:22 PM PDT 24
Finished Jun 04 12:59:25 PM PDT 24
Peak memory 196068 kb
Host smart-0ad990ca-d08f-419b-88fa-8531eeb817ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422611741 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.422611741
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1435467014
Short name T413
Test name
Test status
Simulation time 443247183 ps
CPU time 0.71 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:21 PM PDT 24
Peak memory 193272 kb
Host smart-6ea34d6c-be7f-4e2b-972d-98c287215afd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435467014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1435467014
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.407720599
Short name T408
Test name
Test status
Simulation time 525388738 ps
CPU time 0.85 seconds
Started Jun 04 12:59:18 PM PDT 24
Finished Jun 04 12:59:19 PM PDT 24
Peak memory 183588 kb
Host smart-deed5cd9-f1b1-4a46-9c89-5d6df17c2238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407720599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.407720599
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2864740
Short name T313
Test name
Test status
Simulation time 332178010 ps
CPU time 0.58 seconds
Started Jun 04 12:59:23 PM PDT 24
Finished Jun 04 12:59:25 PM PDT 24
Peak memory 183460 kb
Host smart-7f80d9a8-ef99-4066-b52b-57901e36641a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_t
imer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_time
r_mem_partial_access.2864740
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3435369030
Short name T387
Test name
Test status
Simulation time 454518106 ps
CPU time 0.88 seconds
Started Jun 04 12:59:18 PM PDT 24
Finished Jun 04 12:59:20 PM PDT 24
Peak memory 183520 kb
Host smart-904c3e3b-70aa-4e18-bba8-d558ff07f4fb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435369030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3435369030
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3837179001
Short name T405
Test name
Test status
Simulation time 1508658899 ps
CPU time 2.62 seconds
Started Jun 04 12:59:20 PM PDT 24
Finished Jun 04 12:59:24 PM PDT 24
Peak memory 192600 kb
Host smart-1c86f3d6-84ad-41eb-b7fe-99da3b0403a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837179001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3837179001
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1133226657
Short name T415
Test name
Test status
Simulation time 365708481 ps
CPU time 2.14 seconds
Started Jun 04 12:59:20 PM PDT 24
Finished Jun 04 12:59:23 PM PDT 24
Peak memory 198388 kb
Host smart-ee963569-9d35-4444-9ba3-d69d50505927
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133226657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1133226657
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1962253587
Short name T369
Test name
Test status
Simulation time 8205447134 ps
CPU time 4.13 seconds
Started Jun 04 12:59:17 PM PDT 24
Finished Jun 04 12:59:22 PM PDT 24
Peak memory 197964 kb
Host smart-9f709677-6bd7-4a23-9b31-ceb5fed68183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962253587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1962253587
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1739189792
Short name T351
Test name
Test status
Simulation time 515996101 ps
CPU time 0.97 seconds
Started Jun 04 12:59:34 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 183564 kb
Host smart-c2293a6e-be5d-44fc-8251-3deadd7d96e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739189792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1739189792
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1434894705
Short name T362
Test name
Test status
Simulation time 457960979 ps
CPU time 1.11 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 12:59:40 PM PDT 24
Peak memory 183588 kb
Host smart-f5ad0dc5-0d32-4490-9e94-11069aa43b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434894705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1434894705
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3461847929
Short name T282
Test name
Test status
Simulation time 339819281 ps
CPU time 1.04 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 12:59:43 PM PDT 24
Peak memory 183592 kb
Host smart-4995f135-cdd7-4d9a-ba70-5c4afcabbc7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461847929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3461847929
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3826946679
Short name T392
Test name
Test status
Simulation time 470451521 ps
CPU time 0.76 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 12:59:41 PM PDT 24
Peak memory 183524 kb
Host smart-2b9eb1c3-98f2-47ae-9510-46cab7ed2e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826946679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3826946679
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3202917396
Short name T335
Test name
Test status
Simulation time 504307244 ps
CPU time 1.38 seconds
Started Jun 04 12:59:32 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 183584 kb
Host smart-7ee6c9c1-86f9-4922-a4bf-b98806027dad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202917396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3202917396
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.115780360
Short name T289
Test name
Test status
Simulation time 483040031 ps
CPU time 1.25 seconds
Started Jun 04 12:59:32 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 183564 kb
Host smart-99dde158-05ba-40ed-90cb-f10ade194a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115780360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.115780360
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1926598964
Short name T345
Test name
Test status
Simulation time 381900807 ps
CPU time 0.98 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 12:59:40 PM PDT 24
Peak memory 183568 kb
Host smart-317f84fe-e1c6-4931-bed5-12ea4fed9fa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926598964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1926598964
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1620909795
Short name T292
Test name
Test status
Simulation time 295871153 ps
CPU time 0.96 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 12:59:41 PM PDT 24
Peak memory 183560 kb
Host smart-f742ad12-974c-413a-9262-4c171e9982eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620909795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1620909795
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3374898639
Short name T284
Test name
Test status
Simulation time 463511998 ps
CPU time 0.84 seconds
Started Jun 04 12:59:36 PM PDT 24
Finished Jun 04 12:59:38 PM PDT 24
Peak memory 183588 kb
Host smart-9927ba2c-ffd3-4b38-990f-1c3a6409b989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374898639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3374898639
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2392229564
Short name T320
Test name
Test status
Simulation time 378939575 ps
CPU time 1.08 seconds
Started Jun 04 12:59:34 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 183560 kb
Host smart-8f091b57-5c3f-4283-90ad-4ccc5e7f9295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392229564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2392229564
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2118199099
Short name T32
Test name
Test status
Simulation time 507829695 ps
CPU time 0.92 seconds
Started Jun 04 12:59:22 PM PDT 24
Finished Jun 04 12:59:24 PM PDT 24
Peak memory 183644 kb
Host smart-ea4060be-a895-484f-b8a3-c08c02f4affd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118199099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2118199099
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.542508871
Short name T385
Test name
Test status
Simulation time 14148738387 ps
CPU time 19.89 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:41 PM PDT 24
Peak memory 191900 kb
Host smart-0327e9be-3a15-402b-82ea-e2d48bbee678
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542508871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.542508871
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1673489619
Short name T323
Test name
Test status
Simulation time 925020384 ps
CPU time 1.39 seconds
Started Jun 04 12:59:21 PM PDT 24
Finished Jun 04 12:59:23 PM PDT 24
Peak memory 183632 kb
Host smart-b16ae36e-afa8-4ca4-bd51-a32f8b0598d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673489619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1673489619
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2989930963
Short name T300
Test name
Test status
Simulation time 433920238 ps
CPU time 1.35 seconds
Started Jun 04 12:59:15 PM PDT 24
Finished Jun 04 12:59:18 PM PDT 24
Peak memory 195252 kb
Host smart-f3590652-91aa-45d1-9bce-15381efd1cb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989930963 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2989930963
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2579223785
Short name T325
Test name
Test status
Simulation time 427525012 ps
CPU time 0.88 seconds
Started Jun 04 12:59:21 PM PDT 24
Finished Jun 04 12:59:23 PM PDT 24
Peak memory 192988 kb
Host smart-6148e057-e443-47e9-8edf-e4b7e00f825a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579223785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2579223785
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.54781815
Short name T396
Test name
Test status
Simulation time 431951716 ps
CPU time 1.02 seconds
Started Jun 04 12:59:17 PM PDT 24
Finished Jun 04 12:59:19 PM PDT 24
Peak memory 183564 kb
Host smart-c3d02178-8c92-493e-9e37-c877d4e8fa56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54781815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.54781815
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.362928359
Short name T310
Test name
Test status
Simulation time 291920447 ps
CPU time 0.79 seconds
Started Jun 04 12:59:20 PM PDT 24
Finished Jun 04 12:59:23 PM PDT 24
Peak memory 183512 kb
Host smart-0090fd03-6dd6-4d8f-a6f3-59d325d40a8f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362928359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.362928359
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.863628348
Short name T420
Test name
Test status
Simulation time 286081331 ps
CPU time 0.63 seconds
Started Jun 04 12:59:22 PM PDT 24
Finished Jun 04 12:59:24 PM PDT 24
Peak memory 183588 kb
Host smart-1bcffa22-10fd-473d-ba03-c474db92d48d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863628348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.863628348
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.440234999
Short name T69
Test name
Test status
Simulation time 1298327608 ps
CPU time 2.29 seconds
Started Jun 04 12:59:17 PM PDT 24
Finished Jun 04 12:59:20 PM PDT 24
Peak memory 183700 kb
Host smart-e9108d1c-b12b-489d-933e-feac4efa48d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440234999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.440234999
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2459363253
Short name T297
Test name
Test status
Simulation time 522358685 ps
CPU time 2.27 seconds
Started Jun 04 12:59:24 PM PDT 24
Finished Jun 04 12:59:27 PM PDT 24
Peak memory 198352 kb
Host smart-b735dbac-26a6-4d89-bf1b-499804213be7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459363253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2459363253
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2612701631
Short name T183
Test name
Test status
Simulation time 8393609616 ps
CPU time 4.54 seconds
Started Jun 04 12:59:20 PM PDT 24
Finished Jun 04 12:59:26 PM PDT 24
Peak memory 198000 kb
Host smart-58a88252-efc9-427b-ad61-49723d70ead9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612701631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2612701631
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1123781816
Short name T358
Test name
Test status
Simulation time 376426407 ps
CPU time 0.67 seconds
Started Jun 04 12:59:54 PM PDT 24
Finished Jun 04 12:59:55 PM PDT 24
Peak memory 183592 kb
Host smart-4c0787b5-0492-4b9f-8d51-8c6d6cd2b37b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123781816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1123781816
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.982249501
Short name T283
Test name
Test status
Simulation time 307078167 ps
CPU time 0.6 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 12:59:39 PM PDT 24
Peak memory 183588 kb
Host smart-8037a734-279d-46c3-ba2b-f4fa120f206c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982249501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.982249501
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2906515281
Short name T367
Test name
Test status
Simulation time 410832498 ps
CPU time 0.63 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 12:59:41 PM PDT 24
Peak memory 183560 kb
Host smart-24950398-baa9-48e3-b430-1fb473d74bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906515281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2906515281
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1014986870
Short name T374
Test name
Test status
Simulation time 499811987 ps
CPU time 1.27 seconds
Started Jun 04 12:59:33 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 183580 kb
Host smart-ac26b007-d520-4526-b130-2ba5b92e810f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014986870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1014986870
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3626708616
Short name T383
Test name
Test status
Simulation time 518750564 ps
CPU time 0.77 seconds
Started Jun 04 12:59:40 PM PDT 24
Finished Jun 04 12:59:43 PM PDT 24
Peak memory 183544 kb
Host smart-a25e7103-f361-44f7-9f5a-928ff5bf4b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626708616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3626708616
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.144525837
Short name T330
Test name
Test status
Simulation time 379482943 ps
CPU time 1.07 seconds
Started Jun 04 12:59:34 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 183564 kb
Host smart-e7d6c991-797e-42c1-8270-5226c36be9b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144525837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.144525837
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2164025244
Short name T338
Test name
Test status
Simulation time 293351052 ps
CPU time 0.96 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 12:59:39 PM PDT 24
Peak memory 183588 kb
Host smart-0d2e9065-c78f-43fa-bb59-0c80b3b04699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164025244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2164025244
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3240745518
Short name T364
Test name
Test status
Simulation time 449107576 ps
CPU time 0.79 seconds
Started Jun 04 12:59:36 PM PDT 24
Finished Jun 04 12:59:39 PM PDT 24
Peak memory 183556 kb
Host smart-2c85985d-2db5-4d9b-95af-94f185c0be08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240745518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3240745518
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3625357009
Short name T280
Test name
Test status
Simulation time 420120617 ps
CPU time 1.17 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 12:59:41 PM PDT 24
Peak memory 183572 kb
Host smart-827e9cb4-a7f4-4fb1-a567-4009a3faffea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625357009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3625357009
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2415186087
Short name T331
Test name
Test status
Simulation time 512302802 ps
CPU time 1.33 seconds
Started Jun 04 12:59:43 PM PDT 24
Finished Jun 04 12:59:46 PM PDT 24
Peak memory 183544 kb
Host smart-a33a91d3-75e1-425f-9b8f-801c506d0819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415186087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2415186087
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.248768983
Short name T314
Test name
Test status
Simulation time 371747050 ps
CPU time 0.8 seconds
Started Jun 04 12:59:22 PM PDT 24
Finished Jun 04 12:59:24 PM PDT 24
Peak memory 196064 kb
Host smart-41b23127-6025-4359-b0f8-4601d335551f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248768983 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.248768983
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2032924230
Short name T55
Test name
Test status
Simulation time 347296624 ps
CPU time 1.16 seconds
Started Jun 04 12:59:20 PM PDT 24
Finished Jun 04 12:59:23 PM PDT 24
Peak memory 193016 kb
Host smart-88cf7871-df7b-42c6-95be-3f2ecbb254c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032924230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2032924230
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.690661720
Short name T287
Test name
Test status
Simulation time 436099020 ps
CPU time 0.63 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:21 PM PDT 24
Peak memory 183404 kb
Host smart-2e15d3ed-ae4b-4868-b2bb-030d79c65a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690661720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.690661720
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2436578789
Short name T70
Test name
Test status
Simulation time 1142771214 ps
CPU time 1.16 seconds
Started Jun 04 12:59:20 PM PDT 24
Finished Jun 04 12:59:23 PM PDT 24
Peak memory 192600 kb
Host smart-5832a2e7-c987-4edb-ae81-a2b3c7a8ce27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436578789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2436578789
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.4158475937
Short name T347
Test name
Test status
Simulation time 715043115 ps
CPU time 1.46 seconds
Started Jun 04 12:59:17 PM PDT 24
Finished Jun 04 12:59:20 PM PDT 24
Peak memory 198352 kb
Host smart-2bb7eb8c-04a2-4e3f-acfe-6b2de38d5dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158475937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.4158475937
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3096365946
Short name T181
Test name
Test status
Simulation time 8582906819 ps
CPU time 12.56 seconds
Started Jun 04 12:59:20 PM PDT 24
Finished Jun 04 12:59:34 PM PDT 24
Peak memory 197900 kb
Host smart-3438c873-fe9e-44b4-b383-a901b26f778d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096365946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3096365946
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2752549737
Short name T354
Test name
Test status
Simulation time 448172055 ps
CPU time 0.95 seconds
Started Jun 04 12:59:21 PM PDT 24
Finished Jun 04 12:59:24 PM PDT 24
Peak memory 196656 kb
Host smart-db587c64-911f-4041-b7ce-dd3f49a32ae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752549737 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2752549737
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1389631502
Short name T382
Test name
Test status
Simulation time 403421534 ps
CPU time 0.68 seconds
Started Jun 04 12:59:23 PM PDT 24
Finished Jun 04 12:59:25 PM PDT 24
Peak memory 183680 kb
Host smart-5e0ba484-f862-46f5-aeae-1723cbc2d6e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389631502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1389631502
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1806542370
Short name T290
Test name
Test status
Simulation time 540694341 ps
CPU time 0.69 seconds
Started Jun 04 12:59:21 PM PDT 24
Finished Jun 04 12:59:23 PM PDT 24
Peak memory 183572 kb
Host smart-d618ed19-fd5b-469d-aa04-8a25a3fe8ee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806542370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1806542370
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2679106499
Short name T391
Test name
Test status
Simulation time 2956868100 ps
CPU time 3.41 seconds
Started Jun 04 12:59:24 PM PDT 24
Finished Jun 04 12:59:28 PM PDT 24
Peak memory 183864 kb
Host smart-ab11eefb-998d-4d53-ba0e-4644d482e84d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679106499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2679106499
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3780821933
Short name T366
Test name
Test status
Simulation time 435642719 ps
CPU time 1.53 seconds
Started Jun 04 12:59:22 PM PDT 24
Finished Jun 04 12:59:25 PM PDT 24
Peak memory 198420 kb
Host smart-b88ed1ba-d325-4810-b05c-fd11381b3fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780821933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3780821933
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.850643320
Short name T403
Test name
Test status
Simulation time 8243562066 ps
CPU time 3.54 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:24 PM PDT 24
Peak memory 198072 kb
Host smart-84d58aaa-ea8b-4a40-86a7-6ddfdf01d3f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850643320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.850643320
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1832967450
Short name T393
Test name
Test status
Simulation time 560470012 ps
CPU time 0.97 seconds
Started Jun 04 12:59:20 PM PDT 24
Finished Jun 04 12:59:23 PM PDT 24
Peak memory 196952 kb
Host smart-7bbd77b2-9964-425b-859e-2ad9c3098f4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832967450 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1832967450
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3023258706
Short name T419
Test name
Test status
Simulation time 465581377 ps
CPU time 0.89 seconds
Started Jun 04 12:59:18 PM PDT 24
Finished Jun 04 12:59:20 PM PDT 24
Peak memory 183780 kb
Host smart-1774d12e-5fde-41c6-8ad1-ac6f309afe95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023258706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3023258706
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1573584528
Short name T311
Test name
Test status
Simulation time 500728120 ps
CPU time 0.72 seconds
Started Jun 04 12:59:18 PM PDT 24
Finished Jun 04 12:59:20 PM PDT 24
Peak memory 183576 kb
Host smart-798fb3b6-e7b8-4a4e-a335-f048c0f88798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573584528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1573584528
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1158678314
Short name T350
Test name
Test status
Simulation time 1822353730 ps
CPU time 5.09 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:26 PM PDT 24
Peak memory 193008 kb
Host smart-71729dfb-abec-409f-86ec-eb0f604c1a70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158678314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1158678314
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2121728874
Short name T302
Test name
Test status
Simulation time 643174854 ps
CPU time 1.66 seconds
Started Jun 04 12:59:19 PM PDT 24
Finished Jun 04 12:59:22 PM PDT 24
Peak memory 198388 kb
Host smart-625695b7-46c2-4360-b9a4-a2506cdb3b89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121728874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2121728874
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3147663904
Short name T401
Test name
Test status
Simulation time 4316731265 ps
CPU time 2.39 seconds
Started Jun 04 12:59:22 PM PDT 24
Finished Jun 04 12:59:26 PM PDT 24
Peak memory 197636 kb
Host smart-6e4ee041-2ea6-40cc-8d80-37c8dec0949b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147663904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3147663904
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3837451033
Short name T303
Test name
Test status
Simulation time 585387101 ps
CPU time 0.92 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:34 PM PDT 24
Peak memory 198380 kb
Host smart-d5b5dd1e-43f9-4978-9831-dc03c0e4ea19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837451033 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3837451033
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3802092546
Short name T64
Test name
Test status
Simulation time 414739894 ps
CPU time 0.86 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 12:59:42 PM PDT 24
Peak memory 192868 kb
Host smart-7b26e7d9-b95e-4c3d-ab2f-039200520db6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802092546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3802092546
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2749886446
Short name T390
Test name
Test status
Simulation time 322267043 ps
CPU time 0.67 seconds
Started Jun 04 12:59:27 PM PDT 24
Finished Jun 04 12:59:29 PM PDT 24
Peak memory 183560 kb
Host smart-513522c6-ed6c-4b0e-9223-6a07d51c5061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749886446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2749886446
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.448724379
Short name T74
Test name
Test status
Simulation time 2739371438 ps
CPU time 8.23 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:41 PM PDT 24
Peak memory 191880 kb
Host smart-c7c95066-460a-4bb1-9027-e87207d3538e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448724379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.448724379
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4054201914
Short name T344
Test name
Test status
Simulation time 421717859 ps
CPU time 2.31 seconds
Started Jun 04 12:59:23 PM PDT 24
Finished Jun 04 12:59:26 PM PDT 24
Peak memory 198320 kb
Host smart-2a3034f3-7357-4c92-9056-8a33782bc7e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054201914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4054201914
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.845879915
Short name T357
Test name
Test status
Simulation time 8092753315 ps
CPU time 6.62 seconds
Started Jun 04 12:59:30 PM PDT 24
Finished Jun 04 12:59:37 PM PDT 24
Peak memory 198072 kb
Host smart-2bda28d7-e453-4bf5-8932-e61a6c737414
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845879915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.845879915
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2406733672
Short name T309
Test name
Test status
Simulation time 568276832 ps
CPU time 0.89 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:34 PM PDT 24
Peak memory 195820 kb
Host smart-21c19c22-895b-4f2b-9098-6e61cafe30e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406733672 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2406733672
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1898590805
Short name T327
Test name
Test status
Simulation time 336525646 ps
CPU time 1.01 seconds
Started Jun 04 12:59:26 PM PDT 24
Finished Jun 04 12:59:29 PM PDT 24
Peak memory 192916 kb
Host smart-5bce9fae-baf0-4e7a-8b49-bd23d650986f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898590805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1898590805
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1527339764
Short name T281
Test name
Test status
Simulation time 450352179 ps
CPU time 0.72 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:33 PM PDT 24
Peak memory 183588 kb
Host smart-2aa0c5bb-4635-4956-aa3c-1d3cee30fa34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527339764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1527339764
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2290234293
Short name T336
Test name
Test status
Simulation time 891722409 ps
CPU time 1.15 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:34 PM PDT 24
Peak memory 183556 kb
Host smart-ad84e331-a1a2-43fe-a5cb-e9fcdcee1975
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290234293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2290234293
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.254716489
Short name T285
Test name
Test status
Simulation time 841097556 ps
CPU time 1.85 seconds
Started Jun 04 12:59:31 PM PDT 24
Finished Jun 04 12:59:35 PM PDT 24
Peak memory 198416 kb
Host smart-57acb969-3617-4cbd-aeb5-1cf77b8d16f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254716489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.254716489
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2711439460
Short name T381
Test name
Test status
Simulation time 4538528571 ps
CPU time 6.86 seconds
Started Jun 04 12:59:43 PM PDT 24
Finished Jun 04 12:59:51 PM PDT 24
Peak memory 197680 kb
Host smart-d8a495a7-9191-41c5-8b01-7ef8a1c3fb5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711439460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2711439460
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.813514787
Short name T184
Test name
Test status
Simulation time 56966633142 ps
CPU time 82.64 seconds
Started Jun 04 01:27:59 PM PDT 24
Finished Jun 04 01:29:23 PM PDT 24
Peak memory 191920 kb
Host smart-be47de5a-0e1e-4887-b366-1d2f2d09e2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813514787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.813514787
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2097568114
Short name T267
Test name
Test status
Simulation time 607542217 ps
CPU time 0.7 seconds
Started Jun 04 01:27:58 PM PDT 24
Finished Jun 04 01:28:00 PM PDT 24
Peak memory 191780 kb
Host smart-f37f274a-6437-4d3b-84e7-83cad260c3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097568114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2097568114
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1748638094
Short name T259
Test name
Test status
Simulation time 30821785531 ps
CPU time 46.46 seconds
Started Jun 04 01:28:05 PM PDT 24
Finished Jun 04 01:28:53 PM PDT 24
Peak memory 191928 kb
Host smart-1325656c-b50c-4999-a321-daae82c6e266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748638094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1748638094
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1017364495
Short name T17
Test name
Test status
Simulation time 8264948373 ps
CPU time 4.02 seconds
Started Jun 04 01:28:08 PM PDT 24
Finished Jun 04 01:28:13 PM PDT 24
Peak memory 215660 kb
Host smart-0414bc26-8bf2-43bb-94ef-369c69cb3163
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017364495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1017364495
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.47292087
Short name T275
Test name
Test status
Simulation time 409917978 ps
CPU time 0.88 seconds
Started Jun 04 01:28:07 PM PDT 24
Finished Jun 04 01:28:08 PM PDT 24
Peak memory 191788 kb
Host smart-754e47d0-6942-41b3-be1b-419327de04f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47292087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.47292087
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3939367977
Short name T218
Test name
Test status
Simulation time 58974323565 ps
CPU time 18.21 seconds
Started Jun 04 01:28:43 PM PDT 24
Finished Jun 04 01:29:03 PM PDT 24
Peak memory 191928 kb
Host smart-60cff55e-d12f-4a96-8822-8a37fbf904a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939367977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3939367977
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1551319328
Short name T243
Test name
Test status
Simulation time 399502073 ps
CPU time 1.2 seconds
Started Jun 04 01:28:43 PM PDT 24
Finished Jun 04 01:28:45 PM PDT 24
Peak memory 191776 kb
Host smart-33cadb91-a15f-403e-8e99-041112ed81d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551319328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1551319328
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3335430624
Short name T2
Test name
Test status
Simulation time 15708998104 ps
CPU time 21.28 seconds
Started Jun 04 01:28:45 PM PDT 24
Finished Jun 04 01:29:07 PM PDT 24
Peak memory 191916 kb
Host smart-504e7055-aa08-49dc-89a4-99af3164828a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335430624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3335430624
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1509983580
Short name T187
Test name
Test status
Simulation time 406211412 ps
CPU time 0.71 seconds
Started Jun 04 01:28:45 PM PDT 24
Finished Jun 04 01:28:46 PM PDT 24
Peak memory 191768 kb
Host smart-89237d01-f613-45b8-bc99-e1336d8572d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509983580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1509983580
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1211549580
Short name T204
Test name
Test status
Simulation time 55991153603 ps
CPU time 76.67 seconds
Started Jun 04 01:28:55 PM PDT 24
Finished Jun 04 01:30:12 PM PDT 24
Peak memory 191840 kb
Host smart-7a5192d8-b521-40b2-9855-4c510717f985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211549580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1211549580
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2589371535
Short name T23
Test name
Test status
Simulation time 420638308 ps
CPU time 0.76 seconds
Started Jun 04 01:28:45 PM PDT 24
Finished Jun 04 01:28:46 PM PDT 24
Peak memory 191796 kb
Host smart-0d22af09-dc6e-4446-907a-304587a4a350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589371535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2589371535
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2173324671
Short name T179
Test name
Test status
Simulation time 519422178 ps
CPU time 0.77 seconds
Started Jun 04 01:28:53 PM PDT 24
Finished Jun 04 01:28:54 PM PDT 24
Peak memory 196376 kb
Host smart-a2895353-20c5-4556-ad1e-36cbd9d45908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173324671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2173324671
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3165586033
Short name T227
Test name
Test status
Simulation time 40099775902 ps
CPU time 13.81 seconds
Started Jun 04 01:28:54 PM PDT 24
Finished Jun 04 01:29:09 PM PDT 24
Peak memory 191844 kb
Host smart-c7aeebb0-23ce-483f-9cc0-843d6221fe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165586033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3165586033
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1918528242
Short name T238
Test name
Test status
Simulation time 594525579 ps
CPU time 0.82 seconds
Started Jun 04 01:28:54 PM PDT 24
Finished Jun 04 01:28:55 PM PDT 24
Peak memory 191724 kb
Host smart-e9157488-c3f5-4969-9d9b-c76dee7459e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918528242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1918528242
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.488194322
Short name T6
Test name
Test status
Simulation time 17349874592 ps
CPU time 5.71 seconds
Started Jun 04 01:28:53 PM PDT 24
Finished Jun 04 01:28:59 PM PDT 24
Peak memory 191928 kb
Host smart-52db6360-fa12-400a-9556-22eb920be86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488194322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.488194322
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3461476265
Short name T232
Test name
Test status
Simulation time 597806776 ps
CPU time 0.64 seconds
Started Jun 04 01:28:54 PM PDT 24
Finished Jun 04 01:28:56 PM PDT 24
Peak memory 191796 kb
Host smart-af5fb444-1390-4777-880b-0abe5f017db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461476265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3461476265
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1406435709
Short name T242
Test name
Test status
Simulation time 15215903322 ps
CPU time 5.71 seconds
Started Jun 04 01:28:59 PM PDT 24
Finished Jun 04 01:29:05 PM PDT 24
Peak memory 191920 kb
Host smart-80a58367-3473-42bf-942b-e3f962eba86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406435709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1406435709
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1421946497
Short name T192
Test name
Test status
Simulation time 568698724 ps
CPU time 0.8 seconds
Started Jun 04 01:29:01 PM PDT 24
Finished Jun 04 01:29:03 PM PDT 24
Peak memory 191788 kb
Host smart-7c2684ee-0e07-4bce-b0f4-14a5dae7725d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421946497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1421946497
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1322241923
Short name T277
Test name
Test status
Simulation time 4635633902 ps
CPU time 3.84 seconds
Started Jun 04 01:29:03 PM PDT 24
Finished Jun 04 01:29:07 PM PDT 24
Peak memory 191912 kb
Host smart-308bff56-ab00-49eb-b837-04de74dfe8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322241923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1322241923
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3171744744
Short name T247
Test name
Test status
Simulation time 436220888 ps
CPU time 0.75 seconds
Started Jun 04 01:29:03 PM PDT 24
Finished Jun 04 01:29:04 PM PDT 24
Peak memory 191800 kb
Host smart-2c016e17-4848-4aac-b309-a4b94ad2c720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171744744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3171744744
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.4263031443
Short name T223
Test name
Test status
Simulation time 47716265463 ps
CPU time 12.48 seconds
Started Jun 04 01:29:02 PM PDT 24
Finished Jun 04 01:29:15 PM PDT 24
Peak memory 191916 kb
Host smart-93b06d9b-f786-45b2-9b0e-f180565925ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263031443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.4263031443
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.4266042362
Short name T211
Test name
Test status
Simulation time 419838233 ps
CPU time 1.18 seconds
Started Jun 04 01:29:01 PM PDT 24
Finished Jun 04 01:29:03 PM PDT 24
Peak memory 191768 kb
Host smart-f92ab0ff-068f-4dc5-8240-8a0bde7219cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266042362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.4266042362
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.50299153
Short name T206
Test name
Test status
Simulation time 51580304928 ps
CPU time 20.06 seconds
Started Jun 04 01:28:59 PM PDT 24
Finished Jun 04 01:29:20 PM PDT 24
Peak memory 191864 kb
Host smart-4c415d83-af3f-4497-96a1-6acb9c923914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50299153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.50299153
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2298352096
Short name T193
Test name
Test status
Simulation time 502063720 ps
CPU time 0.84 seconds
Started Jun 04 01:29:00 PM PDT 24
Finished Jun 04 01:29:01 PM PDT 24
Peak memory 191716 kb
Host smart-2de96056-b0fe-405c-82fb-a20f03ac6a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298352096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2298352096
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.485210173
Short name T20
Test name
Test status
Simulation time 5928197405 ps
CPU time 5.12 seconds
Started Jun 04 01:29:06 PM PDT 24
Finished Jun 04 01:29:12 PM PDT 24
Peak memory 191888 kb
Host smart-2212c64d-7a6f-4f00-9642-f71a180d89cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485210173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.485210173
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2701545104
Short name T200
Test name
Test status
Simulation time 444221592 ps
CPU time 0.88 seconds
Started Jun 04 01:29:06 PM PDT 24
Finished Jun 04 01:29:08 PM PDT 24
Peak memory 191736 kb
Host smart-4a74153f-7a58-4841-988b-39e00e0af480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701545104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2701545104
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1739945960
Short name T245
Test name
Test status
Simulation time 6540065869 ps
CPU time 4.91 seconds
Started Jun 04 01:28:15 PM PDT 24
Finished Jun 04 01:28:21 PM PDT 24
Peak memory 191920 kb
Host smart-208feef3-7de7-49de-a02b-c1bcda1a07fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739945960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1739945960
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2388779408
Short name T15
Test name
Test status
Simulation time 8437937942 ps
CPU time 3.92 seconds
Started Jun 04 01:28:15 PM PDT 24
Finished Jun 04 01:28:20 PM PDT 24
Peak memory 215760 kb
Host smart-bf501301-5f69-44f4-b8f2-4594ef2d1c69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388779408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2388779408
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1479030661
Short name T255
Test name
Test status
Simulation time 462042954 ps
CPU time 1.29 seconds
Started Jun 04 01:28:07 PM PDT 24
Finished Jun 04 01:28:10 PM PDT 24
Peak memory 191800 kb
Host smart-c8bd74c2-4b11-4c49-bdc3-3eaff466069b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479030661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1479030661
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2393245662
Short name T254
Test name
Test status
Simulation time 50861407841 ps
CPU time 76.03 seconds
Started Jun 04 01:29:08 PM PDT 24
Finished Jun 04 01:30:25 PM PDT 24
Peak memory 191920 kb
Host smart-e3245a4d-0388-4f95-a3a7-5bcafc56ab61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393245662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2393245662
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3985646826
Short name T253
Test name
Test status
Simulation time 483897573 ps
CPU time 0.89 seconds
Started Jun 04 01:29:07 PM PDT 24
Finished Jun 04 01:29:09 PM PDT 24
Peak memory 191724 kb
Host smart-d2600715-38a2-440f-86dc-6609c3fa0e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985646826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3985646826
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.4282226836
Short name T214
Test name
Test status
Simulation time 95650378856 ps
CPU time 177.33 seconds
Started Jun 04 01:29:10 PM PDT 24
Finished Jun 04 01:32:08 PM PDT 24
Peak memory 214660 kb
Host smart-b94af478-5c19-4211-84ef-c9a05d2385db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282226836 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.4282226836
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2709468604
Short name T225
Test name
Test status
Simulation time 16705174364 ps
CPU time 25.17 seconds
Started Jun 04 01:29:10 PM PDT 24
Finished Jun 04 01:29:35 PM PDT 24
Peak memory 191844 kb
Host smart-85fcb653-2d69-43e0-811a-eedb2aaa7a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709468604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2709468604
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3136097662
Short name T258
Test name
Test status
Simulation time 378146568 ps
CPU time 0.73 seconds
Started Jun 04 01:29:10 PM PDT 24
Finished Jun 04 01:29:11 PM PDT 24
Peak memory 191808 kb
Host smart-bd90c80a-3806-4d6a-8740-c9f0f8dcce1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136097662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3136097662
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1821275525
Short name T209
Test name
Test status
Simulation time 907503284 ps
CPU time 2.14 seconds
Started Jun 04 01:29:07 PM PDT 24
Finished Jun 04 01:29:10 PM PDT 24
Peak memory 191796 kb
Host smart-603034f2-e0b4-408d-a71b-781262fa1cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821275525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1821275525
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1253612432
Short name T205
Test name
Test status
Simulation time 525339018 ps
CPU time 0.73 seconds
Started Jun 04 01:29:08 PM PDT 24
Finished Jun 04 01:29:09 PM PDT 24
Peak memory 191800 kb
Host smart-f9f8b193-b170-4b80-85a3-30f677252750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253612432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1253612432
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3373870195
Short name T22
Test name
Test status
Simulation time 52559849437 ps
CPU time 7.32 seconds
Started Jun 04 01:29:14 PM PDT 24
Finished Jun 04 01:29:21 PM PDT 24
Peak memory 191888 kb
Host smart-47beec6c-34b8-4398-a26e-8e85547b92b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373870195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3373870195
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.4136008432
Short name T261
Test name
Test status
Simulation time 487908892 ps
CPU time 1.24 seconds
Started Jun 04 01:29:18 PM PDT 24
Finished Jun 04 01:29:20 PM PDT 24
Peak memory 191740 kb
Host smart-67c747a4-7559-49ea-8e50-1ae8aa8beba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136008432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.4136008432
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3288134694
Short name T226
Test name
Test status
Simulation time 24274112360 ps
CPU time 40.71 seconds
Started Jun 04 01:29:15 PM PDT 24
Finished Jun 04 01:29:56 PM PDT 24
Peak memory 191976 kb
Host smart-b27abd83-b145-437d-b7da-6dccb27affdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288134694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3288134694
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1053358441
Short name T251
Test name
Test status
Simulation time 549823449 ps
CPU time 0.77 seconds
Started Jun 04 01:29:16 PM PDT 24
Finished Jun 04 01:29:17 PM PDT 24
Peak memory 191792 kb
Host smart-1ee36a9a-1f86-40cd-8031-62f472f358c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053358441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1053358441
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1376727665
Short name T220
Test name
Test status
Simulation time 30205041963 ps
CPU time 9.1 seconds
Started Jun 04 01:29:21 PM PDT 24
Finished Jun 04 01:29:31 PM PDT 24
Peak memory 191896 kb
Host smart-397b724b-bea3-4124-b8c0-9d926ff1a4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376727665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1376727665
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2578159202
Short name T260
Test name
Test status
Simulation time 379535768 ps
CPU time 1.08 seconds
Started Jun 04 01:29:15 PM PDT 24
Finished Jun 04 01:29:16 PM PDT 24
Peak memory 191760 kb
Host smart-5d906a93-aa28-45dd-a154-0184e41d4d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578159202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2578159202
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1684271488
Short name T215
Test name
Test status
Simulation time 33963442471 ps
CPU time 13.84 seconds
Started Jun 04 01:29:22 PM PDT 24
Finished Jun 04 01:29:36 PM PDT 24
Peak memory 191892 kb
Host smart-1debf22b-9362-41a4-8a3f-b842c3a427d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684271488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1684271488
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1529992367
Short name T224
Test name
Test status
Simulation time 416888613 ps
CPU time 0.72 seconds
Started Jun 04 01:29:20 PM PDT 24
Finished Jun 04 01:29:22 PM PDT 24
Peak memory 191812 kb
Host smart-a014b86b-df90-4e28-a79e-07c1e91044e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529992367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1529992367
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.912872567
Short name T273
Test name
Test status
Simulation time 40085591973 ps
CPU time 53.79 seconds
Started Jun 04 01:29:23 PM PDT 24
Finished Jun 04 01:30:18 PM PDT 24
Peak memory 191920 kb
Host smart-68be09fd-a327-40ea-84cb-64a9d3d5f0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912872567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.912872567
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.554611528
Short name T268
Test name
Test status
Simulation time 350216850 ps
CPU time 1.15 seconds
Started Jun 04 01:29:23 PM PDT 24
Finished Jun 04 01:29:25 PM PDT 24
Peak memory 191792 kb
Host smart-4439a2ad-db8b-4748-ad41-46563f4ba96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554611528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.554611528
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1865093869
Short name T229
Test name
Test status
Simulation time 16510248330 ps
CPU time 13.46 seconds
Started Jun 04 01:29:28 PM PDT 24
Finished Jun 04 01:29:42 PM PDT 24
Peak memory 191896 kb
Host smart-8e9e7e11-8b3e-4464-b89a-91864f7b10f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865093869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1865093869
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2512558179
Short name T21
Test name
Test status
Simulation time 413591851 ps
CPU time 0.76 seconds
Started Jun 04 01:29:21 PM PDT 24
Finished Jun 04 01:29:23 PM PDT 24
Peak memory 191752 kb
Host smart-2372234e-7740-42cb-a2fa-a6ec0cc54955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512558179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2512558179
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3686032286
Short name T199
Test name
Test status
Simulation time 227535221874 ps
CPU time 94.44 seconds
Started Jun 04 01:29:32 PM PDT 24
Finished Jun 04 01:31:06 PM PDT 24
Peak memory 184164 kb
Host smart-a6c9a93f-bed5-4704-8a5a-ba39936f6e0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686032286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3686032286
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3963373046
Short name T256
Test name
Test status
Simulation time 26354730118 ps
CPU time 22.94 seconds
Started Jun 04 01:29:29 PM PDT 24
Finished Jun 04 01:29:53 PM PDT 24
Peak memory 191920 kb
Host smart-1e9a7c5e-0225-49e3-a433-923172c3e7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963373046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3963373046
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2407145939
Short name T189
Test name
Test status
Simulation time 388636920 ps
CPU time 0.74 seconds
Started Jun 04 01:29:30 PM PDT 24
Finished Jun 04 01:29:31 PM PDT 24
Peak memory 191792 kb
Host smart-038da5c2-967d-424a-bd5e-2a7259fdb57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407145939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2407145939
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.32219535
Short name T264
Test name
Test status
Simulation time 41659218769 ps
CPU time 7.01 seconds
Started Jun 04 01:28:11 PM PDT 24
Finished Jun 04 01:28:19 PM PDT 24
Peak memory 191920 kb
Host smart-062eac0a-e3cf-47f9-ae74-15883f8a767f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32219535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.32219535
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2635583842
Short name T16
Test name
Test status
Simulation time 3886690953 ps
CPU time 6.9 seconds
Started Jun 04 01:28:21 PM PDT 24
Finished Jun 04 01:28:28 PM PDT 24
Peak memory 215352 kb
Host smart-57f5dd86-e751-446a-b73a-2ab083b47e43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635583842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2635583842
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2426080582
Short name T236
Test name
Test status
Simulation time 413488310 ps
CPU time 0.71 seconds
Started Jun 04 01:28:12 PM PDT 24
Finished Jun 04 01:28:13 PM PDT 24
Peak memory 191724 kb
Host smart-c8390345-7ffa-4289-856e-087047c94247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426080582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2426080582
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3598741554
Short name T216
Test name
Test status
Simulation time 19002880177 ps
CPU time 8.72 seconds
Started Jun 04 01:29:30 PM PDT 24
Finished Jun 04 01:29:39 PM PDT 24
Peak memory 191936 kb
Host smart-fd792dcc-0120-47ca-a88b-00ae8076a8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598741554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3598741554
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.367198948
Short name T274
Test name
Test status
Simulation time 557777398 ps
CPU time 0.73 seconds
Started Jun 04 01:29:29 PM PDT 24
Finished Jun 04 01:29:31 PM PDT 24
Peak memory 191792 kb
Host smart-783d442c-49ef-422e-9dc4-4fa945d907b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367198948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.367198948
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2479890638
Short name T239
Test name
Test status
Simulation time 15560733868 ps
CPU time 25.04 seconds
Started Jun 04 01:29:31 PM PDT 24
Finished Jun 04 01:29:57 PM PDT 24
Peak memory 191912 kb
Host smart-6139ff9a-b20c-496d-ad97-9ecc4f1b3938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479890638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2479890638
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3730285245
Short name T249
Test name
Test status
Simulation time 435850419 ps
CPU time 0.69 seconds
Started Jun 04 01:29:30 PM PDT 24
Finished Jun 04 01:29:32 PM PDT 24
Peak memory 191808 kb
Host smart-bda584c4-473b-47dc-b43f-90ddd42689fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730285245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3730285245
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2159621997
Short name T198
Test name
Test status
Simulation time 2204354013 ps
CPU time 4.12 seconds
Started Jun 04 01:29:38 PM PDT 24
Finished Jun 04 01:29:42 PM PDT 24
Peak memory 191864 kb
Host smart-a79f9fc6-6c10-4a16-8e0e-ea3f5decd8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159621997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2159621997
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2033812547
Short name T219
Test name
Test status
Simulation time 394237738 ps
CPU time 0.88 seconds
Started Jun 04 01:29:38 PM PDT 24
Finished Jun 04 01:29:39 PM PDT 24
Peak memory 191776 kb
Host smart-62c90ac9-748d-4ced-8cdb-fcb1046cec40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033812547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2033812547
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1260920754
Short name T240
Test name
Test status
Simulation time 40281157794 ps
CPU time 7.54 seconds
Started Jun 04 01:29:37 PM PDT 24
Finished Jun 04 01:29:45 PM PDT 24
Peak memory 191920 kb
Host smart-2b91463d-95ea-486d-90dd-52dd0b902d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260920754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1260920754
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1017906469
Short name T237
Test name
Test status
Simulation time 354896703 ps
CPU time 0.67 seconds
Started Jun 04 01:29:38 PM PDT 24
Finished Jun 04 01:29:39 PM PDT 24
Peak memory 191808 kb
Host smart-bd83fec3-2113-4fa5-8093-5a2fc504f0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017906469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1017906469
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2829165323
Short name T152
Test name
Test status
Simulation time 459327169 ps
CPU time 0.79 seconds
Started Jun 04 01:29:38 PM PDT 24
Finished Jun 04 01:29:40 PM PDT 24
Peak memory 196440 kb
Host smart-61bdb4cf-c543-4efc-a5b2-144d95d9ee3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829165323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2829165323
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2158331326
Short name T252
Test name
Test status
Simulation time 34341283980 ps
CPU time 30.85 seconds
Started Jun 04 01:29:39 PM PDT 24
Finished Jun 04 01:30:11 PM PDT 24
Peak memory 191844 kb
Host smart-7e30dcb2-c9ff-4b8f-aaec-af866d8ad3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158331326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2158331326
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1078170198
Short name T222
Test name
Test status
Simulation time 515347823 ps
CPU time 0.93 seconds
Started Jun 04 01:29:40 PM PDT 24
Finished Jun 04 01:29:42 PM PDT 24
Peak memory 191800 kb
Host smart-d7ae9ff4-c894-4856-8ce7-804d73aaa076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078170198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1078170198
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.747531747
Short name T244
Test name
Test status
Simulation time 1927993896 ps
CPU time 1.3 seconds
Started Jun 04 01:29:51 PM PDT 24
Finished Jun 04 01:29:53 PM PDT 24
Peak memory 191804 kb
Host smart-3848e9f5-da59-4504-808f-444b3beb3097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747531747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.747531747
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2063749117
Short name T262
Test name
Test status
Simulation time 456024952 ps
CPU time 1.27 seconds
Started Jun 04 01:29:48 PM PDT 24
Finished Jun 04 01:29:50 PM PDT 24
Peak memory 191760 kb
Host smart-71b726f8-7b86-4a05-a730-8c3b7c52a994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063749117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2063749117
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2584205809
Short name T176
Test name
Test status
Simulation time 399921139 ps
CPU time 1.24 seconds
Started Jun 04 01:29:49 PM PDT 24
Finished Jun 04 01:29:50 PM PDT 24
Peak memory 196416 kb
Host smart-5e53d073-118a-49c6-b9fe-2da098cdc03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584205809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2584205809
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1098187440
Short name T202
Test name
Test status
Simulation time 10122948516 ps
CPU time 15.27 seconds
Started Jun 04 01:29:49 PM PDT 24
Finished Jun 04 01:30:05 PM PDT 24
Peak memory 191920 kb
Host smart-cfe6ace5-db80-44e1-a441-aee7291dd734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098187440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1098187440
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1053383674
Short name T212
Test name
Test status
Simulation time 537793020 ps
CPU time 1.35 seconds
Started Jun 04 01:29:45 PM PDT 24
Finished Jun 04 01:29:47 PM PDT 24
Peak memory 191680 kb
Host smart-4417edea-76db-45f0-b683-87e6c2c402af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053383674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1053383674
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.137835627
Short name T44
Test name
Test status
Simulation time 35485594478 ps
CPU time 12.26 seconds
Started Jun 04 01:29:45 PM PDT 24
Finished Jun 04 01:29:58 PM PDT 24
Peak memory 191844 kb
Host smart-86d6cde3-e329-4290-97f3-914b2044468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137835627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.137835627
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.407935190
Short name T221
Test name
Test status
Simulation time 536013972 ps
CPU time 1.03 seconds
Started Jun 04 01:29:51 PM PDT 24
Finished Jun 04 01:29:53 PM PDT 24
Peak memory 191808 kb
Host smart-4005b675-e608-4ac0-b425-6aa92016037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407935190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.407935190
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3426143169
Short name T233
Test name
Test status
Simulation time 18084911063 ps
CPU time 5.58 seconds
Started Jun 04 01:29:47 PM PDT 24
Finished Jun 04 01:29:53 PM PDT 24
Peak memory 191908 kb
Host smart-cf8e80a7-2064-4fb6-a6ed-ae1f840379b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426143169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3426143169
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2327974777
Short name T266
Test name
Test status
Simulation time 579341784 ps
CPU time 0.83 seconds
Started Jun 04 01:29:48 PM PDT 24
Finished Jun 04 01:29:50 PM PDT 24
Peak memory 191792 kb
Host smart-404797de-03b1-4e80-a164-bc35fafd9cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327974777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2327974777
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3194008134
Short name T175
Test name
Test status
Simulation time 401376936 ps
CPU time 0.72 seconds
Started Jun 04 01:30:01 PM PDT 24
Finished Jun 04 01:30:02 PM PDT 24
Peak memory 196388 kb
Host smart-b9941fd4-64ec-4098-ad7d-9cf2db8e506d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194008134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3194008134
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.662089973
Short name T230
Test name
Test status
Simulation time 15595910217 ps
CPU time 22.53 seconds
Started Jun 04 01:29:54 PM PDT 24
Finished Jun 04 01:30:17 PM PDT 24
Peak memory 191892 kb
Host smart-17136dba-906f-4b7a-ab26-b510aca3e07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662089973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.662089973
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2603004935
Short name T49
Test name
Test status
Simulation time 546830340 ps
CPU time 1.36 seconds
Started Jun 04 01:29:55 PM PDT 24
Finished Jun 04 01:29:57 PM PDT 24
Peak memory 191724 kb
Host smart-e69a47f4-ced2-449a-9bb2-020024b35bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603004935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2603004935
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3357788914
Short name T196
Test name
Test status
Simulation time 12438540340 ps
CPU time 18.46 seconds
Started Jun 04 01:28:24 PM PDT 24
Finished Jun 04 01:28:43 PM PDT 24
Peak memory 191940 kb
Host smart-1cb4932e-9928-4f07-b13f-f88322516f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357788914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3357788914
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3301974720
Short name T18
Test name
Test status
Simulation time 7355959738 ps
CPU time 12.42 seconds
Started Jun 04 01:28:24 PM PDT 24
Finished Jun 04 01:28:37 PM PDT 24
Peak memory 215688 kb
Host smart-833c5495-3565-4886-b768-5ca1337bc579
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301974720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3301974720
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2582192654
Short name T270
Test name
Test status
Simulation time 372515691 ps
CPU time 0.64 seconds
Started Jun 04 01:28:26 PM PDT 24
Finished Jun 04 01:28:28 PM PDT 24
Peak memory 191796 kb
Host smart-1186d8d9-5cd3-46ad-9376-b8d631e95583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582192654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2582192654
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.715095840
Short name T276
Test name
Test status
Simulation time 24279423195 ps
CPU time 10.19 seconds
Started Jun 04 01:29:54 PM PDT 24
Finished Jun 04 01:30:05 PM PDT 24
Peak memory 191916 kb
Host smart-7cc47560-77d5-4728-9907-affbb7ccf8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715095840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.715095840
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.987258123
Short name T271
Test name
Test status
Simulation time 557667027 ps
CPU time 0.99 seconds
Started Jun 04 01:29:57 PM PDT 24
Finished Jun 04 01:29:58 PM PDT 24
Peak memory 191808 kb
Host smart-bfc6a5d9-4235-42f1-bd09-c94991458c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987258123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.987258123
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1287416898
Short name T191
Test name
Test status
Simulation time 6184080934 ps
CPU time 3.38 seconds
Started Jun 04 01:29:55 PM PDT 24
Finished Jun 04 01:29:59 PM PDT 24
Peak memory 191932 kb
Host smart-31651ed9-c024-455c-a257-44ecb10cdba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287416898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1287416898
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3907264827
Short name T269
Test name
Test status
Simulation time 357843819 ps
CPU time 1.12 seconds
Started Jun 04 01:30:01 PM PDT 24
Finished Jun 04 01:30:02 PM PDT 24
Peak memory 191768 kb
Host smart-2c9ff532-a70b-4fab-90f2-df48a8a76504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907264827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3907264827
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.4155334296
Short name T250
Test name
Test status
Simulation time 49720061134 ps
CPU time 39.37 seconds
Started Jun 04 01:30:00 PM PDT 24
Finished Jun 04 01:30:40 PM PDT 24
Peak memory 191888 kb
Host smart-8b7d3357-601c-4969-974a-eef8bd56cfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155334296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.4155334296
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1769118238
Short name T12
Test name
Test status
Simulation time 437926455 ps
CPU time 0.65 seconds
Started Jun 04 01:29:54 PM PDT 24
Finished Jun 04 01:29:55 PM PDT 24
Peak memory 191768 kb
Host smart-f562d030-20e2-4ca9-9aa1-4a5deac1474e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769118238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1769118238
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3686400448
Short name T48
Test name
Test status
Simulation time 555462867 ps
CPU time 0.67 seconds
Started Jun 04 01:30:03 PM PDT 24
Finished Jun 04 01:30:05 PM PDT 24
Peak memory 196428 kb
Host smart-67368cc4-cc7e-415e-806d-66dc20fc6943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686400448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3686400448
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.4176828009
Short name T213
Test name
Test status
Simulation time 32661873394 ps
CPU time 51.85 seconds
Started Jun 04 01:30:01 PM PDT 24
Finished Jun 04 01:30:53 PM PDT 24
Peak memory 191888 kb
Host smart-88cbd371-c993-446d-bd01-2483d9659552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176828009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.4176828009
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3892277711
Short name T231
Test name
Test status
Simulation time 374483591 ps
CPU time 0.91 seconds
Started Jun 04 01:30:01 PM PDT 24
Finished Jun 04 01:30:03 PM PDT 24
Peak memory 191768 kb
Host smart-4e6a63b8-4316-4062-b32a-a28e7dabe5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892277711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3892277711
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1919877560
Short name T234
Test name
Test status
Simulation time 42845424612 ps
CPU time 32.63 seconds
Started Jun 04 01:30:01 PM PDT 24
Finished Jun 04 01:30:34 PM PDT 24
Peak memory 191888 kb
Host smart-cbb648ca-cf2a-42f2-a382-5bb783d317e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919877560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1919877560
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.540414793
Short name T265
Test name
Test status
Simulation time 412986020 ps
CPU time 1.19 seconds
Started Jun 04 01:30:03 PM PDT 24
Finished Jun 04 01:30:05 PM PDT 24
Peak memory 191800 kb
Host smart-d0c174a7-d6e1-40d1-8e5e-ec8bb1adf928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540414793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.540414793
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.65703625
Short name T217
Test name
Test status
Simulation time 57053738401 ps
CPU time 22.47 seconds
Started Jun 04 01:30:03 PM PDT 24
Finished Jun 04 01:30:26 PM PDT 24
Peak memory 191920 kb
Host smart-f00189d4-53ee-49a0-858a-df861ca9b430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65703625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.65703625
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.968786081
Short name T188
Test name
Test status
Simulation time 598352651 ps
CPU time 1.04 seconds
Started Jun 04 01:30:01 PM PDT 24
Finished Jun 04 01:30:02 PM PDT 24
Peak memory 191808 kb
Host smart-0ff31c29-09f7-4d10-995a-219a739ab1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968786081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.968786081
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3553170086
Short name T210
Test name
Test status
Simulation time 52708965688 ps
CPU time 34.97 seconds
Started Jun 04 01:30:16 PM PDT 24
Finished Jun 04 01:30:52 PM PDT 24
Peak memory 191860 kb
Host smart-968dfed3-db7f-4476-b142-c96f374012ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553170086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3553170086
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1887224587
Short name T195
Test name
Test status
Simulation time 485013177 ps
CPU time 0.75 seconds
Started Jun 04 01:30:01 PM PDT 24
Finished Jun 04 01:30:03 PM PDT 24
Peak memory 191768 kb
Host smart-f61f9e78-c803-49c1-adb3-d485ca9bba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887224587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1887224587
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1723983312
Short name T208
Test name
Test status
Simulation time 28994941904 ps
CPU time 38.39 seconds
Started Jun 04 01:30:13 PM PDT 24
Finished Jun 04 01:30:52 PM PDT 24
Peak memory 191928 kb
Host smart-06020309-29cd-4d8d-ace7-07e59655af4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723983312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1723983312
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2403259298
Short name T194
Test name
Test status
Simulation time 490843679 ps
CPU time 0.74 seconds
Started Jun 04 01:30:10 PM PDT 24
Finished Jun 04 01:30:12 PM PDT 24
Peak memory 191848 kb
Host smart-c2992959-1440-4bb7-a132-0ccd5188f170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403259298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2403259298
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3636875917
Short name T207
Test name
Test status
Simulation time 2588725200 ps
CPU time 2.15 seconds
Started Jun 04 01:30:10 PM PDT 24
Finished Jun 04 01:30:13 PM PDT 24
Peak memory 192028 kb
Host smart-c2ca8414-2c9f-4f56-a466-d21f2fa849f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636875917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3636875917
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.253372188
Short name T75
Test name
Test status
Simulation time 520183012 ps
CPU time 0.93 seconds
Started Jun 04 01:30:14 PM PDT 24
Finished Jun 04 01:30:15 PM PDT 24
Peak memory 191792 kb
Host smart-974cf97d-f0c2-4673-a936-5c7841e1a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253372188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.253372188
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3414693180
Short name T248
Test name
Test status
Simulation time 49791567142 ps
CPU time 327.86 seconds
Started Jun 04 01:30:10 PM PDT 24
Finished Jun 04 01:35:39 PM PDT 24
Peak memory 206776 kb
Host smart-6d90d22c-4ddd-430d-913e-9291f7b2a651
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414693180 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3414693180
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3144142613
Short name T228
Test name
Test status
Simulation time 26397493681 ps
CPU time 9.1 seconds
Started Jun 04 01:30:18 PM PDT 24
Finished Jun 04 01:30:28 PM PDT 24
Peak memory 191896 kb
Host smart-ca56db8b-2da8-46ea-b0d6-5f0e6bcd6ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144142613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3144142613
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.4115955125
Short name T246
Test name
Test status
Simulation time 485210004 ps
CPU time 0.78 seconds
Started Jun 04 01:30:11 PM PDT 24
Finished Jun 04 01:30:12 PM PDT 24
Peak memory 191808 kb
Host smart-3de00948-da3e-432d-a3af-ce981e78125a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115955125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4115955125
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1658777242
Short name T272
Test name
Test status
Simulation time 26865515156 ps
CPU time 34.1 seconds
Started Jun 04 01:28:21 PM PDT 24
Finished Jun 04 01:28:55 PM PDT 24
Peak memory 191900 kb
Host smart-41ea8588-8ad0-4307-84e1-b0694a397623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658777242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1658777242
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2117142447
Short name T203
Test name
Test status
Simulation time 518712748 ps
CPU time 1.39 seconds
Started Jun 04 01:28:22 PM PDT 24
Finished Jun 04 01:28:25 PM PDT 24
Peak memory 191724 kb
Host smart-4d34e8d1-3e77-4c1e-9fa0-df1b43462a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117142447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2117142447
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.198664635
Short name T257
Test name
Test status
Simulation time 19028791807 ps
CPU time 26.9 seconds
Started Jun 04 01:28:22 PM PDT 24
Finished Jun 04 01:28:50 PM PDT 24
Peak memory 191920 kb
Host smart-22af71bc-f52a-4984-8983-2e79efbce057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198664635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.198664635
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2557190421
Short name T197
Test name
Test status
Simulation time 596541432 ps
CPU time 0.79 seconds
Started Jun 04 01:28:24 PM PDT 24
Finished Jun 04 01:28:26 PM PDT 24
Peak memory 191796 kb
Host smart-4f15baa9-bba2-42fb-a6d7-ec4e2a41ce87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557190421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2557190421
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.601785886
Short name T190
Test name
Test status
Simulation time 5877130389 ps
CPU time 9.18 seconds
Started Jun 04 01:28:29 PM PDT 24
Finished Jun 04 01:28:39 PM PDT 24
Peak memory 191936 kb
Host smart-0088646c-3431-4c66-bbac-15cf631e5569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601785886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.601785886
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2393128238
Short name T201
Test name
Test status
Simulation time 429272765 ps
CPU time 0.89 seconds
Started Jun 04 01:28:28 PM PDT 24
Finished Jun 04 01:28:30 PM PDT 24
Peak memory 191768 kb
Host smart-8f1c0ae6-cf4c-4cad-9c95-de54a1ee5711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393128238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2393128238
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.57677143
Short name T7
Test name
Test status
Simulation time 21911466272 ps
CPU time 9.31 seconds
Started Jun 04 01:28:31 PM PDT 24
Finished Jun 04 01:28:41 PM PDT 24
Peak memory 191920 kb
Host smart-edadb045-977c-447a-a0d6-9229d3ef27bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57677143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.57677143
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3480566807
Short name T235
Test name
Test status
Simulation time 522958836 ps
CPU time 1.2 seconds
Started Jun 04 01:28:29 PM PDT 24
Finished Jun 04 01:28:31 PM PDT 24
Peak memory 191792 kb
Host smart-6b4485fe-5d96-4184-95de-acdf7229f653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480566807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3480566807
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1342498267
Short name T241
Test name
Test status
Simulation time 35667728005 ps
CPU time 54.68 seconds
Started Jun 04 01:28:36 PM PDT 24
Finished Jun 04 01:29:31 PM PDT 24
Peak memory 191924 kb
Host smart-c2aafe7e-e7a4-4497-85f2-e68c762ee371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342498267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1342498267
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2978577270
Short name T263
Test name
Test status
Simulation time 367573511 ps
CPU time 0.74 seconds
Started Jun 04 01:28:35 PM PDT 24
Finished Jun 04 01:28:37 PM PDT 24
Peak memory 191804 kb
Host smart-33d72707-e065-4e14-ad88-b3b392a78eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978577270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2978577270
Directory /workspace/9.aon_timer_smoke/latest
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