Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	27209	1		T1	12		T2	136		T3	12
bark[1]	640	1		T31	380		T25	21		T40	21
bark[2]	905	1		T22	21		T24	26		T89	21
bark[3]	653	1		T12	26		T32	21		T24	214
bark[4]	609	1		T2	21		T31	300		T87	30
bark[5]	1399	1		T11	26		T39	187		T99	47
bark[6]	1046	1		T106	40		T124	14		T87	26
bark[7]	483	1		T188	14		T165	89		T121	268
bark[8]	502	1		T122	26		T119	21		T183	14
bark[9]	858	1		T11	31		T13	307		T44	14
bark[10]	402	1		T50	21		T25	30		T166	21
bark[11]	373	1		T11	21		T14	26		T109	125
bark[12]	271	1		T2	21		T31	35		T106	21
bark[13]	1032	1		T50	40		T132	14		T121	47
bark[14]	84	1		T32	21		T22	21		T42	7
bark[15]	633	1		T11	170		T14	31		T110	21
bark[16]	221	1		T31	95		T28	14		T111	21
bark[17]	208	1		T138	21		T95	21		T125	21
bark[18]	494	1		T2	21		T29	14		T13	87
bark[19]	861	1		T41	21		T42	272		T194	14
bark[20]	1037	1		T42	139		T121	21		T125	21
bark[21]	831	1		T31	428		T32	21		T50	21
bark[22]	297	1		T124	21		T172	14		T126	14
bark[23]	1034	1		T11	297		T32	21		T49	14
bark[24]	1005	1		T43	14		T163	26		T189	14
bark[25]	778	1		T11	21		T12	14		T50	21
bark[26]	498	1		T6	26		T41	47		T138	21
bark[27]	331	1		T32	21		T50	33		T148	21
bark[28]	526	1		T2	21		T31	21		T50	42
bark[29]	380	1		T22	21		T106	21		T87	95
bark[30]	318	1		T2	26		T26	14		T39	80
bark[31]	203	1		T31	21		T32	21		T122	21
bark_0	4576	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	25797	1		T1	11		T2	156		T3	11
bite[1]	989	1		T12	13		T31	21		T42	295
bite[2]	209	1		T50	42		T103	39		T104	13
bite[3]	457	1		T6	26		T106	21		T110	21
bite[4]	828	1		T12	26		T31	30		T32	21
bite[5]	923	1		T31	115		T39	79		T121	267
bite[6]	608	1		T11	21		T13	86		T14	25
bite[7]	402	1		T11	26		T41	25		T110	21
bite[8]	503	1		T22	21		T24	26		T39	102
bite[9]	576	1		T43	13		T25	21		T41	21
bite[10]	575	1		T2	21		T50	21		T163	4
bite[11]	1265	1		T2	21		T11	169		T31	242
bite[12]	661	1		T32	21		T163	26		T143	216
bite[13]	844	1		T22	21		T42	271		T99	26
bite[14]	796	1		T40	6		T126	13		T89	201
bite[15]	1071	1		T2	21		T29	13		T13	306
bite[16]	1144	1		T31	427		T87	532		T51	51
bite[17]	166	1		T31	21		T32	47		T25	30
bite[18]	927	1		T11	296		T106	21		T98	13
bite[19]	131	1		T11	21		T22	13		T143	30
bite[20]	375	1		T32	42		T25	21		T41	21
bite[21]	557	1		T11	31		T41	21		T124	129
bite[22]	592	1		T40	21		T122	26		T188	13
bite[23]	495	1		T117	21		T159	64		T149	13
bite[24]	1385	1		T50	21		T39	194		T148	256
bite[25]	391	1		T50	32		T165	21		T119	13
bite[26]	639	1		T14	30		T31	35		T26	13
bite[27]	459	1		T2	26		T44	13		T194	13
bite[28]	518	1		T49	13		T106	40		T87	21
bite[29]	490	1		T32	21		T50	21		T192	13
bite[30]	407	1		T31	21		T40	21		T41	255
bite[31]	433	1		T31	299		T189	13		T56	66
bite_0	5084	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	50697	1		T1	19		T2	253		T3	19

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	926	1		T11	19		T50	19		T42	19
prescale[1]	686	1		T6	29		T31	160		T38	19
prescale[2]	1210	1		T50	19		T22	32		T41	95
prescale[3]	851	1		T12	23		T38	86		T24	2
prescale[4]	748	1		T14	2		T32	24		T106	76
prescale[5]	1317	1		T11	58		T12	19		T13	33
prescale[6]	532	1		T11	38		T13	19		T46	9
prescale[7]	996	1		T11	2		T13	9		T31	103
prescale[8]	574	1		T11	23		T13	48		T38	37
prescale[9]	680	1		T9	9		T50	19		T38	19
prescale[10]	486	1		T6	28		T32	19		T138	28
prescale[11]	582	1		T31	37		T50	19		T42	19
prescale[12]	616	1		T50	19		T24	2		T40	4
prescale[13]	745	1		T1	9		T3	9		T11	2
prescale[14]	754	1		T11	19		T38	19		T24	4
prescale[15]	949	1		T2	18		T13	2		T31	48
prescale[16]	593	1		T11	53		T12	60		T38	2
prescale[17]	1088	1		T11	29		T31	28		T99	19
prescale[18]	654	1		T11	19		T50	23		T39	4
prescale[19]	547	1		T31	111		T24	25		T171	28
prescale[20]	924	1		T31	41		T50	23		T25	19
prescale[21]	493	1		T11	19		T31	95		T48	9
prescale[22]	691	1		T11	22		T14	2		T31	101
prescale[23]	646	1		T11	78		T14	2		T38	19
prescale[24]	519	1		T4	9		T13	2		T45	9
prescale[25]	609	1		T6	56		T31	19		T38	19
prescale[26]	914	1		T11	2		T31	109		T41	72
prescale[27]	906	1		T31	138		T38	14		T25	28
prescale[28]	762	1		T11	2		T47	9		T31	91
prescale[29]	1107	1		T2	28		T14	19		T31	222
prescale[30]	1010	1		T31	75		T38	2		T24	2
prescale[31]	851	1		T12	28		T40	29		T41	19
prescale_0	25731	1		T1	10		T2	207		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	38336	1		T1	9		T2	206		T3	19
auto[1]	12361	1		T1	10		T2	47		T5	9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	50697	1		T1	19		T2	253		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30358	1		T1	14		T2	138		T3	14
wkup[1]	221	1		T25	21		T138	30		T109	21
wkup[2]	224	1		T13	21		T50	21		T106	21
wkup[3]	202	1		T40	21		T87	30		T55	31
wkup[4]	332	1		T13	47		T50	21		T98	15
wkup[5]	187	1		T11	8		T13	21		T31	51
wkup[6]	236	1		T31	21		T143	8		T138	21
wkup[7]	322	1		T32	26		T22	21		T110	21
wkup[8]	120	1		T90	21		T51	15		T135	21
wkup[9]	132	1		T2	21		T31	26		T42	8
wkup[10]	337	1		T109	8		T121	21		T159	21
wkup[11]	387	1		T31	21		T22	21		T24	35
wkup[12]	157	1		T31	56		T122	21		T57	15
wkup[13]	209	1		T2	26		T31	42		T109	21
wkup[14]	376	1		T11	21		T44	15		T31	70
wkup[15]	230	1		T50	21		T40	14		T42	30
wkup[16]	228	1		T13	21		T31	21		T42	21
wkup[17]	282	1		T11	47		T90	21		T56	26
wkup[18]	197	1		T13	21		T124	21		T87	21
wkup[19]	192	1		T24	15		T138	21		T87	21
wkup[20]	317	1		T32	21		T24	15		T106	21
wkup[21]	245	1		T31	74		T24	30		T124	21
wkup[22]	133	1		T12	15		T41	21		T99	26
wkup[23]	304	1		T42	21		T87	21		T89	21
wkup[24]	230	1		T122	26		T138	21		T119	15
wkup[25]	114	1		T143	21		T91	21		T92	21
wkup[26]	156	1		T188	15		T170	15		T59	21
wkup[27]	276	1		T11	21		T13	21		T42	21
wkup[28]	210	1		T32	21		T166	21		T148	26
wkup[29]	296	1		T25	30		T42	21		T143	21
wkup[30]	351	1		T2	21		T11	21		T14	21
wkup[31]	329	1		T87	34		T148	21		T89	21
wkup[32]	202	1		T151	15		T109	21		T148	21
wkup[33]	362	1		T11	21		T31	21		T39	21
wkup[34]	360	1		T11	31		T25	21		T26	15
wkup[35]	553	1		T11	26		T31	42		T24	8
wkup[36]	267	1		T11	21		T25	21		T41	21
wkup[37]	194	1		T31	21		T50	21		T39	8
wkup[38]	337	1		T24	30		T42	51		T163	21
wkup[39]	176	1		T122	26		T87	21		T132	15
wkup[40]	200	1		T157	15		T90	8		T121	21
wkup[41]	310	1		T2	21		T31	21		T50	21
wkup[42]	287	1		T32	21		T39	21		T106	21
wkup[43]	342	1		T6	26		T11	26		T13	39
wkup[44]	481	1		T11	30		T31	42		T22	21
wkup[45]	377	1		T2	21		T29	15		T22	15
wkup[46]	295	1		T31	51		T49	15		T42	26
wkup[47]	179	1		T11	21		T50	21		T41	21
wkup[48]	405	1		T32	21		T40	21		T87	56
wkup[49]	277	1		T31	21		T32	21		T171	21
wkup[50]	156	1		T31	21		T42	30		T124	15
wkup[51]	213	1		T43	15		T138	21		T126	21
wkup[52]	193	1		T11	30		T31	15		T40	8
wkup[53]	326	1		T31	42		T32	21		T41	21
wkup[54]	362	1		T24	73		T39	21		T41	21
wkup[55]	243	1		T194	15		T87	21		T121	21
wkup[56]	144	1		T50	21		T42	21		T116	26
wkup[57]	218	1		T95	30		T56	21		T108	21
wkup[58]	306	1		T14	26		T31	26		T32	21
wkup[59]	288	1		T148	39		T159	21		T154	21
wkup[60]	187	1		T11	21		T31	15		T22	26
wkup[61]	311	1		T12	26		T39	21		T122	15
wkup[62]	338	1		T11	21		T31	30		T138	21
wkup[63]	344	1		T13	21		T31	21		T38	21
wkup_0	3574	1		T1	5		T2	5		T3	5