Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.04 99.33 93.67 100.00 98.40 99.51 49.35


Total test records in report: 419
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T61 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.4036861387 Jun 05 05:23:56 PM PDT 24 Jun 05 05:23:58 PM PDT 24 957988333 ps
T282 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2152853257 Jun 05 05:24:39 PM PDT 24 Jun 05 05:24:41 PM PDT 24 405283486 ps
T37 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.261114836 Jun 05 05:24:01 PM PDT 24 Jun 05 05:24:08 PM PDT 24 4504156231 ps
T78 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4116136945 Jun 05 05:23:58 PM PDT 24 Jun 05 05:24:00 PM PDT 24 1353725068 ps
T198 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1020879233 Jun 05 05:24:05 PM PDT 24 Jun 05 05:24:16 PM PDT 24 8103324185 ps
T283 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.275972541 Jun 05 05:23:47 PM PDT 24 Jun 05 05:23:48 PM PDT 24 517269953 ps
T284 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1437563995 Jun 05 05:24:31 PM PDT 24 Jun 05 05:24:39 PM PDT 24 4131873686 ps
T199 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3177284974 Jun 05 05:23:51 PM PDT 24 Jun 05 05:24:00 PM PDT 24 8077159076 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2473982431 Jun 05 05:24:02 PM PDT 24 Jun 05 05:24:04 PM PDT 24 453845400 ps
T63 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2193295675 Jun 05 05:24:02 PM PDT 24 Jun 05 05:24:04 PM PDT 24 710870331 ps
T201 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3940755854 Jun 05 05:24:13 PM PDT 24 Jun 05 05:24:21 PM PDT 24 8508737233 ps
T79 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.22860632 Jun 05 05:23:57 PM PDT 24 Jun 05 05:24:02 PM PDT 24 2109408053 ps
T285 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4073934858 Jun 05 05:24:37 PM PDT 24 Jun 05 05:24:39 PM PDT 24 521164569 ps
T286 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2213158458 Jun 05 05:24:00 PM PDT 24 Jun 05 05:24:01 PM PDT 24 471254886 ps
T80 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1488421657 Jun 05 05:24:04 PM PDT 24 Jun 05 05:24:06 PM PDT 24 1377907831 ps
T287 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3564089024 Jun 05 05:24:37 PM PDT 24 Jun 05 05:24:38 PM PDT 24 357091794 ps
T288 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2216121574 Jun 05 05:24:30 PM PDT 24 Jun 05 05:24:32 PM PDT 24 275833035 ps
T289 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1931907653 Jun 05 05:24:05 PM PDT 24 Jun 05 05:24:10 PM PDT 24 6975184800 ps
T290 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1314999300 Jun 05 05:24:39 PM PDT 24 Jun 05 05:24:40 PM PDT 24 388465142 ps
T291 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2472034727 Jun 05 05:24:29 PM PDT 24 Jun 05 05:24:31 PM PDT 24 1192174216 ps
T292 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2651821253 Jun 05 05:24:40 PM PDT 24 Jun 05 05:24:41 PM PDT 24 475971677 ps
T293 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4290369129 Jun 05 05:24:05 PM PDT 24 Jun 05 05:24:06 PM PDT 24 299712015 ps
T64 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2452567423 Jun 05 05:23:53 PM PDT 24 Jun 05 05:23:54 PM PDT 24 575536423 ps
T294 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1855802433 Jun 05 05:24:02 PM PDT 24 Jun 05 05:24:04 PM PDT 24 404244331 ps
T295 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.631629821 Jun 05 05:24:21 PM PDT 24 Jun 05 05:24:23 PM PDT 24 379771878 ps
T296 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3825022460 Jun 05 05:24:41 PM PDT 24 Jun 05 05:24:42 PM PDT 24 558623175 ps
T297 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.329324948 Jun 05 05:24:38 PM PDT 24 Jun 05 05:24:40 PM PDT 24 410863164 ps
T298 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3270718116 Jun 05 05:23:58 PM PDT 24 Jun 05 05:24:01 PM PDT 24 353846062 ps
T65 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.728782884 Jun 05 05:24:04 PM PDT 24 Jun 05 05:24:06 PM PDT 24 535751278 ps
T299 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1971542980 Jun 05 05:23:54 PM PDT 24 Jun 05 05:23:55 PM PDT 24 929985313 ps
T300 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.406512020 Jun 05 05:24:49 PM PDT 24 Jun 05 05:24:50 PM PDT 24 513325270 ps
T301 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1367500171 Jun 05 05:24:31 PM PDT 24 Jun 05 05:24:33 PM PDT 24 4820398138 ps
T302 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2836818965 Jun 05 05:24:28 PM PDT 24 Jun 05 05:24:30 PM PDT 24 469748590 ps
T303 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.903961890 Jun 05 05:24:43 PM PDT 24 Jun 05 05:24:44 PM PDT 24 452186982 ps
T66 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3401305162 Jun 05 05:24:02 PM PDT 24 Jun 05 05:24:04 PM PDT 24 468835008 ps
T304 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2834986779 Jun 05 05:24:29 PM PDT 24 Jun 05 05:24:31 PM PDT 24 421009928 ps
T67 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3850770412 Jun 05 05:24:01 PM PDT 24 Jun 05 05:24:10 PM PDT 24 8575285454 ps
T81 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1055850965 Jun 05 05:24:05 PM PDT 24 Jun 05 05:24:07 PM PDT 24 3284104251 ps
T305 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.191001671 Jun 05 05:24:39 PM PDT 24 Jun 05 05:24:41 PM PDT 24 400519081 ps
T306 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2784395652 Jun 05 05:24:29 PM PDT 24 Jun 05 05:24:30 PM PDT 24 410832443 ps
T307 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3621298514 Jun 05 05:24:20 PM PDT 24 Jun 05 05:24:23 PM PDT 24 379362498 ps
T308 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3384839487 Jun 05 05:24:37 PM PDT 24 Jun 05 05:24:39 PM PDT 24 377819463 ps
T82 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4187839895 Jun 05 05:23:58 PM PDT 24 Jun 05 05:24:00 PM PDT 24 1286802642 ps
T68 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2888894698 Jun 05 05:24:10 PM PDT 24 Jun 05 05:24:11 PM PDT 24 376942945 ps
T309 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2133342884 Jun 05 05:24:39 PM PDT 24 Jun 05 05:24:41 PM PDT 24 515815090 ps
T310 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2812382636 Jun 05 05:24:53 PM PDT 24 Jun 05 05:24:54 PM PDT 24 368519819 ps
T73 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.652721309 Jun 05 05:24:20 PM PDT 24 Jun 05 05:24:21 PM PDT 24 390212443 ps
T83 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1877383780 Jun 05 05:24:33 PM PDT 24 Jun 05 05:24:37 PM PDT 24 2856464650 ps
T84 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2617066556 Jun 05 05:24:18 PM PDT 24 Jun 05 05:24:24 PM PDT 24 2090366325 ps
T311 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2889533485 Jun 05 05:24:11 PM PDT 24 Jun 05 05:24:13 PM PDT 24 401730809 ps
T85 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1206176239 Jun 05 05:24:36 PM PDT 24 Jun 05 05:24:39 PM PDT 24 1894538283 ps
T312 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1647065056 Jun 05 05:24:41 PM PDT 24 Jun 05 05:24:43 PM PDT 24 275340553 ps
T313 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1652842649 Jun 05 05:24:03 PM PDT 24 Jun 05 05:24:06 PM PDT 24 1101485993 ps
T314 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3785984846 Jun 05 05:24:30 PM PDT 24 Jun 05 05:24:35 PM PDT 24 8356486116 ps
T315 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2051802501 Jun 05 05:24:31 PM PDT 24 Jun 05 05:24:33 PM PDT 24 436583935 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3706873699 Jun 05 05:24:05 PM PDT 24 Jun 05 05:24:08 PM PDT 24 686080980 ps
T317 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1412164591 Jun 05 05:24:21 PM PDT 24 Jun 05 05:24:23 PM PDT 24 405479364 ps
T318 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1631694860 Jun 05 05:24:19 PM PDT 24 Jun 05 05:24:21 PM PDT 24 376338200 ps
T319 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3754090630 Jun 05 05:24:06 PM PDT 24 Jun 05 05:24:08 PM PDT 24 559198133 ps
T320 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3677529040 Jun 05 05:24:46 PM PDT 24 Jun 05 05:24:48 PM PDT 24 495272723 ps
T321 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3651908277 Jun 05 05:24:20 PM PDT 24 Jun 05 05:24:22 PM PDT 24 419351826 ps
T322 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2028058356 Jun 05 05:23:57 PM PDT 24 Jun 05 05:23:59 PM PDT 24 619192767 ps
T323 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.337287138 Jun 05 05:24:01 PM PDT 24 Jun 05 05:24:03 PM PDT 24 560396693 ps
T324 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3090260013 Jun 05 05:24:19 PM PDT 24 Jun 05 05:24:21 PM PDT 24 461204385 ps
T325 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1767930534 Jun 05 05:24:05 PM PDT 24 Jun 05 05:24:07 PM PDT 24 516239813 ps
T326 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2066137312 Jun 05 05:23:58 PM PDT 24 Jun 05 05:23:59 PM PDT 24 300320534 ps
T327 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1196132979 Jun 05 05:24:32 PM PDT 24 Jun 05 05:24:34 PM PDT 24 1151208056 ps
T328 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1784717343 Jun 05 05:24:29 PM PDT 24 Jun 05 05:24:35 PM PDT 24 8974686555 ps
T77 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1670289409 Jun 05 05:24:25 PM PDT 24 Jun 05 05:24:26 PM PDT 24 501186059 ps
T329 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2187905343 Jun 05 05:24:12 PM PDT 24 Jun 05 05:24:14 PM PDT 24 436958194 ps
T330 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2590248050 Jun 05 05:24:22 PM PDT 24 Jun 05 05:24:30 PM PDT 24 2458610297 ps
T331 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.739863708 Jun 05 05:23:48 PM PDT 24 Jun 05 05:23:50 PM PDT 24 501959065 ps
T332 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.4060957842 Jun 05 05:24:36 PM PDT 24 Jun 05 05:24:38 PM PDT 24 474645701 ps
T333 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2996041891 Jun 05 05:24:35 PM PDT 24 Jun 05 05:24:36 PM PDT 24 283431186 ps
T334 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3241521767 Jun 05 05:23:56 PM PDT 24 Jun 05 05:23:58 PM PDT 24 1152486820 ps
T335 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2902675821 Jun 05 05:24:31 PM PDT 24 Jun 05 05:24:33 PM PDT 24 443437742 ps
T336 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3866427733 Jun 05 05:24:30 PM PDT 24 Jun 05 05:24:31 PM PDT 24 376271604 ps
T337 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1860587606 Jun 05 05:24:04 PM PDT 24 Jun 05 05:24:06 PM PDT 24 469786849 ps
T69 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3947133074 Jun 05 05:24:01 PM PDT 24 Jun 05 05:24:02 PM PDT 24 970965055 ps
T338 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3246893369 Jun 05 05:24:31 PM PDT 24 Jun 05 05:24:34 PM PDT 24 585666519 ps
T339 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.992930117 Jun 05 05:23:58 PM PDT 24 Jun 05 05:24:03 PM PDT 24 4483730721 ps
T340 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.450739389 Jun 05 05:24:37 PM PDT 24 Jun 05 05:24:40 PM PDT 24 404391718 ps
T341 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4194046322 Jun 05 05:24:21 PM PDT 24 Jun 05 05:24:23 PM PDT 24 439394688 ps
T70 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1328329423 Jun 05 05:23:57 PM PDT 24 Jun 05 05:24:15 PM PDT 24 10591775104 ps
T342 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.482882875 Jun 05 05:24:31 PM PDT 24 Jun 05 05:24:33 PM PDT 24 514085482 ps
T343 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1190740364 Jun 05 05:24:40 PM PDT 24 Jun 05 05:24:42 PM PDT 24 404677743 ps
T344 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2214697787 Jun 05 05:24:32 PM PDT 24 Jun 05 05:24:34 PM PDT 24 563327105 ps
T345 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1703463909 Jun 05 05:24:36 PM PDT 24 Jun 05 05:24:38 PM PDT 24 379943122 ps
T346 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2783273519 Jun 05 05:24:02 PM PDT 24 Jun 05 05:24:04 PM PDT 24 507317967 ps
T347 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4107767003 Jun 05 05:24:31 PM PDT 24 Jun 05 05:24:36 PM PDT 24 1160198988 ps
T348 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.744635909 Jun 05 05:24:52 PM PDT 24 Jun 05 05:24:53 PM PDT 24 506388646 ps
T349 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2644498439 Jun 05 05:24:40 PM PDT 24 Jun 05 05:24:41 PM PDT 24 438891054 ps
T200 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2825879626 Jun 05 05:24:21 PM PDT 24 Jun 05 05:24:34 PM PDT 24 7842133854 ps
T350 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2454842090 Jun 05 05:24:30 PM PDT 24 Jun 05 05:24:33 PM PDT 24 544961669 ps
T351 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3456203113 Jun 05 05:23:59 PM PDT 24 Jun 05 05:24:00 PM PDT 24 379651872 ps
T74 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1017131417 Jun 05 05:23:56 PM PDT 24 Jun 05 05:23:58 PM PDT 24 501916838 ps
T352 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1339460236 Jun 05 05:24:46 PM PDT 24 Jun 05 05:24:48 PM PDT 24 445613147 ps
T353 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.358891470 Jun 05 05:23:57 PM PDT 24 Jun 05 05:24:21 PM PDT 24 13792286343 ps
T354 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3179573444 Jun 05 05:23:58 PM PDT 24 Jun 05 05:24:01 PM PDT 24 4498244536 ps
T355 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1755304349 Jun 05 05:24:37 PM PDT 24 Jun 05 05:24:39 PM PDT 24 373022533 ps
T75 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1863134201 Jun 05 05:23:57 PM PDT 24 Jun 05 05:24:16 PM PDT 24 11672047811 ps
T356 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1761378780 Jun 05 05:24:03 PM PDT 24 Jun 05 05:24:04 PM PDT 24 565199119 ps
T357 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3630501422 Jun 05 05:23:57 PM PDT 24 Jun 05 05:23:59 PM PDT 24 314888689 ps
T358 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2980361590 Jun 05 05:23:58 PM PDT 24 Jun 05 05:24:00 PM PDT 24 461141940 ps
T359 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.84722758 Jun 05 05:24:20 PM PDT 24 Jun 05 05:24:22 PM PDT 24 330104642 ps
T360 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1359342742 Jun 05 05:24:30 PM PDT 24 Jun 05 05:24:36 PM PDT 24 2846407040 ps
T361 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2356578231 Jun 05 05:24:20 PM PDT 24 Jun 05 05:24:22 PM PDT 24 362450088 ps
T362 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3209579456 Jun 05 05:24:31 PM PDT 24 Jun 05 05:24:34 PM PDT 24 539364142 ps
T363 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3305666961 Jun 05 05:24:31 PM PDT 24 Jun 05 05:24:33 PM PDT 24 533868578 ps
T364 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1014792128 Jun 05 05:23:48 PM PDT 24 Jun 05 05:23:51 PM PDT 24 4528771035 ps
T365 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.106394310 Jun 05 05:24:21 PM PDT 24 Jun 05 05:24:23 PM PDT 24 1213607201 ps
T366 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1258511308 Jun 05 05:23:57 PM PDT 24 Jun 05 05:23:59 PM PDT 24 339460007 ps
T367 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2662131894 Jun 05 05:24:30 PM PDT 24 Jun 05 05:24:32 PM PDT 24 481315061 ps
T368 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1560712223 Jun 05 05:24:01 PM PDT 24 Jun 05 05:24:02 PM PDT 24 382439731 ps
T71 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.451799227 Jun 05 05:23:53 PM PDT 24 Jun 05 05:23:54 PM PDT 24 507315514 ps
T369 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2339992510 Jun 05 05:24:21 PM PDT 24 Jun 05 05:24:23 PM PDT 24 550876254 ps
T370 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2045701195 Jun 05 05:24:01 PM PDT 24 Jun 05 05:24:02 PM PDT 24 408431370 ps
T371 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.374217707 Jun 05 05:24:32 PM PDT 24 Jun 05 05:24:33 PM PDT 24 354993526 ps
T372 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.507222976 Jun 05 05:24:30 PM PDT 24 Jun 05 05:24:31 PM PDT 24 572465970 ps
T373 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3515910438 Jun 05 05:24:28 PM PDT 24 Jun 05 05:24:30 PM PDT 24 479065059 ps
T374 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2737085655 Jun 05 05:24:19 PM PDT 24 Jun 05 05:24:20 PM PDT 24 702549256 ps
T375 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2195732823 Jun 05 05:24:39 PM PDT 24 Jun 05 05:24:41 PM PDT 24 449633570 ps
T376 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3253897259 Jun 05 05:24:11 PM PDT 24 Jun 05 05:24:13 PM PDT 24 2458950575 ps
T377 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1105988083 Jun 05 05:24:26 PM PDT 24 Jun 05 05:24:28 PM PDT 24 423805201 ps
T378 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2180623906 Jun 05 05:24:23 PM PDT 24 Jun 05 05:24:25 PM PDT 24 900095069 ps
T379 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.477677555 Jun 05 05:24:37 PM PDT 24 Jun 05 05:24:38 PM PDT 24 336615896 ps
T380 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2052938289 Jun 05 05:24:32 PM PDT 24 Jun 05 05:24:33 PM PDT 24 438509553 ps
T381 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.426461264 Jun 05 05:24:20 PM PDT 24 Jun 05 05:24:24 PM PDT 24 371419360 ps
T382 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3563251052 Jun 05 05:24:05 PM PDT 24 Jun 05 05:24:06 PM PDT 24 426154428 ps
T383 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2288259667 Jun 05 05:24:06 PM PDT 24 Jun 05 05:24:09 PM PDT 24 509385878 ps
T384 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2970102558 Jun 05 05:24:43 PM PDT 24 Jun 05 05:24:44 PM PDT 24 501744398 ps
T385 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1011974656 Jun 05 05:24:39 PM PDT 24 Jun 05 05:24:41 PM PDT 24 305121615 ps
T386 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3838185923 Jun 05 05:24:21 PM PDT 24 Jun 05 05:24:23 PM PDT 24 376468374 ps
T72 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.659520881 Jun 05 05:24:30 PM PDT 24 Jun 05 05:24:32 PM PDT 24 483250606 ps
T387 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3838411703 Jun 05 05:24:40 PM PDT 24 Jun 05 05:24:55 PM PDT 24 7996183359 ps
T388 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.4039386142 Jun 05 05:24:50 PM PDT 24 Jun 05 05:24:52 PM PDT 24 307695043 ps
T389 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.440203371 Jun 05 05:24:39 PM PDT 24 Jun 05 05:24:41 PM PDT 24 507313429 ps
T390 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1037894371 Jun 05 05:24:22 PM PDT 24 Jun 05 05:24:30 PM PDT 24 4053052188 ps
T391 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3969058353 Jun 05 05:24:31 PM PDT 24 Jun 05 05:24:33 PM PDT 24 1457732820 ps
T392 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1817023097 Jun 05 05:24:35 PM PDT 24 Jun 05 05:24:38 PM PDT 24 491189701 ps
T393 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2307523632 Jun 05 05:24:19 PM PDT 24 Jun 05 05:24:21 PM PDT 24 306841679 ps
T394 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.533755428 Jun 05 05:24:06 PM PDT 24 Jun 05 05:24:08 PM PDT 24 823578123 ps
T395 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.936990817 Jun 05 05:24:29 PM PDT 24 Jun 05 05:24:43 PM PDT 24 8373052968 ps
T396 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1545046447 Jun 05 05:24:04 PM PDT 24 Jun 05 05:24:07 PM PDT 24 436191277 ps
T397 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1361505850 Jun 05 05:24:46 PM PDT 24 Jun 05 05:24:48 PM PDT 24 418954703 ps
T398 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3466400216 Jun 05 05:24:39 PM PDT 24 Jun 05 05:24:43 PM PDT 24 2289960922 ps
T399 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2045037455 Jun 05 05:24:11 PM PDT 24 Jun 05 05:24:12 PM PDT 24 1185198650 ps
T400 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4070580199 Jun 05 05:24:22 PM PDT 24 Jun 05 05:24:24 PM PDT 24 431769223 ps
T202 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3495514912 Jun 05 05:24:37 PM PDT 24 Jun 05 05:24:39 PM PDT 24 4169026542 ps
T401 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2818361227 Jun 05 05:24:40 PM PDT 24 Jun 05 05:24:42 PM PDT 24 2720538012 ps
T402 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3067351437 Jun 05 05:24:04 PM PDT 24 Jun 05 05:24:05 PM PDT 24 401345752 ps
T403 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1409733333 Jun 05 05:24:11 PM PDT 24 Jun 05 05:24:12 PM PDT 24 442953692 ps
T404 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3704598836 Jun 05 05:24:21 PM PDT 24 Jun 05 05:24:24 PM PDT 24 4098533228 ps
T405 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2619192316 Jun 05 05:24:19 PM PDT 24 Jun 05 05:24:21 PM PDT 24 527890404 ps
T406 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2376221026 Jun 05 05:24:11 PM PDT 24 Jun 05 05:24:12 PM PDT 24 401451948 ps
T407 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2324206446 Jun 05 05:24:36 PM PDT 24 Jun 05 05:24:38 PM PDT 24 355794148 ps
T408 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2391058442 Jun 05 05:24:30 PM PDT 24 Jun 05 05:24:33 PM PDT 24 773656935 ps
T409 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3981143678 Jun 05 05:23:57 PM PDT 24 Jun 05 05:23:58 PM PDT 24 388490662 ps
T410 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1997009822 Jun 05 05:24:38 PM PDT 24 Jun 05 05:24:39 PM PDT 24 371378467 ps
T411 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1129557749 Jun 05 05:24:39 PM PDT 24 Jun 05 05:24:41 PM PDT 24 485827242 ps
T412 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1813002347 Jun 05 05:23:59 PM PDT 24 Jun 05 05:24:01 PM PDT 24 451136475 ps
T413 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1075073697 Jun 05 05:23:58 PM PDT 24 Jun 05 05:23:59 PM PDT 24 322216622 ps
T414 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4228065091 Jun 05 05:24:02 PM PDT 24 Jun 05 05:24:03 PM PDT 24 336135527 ps
T415 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2274044491 Jun 05 05:23:59 PM PDT 24 Jun 05 05:24:00 PM PDT 24 365338611 ps
T416 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3330810010 Jun 05 05:24:53 PM PDT 24 Jun 05 05:24:54 PM PDT 24 289260343 ps
T76 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2166669269 Jun 05 05:24:02 PM PDT 24 Jun 05 05:24:04 PM PDT 24 553469754 ps
T417 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2534612976 Jun 05 05:24:37 PM PDT 24 Jun 05 05:24:39 PM PDT 24 303301377 ps
T418 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2215075554 Jun 05 05:24:30 PM PDT 24 Jun 05 05:24:32 PM PDT 24 327133707 ps
T419 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4029372392 Jun 05 05:24:19 PM PDT 24 Jun 05 05:24:27 PM PDT 24 8156507860 ps

Test location /workspace/coverage/default/46.aon_timer_stress_all.3375391357
Short name T6
Test name
Test status
Simulation time 189715150029 ps
CPU time 54.72 seconds
Started Jun 05 05:23:48 PM PDT 24
Finished Jun 05 05:24:43 PM PDT 24
Peak memory 191884 kb
Host smart-32d03555-6ff6-41f3-8203-fdbbe142481a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375391357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3375391357
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2291092674
Short name T11
Test name
Test status
Simulation time 273663332999 ps
CPU time 1164.71 seconds
Started Jun 05 05:22:52 PM PDT 24
Finished Jun 05 05:42:18 PM PDT 24
Peak memory 212224 kb
Host smart-ea80b7c0-1ad4-4a69-b3e8-1a97fe00e081
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291092674 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2291092674
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3721364124
Short name T36
Test name
Test status
Simulation time 4530906829 ps
CPU time 4.25 seconds
Started Jun 05 05:24:27 PM PDT 24
Finished Jun 05 05:24:32 PM PDT 24
Peak memory 196540 kb
Host smart-754cc6ef-6a0b-43f8-9d55-b0e0ac6c8b11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721364124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3721364124
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2480271278
Short name T91
Test name
Test status
Simulation time 61208475535 ps
CPU time 318.02 seconds
Started Jun 05 05:23:37 PM PDT 24
Finished Jun 05 05:28:55 PM PDT 24
Peak memory 214292 kb
Host smart-69299e2c-3b3b-4795-bf45-282e38123688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480271278 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2480271278
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2142104746
Short name T31
Test name
Test status
Simulation time 947362645631 ps
CPU time 747.26 seconds
Started Jun 05 05:22:51 PM PDT 24
Finished Jun 05 05:35:20 PM PDT 24
Peak memory 208232 kb
Host smart-eed21985-a824-4b04-9823-dc4d450e1432
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142104746 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2142104746
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1576617070
Short name T51
Test name
Test status
Simulation time 138231026464 ps
CPU time 750.47 seconds
Started Jun 05 05:23:09 PM PDT 24
Finished Jun 05 05:35:40 PM PDT 24
Peak memory 207404 kb
Host smart-7d36b4ba-5c41-4293-975e-4f3bf66f65ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576617070 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1576617070
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1493203149
Short name T87
Test name
Test status
Simulation time 279899614806 ps
CPU time 825.1 seconds
Started Jun 05 05:23:48 PM PDT 24
Finished Jun 05 05:37:34 PM PDT 24
Peak memory 215024 kb
Host smart-1397e280-fa20-4278-921e-a82bf305edac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493203149 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1493203149
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3642408948
Short name T120
Test name
Test status
Simulation time 229081436212 ps
CPU time 445.28 seconds
Started Jun 05 05:23:42 PM PDT 24
Finished Jun 05 05:31:08 PM PDT 24
Peak memory 203300 kb
Host smart-8970221e-c532-4349-9b74-7575b2fcdac3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642408948 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3642408948
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.162795095
Short name T121
Test name
Test status
Simulation time 93698930830 ps
CPU time 822.16 seconds
Started Jun 05 05:23:07 PM PDT 24
Finished Jun 05 05:36:50 PM PDT 24
Peak memory 215216 kb
Host smart-d0f7aff5-437f-489e-8579-13c607672cd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162795095 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.162795095
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3995966836
Short name T125
Test name
Test status
Simulation time 255357960858 ps
CPU time 565.56 seconds
Started Jun 05 05:23:14 PM PDT 24
Finished Jun 05 05:32:40 PM PDT 24
Peak memory 204472 kb
Host smart-d01b27ee-e314-478a-8f0b-159c6dc4af7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995966836 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3995966836
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3554306997
Short name T105
Test name
Test status
Simulation time 36276859049 ps
CPU time 294.01 seconds
Started Jun 05 05:23:13 PM PDT 24
Finished Jun 05 05:28:08 PM PDT 24
Peak memory 198692 kb
Host smart-d658bc02-f6dd-446b-b8b4-e4a683230f78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554306997 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3554306997
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1051925585
Short name T56
Test name
Test status
Simulation time 230934539548 ps
CPU time 912.63 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:38:54 PM PDT 24
Peak memory 215052 kb
Host smart-c58d2627-6323-4797-9beb-e522f1ef08b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051925585 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1051925585
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1778754173
Short name T32
Test name
Test status
Simulation time 43122881614 ps
CPU time 31.75 seconds
Started Jun 05 05:23:36 PM PDT 24
Finished Jun 05 05:24:08 PM PDT 24
Peak memory 184644 kb
Host smart-ad2d7764-3959-4b20-ba3b-2c25c87e55a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778754173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1778754173
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.428282635
Short name T17
Test name
Test status
Simulation time 7509294743 ps
CPU time 12.39 seconds
Started Jun 05 05:22:45 PM PDT 24
Finished Jun 05 05:22:58 PM PDT 24
Peak memory 215852 kb
Host smart-b7df4e54-475b-46fb-9ccd-8e19c427cc74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428282635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.428282635
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2735413627
Short name T50
Test name
Test status
Simulation time 191578066836 ps
CPU time 74.57 seconds
Started Jun 05 05:23:16 PM PDT 24
Finished Jun 05 05:24:32 PM PDT 24
Peak memory 184796 kb
Host smart-3ba5f935-3b85-4adf-ad84-7676c2c05765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735413627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2735413627
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.232596645
Short name T123
Test name
Test status
Simulation time 133435001858 ps
CPU time 274.83 seconds
Started Jun 05 05:23:07 PM PDT 24
Finished Jun 05 05:27:43 PM PDT 24
Peak memory 200800 kb
Host smart-6e03069c-ef85-4eeb-bddd-6e4753c4f50d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232596645 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.232596645
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3901504772
Short name T100
Test name
Test status
Simulation time 195057344171 ps
CPU time 445.87 seconds
Started Jun 05 05:23:35 PM PDT 24
Finished Jun 05 05:31:02 PM PDT 24
Peak memory 202912 kb
Host smart-428fb8eb-dc5e-41d5-8290-c66d8d62006e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901504772 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3901504772
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2329568408
Short name T107
Test name
Test status
Simulation time 208882509142 ps
CPU time 71.72 seconds
Started Jun 05 05:23:41 PM PDT 24
Finished Jun 05 05:24:54 PM PDT 24
Peak memory 192684 kb
Host smart-9970a6a9-d4d5-491f-93b9-a8f7f4b84cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329568408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2329568408
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1897720058
Short name T94
Test name
Test status
Simulation time 169453514269 ps
CPU time 910.1 seconds
Started Jun 05 05:22:44 PM PDT 24
Finished Jun 05 05:37:55 PM PDT 24
Peak memory 215028 kb
Host smart-293aa1f7-ad17-49cd-8caf-81bd1b467d3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897720058 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1897720058
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2147489084
Short name T111
Test name
Test status
Simulation time 549815378654 ps
CPU time 180.47 seconds
Started Jun 05 05:23:07 PM PDT 24
Finished Jun 05 05:26:08 PM PDT 24
Peak memory 193188 kb
Host smart-01a6b466-aa41-4182-9220-2e10cd25d367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147489084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2147489084
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.860480203
Short name T148
Test name
Test status
Simulation time 230147450453 ps
CPU time 479.51 seconds
Started Jun 05 05:22:50 PM PDT 24
Finished Jun 05 05:30:51 PM PDT 24
Peak memory 211884 kb
Host smart-c345e360-bdbc-4212-84a8-be76d3eed595
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860480203 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.860480203
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3904837758
Short name T103
Test name
Test status
Simulation time 46183734016 ps
CPU time 254.4 seconds
Started Jun 05 05:22:59 PM PDT 24
Finished Jun 05 05:27:14 PM PDT 24
Peak memory 198748 kb
Host smart-0cec1b62-b35f-4789-a00c-f3d639cfdced
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904837758 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3904837758
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.523302354
Short name T129
Test name
Test status
Simulation time 58274345426 ps
CPU time 130.93 seconds
Started Jun 05 05:23:54 PM PDT 24
Finished Jun 05 05:26:05 PM PDT 24
Peak memory 206912 kb
Host smart-97c3fc27-7ede-474b-b982-fede2ed8c674
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523302354 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.523302354
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.721718119
Short name T95
Test name
Test status
Simulation time 79356448373 ps
CPU time 125.15 seconds
Started Jun 05 05:23:16 PM PDT 24
Finished Jun 05 05:25:21 PM PDT 24
Peak memory 192304 kb
Host smart-503b28e1-ab51-4a29-b478-5b9d661b6cca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721718119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.721718119
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.549529213
Short name T137
Test name
Test status
Simulation time 314740575527 ps
CPU time 83.18 seconds
Started Jun 05 05:23:07 PM PDT 24
Finished Jun 05 05:24:31 PM PDT 24
Peak memory 191932 kb
Host smart-73c16f4d-c1ab-44f9-b84d-a1fd18eb2c14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549529213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.549529213
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.284092436
Short name T108
Test name
Test status
Simulation time 188140358145 ps
CPU time 302.29 seconds
Started Jun 05 05:23:36 PM PDT 24
Finished Jun 05 05:28:39 PM PDT 24
Peak memory 192456 kb
Host smart-66b76c36-1e40-42a1-8a53-d4dbc34851c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284092436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.284092436
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1120323890
Short name T25
Test name
Test status
Simulation time 149389404122 ps
CPU time 233.6 seconds
Started Jun 05 05:23:49 PM PDT 24
Finished Jun 05 05:27:43 PM PDT 24
Peak memory 193028 kb
Host smart-0404fbe9-6edf-46e5-a247-66342d50c664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120323890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1120323890
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1202768060
Short name T2
Test name
Test status
Simulation time 43279553565 ps
CPU time 62.12 seconds
Started Jun 05 05:22:47 PM PDT 24
Finished Jun 05 05:23:50 PM PDT 24
Peak memory 191924 kb
Host smart-381de818-99ff-4c6b-ab4d-bc8bc098f1ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202768060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1202768060
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3616334361
Short name T41
Test name
Test status
Simulation time 80196100026 ps
CPU time 282.65 seconds
Started Jun 05 05:23:08 PM PDT 24
Finished Jun 05 05:27:51 PM PDT 24
Peak memory 200184 kb
Host smart-c617569f-1143-4b1d-b435-966de5c5ac14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616334361 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3616334361
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.652721309
Short name T73
Test name
Test status
Simulation time 390212443 ps
CPU time 0.98 seconds
Started Jun 05 05:24:20 PM PDT 24
Finished Jun 05 05:24:21 PM PDT 24
Peak memory 193396 kb
Host smart-46a787ff-38b9-47d4-82c0-66145f8cf46a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652721309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.652721309
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2734392243
Short name T55
Test name
Test status
Simulation time 1826603753133 ps
CPU time 510.36 seconds
Started Jun 05 05:23:06 PM PDT 24
Finished Jun 05 05:31:37 PM PDT 24
Peak memory 214436 kb
Host smart-22bbff62-c3e4-4eae-86ae-83b1cdde7e3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734392243 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2734392243
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1058414132
Short name T138
Test name
Test status
Simulation time 16764931113 ps
CPU time 179.65 seconds
Started Jun 05 05:23:39 PM PDT 24
Finished Jun 05 05:26:40 PM PDT 24
Peak memory 198620 kb
Host smart-80938e57-b1ee-4373-9f95-526222fec2d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058414132 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1058414132
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.463263738
Short name T92
Test name
Test status
Simulation time 36685454544 ps
CPU time 277.49 seconds
Started Jun 05 05:22:51 PM PDT 24
Finished Jun 05 05:27:30 PM PDT 24
Peak memory 214396 kb
Host smart-70ef860b-0f5e-46a7-a301-8ae3265a8079
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463263738 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.463263738
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.4202134042
Short name T13
Test name
Test status
Simulation time 91622262121 ps
CPU time 200.41 seconds
Started Jun 05 05:22:50 PM PDT 24
Finished Jun 05 05:26:11 PM PDT 24
Peak memory 208400 kb
Host smart-3b0b20dc-c026-4222-8a5e-4f3c3eace113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202134042 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.4202134042
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1124528601
Short name T142
Test name
Test status
Simulation time 245489025763 ps
CPU time 96.29 seconds
Started Jun 05 05:23:14 PM PDT 24
Finished Jun 05 05:24:51 PM PDT 24
Peak memory 192404 kb
Host smart-081dce0a-9e42-4e86-8bcb-3707c1d21b28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124528601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1124528601
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2259511846
Short name T135
Test name
Test status
Simulation time 96756209925 ps
CPU time 810.54 seconds
Started Jun 05 05:23:14 PM PDT 24
Finished Jun 05 05:36:45 PM PDT 24
Peak memory 207484 kb
Host smart-7d67445c-4cfc-4e1e-8013-adcd00201ca4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259511846 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2259511846
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.845833602
Short name T110
Test name
Test status
Simulation time 338748394396 ps
CPU time 104.42 seconds
Started Jun 05 05:23:38 PM PDT 24
Finished Jun 05 05:25:23 PM PDT 24
Peak memory 192556 kb
Host smart-d06e81b7-80f2-4b68-b22c-4e8d6285fe12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845833602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.845833602
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3269244047
Short name T42
Test name
Test status
Simulation time 318832556496 ps
CPU time 279.96 seconds
Started Jun 05 05:23:16 PM PDT 24
Finished Jun 05 05:27:57 PM PDT 24
Peak memory 209124 kb
Host smart-015280fc-047b-45fe-8d52-c0ab8fd32001
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269244047 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3269244047
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2782038557
Short name T133
Test name
Test status
Simulation time 67552092267 ps
CPU time 98.66 seconds
Started Jun 05 05:23:23 PM PDT 24
Finished Jun 05 05:25:03 PM PDT 24
Peak memory 191904 kb
Host smart-1cc1bcc2-2893-4604-a08f-d5a22909b449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782038557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2782038557
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2916715088
Short name T144
Test name
Test status
Simulation time 118388315463 ps
CPU time 172.72 seconds
Started Jun 05 05:23:41 PM PDT 24
Finished Jun 05 05:26:34 PM PDT 24
Peak memory 192604 kb
Host smart-4eeaf23c-7f4c-4d2f-930d-6d97ec9c0665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916715088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2916715088
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2690970073
Short name T90
Test name
Test status
Simulation time 285581322398 ps
CPU time 534.76 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:32:35 PM PDT 24
Peak memory 212412 kb
Host smart-b62b6736-169e-4afe-98ae-7893829066c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690970073 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2690970073
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.194270162
Short name T154
Test name
Test status
Simulation time 269158937924 ps
CPU time 300.21 seconds
Started Jun 05 05:23:15 PM PDT 24
Finished Jun 05 05:28:16 PM PDT 24
Peak memory 192956 kb
Host smart-e9ecda85-1122-4682-81f0-a1b1ab3dd3d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194270162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.194270162
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1794761997
Short name T39
Test name
Test status
Simulation time 36654685996 ps
CPU time 403.82 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:30:25 PM PDT 24
Peak memory 199396 kb
Host smart-71fac97f-2b6e-4e32-8522-9d30e46b0a97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794761997 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1794761997
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.483500761
Short name T159
Test name
Test status
Simulation time 14444177009 ps
CPU time 108.32 seconds
Started Jun 05 05:23:20 PM PDT 24
Finished Jun 05 05:25:09 PM PDT 24
Peak memory 214696 kb
Host smart-53690a4e-219e-43ce-bbc4-b30192a3cdef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483500761 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.483500761
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.807304012
Short name T122
Test name
Test status
Simulation time 69727119705 ps
CPU time 91.1 seconds
Started Jun 05 05:23:37 PM PDT 24
Finished Jun 05 05:25:09 PM PDT 24
Peak memory 192080 kb
Host smart-f6743fe7-41bd-4134-912f-2e2317c093e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807304012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.807304012
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.4253164995
Short name T89
Test name
Test status
Simulation time 65943034000 ps
CPU time 119.09 seconds
Started Jun 05 05:23:36 PM PDT 24
Finished Jun 05 05:25:36 PM PDT 24
Peak memory 198612 kb
Host smart-c1ddf641-bfeb-4acc-9fef-cd06713bc72a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253164995 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.4253164995
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3065407509
Short name T145
Test name
Test status
Simulation time 112130167137 ps
CPU time 60.61 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:24:41 PM PDT 24
Peak memory 192952 kb
Host smart-d0bf1530-803c-4d0c-b2cf-273eabc317ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065407509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3065407509
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.438796969
Short name T102
Test name
Test status
Simulation time 103657526657 ps
CPU time 172.25 seconds
Started Jun 05 05:22:59 PM PDT 24
Finished Jun 05 05:25:52 PM PDT 24
Peak memory 191908 kb
Host smart-150ce0a8-83fe-4d15-8579-05300e5964eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438796969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.438796969
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.594713150
Short name T150
Test name
Test status
Simulation time 204582210641 ps
CPU time 81.92 seconds
Started Jun 05 05:23:23 PM PDT 24
Finished Jun 05 05:24:46 PM PDT 24
Peak memory 192660 kb
Host smart-9a7b80f9-b921-4350-afb6-e59e18845d67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594713150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.594713150
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3983456418
Short name T160
Test name
Test status
Simulation time 459299505852 ps
CPU time 410.28 seconds
Started Jun 05 05:22:53 PM PDT 24
Finished Jun 05 05:29:44 PM PDT 24
Peak memory 192408 kb
Host smart-60c83080-dea4-4ae0-aac0-a7c71807bf44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983456418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3983456418
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2094364373
Short name T136
Test name
Test status
Simulation time 74124277326 ps
CPU time 23.56 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:25 PM PDT 24
Peak memory 192608 kb
Host smart-e37dd197-86c6-471d-8cbe-8221afd5a606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094364373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2094364373
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3323504053
Short name T156
Test name
Test status
Simulation time 116376008968 ps
CPU time 47.86 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:49 PM PDT 24
Peak memory 192848 kb
Host smart-ed574b94-4d31-4c19-a83c-111759e74445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323504053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3323504053
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.570052529
Short name T117
Test name
Test status
Simulation time 223493321576 ps
CPU time 30.16 seconds
Started Jun 05 05:23:13 PM PDT 24
Finished Jun 05 05:23:43 PM PDT 24
Peak memory 191948 kb
Host smart-36f70557-c5bc-4c69-9fad-1538c5e96473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570052529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.570052529
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1569833069
Short name T116
Test name
Test status
Simulation time 217198961673 ps
CPU time 354.76 seconds
Started Jun 05 05:23:06 PM PDT 24
Finished Jun 05 05:29:01 PM PDT 24
Peak memory 192968 kb
Host smart-ea981454-8b2d-4a6a-b5e0-c4f2c1f69a61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569833069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1569833069
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3966613820
Short name T124
Test name
Test status
Simulation time 394295869967 ps
CPU time 249.6 seconds
Started Jun 05 05:23:39 PM PDT 24
Finished Jun 05 05:27:49 PM PDT 24
Peak memory 192596 kb
Host smart-3a2371f7-291c-4a81-929c-cc541e16c259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966613820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3966613820
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.4265207053
Short name T96
Test name
Test status
Simulation time 60945273949 ps
CPU time 97.35 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:24:38 PM PDT 24
Peak memory 192944 kb
Host smart-4d5cc1ef-c19c-4c1d-aef3-18bb8e17e3eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265207053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.4265207053
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1240778986
Short name T59
Test name
Test status
Simulation time 97009945641 ps
CPU time 36.42 seconds
Started Jun 05 05:23:41 PM PDT 24
Finished Jun 05 05:24:18 PM PDT 24
Peak memory 191940 kb
Host smart-b46676b2-c756-41f6-b093-3b3ff092fda5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240778986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1240778986
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1603950692
Short name T128
Test name
Test status
Simulation time 5081514981 ps
CPU time 33.13 seconds
Started Jun 05 05:23:41 PM PDT 24
Finished Jun 05 05:24:15 PM PDT 24
Peak memory 206828 kb
Host smart-2f4f808c-924f-4c2c-ac5b-5463219a064d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603950692 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1603950692
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.668234765
Short name T114
Test name
Test status
Simulation time 4476244134 ps
CPU time 7.59 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:09 PM PDT 24
Peak memory 191936 kb
Host smart-4b556cb7-15b7-419d-95af-ffbcdce7bb5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668234765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.668234765
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3124159876
Short name T22
Test name
Test status
Simulation time 10896197126 ps
CPU time 5.16 seconds
Started Jun 05 05:22:55 PM PDT 24
Finished Jun 05 05:23:01 PM PDT 24
Peak memory 192944 kb
Host smart-e9b34576-15dc-4c77-bfb9-39eb85e34c97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124159876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3124159876
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2467014210
Short name T115
Test name
Test status
Simulation time 100031306428 ps
CPU time 151.99 seconds
Started Jun 05 05:23:13 PM PDT 24
Finished Jun 05 05:25:46 PM PDT 24
Peak memory 192588 kb
Host smart-5202fa57-4cd2-4ddb-b12e-5dfe05f0715d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467014210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2467014210
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1369481519
Short name T104
Test name
Test status
Simulation time 406425602 ps
CPU time 1.05 seconds
Started Jun 05 05:23:02 PM PDT 24
Finished Jun 05 05:23:04 PM PDT 24
Peak memory 196440 kb
Host smart-d57c2ffe-7f6c-4fc9-815d-269e397ead39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369481519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1369481519
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3625490218
Short name T153
Test name
Test status
Simulation time 405358451 ps
CPU time 0.77 seconds
Started Jun 05 05:23:14 PM PDT 24
Finished Jun 05 05:23:15 PM PDT 24
Peak memory 196516 kb
Host smart-483468ac-4745-4c82-96e5-83bf74d74c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625490218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3625490218
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1430030935
Short name T143
Test name
Test status
Simulation time 60907388313 ps
CPU time 343.84 seconds
Started Jun 05 05:23:34 PM PDT 24
Finished Jun 05 05:29:18 PM PDT 24
Peak memory 208824 kb
Host smart-84a603c2-6991-44ba-bde1-fbbb2d8f63bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430030935 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1430030935
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.765005695
Short name T127
Test name
Test status
Simulation time 467231336 ps
CPU time 1.12 seconds
Started Jun 05 05:22:50 PM PDT 24
Finished Jun 05 05:22:52 PM PDT 24
Peak memory 196428 kb
Host smart-1d0b4b61-8a15-4fbe-8c70-bc8a287368c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765005695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.765005695
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1222517753
Short name T112
Test name
Test status
Simulation time 295532986996 ps
CPU time 117.92 seconds
Started Jun 05 05:22:51 PM PDT 24
Finished Jun 05 05:24:50 PM PDT 24
Peak memory 192660 kb
Host smart-9c6b58d7-e8de-486f-ae3d-add03f4d3725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222517753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1222517753
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1593539087
Short name T158
Test name
Test status
Simulation time 431722190 ps
CPU time 0.88 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:23:42 PM PDT 24
Peak memory 196452 kb
Host smart-a7889271-557e-4152-8281-a335999c774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593539087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1593539087
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.773265099
Short name T126
Test name
Test status
Simulation time 117411559181 ps
CPU time 40.06 seconds
Started Jun 05 05:23:41 PM PDT 24
Finished Jun 05 05:24:22 PM PDT 24
Peak memory 184088 kb
Host smart-b2c4794b-93de-4212-9918-7b348aa281b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773265099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.773265099
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.951332549
Short name T97
Test name
Test status
Simulation time 645614170 ps
CPU time 0.73 seconds
Started Jun 05 05:23:48 PM PDT 24
Finished Jun 05 05:23:50 PM PDT 24
Peak memory 196440 kb
Host smart-bb20e8dd-770f-4308-8830-6010d199d07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951332549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.951332549
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2387101336
Short name T113
Test name
Test status
Simulation time 379794906 ps
CPU time 0.85 seconds
Started Jun 05 05:23:55 PM PDT 24
Finished Jun 05 05:23:57 PM PDT 24
Peak memory 196520 kb
Host smart-fce8c33a-581d-4006-b074-de9d6d75ad42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387101336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2387101336
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3718485052
Short name T106
Test name
Test status
Simulation time 66748653224 ps
CPU time 51.05 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:53 PM PDT 24
Peak memory 192948 kb
Host smart-22331b05-b799-48cd-ae88-3d776ee40dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718485052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3718485052
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3769669860
Short name T109
Test name
Test status
Simulation time 152788072363 ps
CPU time 447.12 seconds
Started Jun 05 05:23:01 PM PDT 24
Finished Jun 05 05:30:30 PM PDT 24
Peak memory 203628 kb
Host smart-78f4a059-50e5-4f6b-b5dd-cdd0f035c63d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769669860 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3769669860
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3125175066
Short name T152
Test name
Test status
Simulation time 11490507166 ps
CPU time 83.51 seconds
Started Jun 05 05:23:22 PM PDT 24
Finished Jun 05 05:24:46 PM PDT 24
Peak memory 206836 kb
Host smart-2442bfe9-4368-4a04-95ca-e6ee9f73d136
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125175066 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3125175066
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2757772364
Short name T161
Test name
Test status
Simulation time 76553411346 ps
CPU time 24.34 seconds
Started Jun 05 05:22:50 PM PDT 24
Finished Jun 05 05:23:15 PM PDT 24
Peak memory 191904 kb
Host smart-143eb627-1488-472c-9de2-480bae6ce2b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757772364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2757772364
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3667284364
Short name T52
Test name
Test status
Simulation time 568617361 ps
CPU time 0.82 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:23:42 PM PDT 24
Peak memory 196440 kb
Host smart-0e113b9a-a537-4685-9984-54b165225d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667284364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3667284364
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.4123787470
Short name T131
Test name
Test status
Simulation time 444927434 ps
CPU time 0.76 seconds
Started Jun 05 05:23:46 PM PDT 24
Finished Jun 05 05:23:47 PM PDT 24
Peak memory 196448 kb
Host smart-8dac428d-30a4-4113-a37d-081d8471ccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123787470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.4123787470
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1872496183
Short name T99
Test name
Test status
Simulation time 455964806648 ps
CPU time 650.47 seconds
Started Jun 05 05:23:06 PM PDT 24
Finished Jun 05 05:33:57 PM PDT 24
Peak memory 191932 kb
Host smart-395eb131-4a02-475c-9b4d-43904231fd36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872496183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1872496183
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1686250547
Short name T163
Test name
Test status
Simulation time 43902154057 ps
CPU time 354.75 seconds
Started Jun 05 05:23:49 PM PDT 24
Finished Jun 05 05:29:44 PM PDT 24
Peak memory 199460 kb
Host smart-ed2b19ac-e6b5-416b-a2eb-3256d8b6eb76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686250547 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1686250547
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.223583248
Short name T130
Test name
Test status
Simulation time 464484747 ps
CPU time 1.39 seconds
Started Jun 05 05:23:37 PM PDT 24
Finished Jun 05 05:23:40 PM PDT 24
Peak memory 196452 kb
Host smart-d20806fe-afab-46ba-887a-467f977fef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223583248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.223583248
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.315530941
Short name T98
Test name
Test status
Simulation time 478713050 ps
CPU time 0.7 seconds
Started Jun 05 05:23:37 PM PDT 24
Finished Jun 05 05:23:39 PM PDT 24
Peak memory 196468 kb
Host smart-9e518db0-e2a6-4169-980f-557946d2400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315530941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.315530941
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3947284278
Short name T155
Test name
Test status
Simulation time 30846484426 ps
CPU time 216.04 seconds
Started Jun 05 05:23:34 PM PDT 24
Finished Jun 05 05:27:11 PM PDT 24
Peak memory 198684 kb
Host smart-234597ed-30a6-4e8f-ae5b-c92fed74b5e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947284278 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3947284278
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2616812581
Short name T24
Test name
Test status
Simulation time 167891841317 ps
CPU time 663.46 seconds
Started Jun 05 05:23:01 PM PDT 24
Finished Jun 05 05:34:06 PM PDT 24
Peak memory 213824 kb
Host smart-f583f6bf-deae-4256-be77-2f83db902ecd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616812581 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2616812581
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.4087604310
Short name T118
Test name
Test status
Simulation time 360456134 ps
CPU time 1.11 seconds
Started Jun 05 05:22:44 PM PDT 24
Finished Jun 05 05:22:46 PM PDT 24
Peak memory 196464 kb
Host smart-e54bffdb-c67e-4f20-b997-3b50f2271dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087604310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4087604310
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1812613250
Short name T132
Test name
Test status
Simulation time 540978482 ps
CPU time 1.02 seconds
Started Jun 05 05:23:07 PM PDT 24
Finished Jun 05 05:23:09 PM PDT 24
Peak memory 196456 kb
Host smart-3c088dad-6640-4314-8463-a6127ac42ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812613250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1812613250
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.855157023
Short name T29
Test name
Test status
Simulation time 336602920 ps
CPU time 0.84 seconds
Started Jun 05 05:23:35 PM PDT 24
Finished Jun 05 05:23:37 PM PDT 24
Peak memory 196532 kb
Host smart-fc8c1ad4-e805-4df6-b6fe-0635265de08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855157023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.855157023
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.4222691934
Short name T166
Test name
Test status
Simulation time 339435407062 ps
CPU time 25.38 seconds
Started Jun 05 05:23:49 PM PDT 24
Finished Jun 05 05:24:15 PM PDT 24
Peak memory 184660 kb
Host smart-bb627f60-1fa1-4d78-887c-7fd2f788b1d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222691934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.4222691934
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3350451363
Short name T157
Test name
Test status
Simulation time 461789487 ps
CPU time 0.99 seconds
Started Jun 05 05:23:07 PM PDT 24
Finished Jun 05 05:23:08 PM PDT 24
Peak memory 196396 kb
Host smart-dfeadf86-28dc-413c-9990-7497c5edb776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350451363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3350451363
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3817326961
Short name T139
Test name
Test status
Simulation time 541555682 ps
CPU time 1.52 seconds
Started Jun 05 05:23:06 PM PDT 24
Finished Jun 05 05:23:08 PM PDT 24
Peak memory 196432 kb
Host smart-90da1b19-1202-4b8a-b233-dcbbb51c8a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817326961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3817326961
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2712823269
Short name T49
Test name
Test status
Simulation time 389670387 ps
CPU time 0.88 seconds
Started Jun 05 05:23:17 PM PDT 24
Finished Jun 05 05:23:18 PM PDT 24
Peak memory 196472 kb
Host smart-0e087f45-cba0-41ce-a5cb-8b851f8ec505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712823269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2712823269
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2070828273
Short name T119
Test name
Test status
Simulation time 231896827348 ps
CPU time 248.49 seconds
Started Jun 05 05:23:02 PM PDT 24
Finished Jun 05 05:27:12 PM PDT 24
Peak memory 192948 kb
Host smart-005ae624-9d55-4264-9a97-c279e70f3294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070828273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2070828273
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1736643899
Short name T149
Test name
Test status
Simulation time 502137658 ps
CPU time 1.34 seconds
Started Jun 05 05:23:21 PM PDT 24
Finished Jun 05 05:23:23 PM PDT 24
Peak memory 196416 kb
Host smart-ceeb5409-0482-4999-b526-c5c4db2d9d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736643899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1736643899
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2721562581
Short name T165
Test name
Test status
Simulation time 61651214296 ps
CPU time 80.38 seconds
Started Jun 05 05:23:34 PM PDT 24
Finished Jun 05 05:24:55 PM PDT 24
Peak memory 191916 kb
Host smart-b209c9e2-a803-4bc3-843e-7887667b798b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721562581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2721562581
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1089927903
Short name T93
Test name
Test status
Simulation time 116978317546 ps
CPU time 234.93 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:27:36 PM PDT 24
Peak memory 200352 kb
Host smart-01a72a34-5476-4dd8-ba79-39d49c2a0518
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089927903 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1089927903
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2580328923
Short name T146
Test name
Test status
Simulation time 547840623 ps
CPU time 0.79 seconds
Started Jun 05 05:23:39 PM PDT 24
Finished Jun 05 05:23:41 PM PDT 24
Peak memory 196512 kb
Host smart-ac30ee83-2ee0-45bc-a43c-07ba74b35840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580328923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2580328923
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3889194136
Short name T40
Test name
Test status
Simulation time 408921638982 ps
CPU time 455.02 seconds
Started Jun 05 05:23:55 PM PDT 24
Finished Jun 05 05:31:31 PM PDT 24
Peak memory 211860 kb
Host smart-55759c7b-29a0-4941-8639-d286143eeda1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889194136 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3889194136
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.995268701
Short name T101
Test name
Test status
Simulation time 586537409 ps
CPU time 0.82 seconds
Started Jun 05 05:23:01 PM PDT 24
Finished Jun 05 05:23:03 PM PDT 24
Peak memory 196460 kb
Host smart-e08871c5-6c7c-4549-8e15-b234f87bdd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995268701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.995268701
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.228584907
Short name T147
Test name
Test status
Simulation time 433902076 ps
CPU time 0.66 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:44 PM PDT 24
Peak memory 196528 kb
Host smart-8d5bf948-35db-4246-8927-10af16a81d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228584907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.228584907
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.197905102
Short name T197
Test name
Test status
Simulation time 72985357847 ps
CPU time 166.3 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:25:30 PM PDT 24
Peak memory 198892 kb
Host smart-99f14ea2-767c-40ab-8223-38ffb654cf4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197905102 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.197905102
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3526979812
Short name T174
Test name
Test status
Simulation time 206785356839 ps
CPU time 163.99 seconds
Started Jun 05 05:22:58 PM PDT 24
Finished Jun 05 05:25:43 PM PDT 24
Peak memory 191932 kb
Host smart-1fa1080e-1ed3-493d-a28f-be9d959b6333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526979812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3526979812
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.4168264873
Short name T14
Test name
Test status
Simulation time 91676587431 ps
CPU time 173.44 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:25:55 PM PDT 24
Peak memory 199668 kb
Host smart-e7b5b68c-4b9a-48f4-a1c8-23235bcab052
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168264873 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.4168264873
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.915197125
Short name T26
Test name
Test status
Simulation time 583986745 ps
CPU time 1.42 seconds
Started Jun 05 05:23:07 PM PDT 24
Finished Jun 05 05:23:09 PM PDT 24
Peak memory 196496 kb
Host smart-81b552aa-6591-4309-b2e1-63eb4a15e63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915197125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.915197125
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3227600780
Short name T151
Test name
Test status
Simulation time 437442420 ps
CPU time 0.98 seconds
Started Jun 05 05:23:08 PM PDT 24
Finished Jun 05 05:23:09 PM PDT 24
Peak memory 196456 kb
Host smart-5ebfd70b-0c91-4ad5-8d75-ee891262e910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227600780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3227600780
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1661945095
Short name T190
Test name
Test status
Simulation time 167335812511 ps
CPU time 57.17 seconds
Started Jun 05 05:23:37 PM PDT 24
Finished Jun 05 05:24:35 PM PDT 24
Peak memory 191948 kb
Host smart-e04086da-af26-4b85-9b4d-76ebdc17fff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661945095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1661945095
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2160307143
Short name T140
Test name
Test status
Simulation time 373845391 ps
CPU time 1.15 seconds
Started Jun 05 05:22:51 PM PDT 24
Finished Jun 05 05:22:54 PM PDT 24
Peak memory 196592 kb
Host smart-00f5f9ca-9799-430d-b49a-a3774757446a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160307143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2160307143
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3842061339
Short name T194
Test name
Test status
Simulation time 565839174 ps
CPU time 1.58 seconds
Started Jun 05 05:23:37 PM PDT 24
Finished Jun 05 05:23:40 PM PDT 24
Peak memory 196424 kb
Host smart-523cdbfa-3706-4e8c-b2c7-d96e67b8c073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842061339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3842061339
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.4212724278
Short name T181
Test name
Test status
Simulation time 528107202 ps
CPU time 0.8 seconds
Started Jun 05 05:23:47 PM PDT 24
Finished Jun 05 05:23:49 PM PDT 24
Peak memory 196516 kb
Host smart-c816cf98-2359-4036-aee3-d71ce27f3d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212724278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.4212724278
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2343665464
Short name T12
Test name
Test status
Simulation time 58281116502 ps
CPU time 22.53 seconds
Started Jun 05 05:23:49 PM PDT 24
Finished Jun 05 05:24:12 PM PDT 24
Peak memory 191876 kb
Host smart-37016dd0-f0ee-43ab-9435-59784a71ed3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343665464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2343665464
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3918375325
Short name T141
Test name
Test status
Simulation time 467077775 ps
CPU time 0.72 seconds
Started Jun 05 05:23:53 PM PDT 24
Finished Jun 05 05:23:54 PM PDT 24
Peak memory 196416 kb
Host smart-fa872fec-50b5-40db-ab18-8181ef39ce2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918375325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3918375325
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4029372392
Short name T419
Test name
Test status
Simulation time 8156507860 ps
CPU time 7.3 seconds
Started Jun 05 05:24:19 PM PDT 24
Finished Jun 05 05:24:27 PM PDT 24
Peak memory 198088 kb
Host smart-c5823a77-281b-4fdb-a610-d03cbfeb0340
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029372392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.4029372392
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_jump.926605213
Short name T170
Test name
Test status
Simulation time 530015009 ps
CPU time 0.83 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:03 PM PDT 24
Peak memory 196424 kb
Host smart-ce1fa838-9011-449e-9cf2-8a2b1d70aebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926605213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.926605213
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1904952266
Short name T173
Test name
Test status
Simulation time 396635032 ps
CPU time 0.89 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:03 PM PDT 24
Peak memory 196456 kb
Host smart-5c102bfe-ceda-4136-b001-5c3656c31fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904952266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1904952266
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1347875989
Short name T177
Test name
Test status
Simulation time 546982493 ps
CPU time 1 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:03 PM PDT 24
Peak memory 196428 kb
Host smart-3117932e-b853-4d01-a60f-4a67ff557f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347875989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1347875989
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2023730121
Short name T191
Test name
Test status
Simulation time 44632339729 ps
CPU time 338.11 seconds
Started Jun 05 05:22:59 PM PDT 24
Finished Jun 05 05:28:38 PM PDT 24
Peak memory 207276 kb
Host smart-38450295-3dd5-4afb-920d-d4945746de06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023730121 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2023730121
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.416151155
Short name T193
Test name
Test status
Simulation time 555559580 ps
CPU time 0.83 seconds
Started Jun 05 05:23:21 PM PDT 24
Finished Jun 05 05:23:23 PM PDT 24
Peak memory 196420 kb
Host smart-83f709ff-ce3a-4fe5-9250-52f35278caea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416151155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.416151155
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2284549707
Short name T134
Test name
Test status
Simulation time 400458316 ps
CPU time 0.76 seconds
Started Jun 05 05:23:19 PM PDT 24
Finished Jun 05 05:23:20 PM PDT 24
Peak memory 196432 kb
Host smart-59957778-1922-4da9-a0e3-c23208f097bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284549707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2284549707
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4089905049
Short name T189
Test name
Test status
Simulation time 478491898 ps
CPU time 0.97 seconds
Started Jun 05 05:23:48 PM PDT 24
Finished Jun 05 05:23:50 PM PDT 24
Peak memory 196476 kb
Host smart-3e532eba-838f-4f24-b99e-d221e74103cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089905049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4089905049
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1219853882
Short name T171
Test name
Test status
Simulation time 60924705728 ps
CPU time 5.44 seconds
Started Jun 05 05:23:50 PM PDT 24
Finished Jun 05 05:23:56 PM PDT 24
Peak memory 193016 kb
Host smart-befa168f-7276-4ed1-a3ae-6618c378d112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219853882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1219853882
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3753981336
Short name T168
Test name
Test status
Simulation time 623013942415 ps
CPU time 115.02 seconds
Started Jun 05 05:23:01 PM PDT 24
Finished Jun 05 05:24:57 PM PDT 24
Peak memory 192976 kb
Host smart-65bb9153-eb7b-41a6-b872-06975ac15468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753981336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3753981336
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1625923961
Short name T182
Test name
Test status
Simulation time 588911362 ps
CPU time 1.53 seconds
Started Jun 05 05:22:58 PM PDT 24
Finished Jun 05 05:23:00 PM PDT 24
Peak memory 196508 kb
Host smart-ec4af520-f531-4153-aea8-1493f231ac0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625923961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1625923961
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3869221903
Short name T43
Test name
Test status
Simulation time 477217329 ps
CPU time 1.31 seconds
Started Jun 05 05:23:17 PM PDT 24
Finished Jun 05 05:23:18 PM PDT 24
Peak memory 196444 kb
Host smart-da39dc73-182c-4470-aa01-424e86922a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869221903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3869221903
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3335821309
Short name T183
Test name
Test status
Simulation time 494899652 ps
CPU time 1.39 seconds
Started Jun 05 05:23:15 PM PDT 24
Finished Jun 05 05:23:17 PM PDT 24
Peak memory 196424 kb
Host smart-5c5277ab-638c-45dc-a1a0-c03fbece525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335821309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3335821309
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1838845442
Short name T164
Test name
Test status
Simulation time 38990347262 ps
CPU time 228.6 seconds
Started Jun 05 05:23:14 PM PDT 24
Finished Jun 05 05:27:03 PM PDT 24
Peak memory 206864 kb
Host smart-5bc7e894-a182-4de4-8a95-a5d848ddcad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838845442 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1838845442
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3798885120
Short name T38
Test name
Test status
Simulation time 43682691931 ps
CPU time 267.31 seconds
Started Jun 05 05:23:23 PM PDT 24
Finished Jun 05 05:27:51 PM PDT 24
Peak memory 214220 kb
Host smart-61e02279-44cc-4523-a2ce-d61cdd96ce4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798885120 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3798885120
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3941706625
Short name T195
Test name
Test status
Simulation time 424119677 ps
CPU time 0.71 seconds
Started Jun 05 05:23:35 PM PDT 24
Finished Jun 05 05:23:37 PM PDT 24
Peak memory 196640 kb
Host smart-0a7f2038-2d0a-48cb-b4ca-7aca3d946129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941706625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3941706625
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1355746273
Short name T86
Test name
Test status
Simulation time 30505614854 ps
CPU time 238.65 seconds
Started Jun 05 05:23:37 PM PDT 24
Finished Jun 05 05:27:36 PM PDT 24
Peak memory 206920 kb
Host smart-dfcecab0-28f7-49cf-b766-074b30d09610
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355746273 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1355746273
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2144803025
Short name T185
Test name
Test status
Simulation time 569337248 ps
CPU time 0.68 seconds
Started Jun 05 05:23:35 PM PDT 24
Finished Jun 05 05:23:37 PM PDT 24
Peak memory 196424 kb
Host smart-f1bfd49e-6a11-4d99-9116-503fdb0a9dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144803025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2144803025
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1263153368
Short name T192
Test name
Test status
Simulation time 501456213 ps
CPU time 0.79 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:23:42 PM PDT 24
Peak memory 196576 kb
Host smart-a8a99b36-1a0c-454b-ad2a-63a3fff0ea37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263153368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1263153368
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1948188423
Short name T176
Test name
Test status
Simulation time 153572794744 ps
CPU time 216.14 seconds
Started Jun 05 05:23:50 PM PDT 24
Finished Jun 05 05:27:26 PM PDT 24
Peak memory 184060 kb
Host smart-1cbeeacc-aaab-4582-abd4-b34e752b60f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948188423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1948188423
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3390111229
Short name T57
Test name
Test status
Simulation time 395032697 ps
CPU time 0.85 seconds
Started Jun 05 05:22:52 PM PDT 24
Finished Jun 05 05:22:54 PM PDT 24
Peak memory 196448 kb
Host smart-3ee9f1fb-33c2-497d-bf43-b4296a28f49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390111229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3390111229
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2452567423
Short name T64
Test name
Test status
Simulation time 575536423 ps
CPU time 0.74 seconds
Started Jun 05 05:23:53 PM PDT 24
Finished Jun 05 05:23:54 PM PDT 24
Peak memory 183708 kb
Host smart-4982c9d4-c917-4e34-8db9-f36eb1721829
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452567423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2452567423
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1863134201
Short name T75
Test name
Test status
Simulation time 11672047811 ps
CPU time 17.81 seconds
Started Jun 05 05:23:57 PM PDT 24
Finished Jun 05 05:24:16 PM PDT 24
Peak memory 183952 kb
Host smart-123851a7-0be3-414a-a477-288dfa699d31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863134201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1863134201
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1971542980
Short name T299
Test name
Test status
Simulation time 929985313 ps
CPU time 1.28 seconds
Started Jun 05 05:23:54 PM PDT 24
Finished Jun 05 05:23:55 PM PDT 24
Peak memory 183732 kb
Host smart-bedc5a5a-6538-486a-ba67-e5751c972d5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971542980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1971542980
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1743825081
Short name T34
Test name
Test status
Simulation time 769054199 ps
CPU time 0.8 seconds
Started Jun 05 05:23:52 PM PDT 24
Finished Jun 05 05:23:53 PM PDT 24
Peak memory 197500 kb
Host smart-2a0d4fb3-bc2b-45cf-82aa-c84dabe75418
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743825081 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1743825081
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2045701195
Short name T370
Test name
Test status
Simulation time 408431370 ps
CPU time 0.66 seconds
Started Jun 05 05:24:01 PM PDT 24
Finished Jun 05 05:24:02 PM PDT 24
Peak memory 192916 kb
Host smart-ce382f1c-ba78-41c3-8f10-08ca18ff42fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045701195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2045701195
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.275972541
Short name T283
Test name
Test status
Simulation time 517269953 ps
CPU time 0.64 seconds
Started Jun 05 05:23:47 PM PDT 24
Finished Jun 05 05:23:48 PM PDT 24
Peak memory 183592 kb
Host smart-13109e49-1a8d-403c-bb50-ac2a36d7eecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275972541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.275972541
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2213158458
Short name T286
Test name
Test status
Simulation time 471254886 ps
CPU time 0.71 seconds
Started Jun 05 05:24:00 PM PDT 24
Finished Jun 05 05:24:01 PM PDT 24
Peak memory 183508 kb
Host smart-5918d7f0-65f1-47f0-a81c-3a27b35701e6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213158458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2213158458
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.739863708
Short name T331
Test name
Test status
Simulation time 501959065 ps
CPU time 0.71 seconds
Started Jun 05 05:23:48 PM PDT 24
Finished Jun 05 05:23:50 PM PDT 24
Peak memory 183632 kb
Host smart-5cd01f2b-fade-49e8-8b5d-a106a558c166
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739863708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.739863708
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.22860632
Short name T79
Test name
Test status
Simulation time 2109408053 ps
CPU time 4.7 seconds
Started Jun 05 05:23:57 PM PDT 24
Finished Jun 05 05:24:02 PM PDT 24
Peak memory 194580 kb
Host smart-34196e00-6519-4e57-ab23-f2c0c388c50e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22860632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_same_csr_outstanding.22860632
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3270718116
Short name T298
Test name
Test status
Simulation time 353846062 ps
CPU time 2.15 seconds
Started Jun 05 05:23:58 PM PDT 24
Finished Jun 05 05:24:01 PM PDT 24
Peak memory 198452 kb
Host smart-d093d8ea-e0aa-4f5b-91cf-d7ed5225af21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270718116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3270718116
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1014792128
Short name T364
Test name
Test status
Simulation time 4528771035 ps
CPU time 2.66 seconds
Started Jun 05 05:23:48 PM PDT 24
Finished Jun 05 05:23:51 PM PDT 24
Peak memory 197776 kb
Host smart-18d654c5-6170-4715-925f-00440ae158d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014792128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1014792128
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2046676792
Short name T88
Test name
Test status
Simulation time 492326978 ps
CPU time 1.13 seconds
Started Jun 05 05:23:51 PM PDT 24
Finished Jun 05 05:23:53 PM PDT 24
Peak memory 183644 kb
Host smart-18610ff6-7b45-44fe-aacc-7d73ab00f916
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046676792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2046676792
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3850770412
Short name T67
Test name
Test status
Simulation time 8575285454 ps
CPU time 8.39 seconds
Started Jun 05 05:24:01 PM PDT 24
Finished Jun 05 05:24:10 PM PDT 24
Peak memory 195432 kb
Host smart-5030ed78-3c00-4cbd-836e-e1271a07cab4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850770412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3850770412
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.4036861387
Short name T61
Test name
Test status
Simulation time 957988333 ps
CPU time 1.28 seconds
Started Jun 05 05:23:56 PM PDT 24
Finished Jun 05 05:23:58 PM PDT 24
Peak memory 183704 kb
Host smart-56f6ef6e-28dd-4836-97e1-9e51507926f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036861387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.4036861387
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4228065091
Short name T414
Test name
Test status
Simulation time 336135527 ps
CPU time 0.84 seconds
Started Jun 05 05:24:02 PM PDT 24
Finished Jun 05 05:24:03 PM PDT 24
Peak memory 195160 kb
Host smart-d9df741d-ed9a-4e96-8932-c4bc9a69872f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228065091 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.4228065091
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.451799227
Short name T71
Test name
Test status
Simulation time 507315514 ps
CPU time 1.39 seconds
Started Jun 05 05:23:53 PM PDT 24
Finished Jun 05 05:23:54 PM PDT 24
Peak memory 183784 kb
Host smart-f2232c33-a103-4c68-b73c-3180eb500542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451799227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.451799227
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3981143678
Short name T409
Test name
Test status
Simulation time 388490662 ps
CPU time 1.08 seconds
Started Jun 05 05:23:57 PM PDT 24
Finished Jun 05 05:23:58 PM PDT 24
Peak memory 183648 kb
Host smart-ba1d61c5-48f8-4d8a-83fb-dbef31b4b9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981143678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3981143678
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3456203113
Short name T351
Test name
Test status
Simulation time 379651872 ps
CPU time 0.62 seconds
Started Jun 05 05:23:59 PM PDT 24
Finished Jun 05 05:24:00 PM PDT 24
Peak memory 183568 kb
Host smart-d967d555-a7ea-4ea1-a2fb-42523e55daf6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456203113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3456203113
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2274044491
Short name T415
Test name
Test status
Simulation time 365338611 ps
CPU time 0.81 seconds
Started Jun 05 05:23:59 PM PDT 24
Finished Jun 05 05:24:00 PM PDT 24
Peak memory 183640 kb
Host smart-2fc0faf8-79ab-4ddd-b444-dc0601a69ff6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274044491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2274044491
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4187839895
Short name T82
Test name
Test status
Simulation time 1286802642 ps
CPU time 1.44 seconds
Started Jun 05 05:23:58 PM PDT 24
Finished Jun 05 05:24:00 PM PDT 24
Peak memory 193432 kb
Host smart-a544350b-910a-4c52-88d9-544368249cb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187839895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.4187839895
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2028058356
Short name T322
Test name
Test status
Simulation time 619192767 ps
CPU time 1.23 seconds
Started Jun 05 05:23:57 PM PDT 24
Finished Jun 05 05:23:59 PM PDT 24
Peak memory 198356 kb
Host smart-1919028e-8198-4be4-8de7-2ff48ce6a72b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028058356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2028058356
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3177284974
Short name T199
Test name
Test status
Simulation time 8077159076 ps
CPU time 7.7 seconds
Started Jun 05 05:23:51 PM PDT 24
Finished Jun 05 05:24:00 PM PDT 24
Peak memory 198352 kb
Host smart-66792ad5-acee-4e2a-994c-50640af92479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177284974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3177284974
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1412164591
Short name T317
Test name
Test status
Simulation time 405479364 ps
CPU time 1.04 seconds
Started Jun 05 05:24:21 PM PDT 24
Finished Jun 05 05:24:23 PM PDT 24
Peak memory 196924 kb
Host smart-dfe0d2ad-401a-4919-9820-85681859c5a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412164591 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1412164591
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.84722758
Short name T359
Test name
Test status
Simulation time 330104642 ps
CPU time 1.07 seconds
Started Jun 05 05:24:20 PM PDT 24
Finished Jun 05 05:24:22 PM PDT 24
Peak memory 193184 kb
Host smart-fd7fc122-a5ee-4f31-8593-a1dddb1a5c10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84722758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.84722758
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2307523632
Short name T393
Test name
Test status
Simulation time 306841679 ps
CPU time 0.67 seconds
Started Jun 05 05:24:19 PM PDT 24
Finished Jun 05 05:24:21 PM PDT 24
Peak memory 183648 kb
Host smart-74e942fc-c90e-4418-8425-d49d462c95d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307523632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2307523632
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2180623906
Short name T378
Test name
Test status
Simulation time 900095069 ps
CPU time 2.02 seconds
Started Jun 05 05:24:23 PM PDT 24
Finished Jun 05 05:24:25 PM PDT 24
Peak memory 193176 kb
Host smart-6bb59195-f9c3-4a47-b3a0-070979ff543b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180623906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2180623906
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2737085655
Short name T374
Test name
Test status
Simulation time 702549256 ps
CPU time 1.41 seconds
Started Jun 05 05:24:19 PM PDT 24
Finished Jun 05 05:24:20 PM PDT 24
Peak memory 198448 kb
Host smart-02980d22-df2b-45e2-81fc-8ad64a8a996e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737085655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2737085655
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2825879626
Short name T200
Test name
Test status
Simulation time 7842133854 ps
CPU time 12.4 seconds
Started Jun 05 05:24:21 PM PDT 24
Finished Jun 05 05:24:34 PM PDT 24
Peak memory 197828 kb
Host smart-5edf900d-6307-439e-8f8f-9150fd634e97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825879626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2825879626
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2356578231
Short name T361
Test name
Test status
Simulation time 362450088 ps
CPU time 1.24 seconds
Started Jun 05 05:24:20 PM PDT 24
Finished Jun 05 05:24:22 PM PDT 24
Peak memory 196244 kb
Host smart-8abe79cc-5016-4296-96f0-2610cced2e3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356578231 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2356578231
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1670289409
Short name T77
Test name
Test status
Simulation time 501186059 ps
CPU time 0.82 seconds
Started Jun 05 05:24:25 PM PDT 24
Finished Jun 05 05:24:26 PM PDT 24
Peak memory 193196 kb
Host smart-df42f850-5728-4259-ac89-0b4a12ab4d5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670289409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1670289409
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.631629821
Short name T295
Test name
Test status
Simulation time 379771878 ps
CPU time 0.63 seconds
Started Jun 05 05:24:21 PM PDT 24
Finished Jun 05 05:24:23 PM PDT 24
Peak memory 183624 kb
Host smart-f10865ac-b4ba-4a7e-8507-f97b5e761266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631629821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.631629821
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2617066556
Short name T84
Test name
Test status
Simulation time 2090366325 ps
CPU time 5.55 seconds
Started Jun 05 05:24:18 PM PDT 24
Finished Jun 05 05:24:24 PM PDT 24
Peak memory 183708 kb
Host smart-6468f000-f858-41d5-8f3d-8b1cc1a148e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617066556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2617066556
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3621298514
Short name T307
Test name
Test status
Simulation time 379362498 ps
CPU time 2.44 seconds
Started Jun 05 05:24:20 PM PDT 24
Finished Jun 05 05:24:23 PM PDT 24
Peak memory 198480 kb
Host smart-2289ae13-6588-4665-88e0-9c1b8519d64b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621298514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3621298514
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3246893369
Short name T338
Test name
Test status
Simulation time 585666519 ps
CPU time 1.61 seconds
Started Jun 05 05:24:31 PM PDT 24
Finished Jun 05 05:24:34 PM PDT 24
Peak memory 196292 kb
Host smart-9ffbf18f-fcf3-4517-93d6-989a2150ff2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246893369 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3246893369
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.419477852
Short name T33
Test name
Test status
Simulation time 290865275 ps
CPU time 0.79 seconds
Started Jun 05 05:24:29 PM PDT 24
Finished Jun 05 05:24:31 PM PDT 24
Peak memory 192932 kb
Host smart-c4066710-8991-4d4e-a721-11f28b2477b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419477852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.419477852
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.374217707
Short name T371
Test name
Test status
Simulation time 354993526 ps
CPU time 0.67 seconds
Started Jun 05 05:24:32 PM PDT 24
Finished Jun 05 05:24:33 PM PDT 24
Peak memory 183632 kb
Host smart-c3ac6407-aeaa-4b2c-a67b-45477314ea44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374217707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.374217707
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4107767003
Short name T347
Test name
Test status
Simulation time 1160198988 ps
CPU time 3.71 seconds
Started Jun 05 05:24:31 PM PDT 24
Finished Jun 05 05:24:36 PM PDT 24
Peak memory 192940 kb
Host smart-140e871c-4ebc-421d-b9d8-079bfd60ba3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107767003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.4107767003
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3838185923
Short name T386
Test name
Test status
Simulation time 376468374 ps
CPU time 1.37 seconds
Started Jun 05 05:24:21 PM PDT 24
Finished Jun 05 05:24:23 PM PDT 24
Peak memory 198440 kb
Host smart-8a52ba74-af2c-44cd-bb69-7378612399e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838185923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3838185923
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1784717343
Short name T328
Test name
Test status
Simulation time 8974686555 ps
CPU time 4.6 seconds
Started Jun 05 05:24:29 PM PDT 24
Finished Jun 05 05:24:35 PM PDT 24
Peak memory 198012 kb
Host smart-1666a9cb-fbbf-4e80-8180-15585f6f0be2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784717343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1784717343
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2784395652
Short name T306
Test name
Test status
Simulation time 410832443 ps
CPU time 1.01 seconds
Started Jun 05 05:24:29 PM PDT 24
Finished Jun 05 05:24:30 PM PDT 24
Peak memory 196100 kb
Host smart-37ad54df-3781-4689-abf1-469462a9f6ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784395652 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2784395652
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1105988083
Short name T377
Test name
Test status
Simulation time 423805201 ps
CPU time 1.28 seconds
Started Jun 05 05:24:26 PM PDT 24
Finished Jun 05 05:24:28 PM PDT 24
Peak memory 193112 kb
Host smart-efaf88cb-25d9-4916-bca0-896105bd0ac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105988083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1105988083
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2051802501
Short name T315
Test name
Test status
Simulation time 436583935 ps
CPU time 1.29 seconds
Started Jun 05 05:24:31 PM PDT 24
Finished Jun 05 05:24:33 PM PDT 24
Peak memory 183604 kb
Host smart-e70e7fcc-3fb2-4f32-80b8-aa3f4fe9f344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051802501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2051802501
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3969058353
Short name T391
Test name
Test status
Simulation time 1457732820 ps
CPU time 1.46 seconds
Started Jun 05 05:24:31 PM PDT 24
Finished Jun 05 05:24:33 PM PDT 24
Peak memory 183908 kb
Host smart-4a222015-138b-4530-9098-6411ca51112e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969058353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3969058353
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2391058442
Short name T408
Test name
Test status
Simulation time 773656935 ps
CPU time 1.57 seconds
Started Jun 05 05:24:30 PM PDT 24
Finished Jun 05 05:24:33 PM PDT 24
Peak memory 198408 kb
Host smart-a6beee57-525d-4dc6-bec8-f08ee362ff52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391058442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2391058442
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1367500171
Short name T301
Test name
Test status
Simulation time 4820398138 ps
CPU time 1.46 seconds
Started Jun 05 05:24:31 PM PDT 24
Finished Jun 05 05:24:33 PM PDT 24
Peak memory 196372 kb
Host smart-52b77ef4-c879-4220-8c2e-25fa988ea341
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367500171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1367500171
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.482882875
Short name T342
Test name
Test status
Simulation time 514085482 ps
CPU time 1.6 seconds
Started Jun 05 05:24:31 PM PDT 24
Finished Jun 05 05:24:33 PM PDT 24
Peak memory 196168 kb
Host smart-7f03126a-5c7b-4e00-a992-587cd5b8a679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482882875 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.482882875
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3305666961
Short name T363
Test name
Test status
Simulation time 533868578 ps
CPU time 0.8 seconds
Started Jun 05 05:24:31 PM PDT 24
Finished Jun 05 05:24:33 PM PDT 24
Peak memory 193092 kb
Host smart-92be8598-320a-4e7d-817e-928c355d55ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305666961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3305666961
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2052938289
Short name T380
Test name
Test status
Simulation time 438509553 ps
CPU time 0.71 seconds
Started Jun 05 05:24:32 PM PDT 24
Finished Jun 05 05:24:33 PM PDT 24
Peak memory 183644 kb
Host smart-3a34ab1e-78b3-4e8a-a777-98656ef03c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052938289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2052938289
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1877383780
Short name T83
Test name
Test status
Simulation time 2856464650 ps
CPU time 3.88 seconds
Started Jun 05 05:24:33 PM PDT 24
Finished Jun 05 05:24:37 PM PDT 24
Peak memory 194728 kb
Host smart-ea5cf1f8-9b6b-4564-b5a4-345eeb32d431
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877383780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1877383780
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3209579456
Short name T362
Test name
Test status
Simulation time 539364142 ps
CPU time 2.19 seconds
Started Jun 05 05:24:31 PM PDT 24
Finished Jun 05 05:24:34 PM PDT 24
Peak memory 198416 kb
Host smart-f87bce3d-0af0-4d65-80d0-0760912ed1b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209579456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3209579456
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3785984846
Short name T314
Test name
Test status
Simulation time 8356486116 ps
CPU time 4.92 seconds
Started Jun 05 05:24:30 PM PDT 24
Finished Jun 05 05:24:35 PM PDT 24
Peak memory 198168 kb
Host smart-0e678e30-d67b-4a92-99c0-bdd863bdbb14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785984846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3785984846
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3515910438
Short name T373
Test name
Test status
Simulation time 479065059 ps
CPU time 1.47 seconds
Started Jun 05 05:24:28 PM PDT 24
Finished Jun 05 05:24:30 PM PDT 24
Peak memory 195524 kb
Host smart-05cb7303-3c1a-4a2d-8ff9-8f36a7aae435
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515910438 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3515910438
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2215075554
Short name T418
Test name
Test status
Simulation time 327133707 ps
CPU time 1.03 seconds
Started Jun 05 05:24:30 PM PDT 24
Finished Jun 05 05:24:32 PM PDT 24
Peak memory 193024 kb
Host smart-e8d2aceb-454e-4254-a50e-f86f0c71c033
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215075554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2215075554
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2216121574
Short name T288
Test name
Test status
Simulation time 275833035 ps
CPU time 0.95 seconds
Started Jun 05 05:24:30 PM PDT 24
Finished Jun 05 05:24:32 PM PDT 24
Peak memory 183588 kb
Host smart-6c132fbd-1ae3-4cf3-bdb6-f5438eefeca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216121574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2216121574
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1196132979
Short name T327
Test name
Test status
Simulation time 1151208056 ps
CPU time 1.34 seconds
Started Jun 05 05:24:32 PM PDT 24
Finished Jun 05 05:24:34 PM PDT 24
Peak memory 183896 kb
Host smart-bc35b62b-bfb4-46eb-ae36-81535517035c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196132979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1196132979
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2454842090
Short name T350
Test name
Test status
Simulation time 544961669 ps
CPU time 2.85 seconds
Started Jun 05 05:24:30 PM PDT 24
Finished Jun 05 05:24:33 PM PDT 24
Peak memory 198472 kb
Host smart-67ac4303-96e8-43b4-a379-50f0a292dabe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454842090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2454842090
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.936990817
Short name T395
Test name
Test status
Simulation time 8373052968 ps
CPU time 12.82 seconds
Started Jun 05 05:24:29 PM PDT 24
Finished Jun 05 05:24:43 PM PDT 24
Peak memory 198076 kb
Host smart-c053f89e-a8a4-41fa-896e-9042bd03afe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936990817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.936990817
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2662131894
Short name T367
Test name
Test status
Simulation time 481315061 ps
CPU time 1.32 seconds
Started Jun 05 05:24:30 PM PDT 24
Finished Jun 05 05:24:32 PM PDT 24
Peak memory 195980 kb
Host smart-ee6cdde1-4e8c-4a49-a860-9d19e64917c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662131894 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2662131894
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2836818965
Short name T302
Test name
Test status
Simulation time 469748590 ps
CPU time 0.93 seconds
Started Jun 05 05:24:28 PM PDT 24
Finished Jun 05 05:24:30 PM PDT 24
Peak memory 193024 kb
Host smart-04d5da37-c144-45d9-817a-31921e5485c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836818965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2836818965
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2902675821
Short name T335
Test name
Test status
Simulation time 443437742 ps
CPU time 0.95 seconds
Started Jun 05 05:24:31 PM PDT 24
Finished Jun 05 05:24:33 PM PDT 24
Peak memory 183644 kb
Host smart-ea22d680-6a3e-4901-b0d6-56543c51d957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902675821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2902675821
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1206176239
Short name T85
Test name
Test status
Simulation time 1894538283 ps
CPU time 3.23 seconds
Started Jun 05 05:24:36 PM PDT 24
Finished Jun 05 05:24:39 PM PDT 24
Peak memory 194740 kb
Host smart-08c5fb2a-d8f0-4929-af66-8065cce4be27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206176239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1206176239
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2834986779
Short name T304
Test name
Test status
Simulation time 421009928 ps
CPU time 1.11 seconds
Started Jun 05 05:24:29 PM PDT 24
Finished Jun 05 05:24:31 PM PDT 24
Peak memory 198372 kb
Host smart-cf165e12-4cb3-4284-b741-a24ed03bff9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834986779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2834986779
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.507222976
Short name T372
Test name
Test status
Simulation time 572465970 ps
CPU time 0.96 seconds
Started Jun 05 05:24:30 PM PDT 24
Finished Jun 05 05:24:31 PM PDT 24
Peak memory 196828 kb
Host smart-e129fc32-3053-4272-ab1e-652c2238e960
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507222976 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.507222976
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.659520881
Short name T72
Test name
Test status
Simulation time 483250606 ps
CPU time 0.94 seconds
Started Jun 05 05:24:30 PM PDT 24
Finished Jun 05 05:24:32 PM PDT 24
Peak memory 183760 kb
Host smart-10496207-c721-429a-b6e1-70d39ade2a8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659520881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.659520881
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3866427733
Short name T336
Test name
Test status
Simulation time 376271604 ps
CPU time 0.83 seconds
Started Jun 05 05:24:30 PM PDT 24
Finished Jun 05 05:24:31 PM PDT 24
Peak memory 183644 kb
Host smart-217d04b2-916e-4a7f-817a-d9ead0828270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866427733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3866427733
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1359342742
Short name T360
Test name
Test status
Simulation time 2846407040 ps
CPU time 5.14 seconds
Started Jun 05 05:24:30 PM PDT 24
Finished Jun 05 05:24:36 PM PDT 24
Peak memory 191984 kb
Host smart-63280373-991f-4419-9e45-7e8f58f02651
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359342742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1359342742
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2214697787
Short name T344
Test name
Test status
Simulation time 563327105 ps
CPU time 2.14 seconds
Started Jun 05 05:24:32 PM PDT 24
Finished Jun 05 05:24:34 PM PDT 24
Peak memory 198456 kb
Host smart-7bcf7d01-0963-401c-859b-9321c3660b9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214697787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2214697787
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1437563995
Short name T284
Test name
Test status
Simulation time 4131873686 ps
CPU time 7.81 seconds
Started Jun 05 05:24:31 PM PDT 24
Finished Jun 05 05:24:39 PM PDT 24
Peak memory 197884 kb
Host smart-4ed0633f-4dba-40bd-a8ba-51f649ff9d85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437563995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1437563995
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1703463909
Short name T345
Test name
Test status
Simulation time 379943122 ps
CPU time 0.95 seconds
Started Jun 05 05:24:36 PM PDT 24
Finished Jun 05 05:24:38 PM PDT 24
Peak memory 197448 kb
Host smart-eaa2b16b-6413-4f2e-960d-7d670265f314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703463909 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1703463909
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3825022460
Short name T296
Test name
Test status
Simulation time 558623175 ps
CPU time 0.83 seconds
Started Jun 05 05:24:41 PM PDT 24
Finished Jun 05 05:24:42 PM PDT 24
Peak memory 192984 kb
Host smart-b04a7465-5d40-496a-af5c-38603e2d0753
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825022460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3825022460
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2195732823
Short name T375
Test name
Test status
Simulation time 449633570 ps
CPU time 0.62 seconds
Started Jun 05 05:24:39 PM PDT 24
Finished Jun 05 05:24:41 PM PDT 24
Peak memory 183580 kb
Host smart-cc4a5ad4-7be7-49de-ab69-9d9a2d95e79d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195732823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2195732823
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3466400216
Short name T398
Test name
Test status
Simulation time 2289960922 ps
CPU time 2.99 seconds
Started Jun 05 05:24:39 PM PDT 24
Finished Jun 05 05:24:43 PM PDT 24
Peak memory 194400 kb
Host smart-1072b672-d853-4155-a898-dd2e85c654e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466400216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3466400216
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2472034727
Short name T291
Test name
Test status
Simulation time 1192174216 ps
CPU time 2.42 seconds
Started Jun 05 05:24:29 PM PDT 24
Finished Jun 05 05:24:31 PM PDT 24
Peak memory 198452 kb
Host smart-193b7c14-8d21-4561-a3b3-df30d73112cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472034727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2472034727
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3838411703
Short name T387
Test name
Test status
Simulation time 7996183359 ps
CPU time 13.96 seconds
Started Jun 05 05:24:40 PM PDT 24
Finished Jun 05 05:24:55 PM PDT 24
Peak memory 198056 kb
Host smart-42eb4a0f-7d29-4a62-945c-caa0a6fc9753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838411703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3838411703
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2324206446
Short name T407
Test name
Test status
Simulation time 355794148 ps
CPU time 1.2 seconds
Started Jun 05 05:24:36 PM PDT 24
Finished Jun 05 05:24:38 PM PDT 24
Peak memory 196176 kb
Host smart-c7e8b22b-f5d7-4027-a6cb-10c373d8595d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324206446 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2324206446
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1647065056
Short name T312
Test name
Test status
Simulation time 275340553 ps
CPU time 0.78 seconds
Started Jun 05 05:24:41 PM PDT 24
Finished Jun 05 05:24:43 PM PDT 24
Peak memory 192996 kb
Host smart-cd1246cb-14cf-4b4b-bb2b-409d73a17a62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647065056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1647065056
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1997009822
Short name T410
Test name
Test status
Simulation time 371378467 ps
CPU time 0.6 seconds
Started Jun 05 05:24:38 PM PDT 24
Finished Jun 05 05:24:39 PM PDT 24
Peak memory 183640 kb
Host smart-37d0e456-0c9b-4c10-b0bf-9f15baf22959
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997009822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1997009822
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2818361227
Short name T401
Test name
Test status
Simulation time 2720538012 ps
CPU time 1.57 seconds
Started Jun 05 05:24:40 PM PDT 24
Finished Jun 05 05:24:42 PM PDT 24
Peak memory 193924 kb
Host smart-64745192-bc40-41e2-b547-b12a3f60de3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818361227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2818361227
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1817023097
Short name T392
Test name
Test status
Simulation time 491189701 ps
CPU time 2.41 seconds
Started Jun 05 05:24:35 PM PDT 24
Finished Jun 05 05:24:38 PM PDT 24
Peak memory 198440 kb
Host smart-dcffc8e3-e99b-4369-a07b-f19150de236d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817023097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1817023097
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3495514912
Short name T202
Test name
Test status
Simulation time 4169026542 ps
CPU time 1.64 seconds
Started Jun 05 05:24:37 PM PDT 24
Finished Jun 05 05:24:39 PM PDT 24
Peak memory 197692 kb
Host smart-da467dd6-3ea1-486b-8725-7cfbb700dcdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495514912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3495514912
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1017131417
Short name T74
Test name
Test status
Simulation time 501916838 ps
CPU time 1.49 seconds
Started Jun 05 05:23:56 PM PDT 24
Finished Jun 05 05:23:58 PM PDT 24
Peak memory 183688 kb
Host smart-46f261d1-fe8a-4041-b14d-804fa983d359
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017131417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1017131417
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1328329423
Short name T70
Test name
Test status
Simulation time 10591775104 ps
CPU time 17.95 seconds
Started Jun 05 05:23:57 PM PDT 24
Finished Jun 05 05:24:15 PM PDT 24
Peak memory 192108 kb
Host smart-5b502600-c552-4977-aee0-ceab3c9d35fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328329423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1328329423
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2193295675
Short name T63
Test name
Test status
Simulation time 710870331 ps
CPU time 1.57 seconds
Started Jun 05 05:24:02 PM PDT 24
Finished Jun 05 05:24:04 PM PDT 24
Peak memory 183708 kb
Host smart-5d81c3c8-f8e5-451b-aab0-0431eac5483c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193295675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2193295675
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1813002347
Short name T412
Test name
Test status
Simulation time 451136475 ps
CPU time 0.94 seconds
Started Jun 05 05:23:59 PM PDT 24
Finished Jun 05 05:24:01 PM PDT 24
Peak memory 196768 kb
Host smart-111b7949-fa5e-434b-b24e-2b9ddd368821
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813002347 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1813002347
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3754090630
Short name T319
Test name
Test status
Simulation time 559198133 ps
CPU time 0.84 seconds
Started Jun 05 05:24:06 PM PDT 24
Finished Jun 05 05:24:08 PM PDT 24
Peak memory 183788 kb
Host smart-5135e55b-26c9-4f41-a1a5-748bb7abb3ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754090630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3754090630
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1075073697
Short name T413
Test name
Test status
Simulation time 322216622 ps
CPU time 0.65 seconds
Started Jun 05 05:23:58 PM PDT 24
Finished Jun 05 05:23:59 PM PDT 24
Peak memory 183648 kb
Host smart-4cbaff13-a637-48bc-be11-e68f6ce1a7d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075073697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1075073697
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2066137312
Short name T326
Test name
Test status
Simulation time 300320534 ps
CPU time 0.62 seconds
Started Jun 05 05:23:58 PM PDT 24
Finished Jun 05 05:23:59 PM PDT 24
Peak memory 183568 kb
Host smart-97afd85a-66e5-47e1-8717-09370d35b92b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066137312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2066137312
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2980361590
Short name T358
Test name
Test status
Simulation time 461141940 ps
CPU time 1.23 seconds
Started Jun 05 05:23:58 PM PDT 24
Finished Jun 05 05:24:00 PM PDT 24
Peak memory 183644 kb
Host smart-bcbc4275-5201-4988-a0df-c4f5f8a487b1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980361590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2980361590
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4116136945
Short name T78
Test name
Test status
Simulation time 1353725068 ps
CPU time 2.02 seconds
Started Jun 05 05:23:58 PM PDT 24
Finished Jun 05 05:24:00 PM PDT 24
Peak memory 193156 kb
Host smart-d1c3e422-388d-4949-83a6-6f80e2eb7eae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116136945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.4116136945
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3241521767
Short name T334
Test name
Test status
Simulation time 1152486820 ps
CPU time 1.15 seconds
Started Jun 05 05:23:56 PM PDT 24
Finished Jun 05 05:23:58 PM PDT 24
Peak memory 198452 kb
Host smart-368d3bc9-2aaa-4147-a801-8657dce684ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241521767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3241521767
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3179573444
Short name T354
Test name
Test status
Simulation time 4498244536 ps
CPU time 2.47 seconds
Started Jun 05 05:23:58 PM PDT 24
Finished Jun 05 05:24:01 PM PDT 24
Peak memory 197460 kb
Host smart-a20ec258-fa95-4362-90a5-751a12df8a0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179573444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3179573444
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2534612976
Short name T417
Test name
Test status
Simulation time 303301377 ps
CPU time 0.93 seconds
Started Jun 05 05:24:37 PM PDT 24
Finished Jun 05 05:24:39 PM PDT 24
Peak memory 183624 kb
Host smart-9140768a-df5a-4b02-ba89-905d2cdd000f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534612976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2534612976
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.450739389
Short name T340
Test name
Test status
Simulation time 404391718 ps
CPU time 1.19 seconds
Started Jun 05 05:24:37 PM PDT 24
Finished Jun 05 05:24:40 PM PDT 24
Peak memory 183632 kb
Host smart-e18710f7-cc3e-4ee5-9dee-aa021724a14f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450739389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.450739389
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.440203371
Short name T389
Test name
Test status
Simulation time 507313429 ps
CPU time 1.19 seconds
Started Jun 05 05:24:39 PM PDT 24
Finished Jun 05 05:24:41 PM PDT 24
Peak memory 183644 kb
Host smart-d289ee69-69ad-4e54-bf1b-bea2010ec86f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440203371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.440203371
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.4060957842
Short name T332
Test name
Test status
Simulation time 474645701 ps
CPU time 0.96 seconds
Started Jun 05 05:24:36 PM PDT 24
Finished Jun 05 05:24:38 PM PDT 24
Peak memory 183648 kb
Host smart-6d02421f-9477-4cd1-96e3-806bcef58db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060957842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.4060957842
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1314999300
Short name T290
Test name
Test status
Simulation time 388465142 ps
CPU time 0.85 seconds
Started Jun 05 05:24:39 PM PDT 24
Finished Jun 05 05:24:40 PM PDT 24
Peak memory 183640 kb
Host smart-414cf8d8-02a3-4db3-ae9f-1f8c9736de35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314999300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1314999300
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2651821253
Short name T292
Test name
Test status
Simulation time 475971677 ps
CPU time 0.64 seconds
Started Jun 05 05:24:40 PM PDT 24
Finished Jun 05 05:24:41 PM PDT 24
Peak memory 183588 kb
Host smart-901976dc-047c-4d9e-99bc-84ab0eb0cb0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651821253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2651821253
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1190740364
Short name T343
Test name
Test status
Simulation time 404677743 ps
CPU time 0.86 seconds
Started Jun 05 05:24:40 PM PDT 24
Finished Jun 05 05:24:42 PM PDT 24
Peak memory 183644 kb
Host smart-5b0bde62-83fd-4bb6-a0c7-37ca673a1356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190740364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1190740364
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1129557749
Short name T411
Test name
Test status
Simulation time 485827242 ps
CPU time 1.27 seconds
Started Jun 05 05:24:39 PM PDT 24
Finished Jun 05 05:24:41 PM PDT 24
Peak memory 183644 kb
Host smart-d8eed32b-e712-47b0-8bfe-8653f2843665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129557749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1129557749
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2133342884
Short name T309
Test name
Test status
Simulation time 515815090 ps
CPU time 1.05 seconds
Started Jun 05 05:24:39 PM PDT 24
Finished Jun 05 05:24:41 PM PDT 24
Peak memory 183644 kb
Host smart-233f647c-40ce-4a83-a749-1980621ba3a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133342884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2133342884
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2644498439
Short name T349
Test name
Test status
Simulation time 438891054 ps
CPU time 0.71 seconds
Started Jun 05 05:24:40 PM PDT 24
Finished Jun 05 05:24:41 PM PDT 24
Peak memory 183628 kb
Host smart-3e4bd0bf-839e-4e4e-9401-06f929c93ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644498439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2644498439
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2166669269
Short name T76
Test name
Test status
Simulation time 553469754 ps
CPU time 1.28 seconds
Started Jun 05 05:24:02 PM PDT 24
Finished Jun 05 05:24:04 PM PDT 24
Peak memory 183700 kb
Host smart-2edcdc0b-2894-485c-b202-d6be2f4b994a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166669269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2166669269
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.358891470
Short name T353
Test name
Test status
Simulation time 13792286343 ps
CPU time 23.03 seconds
Started Jun 05 05:23:57 PM PDT 24
Finished Jun 05 05:24:21 PM PDT 24
Peak memory 192128 kb
Host smart-6ed6f0f4-e43e-4946-973a-4c6cbbef98c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358891470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.358891470
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3947133074
Short name T69
Test name
Test status
Simulation time 970965055 ps
CPU time 0.92 seconds
Started Jun 05 05:24:01 PM PDT 24
Finished Jun 05 05:24:02 PM PDT 24
Peak memory 183756 kb
Host smart-5ac4f153-69a0-4074-8470-b53f1c5cf36c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947133074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3947133074
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.337287138
Short name T323
Test name
Test status
Simulation time 560396693 ps
CPU time 1.13 seconds
Started Jun 05 05:24:01 PM PDT 24
Finished Jun 05 05:24:03 PM PDT 24
Peak memory 198352 kb
Host smart-7763219e-1817-4ef7-8bed-f3cae42a012e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337287138 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.337287138
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1560712223
Short name T368
Test name
Test status
Simulation time 382439731 ps
CPU time 1.28 seconds
Started Jun 05 05:24:01 PM PDT 24
Finished Jun 05 05:24:02 PM PDT 24
Peak memory 193248 kb
Host smart-30080782-7a11-4a4f-9e15-a93b600c9ea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560712223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1560712223
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3630501422
Short name T357
Test name
Test status
Simulation time 314888689 ps
CPU time 1.02 seconds
Started Jun 05 05:23:57 PM PDT 24
Finished Jun 05 05:23:59 PM PDT 24
Peak memory 183648 kb
Host smart-9d1e9eaa-cfd8-42ae-9ff2-18a1b36e0aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630501422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3630501422
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3563251052
Short name T382
Test name
Test status
Simulation time 426154428 ps
CPU time 0.64 seconds
Started Jun 05 05:24:05 PM PDT 24
Finished Jun 05 05:24:06 PM PDT 24
Peak memory 183576 kb
Host smart-091b613a-93db-4604-a990-21e0db17c874
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563251052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3563251052
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2995229747
Short name T281
Test name
Test status
Simulation time 412011892 ps
CPU time 0.58 seconds
Started Jun 05 05:23:58 PM PDT 24
Finished Jun 05 05:24:00 PM PDT 24
Peak memory 183620 kb
Host smart-e701028d-6c2b-4592-a3b9-2e5c3fc0c0af
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995229747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2995229747
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1055850965
Short name T81
Test name
Test status
Simulation time 3284104251 ps
CPU time 1.26 seconds
Started Jun 05 05:24:05 PM PDT 24
Finished Jun 05 05:24:07 PM PDT 24
Peak memory 192036 kb
Host smart-230f2588-1125-45a3-84b7-8d798e38ec31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055850965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1055850965
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2288259667
Short name T383
Test name
Test status
Simulation time 509385878 ps
CPU time 2.82 seconds
Started Jun 05 05:24:06 PM PDT 24
Finished Jun 05 05:24:09 PM PDT 24
Peak memory 198456 kb
Host smart-cb4d99ff-d5bc-47c4-89ce-888c921602f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288259667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2288259667
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.261114836
Short name T37
Test name
Test status
Simulation time 4504156231 ps
CPU time 7.27 seconds
Started Jun 05 05:24:01 PM PDT 24
Finished Jun 05 05:24:08 PM PDT 24
Peak memory 197752 kb
Host smart-c65f12e3-efb0-430b-83fc-7017036959c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261114836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.261114836
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2152853257
Short name T282
Test name
Test status
Simulation time 405283486 ps
CPU time 1.08 seconds
Started Jun 05 05:24:39 PM PDT 24
Finished Jun 05 05:24:41 PM PDT 24
Peak memory 183644 kb
Host smart-fcb39d79-29cc-4d62-b3dc-072a53d39fb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152853257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2152853257
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1755304349
Short name T355
Test name
Test status
Simulation time 373022533 ps
CPU time 0.8 seconds
Started Jun 05 05:24:37 PM PDT 24
Finished Jun 05 05:24:39 PM PDT 24
Peak memory 183624 kb
Host smart-653417b7-8ab1-4b5c-a498-14cc40fb0c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755304349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1755304349
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3384839487
Short name T308
Test name
Test status
Simulation time 377819463 ps
CPU time 0.76 seconds
Started Jun 05 05:24:37 PM PDT 24
Finished Jun 05 05:24:39 PM PDT 24
Peak memory 183576 kb
Host smart-46d33e78-6cd0-4480-adad-bda2da5ebfd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384839487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3384839487
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2996041891
Short name T333
Test name
Test status
Simulation time 283431186 ps
CPU time 0.64 seconds
Started Jun 05 05:24:35 PM PDT 24
Finished Jun 05 05:24:36 PM PDT 24
Peak memory 183628 kb
Host smart-415f151f-f7a1-45e7-97e2-169bb704ef57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996041891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2996041891
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.477677555
Short name T379
Test name
Test status
Simulation time 336615896 ps
CPU time 0.65 seconds
Started Jun 05 05:24:37 PM PDT 24
Finished Jun 05 05:24:38 PM PDT 24
Peak memory 183600 kb
Host smart-04728d35-90cb-41a0-9cea-71735ae90905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477677555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.477677555
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.329324948
Short name T297
Test name
Test status
Simulation time 410863164 ps
CPU time 0.71 seconds
Started Jun 05 05:24:38 PM PDT 24
Finished Jun 05 05:24:40 PM PDT 24
Peak memory 183648 kb
Host smart-acc2d26e-e794-4b72-afc0-0d00c3182cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329324948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.329324948
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1011974656
Short name T385
Test name
Test status
Simulation time 305121615 ps
CPU time 0.99 seconds
Started Jun 05 05:24:39 PM PDT 24
Finished Jun 05 05:24:41 PM PDT 24
Peak memory 183648 kb
Host smart-dfe28589-83ee-4abb-9c52-2080feba3c64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011974656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1011974656
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2970102558
Short name T384
Test name
Test status
Simulation time 501744398 ps
CPU time 0.71 seconds
Started Jun 05 05:24:43 PM PDT 24
Finished Jun 05 05:24:44 PM PDT 24
Peak memory 183648 kb
Host smart-98b7a303-a872-4481-9592-1ce3f6b80020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970102558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2970102558
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.191001671
Short name T305
Test name
Test status
Simulation time 400519081 ps
CPU time 1.24 seconds
Started Jun 05 05:24:39 PM PDT 24
Finished Jun 05 05:24:41 PM PDT 24
Peak memory 183572 kb
Host smart-daf4168b-da23-4575-b486-e1ef59043674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191001671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.191001671
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4073934858
Short name T285
Test name
Test status
Simulation time 521164569 ps
CPU time 0.89 seconds
Started Jun 05 05:24:37 PM PDT 24
Finished Jun 05 05:24:39 PM PDT 24
Peak memory 183596 kb
Host smart-89c5be2f-d625-44ea-9e1c-12e95cb09285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073934858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4073934858
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.728782884
Short name T65
Test name
Test status
Simulation time 535751278 ps
CPU time 0.87 seconds
Started Jun 05 05:24:04 PM PDT 24
Finished Jun 05 05:24:06 PM PDT 24
Peak memory 183788 kb
Host smart-7300c024-0c4c-4c44-87e3-923bb677aa8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728782884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.728782884
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1931907653
Short name T289
Test name
Test status
Simulation time 6975184800 ps
CPU time 3.73 seconds
Started Jun 05 05:24:05 PM PDT 24
Finished Jun 05 05:24:10 PM PDT 24
Peak memory 192100 kb
Host smart-7783b44c-eb37-4ec2-aae9-3e6f61b1f44e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931907653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1931907653
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.533755428
Short name T394
Test name
Test status
Simulation time 823578123 ps
CPU time 0.76 seconds
Started Jun 05 05:24:06 PM PDT 24
Finished Jun 05 05:24:08 PM PDT 24
Peak memory 183784 kb
Host smart-5794ce3b-9dd0-4f5c-96f6-038a5e2a7bfc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533755428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.533755428
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1855802433
Short name T294
Test name
Test status
Simulation time 404244331 ps
CPU time 1.22 seconds
Started Jun 05 05:24:02 PM PDT 24
Finished Jun 05 05:24:04 PM PDT 24
Peak memory 195712 kb
Host smart-dfb2463a-4841-40fa-a1dd-59ec6593f1f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855802433 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1855802433
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2473982431
Short name T62
Test name
Test status
Simulation time 453845400 ps
CPU time 1.4 seconds
Started Jun 05 05:24:02 PM PDT 24
Finished Jun 05 05:24:04 PM PDT 24
Peak memory 193208 kb
Host smart-139bef24-45dc-45db-8be7-8809dee41bbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473982431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2473982431
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4290369129
Short name T293
Test name
Test status
Simulation time 299712015 ps
CPU time 0.65 seconds
Started Jun 05 05:24:05 PM PDT 24
Finished Jun 05 05:24:06 PM PDT 24
Peak memory 183648 kb
Host smart-4e394773-8d72-45f4-968c-f7d983f5e36a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290369129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.4290369129
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1258511308
Short name T366
Test name
Test status
Simulation time 339460007 ps
CPU time 1.08 seconds
Started Jun 05 05:23:57 PM PDT 24
Finished Jun 05 05:23:59 PM PDT 24
Peak memory 183572 kb
Host smart-6bb36a8e-1bc3-4782-9f8f-0d59cda1a358
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258511308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1258511308
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2783273519
Short name T346
Test name
Test status
Simulation time 507317967 ps
CPU time 1.32 seconds
Started Jun 05 05:24:02 PM PDT 24
Finished Jun 05 05:24:04 PM PDT 24
Peak memory 183628 kb
Host smart-e70063f6-5bcd-43a1-8dfe-5fce4de94fa7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783273519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2783273519
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1488421657
Short name T80
Test name
Test status
Simulation time 1377907831 ps
CPU time 1.53 seconds
Started Jun 05 05:24:04 PM PDT 24
Finished Jun 05 05:24:06 PM PDT 24
Peak memory 193224 kb
Host smart-34c42cef-3439-4a67-8dfc-dcfd2ce0a0e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488421657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1488421657
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3706873699
Short name T316
Test name
Test status
Simulation time 686080980 ps
CPU time 2.32 seconds
Started Jun 05 05:24:05 PM PDT 24
Finished Jun 05 05:24:08 PM PDT 24
Peak memory 198452 kb
Host smart-369eaaae-fc29-48b3-a00b-d6ca348adcb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706873699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3706873699
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.992930117
Short name T339
Test name
Test status
Simulation time 4483730721 ps
CPU time 4.63 seconds
Started Jun 05 05:23:58 PM PDT 24
Finished Jun 05 05:24:03 PM PDT 24
Peak memory 197480 kb
Host smart-353ddcbc-781f-48a5-84b3-5574c27b1dc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992930117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.992930117
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.903961890
Short name T303
Test name
Test status
Simulation time 452186982 ps
CPU time 0.67 seconds
Started Jun 05 05:24:43 PM PDT 24
Finished Jun 05 05:24:44 PM PDT 24
Peak memory 183648 kb
Host smart-aa0eba8a-8453-45bf-a0e9-664411816a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903961890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.903961890
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3564089024
Short name T287
Test name
Test status
Simulation time 357091794 ps
CPU time 0.77 seconds
Started Jun 05 05:24:37 PM PDT 24
Finished Jun 05 05:24:38 PM PDT 24
Peak memory 183600 kb
Host smart-cb6bd2e1-6533-465a-8213-c9af4fe1ff54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564089024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3564089024
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1339460236
Short name T352
Test name
Test status
Simulation time 445613147 ps
CPU time 1.17 seconds
Started Jun 05 05:24:46 PM PDT 24
Finished Jun 05 05:24:48 PM PDT 24
Peak memory 183544 kb
Host smart-0f875499-49f5-4c91-b163-8ad73abe07be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339460236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1339460236
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3677529040
Short name T320
Test name
Test status
Simulation time 495272723 ps
CPU time 0.66 seconds
Started Jun 05 05:24:46 PM PDT 24
Finished Jun 05 05:24:48 PM PDT 24
Peak memory 183648 kb
Host smart-5068c448-7e71-406f-b578-ff26703661c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677529040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3677529040
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.744635909
Short name T348
Test name
Test status
Simulation time 506388646 ps
CPU time 0.79 seconds
Started Jun 05 05:24:52 PM PDT 24
Finished Jun 05 05:24:53 PM PDT 24
Peak memory 183624 kb
Host smart-8a10f19c-8d34-490b-acf7-f1170a3ddb3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744635909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.744635909
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1361505850
Short name T397
Test name
Test status
Simulation time 418954703 ps
CPU time 1.12 seconds
Started Jun 05 05:24:46 PM PDT 24
Finished Jun 05 05:24:48 PM PDT 24
Peak memory 183572 kb
Host smart-7998060c-3fdd-425d-94f4-2ee0d684dfcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361505850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1361505850
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.406512020
Short name T300
Test name
Test status
Simulation time 513325270 ps
CPU time 0.77 seconds
Started Jun 05 05:24:49 PM PDT 24
Finished Jun 05 05:24:50 PM PDT 24
Peak memory 183600 kb
Host smart-23f12497-0b5e-4c71-a179-410177f7cbf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406512020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.406512020
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3330810010
Short name T416
Test name
Test status
Simulation time 289260343 ps
CPU time 0.65 seconds
Started Jun 05 05:24:53 PM PDT 24
Finished Jun 05 05:24:54 PM PDT 24
Peak memory 183644 kb
Host smart-14e1b7da-093f-437a-8155-670ea3edc472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330810010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3330810010
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.4039386142
Short name T388
Test name
Test status
Simulation time 307695043 ps
CPU time 1 seconds
Started Jun 05 05:24:50 PM PDT 24
Finished Jun 05 05:24:52 PM PDT 24
Peak memory 183620 kb
Host smart-094628d2-1fa8-44ca-bad1-7128d90f7c5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039386142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.4039386142
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2812382636
Short name T310
Test name
Test status
Simulation time 368519819 ps
CPU time 0.67 seconds
Started Jun 05 05:24:53 PM PDT 24
Finished Jun 05 05:24:54 PM PDT 24
Peak memory 183640 kb
Host smart-a9cd18c8-b663-4e3c-8285-011624e20f9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812382636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2812382636
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1761378780
Short name T356
Test name
Test status
Simulation time 565199119 ps
CPU time 1.09 seconds
Started Jun 05 05:24:03 PM PDT 24
Finished Jun 05 05:24:04 PM PDT 24
Peak memory 195844 kb
Host smart-ec545056-c797-4ff4-b718-e51bb9ab4018
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761378780 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1761378780
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3401305162
Short name T66
Test name
Test status
Simulation time 468835008 ps
CPU time 0.7 seconds
Started Jun 05 05:24:02 PM PDT 24
Finished Jun 05 05:24:04 PM PDT 24
Peak memory 183780 kb
Host smart-1d20c855-900b-416f-8683-57b404eda1cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401305162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3401305162
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1767930534
Short name T325
Test name
Test status
Simulation time 516239813 ps
CPU time 1.35 seconds
Started Jun 05 05:24:05 PM PDT 24
Finished Jun 05 05:24:07 PM PDT 24
Peak memory 183644 kb
Host smart-40f8dd5d-f6ad-4b27-84eb-301897772a6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767930534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1767930534
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1652842649
Short name T313
Test name
Test status
Simulation time 1101485993 ps
CPU time 2.19 seconds
Started Jun 05 05:24:03 PM PDT 24
Finished Jun 05 05:24:06 PM PDT 24
Peak memory 183712 kb
Host smart-850a06e0-add5-4548-b718-e789f27166a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652842649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1652842649
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1860587606
Short name T337
Test name
Test status
Simulation time 469786849 ps
CPU time 1.89 seconds
Started Jun 05 05:24:04 PM PDT 24
Finished Jun 05 05:24:06 PM PDT 24
Peak memory 198352 kb
Host smart-ac1bbaad-5c96-41a7-a680-73abf6d07f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860587606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1860587606
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2496981560
Short name T35
Test name
Test status
Simulation time 4744997588 ps
CPU time 2.79 seconds
Started Jun 05 05:24:05 PM PDT 24
Finished Jun 05 05:24:08 PM PDT 24
Peak memory 197528 kb
Host smart-cf8ecb94-734e-43ad-8962-ea6c0fe10909
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496981560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2496981560
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2187905343
Short name T329
Test name
Test status
Simulation time 436958194 ps
CPU time 1.32 seconds
Started Jun 05 05:24:12 PM PDT 24
Finished Jun 05 05:24:14 PM PDT 24
Peak memory 195980 kb
Host smart-60930154-7bd9-4858-9708-f5ba22fc7aa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187905343 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2187905343
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2888894698
Short name T68
Test name
Test status
Simulation time 376942945 ps
CPU time 0.66 seconds
Started Jun 05 05:24:10 PM PDT 24
Finished Jun 05 05:24:11 PM PDT 24
Peak memory 192992 kb
Host smart-2572c935-aad8-4551-b2fa-f403e66c2493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888894698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2888894698
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3067351437
Short name T402
Test name
Test status
Simulation time 401345752 ps
CPU time 0.68 seconds
Started Jun 05 05:24:04 PM PDT 24
Finished Jun 05 05:24:05 PM PDT 24
Peak memory 183604 kb
Host smart-4127c341-8cab-4ea3-bbd0-dc751c5f299e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067351437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3067351437
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2045037455
Short name T399
Test name
Test status
Simulation time 1185198650 ps
CPU time 1.14 seconds
Started Jun 05 05:24:11 PM PDT 24
Finished Jun 05 05:24:12 PM PDT 24
Peak memory 193156 kb
Host smart-f5ebaec5-bc99-4d5a-99b9-b097fd8a2343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045037455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2045037455
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1545046447
Short name T396
Test name
Test status
Simulation time 436191277 ps
CPU time 2.42 seconds
Started Jun 05 05:24:04 PM PDT 24
Finished Jun 05 05:24:07 PM PDT 24
Peak memory 198616 kb
Host smart-d745529c-abd6-47ec-b017-541e94ae9ed0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545046447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1545046447
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1020879233
Short name T198
Test name
Test status
Simulation time 8103324185 ps
CPU time 10.36 seconds
Started Jun 05 05:24:05 PM PDT 24
Finished Jun 05 05:24:16 PM PDT 24
Peak memory 197836 kb
Host smart-349dc501-023e-4fdb-afc6-417ba1a19191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020879233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1020879233
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4194046322
Short name T341
Test name
Test status
Simulation time 439394688 ps
CPU time 0.82 seconds
Started Jun 05 05:24:21 PM PDT 24
Finished Jun 05 05:24:23 PM PDT 24
Peak memory 195664 kb
Host smart-ae0e94cc-4c09-47d8-9073-c89f399cceb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194046322 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.4194046322
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2376221026
Short name T406
Test name
Test status
Simulation time 401451948 ps
CPU time 1.25 seconds
Started Jun 05 05:24:11 PM PDT 24
Finished Jun 05 05:24:12 PM PDT 24
Peak memory 192988 kb
Host smart-9d02fcc7-169a-4439-aaf8-04c84a0fd445
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376221026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2376221026
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2889533485
Short name T311
Test name
Test status
Simulation time 401730809 ps
CPU time 0.85 seconds
Started Jun 05 05:24:11 PM PDT 24
Finished Jun 05 05:24:13 PM PDT 24
Peak memory 183580 kb
Host smart-7ec3d6f6-6af0-4021-861b-6d457f5346e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889533485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2889533485
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3253897259
Short name T376
Test name
Test status
Simulation time 2458950575 ps
CPU time 1.42 seconds
Started Jun 05 05:24:11 PM PDT 24
Finished Jun 05 05:24:13 PM PDT 24
Peak memory 191972 kb
Host smart-f6a1d173-8f70-4e2c-9ffe-3fb985027f14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253897259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3253897259
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1409733333
Short name T403
Test name
Test status
Simulation time 442953692 ps
CPU time 1.29 seconds
Started Jun 05 05:24:11 PM PDT 24
Finished Jun 05 05:24:12 PM PDT 24
Peak memory 198348 kb
Host smart-aa533863-d092-47f0-bce0-f5219639ceed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409733333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1409733333
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3940755854
Short name T201
Test name
Test status
Simulation time 8508737233 ps
CPU time 8.04 seconds
Started Jun 05 05:24:13 PM PDT 24
Finished Jun 05 05:24:21 PM PDT 24
Peak memory 198128 kb
Host smart-cf359312-08ee-4730-a2b9-7886df56a991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940755854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3940755854
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2339992510
Short name T369
Test name
Test status
Simulation time 550876254 ps
CPU time 1.48 seconds
Started Jun 05 05:24:21 PM PDT 24
Finished Jun 05 05:24:23 PM PDT 24
Peak memory 196432 kb
Host smart-8f2b7f6f-d7e2-4a51-b943-6c27241ca505
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339992510 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2339992510
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1631694860
Short name T318
Test name
Test status
Simulation time 376338200 ps
CPU time 0.64 seconds
Started Jun 05 05:24:19 PM PDT 24
Finished Jun 05 05:24:21 PM PDT 24
Peak memory 183636 kb
Host smart-dfe35b46-2272-4ec1-954e-8a55ae0ebbcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631694860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1631694860
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2590248050
Short name T330
Test name
Test status
Simulation time 2458610297 ps
CPU time 7.2 seconds
Started Jun 05 05:24:22 PM PDT 24
Finished Jun 05 05:24:30 PM PDT 24
Peak memory 183976 kb
Host smart-e000060d-f848-4b40-b913-4e0ab4b84566
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590248050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2590248050
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.426461264
Short name T381
Test name
Test status
Simulation time 371419360 ps
CPU time 2.68 seconds
Started Jun 05 05:24:20 PM PDT 24
Finished Jun 05 05:24:24 PM PDT 24
Peak memory 198444 kb
Host smart-6d6c7790-b560-4eaf-811c-9fcb944b259c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426461264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.426461264
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3704598836
Short name T404
Test name
Test status
Simulation time 4098533228 ps
CPU time 1.74 seconds
Started Jun 05 05:24:21 PM PDT 24
Finished Jun 05 05:24:24 PM PDT 24
Peak memory 197764 kb
Host smart-dabaa9ac-bcc0-4d5c-ba3d-b76d16bc8618
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704598836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3704598836
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4070580199
Short name T400
Test name
Test status
Simulation time 431769223 ps
CPU time 1.36 seconds
Started Jun 05 05:24:22 PM PDT 24
Finished Jun 05 05:24:24 PM PDT 24
Peak memory 196276 kb
Host smart-da18146d-43ad-408c-baa7-12ab494c0881
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070580199 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.4070580199
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3651908277
Short name T321
Test name
Test status
Simulation time 419351826 ps
CPU time 0.92 seconds
Started Jun 05 05:24:20 PM PDT 24
Finished Jun 05 05:24:22 PM PDT 24
Peak memory 193004 kb
Host smart-ae715a17-80bb-40cb-a7d9-4adf6f1a4b42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651908277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3651908277
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3090260013
Short name T324
Test name
Test status
Simulation time 461204385 ps
CPU time 0.61 seconds
Started Jun 05 05:24:19 PM PDT 24
Finished Jun 05 05:24:21 PM PDT 24
Peak memory 183644 kb
Host smart-ae6c005f-5293-402f-8230-becae7e415ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090260013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3090260013
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.106394310
Short name T365
Test name
Test status
Simulation time 1213607201 ps
CPU time 1.55 seconds
Started Jun 05 05:24:21 PM PDT 24
Finished Jun 05 05:24:23 PM PDT 24
Peak memory 193168 kb
Host smart-9b930209-0973-4e2e-9e9c-b4cb8585c3d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106394310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.106394310
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2619192316
Short name T405
Test name
Test status
Simulation time 527890404 ps
CPU time 1.56 seconds
Started Jun 05 05:24:19 PM PDT 24
Finished Jun 05 05:24:21 PM PDT 24
Peak memory 198452 kb
Host smart-49556f73-de2b-4d7b-bdde-bf63ffef8f24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619192316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2619192316
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1037894371
Short name T390
Test name
Test status
Simulation time 4053052188 ps
CPU time 6.82 seconds
Started Jun 05 05:24:22 PM PDT 24
Finished Jun 05 05:24:30 PM PDT 24
Peak memory 197896 kb
Host smart-36418bf9-11cc-4784-8e1a-d941465b78f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037894371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1037894371
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3273893041
Short name T231
Test name
Test status
Simulation time 15341463043 ps
CPU time 6.47 seconds
Started Jun 05 05:22:56 PM PDT 24
Finished Jun 05 05:23:04 PM PDT 24
Peak memory 191916 kb
Host smart-19b0857c-061a-4e18-a2b2-922b98ef42dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273893041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3273893041
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1508414766
Short name T215
Test name
Test status
Simulation time 464814924 ps
CPU time 0.74 seconds
Started Jun 05 05:22:54 PM PDT 24
Finished Jun 05 05:22:56 PM PDT 24
Peak memory 191792 kb
Host smart-bf75230c-214e-4cc0-8448-4245bc36c309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508414766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1508414766
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.783677960
Short name T205
Test name
Test status
Simulation time 26590785340 ps
CPU time 21.08 seconds
Started Jun 05 05:22:55 PM PDT 24
Finished Jun 05 05:23:17 PM PDT 24
Peak memory 191912 kb
Host smart-b45e653d-ee1b-4149-9985-be553a3d6422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783677960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.783677960
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3850849610
Short name T15
Test name
Test status
Simulation time 8436049544 ps
CPU time 2.94 seconds
Started Jun 05 05:22:44 PM PDT 24
Finished Jun 05 05:22:48 PM PDT 24
Peak memory 215596 kb
Host smart-3ed2c99d-8a9c-4936-96cd-b3a754196c56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850849610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3850849610
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2311608942
Short name T209
Test name
Test status
Simulation time 585295299 ps
CPU time 1.61 seconds
Started Jun 05 05:22:46 PM PDT 24
Finished Jun 05 05:22:49 PM PDT 24
Peak memory 191804 kb
Host smart-ed29e748-c2ec-4637-b5ee-9b96a98b3eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311608942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2311608942
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.452241898
Short name T251
Test name
Test status
Simulation time 33287149688 ps
CPU time 39.91 seconds
Started Jun 05 05:22:59 PM PDT 24
Finished Jun 05 05:23:40 PM PDT 24
Peak memory 191908 kb
Host smart-4d7d599f-48bc-4b27-a252-a7f5218034e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452241898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.452241898
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2508823461
Short name T253
Test name
Test status
Simulation time 598171568 ps
CPU time 1.02 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:02 PM PDT 24
Peak memory 191792 kb
Host smart-ff738926-ae27-442d-9b82-873cdad65fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508823461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2508823461
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3999490502
Short name T178
Test name
Test status
Simulation time 485798470 ps
CPU time 1.22 seconds
Started Jun 05 05:22:59 PM PDT 24
Finished Jun 05 05:23:01 PM PDT 24
Peak memory 196500 kb
Host smart-cfeee16c-3d2a-4162-90ac-cb3f988caa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999490502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3999490502
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.402325480
Short name T277
Test name
Test status
Simulation time 11660528574 ps
CPU time 9.27 seconds
Started Jun 05 05:23:01 PM PDT 24
Finished Jun 05 05:23:12 PM PDT 24
Peak memory 191924 kb
Host smart-5b9a8bba-f59d-48f4-9d34-4c3b2bf169a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402325480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.402325480
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2594022405
Short name T256
Test name
Test status
Simulation time 444218254 ps
CPU time 1.28 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:03 PM PDT 24
Peak memory 191760 kb
Host smart-b36adc95-4225-48ac-ad75-5e49dcc190b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594022405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2594022405
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1900838155
Short name T60
Test name
Test status
Simulation time 19102159794 ps
CPU time 4.36 seconds
Started Jun 05 05:23:03 PM PDT 24
Finished Jun 05 05:23:08 PM PDT 24
Peak memory 191932 kb
Host smart-56cffa72-30b3-4206-b1cc-650e27e915ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900838155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1900838155
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.213991498
Short name T224
Test name
Test status
Simulation time 419925292 ps
CPU time 1.29 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:02 PM PDT 24
Peak memory 191756 kb
Host smart-72ce9d86-fa97-48f2-9e69-0aa139fbbaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213991498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.213991498
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.327949826
Short name T53
Test name
Test status
Simulation time 6474508490 ps
CPU time 10.89 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:12 PM PDT 24
Peak memory 191924 kb
Host smart-a3eddbc6-8b2f-4f94-9b0e-dffa35ef1113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327949826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.327949826
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.879183589
Short name T260
Test name
Test status
Simulation time 435172339 ps
CPU time 0.72 seconds
Started Jun 05 05:22:59 PM PDT 24
Finished Jun 05 05:23:01 PM PDT 24
Peak memory 191760 kb
Host smart-6a5c7f73-67df-49da-a409-6e70bca187cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879183589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.879183589
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2080899317
Short name T254
Test name
Test status
Simulation time 50361540298 ps
CPU time 23.82 seconds
Started Jun 05 05:23:01 PM PDT 24
Finished Jun 05 05:23:26 PM PDT 24
Peak memory 191852 kb
Host smart-2e8d5162-b729-49f3-bfa3-f9e2059457f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080899317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2080899317
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2757880913
Short name T274
Test name
Test status
Simulation time 553925188 ps
CPU time 1.49 seconds
Started Jun 05 05:23:01 PM PDT 24
Finished Jun 05 05:23:04 PM PDT 24
Peak memory 191748 kb
Host smart-8d448c43-de76-4b51-890e-51f25a5dbecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757880913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2757880913
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3486224023
Short name T214
Test name
Test status
Simulation time 51730742945 ps
CPU time 84.78 seconds
Started Jun 05 05:23:07 PM PDT 24
Finished Jun 05 05:24:33 PM PDT 24
Peak memory 191852 kb
Host smart-8eae7f1d-e8c7-491f-b186-77e279feda20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486224023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3486224023
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3927276041
Short name T262
Test name
Test status
Simulation time 442373112 ps
CPU time 1.2 seconds
Started Jun 05 05:23:05 PM PDT 24
Finished Jun 05 05:23:07 PM PDT 24
Peak memory 191792 kb
Host smart-5766fa93-bf0c-4fd9-8f30-0157d86d59cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927276041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3927276041
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3468016709
Short name T218
Test name
Test status
Simulation time 4616555639 ps
CPU time 7.62 seconds
Started Jun 05 05:23:11 PM PDT 24
Finished Jun 05 05:23:19 PM PDT 24
Peak memory 191928 kb
Host smart-37bc3393-9d13-4aaa-a111-470bd172cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468016709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3468016709
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1888058911
Short name T23
Test name
Test status
Simulation time 494699164 ps
CPU time 0.74 seconds
Started Jun 05 05:23:05 PM PDT 24
Finished Jun 05 05:23:07 PM PDT 24
Peak memory 191808 kb
Host smart-65a65a4c-4b69-4073-96a0-35328c11a5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888058911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1888058911
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.974416351
Short name T4
Test name
Test status
Simulation time 47312669919 ps
CPU time 37.27 seconds
Started Jun 05 05:23:07 PM PDT 24
Finished Jun 05 05:23:45 PM PDT 24
Peak memory 191924 kb
Host smart-44a831ef-4f7a-491c-9077-a97e8840f535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974416351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.974416351
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.423097583
Short name T233
Test name
Test status
Simulation time 392255488 ps
CPU time 0.86 seconds
Started Jun 05 05:23:06 PM PDT 24
Finished Jun 05 05:23:08 PM PDT 24
Peak memory 191804 kb
Host smart-9a23d41f-ebd2-46e6-9832-12f3300cc658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423097583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.423097583
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.4060397563
Short name T229
Test name
Test status
Simulation time 41365108813 ps
CPU time 14.16 seconds
Started Jun 05 05:23:07 PM PDT 24
Finished Jun 05 05:23:21 PM PDT 24
Peak memory 191900 kb
Host smart-1b11ef45-e5dd-4143-94a1-2fa228cc2770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060397563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.4060397563
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3691564833
Short name T54
Test name
Test status
Simulation time 471952831 ps
CPU time 0.8 seconds
Started Jun 05 05:23:06 PM PDT 24
Finished Jun 05 05:23:08 PM PDT 24
Peak memory 191808 kb
Host smart-56b070fe-9f70-4f51-a69e-e4c8c86fc36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691564833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3691564833
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2813895826
Short name T48
Test name
Test status
Simulation time 41986916665 ps
CPU time 60.11 seconds
Started Jun 05 05:23:16 PM PDT 24
Finished Jun 05 05:24:16 PM PDT 24
Peak memory 191944 kb
Host smart-50202433-bc8c-45f3-8d41-a52471464b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813895826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2813895826
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3005343980
Short name T226
Test name
Test status
Simulation time 544958921 ps
CPU time 0.79 seconds
Started Jun 05 05:23:08 PM PDT 24
Finished Jun 05 05:23:09 PM PDT 24
Peak memory 191616 kb
Host smart-cde9261b-4399-410c-b1d3-4816393f09e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005343980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3005343980
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3073079431
Short name T259
Test name
Test status
Simulation time 11193085253 ps
CPU time 4.97 seconds
Started Jun 05 05:22:52 PM PDT 24
Finished Jun 05 05:22:59 PM PDT 24
Peak memory 191876 kb
Host smart-91ce6c3e-dcd2-46c8-90bc-137e2e92effb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073079431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3073079431
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.4216558197
Short name T16
Test name
Test status
Simulation time 7602266791 ps
CPU time 6.57 seconds
Started Jun 05 05:22:49 PM PDT 24
Finished Jun 05 05:22:56 PM PDT 24
Peak memory 215736 kb
Host smart-fe99855b-8028-4dce-a454-324b7024c21c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216558197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.4216558197
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3760059131
Short name T204
Test name
Test status
Simulation time 394385037 ps
CPU time 0.65 seconds
Started Jun 05 05:22:50 PM PDT 24
Finished Jun 05 05:22:51 PM PDT 24
Peak memory 191800 kb
Host smart-90c6102e-918a-4ead-a0a0-ed1aef89201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760059131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3760059131
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3533643508
Short name T1
Test name
Test status
Simulation time 26999618080 ps
CPU time 42.18 seconds
Started Jun 05 05:23:16 PM PDT 24
Finished Jun 05 05:23:58 PM PDT 24
Peak memory 191900 kb
Host smart-532fef91-276b-46a0-9694-9ccb8ebba936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533643508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3533643508
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1436054671
Short name T219
Test name
Test status
Simulation time 573485964 ps
CPU time 0.97 seconds
Started Jun 05 05:23:14 PM PDT 24
Finished Jun 05 05:23:15 PM PDT 24
Peak memory 191788 kb
Host smart-1f3f538f-3d09-4393-822f-f326631d8541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436054671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1436054671
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.449598701
Short name T47
Test name
Test status
Simulation time 36738642707 ps
CPU time 16.8 seconds
Started Jun 05 05:23:14 PM PDT 24
Finished Jun 05 05:23:31 PM PDT 24
Peak memory 191924 kb
Host smart-3033068e-e66c-480e-a594-5315745ded7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449598701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.449598701
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.126484398
Short name T232
Test name
Test status
Simulation time 437323895 ps
CPU time 0.7 seconds
Started Jun 05 05:23:13 PM PDT 24
Finished Jun 05 05:23:14 PM PDT 24
Peak memory 191804 kb
Host smart-81fcfd76-850b-4e68-8b72-96c627f96010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126484398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.126484398
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1690094080
Short name T9
Test name
Test status
Simulation time 12036005599 ps
CPU time 5.61 seconds
Started Jun 05 05:23:15 PM PDT 24
Finished Jun 05 05:23:21 PM PDT 24
Peak memory 191928 kb
Host smart-ee8299e4-068e-465d-bdfc-1766fa2df7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690094080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1690094080
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3792532574
Short name T280
Test name
Test status
Simulation time 570370240 ps
CPU time 1.48 seconds
Started Jun 05 05:23:15 PM PDT 24
Finished Jun 05 05:23:17 PM PDT 24
Peak memory 191792 kb
Host smart-fade73ef-7e86-4162-bf7b-fa733da8aa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792532574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3792532574
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_jump.56922873
Short name T188
Test name
Test status
Simulation time 481682848 ps
CPU time 1.01 seconds
Started Jun 05 05:23:17 PM PDT 24
Finished Jun 05 05:23:18 PM PDT 24
Peak memory 196492 kb
Host smart-fd9ed119-1965-4030-a2ff-107956b78b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56922873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.56922873
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2229062864
Short name T234
Test name
Test status
Simulation time 24133651911 ps
CPU time 9.5 seconds
Started Jun 05 05:23:14 PM PDT 24
Finished Jun 05 05:23:24 PM PDT 24
Peak memory 191928 kb
Host smart-8f6998fd-c5cf-4031-8d1f-733369e8c296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229062864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2229062864
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3286900591
Short name T279
Test name
Test status
Simulation time 531231301 ps
CPU time 1.4 seconds
Started Jun 05 05:23:15 PM PDT 24
Finished Jun 05 05:23:17 PM PDT 24
Peak memory 191808 kb
Host smart-4aa01fbd-4a0f-4022-892a-10cfc68c2baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286900591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3286900591
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2787373319
Short name T28
Test name
Test status
Simulation time 464063904 ps
CPU time 1.29 seconds
Started Jun 05 05:23:16 PM PDT 24
Finished Jun 05 05:23:17 PM PDT 24
Peak memory 196432 kb
Host smart-0b9f4d9c-03a7-4f57-b5e2-d51ca9065ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787373319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2787373319
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2339664279
Short name T273
Test name
Test status
Simulation time 32336903505 ps
CPU time 52.28 seconds
Started Jun 05 05:23:17 PM PDT 24
Finished Jun 05 05:24:10 PM PDT 24
Peak memory 191904 kb
Host smart-035f2439-6bc0-481d-91df-07fda0009b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339664279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2339664279
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3344196510
Short name T239
Test name
Test status
Simulation time 529137553 ps
CPU time 0.92 seconds
Started Jun 05 05:23:17 PM PDT 24
Finished Jun 05 05:23:19 PM PDT 24
Peak memory 191816 kb
Host smart-f1998d39-5678-4ed7-8041-eb0691508f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344196510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3344196510
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.387952496
Short name T211
Test name
Test status
Simulation time 5911753119 ps
CPU time 2.94 seconds
Started Jun 05 05:23:23 PM PDT 24
Finished Jun 05 05:23:26 PM PDT 24
Peak memory 191924 kb
Host smart-abe99d71-07e5-461a-922f-d5e06d513a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387952496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.387952496
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.181947837
Short name T268
Test name
Test status
Simulation time 411339169 ps
CPU time 0.72 seconds
Started Jun 05 05:23:17 PM PDT 24
Finished Jun 05 05:23:18 PM PDT 24
Peak memory 191804 kb
Host smart-9c0d4729-566f-446d-a45d-684ff32591e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181947837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.181947837
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.769710803
Short name T276
Test name
Test status
Simulation time 15133120185 ps
CPU time 5.52 seconds
Started Jun 05 05:23:22 PM PDT 24
Finished Jun 05 05:23:28 PM PDT 24
Peak memory 191880 kb
Host smart-dd783de4-e04d-4607-a059-a9dde9cdc978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769710803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.769710803
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3123911741
Short name T203
Test name
Test status
Simulation time 627012201 ps
CPU time 0.83 seconds
Started Jun 05 05:23:23 PM PDT 24
Finished Jun 05 05:23:24 PM PDT 24
Peak memory 191792 kb
Host smart-d73cfe54-ba85-4e97-a0a1-0aaed1e84c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123911741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3123911741
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1722509658
Short name T264
Test name
Test status
Simulation time 26649656765 ps
CPU time 37.4 seconds
Started Jun 05 05:23:21 PM PDT 24
Finished Jun 05 05:23:59 PM PDT 24
Peak memory 191940 kb
Host smart-1f5e7c47-4dfe-4917-b92f-6a164499387c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722509658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1722509658
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3663480681
Short name T7
Test name
Test status
Simulation time 440383377 ps
CPU time 0.76 seconds
Started Jun 05 05:23:22 PM PDT 24
Finished Jun 05 05:23:23 PM PDT 24
Peak memory 191816 kb
Host smart-da1d2fe3-ddc4-4a90-80ec-3a635d99c43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663480681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3663480681
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1409004123
Short name T269
Test name
Test status
Simulation time 23522864848 ps
CPU time 32.85 seconds
Started Jun 05 05:23:35 PM PDT 24
Finished Jun 05 05:24:09 PM PDT 24
Peak memory 191944 kb
Host smart-61834482-1de1-47dc-85b8-81e86bdc443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409004123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1409004123
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1408348094
Short name T258
Test name
Test status
Simulation time 434870960 ps
CPU time 1.07 seconds
Started Jun 05 05:23:34 PM PDT 24
Finished Jun 05 05:23:36 PM PDT 24
Peak memory 191800 kb
Host smart-7dc61237-1e69-4e31-ab0f-c1babcf882e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408348094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1408348094
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1152282234
Short name T220
Test name
Test status
Simulation time 24421171316 ps
CPU time 19.27 seconds
Started Jun 05 05:23:35 PM PDT 24
Finished Jun 05 05:23:55 PM PDT 24
Peak memory 191916 kb
Host smart-05899982-2645-483a-81c5-60abc1e6cc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152282234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1152282234
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2848146657
Short name T244
Test name
Test status
Simulation time 392142562 ps
CPU time 1.12 seconds
Started Jun 05 05:23:35 PM PDT 24
Finished Jun 05 05:23:36 PM PDT 24
Peak memory 191804 kb
Host smart-08137d2b-1aed-4fb1-9184-1cbb2ac4573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848146657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2848146657
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.136396360
Short name T208
Test name
Test status
Simulation time 29187935600 ps
CPU time 37.89 seconds
Started Jun 05 05:22:51 PM PDT 24
Finished Jun 05 05:23:30 PM PDT 24
Peak memory 191924 kb
Host smart-7ef9e739-46bf-4171-bef7-755c1e13fcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136396360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.136396360
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.9759830
Short name T19
Test name
Test status
Simulation time 4368735922 ps
CPU time 1.45 seconds
Started Jun 05 05:22:53 PM PDT 24
Finished Jun 05 05:22:56 PM PDT 24
Peak memory 215680 kb
Host smart-c2bc318b-473f-430d-9055-15923f8b9bc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9759830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.9759830
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1549561076
Short name T252
Test name
Test status
Simulation time 564826233 ps
CPU time 0.82 seconds
Started Jun 05 05:22:59 PM PDT 24
Finished Jun 05 05:23:00 PM PDT 24
Peak memory 191808 kb
Host smart-80f25ac3-9e8e-42bf-aab0-4ae0688f2fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549561076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1549561076
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1991229377
Short name T257
Test name
Test status
Simulation time 54425153271 ps
CPU time 16.53 seconds
Started Jun 05 05:23:35 PM PDT 24
Finished Jun 05 05:23:53 PM PDT 24
Peak memory 191920 kb
Host smart-fd0e1c36-3998-403e-ad53-dff16566188c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991229377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1991229377
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.446467094
Short name T212
Test name
Test status
Simulation time 409056239 ps
CPU time 0.68 seconds
Started Jun 05 05:23:35 PM PDT 24
Finished Jun 05 05:23:36 PM PDT 24
Peak memory 191792 kb
Host smart-d6fa88d0-9d20-4308-8a00-c267079fca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446467094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.446467094
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.76925133
Short name T186
Test name
Test status
Simulation time 365910824 ps
CPU time 1.08 seconds
Started Jun 05 05:23:37 PM PDT 24
Finished Jun 05 05:23:39 PM PDT 24
Peak memory 196412 kb
Host smart-066bef69-5d72-47b3-b78f-819227a01f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76925133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.76925133
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1001150902
Short name T266
Test name
Test status
Simulation time 29630748288 ps
CPU time 12.06 seconds
Started Jun 05 05:23:36 PM PDT 24
Finished Jun 05 05:23:49 PM PDT 24
Peak memory 191900 kb
Host smart-c25e15ad-1868-4d48-97b4-59b097ac3662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001150902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1001150902
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3844980233
Short name T238
Test name
Test status
Simulation time 356631898 ps
CPU time 1.16 seconds
Started Jun 05 05:23:36 PM PDT 24
Finished Jun 05 05:23:38 PM PDT 24
Peak memory 191816 kb
Host smart-835094ad-f9e5-4904-b6a5-9166db0bc970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844980233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3844980233
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.769700083
Short name T45
Test name
Test status
Simulation time 31063178561 ps
CPU time 4.78 seconds
Started Jun 05 05:23:35 PM PDT 24
Finished Jun 05 05:23:41 PM PDT 24
Peak memory 191928 kb
Host smart-15842f06-8a0b-48d3-8b9b-cae2eba9cf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769700083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.769700083
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.176285062
Short name T20
Test name
Test status
Simulation time 360706510 ps
CPU time 0.75 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:23:41 PM PDT 24
Peak memory 191808 kb
Host smart-fe6a317f-21bc-4228-9723-db1191443b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176285062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.176285062
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.315438200
Short name T243
Test name
Test status
Simulation time 3623838306 ps
CPU time 3.25 seconds
Started Jun 05 05:23:36 PM PDT 24
Finished Jun 05 05:23:40 PM PDT 24
Peak memory 191924 kb
Host smart-571a87ac-0a5f-42f0-95c8-f3c889fb3a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315438200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.315438200
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2651128502
Short name T10
Test name
Test status
Simulation time 418919816 ps
CPU time 1.25 seconds
Started Jun 05 05:23:35 PM PDT 24
Finished Jun 05 05:23:38 PM PDT 24
Peak memory 191808 kb
Host smart-fc06bc50-e8d6-48d3-a4b2-4119cd8624e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651128502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2651128502
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2930635838
Short name T58
Test name
Test status
Simulation time 945569612 ps
CPU time 2.02 seconds
Started Jun 05 05:23:35 PM PDT 24
Finished Jun 05 05:23:38 PM PDT 24
Peak memory 191784 kb
Host smart-a165f9aa-995e-46fe-9dfe-195279ab229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930635838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2930635838
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.433877906
Short name T241
Test name
Test status
Simulation time 583233033 ps
CPU time 1.01 seconds
Started Jun 05 05:23:37 PM PDT 24
Finished Jun 05 05:23:38 PM PDT 24
Peak memory 191804 kb
Host smart-6f07b8c7-5341-42dd-8c82-5b7ebb4bda42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433877906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.433877906
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_jump.943071620
Short name T167
Test name
Test status
Simulation time 373175056 ps
CPU time 0.71 seconds
Started Jun 05 05:23:42 PM PDT 24
Finished Jun 05 05:23:43 PM PDT 24
Peak memory 196404 kb
Host smart-a6963cdf-de5f-4a86-8312-17bb9364c5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943071620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.943071620
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1826233370
Short name T247
Test name
Test status
Simulation time 23323070364 ps
CPU time 5.74 seconds
Started Jun 05 05:23:36 PM PDT 24
Finished Jun 05 05:23:42 PM PDT 24
Peak memory 192120 kb
Host smart-0231a76f-9d9f-41b8-8ea5-b0afd6d97ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826233370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1826233370
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1827935499
Short name T263
Test name
Test status
Simulation time 619902439 ps
CPU time 0.82 seconds
Started Jun 05 05:23:36 PM PDT 24
Finished Jun 05 05:23:38 PM PDT 24
Peak memory 191812 kb
Host smart-8a0a7d8c-c16d-4a74-8c8c-97f4c3008b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827935499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1827935499
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2951267025
Short name T196
Test name
Test status
Simulation time 355924226 ps
CPU time 1.22 seconds
Started Jun 05 05:23:41 PM PDT 24
Finished Jun 05 05:23:43 PM PDT 24
Peak memory 196424 kb
Host smart-3a124020-00b3-4762-9a1d-027299109396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951267025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2951267025
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1560571216
Short name T221
Test name
Test status
Simulation time 27646274939 ps
CPU time 10.23 seconds
Started Jun 05 05:23:39 PM PDT 24
Finished Jun 05 05:23:50 PM PDT 24
Peak memory 191908 kb
Host smart-d830b818-1247-49ad-9be9-50bbfab99cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560571216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1560571216
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3800678797
Short name T249
Test name
Test status
Simulation time 649422068 ps
CPU time 0.65 seconds
Started Jun 05 05:23:43 PM PDT 24
Finished Jun 05 05:23:44 PM PDT 24
Peak memory 191816 kb
Host smart-23555fd9-1901-46d7-a8a7-055e857df3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800678797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3800678797
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1952445828
Short name T180
Test name
Test status
Simulation time 309111802588 ps
CPU time 110.78 seconds
Started Jun 05 05:23:38 PM PDT 24
Finished Jun 05 05:25:29 PM PDT 24
Peak memory 191908 kb
Host smart-a2602ce1-c9fd-456f-9c41-b9cae4d714d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952445828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1952445828
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2209359712
Short name T227
Test name
Test status
Simulation time 25777679257 ps
CPU time 18.66 seconds
Started Jun 05 05:23:41 PM PDT 24
Finished Jun 05 05:24:00 PM PDT 24
Peak memory 191900 kb
Host smart-d01cbfc4-280e-442c-8f2e-9cd0c97ab3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209359712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2209359712
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3929600804
Short name T5
Test name
Test status
Simulation time 449496296 ps
CPU time 0.91 seconds
Started Jun 05 05:23:39 PM PDT 24
Finished Jun 05 05:23:40 PM PDT 24
Peak memory 191996 kb
Host smart-79e02efe-a71f-4bed-873a-aaf1469ad64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929600804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3929600804
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1435937855
Short name T3
Test name
Test status
Simulation time 26956894205 ps
CPU time 10.69 seconds
Started Jun 05 05:23:39 PM PDT 24
Finished Jun 05 05:23:50 PM PDT 24
Peak memory 191924 kb
Host smart-18a2d89f-dbdc-4bca-a876-75ba63e11a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435937855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1435937855
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1813672157
Short name T8
Test name
Test status
Simulation time 544007527 ps
CPU time 0.92 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:23:42 PM PDT 24
Peak memory 191792 kb
Host smart-17303c54-9b73-46f6-aec0-822ee242cd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813672157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1813672157
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2597414737
Short name T184
Test name
Test status
Simulation time 87186396867 ps
CPU time 729.43 seconds
Started Jun 05 05:23:42 PM PDT 24
Finished Jun 05 05:35:52 PM PDT 24
Peak memory 214860 kb
Host smart-b99d028c-6784-4ded-b278-46afdb22b99f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597414737 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2597414737
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1138822667
Short name T179
Test name
Test status
Simulation time 374892383 ps
CPU time 1.17 seconds
Started Jun 05 05:23:42 PM PDT 24
Finished Jun 05 05:23:44 PM PDT 24
Peak memory 196352 kb
Host smart-9b951785-5652-4435-87c1-834840718e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138822667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1138822667
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.279669709
Short name T222
Test name
Test status
Simulation time 30600986713 ps
CPU time 27.19 seconds
Started Jun 05 05:23:42 PM PDT 24
Finished Jun 05 05:24:10 PM PDT 24
Peak memory 191924 kb
Host smart-4a2fb1d2-bfd4-487c-9cc2-3333e526c809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279669709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.279669709
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1458645106
Short name T272
Test name
Test status
Simulation time 533311753 ps
CPU time 0.74 seconds
Started Jun 05 05:23:38 PM PDT 24
Finished Jun 05 05:23:40 PM PDT 24
Peak memory 191792 kb
Host smart-146c633c-df55-4e5f-b21f-3aa4ef3dc1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458645106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1458645106
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1401545406
Short name T169
Test name
Test status
Simulation time 125019630387 ps
CPU time 171.3 seconds
Started Jun 05 05:23:41 PM PDT 24
Finished Jun 05 05:26:33 PM PDT 24
Peak memory 191928 kb
Host smart-c8b977b3-d2b4-4682-b51f-43783f1a175a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401545406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1401545406
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1950915753
Short name T278
Test name
Test status
Simulation time 28084369116 ps
CPU time 44.43 seconds
Started Jun 05 05:22:52 PM PDT 24
Finished Jun 05 05:23:38 PM PDT 24
Peak memory 191908 kb
Host smart-4f460cf4-62d2-4d06-b455-43491d99bac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950915753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1950915753
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3909988747
Short name T18
Test name
Test status
Simulation time 4056096011 ps
CPU time 6.55 seconds
Started Jun 05 05:22:49 PM PDT 24
Finished Jun 05 05:22:56 PM PDT 24
Peak memory 215404 kb
Host smart-702a0875-a5d7-4f55-825a-8d7cf0369b3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909988747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3909988747
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2475570857
Short name T162
Test name
Test status
Simulation time 566433615 ps
CPU time 1.11 seconds
Started Jun 05 05:22:52 PM PDT 24
Finished Jun 05 05:22:55 PM PDT 24
Peak memory 191808 kb
Host smart-a13449e7-394b-49cb-b073-def4ea7e44e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475570857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2475570857
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2645743410
Short name T216
Test name
Test status
Simulation time 1608663607 ps
CPU time 2.69 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:23:44 PM PDT 24
Peak memory 191784 kb
Host smart-4ec3f411-95d5-474f-b4b4-41c91d903704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645743410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2645743410
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.4140721919
Short name T246
Test name
Test status
Simulation time 488752646 ps
CPU time 0.85 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:23:42 PM PDT 24
Peak memory 191804 kb
Host smart-9c96f455-8f63-4a4c-a492-854d8bc10c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140721919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.4140721919
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1889290408
Short name T248
Test name
Test status
Simulation time 42694900783 ps
CPU time 4.92 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:23:45 PM PDT 24
Peak memory 191864 kb
Host smart-6f98519f-80af-4a82-ab77-a68f2ad77903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889290408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1889290408
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.4049828518
Short name T230
Test name
Test status
Simulation time 518836236 ps
CPU time 0.76 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:23:41 PM PDT 24
Peak memory 191744 kb
Host smart-bbf414f6-ee39-4852-8bd4-cf3f845177df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049828518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.4049828518
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_jump.17831359
Short name T44
Test name
Test status
Simulation time 537682256 ps
CPU time 0.8 seconds
Started Jun 05 05:23:42 PM PDT 24
Finished Jun 05 05:23:43 PM PDT 24
Peak memory 196408 kb
Host smart-a3824e09-bd3d-4035-b9ac-c3553506a4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17831359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.17831359
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1315003612
Short name T46
Test name
Test status
Simulation time 9010958727 ps
CPU time 3.54 seconds
Started Jun 05 05:23:41 PM PDT 24
Finished Jun 05 05:23:46 PM PDT 24
Peak memory 191900 kb
Host smart-f81bcae8-2185-4fa3-95a9-ebdf18d082e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315003612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1315003612
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2531176476
Short name T27
Test name
Test status
Simulation time 417824554 ps
CPU time 1.19 seconds
Started Jun 05 05:23:41 PM PDT 24
Finished Jun 05 05:23:43 PM PDT 24
Peak memory 191804 kb
Host smart-bd0d1e7e-6c75-49ca-bef4-fcdf662f14a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531176476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2531176476
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3450277127
Short name T271
Test name
Test status
Simulation time 29443735030 ps
CPU time 44.05 seconds
Started Jun 05 05:23:49 PM PDT 24
Finished Jun 05 05:24:33 PM PDT 24
Peak memory 191924 kb
Host smart-7d7ae18d-a990-45cf-9b39-dfa50b37f5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450277127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3450277127
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1341307893
Short name T240
Test name
Test status
Simulation time 459427060 ps
CPU time 0.76 seconds
Started Jun 05 05:23:40 PM PDT 24
Finished Jun 05 05:23:42 PM PDT 24
Peak memory 191732 kb
Host smart-cdf7502f-8bfe-4514-91ea-7beafedfed23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341307893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1341307893
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1332370410
Short name T175
Test name
Test status
Simulation time 476966005 ps
CPU time 0.92 seconds
Started Jun 05 05:23:56 PM PDT 24
Finished Jun 05 05:23:58 PM PDT 24
Peak memory 196420 kb
Host smart-2500d6db-e976-419a-9f1b-5478fece2c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332370410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1332370410
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3159986184
Short name T210
Test name
Test status
Simulation time 12576494409 ps
CPU time 1.64 seconds
Started Jun 05 05:23:49 PM PDT 24
Finished Jun 05 05:23:52 PM PDT 24
Peak memory 191924 kb
Host smart-89ff95e7-44fa-44c3-a89d-d167b0c6902b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159986184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3159986184
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.10617969
Short name T267
Test name
Test status
Simulation time 412951303 ps
CPU time 1.19 seconds
Started Jun 05 05:23:51 PM PDT 24
Finished Jun 05 05:23:53 PM PDT 24
Peak memory 191752 kb
Host smart-02ff2b93-7f47-4df3-bfed-931e232a53b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10617969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.10617969
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2603836975
Short name T225
Test name
Test status
Simulation time 11795574277 ps
CPU time 9.08 seconds
Started Jun 05 05:23:53 PM PDT 24
Finished Jun 05 05:24:03 PM PDT 24
Peak memory 191924 kb
Host smart-1ec40f42-4c31-4c07-ba84-6d785dda1e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603836975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2603836975
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1312743453
Short name T223
Test name
Test status
Simulation time 515886565 ps
CPU time 0.78 seconds
Started Jun 05 05:23:49 PM PDT 24
Finished Jun 05 05:23:51 PM PDT 24
Peak memory 191800 kb
Host smart-40107b07-79e4-4006-8625-2e6e097b3fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312743453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1312743453
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.230251568
Short name T235
Test name
Test status
Simulation time 48425756989 ps
CPU time 59 seconds
Started Jun 05 05:23:46 PM PDT 24
Finished Jun 05 05:24:46 PM PDT 24
Peak memory 191936 kb
Host smart-076dadba-f438-46a7-8c09-8732cca6787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230251568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.230251568
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.317020147
Short name T30
Test name
Test status
Simulation time 472520499 ps
CPU time 1.3 seconds
Started Jun 05 05:23:50 PM PDT 24
Finished Jun 05 05:23:52 PM PDT 24
Peak memory 191760 kb
Host smart-41276429-fe95-41ca-9cdb-7dfd58fcffc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317020147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.317020147
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1283751877
Short name T242
Test name
Test status
Simulation time 21874813691 ps
CPU time 3.05 seconds
Started Jun 05 05:23:55 PM PDT 24
Finished Jun 05 05:23:59 PM PDT 24
Peak memory 191932 kb
Host smart-6df5d6e4-6b30-4b38-8574-eb7f1d66fc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283751877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1283751877
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.632233721
Short name T206
Test name
Test status
Simulation time 481716376 ps
CPU time 0.75 seconds
Started Jun 05 05:23:50 PM PDT 24
Finished Jun 05 05:23:51 PM PDT 24
Peak memory 191760 kb
Host smart-9cbdcc24-9b1f-4fec-b951-bd0c6d26970d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632233721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.632233721
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2824635178
Short name T270
Test name
Test status
Simulation time 2008213326 ps
CPU time 2.36 seconds
Started Jun 05 05:23:50 PM PDT 24
Finished Jun 05 05:23:53 PM PDT 24
Peak memory 191808 kb
Host smart-aa8acde8-1c4d-4adf-897b-280ec669b3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824635178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2824635178
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1613310322
Short name T236
Test name
Test status
Simulation time 420024467 ps
CPU time 0.69 seconds
Started Jun 05 05:23:49 PM PDT 24
Finished Jun 05 05:23:50 PM PDT 24
Peak memory 191804 kb
Host smart-dfed0c88-7a2f-4f19-8122-f9fe2cabe4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613310322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1613310322
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1833637310
Short name T261
Test name
Test status
Simulation time 35203304932 ps
CPU time 5.14 seconds
Started Jun 05 05:23:51 PM PDT 24
Finished Jun 05 05:23:57 PM PDT 24
Peak memory 191852 kb
Host smart-d71681fe-d9e3-4932-a139-396ca3edfa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833637310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1833637310
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.4061154212
Short name T265
Test name
Test status
Simulation time 384644810 ps
CPU time 0.7 seconds
Started Jun 05 05:23:47 PM PDT 24
Finished Jun 05 05:23:49 PM PDT 24
Peak memory 191812 kb
Host smart-c402ae00-4158-4e06-b079-9f74c27087e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061154212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4061154212
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1868312136
Short name T187
Test name
Test status
Simulation time 590968430 ps
CPU time 0.79 seconds
Started Jun 05 05:22:52 PM PDT 24
Finished Jun 05 05:22:54 PM PDT 24
Peak memory 196504 kb
Host smart-1eb8e5eb-b02c-4b6e-a3fe-18d4387fe4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868312136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1868312136
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2660002100
Short name T275
Test name
Test status
Simulation time 4922530209 ps
CPU time 7.35 seconds
Started Jun 05 05:22:52 PM PDT 24
Finished Jun 05 05:23:01 PM PDT 24
Peak memory 191924 kb
Host smart-f9306c62-e5ca-4a16-9581-db4e2c61a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660002100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2660002100
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.99095174
Short name T255
Test name
Test status
Simulation time 528937517 ps
CPU time 1.6 seconds
Started Jun 05 05:22:50 PM PDT 24
Finished Jun 05 05:22:53 PM PDT 24
Peak memory 192008 kb
Host smart-452f3c17-c312-45a9-9183-7d71f3f89a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99095174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.99095174
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3220942191
Short name T228
Test name
Test status
Simulation time 28117714921 ps
CPU time 40.33 seconds
Started Jun 05 05:22:50 PM PDT 24
Finished Jun 05 05:23:31 PM PDT 24
Peak memory 191884 kb
Host smart-1b18d316-7812-4866-9510-a1fcf680593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220942191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3220942191
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.214509208
Short name T207
Test name
Test status
Simulation time 555549762 ps
CPU time 1.42 seconds
Started Jun 05 05:22:52 PM PDT 24
Finished Jun 05 05:22:54 PM PDT 24
Peak memory 191796 kb
Host smart-83587cdf-77ab-4f8d-b3ea-e4dbbc10d826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214509208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.214509208
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2502797620
Short name T172
Test name
Test status
Simulation time 591838414 ps
CPU time 1.22 seconds
Started Jun 05 05:22:59 PM PDT 24
Finished Jun 05 05:23:00 PM PDT 24
Peak memory 196412 kb
Host smart-e46f37d3-b4aa-4338-bf80-a3b0f9f57879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502797620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2502797620
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2785106418
Short name T21
Test name
Test status
Simulation time 29100264246 ps
CPU time 45.91 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:47 PM PDT 24
Peak memory 191928 kb
Host smart-d6cf2c61-8b4f-445f-8e5f-c0c25cb594d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785106418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2785106418
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1345054194
Short name T245
Test name
Test status
Simulation time 357997180 ps
CPU time 0.7 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:03 PM PDT 24
Peak memory 191804 kb
Host smart-56cd2bc3-c2e0-48d2-afcd-774bcff8ab08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345054194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1345054194
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2387273457
Short name T213
Test name
Test status
Simulation time 26907714983 ps
CPU time 31.23 seconds
Started Jun 05 05:23:01 PM PDT 24
Finished Jun 05 05:23:33 PM PDT 24
Peak memory 191928 kb
Host smart-5312e005-53b7-4003-bd92-4b048f0569dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387273457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2387273457
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1262539639
Short name T237
Test name
Test status
Simulation time 507810130 ps
CPU time 1.3 seconds
Started Jun 05 05:22:59 PM PDT 24
Finished Jun 05 05:23:01 PM PDT 24
Peak memory 191808 kb
Host smart-9d1a0b29-5f4f-46b0-a4fd-4e2578136792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262539639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1262539639
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2287706759
Short name T217
Test name
Test status
Simulation time 46858761351 ps
CPU time 16.9 seconds
Started Jun 05 05:23:01 PM PDT 24
Finished Jun 05 05:23:19 PM PDT 24
Peak memory 191884 kb
Host smart-64435836-ff03-4add-9f6f-eb2753897b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287706759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2287706759
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1010934091
Short name T250
Test name
Test status
Simulation time 581400212 ps
CPU time 0.79 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:23:03 PM PDT 24
Peak memory 191800 kb
Host smart-738f25bc-c163-4563-a455-071f2c0a8381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010934091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1010934091
Directory /workspace/9.aon_timer_smoke/latest
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