Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	0	34	100.00	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	36645	1		T1	12		T2	400		T3	11
bark[1]	531	1		T43	14		T37	119		T136	7
bark[2]	574	1		T6	61		T11	331		T38	14
bark[3]	190	1		T8	5		T92	30		T35	26
bark[4]	1044	1		T8	7		T37	238		T136	259
bark[5]	900	1		T36	21		T111	14		T174	14
bark[6]	459	1		T2	31		T10	7		T36	21
bark[7]	707	1		T28	30		T149	196		T117	21
bark[8]	621	1		T16	21		T121	26		T154	21
bark[9]	336	1		T10	21		T37	40		T124	14
bark[10]	133	1		T28	21		T127	26		T126	21
bark[11]	1241	1		T28	21		T127	21		T25	248
bark[12]	528	1		T2	19		T8	30		T44	60
bark[13]	210	1		T171	49		T126	14		T163	14
bark[14]	402	1		T7	21		T137	14		T127	30
bark[15]	272	1		T16	21		T127	21		T21	30
bark[16]	418	1		T4	14		T10	21		T149	65
bark[17]	452	1		T12	66		T127	21		T178	14
bark[18]	587	1		T10	21		T92	35		T35	44
bark[19]	505	1		T2	205		T10	21		T16	26
bark[20]	887	1		T2	30		T171	21		T117	289
bark[21]	669	1		T36	26		T37	118		T102	52
bark[22]	260	1		T12	21		T150	19		T149	21
bark[23]	259	1		T10	21		T20	21		T107	21
bark[24]	741	1		T126	21		T101	14		T128	21
bark[25]	466	1		T5	44		T42	14		T110	21
bark[26]	315	1		T12	21		T168	21		T126	53
bark[27]	846	1		T8	44		T187	14		T25	273
bark[28]	808	1		T28	21		T90	14		T136	31
bark[29]	613	1		T35	21		T36	191		T158	14
bark[30]	635	1		T2	26		T10	129		T16	133
bark[31]	366	1		T189	14		T149	47		T117	5
bark_0	4868	1		T1	7		T2	84		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	35843	1		T1	11		T2	373		T3	10
bite[1]	376	1		T8	4		T149	46		T132	84
bite[2]	255	1		T126	21		T114	22		T147	42
bite[3]	735	1		T2	30		T11	330		T36	26
bite[4]	158	1		T28	30		T21	21		T23	13
bite[5]	516	1		T136	6		T128	21		T142	21
bite[6]	701	1		T8	6		T10	21		T12	66
bite[7]	460	1		T6	61		T28	21		T37	139
bite[8]	554	1		T117	4		T172	13		T98	21
bite[9]	427	1		T6	21		T36	21		T124	13
bite[10]	1418	1		T2	204		T10	185		T38	13
bite[11]	156	1		T117	46		T95	26		T57	21
bite[12]	1026	1		T36	46		T149	64		T126	21
bite[13]	821	1		T10	21		T16	26		T21	30
bite[14]	92	1		T154	31		T189	13		T110	48
bite[15]	753	1		T8	30		T10	21		T36	21
bite[16]	827	1		T10	27		T28	21		T43	13
bite[17]	569	1		T137	13		T127	21		T171	21
bite[18]	632	1		T35	21		T127	30		T147	32
bite[19]	587	1		T10	128		T16	21		T175	13
bite[20]	837	1		T12	21		T45	13		T25	247
bite[21]	477	1		T2	31		T136	192		T195	6
bite[22]	430	1		T2	26		T10	21		T16	21
bite[23]	213	1		T8	43		T127	21		T177	42
bite[24]	534	1		T7	21		T92	35		T35	21
bite[25]	552	1		T12	21		T25	21		T109	21
bite[26]	498	1		T16	132		T44	60		T37	117
bite[27]	651	1		T90	13		T35	43		T102	21
bite[28]	650	1		T150	21		T171	49		T147	21
bite[29]	245	1		T4	13		T28	21		T42	13
bite[30]	255	1		T2	18		T158	13		T136	31
bite[31]	846	1		T2	21		T5	43		T35	25
bite_0	5394	1		T1	8		T2	92		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	58488	1		T1	19		T2	795		T3	18

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	0	34	100.00

User Defined Bins for prescale_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale_max	32	1		T112	32		-	-		-	-
prescale[0]	919	1		T5	9		T8	9		T11	40
prescale[1]	684	1		T147	46		T105	23		T132	19
prescale[2]	1020	1		T28	21		T196	9		T176	103
prescale[3]	1320	1		T2	37		T5	19		T7	63
prescale[4]	1560	1		T2	28		T6	58		T7	98
prescale[5]	1025	1		T2	37		T5	133		T37	64
prescale[6]	1002	1		T7	55		T8	19		T10	28
prescale[7]	1531	1		T1	9		T5	19		T10	19
prescale[8]	955	1		T7	47		T11	9		T12	9
prescale[9]	595	1		T2	19		T8	60		T168	24
prescale[10]	1070	1		T6	28		T7	42		T8	19
prescale[11]	554	1		T2	107		T7	2		T8	4
prescale[12]	746	1		T7	94		T9	9		T10	96
prescale[13]	1197	1		T2	42		T5	37		T8	2
prescale[14]	1042	1		T2	4		T5	48		T8	134
prescale[15]	1297	1		T16	55		T136	223		T154	19
prescale[16]	838	1		T6	9		T8	32		T10	102
prescale[17]	1122	1		T8	2		T10	20		T36	37
prescale[18]	1029	1		T5	2		T7	224		T10	2
prescale[19]	754	1		T5	19		T7	19		T8	19
prescale[20]	491	1		T7	19		T8	120		T36	2
prescale[21]	906	1		T150	19		T37	224		T117	21
prescale[22]	782	1		T10	100		T11	106		T150	37
prescale[23]	1082	1		T5	94		T11	49		T44	41
prescale[24]	970	1		T2	2		T5	2		T11	19
prescale[25]	955	1		T5	4		T7	24		T10	32
prescale[26]	1130	1		T2	28		T7	19		T10	37
prescale[27]	452	1		T8	19		T10	68		T11	14
prescale[28]	623	1		T2	2		T5	31		T7	19
prescale[29]	918	1		T5	21		T7	121		T10	2
prescale[30]	877	1		T8	19		T22	19		T117	40
prescale[31]	1357	1		T5	29		T8	55		T35	2
prescale_0	27685	1		T1	10		T2	489		T3	18

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	44227	1		T1	19		T2	552		T3	9
auto[1]	14261	1		T2	243		T3	9		T5	219

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	58488	1		T1	19		T2	795		T3	18

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	35097	1		T1	14		T2	427		T3	13
wkup[1]	373	1		T25	8		T156	15		T142	52
wkup[2]	230	1		T5	21		T7	15		T137	15
wkup[3]	534	1		T2	21		T4	15		T8	42
wkup[4]	215	1		T2	31		T149	26		T20	21
wkup[5]	206	1		T5	21		T8	21		T11	21
wkup[6]	278	1		T7	21		T10	8		T171	21
wkup[7]	283	1		T37	30		T136	21		T176	8
wkup[8]	439	1		T16	21		T36	42		T37	21
wkup[9]	376	1		T10	21		T36	21		T103	21
wkup[10]	229	1		T7	21		T136	21		T105	21
wkup[11]	284	1		T2	26		T7	26		T10	21
wkup[12]	344	1		T5	30		T11	21		T28	8
wkup[13]	123	1		T136	21		T27	15		T172	15
wkup[14]	422	1		T6	21		T7	21		T10	21
wkup[15]	276	1		T144	30		T116	15		T118	15
wkup[16]	390	1		T28	21		T37	40		T157	21
wkup[17]	180	1		T43	15		T44	21		T46	21
wkup[18]	387	1		T8	21		T35	21		T37	26
wkup[19]	230	1		T2	45		T124	15		T117	21
wkup[20]	171	1		T7	21		T90	15		T121	26
wkup[21]	375	1		T2	20		T5	21		T7	21
wkup[22]	189	1		T7	21		T37	21		T136	21
wkup[23]	401	1		T2	26		T127	21		T136	79
wkup[24]	355	1		T127	30		T37	51		T126	15
wkup[25]	350	1		T127	21		T102	26		T107	48
wkup[26]	350	1		T8	21		T25	26		T144	21
wkup[27]	254	1		T37	21		T117	26		T141	42
wkup[28]	254	1		T6	21		T136	42		T149	30
wkup[29]	500	1		T6	21		T8	8		T10	30
wkup[30]	161	1		T117	6		T180	21		T98	21
wkup[31]	257	1		T7	30		T8	21		T20	8
wkup[32]	360	1		T7	21		T36	26		T20	30
wkup[33]	355	1		T11	8		T20	30		T26	21
wkup[34]	188	1		T2	21		T10	21		T117	21
wkup[35]	315	1		T2	21		T5	30		T12	21
wkup[36]	359	1		T35	21		T36	21		T117	42
wkup[37]	298	1		T5	21		T16	21		T154	31
wkup[38]	250	1		T42	15		T37	21		T117	21
wkup[39]	364	1		T25	21		T138	42		T96	30
wkup[40]	380	1		T2	11		T28	42		T158	15
wkup[41]	424	1		T2	30		T37	41		T149	21
wkup[42]	288	1		T2	21		T12	21		T136	30
wkup[43]	291	1		T28	15		T16	21		T136	39
wkup[44]	204	1		T5	26		T35	8		T127	26
wkup[45]	274	1		T8	26		T92	35		T35	21
wkup[46]	432	1		T8	6		T10	21		T150	21
wkup[47]	333	1		T2	21		T44	21		T36	21
wkup[48]	259	1		T102	21		T147	21		T132	26
wkup[49]	383	1		T10	35		T16	26		T45	15
wkup[50]	300	1		T11	21		T28	21		T37	30
wkup[51]	361	1		T7	21		T8	21		T11	21
wkup[52]	302	1		T11	21		T149	21		T126	21
wkup[53]	363	1		T7	42		T35	21		T37	21
wkup[54]	262	1		T8	21		T150	20		T37	29
wkup[55]	363	1		T6	40		T7	21		T136	71
wkup[56]	303	1		T10	21		T28	21		T35	21
wkup[57]	236	1		T2	30		T8	30		T10	21
wkup[58]	342	1		T10	21		T11	21		T12	21
wkup[59]	236	1		T10	42		T37	30		T187	15
wkup[60]	173	1		T28	30		T136	21		T24	15
wkup[61]	323	1		T25	21		T190	15		T138	21
wkup[62]	380	1		T168	21		T36	26		T176	21
wkup[63]	461	1		T5	52		T10	21		T16	21
wkup_0	3813	1		T1	5		T2	44		T3	5