Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.41 99.33 93.67 100.00 98.40 99.51 51.54


Total test records in report: 424
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T30 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1853821370 Jun 06 12:57:34 PM PDT 24 Jun 06 12:57:39 PM PDT 24 8520140784 ps
T34 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2321241825 Jun 06 12:57:11 PM PDT 24 Jun 06 12:57:13 PM PDT 24 1422348549 ps
T286 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1773675016 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:46 PM PDT 24 481247412 ps
T31 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2728818127 Jun 06 12:57:27 PM PDT 24 Jun 06 12:57:28 PM PDT 24 444047417 ps
T82 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1942209505 Jun 06 12:57:37 PM PDT 24 Jun 06 12:57:40 PM PDT 24 2205357238 ps
T199 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2153802526 Jun 06 12:57:36 PM PDT 24 Jun 06 12:57:38 PM PDT 24 330154677 ps
T287 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2212223331 Jun 06 12:57:26 PM PDT 24 Jun 06 12:57:28 PM PDT 24 535923792 ps
T288 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1921596333 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:46 PM PDT 24 383012827 ps
T289 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3641603552 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:19 PM PDT 24 386986867 ps
T290 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.802664660 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:46 PM PDT 24 309357749 ps
T291 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.433772743 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:47 PM PDT 24 281736840 ps
T59 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1013983436 Jun 06 12:57:25 PM PDT 24 Jun 06 12:57:27 PM PDT 24 539295207 ps
T292 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2164937680 Jun 06 12:57:36 PM PDT 24 Jun 06 12:57:38 PM PDT 24 436339516 ps
T293 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4272491959 Jun 06 12:57:49 PM PDT 24 Jun 06 12:57:51 PM PDT 24 494466796 ps
T200 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3004434974 Jun 06 12:57:38 PM PDT 24 Jun 06 12:57:41 PM PDT 24 582259969 ps
T32 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.794187857 Jun 06 12:57:38 PM PDT 24 Jun 06 12:57:40 PM PDT 24 5020158608 ps
T197 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.535090454 Jun 06 12:57:28 PM PDT 24 Jun 06 12:57:30 PM PDT 24 365029716 ps
T294 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.730990981 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:21 PM PDT 24 1221931622 ps
T295 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.291084615 Jun 06 12:57:28 PM PDT 24 Jun 06 12:57:32 PM PDT 24 489004814 ps
T296 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3432562655 Jun 06 12:57:16 PM PDT 24 Jun 06 12:57:18 PM PDT 24 395637171 ps
T83 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1841947149 Jun 06 12:57:27 PM PDT 24 Jun 06 12:57:29 PM PDT 24 2725395297 ps
T198 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.540899277 Jun 06 12:57:35 PM PDT 24 Jun 06 12:57:37 PM PDT 24 409452327 ps
T297 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1766525171 Jun 06 12:57:43 PM PDT 24 Jun 06 12:57:45 PM PDT 24 308874371 ps
T298 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2973088402 Jun 06 12:57:25 PM PDT 24 Jun 06 12:57:27 PM PDT 24 512745749 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2765361132 Jun 06 12:57:11 PM PDT 24 Jun 06 12:57:13 PM PDT 24 644350527 ps
T84 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.784607093 Jun 06 12:57:43 PM PDT 24 Jun 06 12:57:46 PM PDT 24 2507483069 ps
T299 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1802642966 Jun 06 12:57:49 PM PDT 24 Jun 06 12:57:51 PM PDT 24 404798710 ps
T300 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3928081026 Jun 06 12:57:38 PM PDT 24 Jun 06 12:57:40 PM PDT 24 585510166 ps
T201 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.185792839 Jun 06 12:57:24 PM PDT 24 Jun 06 12:57:26 PM PDT 24 373959181 ps
T301 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2056407222 Jun 06 12:57:10 PM PDT 24 Jun 06 12:57:12 PM PDT 24 387268680 ps
T302 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1626052535 Jun 06 12:57:43 PM PDT 24 Jun 06 12:57:44 PM PDT 24 448729760 ps
T303 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2344428014 Jun 06 12:57:16 PM PDT 24 Jun 06 12:57:17 PM PDT 24 479051115 ps
T304 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2179232402 Jun 06 12:57:11 PM PDT 24 Jun 06 12:57:13 PM PDT 24 464613676 ps
T305 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1396371723 Jun 06 12:57:28 PM PDT 24 Jun 06 12:57:30 PM PDT 24 393345831 ps
T61 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.843955155 Jun 06 12:57:23 PM PDT 24 Jun 06 12:57:25 PM PDT 24 322916251 ps
T306 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.999621182 Jun 06 12:57:43 PM PDT 24 Jun 06 12:57:46 PM PDT 24 574076469 ps
T33 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.801552824 Jun 06 12:57:36 PM PDT 24 Jun 06 12:57:40 PM PDT 24 8250976333 ps
T307 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1110358055 Jun 06 12:57:45 PM PDT 24 Jun 06 12:57:47 PM PDT 24 372152020 ps
T85 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.93068977 Jun 06 12:57:39 PM PDT 24 Jun 06 12:57:45 PM PDT 24 2717636815 ps
T308 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3525970015 Jun 06 12:57:25 PM PDT 24 Jun 06 12:57:33 PM PDT 24 4246696493 ps
T86 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2371185046 Jun 06 12:57:37 PM PDT 24 Jun 06 12:57:39 PM PDT 24 512973326 ps
T309 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2830263273 Jun 06 12:57:08 PM PDT 24 Jun 06 12:57:10 PM PDT 24 388911303 ps
T310 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1316865839 Jun 06 12:57:18 PM PDT 24 Jun 06 12:57:22 PM PDT 24 498872428 ps
T311 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2461636622 Jun 06 12:57:47 PM PDT 24 Jun 06 12:57:49 PM PDT 24 375977246 ps
T192 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3706538142 Jun 06 12:57:22 PM PDT 24 Jun 06 12:57:31 PM PDT 24 4298881541 ps
T312 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3515441946 Jun 06 12:57:22 PM PDT 24 Jun 06 12:57:24 PM PDT 24 357993346 ps
T313 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2836196119 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:47 PM PDT 24 308285167 ps
T87 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.35867968 Jun 06 12:57:27 PM PDT 24 Jun 06 12:57:29 PM PDT 24 1127066903 ps
T314 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.840810215 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:47 PM PDT 24 488153397 ps
T315 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2449345904 Jun 06 12:57:10 PM PDT 24 Jun 06 12:57:12 PM PDT 24 426255162 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1934181431 Jun 06 12:57:16 PM PDT 24 Jun 06 12:57:19 PM PDT 24 476400936 ps
T88 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3853239709 Jun 06 12:57:36 PM PDT 24 Jun 06 12:57:40 PM PDT 24 1356260513 ps
T317 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2664871597 Jun 06 12:57:43 PM PDT 24 Jun 06 12:57:45 PM PDT 24 368223325 ps
T318 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1852935118 Jun 06 12:57:35 PM PDT 24 Jun 06 12:57:38 PM PDT 24 623481389 ps
T89 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3966015636 Jun 06 12:57:39 PM PDT 24 Jun 06 12:57:43 PM PDT 24 1565619709 ps
T193 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2454478608 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:23 PM PDT 24 8591417711 ps
T319 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1261432502 Jun 06 12:57:22 PM PDT 24 Jun 06 12:57:24 PM PDT 24 499681151 ps
T320 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1283434353 Jun 06 12:57:38 PM PDT 24 Jun 06 12:57:41 PM PDT 24 636898200 ps
T321 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.813700128 Jun 06 12:57:10 PM PDT 24 Jun 06 12:57:13 PM PDT 24 519494243 ps
T322 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1378904275 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:22 PM PDT 24 806004924 ps
T62 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.47115451 Jun 06 12:57:12 PM PDT 24 Jun 06 12:57:13 PM PDT 24 367941480 ps
T63 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2286331260 Jun 06 12:57:18 PM PDT 24 Jun 06 12:57:31 PM PDT 24 7114004916 ps
T323 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.634752004 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:20 PM PDT 24 516089533 ps
T324 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3602025917 Jun 06 12:57:26 PM PDT 24 Jun 06 12:57:28 PM PDT 24 685263711 ps
T325 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1722219702 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:46 PM PDT 24 365302675 ps
T194 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1700022058 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:49 PM PDT 24 4264571826 ps
T326 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3199842243 Jun 06 12:57:45 PM PDT 24 Jun 06 12:57:47 PM PDT 24 360546631 ps
T64 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3435895265 Jun 06 12:57:43 PM PDT 24 Jun 06 12:57:45 PM PDT 24 423223169 ps
T327 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2158492488 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:20 PM PDT 24 385666666 ps
T328 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.756865120 Jun 06 12:57:36 PM PDT 24 Jun 06 12:57:38 PM PDT 24 288694770 ps
T329 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3597722591 Jun 06 12:57:25 PM PDT 24 Jun 06 12:57:28 PM PDT 24 4367791149 ps
T330 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2105963425 Jun 06 12:57:22 PM PDT 24 Jun 06 12:57:25 PM PDT 24 620194376 ps
T331 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3681168640 Jun 06 12:57:47 PM PDT 24 Jun 06 12:57:49 PM PDT 24 373901173 ps
T332 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1934184073 Jun 06 12:57:29 PM PDT 24 Jun 06 12:57:37 PM PDT 24 8233834867 ps
T333 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2116375015 Jun 06 12:57:39 PM PDT 24 Jun 06 12:57:43 PM PDT 24 4400519809 ps
T334 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.170583573 Jun 06 12:57:26 PM PDT 24 Jun 06 12:57:32 PM PDT 24 1342963649 ps
T335 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.849259485 Jun 06 12:57:34 PM PDT 24 Jun 06 12:57:36 PM PDT 24 477138428 ps
T76 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.598021821 Jun 06 12:57:29 PM PDT 24 Jun 06 12:57:31 PM PDT 24 451631243 ps
T336 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1977676499 Jun 06 12:57:16 PM PDT 24 Jun 06 12:57:20 PM PDT 24 560881499 ps
T337 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1978640107 Jun 06 12:57:16 PM PDT 24 Jun 06 12:57:18 PM PDT 24 4372676494 ps
T77 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.486076642 Jun 06 12:57:23 PM PDT 24 Jun 06 12:57:45 PM PDT 24 13853999727 ps
T338 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1668240718 Jun 06 12:57:26 PM PDT 24 Jun 06 12:57:29 PM PDT 24 910321846 ps
T339 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1451607798 Jun 06 12:57:28 PM PDT 24 Jun 06 12:57:31 PM PDT 24 791650634 ps
T340 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.863516938 Jun 06 12:57:34 PM PDT 24 Jun 06 12:57:37 PM PDT 24 604612528 ps
T341 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1653007521 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:46 PM PDT 24 510865707 ps
T342 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1439967872 Jun 06 12:57:29 PM PDT 24 Jun 06 12:57:32 PM PDT 24 2569654075 ps
T343 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1383032125 Jun 06 12:57:28 PM PDT 24 Jun 06 12:57:30 PM PDT 24 464853530 ps
T344 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3973782111 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:19 PM PDT 24 355148326 ps
T345 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2255642035 Jun 06 12:57:16 PM PDT 24 Jun 06 12:57:19 PM PDT 24 1285781875 ps
T346 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4265951636 Jun 06 12:57:34 PM PDT 24 Jun 06 12:57:36 PM PDT 24 533902442 ps
T78 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3558913346 Jun 06 12:57:16 PM PDT 24 Jun 06 12:57:18 PM PDT 24 1177151153 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1404018651 Jun 06 12:57:10 PM PDT 24 Jun 06 12:57:12 PM PDT 24 340268040 ps
T348 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1718797851 Jun 06 12:57:47 PM PDT 24 Jun 06 12:57:48 PM PDT 24 443547000 ps
T349 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3791709189 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:19 PM PDT 24 365786620 ps
T350 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3863129926 Jun 06 12:57:57 PM PDT 24 Jun 06 12:57:58 PM PDT 24 297993794 ps
T351 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2178127463 Jun 06 12:57:15 PM PDT 24 Jun 06 12:57:17 PM PDT 24 406008416 ps
T352 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2915780080 Jun 06 12:57:28 PM PDT 24 Jun 06 12:57:30 PM PDT 24 487165520 ps
T353 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2605822290 Jun 06 12:57:28 PM PDT 24 Jun 06 12:57:31 PM PDT 24 575277631 ps
T354 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.4263774250 Jun 06 12:57:14 PM PDT 24 Jun 06 12:57:17 PM PDT 24 4617407557 ps
T355 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.807014521 Jun 06 12:57:33 PM PDT 24 Jun 06 12:57:35 PM PDT 24 2243145666 ps
T356 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2853014964 Jun 06 12:57:18 PM PDT 24 Jun 06 12:57:21 PM PDT 24 386460999 ps
T357 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.805986190 Jun 06 12:57:33 PM PDT 24 Jun 06 12:57:35 PM PDT 24 404220940 ps
T358 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2894376926 Jun 06 12:57:22 PM PDT 24 Jun 06 12:57:24 PM PDT 24 423516415 ps
T359 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.589245557 Jun 06 12:57:27 PM PDT 24 Jun 06 12:57:30 PM PDT 24 4740605534 ps
T360 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1196959179 Jun 06 12:57:34 PM PDT 24 Jun 06 12:57:37 PM PDT 24 1184494871 ps
T361 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2698230731 Jun 06 12:57:45 PM PDT 24 Jun 06 12:57:47 PM PDT 24 501855716 ps
T362 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2359552464 Jun 06 12:57:28 PM PDT 24 Jun 06 12:57:30 PM PDT 24 508767097 ps
T363 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3204382803 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:46 PM PDT 24 419812604 ps
T364 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.267290910 Jun 06 12:57:42 PM PDT 24 Jun 06 12:57:44 PM PDT 24 449005421 ps
T365 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.16675559 Jun 06 12:57:06 PM PDT 24 Jun 06 12:57:09 PM PDT 24 907301660 ps
T366 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2377553561 Jun 06 12:57:19 PM PDT 24 Jun 06 12:57:21 PM PDT 24 434978144 ps
T367 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3634312366 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:21 PM PDT 24 1049457029 ps
T368 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4276081889 Jun 06 12:57:27 PM PDT 24 Jun 06 12:57:29 PM PDT 24 604188762 ps
T369 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4133805196 Jun 06 12:57:28 PM PDT 24 Jun 06 12:57:41 PM PDT 24 8096988418 ps
T81 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2027864979 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:20 PM PDT 24 368191690 ps
T370 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3340680280 Jun 06 12:57:49 PM PDT 24 Jun 06 12:57:51 PM PDT 24 363852278 ps
T371 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3527362180 Jun 06 12:57:10 PM PDT 24 Jun 06 12:57:12 PM PDT 24 501383615 ps
T372 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1908308516 Jun 06 12:57:07 PM PDT 24 Jun 06 12:57:09 PM PDT 24 611529543 ps
T373 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2446375676 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:46 PM PDT 24 362150952 ps
T374 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3643282751 Jun 06 12:57:52 PM PDT 24 Jun 06 12:57:54 PM PDT 24 320467322 ps
T375 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.55549025 Jun 06 12:57:36 PM PDT 24 Jun 06 12:57:39 PM PDT 24 583066147 ps
T376 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2844750256 Jun 06 12:57:43 PM PDT 24 Jun 06 12:57:45 PM PDT 24 356059068 ps
T377 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3645709618 Jun 06 12:57:33 PM PDT 24 Jun 06 12:57:35 PM PDT 24 521327449 ps
T79 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4280256154 Jun 06 12:57:35 PM PDT 24 Jun 06 12:57:37 PM PDT 24 357537508 ps
T378 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3230588224 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:21 PM PDT 24 2142192877 ps
T379 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3646441795 Jun 06 12:57:28 PM PDT 24 Jun 06 12:57:31 PM PDT 24 459804601 ps
T380 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.589069786 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:19 PM PDT 24 295008598 ps
T381 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2156411517 Jun 06 12:57:33 PM PDT 24 Jun 06 12:57:35 PM PDT 24 562944410 ps
T382 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4252559332 Jun 06 12:57:09 PM PDT 24 Jun 06 12:57:11 PM PDT 24 373305182 ps
T383 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1994336099 Jun 06 12:57:16 PM PDT 24 Jun 06 12:57:18 PM PDT 24 506965122 ps
T80 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3816851882 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:40 PM PDT 24 13982273689 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2886456505 Jun 06 12:57:18 PM PDT 24 Jun 06 12:57:21 PM PDT 24 373984316 ps
T384 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.980781937 Jun 06 12:57:19 PM PDT 24 Jun 06 12:57:23 PM PDT 24 626777379 ps
T385 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2235257468 Jun 06 12:57:34 PM PDT 24 Jun 06 12:57:36 PM PDT 24 336934399 ps
T386 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1207350374 Jun 06 12:57:22 PM PDT 24 Jun 06 12:57:24 PM PDT 24 322823619 ps
T387 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1618498257 Jun 06 12:57:43 PM PDT 24 Jun 06 12:57:49 PM PDT 24 2615198168 ps
T388 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.705244532 Jun 06 12:57:24 PM PDT 24 Jun 06 12:57:33 PM PDT 24 6975815455 ps
T389 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4132035308 Jun 06 12:57:38 PM PDT 24 Jun 06 12:57:42 PM PDT 24 741347614 ps
T390 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2883154137 Jun 06 12:57:22 PM PDT 24 Jun 06 12:57:24 PM PDT 24 998962578 ps
T391 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.581249081 Jun 06 12:57:49 PM PDT 24 Jun 06 12:57:51 PM PDT 24 438846404 ps
T392 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3410707018 Jun 06 12:57:24 PM PDT 24 Jun 06 12:57:27 PM PDT 24 338457476 ps
T393 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2099737347 Jun 06 12:57:22 PM PDT 24 Jun 06 12:57:28 PM PDT 24 4626686019 ps
T394 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1774401995 Jun 06 12:57:18 PM PDT 24 Jun 06 12:57:22 PM PDT 24 8170644081 ps
T395 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2246497071 Jun 06 12:57:18 PM PDT 24 Jun 06 12:57:28 PM PDT 24 8185577772 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.822861845 Jun 06 12:57:18 PM PDT 24 Jun 06 12:57:21 PM PDT 24 469215289 ps
T397 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3645581641 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:46 PM PDT 24 475832001 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2418197811 Jun 06 12:57:18 PM PDT 24 Jun 06 12:57:23 PM PDT 24 2236214109 ps
T398 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2197747919 Jun 06 12:57:47 PM PDT 24 Jun 06 12:57:49 PM PDT 24 499418126 ps
T399 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3992350430 Jun 06 12:57:10 PM PDT 24 Jun 06 12:57:12 PM PDT 24 429396929 ps
T400 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4214596007 Jun 06 12:57:38 PM PDT 24 Jun 06 12:57:40 PM PDT 24 418152489 ps
T401 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3141661393 Jun 06 12:57:53 PM PDT 24 Jun 06 12:57:56 PM PDT 24 407787352 ps
T402 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.834595108 Jun 06 12:57:33 PM PDT 24 Jun 06 12:57:36 PM PDT 24 4393897133 ps
T403 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1289826135 Jun 06 12:57:45 PM PDT 24 Jun 06 12:57:47 PM PDT 24 492196159 ps
T404 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3962171613 Jun 06 12:57:24 PM PDT 24 Jun 06 12:57:25 PM PDT 24 353135213 ps
T405 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1529931944 Jun 06 12:57:47 PM PDT 24 Jun 06 12:57:49 PM PDT 24 314169615 ps
T406 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.137159999 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:19 PM PDT 24 384815177 ps
T407 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3999030300 Jun 06 12:57:40 PM PDT 24 Jun 06 12:57:42 PM PDT 24 365967539 ps
T408 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1985049480 Jun 06 12:57:23 PM PDT 24 Jun 06 12:57:26 PM PDT 24 359513819 ps
T409 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3821186320 Jun 06 12:57:15 PM PDT 24 Jun 06 12:57:17 PM PDT 24 1183652915 ps
T410 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1255796439 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:20 PM PDT 24 1250720053 ps
T411 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2318637895 Jun 06 12:57:28 PM PDT 24 Jun 06 12:57:30 PM PDT 24 444733905 ps
T412 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.272724223 Jun 06 12:57:16 PM PDT 24 Jun 06 12:57:18 PM PDT 24 413953326 ps
T413 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1001452975 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:48 PM PDT 24 834710715 ps
T414 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1466870052 Jun 06 12:57:34 PM PDT 24 Jun 06 12:57:38 PM PDT 24 492017788 ps
T415 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3657729642 Jun 06 12:57:48 PM PDT 24 Jun 06 12:57:50 PM PDT 24 280809029 ps
T416 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1439433937 Jun 06 12:57:36 PM PDT 24 Jun 06 12:57:38 PM PDT 24 360643862 ps
T417 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3302007853 Jun 06 12:57:16 PM PDT 24 Jun 06 12:57:19 PM PDT 24 498669459 ps
T418 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3777675886 Jun 06 12:57:16 PM PDT 24 Jun 06 12:57:18 PM PDT 24 503897912 ps
T419 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3298291615 Jun 06 12:57:34 PM PDT 24 Jun 06 12:57:43 PM PDT 24 4284341243 ps
T420 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3441437915 Jun 06 12:57:59 PM PDT 24 Jun 06 12:58:00 PM PDT 24 395524338 ps
T421 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2463419423 Jun 06 12:57:28 PM PDT 24 Jun 06 12:57:31 PM PDT 24 545857943 ps
T422 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1121567781 Jun 06 12:57:17 PM PDT 24 Jun 06 12:57:19 PM PDT 24 394108098 ps
T423 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.654604811 Jun 06 12:57:43 PM PDT 24 Jun 06 12:57:45 PM PDT 24 344457906 ps
T424 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3967872765 Jun 06 12:57:44 PM PDT 24 Jun 06 12:57:49 PM PDT 24 4182758544 ps

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1445837784
Short name T8
Test name
Test status
Simulation time 183749991271 ps
CPU time 384.04 seconds
Started Jun 06 12:54:57 PM PDT 24
Finished Jun 06 01:01:23 PM PDT 24
Peak memory 202604 kb
Host smart-4c32a10b-5d1e-40e1-bcda-705dd5881e8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445837784 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1445837784
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1853821370
Short name T30
Test name
Test status
Simulation time 8520140784 ps
CPU time 4.02 seconds
Started Jun 06 12:57:34 PM PDT 24
Finished Jun 06 12:57:39 PM PDT 24
Peak memory 198072 kb
Host smart-5381fa59-92c0-42f3-bfc6-16400b46b48d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853821370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1853821370
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3360365508
Short name T2
Test name
Test status
Simulation time 20350688160 ps
CPU time 147.45 seconds
Started Jun 06 12:54:53 PM PDT 24
Finished Jun 06 12:57:22 PM PDT 24
Peak memory 198724 kb
Host smart-dc5cc63e-86ef-4c98-8035-45b02d8068ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360365508 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3360365508
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1564741977
Short name T57
Test name
Test status
Simulation time 101778629959 ps
CPU time 312.84 seconds
Started Jun 06 12:55:12 PM PDT 24
Finished Jun 06 01:00:26 PM PDT 24
Peak memory 200048 kb
Host smart-39d3ec5d-79a2-4b49-9e5a-be168cff026f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564741977 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1564741977
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.4023810132
Short name T28
Test name
Test status
Simulation time 83092889661 ps
CPU time 316.09 seconds
Started Jun 06 12:55:04 PM PDT 24
Finished Jun 06 01:00:21 PM PDT 24
Peak memory 200900 kb
Host smart-3e56c20d-43d6-4024-a8a3-028a99f8eef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023810132 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.4023810132
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1520761013
Short name T112
Test name
Test status
Simulation time 756338168314 ps
CPU time 1231.98 seconds
Started Jun 06 12:54:46 PM PDT 24
Finished Jun 06 01:15:20 PM PDT 24
Peak memory 214984 kb
Host smart-e49dce1a-f655-4fe4-98e5-fe58deb98bc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520761013 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1520761013
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2856687397
Short name T136
Test name
Test status
Simulation time 412133071441 ps
CPU time 281.5 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 01:00:05 PM PDT 24
Peak memory 206804 kb
Host smart-ac156677-0cb2-443b-837a-1edede293391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856687397 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2856687397
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3465189148
Short name T127
Test name
Test status
Simulation time 36866672758 ps
CPU time 4.96 seconds
Started Jun 06 12:54:47 PM PDT 24
Finished Jun 06 12:54:53 PM PDT 24
Peak memory 184020 kb
Host smart-2b4bf798-b9a6-4fb7-bf04-a03d9445032b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465189148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3465189148
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2538230276
Short name T98
Test name
Test status
Simulation time 178761944820 ps
CPU time 329.33 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 01:00:36 PM PDT 24
Peak memory 214916 kb
Host smart-35cad49d-7919-4896-8879-93b4972901a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538230276 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2538230276
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.119221884
Short name T97
Test name
Test status
Simulation time 310333601414 ps
CPU time 558.22 seconds
Started Jun 06 12:54:57 PM PDT 24
Finished Jun 06 01:04:17 PM PDT 24
Peak memory 204452 kb
Host smart-ca5f5573-f45f-49d5-aa61-c6bd3e3e016a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119221884 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.119221884
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1353456299
Short name T37
Test name
Test status
Simulation time 111866495080 ps
CPU time 1029.99 seconds
Started Jun 06 12:55:21 PM PDT 24
Finished Jun 06 01:12:32 PM PDT 24
Peak memory 209156 kb
Host smart-9b8bf666-c21f-4821-8853-04d01f81fc98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353456299 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1353456299
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1303427674
Short name T58
Test name
Test status
Simulation time 60705201753 ps
CPU time 609.17 seconds
Started Jun 06 12:54:53 PM PDT 24
Finished Jun 06 01:05:03 PM PDT 24
Peak memory 203836 kb
Host smart-3dd59fb9-d26e-45f5-82a8-9f32d12e351e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303427674 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1303427674
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1249012462
Short name T18
Test name
Test status
Simulation time 8347191315 ps
CPU time 7.41 seconds
Started Jun 06 12:54:43 PM PDT 24
Finished Jun 06 12:54:52 PM PDT 24
Peak memory 215652 kb
Host smart-4fe3f96a-2c72-444c-8829-e58946742873
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249012462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1249012462
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1885262431
Short name T117
Test name
Test status
Simulation time 215639987211 ps
CPU time 733.51 seconds
Started Jun 06 12:55:12 PM PDT 24
Finished Jun 06 01:07:27 PM PDT 24
Peak memory 207044 kb
Host smart-84d4b910-ba2e-46c8-b394-488529f48b62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885262431 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1885262431
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.562303534
Short name T155
Test name
Test status
Simulation time 1311667057531 ps
CPU time 955.72 seconds
Started Jun 06 12:54:52 PM PDT 24
Finished Jun 06 01:10:50 PM PDT 24
Peak memory 210764 kb
Host smart-6caa00e9-ae41-4239-adf1-2d942cd1f331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562303534 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.562303534
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.432810556
Short name T133
Test name
Test status
Simulation time 105177009939 ps
CPU time 39.85 seconds
Started Jun 06 12:54:59 PM PDT 24
Finished Jun 06 12:55:40 PM PDT 24
Peak memory 184652 kb
Host smart-a36c5c50-5c54-409c-acba-8e19818b383d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432810556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.432810556
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3096044403
Short name T119
Test name
Test status
Simulation time 74555745540 ps
CPU time 280.55 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:59:36 PM PDT 24
Peak memory 208192 kb
Host smart-2cfea382-fe15-4ce8-a20f-450db728bd6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096044403 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3096044403
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3868866790
Short name T139
Test name
Test status
Simulation time 102025920406 ps
CPU time 10.77 seconds
Started Jun 06 12:55:21 PM PDT 24
Finished Jun 06 12:55:33 PM PDT 24
Peak memory 192928 kb
Host smart-9dfa939d-a63d-48ed-a372-d4cdee7de56a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868866790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3868866790
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.4246719144
Short name T103
Test name
Test status
Simulation time 248391446914 ps
CPU time 82.59 seconds
Started Jun 06 12:55:08 PM PDT 24
Finished Jun 06 12:56:31 PM PDT 24
Peak memory 192852 kb
Host smart-231ca42a-e309-438b-9400-90465923ca49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246719144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.4246719144
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2059587451
Short name T10
Test name
Test status
Simulation time 551315450948 ps
CPU time 288.86 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 01:00:13 PM PDT 24
Peak memory 206840 kb
Host smart-7b47a982-3101-4b0b-97db-df3df438cf67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059587451 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2059587451
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1118496081
Short name T94
Test name
Test status
Simulation time 32934023909 ps
CPU time 292.3 seconds
Started Jun 06 12:55:06 PM PDT 24
Finished Jun 06 12:59:59 PM PDT 24
Peak memory 198612 kb
Host smart-a8e6eccc-e0ff-473b-a277-ee4f3f4d08cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118496081 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1118496081
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2784336050
Short name T148
Test name
Test status
Simulation time 84583921920 ps
CPU time 167.6 seconds
Started Jun 06 12:55:23 PM PDT 24
Finished Jun 06 12:58:12 PM PDT 24
Peak memory 199384 kb
Host smart-9dd05a56-b7ad-4c00-801b-e3917fa83314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784336050 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2784336050
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2666132725
Short name T115
Test name
Test status
Simulation time 58556404881 ps
CPU time 19.47 seconds
Started Jun 06 12:54:58 PM PDT 24
Finished Jun 06 12:55:19 PM PDT 24
Peak memory 184132 kb
Host smart-374c4cfc-f669-411a-a1b5-aabeb3226eeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666132725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2666132725
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.112061042
Short name T142
Test name
Test status
Simulation time 278313969462 ps
CPU time 415.09 seconds
Started Jun 06 12:54:44 PM PDT 24
Finished Jun 06 01:01:40 PM PDT 24
Peak memory 210636 kb
Host smart-47d01dc7-b12b-47e5-8284-35ba8e2bfabe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112061042 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.112061042
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1336954457
Short name T114
Test name
Test status
Simulation time 65371637909 ps
CPU time 49.91 seconds
Started Jun 06 12:55:29 PM PDT 24
Finished Jun 06 12:56:20 PM PDT 24
Peak memory 192500 kb
Host smart-7a312ae7-ef0c-4f24-9665-fcf4a0eaa6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336954457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1336954457
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.589528841
Short name T73
Test name
Test status
Simulation time 70848561096 ps
CPU time 28.6 seconds
Started Jun 06 12:54:43 PM PDT 24
Finished Jun 06 12:55:13 PM PDT 24
Peak memory 192716 kb
Host smart-c7c41f46-a3fd-4108-af3e-816d0e845b04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589528841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.589528841
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2129486520
Short name T25
Test name
Test status
Simulation time 203962977242 ps
CPU time 204.14 seconds
Started Jun 06 12:55:16 PM PDT 24
Finished Jun 06 12:58:42 PM PDT 24
Peak memory 208396 kb
Host smart-76712356-9989-48f9-9509-9f91fa490058
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129486520 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2129486520
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.772432455
Short name T134
Test name
Test status
Simulation time 296732675444 ps
CPU time 419 seconds
Started Jun 06 12:55:24 PM PDT 24
Finished Jun 06 01:02:25 PM PDT 24
Peak memory 192132 kb
Host smart-c3e5818e-bdcc-47f2-8fde-4c5a8a336e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772432455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.772432455
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.4287943842
Short name T130
Test name
Test status
Simulation time 84377587747 ps
CPU time 32.96 seconds
Started Jun 06 12:55:13 PM PDT 24
Finished Jun 06 12:55:48 PM PDT 24
Peak memory 192540 kb
Host smart-215f00fe-e7d6-4416-85d9-48bf7278cfc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287943842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.4287943842
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.509136173
Short name T126
Test name
Test status
Simulation time 35138581946 ps
CPU time 29.14 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:55:15 PM PDT 24
Peak memory 191888 kb
Host smart-63ad0de4-6059-488c-b870-9aeb8be7f958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509136173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.509136173
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3910134797
Short name T141
Test name
Test status
Simulation time 29625695295 ps
CPU time 11.11 seconds
Started Jun 06 12:54:59 PM PDT 24
Finished Jun 06 12:55:11 PM PDT 24
Peak memory 184596 kb
Host smart-90d2f13f-e0e8-4903-9100-26634f441ac1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910134797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3910134797
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.859620673
Short name T144
Test name
Test status
Simulation time 596665505204 ps
CPU time 1070.53 seconds
Started Jun 06 12:55:07 PM PDT 24
Finished Jun 06 01:12:59 PM PDT 24
Peak memory 211964 kb
Host smart-30688f00-fe02-4c8d-99c1-6e7b60fad598
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859620673 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.859620673
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.917759905
Short name T104
Test name
Test status
Simulation time 147132494308 ps
CPU time 54.99 seconds
Started Jun 06 12:55:18 PM PDT 24
Finished Jun 06 12:56:15 PM PDT 24
Peak memory 191900 kb
Host smart-ffee8d09-7fbe-4478-a0d9-bc044b82ec22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917759905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.917759905
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2249760142
Short name T93
Test name
Test status
Simulation time 86077597075 ps
CPU time 888.72 seconds
Started Jun 06 12:55:24 PM PDT 24
Finished Jun 06 01:10:14 PM PDT 24
Peak memory 210492 kb
Host smart-f946b4ff-98a3-46f7-a234-ae00959a2138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249760142 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2249760142
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.4003064671
Short name T20
Test name
Test status
Simulation time 204592890821 ps
CPU time 440.05 seconds
Started Jun 06 12:54:57 PM PDT 24
Finished Jun 06 01:02:19 PM PDT 24
Peak memory 211128 kb
Host smart-07a0b568-5b1f-4581-9565-c1f9d153662d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003064671 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.4003064671
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.527450111
Short name T109
Test name
Test status
Simulation time 162031723313 ps
CPU time 39.4 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:45 PM PDT 24
Peak memory 191872 kb
Host smart-4a0d047c-d1c4-4bdd-b1a6-08bb538b0dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527450111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.527450111
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2490096541
Short name T107
Test name
Test status
Simulation time 159830326768 ps
CPU time 63.08 seconds
Started Jun 06 12:55:21 PM PDT 24
Finished Jun 06 12:56:25 PM PDT 24
Peak memory 192560 kb
Host smart-7a5cfb43-a057-47c6-947a-7f94442f2ca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490096541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2490096541
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3099602974
Short name T146
Test name
Test status
Simulation time 105584129693 ps
CPU time 205.84 seconds
Started Jun 06 12:54:49 PM PDT 24
Finished Jun 06 12:58:16 PM PDT 24
Peak memory 208364 kb
Host smart-defd4794-2715-405d-8f86-2c998b75154e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099602974 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3099602974
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2720661959
Short name T116
Test name
Test status
Simulation time 122210517817 ps
CPU time 181.47 seconds
Started Jun 06 12:55:16 PM PDT 24
Finished Jun 06 12:58:19 PM PDT 24
Peak memory 192984 kb
Host smart-6a7a8996-2864-45b9-90b9-9cfdc113e658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720661959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2720661959
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2990395244
Short name T169
Test name
Test status
Simulation time 195649659519 ps
CPU time 408.46 seconds
Started Jun 06 12:54:42 PM PDT 24
Finished Jun 06 01:01:31 PM PDT 24
Peak memory 206840 kb
Host smart-783d2dd0-00f6-431a-b9dd-7f8783b6a942
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990395244 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2990395244
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3055416943
Short name T110
Test name
Test status
Simulation time 107038319282 ps
CPU time 14.85 seconds
Started Jun 06 12:54:58 PM PDT 24
Finished Jun 06 12:55:14 PM PDT 24
Peak memory 192412 kb
Host smart-43951365-cf41-45f6-acb4-bd5c46124fd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055416943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3055416943
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2743580856
Short name T157
Test name
Test status
Simulation time 217613392874 ps
CPU time 323.78 seconds
Started Jun 06 12:55:11 PM PDT 24
Finished Jun 06 01:00:35 PM PDT 24
Peak memory 198216 kb
Host smart-27674ab1-5ec2-410e-9285-1ea704bc72cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743580856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2743580856
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3925029184
Short name T72
Test name
Test status
Simulation time 30386479853 ps
CPU time 212.44 seconds
Started Jun 06 12:54:48 PM PDT 24
Finished Jun 06 12:58:21 PM PDT 24
Peak memory 206816 kb
Host smart-bb09714b-1da7-4b00-9596-cb006a0258e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925029184 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3925029184
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3887527554
Short name T16
Test name
Test status
Simulation time 55064273732 ps
CPU time 39.4 seconds
Started Jun 06 12:54:55 PM PDT 24
Finished Jun 06 12:55:37 PM PDT 24
Peak memory 191900 kb
Host smart-4171ac60-013f-4f55-aee8-dfc3009688e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887527554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3887527554
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1470314062
Short name T149
Test name
Test status
Simulation time 111109595305 ps
CPU time 322.24 seconds
Started Jun 06 12:55:33 PM PDT 24
Finished Jun 06 01:00:57 PM PDT 24
Peak memory 201876 kb
Host smart-bfbef287-b568-474b-9858-02265c641a1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470314062 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1470314062
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1232755184
Short name T138
Test name
Test status
Simulation time 158268775431 ps
CPU time 298.88 seconds
Started Jun 06 12:54:55 PM PDT 24
Finished Jun 06 12:59:56 PM PDT 24
Peak memory 201680 kb
Host smart-cdba72b9-df55-4dde-af7d-c4252951b4e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232755184 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1232755184
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.4206373696
Short name T105
Test name
Test status
Simulation time 112013605317 ps
CPU time 157.73 seconds
Started Jun 06 12:54:44 PM PDT 24
Finished Jun 06 12:57:23 PM PDT 24
Peak memory 191860 kb
Host smart-81b84e4a-b9ee-4ef4-a047-22746191d913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206373696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.4206373696
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3099599690
Short name T159
Test name
Test status
Simulation time 204844861244 ps
CPU time 378.21 seconds
Started Jun 06 12:55:31 PM PDT 24
Finished Jun 06 01:01:51 PM PDT 24
Peak memory 210680 kb
Host smart-b70afbac-c1f4-41b8-835e-2f9699cb1bfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099599690 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3099599690
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3679900848
Short name T121
Test name
Test status
Simulation time 18136069674 ps
CPU time 6.25 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:55:02 PM PDT 24
Peak memory 191856 kb
Host smart-fabd00ca-a35c-4b06-95f0-67f2edffa8b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679900848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3679900848
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3240426721
Short name T164
Test name
Test status
Simulation time 409161686049 ps
CPU time 142.9 seconds
Started Jun 06 12:55:06 PM PDT 24
Finished Jun 06 12:57:30 PM PDT 24
Peak memory 198176 kb
Host smart-13b622f1-80c6-4878-b2fb-8c7fb0da8b81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240426721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3240426721
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.882882568
Short name T166
Test name
Test status
Simulation time 250000296105 ps
CPU time 580.78 seconds
Started Jun 06 12:55:04 PM PDT 24
Finished Jun 06 01:04:46 PM PDT 24
Peak memory 212800 kb
Host smart-0a87decd-2b7f-45f2-9019-14944f89b4d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882882568 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.882882568
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.992282713
Short name T75
Test name
Test status
Simulation time 135929919741 ps
CPU time 101.76 seconds
Started Jun 06 12:55:07 PM PDT 24
Finished Jun 06 12:56:50 PM PDT 24
Peak memory 191904 kb
Host smart-07a890a8-cf3f-42d8-9d4d-fe182dc03eed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992282713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.992282713
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.893398770
Short name T12
Test name
Test status
Simulation time 33233846984 ps
CPU time 11.73 seconds
Started Jun 06 12:55:19 PM PDT 24
Finished Jun 06 12:55:32 PM PDT 24
Peak memory 192844 kb
Host smart-672d8daf-2095-4144-8298-28ef8eddfeed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893398770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.893398770
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2292925275
Short name T102
Test name
Test status
Simulation time 106985795599 ps
CPU time 565.06 seconds
Started Jun 06 12:55:31 PM PDT 24
Finished Jun 06 01:04:57 PM PDT 24
Peak memory 206860 kb
Host smart-4a9f0b32-8aa7-4196-94a2-7c3fd448dadd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292925275 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2292925275
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2177153635
Short name T21
Test name
Test status
Simulation time 45260813011 ps
CPU time 13.41 seconds
Started Jun 06 12:55:35 PM PDT 24
Finished Jun 06 12:55:49 PM PDT 24
Peak memory 192372 kb
Host smart-e9ae0694-577e-4dca-a7f2-f50e849931a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177153635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2177153635
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.248671374
Short name T48
Test name
Test status
Simulation time 41350036912 ps
CPU time 198.52 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:58:25 PM PDT 24
Peak memory 198712 kb
Host smart-d5e31b90-3ad9-4a67-9ffc-01242707634d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248671374 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.248671374
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3141782553
Short name T99
Test name
Test status
Simulation time 456047568637 ps
CPU time 219.28 seconds
Started Jun 06 12:55:11 PM PDT 24
Finished Jun 06 12:58:51 PM PDT 24
Peak memory 200248 kb
Host smart-e5e4fdd2-0c49-4f9c-87c0-8d2ea900c7c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141782553 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3141782553
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1848129902
Short name T95
Test name
Test status
Simulation time 45535887871 ps
CPU time 340.29 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 01:00:27 PM PDT 24
Peak memory 206988 kb
Host smart-02fb7795-def6-4ecb-a87b-217de8177c5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848129902 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1848129902
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2765361132
Short name T60
Test name
Test status
Simulation time 644350527 ps
CPU time 1.76 seconds
Started Jun 06 12:57:11 PM PDT 24
Finished Jun 06 12:57:13 PM PDT 24
Peak memory 183644 kb
Host smart-31bc2dba-a383-4fd7-8dd9-4037202496b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765361132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2765361132
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2321241825
Short name T34
Test name
Test status
Simulation time 1422348549 ps
CPU time 0.8 seconds
Started Jun 06 12:57:11 PM PDT 24
Finished Jun 06 12:57:13 PM PDT 24
Peak memory 183772 kb
Host smart-4056d1cc-594d-4daa-98ad-4829eb4e68be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321241825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2321241825
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.710741508
Short name T147
Test name
Test status
Simulation time 383687227470 ps
CPU time 607.32 seconds
Started Jun 06 12:54:52 PM PDT 24
Finished Jun 06 01:05:01 PM PDT 24
Peak memory 184480 kb
Host smart-2d5fad13-ee2e-41aa-9db0-981f7b406f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710741508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.710741508
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.4098854638
Short name T36
Test name
Test status
Simulation time 149015067076 ps
CPU time 272.26 seconds
Started Jun 06 12:54:59 PM PDT 24
Finished Jun 06 12:59:33 PM PDT 24
Peak memory 209124 kb
Host smart-22648471-dcfd-4426-9b03-505307d2e3bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098854638 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.4098854638
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3637755550
Short name T100
Test name
Test status
Simulation time 305534412186 ps
CPU time 90.81 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:56:17 PM PDT 24
Peak memory 192928 kb
Host smart-1dabbe1c-174e-4b79-9782-47c90af14dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637755550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3637755550
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2003625879
Short name T35
Test name
Test status
Simulation time 172364820239 ps
CPU time 394.15 seconds
Started Jun 06 12:55:06 PM PDT 24
Finished Jun 06 01:01:41 PM PDT 24
Peak memory 202152 kb
Host smart-f9907f36-6649-4619-b869-8e5fc8ae6d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003625879 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2003625879
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1993420973
Short name T46
Test name
Test status
Simulation time 145842074072 ps
CPU time 485.01 seconds
Started Jun 06 12:55:02 PM PDT 24
Finished Jun 06 01:03:08 PM PDT 24
Peak memory 206824 kb
Host smart-7e925b9e-6329-49de-bbb9-5a8f65bf6774
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993420973 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1993420973
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.514114188
Short name T42
Test name
Test status
Simulation time 350603750 ps
CPU time 1.17 seconds
Started Jun 06 12:54:47 PM PDT 24
Finished Jun 06 12:54:49 PM PDT 24
Peak memory 196428 kb
Host smart-7efd9890-5d47-4e8a-9043-b6e869faaace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514114188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.514114188
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2909999862
Short name T176
Test name
Test status
Simulation time 27747296008 ps
CPU time 141.38 seconds
Started Jun 06 12:55:06 PM PDT 24
Finished Jun 06 12:57:28 PM PDT 24
Peak memory 198484 kb
Host smart-7c8ee38b-7cbb-4abe-9dd4-96cbe5dc47f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909999862 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2909999862
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2911875121
Short name T120
Test name
Test status
Simulation time 550724774 ps
CPU time 1.36 seconds
Started Jun 06 12:55:03 PM PDT 24
Finished Jun 06 12:55:06 PM PDT 24
Peak memory 196420 kb
Host smart-972fbd81-1092-4f83-b92b-4453809e95f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911875121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2911875121
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2442817041
Short name T160
Test name
Test status
Simulation time 354081875 ps
CPU time 1.33 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:07 PM PDT 24
Peak memory 196484 kb
Host smart-a739675f-5d93-4ade-ac0b-1a22917e2500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442817041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2442817041
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1730538885
Short name T19
Test name
Test status
Simulation time 348436862 ps
CPU time 1.01 seconds
Started Jun 06 12:55:03 PM PDT 24
Finished Jun 06 12:55:05 PM PDT 24
Peak memory 196388 kb
Host smart-99e2c979-566c-4e91-8ef7-ad822c3151e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730538885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1730538885
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1407115311
Short name T7
Test name
Test status
Simulation time 112111404293 ps
CPU time 384.71 seconds
Started Jun 06 12:55:21 PM PDT 24
Finished Jun 06 01:01:47 PM PDT 24
Peak memory 202192 kb
Host smart-d6df681b-0e1d-4a9f-8e5e-caad716bc164
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407115311 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1407115311
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1711359527
Short name T122
Test name
Test status
Simulation time 302472191952 ps
CPU time 495.72 seconds
Started Jun 06 12:55:30 PM PDT 24
Finished Jun 06 01:03:47 PM PDT 24
Peak memory 192272 kb
Host smart-aa4e4325-8621-48fe-b591-2e1757c469d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711359527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1711359527
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2741982976
Short name T5
Test name
Test status
Simulation time 456154625141 ps
CPU time 640.85 seconds
Started Jun 06 12:54:43 PM PDT 24
Finished Jun 06 01:05:25 PM PDT 24
Peak memory 206164 kb
Host smart-492caadb-1cde-4f22-9023-7cc28b30bab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741982976 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2741982976
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3170174313
Short name T135
Test name
Test status
Simulation time 584975775 ps
CPU time 1.59 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:54:57 PM PDT 24
Peak memory 196416 kb
Host smart-118f4f21-7ee8-4fc4-a658-79a2cd418267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170174313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3170174313
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2087577351
Short name T6
Test name
Test status
Simulation time 64195480545 ps
CPU time 24.24 seconds
Started Jun 06 12:55:02 PM PDT 24
Finished Jun 06 12:55:28 PM PDT 24
Peak memory 191852 kb
Host smart-8ccc86fa-d521-4c91-9ef0-1f2aeb6e845b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087577351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2087577351
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2011330090
Short name T96
Test name
Test status
Simulation time 70469312385 ps
CPU time 140.51 seconds
Started Jun 06 12:55:06 PM PDT 24
Finished Jun 06 12:57:28 PM PDT 24
Peak memory 206924 kb
Host smart-741949f5-bb01-4b54-bcf5-10ee58a0a344
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011330090 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2011330090
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1509381236
Short name T128
Test name
Test status
Simulation time 107156764704 ps
CPU time 171.4 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 12:58:15 PM PDT 24
Peak memory 191904 kb
Host smart-9da94f10-1c3e-4319-865c-705f85fc37cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509381236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1509381236
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.647561947
Short name T113
Test name
Test status
Simulation time 379534150 ps
CPU time 0.78 seconds
Started Jun 06 12:55:20 PM PDT 24
Finished Jun 06 12:55:22 PM PDT 24
Peak memory 196440 kb
Host smart-0b06731a-1acb-4a1c-9f86-d323fa0c0c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647561947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.647561947
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2638881635
Short name T108
Test name
Test status
Simulation time 168805896254 ps
CPU time 255.51 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:59:02 PM PDT 24
Peak memory 191860 kb
Host smart-258cf32c-738a-4635-8d12-0d8107e342f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638881635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2638881635
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.801475292
Short name T143
Test name
Test status
Simulation time 28712853547 ps
CPU time 39.38 seconds
Started Jun 06 12:54:46 PM PDT 24
Finished Jun 06 12:55:26 PM PDT 24
Peak memory 192008 kb
Host smart-306f87e9-83a1-431a-acb0-2891c12806aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801475292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.801475292
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.248228304
Short name T23
Test name
Test status
Simulation time 390923182 ps
CPU time 0.89 seconds
Started Jun 06 12:54:53 PM PDT 24
Finished Jun 06 12:54:55 PM PDT 24
Peak memory 196488 kb
Host smart-53d4dd54-0919-4cc2-942c-96f638e95279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248228304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.248228304
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1324825294
Short name T177
Test name
Test status
Simulation time 19057488389 ps
CPU time 7.62 seconds
Started Jun 06 12:55:02 PM PDT 24
Finished Jun 06 12:55:11 PM PDT 24
Peak memory 192992 kb
Host smart-6680dc22-2d91-421f-9e00-90d32d555a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324825294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1324825294
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2355828419
Short name T101
Test name
Test status
Simulation time 493105670 ps
CPU time 0.62 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:07 PM PDT 24
Peak memory 196416 kb
Host smart-068794e9-3148-440c-bb00-932b8febbbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355828419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2355828419
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2742863735
Short name T56
Test name
Test status
Simulation time 71622384114 ps
CPU time 668.96 seconds
Started Jun 06 12:55:07 PM PDT 24
Finished Jun 06 01:06:17 PM PDT 24
Peak memory 205084 kb
Host smart-8946508b-b55b-4efc-b8fb-0572a37ff014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742863735 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2742863735
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3592412180
Short name T106
Test name
Test status
Simulation time 551461606861 ps
CPU time 224.29 seconds
Started Jun 06 12:55:17 PM PDT 24
Finished Jun 06 12:59:03 PM PDT 24
Peak memory 191824 kb
Host smart-1caba9eb-e738-4d56-867b-d76f210747d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592412180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3592412180
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.407666375
Short name T67
Test name
Test status
Simulation time 55673580527 ps
CPU time 304.77 seconds
Started Jun 06 12:54:55 PM PDT 24
Finished Jun 06 01:00:02 PM PDT 24
Peak memory 206788 kb
Host smart-033fe402-a16c-46e8-a81c-40353f6432ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407666375 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.407666375
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1025287573
Short name T152
Test name
Test status
Simulation time 44392096599 ps
CPU time 468.28 seconds
Started Jun 06 12:54:52 PM PDT 24
Finished Jun 06 01:02:42 PM PDT 24
Peak memory 206820 kb
Host smart-7ae1d252-f643-4d16-92d4-f3aea1f02e44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025287573 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1025287573
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.572826583
Short name T137
Test name
Test status
Simulation time 578120049 ps
CPU time 0.79 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:54:57 PM PDT 24
Peak memory 196496 kb
Host smart-4424bb85-d9ce-42d8-8849-5bf3d99f9162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572826583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.572826583
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2107894025
Short name T129
Test name
Test status
Simulation time 360731489 ps
CPU time 0.75 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:06 PM PDT 24
Peak memory 196372 kb
Host smart-594f457e-0bbf-4c1b-949d-34d8bdd6874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107894025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2107894025
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.227197039
Short name T153
Test name
Test status
Simulation time 362008363 ps
CPU time 1.16 seconds
Started Jun 06 12:55:03 PM PDT 24
Finished Jun 06 12:55:05 PM PDT 24
Peak memory 196412 kb
Host smart-3bb743e6-316c-4140-a59d-31eb0915723c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227197039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.227197039
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1589336343
Short name T150
Test name
Test status
Simulation time 369740413528 ps
CPU time 550.62 seconds
Started Jun 06 12:55:07 PM PDT 24
Finished Jun 06 01:04:19 PM PDT 24
Peak memory 191832 kb
Host smart-996e148c-5f72-4e61-a944-c40cdcd38c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589336343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1589336343
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2723694604
Short name T43
Test name
Test status
Simulation time 424767608 ps
CPU time 1.17 seconds
Started Jun 06 12:55:17 PM PDT 24
Finished Jun 06 12:55:20 PM PDT 24
Peak memory 196436 kb
Host smart-8d8cf4a0-5d29-41ed-830f-b8f5f597ec9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723694604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2723694604
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1087403055
Short name T11
Test name
Test status
Simulation time 90274685088 ps
CPU time 204.82 seconds
Started Jun 06 12:55:30 PM PDT 24
Finished Jun 06 12:58:56 PM PDT 24
Peak memory 206836 kb
Host smart-2da6612e-0a3a-4bdb-9b3d-15f52d7bdd16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087403055 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1087403055
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1538147188
Short name T131
Test name
Test status
Simulation time 513612664 ps
CPU time 0.72 seconds
Started Jun 06 12:55:31 PM PDT 24
Finished Jun 06 12:55:32 PM PDT 24
Peak memory 196424 kb
Host smart-7fcaa7aa-17e6-4957-ae4a-252d5c1e5622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538147188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1538147188
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2056524948
Short name T123
Test name
Test status
Simulation time 427020180 ps
CPU time 0.88 seconds
Started Jun 06 12:55:06 PM PDT 24
Finished Jun 06 12:55:08 PM PDT 24
Peak memory 196440 kb
Host smart-6e5b5f5f-a096-4890-82ea-a2b838549e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056524948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2056524948
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1469891561
Short name T168
Test name
Test status
Simulation time 155594084423 ps
CPU time 240.15 seconds
Started Jun 06 12:55:13 PM PDT 24
Finished Jun 06 12:59:15 PM PDT 24
Peak memory 191856 kb
Host smart-8cfad5a7-7c10-431d-8765-5935de26bbf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469891561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1469891561
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3532423719
Short name T124
Test name
Test status
Simulation time 601487124 ps
CPU time 0.75 seconds
Started Jun 06 12:55:14 PM PDT 24
Finished Jun 06 12:55:17 PM PDT 24
Peak memory 196400 kb
Host smart-9ecfcb2f-5baa-4136-85c8-aad4f8063f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532423719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3532423719
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2450187742
Short name T92
Test name
Test status
Simulation time 83716412429 ps
CPU time 31.45 seconds
Started Jun 06 12:55:21 PM PDT 24
Finished Jun 06 12:55:54 PM PDT 24
Peak memory 192920 kb
Host smart-7de20cf5-b468-4e2d-944b-5d58bd8e0748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450187742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2450187742
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.514118505
Short name T44
Test name
Test status
Simulation time 63049595991 ps
CPU time 12.75 seconds
Started Jun 06 12:55:33 PM PDT 24
Finished Jun 06 12:55:46 PM PDT 24
Peak memory 191836 kb
Host smart-ce1d9234-707e-4d13-a70b-f71bee7fd71f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514118505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.514118505
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2827744085
Short name T171
Test name
Test status
Simulation time 278294666354 ps
CPU time 91.42 seconds
Started Jun 06 12:54:55 PM PDT 24
Finished Jun 06 12:56:28 PM PDT 24
Peak memory 192876 kb
Host smart-600a32fc-36cb-41b4-8508-e279992187ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827744085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2827744085
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1928333007
Short name T165
Test name
Test status
Simulation time 389116403 ps
CPU time 0.84 seconds
Started Jun 06 12:54:53 PM PDT 24
Finished Jun 06 12:54:56 PM PDT 24
Peak memory 196492 kb
Host smart-14bed8c7-79a7-40b1-80ad-5656d50e1547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928333007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1928333007
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3925139094
Short name T173
Test name
Test status
Simulation time 71815931216 ps
CPU time 71.26 seconds
Started Jun 06 12:55:06 PM PDT 24
Finished Jun 06 12:56:19 PM PDT 24
Peak memory 191824 kb
Host smart-45400b1a-7612-44bf-b477-d5bbfaef0a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925139094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3925139094
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.4108368293
Short name T161
Test name
Test status
Simulation time 49222144448 ps
CPU time 37.09 seconds
Started Jun 06 12:55:03 PM PDT 24
Finished Jun 06 12:55:41 PM PDT 24
Peak memory 192028 kb
Host smart-075f9520-10b5-4724-b241-34b2b13bf611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108368293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.4108368293
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2557635578
Short name T154
Test name
Test status
Simulation time 133161174504 ps
CPU time 230.01 seconds
Started Jun 06 12:54:46 PM PDT 24
Finished Jun 06 12:58:37 PM PDT 24
Peak memory 191884 kb
Host smart-9d57ada1-ac6a-4ccd-9a30-1624470830d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557635578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2557635578
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3715282071
Short name T180
Test name
Test status
Simulation time 31920085154 ps
CPU time 173.41 seconds
Started Jun 06 12:55:15 PM PDT 24
Finished Jun 06 12:58:11 PM PDT 24
Peak memory 206844 kb
Host smart-7f5c4be5-51b6-4ed1-92c7-b30d272088bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715282071 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3715282071
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.722874020
Short name T69
Test name
Test status
Simulation time 124343033082 ps
CPU time 52.67 seconds
Started Jun 06 12:55:23 PM PDT 24
Finished Jun 06 12:56:18 PM PDT 24
Peak memory 191804 kb
Host smart-bf5dd002-18fb-4d30-a728-bb2b8511e01b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722874020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.722874020
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2924410921
Short name T140
Test name
Test status
Simulation time 547658486 ps
CPU time 0.93 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:54:47 PM PDT 24
Peak memory 196376 kb
Host smart-21107d1c-ac63-44f9-a8fd-5c63be1f9e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924410921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2924410921
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2534396705
Short name T156
Test name
Test status
Simulation time 505615290 ps
CPU time 0.94 seconds
Started Jun 06 12:54:44 PM PDT 24
Finished Jun 06 12:54:46 PM PDT 24
Peak memory 196336 kb
Host smart-37cf2905-122c-48a9-9ae2-f12ed94ba8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534396705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2534396705
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2942138010
Short name T125
Test name
Test status
Simulation time 531956710 ps
CPU time 1.29 seconds
Started Jun 06 12:55:12 PM PDT 24
Finished Jun 06 12:55:15 PM PDT 24
Peak memory 196400 kb
Host smart-30a542f4-555b-4056-91a8-60ba7f559b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942138010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2942138010
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.491043668
Short name T162
Test name
Test status
Simulation time 509236695 ps
CPU time 0.79 seconds
Started Jun 06 12:55:21 PM PDT 24
Finished Jun 06 12:55:24 PM PDT 24
Peak memory 196428 kb
Host smart-64a2502a-d65b-4ae5-978d-b56f85c344e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491043668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.491043668
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1431964272
Short name T151
Test name
Test status
Simulation time 363481512 ps
CPU time 0.66 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:54:47 PM PDT 24
Peak memory 196380 kb
Host smart-b0a0ea72-aefc-48d1-854a-26ec1a60186f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431964272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1431964272
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1606196943
Short name T145
Test name
Test status
Simulation time 620447506 ps
CPU time 0.78 seconds
Started Jun 06 12:55:24 PM PDT 24
Finished Jun 06 12:55:26 PM PDT 24
Peak memory 196440 kb
Host smart-ade5618f-1476-4d79-a676-02414c84031d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606196943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1606196943
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.907590669
Short name T158
Test name
Test status
Simulation time 562645415 ps
CPU time 0.7 seconds
Started Jun 06 12:55:24 PM PDT 24
Finished Jun 06 12:55:26 PM PDT 24
Peak memory 196232 kb
Host smart-a7799696-0278-49a6-a6f8-71f60063519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907590669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.907590669
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2646756154
Short name T51
Test name
Test status
Simulation time 438229549 ps
CPU time 0.79 seconds
Started Jun 06 12:54:48 PM PDT 24
Finished Jun 06 12:54:50 PM PDT 24
Peak memory 196492 kb
Host smart-334e5433-d060-4dcd-9b37-588282d51530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646756154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2646756154
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1985632334
Short name T27
Test name
Test status
Simulation time 439211444 ps
CPU time 0.98 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:54:57 PM PDT 24
Peak memory 195708 kb
Host smart-a0ccdfcf-0393-4474-a63e-66a3f5b65be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985632334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1985632334
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1700022058
Short name T194
Test name
Test status
Simulation time 4264571826 ps
CPU time 4.36 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:49 PM PDT 24
Peak memory 197708 kb
Host smart-0f5d8486-c4b4-410d-9076-6be5af2834d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700022058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1700022058
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2575961228
Short name T22
Test name
Test status
Simulation time 512755971024 ps
CPU time 170.5 seconds
Started Jun 06 12:54:57 PM PDT 24
Finished Jun 06 12:57:49 PM PDT 24
Peak memory 191812 kb
Host smart-bdff0884-4e9a-4310-988b-4e22830a8ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575961228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2575961228
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2883477272
Short name T170
Test name
Test status
Simulation time 422613859 ps
CPU time 1.15 seconds
Started Jun 06 12:54:58 PM PDT 24
Finished Jun 06 12:55:00 PM PDT 24
Peak memory 196440 kb
Host smart-14bfa29a-2a68-4b83-8e2b-31fcc941f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883477272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2883477272
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3011184502
Short name T90
Test name
Test status
Simulation time 542750371 ps
CPU time 0.96 seconds
Started Jun 06 12:54:44 PM PDT 24
Finished Jun 06 12:54:46 PM PDT 24
Peak memory 196312 kb
Host smart-ce3b042c-9e05-4305-88c5-d4f875aacef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011184502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3011184502
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.585859420
Short name T118
Test name
Test status
Simulation time 363415477 ps
CPU time 1.21 seconds
Started Jun 06 12:55:04 PM PDT 24
Finished Jun 06 12:55:06 PM PDT 24
Peak memory 196476 kb
Host smart-18d6ac82-27c5-4dac-b94b-3dd8ac8097d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585859420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.585859420
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.355793180
Short name T24
Test name
Test status
Simulation time 546838143 ps
CPU time 0.86 seconds
Started Jun 06 12:55:03 PM PDT 24
Finished Jun 06 12:55:05 PM PDT 24
Peak memory 196508 kb
Host smart-96dbaab7-446d-474f-b164-eb25aeca61e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355793180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.355793180
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1241028828
Short name T38
Test name
Test status
Simulation time 362277888 ps
CPU time 1.08 seconds
Started Jun 06 12:55:08 PM PDT 24
Finished Jun 06 12:55:09 PM PDT 24
Peak memory 196368 kb
Host smart-ef76f771-2f4d-4dae-a139-722c785edccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241028828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1241028828
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1099163550
Short name T172
Test name
Test status
Simulation time 491620577 ps
CPU time 0.77 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:54:47 PM PDT 24
Peak memory 196356 kb
Host smart-ee414945-41df-47df-a1a6-baafec6b7b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099163550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1099163550
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2833552065
Short name T183
Test name
Test status
Simulation time 389708393 ps
CPU time 1.23 seconds
Started Jun 06 12:55:13 PM PDT 24
Finished Jun 06 12:55:16 PM PDT 24
Peak memory 196360 kb
Host smart-26cf48b9-b1e7-4e72-b568-39f8c763d33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833552065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2833552065
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2422322058
Short name T185
Test name
Test status
Simulation time 628614558 ps
CPU time 1.6 seconds
Started Jun 06 12:55:13 PM PDT 24
Finished Jun 06 12:55:16 PM PDT 24
Peak memory 196304 kb
Host smart-8064dbb5-e687-4b60-8ea8-bf17e2303df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422322058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2422322058
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3641337101
Short name T191
Test name
Test status
Simulation time 479371861 ps
CPU time 0.78 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 12:55:25 PM PDT 24
Peak memory 196384 kb
Host smart-d6912656-b4a7-43f7-9eb4-474057e8b7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641337101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3641337101
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1665043161
Short name T132
Test name
Test status
Simulation time 102161874329 ps
CPU time 149.73 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 12:57:53 PM PDT 24
Peak memory 191892 kb
Host smart-6c39558c-2110-4984-90fd-fcb915e72628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665043161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1665043161
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2762038392
Short name T163
Test name
Test status
Simulation time 366921246 ps
CPU time 1.2 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 12:55:26 PM PDT 24
Peak memory 196464 kb
Host smart-82883648-766b-4cb8-a4af-b4ab2ce96e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762038392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2762038392
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1270383192
Short name T45
Test name
Test status
Simulation time 374163981 ps
CPU time 0.94 seconds
Started Jun 06 12:55:31 PM PDT 24
Finished Jun 06 12:55:33 PM PDT 24
Peak memory 196432 kb
Host smart-565f9d41-4f9e-47ef-ad7f-7a9a64feb8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270383192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1270383192
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1658646693
Short name T111
Test name
Test status
Simulation time 522747217 ps
CPU time 1 seconds
Started Jun 06 12:54:49 PM PDT 24
Finished Jun 06 12:54:51 PM PDT 24
Peak memory 196392 kb
Host smart-c4df6f3d-b3ea-465e-b4aa-1a1eb598a956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658646693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1658646693
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3180058936
Short name T184
Test name
Test status
Simulation time 154786018809 ps
CPU time 120.23 seconds
Started Jun 06 12:54:55 PM PDT 24
Finished Jun 06 12:56:57 PM PDT 24
Peak memory 192532 kb
Host smart-5045761d-2e75-4a67-ade9-0e9e30d6c932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180058936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3180058936
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2431361589
Short name T182
Test name
Test status
Simulation time 447089760 ps
CPU time 0.75 seconds
Started Jun 06 12:54:53 PM PDT 24
Finished Jun 06 12:54:56 PM PDT 24
Peak memory 196472 kb
Host smart-a7351acf-42e3-4f5f-bdad-159c2faf85dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431361589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2431361589
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1718117960
Short name T178
Test name
Test status
Simulation time 456538087 ps
CPU time 1.29 seconds
Started Jun 06 12:54:58 PM PDT 24
Finished Jun 06 12:55:00 PM PDT 24
Peak memory 196368 kb
Host smart-511d1d59-2e5d-4928-90e4-d0d552526c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718117960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1718117960
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.706782509
Short name T190
Test name
Test status
Simulation time 506570901 ps
CPU time 1.31 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:08 PM PDT 24
Peak memory 196332 kb
Host smart-26054016-7ced-4333-9d45-8896519d4105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706782509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.706782509
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1106083108
Short name T179
Test name
Test status
Simulation time 549413123 ps
CPU time 0.97 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:54:56 PM PDT 24
Peak memory 196380 kb
Host smart-6bd6c356-55de-4434-a631-fbe2ad4ca4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106083108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1106083108
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.817766997
Short name T175
Test name
Test status
Simulation time 558707249 ps
CPU time 1.48 seconds
Started Jun 06 12:54:58 PM PDT 24
Finished Jun 06 12:55:01 PM PDT 24
Peak memory 196360 kb
Host smart-24dff1fd-eb6c-49ad-8fa1-dd0767df7d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817766997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.817766997
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.698209017
Short name T167
Test name
Test status
Simulation time 220090197060 ps
CPU time 156.02 seconds
Started Jun 06 12:55:08 PM PDT 24
Finished Jun 06 12:57:44 PM PDT 24
Peak memory 191832 kb
Host smart-adba3228-e4e3-42b2-8fb6-bdb022dab30b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698209017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.698209017
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1551881231
Short name T189
Test name
Test status
Simulation time 371925279 ps
CPU time 0.94 seconds
Started Jun 06 12:55:03 PM PDT 24
Finished Jun 06 12:55:05 PM PDT 24
Peak memory 196372 kb
Host smart-f383c421-4314-451b-a199-82fd071fcf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551881231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1551881231
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1061962673
Short name T187
Test name
Test status
Simulation time 634747166 ps
CPU time 0.83 seconds
Started Jun 06 12:55:08 PM PDT 24
Finished Jun 06 12:55:09 PM PDT 24
Peak memory 196408 kb
Host smart-aa6e5c08-3d2b-436b-82e3-b1a5c9e7633d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061962673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1061962673
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1174218565
Short name T174
Test name
Test status
Simulation time 387136753 ps
CPU time 1.24 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 12:55:25 PM PDT 24
Peak memory 196296 kb
Host smart-1aef238a-1a38-4a35-9f27-128beb9d80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174218565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1174218565
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1908308516
Short name T372
Test name
Test status
Simulation time 611529543 ps
CPU time 0.93 seconds
Started Jun 06 12:57:07 PM PDT 24
Finished Jun 06 12:57:09 PM PDT 24
Peak memory 183528 kb
Host smart-70a61df4-46b3-42e2-ba77-9072993ff8cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908308516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1908308516
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.705244532
Short name T388
Test name
Test status
Simulation time 6975815455 ps
CPU time 8.58 seconds
Started Jun 06 12:57:24 PM PDT 24
Finished Jun 06 12:57:33 PM PDT 24
Peak memory 191908 kb
Host smart-14688f2a-1c12-4d5a-8a85-51c8ba87d1eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705244532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.705244532
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2105963425
Short name T330
Test name
Test status
Simulation time 620194376 ps
CPU time 1.51 seconds
Started Jun 06 12:57:22 PM PDT 24
Finished Jun 06 12:57:25 PM PDT 24
Peak memory 183584 kb
Host smart-990ec24d-0477-4480-b54e-020a9b97e6b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105963425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2105963425
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3527362180
Short name T371
Test name
Test status
Simulation time 501383615 ps
CPU time 0.83 seconds
Started Jun 06 12:57:10 PM PDT 24
Finished Jun 06 12:57:12 PM PDT 24
Peak memory 195252 kb
Host smart-90296a92-2d17-4eef-a533-817110270d01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527362180 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3527362180
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.47115451
Short name T62
Test name
Test status
Simulation time 367941480 ps
CPU time 0.67 seconds
Started Jun 06 12:57:12 PM PDT 24
Finished Jun 06 12:57:13 PM PDT 24
Peak memory 193032 kb
Host smart-a7580122-8d8f-4fa3-8621-aec97a7578f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47115451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.47115451
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2830263273
Short name T309
Test name
Test status
Simulation time 388911303 ps
CPU time 1.11 seconds
Started Jun 06 12:57:08 PM PDT 24
Finished Jun 06 12:57:10 PM PDT 24
Peak memory 183520 kb
Host smart-de6043fa-bbf3-4412-9f93-1de153b807b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830263273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2830263273
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4252559332
Short name T382
Test name
Test status
Simulation time 373305182 ps
CPU time 0.63 seconds
Started Jun 06 12:57:09 PM PDT 24
Finished Jun 06 12:57:11 PM PDT 24
Peak memory 183464 kb
Host smart-9b0d90c7-8501-40d1-ba78-41091b5a49c1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252559332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.4252559332
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2449345904
Short name T315
Test name
Test status
Simulation time 426255162 ps
CPU time 0.61 seconds
Started Jun 06 12:57:10 PM PDT 24
Finished Jun 06 12:57:12 PM PDT 24
Peak memory 183576 kb
Host smart-31275b8d-d718-4b6b-b96b-44fe248eba3f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449345904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2449345904
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.16675559
Short name T365
Test name
Test status
Simulation time 907301660 ps
CPU time 1.89 seconds
Started Jun 06 12:57:06 PM PDT 24
Finished Jun 06 12:57:09 PM PDT 24
Peak memory 193420 kb
Host smart-bb94a720-0d07-4a40-b1dc-d27f90d7a9cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16675559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_same_csr_outstanding.16675559
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2179232402
Short name T304
Test name
Test status
Simulation time 464613676 ps
CPU time 1.44 seconds
Started Jun 06 12:57:11 PM PDT 24
Finished Jun 06 12:57:13 PM PDT 24
Peak memory 198356 kb
Host smart-da156f16-ef3d-476d-bee5-ce67a87c5431
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179232402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2179232402
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3706538142
Short name T192
Test name
Test status
Simulation time 4298881541 ps
CPU time 7.69 seconds
Started Jun 06 12:57:22 PM PDT 24
Finished Jun 06 12:57:31 PM PDT 24
Peak memory 197604 kb
Host smart-81ca92d7-d8b8-4480-a6fd-598730086f45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706538142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3706538142
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.486076642
Short name T77
Test name
Test status
Simulation time 13853999727 ps
CPU time 20.64 seconds
Started Jun 06 12:57:23 PM PDT 24
Finished Jun 06 12:57:45 PM PDT 24
Peak memory 194248 kb
Host smart-79efc285-0c49-4d8b-bb0b-020ea5131dad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486076642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.486076642
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2883154137
Short name T390
Test name
Test status
Simulation time 998962578 ps
CPU time 0.98 seconds
Started Jun 06 12:57:22 PM PDT 24
Finished Jun 06 12:57:24 PM PDT 24
Peak memory 192716 kb
Host smart-9a49cf43-975d-4923-b122-aa504c62474c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883154137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2883154137
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3992350430
Short name T399
Test name
Test status
Simulation time 429396929 ps
CPU time 1.25 seconds
Started Jun 06 12:57:10 PM PDT 24
Finished Jun 06 12:57:12 PM PDT 24
Peak memory 195308 kb
Host smart-3715674e-c22c-4db0-ad76-2e31f85cc3de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992350430 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3992350430
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.843955155
Short name T61
Test name
Test status
Simulation time 322916251 ps
CPU time 0.99 seconds
Started Jun 06 12:57:23 PM PDT 24
Finished Jun 06 12:57:25 PM PDT 24
Peak memory 183588 kb
Host smart-16cd772a-6e59-4c21-a6e2-582e4e506dc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843955155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.843955155
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2056407222
Short name T301
Test name
Test status
Simulation time 387268680 ps
CPU time 0.82 seconds
Started Jun 06 12:57:10 PM PDT 24
Finished Jun 06 12:57:12 PM PDT 24
Peak memory 183524 kb
Host smart-e0116ebc-c0b4-4bbf-8a3e-1cae8a548a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056407222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2056407222
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1404018651
Short name T347
Test name
Test status
Simulation time 340268040 ps
CPU time 1.02 seconds
Started Jun 06 12:57:10 PM PDT 24
Finished Jun 06 12:57:12 PM PDT 24
Peak memory 183432 kb
Host smart-2c7bf91e-429f-4e69-8e21-411c7f7a5f83
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404018651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1404018651
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3962171613
Short name T404
Test name
Test status
Simulation time 353135213 ps
CPU time 0.8 seconds
Started Jun 06 12:57:24 PM PDT 24
Finished Jun 06 12:57:25 PM PDT 24
Peak memory 183424 kb
Host smart-3a88f3fd-987e-4498-85e4-bea2a80bda4c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962171613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3962171613
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1985049480
Short name T408
Test name
Test status
Simulation time 359513819 ps
CPU time 1.67 seconds
Started Jun 06 12:57:23 PM PDT 24
Finished Jun 06 12:57:26 PM PDT 24
Peak memory 198232 kb
Host smart-784669b5-18fb-40b8-80ef-303d96aace8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985049480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1985049480
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2099737347
Short name T393
Test name
Test status
Simulation time 4626686019 ps
CPU time 4.61 seconds
Started Jun 06 12:57:22 PM PDT 24
Finished Jun 06 12:57:28 PM PDT 24
Peak memory 197276 kb
Host smart-fabe44dd-d41e-45c0-8a78-8af3588b9a51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099737347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2099737347
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1383032125
Short name T343
Test name
Test status
Simulation time 464853530 ps
CPU time 0.81 seconds
Started Jun 06 12:57:28 PM PDT 24
Finished Jun 06 12:57:30 PM PDT 24
Peak memory 195580 kb
Host smart-6d99d023-7972-46b8-bf54-87371e915875
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383032125 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1383032125
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2463419423
Short name T421
Test name
Test status
Simulation time 545857943 ps
CPU time 1.5 seconds
Started Jun 06 12:57:28 PM PDT 24
Finished Jun 06 12:57:31 PM PDT 24
Peak memory 192844 kb
Host smart-ab2d8f2a-7785-4cce-b0cb-626fd8c01644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463419423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2463419423
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2973088402
Short name T298
Test name
Test status
Simulation time 512745749 ps
CPU time 0.73 seconds
Started Jun 06 12:57:25 PM PDT 24
Finished Jun 06 12:57:27 PM PDT 24
Peak memory 183580 kb
Host smart-4b005387-5141-435f-ba30-011e54941eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973088402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2973088402
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.170583573
Short name T334
Test name
Test status
Simulation time 1342963649 ps
CPU time 5.05 seconds
Started Jun 06 12:57:26 PM PDT 24
Finished Jun 06 12:57:32 PM PDT 24
Peak memory 193604 kb
Host smart-aecc33e9-ed59-48ab-beb6-5792b7091624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170583573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.170583573
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1668240718
Short name T338
Test name
Test status
Simulation time 910321846 ps
CPU time 1.92 seconds
Started Jun 06 12:57:26 PM PDT 24
Finished Jun 06 12:57:29 PM PDT 24
Peak memory 198328 kb
Host smart-76d0d879-ada8-4861-baf4-69dd862eb4af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668240718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1668240718
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1934184073
Short name T332
Test name
Test status
Simulation time 8233834867 ps
CPU time 7.29 seconds
Started Jun 06 12:57:29 PM PDT 24
Finished Jun 06 12:57:37 PM PDT 24
Peak memory 197924 kb
Host smart-f0a21ac4-574d-474f-83b1-970f90422e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934184073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1934184073
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2605822290
Short name T353
Test name
Test status
Simulation time 575277631 ps
CPU time 1.49 seconds
Started Jun 06 12:57:28 PM PDT 24
Finished Jun 06 12:57:31 PM PDT 24
Peak memory 196112 kb
Host smart-50a52d29-2b60-4c67-9a68-4cdb746a2ba6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605822290 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2605822290
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1013983436
Short name T59
Test name
Test status
Simulation time 539295207 ps
CPU time 1.41 seconds
Started Jun 06 12:57:25 PM PDT 24
Finished Jun 06 12:57:27 PM PDT 24
Peak memory 193004 kb
Host smart-abd22198-fc32-42d2-9d54-9219fcecbf3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013983436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1013983436
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2915780080
Short name T352
Test name
Test status
Simulation time 487165520 ps
CPU time 0.76 seconds
Started Jun 06 12:57:28 PM PDT 24
Finished Jun 06 12:57:30 PM PDT 24
Peak memory 183572 kb
Host smart-61210ca8-9c4f-4fd7-a544-579ddfcf7ba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915780080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2915780080
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1451607798
Short name T339
Test name
Test status
Simulation time 791650634 ps
CPU time 1.08 seconds
Started Jun 06 12:57:28 PM PDT 24
Finished Jun 06 12:57:31 PM PDT 24
Peak memory 192872 kb
Host smart-1dbfb6e0-ab0e-4dea-9319-c5e6b80ff1f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451607798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1451607798
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3602025917
Short name T324
Test name
Test status
Simulation time 685263711 ps
CPU time 1.46 seconds
Started Jun 06 12:57:26 PM PDT 24
Finished Jun 06 12:57:28 PM PDT 24
Peak memory 198316 kb
Host smart-f82afa72-86ab-4034-b48f-f04819638f02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602025917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3602025917
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4133805196
Short name T369
Test name
Test status
Simulation time 8096988418 ps
CPU time 11.52 seconds
Started Jun 06 12:57:28 PM PDT 24
Finished Jun 06 12:57:41 PM PDT 24
Peak memory 197944 kb
Host smart-2e016a72-4dc3-4711-89bd-e66ffe45939a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133805196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.4133805196
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2164937680
Short name T292
Test name
Test status
Simulation time 436339516 ps
CPU time 0.86 seconds
Started Jun 06 12:57:36 PM PDT 24
Finished Jun 06 12:57:38 PM PDT 24
Peak memory 196592 kb
Host smart-8e4dc280-dd71-44ae-905b-d3d96779f0f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164937680 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2164937680
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4214596007
Short name T400
Test name
Test status
Simulation time 418152489 ps
CPU time 0.73 seconds
Started Jun 06 12:57:38 PM PDT 24
Finished Jun 06 12:57:40 PM PDT 24
Peak memory 192896 kb
Host smart-ddb47f29-d2fc-4818-a2c7-d5acdf630891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214596007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.4214596007
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.805986190
Short name T357
Test name
Test status
Simulation time 404220940 ps
CPU time 0.69 seconds
Started Jun 06 12:57:33 PM PDT 24
Finished Jun 06 12:57:35 PM PDT 24
Peak memory 183520 kb
Host smart-70a27fa4-e7e5-4e3f-b9b5-e467e592d0c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805986190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.805986190
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.807014521
Short name T355
Test name
Test status
Simulation time 2243145666 ps
CPU time 1.55 seconds
Started Jun 06 12:57:33 PM PDT 24
Finished Jun 06 12:57:35 PM PDT 24
Peak memory 193932 kb
Host smart-8c509011-915c-464d-95f6-0c9ec0a021ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807014521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.807014521
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.291084615
Short name T295
Test name
Test status
Simulation time 489004814 ps
CPU time 2.3 seconds
Started Jun 06 12:57:28 PM PDT 24
Finished Jun 06 12:57:32 PM PDT 24
Peak memory 198336 kb
Host smart-49c19411-a449-487c-987b-48f9fa0b7764
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291084615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.291084615
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.794187857
Short name T32
Test name
Test status
Simulation time 5020158608 ps
CPU time 1.78 seconds
Started Jun 06 12:57:38 PM PDT 24
Finished Jun 06 12:57:40 PM PDT 24
Peak memory 196572 kb
Host smart-26fec7e5-6ab6-4d96-9bbc-e77f651abb79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794187857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.794187857
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3004434974
Short name T200
Test name
Test status
Simulation time 582259969 ps
CPU time 1.2 seconds
Started Jun 06 12:57:38 PM PDT 24
Finished Jun 06 12:57:41 PM PDT 24
Peak memory 196212 kb
Host smart-a137d042-0d0a-4e73-be4d-d712758eecf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004434974 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3004434974
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4280256154
Short name T79
Test name
Test status
Simulation time 357537508 ps
CPU time 0.96 seconds
Started Jun 06 12:57:35 PM PDT 24
Finished Jun 06 12:57:37 PM PDT 24
Peak memory 183668 kb
Host smart-adbe7381-a8f9-4a55-8769-fa120d452c9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280256154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.4280256154
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2235257468
Short name T385
Test name
Test status
Simulation time 336934399 ps
CPU time 1.05 seconds
Started Jun 06 12:57:34 PM PDT 24
Finished Jun 06 12:57:36 PM PDT 24
Peak memory 183564 kb
Host smart-e723b1fe-bf07-44ed-8e5a-35cf6b75fd2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235257468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2235257468
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1196959179
Short name T360
Test name
Test status
Simulation time 1184494871 ps
CPU time 1.62 seconds
Started Jun 06 12:57:34 PM PDT 24
Finished Jun 06 12:57:37 PM PDT 24
Peak memory 192796 kb
Host smart-908bb46c-22c4-47d4-af28-f30c8c4a6f58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196959179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1196959179
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1852935118
Short name T318
Test name
Test status
Simulation time 623481389 ps
CPU time 2.42 seconds
Started Jun 06 12:57:35 PM PDT 24
Finished Jun 06 12:57:38 PM PDT 24
Peak memory 198356 kb
Host smart-7c434150-b16a-4efc-8ad5-965c5649edb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852935118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1852935118
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1283434353
Short name T320
Test name
Test status
Simulation time 636898200 ps
CPU time 1.06 seconds
Started Jun 06 12:57:38 PM PDT 24
Finished Jun 06 12:57:41 PM PDT 24
Peak memory 198224 kb
Host smart-8fe53efc-a7f2-47d6-b0e7-def1363c37a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283434353 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1283434353
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2371185046
Short name T86
Test name
Test status
Simulation time 512973326 ps
CPU time 0.78 seconds
Started Jun 06 12:57:37 PM PDT 24
Finished Jun 06 12:57:39 PM PDT 24
Peak memory 192880 kb
Host smart-45fae197-7350-4567-ba18-00d51ad762a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371185046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2371185046
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3999030300
Short name T407
Test name
Test status
Simulation time 365967539 ps
CPU time 1.1 seconds
Started Jun 06 12:57:40 PM PDT 24
Finished Jun 06 12:57:42 PM PDT 24
Peak memory 183496 kb
Host smart-ff690c50-d023-48b2-abf8-0797f1b854a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999030300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3999030300
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3966015636
Short name T89
Test name
Test status
Simulation time 1565619709 ps
CPU time 3 seconds
Started Jun 06 12:57:39 PM PDT 24
Finished Jun 06 12:57:43 PM PDT 24
Peak memory 183616 kb
Host smart-5eaa8f01-beec-4b5d-b822-540fa5592cf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966015636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3966015636
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1466870052
Short name T414
Test name
Test status
Simulation time 492017788 ps
CPU time 2.11 seconds
Started Jun 06 12:57:34 PM PDT 24
Finished Jun 06 12:57:38 PM PDT 24
Peak memory 198332 kb
Host smart-59b73df3-4a48-471f-92b3-513bab36c9a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466870052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1466870052
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2116375015
Short name T333
Test name
Test status
Simulation time 4400519809 ps
CPU time 2.45 seconds
Started Jun 06 12:57:39 PM PDT 24
Finished Jun 06 12:57:43 PM PDT 24
Peak memory 197648 kb
Host smart-57648636-c843-4dc1-a625-649aa279b3b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116375015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2116375015
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3928081026
Short name T300
Test name
Test status
Simulation time 585510166 ps
CPU time 1.31 seconds
Started Jun 06 12:57:38 PM PDT 24
Finished Jun 06 12:57:40 PM PDT 24
Peak memory 195556 kb
Host smart-964ba606-d71f-418a-a59c-7ff2e82616ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928081026 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3928081026
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2156411517
Short name T381
Test name
Test status
Simulation time 562944410 ps
CPU time 0.74 seconds
Started Jun 06 12:57:33 PM PDT 24
Finished Jun 06 12:57:35 PM PDT 24
Peak memory 192852 kb
Host smart-e65a14c5-13f6-43b2-b57e-b0cda029baf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156411517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2156411517
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1439433937
Short name T416
Test name
Test status
Simulation time 360643862 ps
CPU time 0.66 seconds
Started Jun 06 12:57:36 PM PDT 24
Finished Jun 06 12:57:38 PM PDT 24
Peak memory 183580 kb
Host smart-3e19251a-3101-4575-bb29-f3cae8c1a9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439433937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1439433937
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3853239709
Short name T88
Test name
Test status
Simulation time 1356260513 ps
CPU time 2.45 seconds
Started Jun 06 12:57:36 PM PDT 24
Finished Jun 06 12:57:40 PM PDT 24
Peak memory 193072 kb
Host smart-012a40cf-ad63-495f-8352-8f36b4fb8ff3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853239709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3853239709
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.863516938
Short name T340
Test name
Test status
Simulation time 604612528 ps
CPU time 1.98 seconds
Started Jun 06 12:57:34 PM PDT 24
Finished Jun 06 12:57:37 PM PDT 24
Peak memory 198336 kb
Host smart-4954dcf1-9f0d-4100-b251-a89e13b54ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863516938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.863516938
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3298291615
Short name T419
Test name
Test status
Simulation time 4284341243 ps
CPU time 7.47 seconds
Started Jun 06 12:57:34 PM PDT 24
Finished Jun 06 12:57:43 PM PDT 24
Peak memory 197920 kb
Host smart-08dff84e-67c0-41d3-b195-00e9a9c032ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298291615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3298291615
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3645709618
Short name T377
Test name
Test status
Simulation time 521327449 ps
CPU time 0.83 seconds
Started Jun 06 12:57:33 PM PDT 24
Finished Jun 06 12:57:35 PM PDT 24
Peak memory 195800 kb
Host smart-e426da5d-f246-4723-a252-5a4de9ab19a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645709618 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3645709618
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2153802526
Short name T199
Test name
Test status
Simulation time 330154677 ps
CPU time 1.05 seconds
Started Jun 06 12:57:36 PM PDT 24
Finished Jun 06 12:57:38 PM PDT 24
Peak memory 193076 kb
Host smart-f798d914-85aa-4517-8ea6-066725f0fc20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153802526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2153802526
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4265951636
Short name T346
Test name
Test status
Simulation time 533902442 ps
CPU time 0.75 seconds
Started Jun 06 12:57:34 PM PDT 24
Finished Jun 06 12:57:36 PM PDT 24
Peak memory 183580 kb
Host smart-b949bd38-ad15-4ea5-b7f8-cae6b8f56dc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265951636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.4265951636
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.93068977
Short name T85
Test name
Test status
Simulation time 2717636815 ps
CPU time 4.55 seconds
Started Jun 06 12:57:39 PM PDT 24
Finished Jun 06 12:57:45 PM PDT 24
Peak memory 193832 kb
Host smart-5283be08-ce7d-40eb-9847-0b2e29cfbb73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93068977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_
timer_same_csr_outstanding.93068977
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4132035308
Short name T389
Test name
Test status
Simulation time 741347614 ps
CPU time 2.33 seconds
Started Jun 06 12:57:38 PM PDT 24
Finished Jun 06 12:57:42 PM PDT 24
Peak memory 198344 kb
Host smart-302cff84-de17-4d55-a32e-48eb4808e4ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132035308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4132035308
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.801552824
Short name T33
Test name
Test status
Simulation time 8250976333 ps
CPU time 2.77 seconds
Started Jun 06 12:57:36 PM PDT 24
Finished Jun 06 12:57:40 PM PDT 24
Peak memory 197936 kb
Host smart-0cc52e37-3066-4520-b7dc-9145f0b21deb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801552824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.801552824
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.540899277
Short name T198
Test name
Test status
Simulation time 409452327 ps
CPU time 0.89 seconds
Started Jun 06 12:57:35 PM PDT 24
Finished Jun 06 12:57:37 PM PDT 24
Peak memory 196236 kb
Host smart-2db0a2c7-d638-4a6f-b916-e75eef0e83ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540899277 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.540899277
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.756865120
Short name T328
Test name
Test status
Simulation time 288694770 ps
CPU time 0.98 seconds
Started Jun 06 12:57:36 PM PDT 24
Finished Jun 06 12:57:38 PM PDT 24
Peak memory 192864 kb
Host smart-c8d5a3ae-589d-458e-8e4e-cde438840c1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756865120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.756865120
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.849259485
Short name T335
Test name
Test status
Simulation time 477138428 ps
CPU time 0.59 seconds
Started Jun 06 12:57:34 PM PDT 24
Finished Jun 06 12:57:36 PM PDT 24
Peak memory 183576 kb
Host smart-86a3b4a2-0709-4ee1-a973-1750911ac660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849259485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.849259485
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1942209505
Short name T82
Test name
Test status
Simulation time 2205357238 ps
CPU time 1.64 seconds
Started Jun 06 12:57:37 PM PDT 24
Finished Jun 06 12:57:40 PM PDT 24
Peak memory 193852 kb
Host smart-24071a63-31d4-47f9-a89c-4f491261ca5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942209505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1942209505
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.55549025
Short name T375
Test name
Test status
Simulation time 583066147 ps
CPU time 1.51 seconds
Started Jun 06 12:57:36 PM PDT 24
Finished Jun 06 12:57:39 PM PDT 24
Peak memory 198304 kb
Host smart-5c60dd3c-c40f-4729-bc93-60e30f215172
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55549025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.55549025
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.834595108
Short name T402
Test name
Test status
Simulation time 4393897133 ps
CPU time 1.73 seconds
Started Jun 06 12:57:33 PM PDT 24
Finished Jun 06 12:57:36 PM PDT 24
Peak memory 196568 kb
Host smart-c9d95374-cd9a-4beb-ba5d-74a3b7eb4dc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834595108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.834595108
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2197747919
Short name T398
Test name
Test status
Simulation time 499418126 ps
CPU time 0.92 seconds
Started Jun 06 12:57:47 PM PDT 24
Finished Jun 06 12:57:49 PM PDT 24
Peak memory 196120 kb
Host smart-50eea161-a35b-4930-8327-13db320eeec9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197747919 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2197747919
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3435895265
Short name T64
Test name
Test status
Simulation time 423223169 ps
CPU time 1.23 seconds
Started Jun 06 12:57:43 PM PDT 24
Finished Jun 06 12:57:45 PM PDT 24
Peak memory 192912 kb
Host smart-901f8c4c-c196-4ab1-8ac6-8b845708cde0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435895265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3435895265
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.654604811
Short name T423
Test name
Test status
Simulation time 344457906 ps
CPU time 0.85 seconds
Started Jun 06 12:57:43 PM PDT 24
Finished Jun 06 12:57:45 PM PDT 24
Peak memory 183500 kb
Host smart-2f46695e-076c-422e-b175-849920ea6209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654604811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.654604811
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1618498257
Short name T387
Test name
Test status
Simulation time 2615198168 ps
CPU time 4.87 seconds
Started Jun 06 12:57:43 PM PDT 24
Finished Jun 06 12:57:49 PM PDT 24
Peak memory 191912 kb
Host smart-1890a90f-62a9-4ded-ba0e-52aafc4f4992
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618498257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1618498257
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1001452975
Short name T413
Test name
Test status
Simulation time 834710715 ps
CPU time 2.56 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:48 PM PDT 24
Peak memory 198324 kb
Host smart-561ac450-1dd7-4d48-b85d-94aafbeea84b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001452975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1001452975
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3967872765
Short name T424
Test name
Test status
Simulation time 4182758544 ps
CPU time 3.49 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:49 PM PDT 24
Peak memory 196496 kb
Host smart-1c349c60-6dd9-4349-8bef-03d32b93d8e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967872765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3967872765
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.999621182
Short name T306
Test name
Test status
Simulation time 574076469 ps
CPU time 1.54 seconds
Started Jun 06 12:57:43 PM PDT 24
Finished Jun 06 12:57:46 PM PDT 24
Peak memory 196408 kb
Host smart-a5a6b782-a29a-4cc5-898d-2509a81b2e62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999621182 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.999621182
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1626052535
Short name T302
Test name
Test status
Simulation time 448729760 ps
CPU time 0.59 seconds
Started Jun 06 12:57:43 PM PDT 24
Finished Jun 06 12:57:44 PM PDT 24
Peak memory 183680 kb
Host smart-2799827b-bfc8-4aa4-a197-6766f77d37e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626052535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1626052535
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3657729642
Short name T415
Test name
Test status
Simulation time 280809029 ps
CPU time 0.74 seconds
Started Jun 06 12:57:48 PM PDT 24
Finished Jun 06 12:57:50 PM PDT 24
Peak memory 183544 kb
Host smart-31ef425e-9f9c-49db-81e6-4b509211c380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657729642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3657729642
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.784607093
Short name T84
Test name
Test status
Simulation time 2507483069 ps
CPU time 2.04 seconds
Started Jun 06 12:57:43 PM PDT 24
Finished Jun 06 12:57:46 PM PDT 24
Peak memory 191912 kb
Host smart-e588d62a-c436-4575-9535-f0abdc484892
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784607093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.784607093
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1722219702
Short name T325
Test name
Test status
Simulation time 365302675 ps
CPU time 1.24 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:46 PM PDT 24
Peak memory 198384 kb
Host smart-eb716d76-6e7d-4132-bfbf-527fb6ab7234
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722219702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1722219702
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.822861845
Short name T396
Test name
Test status
Simulation time 469215289 ps
CPU time 1.32 seconds
Started Jun 06 12:57:18 PM PDT 24
Finished Jun 06 12:57:21 PM PDT 24
Peak memory 183600 kb
Host smart-7f64b000-3d59-4a3f-85a3-74b2dbc9d8a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822861845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.822861845
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2286331260
Short name T63
Test name
Test status
Simulation time 7114004916 ps
CPU time 11.28 seconds
Started Jun 06 12:57:18 PM PDT 24
Finished Jun 06 12:57:31 PM PDT 24
Peak memory 195588 kb
Host smart-9f1a15c6-7372-4ade-b66b-2396d844583c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286331260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2286331260
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3558913346
Short name T78
Test name
Test status
Simulation time 1177151153 ps
CPU time 0.97 seconds
Started Jun 06 12:57:16 PM PDT 24
Finished Jun 06 12:57:18 PM PDT 24
Peak memory 183708 kb
Host smart-607a4b58-5aaf-4edc-bc2c-6d682396cd4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558913346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3558913346
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3791709189
Short name T349
Test name
Test status
Simulation time 365786620 ps
CPU time 0.9 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:19 PM PDT 24
Peak memory 197268 kb
Host smart-f12148d7-d665-4bed-a2d4-fa0f9581020e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791709189 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3791709189
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2886456505
Short name T65
Test name
Test status
Simulation time 373984316 ps
CPU time 0.85 seconds
Started Jun 06 12:57:18 PM PDT 24
Finished Jun 06 12:57:21 PM PDT 24
Peak memory 192800 kb
Host smart-a6662b02-a66f-4291-a3bf-d0c7d2394864
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886456505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2886456505
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3641603552
Short name T289
Test name
Test status
Simulation time 386986867 ps
CPU time 1.18 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:19 PM PDT 24
Peak memory 183544 kb
Host smart-8d893fa6-1ad7-4a5b-8efb-fc0591ca9590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641603552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3641603552
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2344428014
Short name T303
Test name
Test status
Simulation time 479051115 ps
CPU time 0.67 seconds
Started Jun 06 12:57:16 PM PDT 24
Finished Jun 06 12:57:17 PM PDT 24
Peak memory 183432 kb
Host smart-a263a8cc-de53-46ef-abc0-3a0302ba953e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344428014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2344428014
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1207350374
Short name T386
Test name
Test status
Simulation time 322823619 ps
CPU time 1.01 seconds
Started Jun 06 12:57:22 PM PDT 24
Finished Jun 06 12:57:24 PM PDT 24
Peak memory 183164 kb
Host smart-0459bb52-e753-4480-94f8-3fb4945bfe8a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207350374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1207350374
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3821186320
Short name T409
Test name
Test status
Simulation time 1183652915 ps
CPU time 1.22 seconds
Started Jun 06 12:57:15 PM PDT 24
Finished Jun 06 12:57:17 PM PDT 24
Peak memory 193024 kb
Host smart-7d10a0dc-66fa-4c66-88a9-50e05323ac75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821186320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3821186320
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.813700128
Short name T321
Test name
Test status
Simulation time 519494243 ps
CPU time 2.32 seconds
Started Jun 06 12:57:10 PM PDT 24
Finished Jun 06 12:57:13 PM PDT 24
Peak memory 198356 kb
Host smart-c9535f31-0dfd-48be-b531-8dd978c64ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813700128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.813700128
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2454478608
Short name T193
Test name
Test status
Simulation time 8591417711 ps
CPU time 4.64 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:23 PM PDT 24
Peak memory 198128 kb
Host smart-20bef58a-2f99-4352-81f3-948364a6289f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454478608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2454478608
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2664871597
Short name T317
Test name
Test status
Simulation time 368223325 ps
CPU time 0.6 seconds
Started Jun 06 12:57:43 PM PDT 24
Finished Jun 06 12:57:45 PM PDT 24
Peak memory 183464 kb
Host smart-52db433f-cce5-4ec6-bccd-716c6c5e4860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664871597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2664871597
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1921596333
Short name T288
Test name
Test status
Simulation time 383012827 ps
CPU time 1.1 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:46 PM PDT 24
Peak memory 183580 kb
Host smart-44f9bf27-e0b4-4f61-9b36-73befe47cc51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921596333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1921596333
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2446375676
Short name T373
Test name
Test status
Simulation time 362150952 ps
CPU time 1.05 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:46 PM PDT 24
Peak memory 183480 kb
Host smart-9b09f5e1-2b04-4f08-9da7-30bbc16e8513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446375676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2446375676
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2698230731
Short name T361
Test name
Test status
Simulation time 501855716 ps
CPU time 0.73 seconds
Started Jun 06 12:57:45 PM PDT 24
Finished Jun 06 12:57:47 PM PDT 24
Peak memory 183516 kb
Host smart-2ebdd2bb-a4a6-4229-9404-6163689d64a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698230731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2698230731
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2844750256
Short name T376
Test name
Test status
Simulation time 356059068 ps
CPU time 0.68 seconds
Started Jun 06 12:57:43 PM PDT 24
Finished Jun 06 12:57:45 PM PDT 24
Peak memory 183580 kb
Host smart-7803eab5-31ce-457a-acf8-b33b9a39f377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844750256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2844750256
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3199842243
Short name T326
Test name
Test status
Simulation time 360546631 ps
CPU time 0.84 seconds
Started Jun 06 12:57:45 PM PDT 24
Finished Jun 06 12:57:47 PM PDT 24
Peak memory 183520 kb
Host smart-9c0500ed-3294-450e-9f59-ec2a938289fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199842243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3199842243
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1773675016
Short name T286
Test name
Test status
Simulation time 481247412 ps
CPU time 0.67 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:46 PM PDT 24
Peak memory 183568 kb
Host smart-04383500-78a4-4732-9785-af4b6f772251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773675016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1773675016
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.802664660
Short name T290
Test name
Test status
Simulation time 309357749 ps
CPU time 1.03 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:46 PM PDT 24
Peak memory 183496 kb
Host smart-ec0d1ec8-1827-49ba-a77c-e0fa489cbf4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802664660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.802664660
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3340680280
Short name T370
Test name
Test status
Simulation time 363852278 ps
CPU time 1.08 seconds
Started Jun 06 12:57:49 PM PDT 24
Finished Jun 06 12:57:51 PM PDT 24
Peak memory 183536 kb
Host smart-c527fa7c-1981-4355-b117-0dbac364b3f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340680280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3340680280
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1529931944
Short name T405
Test name
Test status
Simulation time 314169615 ps
CPU time 0.76 seconds
Started Jun 06 12:57:47 PM PDT 24
Finished Jun 06 12:57:49 PM PDT 24
Peak memory 183572 kb
Host smart-7149db0f-c801-4fe0-b016-8ed31d83dae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529931944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1529931944
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.137159999
Short name T406
Test name
Test status
Simulation time 384815177 ps
CPU time 0.77 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:19 PM PDT 24
Peak memory 183600 kb
Host smart-8fa90b7b-2820-487d-868b-8af895f79f5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137159999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.137159999
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3816851882
Short name T80
Test name
Test status
Simulation time 13982273689 ps
CPU time 21.1 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:40 PM PDT 24
Peak memory 191980 kb
Host smart-a4466de2-2ff1-43bd-8a6f-8f935a1030db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816851882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3816851882
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.730990981
Short name T294
Test name
Test status
Simulation time 1221931622 ps
CPU time 1.44 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:21 PM PDT 24
Peak memory 183736 kb
Host smart-595cd0c9-2a56-4a29-988d-c63b2f24fbca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730990981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.730990981
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2377553561
Short name T366
Test name
Test status
Simulation time 434978144 ps
CPU time 0.76 seconds
Started Jun 06 12:57:19 PM PDT 24
Finished Jun 06 12:57:21 PM PDT 24
Peak memory 195164 kb
Host smart-faa55063-6dd4-475e-9069-c1d64c22146e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377553561 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2377553561
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1994336099
Short name T383
Test name
Test status
Simulation time 506965122 ps
CPU time 0.92 seconds
Started Jun 06 12:57:16 PM PDT 24
Finished Jun 06 12:57:18 PM PDT 24
Peak memory 192912 kb
Host smart-52bcafe2-1c91-4f78-a099-159feab7a19d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994336099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1994336099
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2158492488
Short name T327
Test name
Test status
Simulation time 385666666 ps
CPU time 1.18 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:20 PM PDT 24
Peak memory 183496 kb
Host smart-e48571d6-726a-45d4-b55a-68345e33a148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158492488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2158492488
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2178127463
Short name T351
Test name
Test status
Simulation time 406008416 ps
CPU time 1.09 seconds
Started Jun 06 12:57:15 PM PDT 24
Finished Jun 06 12:57:17 PM PDT 24
Peak memory 183492 kb
Host smart-782aeb88-d26e-4561-b4d4-3012cbed05fc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178127463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2178127463
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3515441946
Short name T312
Test name
Test status
Simulation time 357993346 ps
CPU time 0.7 seconds
Started Jun 06 12:57:22 PM PDT 24
Finished Jun 06 12:57:24 PM PDT 24
Peak memory 183564 kb
Host smart-83468d6f-a334-4618-87b2-5657dd655fda
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515441946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3515441946
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3230588224
Short name T378
Test name
Test status
Simulation time 2142192877 ps
CPU time 1.9 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:21 PM PDT 24
Peak memory 193792 kb
Host smart-ce7ab361-6619-4d2d-86aa-d0f104384487
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230588224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3230588224
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1378904275
Short name T322
Test name
Test status
Simulation time 806004924 ps
CPU time 2.57 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:22 PM PDT 24
Peak memory 198364 kb
Host smart-a8ccae19-c885-41e1-9b0d-0045cdd6249c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378904275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1378904275
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1774401995
Short name T394
Test name
Test status
Simulation time 8170644081 ps
CPU time 2.77 seconds
Started Jun 06 12:57:18 PM PDT 24
Finished Jun 06 12:57:22 PM PDT 24
Peak memory 197900 kb
Host smart-adf27247-cb29-49e0-a76d-3d01331f895b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774401995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1774401995
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1802642966
Short name T299
Test name
Test status
Simulation time 404798710 ps
CPU time 1.16 seconds
Started Jun 06 12:57:49 PM PDT 24
Finished Jun 06 12:57:51 PM PDT 24
Peak memory 183524 kb
Host smart-a84c758b-6f91-40d8-8038-73a601a4c2c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802642966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1802642966
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2461636622
Short name T311
Test name
Test status
Simulation time 375977246 ps
CPU time 1.15 seconds
Started Jun 06 12:57:47 PM PDT 24
Finished Jun 06 12:57:49 PM PDT 24
Peak memory 183516 kb
Host smart-80ad0826-8ad9-4b1a-b3b2-eac33ea50e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461636622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2461636622
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1289826135
Short name T403
Test name
Test status
Simulation time 492196159 ps
CPU time 0.7 seconds
Started Jun 06 12:57:45 PM PDT 24
Finished Jun 06 12:57:47 PM PDT 24
Peak memory 183548 kb
Host smart-e05ed010-ca8c-44bf-9718-ef2233492fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289826135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1289826135
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3681168640
Short name T331
Test name
Test status
Simulation time 373901173 ps
CPU time 0.81 seconds
Started Jun 06 12:57:47 PM PDT 24
Finished Jun 06 12:57:49 PM PDT 24
Peak memory 183540 kb
Host smart-0b41e3aa-fb3a-42a0-838a-d75c36b88edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681168640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3681168640
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3645581641
Short name T397
Test name
Test status
Simulation time 475832001 ps
CPU time 0.77 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:46 PM PDT 24
Peak memory 183564 kb
Host smart-85f3ee14-01f3-424e-a7ee-f336e4eee214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645581641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3645581641
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2836196119
Short name T313
Test name
Test status
Simulation time 308285167 ps
CPU time 0.81 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:47 PM PDT 24
Peak memory 183560 kb
Host smart-dc257c61-490b-4e0c-a363-aa716a92ba8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836196119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2836196119
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1653007521
Short name T341
Test name
Test status
Simulation time 510865707 ps
CPU time 0.9 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:46 PM PDT 24
Peak memory 183568 kb
Host smart-6842e8bb-a7f0-471f-a92d-d8e9df76d693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653007521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1653007521
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.840810215
Short name T314
Test name
Test status
Simulation time 488153397 ps
CPU time 1.29 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:47 PM PDT 24
Peak memory 183512 kb
Host smart-ae726155-ee7f-406d-b75b-b126ed77799c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840810215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.840810215
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3204382803
Short name T363
Test name
Test status
Simulation time 419812604 ps
CPU time 0.74 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:46 PM PDT 24
Peak memory 183500 kb
Host smart-2631c87b-91f0-4169-91ac-1e4f86371881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204382803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3204382803
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4272491959
Short name T293
Test name
Test status
Simulation time 494466796 ps
CPU time 0.74 seconds
Started Jun 06 12:57:49 PM PDT 24
Finished Jun 06 12:57:51 PM PDT 24
Peak memory 183560 kb
Host smart-a9a477cd-85bf-489b-9619-7318e57fe92e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272491959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4272491959
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3777675886
Short name T418
Test name
Test status
Simulation time 503897912 ps
CPU time 0.95 seconds
Started Jun 06 12:57:16 PM PDT 24
Finished Jun 06 12:57:18 PM PDT 24
Peak memory 191848 kb
Host smart-b937054f-3cfc-4ed9-8fa9-9d0f3c7f7341
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777675886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3777675886
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2418197811
Short name T66
Test name
Test status
Simulation time 2236214109 ps
CPU time 2.74 seconds
Started Jun 06 12:57:18 PM PDT 24
Finished Jun 06 12:57:23 PM PDT 24
Peak memory 191888 kb
Host smart-2f1819d6-264e-4e97-bb2b-8bd8ef8cf7fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418197811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2418197811
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3634312366
Short name T367
Test name
Test status
Simulation time 1049457029 ps
CPU time 2.04 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:21 PM PDT 24
Peak memory 183712 kb
Host smart-a1b6f9d4-69ef-4f81-8619-8aa4a2738224
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634312366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3634312366
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3432562655
Short name T296
Test name
Test status
Simulation time 395637171 ps
CPU time 1.35 seconds
Started Jun 06 12:57:16 PM PDT 24
Finished Jun 06 12:57:18 PM PDT 24
Peak memory 195768 kb
Host smart-561b6462-6b6a-49df-9341-08739e5d7299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432562655 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3432562655
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.272724223
Short name T412
Test name
Test status
Simulation time 413953326 ps
CPU time 0.74 seconds
Started Jun 06 12:57:16 PM PDT 24
Finished Jun 06 12:57:18 PM PDT 24
Peak memory 192920 kb
Host smart-775b4f3a-7570-4d00-803c-524eedc8f56e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272724223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.272724223
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1261432502
Short name T319
Test name
Test status
Simulation time 499681151 ps
CPU time 1.34 seconds
Started Jun 06 12:57:22 PM PDT 24
Finished Jun 06 12:57:24 PM PDT 24
Peak memory 183568 kb
Host smart-587192d2-64fe-41e8-8421-e1b62aec5496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261432502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1261432502
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.634752004
Short name T323
Test name
Test status
Simulation time 516089533 ps
CPU time 0.92 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:20 PM PDT 24
Peak memory 183488 kb
Host smart-5fdb48d1-8797-4bf7-a261-5eb427933afc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634752004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.634752004
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3973782111
Short name T344
Test name
Test status
Simulation time 355148326 ps
CPU time 0.71 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:19 PM PDT 24
Peak memory 183552 kb
Host smart-dbae9d6f-31e7-47f1-bc96-d4eef9496761
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973782111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3973782111
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1255796439
Short name T410
Test name
Test status
Simulation time 1250720053 ps
CPU time 0.84 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:20 PM PDT 24
Peak memory 192780 kb
Host smart-c00361e2-f422-4ad1-8bc6-e5dfc8d9a0e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255796439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1255796439
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1934181431
Short name T316
Test name
Test status
Simulation time 476400936 ps
CPU time 2.01 seconds
Started Jun 06 12:57:16 PM PDT 24
Finished Jun 06 12:57:19 PM PDT 24
Peak memory 198308 kb
Host smart-c4a5fa73-d12f-49c8-9905-ad3c2f55d143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934181431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1934181431
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.4263774250
Short name T354
Test name
Test status
Simulation time 4617407557 ps
CPU time 1.56 seconds
Started Jun 06 12:57:14 PM PDT 24
Finished Jun 06 12:57:17 PM PDT 24
Peak memory 196252 kb
Host smart-3f0451f5-1261-4bf5-9311-72555d70cdfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263774250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.4263774250
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.433772743
Short name T291
Test name
Test status
Simulation time 281736840 ps
CPU time 0.87 seconds
Started Jun 06 12:57:44 PM PDT 24
Finished Jun 06 12:57:47 PM PDT 24
Peak memory 183576 kb
Host smart-7042d5aa-c340-490d-9054-4a191745a29a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433772743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.433772743
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1766525171
Short name T297
Test name
Test status
Simulation time 308874371 ps
CPU time 1.05 seconds
Started Jun 06 12:57:43 PM PDT 24
Finished Jun 06 12:57:45 PM PDT 24
Peak memory 183528 kb
Host smart-41a48334-b87b-40fe-b7bd-13bd9cdb49ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766525171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1766525171
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1718797851
Short name T348
Test name
Test status
Simulation time 443547000 ps
CPU time 0.69 seconds
Started Jun 06 12:57:47 PM PDT 24
Finished Jun 06 12:57:48 PM PDT 24
Peak memory 183568 kb
Host smart-08991770-9665-49f8-a84a-9ee17bc7e523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718797851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1718797851
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1110358055
Short name T307
Test name
Test status
Simulation time 372152020 ps
CPU time 0.95 seconds
Started Jun 06 12:57:45 PM PDT 24
Finished Jun 06 12:57:47 PM PDT 24
Peak memory 183528 kb
Host smart-1361d375-a4b7-4116-aa8f-bd7db0906c23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110358055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1110358055
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.581249081
Short name T391
Test name
Test status
Simulation time 438846404 ps
CPU time 0.71 seconds
Started Jun 06 12:57:49 PM PDT 24
Finished Jun 06 12:57:51 PM PDT 24
Peak memory 183540 kb
Host smart-27b127e3-c669-4b8c-a930-e5cc9f8fad8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581249081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.581249081
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.267290910
Short name T364
Test name
Test status
Simulation time 449005421 ps
CPU time 1.26 seconds
Started Jun 06 12:57:42 PM PDT 24
Finished Jun 06 12:57:44 PM PDT 24
Peak memory 183512 kb
Host smart-c17dae09-77d2-41e9-8e86-ccde1f45e941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267290910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.267290910
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3441437915
Short name T420
Test name
Test status
Simulation time 395524338 ps
CPU time 1.13 seconds
Started Jun 06 12:57:59 PM PDT 24
Finished Jun 06 12:58:00 PM PDT 24
Peak memory 183500 kb
Host smart-5d2a8601-966d-4264-9205-ac95b934a9b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441437915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3441437915
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3863129926
Short name T350
Test name
Test status
Simulation time 297993794 ps
CPU time 0.65 seconds
Started Jun 06 12:57:57 PM PDT 24
Finished Jun 06 12:57:58 PM PDT 24
Peak memory 183584 kb
Host smart-96e268b7-0fbc-4462-bd7e-3f6f1a74de40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863129926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3863129926
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3643282751
Short name T374
Test name
Test status
Simulation time 320467322 ps
CPU time 0.75 seconds
Started Jun 06 12:57:52 PM PDT 24
Finished Jun 06 12:57:54 PM PDT 24
Peak memory 183580 kb
Host smart-0a72038e-2928-4979-8d02-ffa588e218c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643282751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3643282751
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3141661393
Short name T401
Test name
Test status
Simulation time 407787352 ps
CPU time 0.9 seconds
Started Jun 06 12:57:53 PM PDT 24
Finished Jun 06 12:57:56 PM PDT 24
Peak memory 183464 kb
Host smart-a956e0a8-3a47-4178-b066-f136d0479a2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141661393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3141661393
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2853014964
Short name T356
Test name
Test status
Simulation time 386460999 ps
CPU time 0.78 seconds
Started Jun 06 12:57:18 PM PDT 24
Finished Jun 06 12:57:21 PM PDT 24
Peak memory 195516 kb
Host smart-e8ee4077-c512-4661-8a79-cd586c35e91c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853014964 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2853014964
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2027864979
Short name T81
Test name
Test status
Simulation time 368191690 ps
CPU time 1.11 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:20 PM PDT 24
Peak memory 193096 kb
Host smart-f95416f7-f538-4f69-973b-b32c8a5684cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027864979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2027864979
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2894376926
Short name T358
Test name
Test status
Simulation time 423516415 ps
CPU time 0.67 seconds
Started Jun 06 12:57:22 PM PDT 24
Finished Jun 06 12:57:24 PM PDT 24
Peak memory 183280 kb
Host smart-bb8dbcf0-0feb-4586-bf6a-acd839a47e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894376926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2894376926
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2255642035
Short name T345
Test name
Test status
Simulation time 1285781875 ps
CPU time 1.26 seconds
Started Jun 06 12:57:16 PM PDT 24
Finished Jun 06 12:57:19 PM PDT 24
Peak memory 193176 kb
Host smart-31fe4fa4-4da2-43b8-8d0e-0e1000a9f772
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255642035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2255642035
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.980781937
Short name T384
Test name
Test status
Simulation time 626777379 ps
CPU time 2.81 seconds
Started Jun 06 12:57:19 PM PDT 24
Finished Jun 06 12:57:23 PM PDT 24
Peak memory 198328 kb
Host smart-98c0ccc9-623f-45d7-80bc-b6a48e395197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980781937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.980781937
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2246497071
Short name T395
Test name
Test status
Simulation time 8185577772 ps
CPU time 7.7 seconds
Started Jun 06 12:57:18 PM PDT 24
Finished Jun 06 12:57:28 PM PDT 24
Peak memory 197932 kb
Host smart-68dd4fdf-7eb8-4507-b0f4-73f08131955e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246497071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2246497071
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1121567781
Short name T422
Test name
Test status
Simulation time 394108098 ps
CPU time 1.15 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:19 PM PDT 24
Peak memory 195184 kb
Host smart-73e768b1-3fdd-4e68-bcad-9eb32f7c32ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121567781 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1121567781
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1316865839
Short name T310
Test name
Test status
Simulation time 498872428 ps
CPU time 1.4 seconds
Started Jun 06 12:57:18 PM PDT 24
Finished Jun 06 12:57:22 PM PDT 24
Peak memory 192864 kb
Host smart-deb21b18-de30-4dcc-b593-46482a839454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316865839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1316865839
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.589069786
Short name T380
Test name
Test status
Simulation time 295008598 ps
CPU time 0.67 seconds
Started Jun 06 12:57:17 PM PDT 24
Finished Jun 06 12:57:19 PM PDT 24
Peak memory 183560 kb
Host smart-915afa5e-d29e-406b-aa98-51deb8d6f990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589069786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.589069786
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2526280374
Short name T29
Test name
Test status
Simulation time 1883976397 ps
CPU time 1.74 seconds
Started Jun 06 12:57:16 PM PDT 24
Finished Jun 06 12:57:18 PM PDT 24
Peak memory 192808 kb
Host smart-8f363818-c145-4b33-9c88-a541a47d0d95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526280374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2526280374
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3302007853
Short name T417
Test name
Test status
Simulation time 498669459 ps
CPU time 2.29 seconds
Started Jun 06 12:57:16 PM PDT 24
Finished Jun 06 12:57:19 PM PDT 24
Peak memory 198364 kb
Host smart-ba17c3a8-c8d1-426c-a33e-7c7abfe01782
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302007853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3302007853
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1978640107
Short name T337
Test name
Test status
Simulation time 4372676494 ps
CPU time 2.14 seconds
Started Jun 06 12:57:16 PM PDT 24
Finished Jun 06 12:57:18 PM PDT 24
Peak memory 197344 kb
Host smart-09a695da-894c-4855-86d4-371bb3c9bee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978640107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1978640107
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4276081889
Short name T368
Test name
Test status
Simulation time 604188762 ps
CPU time 1.16 seconds
Started Jun 06 12:57:27 PM PDT 24
Finished Jun 06 12:57:29 PM PDT 24
Peak memory 198276 kb
Host smart-5eb4930f-4717-44e1-9ea1-4369520f2726
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276081889 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.4276081889
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.185792839
Short name T201
Test name
Test status
Simulation time 373959181 ps
CPU time 0.68 seconds
Started Jun 06 12:57:24 PM PDT 24
Finished Jun 06 12:57:26 PM PDT 24
Peak memory 183668 kb
Host smart-bde16d46-ead6-4aab-b8db-635c22800f26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185792839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.185792839
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3646441795
Short name T379
Test name
Test status
Simulation time 459804601 ps
CPU time 1.15 seconds
Started Jun 06 12:57:28 PM PDT 24
Finished Jun 06 12:57:31 PM PDT 24
Peak memory 183552 kb
Host smart-3571ac44-a8f7-491e-addb-1051cb7103ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646441795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3646441795
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.35867968
Short name T87
Test name
Test status
Simulation time 1127066903 ps
CPU time 1.05 seconds
Started Jun 06 12:57:27 PM PDT 24
Finished Jun 06 12:57:29 PM PDT 24
Peak memory 183672 kb
Host smart-d886fea1-7581-45df-bf1c-e6fc312c6b95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35867968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_t
imer_same_csr_outstanding.35867968
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1977676499
Short name T336
Test name
Test status
Simulation time 560881499 ps
CPU time 2.58 seconds
Started Jun 06 12:57:16 PM PDT 24
Finished Jun 06 12:57:20 PM PDT 24
Peak memory 198660 kb
Host smart-87b3afc9-d366-4fb7-a97f-8d78d6b59703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977676499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1977676499
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3525970015
Short name T308
Test name
Test status
Simulation time 4246696493 ps
CPU time 6.7 seconds
Started Jun 06 12:57:25 PM PDT 24
Finished Jun 06 12:57:33 PM PDT 24
Peak memory 197552 kb
Host smart-d31e1c44-e986-4253-9dac-245a7bde036d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525970015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3525970015
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.535090454
Short name T197
Test name
Test status
Simulation time 365029716 ps
CPU time 0.77 seconds
Started Jun 06 12:57:28 PM PDT 24
Finished Jun 06 12:57:30 PM PDT 24
Peak memory 195592 kb
Host smart-16ad8355-61e2-455b-b0ef-5cd90f69d24b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535090454 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.535090454
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.598021821
Short name T76
Test name
Test status
Simulation time 451631243 ps
CPU time 0.65 seconds
Started Jun 06 12:57:29 PM PDT 24
Finished Jun 06 12:57:31 PM PDT 24
Peak memory 193152 kb
Host smart-6b5f0df3-47d8-4458-9c8c-24a0789c920b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598021821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.598021821
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1396371723
Short name T305
Test name
Test status
Simulation time 393345831 ps
CPU time 0.61 seconds
Started Jun 06 12:57:28 PM PDT 24
Finished Jun 06 12:57:30 PM PDT 24
Peak memory 183572 kb
Host smart-4bd32d7c-4abc-4793-9650-5ef7d370b5b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396371723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1396371723
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1841947149
Short name T83
Test name
Test status
Simulation time 2725395297 ps
CPU time 2.09 seconds
Started Jun 06 12:57:27 PM PDT 24
Finished Jun 06 12:57:29 PM PDT 24
Peak memory 194252 kb
Host smart-9c73d628-0866-44cf-bbce-972d2cb52224
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841947149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1841947149
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3410707018
Short name T392
Test name
Test status
Simulation time 338457476 ps
CPU time 1.62 seconds
Started Jun 06 12:57:24 PM PDT 24
Finished Jun 06 12:57:27 PM PDT 24
Peak memory 198280 kb
Host smart-0ff08676-f185-4dc6-9b04-ba7aed9e59d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410707018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3410707018
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3597722591
Short name T329
Test name
Test status
Simulation time 4367791149 ps
CPU time 2.61 seconds
Started Jun 06 12:57:25 PM PDT 24
Finished Jun 06 12:57:28 PM PDT 24
Peak memory 197460 kb
Host smart-b075e973-8e0f-47e3-a473-ba24c9619b06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597722591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3597722591
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2359552464
Short name T362
Test name
Test status
Simulation time 508767097 ps
CPU time 0.93 seconds
Started Jun 06 12:57:28 PM PDT 24
Finished Jun 06 12:57:30 PM PDT 24
Peak memory 196332 kb
Host smart-162b0bb8-507b-41e9-b5f3-4a612587bc2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359552464 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2359552464
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2728818127
Short name T31
Test name
Test status
Simulation time 444047417 ps
CPU time 0.76 seconds
Started Jun 06 12:57:27 PM PDT 24
Finished Jun 06 12:57:28 PM PDT 24
Peak memory 192956 kb
Host smart-b79e07be-7ae4-46d9-ba11-f29e7e1968d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728818127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2728818127
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2318637895
Short name T411
Test name
Test status
Simulation time 444733905 ps
CPU time 0.7 seconds
Started Jun 06 12:57:28 PM PDT 24
Finished Jun 06 12:57:30 PM PDT 24
Peak memory 183052 kb
Host smart-0dcb1ec4-1763-4207-93c1-d849ecee1097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318637895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2318637895
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1439967872
Short name T342
Test name
Test status
Simulation time 2569654075 ps
CPU time 1.87 seconds
Started Jun 06 12:57:29 PM PDT 24
Finished Jun 06 12:57:32 PM PDT 24
Peak memory 193864 kb
Host smart-22ce1228-2e09-4c9a-9fe9-3deec038cdf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439967872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1439967872
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2212223331
Short name T287
Test name
Test status
Simulation time 535923792 ps
CPU time 1.63 seconds
Started Jun 06 12:57:26 PM PDT 24
Finished Jun 06 12:57:28 PM PDT 24
Peak memory 198412 kb
Host smart-dc39582a-ae9f-4fd7-89d0-4053ce5250e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212223331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2212223331
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.589245557
Short name T359
Test name
Test status
Simulation time 4740605534 ps
CPU time 1.49 seconds
Started Jun 06 12:57:27 PM PDT 24
Finished Jun 06 12:57:30 PM PDT 24
Peak memory 196580 kb
Host smart-de83cf8f-895e-450d-afe6-a94d31a882e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589245557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.589245557
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.305774772
Short name T274
Test name
Test status
Simulation time 24028111916 ps
CPU time 39.82 seconds
Started Jun 06 12:54:44 PM PDT 24
Finished Jun 06 12:55:25 PM PDT 24
Peak memory 191844 kb
Host smart-b2056e18-0dc3-4d56-974a-a8ec32f3b0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305774772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.305774772
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3809205451
Short name T282
Test name
Test status
Simulation time 558720745 ps
CPU time 0.93 seconds
Started Jun 06 12:54:41 PM PDT 24
Finished Jun 06 12:54:43 PM PDT 24
Peak memory 191664 kb
Host smart-1d3e865a-b4cb-44a7-81ba-c8a7d0c56ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809205451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3809205451
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3810027906
Short name T195
Test name
Test status
Simulation time 120760865599 ps
CPU time 258.46 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:59:04 PM PDT 24
Peak memory 209720 kb
Host smart-71fe7b42-0902-4fe8-ae25-3c4172e73dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810027906 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3810027906
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2780047126
Short name T224
Test name
Test status
Simulation time 18649444389 ps
CPU time 5.54 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:54:52 PM PDT 24
Peak memory 191884 kb
Host smart-80b99396-9481-44e3-b54f-8d3dc9b2b62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780047126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2780047126
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2397636439
Short name T14
Test name
Test status
Simulation time 7880268767 ps
CPU time 11.84 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:54:58 PM PDT 24
Peak memory 215720 kb
Host smart-1556806f-3f0c-45ca-a731-bf8f9c24b79c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397636439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2397636439
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.758401767
Short name T265
Test name
Test status
Simulation time 574406708 ps
CPU time 1.08 seconds
Started Jun 06 12:54:48 PM PDT 24
Finished Jun 06 12:54:50 PM PDT 24
Peak memory 191764 kb
Host smart-b7151ccb-0678-4a8d-b357-eb4227206640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758401767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.758401767
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.639403915
Short name T71
Test name
Test status
Simulation time 47855504437 ps
CPU time 36.24 seconds
Started Jun 06 12:54:55 PM PDT 24
Finished Jun 06 12:55:34 PM PDT 24
Peak memory 191896 kb
Host smart-ac0e1ddb-53d8-4fb4-8f56-dc718708a19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639403915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.639403915
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1655472423
Short name T210
Test name
Test status
Simulation time 453230579 ps
CPU time 1.24 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:54:57 PM PDT 24
Peak memory 191780 kb
Host smart-59a4aa67-3e22-4986-af81-e22e3f0460c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655472423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1655472423
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.472663872
Short name T232
Test name
Test status
Simulation time 30451116689 ps
CPU time 11.36 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:55:08 PM PDT 24
Peak memory 191916 kb
Host smart-b6341fa2-da4c-4b6d-bf94-dd5510539a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472663872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.472663872
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1268163982
Short name T283
Test name
Test status
Simulation time 435706438 ps
CPU time 0.73 seconds
Started Jun 06 12:54:52 PM PDT 24
Finished Jun 06 12:54:54 PM PDT 24
Peak memory 191752 kb
Host smart-cbafb688-c6c0-489a-beae-0d2ab8e3512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268163982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1268163982
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3966480748
Short name T269
Test name
Test status
Simulation time 8318045356 ps
CPU time 6.95 seconds
Started Jun 06 12:54:52 PM PDT 24
Finished Jun 06 12:55:00 PM PDT 24
Peak memory 191852 kb
Host smart-3e5b6761-23fb-4b5a-8291-6e3b7e7cf97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966480748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3966480748
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.729318745
Short name T231
Test name
Test status
Simulation time 610465355 ps
CPU time 0.74 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:54:57 PM PDT 24
Peak memory 191740 kb
Host smart-70b351ff-10eb-4879-8e33-fbf427e199ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729318745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.729318745
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3264033575
Short name T277
Test name
Test status
Simulation time 39380962767 ps
CPU time 14.77 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:55:11 PM PDT 24
Peak memory 191884 kb
Host smart-d05c4ae8-349b-4efd-945f-c608bf7d478b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264033575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3264033575
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1171564987
Short name T214
Test name
Test status
Simulation time 510803691 ps
CPU time 1.39 seconds
Started Jun 06 12:54:52 PM PDT 24
Finished Jun 06 12:54:55 PM PDT 24
Peak memory 196684 kb
Host smart-d7b0a80e-230e-4e82-92b3-7436b8e6fc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171564987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1171564987
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3921641666
Short name T278
Test name
Test status
Simulation time 502674650899 ps
CPU time 36.76 seconds
Started Jun 06 12:54:55 PM PDT 24
Finished Jun 06 12:55:34 PM PDT 24
Peak memory 192404 kb
Host smart-08a7004f-ea8f-4369-b7a1-dc7167f26fc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921641666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3921641666
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1034149355
Short name T273
Test name
Test status
Simulation time 26122954776 ps
CPU time 40.58 seconds
Started Jun 06 12:54:57 PM PDT 24
Finished Jun 06 12:55:40 PM PDT 24
Peak memory 191860 kb
Host smart-568bae29-5fd7-4856-a64b-8056c7900b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034149355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1034149355
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3945439821
Short name T39
Test name
Test status
Simulation time 443019940 ps
CPU time 1.26 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:07 PM PDT 24
Peak memory 191700 kb
Host smart-e7a2225a-ecce-40a0-99ea-5aba7b2eb8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945439821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3945439821
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.4247464033
Short name T68
Test name
Test status
Simulation time 11355143623 ps
CPU time 8.95 seconds
Started Jun 06 12:54:59 PM PDT 24
Finished Jun 06 12:55:09 PM PDT 24
Peak memory 191872 kb
Host smart-1b5c5b56-2b19-4e70-8611-306c77d3e01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247464033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.4247464033
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2473243428
Short name T74
Test name
Test status
Simulation time 360051180 ps
CPU time 0.7 seconds
Started Jun 06 12:54:53 PM PDT 24
Finished Jun 06 12:54:55 PM PDT 24
Peak memory 191676 kb
Host smart-7c29fdf7-d510-483a-b95f-ce8709daedc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473243428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2473243428
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3651724810
Short name T234
Test name
Test status
Simulation time 9657624998 ps
CPU time 4.38 seconds
Started Jun 06 12:54:57 PM PDT 24
Finished Jun 06 12:55:03 PM PDT 24
Peak memory 191860 kb
Host smart-cdf4a346-5cc9-4a63-a8e5-9d9e3d87e1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651724810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3651724810
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2540897543
Short name T228
Test name
Test status
Simulation time 374082134 ps
CPU time 0.68 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:54:56 PM PDT 24
Peak memory 191740 kb
Host smart-57e9e6a0-a459-4029-8192-78f8c5165724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540897543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2540897543
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.163771684
Short name T204
Test name
Test status
Simulation time 8636217367 ps
CPU time 4.12 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:11 PM PDT 24
Peak memory 191828 kb
Host smart-68e9f4da-eebe-4836-b698-51eb9d389e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163771684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.163771684
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.4103292343
Short name T275
Test name
Test status
Simulation time 429879213 ps
CPU time 0.74 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:54:57 PM PDT 24
Peak memory 191264 kb
Host smart-e486c4c5-83e3-4546-b082-9eeef57db575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103292343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.4103292343
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.4133046983
Short name T208
Test name
Test status
Simulation time 23594621679 ps
CPU time 12.96 seconds
Started Jun 06 12:54:55 PM PDT 24
Finished Jun 06 12:55:10 PM PDT 24
Peak memory 191872 kb
Host smart-eee75862-453e-4bbc-9aae-87dd85e1fba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133046983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.4133046983
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.33697162
Short name T280
Test name
Test status
Simulation time 376398927 ps
CPU time 0.65 seconds
Started Jun 06 12:54:58 PM PDT 24
Finished Jun 06 12:55:00 PM PDT 24
Peak memory 191768 kb
Host smart-d1bd7323-1106-4e53-9ef6-c6023a18efac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33697162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.33697162
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1148129793
Short name T257
Test name
Test status
Simulation time 22758742573 ps
CPU time 36.55 seconds
Started Jun 06 12:55:06 PM PDT 24
Finished Jun 06 12:55:43 PM PDT 24
Peak memory 191824 kb
Host smart-b5d21338-e32d-4bce-8388-9e93030391a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148129793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1148129793
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1858129363
Short name T223
Test name
Test status
Simulation time 379084482 ps
CPU time 0.72 seconds
Started Jun 06 12:54:54 PM PDT 24
Finished Jun 06 12:54:56 PM PDT 24
Peak memory 191756 kb
Host smart-803369b8-9711-42c4-a7d2-d34a98987014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858129363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1858129363
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2984140806
Short name T285
Test name
Test status
Simulation time 13690120260 ps
CPU time 3.26 seconds
Started Jun 06 12:54:56 PM PDT 24
Finished Jun 06 12:55:01 PM PDT 24
Peak memory 191884 kb
Host smart-01ffef2c-c675-4fbe-b6af-a216eec2d93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984140806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2984140806
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1460111917
Short name T15
Test name
Test status
Simulation time 4231295912 ps
CPU time 7.22 seconds
Started Jun 06 12:54:47 PM PDT 24
Finished Jun 06 12:54:55 PM PDT 24
Peak memory 215264 kb
Host smart-cfbe651e-8b3f-4262-8013-239135d03657
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460111917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1460111917
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3287456840
Short name T227
Test name
Test status
Simulation time 566978882 ps
CPU time 1.45 seconds
Started Jun 06 12:54:44 PM PDT 24
Finished Jun 06 12:54:47 PM PDT 24
Peak memory 191720 kb
Host smart-6f9cf703-c056-4c45-9b2c-a75bf78a5a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287456840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3287456840
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2791169631
Short name T270
Test name
Test status
Simulation time 4986029252 ps
CPU time 7.99 seconds
Started Jun 06 12:54:57 PM PDT 24
Finished Jun 06 12:55:06 PM PDT 24
Peak memory 191892 kb
Host smart-94a3bb19-4d37-4191-956e-6b6dbb28f16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791169631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2791169631
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1045928025
Short name T218
Test name
Test status
Simulation time 513849747 ps
CPU time 0.73 seconds
Started Jun 06 12:54:57 PM PDT 24
Finished Jun 06 12:54:59 PM PDT 24
Peak memory 191740 kb
Host smart-0df8d644-de0e-434d-9877-d3e769ff05c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045928025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1045928025
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_jump.454275902
Short name T188
Test name
Test status
Simulation time 364530084 ps
CPU time 1.19 seconds
Started Jun 06 12:54:57 PM PDT 24
Finished Jun 06 12:55:00 PM PDT 24
Peak memory 196360 kb
Host smart-14bec6d3-1cc4-4c92-9380-d3e7509d163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454275902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.454275902
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3264850939
Short name T229
Test name
Test status
Simulation time 35907450538 ps
CPU time 14.09 seconds
Started Jun 06 12:54:56 PM PDT 24
Finished Jun 06 12:55:12 PM PDT 24
Peak memory 191860 kb
Host smart-940cc06d-3ce2-4ec8-a5b5-be8c412fc333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264850939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3264850939
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.364576523
Short name T246
Test name
Test status
Simulation time 368633253 ps
CPU time 1.09 seconds
Started Jun 06 12:54:57 PM PDT 24
Finished Jun 06 12:55:00 PM PDT 24
Peak memory 191740 kb
Host smart-fb0d6826-d0cf-40a9-a47d-76b7e089923b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364576523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.364576523
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2931180733
Short name T236
Test name
Test status
Simulation time 14809341644 ps
CPU time 21.76 seconds
Started Jun 06 12:55:07 PM PDT 24
Finished Jun 06 12:55:30 PM PDT 24
Peak memory 191872 kb
Host smart-9ed18b57-9f4b-4a0d-b83a-edf4fbc2a200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931180733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2931180733
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3580341524
Short name T230
Test name
Test status
Simulation time 450197554 ps
CPU time 0.8 seconds
Started Jun 06 12:55:03 PM PDT 24
Finished Jun 06 12:55:05 PM PDT 24
Peak memory 191724 kb
Host smart-210170b8-edd7-428c-ab47-83ee0a3a4d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580341524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3580341524
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3143032830
Short name T242
Test name
Test status
Simulation time 27419515888 ps
CPU time 19.18 seconds
Started Jun 06 12:55:02 PM PDT 24
Finished Jun 06 12:55:23 PM PDT 24
Peak memory 191836 kb
Host smart-3bb0970b-5a4e-4bd0-9722-6fe326fd14a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143032830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3143032830
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2065407435
Short name T202
Test name
Test status
Simulation time 363000650 ps
CPU time 1.02 seconds
Started Jun 06 12:55:01 PM PDT 24
Finished Jun 06 12:55:03 PM PDT 24
Peak memory 191672 kb
Host smart-e5f57074-e5c7-4561-80ab-b1665a4f52a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065407435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2065407435
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2507753127
Short name T50
Test name
Test status
Simulation time 27767663431 ps
CPU time 24.27 seconds
Started Jun 06 12:55:02 PM PDT 24
Finished Jun 06 12:55:27 PM PDT 24
Peak memory 191864 kb
Host smart-16964e74-485e-4ba6-b1f1-b0c45cb3676b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507753127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2507753127
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.4069736269
Short name T248
Test name
Test status
Simulation time 453317002 ps
CPU time 0.68 seconds
Started Jun 06 12:55:03 PM PDT 24
Finished Jun 06 12:55:05 PM PDT 24
Peak memory 191768 kb
Host smart-776b4db3-7c89-45ba-8eee-e817214625c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069736269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4069736269
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3062950151
Short name T225
Test name
Test status
Simulation time 29210980842 ps
CPU time 11.72 seconds
Started Jun 06 12:55:02 PM PDT 24
Finished Jun 06 12:55:15 PM PDT 24
Peak memory 191816 kb
Host smart-d177962c-34cc-4dd9-bf68-2c0f547fb7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062950151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3062950151
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.407845718
Short name T70
Test name
Test status
Simulation time 502812150 ps
CPU time 1.2 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:07 PM PDT 24
Peak memory 191748 kb
Host smart-ecd03bd0-6e6f-4764-9f0a-54e76882eac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407845718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.407845718
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2850048150
Short name T52
Test name
Test status
Simulation time 10068124785 ps
CPU time 14.89 seconds
Started Jun 06 12:55:03 PM PDT 24
Finished Jun 06 12:55:19 PM PDT 24
Peak memory 191904 kb
Host smart-09e6b765-0aa8-4b14-83bb-c74f71278eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850048150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2850048150
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3480854778
Short name T271
Test name
Test status
Simulation time 511374983 ps
CPU time 0.94 seconds
Started Jun 06 12:55:02 PM PDT 24
Finished Jun 06 12:55:04 PM PDT 24
Peak memory 191764 kb
Host smart-0048d39d-12cd-44d2-92d7-58e064ece37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480854778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3480854778
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.682283929
Short name T267
Test name
Test status
Simulation time 27883269654 ps
CPU time 40.03 seconds
Started Jun 06 12:55:03 PM PDT 24
Finished Jun 06 12:55:44 PM PDT 24
Peak memory 191876 kb
Host smart-df04ca31-0b06-48f7-89e1-0c1132251fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682283929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.682283929
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.22453926
Short name T268
Test name
Test status
Simulation time 396457873 ps
CPU time 0.86 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:06 PM PDT 24
Peak memory 191756 kb
Host smart-c4b8e0d0-783e-4d2b-b665-5364520f589b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22453926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.22453926
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1765386171
Short name T9
Test name
Test status
Simulation time 16231350800 ps
CPU time 3.95 seconds
Started Jun 06 12:55:06 PM PDT 24
Finished Jun 06 12:55:11 PM PDT 24
Peak memory 191872 kb
Host smart-740181de-ce8e-42d7-9d61-c755d07726da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765386171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1765386171
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3391479032
Short name T237
Test name
Test status
Simulation time 511632639 ps
CPU time 1.27 seconds
Started Jun 06 12:55:07 PM PDT 24
Finished Jun 06 12:55:09 PM PDT 24
Peak memory 191776 kb
Host smart-556daf5c-7cb4-44ba-812c-c68c2b71fad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391479032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3391479032
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1654854656
Short name T250
Test name
Test status
Simulation time 25084404302 ps
CPU time 10.21 seconds
Started Jun 06 12:55:04 PM PDT 24
Finished Jun 06 12:55:15 PM PDT 24
Peak memory 191860 kb
Host smart-fd0feabb-e19c-4cc5-bab2-dd9e932d7930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654854656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1654854656
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1495163348
Short name T3
Test name
Test status
Simulation time 564548959 ps
CPU time 0.7 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:07 PM PDT 24
Peak memory 191712 kb
Host smart-f3757968-af59-4189-af38-884a57066a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495163348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1495163348
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2033291738
Short name T212
Test name
Test status
Simulation time 34252784814 ps
CPU time 55.56 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:55:41 PM PDT 24
Peak memory 191840 kb
Host smart-392e60c9-f996-4be5-8d45-29871a816888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033291738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2033291738
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.233705358
Short name T17
Test name
Test status
Simulation time 4505077430 ps
CPU time 2.14 seconds
Started Jun 06 12:54:47 PM PDT 24
Finished Jun 06 12:54:50 PM PDT 24
Peak memory 215580 kb
Host smart-a66029b7-7234-4a23-a69e-01548b129ae1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233705358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.233705358
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1095794707
Short name T238
Test name
Test status
Simulation time 468776504 ps
CPU time 1.33 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:54:47 PM PDT 24
Peak memory 191728 kb
Host smart-f9899b10-8184-4596-a32c-9a4340a7f573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095794707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1095794707
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2735769934
Short name T279
Test name
Test status
Simulation time 29805487389 ps
CPU time 49.87 seconds
Started Jun 06 12:55:03 PM PDT 24
Finished Jun 06 12:55:54 PM PDT 24
Peak memory 191900 kb
Host smart-d48a94a1-de41-4fe1-8556-371d174ab531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735769934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2735769934
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.541971102
Short name T244
Test name
Test status
Simulation time 595589092 ps
CPU time 0.79 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:06 PM PDT 24
Peak memory 191732 kb
Host smart-b543d138-0ae3-46b0-b684-29914f5a4f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541971102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.541971102
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2016926878
Short name T53
Test name
Test status
Simulation time 41438909510 ps
CPU time 11.42 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:17 PM PDT 24
Peak memory 191860 kb
Host smart-f2ee6d03-4b43-4d8d-b38f-11ad5aa28515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016926878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2016926878
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.721843181
Short name T276
Test name
Test status
Simulation time 620243868 ps
CPU time 0.82 seconds
Started Jun 06 12:55:05 PM PDT 24
Finished Jun 06 12:55:06 PM PDT 24
Peak memory 191708 kb
Host smart-440ff342-12a2-4b6d-a86c-b610fe4b41e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721843181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.721843181
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2968774740
Short name T247
Test name
Test status
Simulation time 37537008999 ps
CPU time 15.67 seconds
Started Jun 06 12:55:17 PM PDT 24
Finished Jun 06 12:55:35 PM PDT 24
Peak memory 191892 kb
Host smart-6fd56e63-f201-4f57-bf59-1fb3f590fa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968774740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2968774740
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2079388005
Short name T91
Test name
Test status
Simulation time 585281115 ps
CPU time 0.74 seconds
Started Jun 06 12:55:12 PM PDT 24
Finished Jun 06 12:55:14 PM PDT 24
Peak memory 191580 kb
Host smart-84005d34-7e19-423e-b8bf-cf8b75f6b84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079388005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2079388005
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3015506827
Short name T235
Test name
Test status
Simulation time 6253975176 ps
CPU time 2.86 seconds
Started Jun 06 12:55:14 PM PDT 24
Finished Jun 06 12:55:19 PM PDT 24
Peak memory 191892 kb
Host smart-3d31298a-a3c2-4407-9fe5-8515c793438f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015506827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3015506827
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1743665791
Short name T255
Test name
Test status
Simulation time 622278773 ps
CPU time 0.83 seconds
Started Jun 06 12:55:13 PM PDT 24
Finished Jun 06 12:55:15 PM PDT 24
Peak memory 191580 kb
Host smart-f8400b97-8a21-4cf3-aabe-206550895940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743665791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1743665791
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2773990747
Short name T196
Test name
Test status
Simulation time 3760193988 ps
CPU time 3.76 seconds
Started Jun 06 12:55:14 PM PDT 24
Finished Jun 06 12:55:20 PM PDT 24
Peak memory 191796 kb
Host smart-ead07756-08c9-45e6-9124-ebe3e96bb0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773990747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2773990747
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2769547861
Short name T220
Test name
Test status
Simulation time 432046524 ps
CPU time 1.18 seconds
Started Jun 06 12:55:13 PM PDT 24
Finished Jun 06 12:55:16 PM PDT 24
Peak memory 191724 kb
Host smart-145fad6e-8582-451a-9c78-6ffa4484d0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769547861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2769547861
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2317973924
Short name T284
Test name
Test status
Simulation time 16480708366 ps
CPU time 4.33 seconds
Started Jun 06 12:55:14 PM PDT 24
Finished Jun 06 12:55:20 PM PDT 24
Peak memory 191872 kb
Host smart-d0c0e304-48f9-4bca-bc19-3d885f6a5ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317973924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2317973924
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2118135966
Short name T47
Test name
Test status
Simulation time 449142612 ps
CPU time 0.91 seconds
Started Jun 06 12:55:15 PM PDT 24
Finished Jun 06 12:55:18 PM PDT 24
Peak memory 191752 kb
Host smart-151f56c3-33bc-4710-921b-69cf19b20a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118135966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2118135966
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.433155103
Short name T241
Test name
Test status
Simulation time 6658720465 ps
CPU time 3.3 seconds
Started Jun 06 12:55:11 PM PDT 24
Finished Jun 06 12:55:15 PM PDT 24
Peak memory 191924 kb
Host smart-7675f225-3a03-4325-9b21-c6ed24678953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433155103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.433155103
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2689743993
Short name T216
Test name
Test status
Simulation time 577882687 ps
CPU time 0.79 seconds
Started Jun 06 12:55:18 PM PDT 24
Finished Jun 06 12:55:21 PM PDT 24
Peak memory 191772 kb
Host smart-ccb9792e-6068-4f9c-bd6a-920665125c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689743993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2689743993
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1650694585
Short name T186
Test name
Test status
Simulation time 577874501 ps
CPU time 0.96 seconds
Started Jun 06 12:55:14 PM PDT 24
Finished Jun 06 12:55:17 PM PDT 24
Peak memory 196396 kb
Host smart-478c8ee5-66d9-4198-a0bd-5eedfe959289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650694585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1650694585
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1109013733
Short name T263
Test name
Test status
Simulation time 23962416072 ps
CPU time 8.51 seconds
Started Jun 06 12:55:18 PM PDT 24
Finished Jun 06 12:55:28 PM PDT 24
Peak memory 191892 kb
Host smart-a8a377b9-86af-4e7c-9dc2-33d43091d032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109013733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1109013733
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3405547223
Short name T209
Test name
Test status
Simulation time 400569655 ps
CPU time 0.7 seconds
Started Jun 06 12:55:14 PM PDT 24
Finished Jun 06 12:55:16 PM PDT 24
Peak memory 191752 kb
Host smart-b024c42f-e7e0-48dc-91e0-8b9c0b3e7204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405547223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3405547223
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2244724206
Short name T207
Test name
Test status
Simulation time 50489548934 ps
CPU time 78.98 seconds
Started Jun 06 12:55:15 PM PDT 24
Finished Jun 06 12:56:36 PM PDT 24
Peak memory 191888 kb
Host smart-5ffd99f7-efd8-4156-8cea-210d8f60789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244724206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2244724206
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2669568517
Short name T226
Test name
Test status
Simulation time 498536726 ps
CPU time 1.34 seconds
Started Jun 06 12:55:13 PM PDT 24
Finished Jun 06 12:55:15 PM PDT 24
Peak memory 191672 kb
Host smart-1f535168-ba24-40b8-ac07-3a2b3f6cbadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669568517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2669568517
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1908788160
Short name T251
Test name
Test status
Simulation time 31914104743 ps
CPU time 4.63 seconds
Started Jun 06 12:55:24 PM PDT 24
Finished Jun 06 12:55:30 PM PDT 24
Peak memory 191852 kb
Host smart-4fa03283-d143-42f5-9aca-57f97877239d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908788160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1908788160
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3157422784
Short name T253
Test name
Test status
Simulation time 588455240 ps
CPU time 0.69 seconds
Started Jun 06 12:55:24 PM PDT 24
Finished Jun 06 12:55:26 PM PDT 24
Peak memory 191744 kb
Host smart-122393ae-58fa-429c-82f4-57c167d0ae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157422784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3157422784
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.311285501
Short name T245
Test name
Test status
Simulation time 4386633096 ps
CPU time 7.09 seconds
Started Jun 06 12:54:47 PM PDT 24
Finished Jun 06 12:54:55 PM PDT 24
Peak memory 191876 kb
Host smart-6f0082d5-020d-47e3-9160-f10974a75dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311285501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.311285501
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1320024325
Short name T13
Test name
Test status
Simulation time 4346961995 ps
CPU time 4.22 seconds
Started Jun 06 12:54:44 PM PDT 24
Finished Jun 06 12:54:50 PM PDT 24
Peak memory 215608 kb
Host smart-87f6b71b-d8b6-4e31-b2b8-f333bbd121c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320024325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1320024325
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2921076766
Short name T213
Test name
Test status
Simulation time 444546212 ps
CPU time 1.2 seconds
Started Jun 06 12:54:44 PM PDT 24
Finished Jun 06 12:54:47 PM PDT 24
Peak memory 191720 kb
Host smart-8d915f5b-bf8f-47b9-a842-83347ca7f750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921076766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2921076766
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3022134678
Short name T4
Test name
Test status
Simulation time 389111576 ps
CPU time 1.24 seconds
Started Jun 06 12:55:26 PM PDT 24
Finished Jun 06 12:55:28 PM PDT 24
Peak memory 196340 kb
Host smart-7600292f-e594-4b3c-acb5-34bb68b0029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022134678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3022134678
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3049699662
Short name T264
Test name
Test status
Simulation time 34066995341 ps
CPU time 14.87 seconds
Started Jun 06 12:55:18 PM PDT 24
Finished Jun 06 12:55:35 PM PDT 24
Peak memory 191788 kb
Host smart-f0285374-06cc-44a8-aca7-2e09619545ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049699662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3049699662
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2958986837
Short name T240
Test name
Test status
Simulation time 570991026 ps
CPU time 0.98 seconds
Started Jun 06 12:55:24 PM PDT 24
Finished Jun 06 12:55:26 PM PDT 24
Peak memory 191580 kb
Host smart-4671f195-59ae-4b08-9c62-403adaea7f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958986837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2958986837
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2744712327
Short name T249
Test name
Test status
Simulation time 304499393887 ps
CPU time 249.97 seconds
Started Jun 06 12:55:20 PM PDT 24
Finished Jun 06 12:59:31 PM PDT 24
Peak memory 191848 kb
Host smart-357a7944-2371-48e8-98ea-24271e3f082a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744712327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2744712327
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1718982992
Short name T259
Test name
Test status
Simulation time 24303714843 ps
CPU time 11.08 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 12:55:34 PM PDT 24
Peak memory 191816 kb
Host smart-4761df08-93ea-43dc-9027-a3008f682ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718982992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1718982992
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.811730414
Short name T258
Test name
Test status
Simulation time 532992358 ps
CPU time 1.46 seconds
Started Jun 06 12:55:21 PM PDT 24
Finished Jun 06 12:55:24 PM PDT 24
Peak memory 191796 kb
Host smart-4d109602-cc2c-4187-a6a9-5ea2e6efe47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811730414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.811730414
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.4091769541
Short name T221
Test name
Test status
Simulation time 791407031 ps
CPU time 0.85 seconds
Started Jun 06 12:55:21 PM PDT 24
Finished Jun 06 12:55:24 PM PDT 24
Peak memory 191776 kb
Host smart-56de670c-c686-4379-abe6-3c074f585b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091769541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.4091769541
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.791547603
Short name T203
Test name
Test status
Simulation time 432006673 ps
CPU time 1.24 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 12:55:25 PM PDT 24
Peak memory 191700 kb
Host smart-9f3fba63-d241-4d34-91a5-aad5724f492e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791547603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.791547603
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3453061384
Short name T26
Test name
Test status
Simulation time 81510108618 ps
CPU time 870.66 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 01:09:54 PM PDT 24
Peak memory 214984 kb
Host smart-5b7fd1f5-8393-46ef-8111-6f8f0857602e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453061384 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3453061384
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3388219526
Short name T281
Test name
Test status
Simulation time 28288338480 ps
CPU time 5.05 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 12:55:29 PM PDT 24
Peak memory 191836 kb
Host smart-8e6dee36-2e9b-453c-b7a0-93a7bb9ca8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388219526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3388219526
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2707821606
Short name T211
Test name
Test status
Simulation time 402240071 ps
CPU time 0.78 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 12:55:25 PM PDT 24
Peak memory 191752 kb
Host smart-89a9e1be-9a38-464b-808b-e5caaf535942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707821606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2707821606
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1886634428
Short name T217
Test name
Test status
Simulation time 1544651273 ps
CPU time 1.84 seconds
Started Jun 06 12:55:21 PM PDT 24
Finished Jun 06 12:55:24 PM PDT 24
Peak memory 191728 kb
Host smart-bd78ceec-4f3a-41b1-806b-f9ce067e33ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886634428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1886634428
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.670924568
Short name T206
Test name
Test status
Simulation time 608567985 ps
CPU time 0.81 seconds
Started Jun 06 12:55:21 PM PDT 24
Finished Jun 06 12:55:24 PM PDT 24
Peak memory 191700 kb
Host smart-9a015e32-162a-43f7-a387-b3973bd5ca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670924568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.670924568
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2186801669
Short name T262
Test name
Test status
Simulation time 8739935363 ps
CPU time 2.92 seconds
Started Jun 06 12:55:26 PM PDT 24
Finished Jun 06 12:55:30 PM PDT 24
Peak memory 191836 kb
Host smart-89feee7b-4467-4ac4-b031-3081ceae0579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186801669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2186801669
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1688703756
Short name T215
Test name
Test status
Simulation time 408497818 ps
CPU time 0.71 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 12:55:25 PM PDT 24
Peak memory 191776 kb
Host smart-1a874c29-424a-49bc-babe-8cfe8814f48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688703756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1688703756
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2917447397
Short name T55
Test name
Test status
Simulation time 456928013 ps
CPU time 0.93 seconds
Started Jun 06 12:55:32 PM PDT 24
Finished Jun 06 12:55:34 PM PDT 24
Peak memory 196384 kb
Host smart-11f4ce96-bdf7-486b-969e-14e70a20373b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917447397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2917447397
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.4229796020
Short name T40
Test name
Test status
Simulation time 6470233233 ps
CPU time 10.3 seconds
Started Jun 06 12:55:22 PM PDT 24
Finished Jun 06 12:55:34 PM PDT 24
Peak memory 191832 kb
Host smart-5d608231-801c-4cbd-acf4-a987808b1846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229796020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.4229796020
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2307662906
Short name T260
Test name
Test status
Simulation time 474460653 ps
CPU time 1.33 seconds
Started Jun 06 12:55:23 PM PDT 24
Finished Jun 06 12:55:26 PM PDT 24
Peak memory 191724 kb
Host smart-c3880664-3480-4e2b-acfe-05a9b873ba54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307662906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2307662906
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.570891579
Short name T49
Test name
Test status
Simulation time 2562233777 ps
CPU time 0.94 seconds
Started Jun 06 12:55:36 PM PDT 24
Finished Jun 06 12:55:38 PM PDT 24
Peak memory 191896 kb
Host smart-1fd91b96-6461-4dfc-9996-ab289efccefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570891579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.570891579
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1004507475
Short name T252
Test name
Test status
Simulation time 475219757 ps
CPU time 0.75 seconds
Started Jun 06 12:55:33 PM PDT 24
Finished Jun 06 12:55:35 PM PDT 24
Peak memory 191760 kb
Host smart-c1b1d7a7-b359-4a28-a1a5-6aef08f75746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004507475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1004507475
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2362353435
Short name T181
Test name
Test status
Simulation time 402006098 ps
CPU time 1.26 seconds
Started Jun 06 12:55:32 PM PDT 24
Finished Jun 06 12:55:34 PM PDT 24
Peak memory 196404 kb
Host smart-7baac2d9-d66f-4a9f-b705-b739c1ea7a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362353435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2362353435
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1763949294
Short name T54
Test name
Test status
Simulation time 40073566883 ps
CPU time 17.08 seconds
Started Jun 06 12:55:33 PM PDT 24
Finished Jun 06 12:55:51 PM PDT 24
Peak memory 191880 kb
Host smart-1af6af08-d443-4873-8f6d-294037ad44b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763949294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1763949294
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3129859762
Short name T219
Test name
Test status
Simulation time 463543491 ps
CPU time 0.67 seconds
Started Jun 06 12:55:31 PM PDT 24
Finished Jun 06 12:55:33 PM PDT 24
Peak memory 191732 kb
Host smart-5142ceea-d16d-44d1-9b5a-220303da4719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129859762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3129859762
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3875127758
Short name T205
Test name
Test status
Simulation time 21422982536 ps
CPU time 8.41 seconds
Started Jun 06 12:55:31 PM PDT 24
Finished Jun 06 12:55:41 PM PDT 24
Peak memory 191844 kb
Host smart-a8448a79-5c7a-4316-943a-1dd784508692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875127758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3875127758
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.369121344
Short name T266
Test name
Test status
Simulation time 370182495 ps
CPU time 0.82 seconds
Started Jun 06 12:55:30 PM PDT 24
Finished Jun 06 12:55:32 PM PDT 24
Peak memory 191692 kb
Host smart-edfcc2a2-4f0a-43ee-bc4f-98590d446e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369121344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.369121344
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.807696954
Short name T256
Test name
Test status
Simulation time 8761723281 ps
CPU time 3.91 seconds
Started Jun 06 12:54:46 PM PDT 24
Finished Jun 06 12:54:51 PM PDT 24
Peak memory 191896 kb
Host smart-b1a9354d-b2ae-419b-adec-61b4947ee774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807696954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.807696954
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2466177980
Short name T261
Test name
Test status
Simulation time 574333734 ps
CPU time 0.81 seconds
Started Jun 06 12:54:42 PM PDT 24
Finished Jun 06 12:54:44 PM PDT 24
Peak memory 191692 kb
Host smart-ef532441-2d36-4e9a-9262-f3452dd1347c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466177980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2466177980
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3896224681
Short name T41
Test name
Test status
Simulation time 9359009602 ps
CPU time 7.59 seconds
Started Jun 06 12:54:48 PM PDT 24
Finished Jun 06 12:54:56 PM PDT 24
Peak memory 191872 kb
Host smart-7cc55a51-de80-4042-b74b-c026eb768261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896224681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3896224681
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2663637866
Short name T272
Test name
Test status
Simulation time 465837653 ps
CPU time 1.25 seconds
Started Jun 06 12:54:46 PM PDT 24
Finished Jun 06 12:54:48 PM PDT 24
Peak memory 191764 kb
Host smart-e5fec443-8ff6-4cc6-ad39-eb9672b130e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663637866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2663637866
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2381839684
Short name T233
Test name
Test status
Simulation time 59002478707 ps
CPU time 43.85 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:55:30 PM PDT 24
Peak memory 191852 kb
Host smart-059bf9a8-b86e-4bf9-a225-0aff31b606ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381839684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2381839684
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.766983960
Short name T222
Test name
Test status
Simulation time 517881606 ps
CPU time 1.47 seconds
Started Jun 06 12:54:48 PM PDT 24
Finished Jun 06 12:54:50 PM PDT 24
Peak memory 191728 kb
Host smart-83e426dd-7cd1-47fe-8800-adba5668a7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766983960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.766983960
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1155143663
Short name T1
Test name
Test status
Simulation time 14626175200 ps
CPU time 22.6 seconds
Started Jun 06 12:54:45 PM PDT 24
Finished Jun 06 12:55:09 PM PDT 24
Peak memory 191904 kb
Host smart-4ad70541-546d-4b99-8874-8e02b90b041c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155143663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1155143663
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.815516603
Short name T239
Test name
Test status
Simulation time 516280552 ps
CPU time 1.29 seconds
Started Jun 06 12:54:46 PM PDT 24
Finished Jun 06 12:54:48 PM PDT 24
Peak memory 191760 kb
Host smart-7f13e165-f98c-44b8-8d3f-febf2276f719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815516603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.815516603
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1792417913
Short name T243
Test name
Test status
Simulation time 5798097146 ps
CPU time 4.3 seconds
Started Jun 06 12:54:52 PM PDT 24
Finished Jun 06 12:54:58 PM PDT 24
Peak memory 191880 kb
Host smart-a15bb203-a08b-4b94-a081-d2886c3f7bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792417913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1792417913
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.244359083
Short name T254
Test name
Test status
Simulation time 354031823 ps
CPU time 1.12 seconds
Started Jun 06 12:54:52 PM PDT 24
Finished Jun 06 12:54:54 PM PDT 24
Peak memory 191716 kb
Host smart-986dab63-b602-49f5-b6e1-bbb8d31f4371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244359083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.244359083
Directory /workspace/9.aon_timer_smoke/latest
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