Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	30978	1		T1	146		T2	11		T3	14
bark[1]	664	1		T17	30		T121	52		T185	14
bark[2]	320	1		T15	30		T17	21		T36	21
bark[3]	767	1		T15	39		T107	42		T164	101
bark[4]	444	1		T1	21		T8	21		T117	19
bark[5]	520	1		T1	71		T32	181		T171	21
bark[6]	261	1		T80	184		T94	21		T110	21
bark[7]	407	1		T13	21		T32	99		T77	30
bark[8]	846	1		T16	14		T18	30		T117	21
bark[9]	518	1		T32	21		T40	14		T104	21
bark[10]	603	1		T13	26		T32	21		T33	21
bark[11]	954	1		T15	84		T18	21		T31	339
bark[12]	1063	1		T1	21		T18	413		T144	279
bark[13]	607	1		T13	21		T18	116		T36	21
bark[14]	1176	1		T13	557		T17	31		T117	21
bark[15]	342	1		T8	21		T18	21		T36	21
bark[16]	238	1		T13	26		T36	65		T114	42
bark[17]	561	1		T38	14		T17	32		T144	183
bark[18]	337	1		T16	21		T33	21		T151	21
bark[19]	481	1		T13	26		T18	134		T104	14
bark[20]	603	1		T17	21		T107	21		T32	21
bark[21]	263	1		T10	21		T32	21		T117	31
bark[22]	496	1		T7	14		T107	31		T33	224
bark[23]	537	1		T9	14		T10	21		T74	248
bark[24]	154	1		T8	26		T126	21		T131	21
bark[25]	576	1		T74	21		T153	31		T97	26
bark[26]	251	1		T13	35		T107	63		T114	21
bark[27]	957	1		T16	21		T34	265		T145	26
bark[28]	447	1		T10	21		T23	14		T32	21
bark[29]	353	1		T1	21		T32	14		T164	21
bark[30]	238	1		T114	21		T77	30		T106	33
bark[31]	277	1		T36	21		T173	14		T106	21
bark_0	4476	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	30952	1		T1	145		T2	10		T4	10
bite[1]	677	1		T13	52		T77	21		T88	46
bite[2]	1314	1		T13	556		T17	31		T33	67
bite[3]	505	1		T7	13		T18	51		T96	21
bite[4]	369	1		T1	71		T17	21		T87	72
bite[5]	393	1		T107	21		T104	13		T163	13
bite[6]	343	1		T33	21		T151	83		T153	30
bite[7]	397	1		T144	95		T113	13		T114	21
bite[8]	244	1		T36	57		T74	21		T75	13
bite[9]	876	1		T10	21		T17	31		T31	338
bite[10]	492	1		T13	21		T32	180		T33	21
bite[11]	1020	1		T33	223		T74	21		T77	30
bite[12]	474	1		T13	25		T106	21		T50	21
bite[13]	738	1		T13	34		T18	133		T107	31
bite[14]	364	1		T32	98		T173	13		T153	47
bite[15]	487	1		T10	21		T32	21		T78	54
bite[16]	412	1		T107	63		T40	13		T144	156
bite[17]	167	1		T8	21		T16	21		T88	21
bite[18]	479	1		T32	21		T80	21		T153	21
bite[19]	710	1		T18	190		T114	62		T77	30
bite[20]	232	1		T1	21		T18	21		T32	21
bite[21]	514	1		T38	13		T164	101		T114	47
bite[22]	470	1		T97	26		T95	21		T140	21
bite[23]	444	1		T1	21		T15	30		T16	13
bite[24]	262	1		T107	42		T77	42		T104	21
bite[25]	450	1		T8	26		T144	21		T106	21
bite[26]	562	1		T15	39		T18	115		T145	26
bite[27]	202	1		T1	21		T16	21		T32	21
bite[28]	501	1		T13	21		T36	106		T74	26
bite[29]	738	1		T17	21		T117	18		T111	21
bite[30]	208	1		T9	13		T23	13		T32	13
bite[31]	730	1		T3	13		T8	21		T10	21
bite_0	4989	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	51715	1		T1	287		T2	18		T3	21

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	977	1		T13	40		T18	108		T107	65
prescale[1]	960	1		T13	272		T32	19		T36	58
prescale[2]	753	1		T39	9		T33	37		T35	47
prescale[3]	1194	1		T13	19		T15	19		T17	2
prescale[4]	1230	1		T10	23		T13	40		T17	132
prescale[5]	498	1		T13	19		T18	37		T31	134
prescale[6]	912	1		T18	71		T31	176		T117	23
prescale[7]	717	1		T13	45		T32	2		T145	9
prescale[8]	830	1		T17	58		T37	24		T144	2
prescale[9]	1223	1		T1	69		T6	9		T16	40
prescale[10]	608	1		T32	95		T33	66		T74	19
prescale[11]	851	1		T13	66		T18	28		T32	111
prescale[12]	1019	1		T13	211		T18	21		T107	18
prescale[13]	857	1		T5	9		T17	94		T18	2
prescale[14]	937	1		T18	50		T171	40		T33	2
prescale[15]	800	1		T15	32		T16	98		T31	19
prescale[16]	401	1		T31	94		T36	28		T78	37
prescale[17]	508	1		T15	45		T17	19		T34	2
prescale[18]	619	1		T8	28		T18	2		T31	24
prescale[19]	334	1		T32	2		T145	37		T36	4
prescale[20]	1085	1		T1	19		T13	2		T18	19
prescale[21]	1121	1		T13	63		T18	19		T33	2
prescale[22]	813	1		T8	37		T10	37		T13	19
prescale[23]	735	1		T18	28		T164	19		T37	149
prescale[24]	1038	1		T13	2		T18	21		T164	91
prescale[25]	615	1		T1	55		T12	9		T32	2
prescale[26]	420	1		T17	9		T33	30		T117	32
prescale[27]	550	1		T145	19		T36	177		T37	19
prescale[28]	951	1		T8	23		T13	40		T15	28
prescale[29]	898	1		T13	2		T18	28		T31	40
prescale[30]	518	1		T32	62		T164	19		T34	30
prescale[31]	1204	1		T18	67		T31	46		T32	37
prescale_0	25539	1		T1	144		T2	18		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	39067	1		T1	192		T2	18		T3	9
auto[1]	12648	1		T1	95		T3	12		T5	10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	51715	1		T1	287		T2	18		T3	21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30414	1		T1	167		T2	13		T3	1
wkup[1]	243	1		T31	21		T114	21		T80	26
wkup[2]	210	1		T31	21		T32	21		T36	42
wkup[3]	329	1		T13	26		T15	21		T32	21
wkup[4]	360	1		T13	42		T18	8		T32	26
wkup[5]	329	1		T15	30		T18	21		T31	15
wkup[6]	285	1		T31	60		T164	21		T33	21
wkup[7]	375	1		T18	21		T96	21		T121	21
wkup[8]	313	1		T8	21		T32	26		T144	21
wkup[9]	288	1		T18	21		T33	21		T117	31
wkup[10]	273	1		T13	21		T36	36		T74	21
wkup[11]	254	1		T40	15		T74	47		T104	26
wkup[12]	231	1		T32	21		T81	21		T153	21
wkup[13]	354	1		T13	21		T15	26		T164	21
wkup[14]	304	1		T37	21		T144	30		T88	21
wkup[15]	162	1		T10	21		T18	35		T31	21
wkup[16]	165	1		T17	30		T89	42		T132	15
wkup[17]	330	1		T107	42		T144	26		T80	21
wkup[18]	236	1		T31	21		T37	21		T144	21
wkup[19]	317	1		T8	26		T13	21		T18	21
wkup[20]	270	1		T18	42		T77	30		T81	21
wkup[21]	193	1		T13	21		T18	26		T34	21
wkup[22]	185	1		T18	30		T74	21		T80	21
wkup[23]	313	1		T8	21		T13	21		T17	21
wkup[24]	299	1		T9	15		T31	35		T32	21
wkup[25]	318	1		T3	15		T23	15		T32	21
wkup[26]	179	1		T1	21		T36	29		T108	15
wkup[27]	143	1		T18	21		T106	34		T118	42
wkup[28]	239	1		T171	21		T80	8		T97	36
wkup[29]	322	1		T16	15		T31	26		T145	26
wkup[30]	471	1		T10	21		T13	21		T17	21
wkup[31]	164	1		T17	30		T117	20		T165	21
wkup[32]	239	1		T18	21		T171	21		T36	62
wkup[33]	250	1		T18	21		T32	21		T151	31
wkup[34]	423	1		T13	21		T32	65		T37	8
wkup[35]	186	1		T17	21		T18	21		T121	30
wkup[36]	166	1		T13	26		T37	21		T106	21
wkup[37]	191	1		T38	15		T87	26		T151	21
wkup[38]	187	1		T18	26		T33	26		T144	21
wkup[39]	264	1		T16	21		T32	36		T37	21
wkup[40]	261	1		T35	21		T77	42		T87	26
wkup[41]	276	1		T80	21		T87	21		T88	21
wkup[42]	217	1		T13	57		T32	21		T81	21
wkup[43]	378	1		T1	21		T13	26		T33	15
wkup[44]	323	1		T32	30		T144	21		T77	21
wkup[45]	304	1		T13	21		T18	30		T151	21
wkup[46]	305	1		T1	31		T18	21		T144	35
wkup[47]	278	1		T1	21		T17	21		T36	21
wkup[48]	255	1		T16	21		T32	21		T35	8
wkup[49]	141	1		T144	21		T87	21		T88	42
wkup[50]	415	1		T17	21		T32	21		T144	42
wkup[51]	449	1		T13	52		T33	21		T144	77
wkup[52]	290	1		T1	21		T13	21		T36	21
wkup[53]	196	1		T107	31		T33	8		T34	21
wkup[54]	384	1		T107	21		T31	8		T37	21
wkup[55]	336	1		T36	21		T74	21		T159	21
wkup[56]	371	1		T7	15		T13	21		T32	21
wkup[57]	263	1		T13	21		T18	21		T107	21
wkup[58]	370	1		T17	31		T114	21		T76	15
wkup[59]	338	1		T18	30		T31	31		T34	21
wkup[60]	223	1		T32	21		T118	26		T41	68
wkup[61]	352	1		T13	30		T15	21		T32	42
wkup[62]	273	1		T18	21		T35	21		T74	21
wkup[63]	382	1		T13	21		T16	21		T18	52
wkup_0	3561	1		T1	5		T2	5		T3	5