Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.23 99.33 93.67 100.00 98.40 99.51 50.48


Total test records in report: 418
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T278 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2508817066 Jun 07 08:28:53 PM PDT 24 Jun 07 08:29:10 PM PDT 24 502894654 ps
T279 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4044251806 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:20 PM PDT 24 440918822 ps
T280 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1505329432 Jun 07 08:28:30 PM PDT 24 Jun 07 08:28:45 PM PDT 24 372197086 ps
T281 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1936861922 Jun 07 08:28:52 PM PDT 24 Jun 07 08:29:08 PM PDT 24 459680640 ps
T282 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4130999784 Jun 07 08:28:39 PM PDT 24 Jun 07 08:28:52 PM PDT 24 511439231 ps
T283 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.676640638 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:11 PM PDT 24 353498151 ps
T284 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3755201267 Jun 07 08:28:52 PM PDT 24 Jun 07 08:29:08 PM PDT 24 320788461 ps
T285 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1145439816 Jun 07 08:28:48 PM PDT 24 Jun 07 08:29:05 PM PDT 24 352773324 ps
T54 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3712861805 Jun 07 08:28:52 PM PDT 24 Jun 07 08:29:09 PM PDT 24 380070269 ps
T68 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1183940419 Jun 07 08:28:50 PM PDT 24 Jun 07 08:29:06 PM PDT 24 411391834 ps
T286 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.29091570 Jun 07 08:28:53 PM PDT 24 Jun 07 08:29:10 PM PDT 24 544458568 ps
T287 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2537809280 Jun 07 08:28:38 PM PDT 24 Jun 07 08:28:52 PM PDT 24 496020756 ps
T55 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3386146350 Jun 07 08:28:45 PM PDT 24 Jun 07 08:28:59 PM PDT 24 328421761 ps
T29 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1827521815 Jun 07 08:28:19 PM PDT 24 Jun 07 08:28:42 PM PDT 24 8896935138 ps
T288 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3796761152 Jun 07 08:28:46 PM PDT 24 Jun 07 08:28:59 PM PDT 24 439294487 ps
T289 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.117204397 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:15 PM PDT 24 402323964 ps
T290 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.302218706 Jun 07 08:28:30 PM PDT 24 Jun 07 08:28:45 PM PDT 24 421098464 ps
T69 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1756352412 Jun 07 08:28:25 PM PDT 24 Jun 07 08:28:44 PM PDT 24 1367931247 ps
T291 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1605816851 Jun 07 08:28:44 PM PDT 24 Jun 07 08:28:58 PM PDT 24 443102865 ps
T70 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2984174307 Jun 07 08:28:51 PM PDT 24 Jun 07 08:29:07 PM PDT 24 547096600 ps
T292 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1076737995 Jun 07 08:28:56 PM PDT 24 Jun 07 08:29:14 PM PDT 24 563617380 ps
T293 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3591011688 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:15 PM PDT 24 422050157 ps
T294 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.267394346 Jun 07 08:28:36 PM PDT 24 Jun 07 08:28:51 PM PDT 24 569173619 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3586287580 Jun 07 08:28:41 PM PDT 24 Jun 07 08:28:56 PM PDT 24 1127992176 ps
T295 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2691215872 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:13 PM PDT 24 461353198 ps
T296 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.208467259 Jun 07 08:28:25 PM PDT 24 Jun 07 08:28:42 PM PDT 24 1177751592 ps
T57 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3336150477 Jun 07 08:28:46 PM PDT 24 Jun 07 08:29:00 PM PDT 24 541606656 ps
T71 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2371097566 Jun 07 08:28:44 PM PDT 24 Jun 07 08:28:59 PM PDT 24 2651327852 ps
T297 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3207548100 Jun 07 08:28:39 PM PDT 24 Jun 07 08:28:52 PM PDT 24 622923567 ps
T30 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3280533891 Jun 07 08:28:48 PM PDT 24 Jun 07 08:29:08 PM PDT 24 4585331136 ps
T58 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1998991138 Jun 07 08:28:34 PM PDT 24 Jun 07 08:28:48 PM PDT 24 550249816 ps
T72 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1869338584 Jun 07 08:28:51 PM PDT 24 Jun 07 08:29:08 PM PDT 24 2465650185 ps
T188 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.664750760 Jun 07 08:28:56 PM PDT 24 Jun 07 08:29:26 PM PDT 24 7757515703 ps
T298 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.37647843 Jun 07 08:28:53 PM PDT 24 Jun 07 08:29:10 PM PDT 24 466360993 ps
T299 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1140111453 Jun 07 08:28:50 PM PDT 24 Jun 07 08:29:06 PM PDT 24 263627602 ps
T73 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2828999295 Jun 07 08:28:50 PM PDT 24 Jun 07 08:29:06 PM PDT 24 492990857 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1610516700 Jun 07 08:28:36 PM PDT 24 Jun 07 08:28:49 PM PDT 24 411148441 ps
T300 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3124281762 Jun 07 08:28:51 PM PDT 24 Jun 07 08:29:07 PM PDT 24 521361638 ps
T301 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1044277637 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:20 PM PDT 24 984093489 ps
T302 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.509972946 Jun 07 08:28:44 PM PDT 24 Jun 07 08:28:57 PM PDT 24 506281692 ps
T303 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.4233773660 Jun 07 08:28:50 PM PDT 24 Jun 07 08:29:06 PM PDT 24 1134342289 ps
T304 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.897199054 Jun 07 08:28:48 PM PDT 24 Jun 07 08:29:03 PM PDT 24 337535353 ps
T189 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2031519357 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:18 PM PDT 24 4133247569 ps
T305 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.832841385 Jun 07 08:28:48 PM PDT 24 Jun 07 08:29:05 PM PDT 24 344158805 ps
T306 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3051559623 Jun 07 08:28:47 PM PDT 24 Jun 07 08:29:03 PM PDT 24 1190319186 ps
T307 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3055363799 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:12 PM PDT 24 287677430 ps
T191 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3360724165 Jun 07 08:28:43 PM PDT 24 Jun 07 08:29:03 PM PDT 24 7935198179 ps
T308 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.557979412 Jun 07 08:28:40 PM PDT 24 Jun 07 08:28:53 PM PDT 24 563590182 ps
T309 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3288713328 Jun 07 08:28:51 PM PDT 24 Jun 07 08:29:10 PM PDT 24 2332647309 ps
T310 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3779307898 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:11 PM PDT 24 313502702 ps
T311 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.132762011 Jun 07 08:28:44 PM PDT 24 Jun 07 08:29:04 PM PDT 24 4333976613 ps
T64 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1493721135 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:15 PM PDT 24 297829144 ps
T312 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4083838896 Jun 07 08:28:48 PM PDT 24 Jun 07 08:29:03 PM PDT 24 1691293415 ps
T313 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3011024336 Jun 07 08:28:53 PM PDT 24 Jun 07 08:29:11 PM PDT 24 5007617008 ps
T314 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1180433089 Jun 07 08:28:48 PM PDT 24 Jun 07 08:29:04 PM PDT 24 567943156 ps
T315 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2149427706 Jun 07 08:28:48 PM PDT 24 Jun 07 08:29:03 PM PDT 24 1090969625 ps
T316 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1757932350 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:12 PM PDT 24 408755719 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.767337762 Jun 07 08:28:42 PM PDT 24 Jun 07 08:28:56 PM PDT 24 449276991 ps
T317 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4261336648 Jun 07 08:28:50 PM PDT 24 Jun 07 08:29:06 PM PDT 24 524853929 ps
T318 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2696928576 Jun 07 08:28:55 PM PDT 24 Jun 07 08:29:12 PM PDT 24 410979487 ps
T319 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2685859614 Jun 07 08:28:34 PM PDT 24 Jun 07 08:28:47 PM PDT 24 346159308 ps
T320 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2954418429 Jun 07 08:28:44 PM PDT 24 Jun 07 08:28:59 PM PDT 24 436287492 ps
T321 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2463729108 Jun 07 08:28:44 PM PDT 24 Jun 07 08:28:57 PM PDT 24 498744996 ps
T322 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.416951471 Jun 07 08:29:00 PM PDT 24 Jun 07 08:29:18 PM PDT 24 403514258 ps
T323 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2385021858 Jun 07 08:28:31 PM PDT 24 Jun 07 08:28:46 PM PDT 24 383649137 ps
T324 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1501554149 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:17 PM PDT 24 371466801 ps
T192 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.384975395 Jun 07 08:28:48 PM PDT 24 Jun 07 08:29:04 PM PDT 24 4632632864 ps
T60 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1965924439 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:17 PM PDT 24 457152195 ps
T325 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1293328084 Jun 07 08:28:40 PM PDT 24 Jun 07 08:28:57 PM PDT 24 8998344910 ps
T326 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1071036479 Jun 07 08:28:49 PM PDT 24 Jun 07 08:29:05 PM PDT 24 480584469 ps
T327 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.913466839 Jun 07 08:28:55 PM PDT 24 Jun 07 08:29:14 PM PDT 24 291191712 ps
T328 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3434767152 Jun 07 08:28:45 PM PDT 24 Jun 07 08:28:59 PM PDT 24 459893522 ps
T329 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3505290785 Jun 07 08:28:46 PM PDT 24 Jun 07 08:29:01 PM PDT 24 4553822918 ps
T330 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.521870299 Jun 07 08:28:47 PM PDT 24 Jun 07 08:29:01 PM PDT 24 339691646 ps
T331 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.814656423 Jun 07 08:28:43 PM PDT 24 Jun 07 08:28:56 PM PDT 24 369571981 ps
T332 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3426916860 Jun 07 08:28:56 PM PDT 24 Jun 07 08:29:14 PM PDT 24 370161409 ps
T61 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.624407354 Jun 07 08:28:44 PM PDT 24 Jun 07 08:28:57 PM PDT 24 328692206 ps
T333 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1995814693 Jun 07 08:28:47 PM PDT 24 Jun 07 08:29:01 PM PDT 24 550078189 ps
T334 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2002730422 Jun 07 08:28:49 PM PDT 24 Jun 07 08:29:05 PM PDT 24 443852032 ps
T335 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.766557575 Jun 07 08:28:49 PM PDT 24 Jun 07 08:29:05 PM PDT 24 505337131 ps
T336 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3194319376 Jun 07 08:28:44 PM PDT 24 Jun 07 08:28:58 PM PDT 24 380949113 ps
T337 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1456640283 Jun 07 08:28:53 PM PDT 24 Jun 07 08:29:10 PM PDT 24 540567915 ps
T338 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.805834690 Jun 07 08:28:46 PM PDT 24 Jun 07 08:29:00 PM PDT 24 577199842 ps
T339 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1494100416 Jun 07 08:28:40 PM PDT 24 Jun 07 08:28:55 PM PDT 24 641487968 ps
T340 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.828781736 Jun 07 08:28:49 PM PDT 24 Jun 07 08:29:05 PM PDT 24 356843817 ps
T62 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1153717654 Jun 07 08:28:46 PM PDT 24 Jun 07 08:29:00 PM PDT 24 386695885 ps
T341 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.266452322 Jun 07 08:28:53 PM PDT 24 Jun 07 08:29:10 PM PDT 24 408232558 ps
T342 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.142617928 Jun 07 08:28:29 PM PDT 24 Jun 07 08:28:45 PM PDT 24 512370937 ps
T343 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3668883467 Jun 07 08:28:46 PM PDT 24 Jun 07 08:29:00 PM PDT 24 343627577 ps
T344 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.295841873 Jun 07 08:28:43 PM PDT 24 Jun 07 08:28:58 PM PDT 24 552554522 ps
T345 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3896616010 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:15 PM PDT 24 416864917 ps
T346 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.675770835 Jun 07 08:28:51 PM PDT 24 Jun 07 08:29:08 PM PDT 24 942268020 ps
T347 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4008214642 Jun 07 08:28:35 PM PDT 24 Jun 07 08:28:49 PM PDT 24 578800231 ps
T348 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2808743514 Jun 07 08:28:45 PM PDT 24 Jun 07 08:28:59 PM PDT 24 515654594 ps
T349 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2388495 Jun 07 08:28:56 PM PDT 24 Jun 07 08:29:25 PM PDT 24 484288033 ps
T350 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1070442569 Jun 07 08:28:43 PM PDT 24 Jun 07 08:29:00 PM PDT 24 2427021075 ps
T351 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1203121174 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:15 PM PDT 24 345767881 ps
T352 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1672814727 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:10 PM PDT 24 327481604 ps
T353 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4119713395 Jun 07 08:28:46 PM PDT 24 Jun 07 08:29:02 PM PDT 24 1467732578 ps
T354 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2367015401 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:17 PM PDT 24 310554806 ps
T355 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1835032342 Jun 07 08:28:46 PM PDT 24 Jun 07 08:29:02 PM PDT 24 2117241869 ps
T356 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3612601165 Jun 07 08:28:44 PM PDT 24 Jun 07 08:28:58 PM PDT 24 329574431 ps
T357 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3356528231 Jun 07 08:28:35 PM PDT 24 Jun 07 08:28:49 PM PDT 24 438542233 ps
T358 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2023474373 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:12 PM PDT 24 370700289 ps
T359 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3255776999 Jun 07 08:28:50 PM PDT 24 Jun 07 08:29:12 PM PDT 24 4377747779 ps
T360 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2350623008 Jun 07 08:28:40 PM PDT 24 Jun 07 08:28:52 PM PDT 24 389233111 ps
T361 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2430126099 Jun 07 08:29:04 PM PDT 24 Jun 07 08:29:21 PM PDT 24 296498224 ps
T362 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2005885567 Jun 07 08:28:45 PM PDT 24 Jun 07 08:29:00 PM PDT 24 4295406490 ps
T363 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4238454686 Jun 07 08:28:51 PM PDT 24 Jun 07 08:29:19 PM PDT 24 8414146603 ps
T364 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3330368628 Jun 07 08:28:51 PM PDT 24 Jun 07 08:29:07 PM PDT 24 310625745 ps
T365 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4028607698 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:11 PM PDT 24 417877618 ps
T366 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4164593437 Jun 07 08:28:51 PM PDT 24 Jun 07 08:29:10 PM PDT 24 8432422051 ps
T367 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1993947126 Jun 07 08:28:42 PM PDT 24 Jun 07 08:28:56 PM PDT 24 447755909 ps
T368 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.547291509 Jun 07 08:28:43 PM PDT 24 Jun 07 08:28:58 PM PDT 24 1401115815 ps
T63 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2017142523 Jun 07 08:28:40 PM PDT 24 Jun 07 08:28:54 PM PDT 24 571631773 ps
T369 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1937889143 Jun 07 08:28:47 PM PDT 24 Jun 07 08:29:03 PM PDT 24 1166695196 ps
T370 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3716479229 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:12 PM PDT 24 417378696 ps
T371 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.342593151 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:11 PM PDT 24 308486576 ps
T372 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4223034882 Jun 07 08:28:40 PM PDT 24 Jun 07 08:28:54 PM PDT 24 2344940312 ps
T373 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1023464303 Jun 07 08:28:45 PM PDT 24 Jun 07 08:28:59 PM PDT 24 492224307 ps
T374 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3474630609 Jun 07 08:28:37 PM PDT 24 Jun 07 08:28:50 PM PDT 24 335559138 ps
T190 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.516509158 Jun 07 08:28:28 PM PDT 24 Jun 07 08:28:55 PM PDT 24 8224720840 ps
T375 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1761827701 Jun 07 08:28:41 PM PDT 24 Jun 07 08:28:54 PM PDT 24 396007277 ps
T376 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.51086456 Jun 07 08:28:42 PM PDT 24 Jun 07 08:28:56 PM PDT 24 407017156 ps
T377 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1850134006 Jun 07 08:28:30 PM PDT 24 Jun 07 08:28:45 PM PDT 24 547453953 ps
T378 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3437812506 Jun 07 08:28:45 PM PDT 24 Jun 07 08:29:05 PM PDT 24 6953151596 ps
T379 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4125151958 Jun 07 08:28:44 PM PDT 24 Jun 07 08:28:58 PM PDT 24 495846559 ps
T380 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.104183770 Jun 07 08:28:49 PM PDT 24 Jun 07 08:29:05 PM PDT 24 1253464277 ps
T381 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3319643232 Jun 07 08:28:38 PM PDT 24 Jun 07 08:28:50 PM PDT 24 448306584 ps
T382 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2285345028 Jun 07 08:28:50 PM PDT 24 Jun 07 08:29:19 PM PDT 24 8408850251 ps
T383 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1243478016 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:20 PM PDT 24 441370344 ps
T384 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1193505644 Jun 07 08:28:42 PM PDT 24 Jun 07 08:28:56 PM PDT 24 270958356 ps
T385 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1992320001 Jun 07 08:28:49 PM PDT 24 Jun 07 08:29:05 PM PDT 24 479209114 ps
T386 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.50483401 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:20 PM PDT 24 359920038 ps
T387 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.547157506 Jun 07 08:28:44 PM PDT 24 Jun 07 08:29:09 PM PDT 24 8048164346 ps
T388 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2956222378 Jun 07 08:28:47 PM PDT 24 Jun 07 08:29:02 PM PDT 24 537944747 ps
T389 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2362857680 Jun 07 08:28:50 PM PDT 24 Jun 07 08:29:07 PM PDT 24 2430767413 ps
T390 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.750406276 Jun 07 08:28:50 PM PDT 24 Jun 07 08:29:10 PM PDT 24 4071164617 ps
T391 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3761790276 Jun 07 08:28:48 PM PDT 24 Jun 07 08:29:03 PM PDT 24 2483857871 ps
T392 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.963730605 Jun 07 08:28:30 PM PDT 24 Jun 07 08:28:46 PM PDT 24 741365352 ps
T393 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3796780765 Jun 07 08:28:45 PM PDT 24 Jun 07 08:28:59 PM PDT 24 442484156 ps
T394 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3835504494 Jun 07 08:28:39 PM PDT 24 Jun 07 08:28:52 PM PDT 24 484306386 ps
T395 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3155886619 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:15 PM PDT 24 332498022 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1956734916 Jun 07 08:28:34 PM PDT 24 Jun 07 08:28:48 PM PDT 24 427229886 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2694111478 Jun 07 08:28:22 PM PDT 24 Jun 07 08:28:46 PM PDT 24 14091134753 ps
T398 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1748998913 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:23 PM PDT 24 2648736795 ps
T399 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.27480569 Jun 07 08:28:44 PM PDT 24 Jun 07 08:28:57 PM PDT 24 300491893 ps
T400 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2788109455 Jun 07 08:28:56 PM PDT 24 Jun 07 08:29:14 PM PDT 24 371115477 ps
T401 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3109832971 Jun 07 08:28:46 PM PDT 24 Jun 07 08:28:59 PM PDT 24 392817248 ps
T402 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2344101638 Jun 07 08:28:46 PM PDT 24 Jun 07 08:29:00 PM PDT 24 369428591 ps
T403 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2919377209 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:11 PM PDT 24 1435623107 ps
T404 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1652421637 Jun 07 08:28:52 PM PDT 24 Jun 07 08:29:09 PM PDT 24 292289515 ps
T405 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2204431529 Jun 07 08:28:46 PM PDT 24 Jun 07 08:29:00 PM PDT 24 347747276 ps
T406 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4073257507 Jun 07 08:28:56 PM PDT 24 Jun 07 08:29:26 PM PDT 24 7930668369 ps
T407 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.4184225194 Jun 07 08:28:25 PM PDT 24 Jun 07 08:28:43 PM PDT 24 1245129245 ps
T408 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.550032230 Jun 07 08:28:49 PM PDT 24 Jun 07 08:29:06 PM PDT 24 382224020 ps
T409 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.454516831 Jun 07 08:28:32 PM PDT 24 Jun 07 08:28:48 PM PDT 24 749845619 ps
T410 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.638083471 Jun 07 08:28:49 PM PDT 24 Jun 07 08:29:07 PM PDT 24 452566369 ps
T411 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2693522888 Jun 07 08:28:41 PM PDT 24 Jun 07 08:28:54 PM PDT 24 314794400 ps
T66 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2119550052 Jun 07 08:28:28 PM PDT 24 Jun 07 08:28:44 PM PDT 24 603388530 ps
T412 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.460494145 Jun 07 08:28:39 PM PDT 24 Jun 07 08:28:53 PM PDT 24 411520267 ps
T67 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3332306236 Jun 07 08:28:41 PM PDT 24 Jun 07 08:29:00 PM PDT 24 13398147651 ps
T413 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.235857703 Jun 07 08:28:38 PM PDT 24 Jun 07 08:29:23 PM PDT 24 11979305291 ps
T414 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.191730529 Jun 07 08:28:31 PM PDT 24 Jun 07 08:28:47 PM PDT 24 436148120 ps
T415 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3049499151 Jun 07 08:28:36 PM PDT 24 Jun 07 08:29:00 PM PDT 24 14255392058 ps
T416 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1530667184 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:11 PM PDT 24 551540947 ps
T417 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2049904680 Jun 07 08:28:41 PM PDT 24 Jun 07 08:28:55 PM PDT 24 489833970 ps
T418 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3580846306 Jun 07 08:28:51 PM PDT 24 Jun 07 08:29:07 PM PDT 24 316883339 ps

Test location /workspace/coverage/default/9.aon_timer_jump.2246650932
Short name T7
Test name
Test status
Simulation time 496771505 ps
CPU time 0.74 seconds
Started Jun 07 08:01:45 PM PDT 24
Finished Jun 07 08:01:48 PM PDT 24
Peak memory 196680 kb
Host smart-c25beda8-4929-428a-9d64-2c2b8b7159c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246650932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2246650932
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.745055940
Short name T13
Test name
Test status
Simulation time 82493963881 ps
CPU time 623.62 seconds
Started Jun 07 08:02:10 PM PDT 24
Finished Jun 07 08:12:37 PM PDT 24
Peak memory 214280 kb
Host smart-79bcd7cd-a025-4da1-8601-2601048477aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745055940 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.745055940
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1973062507
Short name T18
Test name
Test status
Simulation time 524065790610 ps
CPU time 444.55 seconds
Started Jun 07 08:02:22 PM PDT 24
Finished Jun 07 08:09:49 PM PDT 24
Peak memory 214524 kb
Host smart-2b800a3c-b253-410c-9860-4d5d7912ed7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973062507 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1973062507
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4034730914
Short name T28
Test name
Test status
Simulation time 4402000235 ps
CPU time 2.67 seconds
Started Jun 07 08:28:53 PM PDT 24
Finished Jun 07 08:29:11 PM PDT 24
Peak memory 197768 kb
Host smart-78057265-05e1-4591-91ad-6043030c9576
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034730914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.4034730914
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.788229671
Short name T52
Test name
Test status
Simulation time 216882718678 ps
CPU time 659.98 seconds
Started Jun 07 08:01:39 PM PDT 24
Finished Jun 07 08:12:42 PM PDT 24
Peak memory 206240 kb
Host smart-dbe35f69-ea44-4532-b1ef-e6a24e1e76d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788229671 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.788229671
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4009167205
Short name T36
Test name
Test status
Simulation time 196449796957 ps
CPU time 676.64 seconds
Started Jun 07 08:02:25 PM PDT 24
Finished Jun 07 08:13:44 PM PDT 24
Peak memory 214160 kb
Host smart-42738114-1a97-4932-93a8-c7f069cd4e66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009167205 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.4009167205
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1726772989
Short name T97
Test name
Test status
Simulation time 40995513771 ps
CPU time 340.67 seconds
Started Jun 07 08:01:48 PM PDT 24
Finished Jun 07 08:07:30 PM PDT 24
Peak memory 198948 kb
Host smart-34042e25-c084-45b0-bd0a-3082e62810c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726772989 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1726772989
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3847803036
Short name T32
Test name
Test status
Simulation time 280370942532 ps
CPU time 538.54 seconds
Started Jun 07 08:01:47 PM PDT 24
Finished Jun 07 08:10:48 PM PDT 24
Peak memory 203976 kb
Host smart-a3e7a07f-3f95-430c-836c-e0565343df71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847803036 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3847803036
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2122012256
Short name T51
Test name
Test status
Simulation time 103931516604 ps
CPU time 960.56 seconds
Started Jun 07 08:01:54 PM PDT 24
Finished Jun 07 08:17:56 PM PDT 24
Peak memory 214916 kb
Host smart-fb1f29ee-8923-4e1c-bcc5-b3b1dfcd733a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122012256 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2122012256
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3582411174
Short name T16
Test name
Test status
Simulation time 356401115810 ps
CPU time 499.57 seconds
Started Jun 07 08:02:11 PM PDT 24
Finished Jun 07 08:10:34 PM PDT 24
Peak memory 191924 kb
Host smart-3fadb9b3-5ae4-48eb-ab25-2f0ae8f7407e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582411174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3582411174
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3316321838
Short name T91
Test name
Test status
Simulation time 141038168906 ps
CPU time 279.41 seconds
Started Jun 07 08:01:50 PM PDT 24
Finished Jun 07 08:06:31 PM PDT 24
Peak memory 201200 kb
Host smart-1862d17a-de6a-4917-a5b5-d22d9a369eea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316321838 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3316321838
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1281083766
Short name T126
Test name
Test status
Simulation time 156049427306 ps
CPU time 174.07 seconds
Started Jun 07 08:02:26 PM PDT 24
Finished Jun 07 08:05:22 PM PDT 24
Peak memory 206756 kb
Host smart-9020cc9a-eade-4d3b-9034-b05aa4930adf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281083766 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1281083766
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1320358739
Short name T74
Test name
Test status
Simulation time 99653291395 ps
CPU time 681.63 seconds
Started Jun 07 08:01:46 PM PDT 24
Finished Jun 07 08:13:10 PM PDT 24
Peak memory 203488 kb
Host smart-6f9bbce6-c04f-43dc-bd0e-0e366dd09e55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320358739 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1320358739
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3745688828
Short name T21
Test name
Test status
Simulation time 4047937722 ps
CPU time 3.84 seconds
Started Jun 07 08:01:39 PM PDT 24
Finished Jun 07 08:01:46 PM PDT 24
Peak memory 215528 kb
Host smart-5e34c1a1-e86e-4f00-8bc9-a73b95e002ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745688828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3745688828
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.245017983
Short name T138
Test name
Test status
Simulation time 23201187414 ps
CPU time 27.32 seconds
Started Jun 07 08:02:20 PM PDT 24
Finished Jun 07 08:02:50 PM PDT 24
Peak memory 198268 kb
Host smart-ef25d137-b06f-43ee-96e2-eb9ee183c552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245017983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.245017983
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.433026558
Short name T111
Test name
Test status
Simulation time 39833110291 ps
CPU time 30.66 seconds
Started Jun 07 08:01:44 PM PDT 24
Finished Jun 07 08:02:16 PM PDT 24
Peak memory 193028 kb
Host smart-512d59f2-e827-4841-b4a0-6dff3e8eba85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433026558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.433026558
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.4110514062
Short name T85
Test name
Test status
Simulation time 492936203489 ps
CPU time 636.05 seconds
Started Jun 07 08:02:22 PM PDT 24
Finished Jun 07 08:13:01 PM PDT 24
Peak memory 206140 kb
Host smart-82ab4a2c-3280-458e-87bc-6db86850b6f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110514062 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.4110514062
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3711324104
Short name T99
Test name
Test status
Simulation time 158829392689 ps
CPU time 461.81 seconds
Started Jun 07 08:02:10 PM PDT 24
Finished Jun 07 08:09:54 PM PDT 24
Peak memory 206780 kb
Host smart-d95335e7-2df9-4b66-a1a5-6becedab3802
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711324104 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3711324104
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3765799806
Short name T100
Test name
Test status
Simulation time 187656705450 ps
CPU time 285.27 seconds
Started Jun 07 08:02:18 PM PDT 24
Finished Jun 07 08:07:05 PM PDT 24
Peak memory 192560 kb
Host smart-76696ecf-0278-4fbd-99f4-bbfa0a37f860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765799806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3765799806
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.815531163
Short name T77
Test name
Test status
Simulation time 32301673072 ps
CPU time 14.03 seconds
Started Jun 07 08:02:36 PM PDT 24
Finished Jun 07 08:02:51 PM PDT 24
Peak memory 193172 kb
Host smart-ec8a1d89-1fcb-49f2-b899-ee4cbe642a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815531163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.815531163
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2817387163
Short name T102
Test name
Test status
Simulation time 16197264996 ps
CPU time 118.67 seconds
Started Jun 07 08:02:09 PM PDT 24
Finished Jun 07 08:04:09 PM PDT 24
Peak memory 198660 kb
Host smart-90d37086-25ef-426a-a304-e2d51ec55e4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817387163 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2817387163
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.695789174
Short name T88
Test name
Test status
Simulation time 220603479630 ps
CPU time 404.2 seconds
Started Jun 07 08:02:17 PM PDT 24
Finished Jun 07 08:09:03 PM PDT 24
Peak memory 206860 kb
Host smart-ab7a4fe1-806d-44aa-a653-5625fa07076e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695789174 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.695789174
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2499271666
Short name T94
Test name
Test status
Simulation time 220864439331 ps
CPU time 424.62 seconds
Started Jun 07 08:01:41 PM PDT 24
Finished Jun 07 08:08:48 PM PDT 24
Peak memory 211380 kb
Host smart-de93c483-165d-4510-8dd9-ea9075ee51ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499271666 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2499271666
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3458984003
Short name T95
Test name
Test status
Simulation time 95741078627 ps
CPU time 82.48 seconds
Started Jun 07 08:01:39 PM PDT 24
Finished Jun 07 08:03:04 PM PDT 24
Peak memory 198480 kb
Host smart-94ef4873-00fe-453c-9fd4-3ac8e4b2968c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458984003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3458984003
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1009662837
Short name T31
Test name
Test status
Simulation time 600525746923 ps
CPU time 230.25 seconds
Started Jun 07 08:01:50 PM PDT 24
Finished Jun 07 08:05:41 PM PDT 24
Peak memory 208592 kb
Host smart-4612fee7-c09b-4596-a0c9-82648fe9fd62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009662837 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1009662837
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3424910971
Short name T158
Test name
Test status
Simulation time 286972875578 ps
CPU time 494.27 seconds
Started Jun 07 08:01:54 PM PDT 24
Finished Jun 07 08:10:10 PM PDT 24
Peak memory 206876 kb
Host smart-d7218313-4697-4a8e-8b4c-414309f6a5a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424910971 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3424910971
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1493919413
Short name T118
Test name
Test status
Simulation time 13472483906 ps
CPU time 152.37 seconds
Started Jun 07 08:02:13 PM PDT 24
Finished Jun 07 08:04:48 PM PDT 24
Peak memory 198728 kb
Host smart-d20eba58-87bc-4f31-b344-53c7701a209d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493919413 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1493919413
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3107617611
Short name T104
Test name
Test status
Simulation time 106421039780 ps
CPU time 153.04 seconds
Started Jun 07 08:02:17 PM PDT 24
Finished Jun 07 08:04:52 PM PDT 24
Peak memory 198252 kb
Host smart-0cc5c254-dd7e-4e44-ae13-e0b53fad9795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107617611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3107617611
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1673466523
Short name T109
Test name
Test status
Simulation time 220156586538 ps
CPU time 340.27 seconds
Started Jun 07 08:02:26 PM PDT 24
Finished Jun 07 08:08:08 PM PDT 24
Peak memory 198220 kb
Host smart-514fea88-f39c-4776-82a4-221bec79161d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673466523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1673466523
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3712861805
Short name T54
Test name
Test status
Simulation time 380070269 ps
CPU time 0.89 seconds
Started Jun 07 08:28:52 PM PDT 24
Finished Jun 07 08:29:09 PM PDT 24
Peak memory 193112 kb
Host smart-c832c11a-9400-40c6-9524-5c52a6a9f578
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712861805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3712861805
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3361603999
Short name T148
Test name
Test status
Simulation time 28889534111 ps
CPU time 301.4 seconds
Started Jun 07 08:01:39 PM PDT 24
Finished Jun 07 08:06:43 PM PDT 24
Peak memory 206816 kb
Host smart-dbbd6fb3-71d7-4df8-b8fd-4cd54ce4baf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361603999 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3361603999
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.4154255888
Short name T144
Test name
Test status
Simulation time 218938602032 ps
CPU time 888.97 seconds
Started Jun 07 08:01:46 PM PDT 24
Finished Jun 07 08:16:38 PM PDT 24
Peak memory 209360 kb
Host smart-ae4acbf8-d5e0-4969-847b-fb4e56c62b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154255888 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.4154255888
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.814336264
Short name T143
Test name
Test status
Simulation time 271286233362 ps
CPU time 107.93 seconds
Started Jun 07 08:01:51 PM PDT 24
Finished Jun 07 08:03:41 PM PDT 24
Peak memory 191948 kb
Host smart-fc13c8e4-de9f-4c94-a19f-2e38e50073f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814336264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.814336264
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1591994292
Short name T120
Test name
Test status
Simulation time 269264180839 ps
CPU time 124.37 seconds
Started Jun 07 08:01:52 PM PDT 24
Finished Jun 07 08:03:57 PM PDT 24
Peak memory 192580 kb
Host smart-a6549087-95f6-49e0-8cc3-ce92db17beb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591994292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1591994292
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.32109642
Short name T160
Test name
Test status
Simulation time 35000258051 ps
CPU time 384 seconds
Started Jun 07 08:02:06 PM PDT 24
Finished Jun 07 08:08:32 PM PDT 24
Peak memory 199180 kb
Host smart-51c5e5eb-4eb7-4c13-bac5-d10623e62e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32109642 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.32109642
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3317969600
Short name T140
Test name
Test status
Simulation time 64394126192 ps
CPU time 22.45 seconds
Started Jun 07 08:02:02 PM PDT 24
Finished Jun 07 08:02:25 PM PDT 24
Peak memory 198196 kb
Host smart-16762bd2-b2e9-4d68-9907-fdff9207c6bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317969600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3317969600
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1857875641
Short name T80
Test name
Test status
Simulation time 79348395021 ps
CPU time 318.41 seconds
Started Jun 07 08:02:34 PM PDT 24
Finished Jun 07 08:07:53 PM PDT 24
Peak memory 209484 kb
Host smart-abf35926-fdca-4599-82c7-83570a794bf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857875641 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1857875641
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1490154563
Short name T121
Test name
Test status
Simulation time 154772286466 ps
CPU time 231.08 seconds
Started Jun 07 08:02:07 PM PDT 24
Finished Jun 07 08:05:59 PM PDT 24
Peak memory 198276 kb
Host smart-c583a6fc-cc54-47eb-ba1c-ea532ccb7f75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490154563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1490154563
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1928091646
Short name T98
Test name
Test status
Simulation time 220486091461 ps
CPU time 400.87 seconds
Started Jun 07 08:02:09 PM PDT 24
Finished Jun 07 08:08:52 PM PDT 24
Peak memory 203032 kb
Host smart-683ab9d7-475c-4b82-b96d-9a23529a79d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928091646 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1928091646
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.4289643658
Short name T93
Test name
Test status
Simulation time 101707177284 ps
CPU time 171.55 seconds
Started Jun 07 08:02:11 PM PDT 24
Finished Jun 07 08:05:05 PM PDT 24
Peak memory 192928 kb
Host smart-cc503939-1bc1-4ced-b578-6c99340db662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289643658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.4289643658
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1086269942
Short name T86
Test name
Test status
Simulation time 52296757549 ps
CPU time 550.33 seconds
Started Jun 07 08:02:26 PM PDT 24
Finished Jun 07 08:11:39 PM PDT 24
Peak memory 202612 kb
Host smart-b5e61d92-df0d-484b-9457-93ae0036f6f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086269942 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1086269942
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.536851884
Short name T103
Test name
Test status
Simulation time 64192202015 ps
CPU time 265.44 seconds
Started Jun 07 08:01:53 PM PDT 24
Finished Jun 07 08:06:20 PM PDT 24
Peak memory 207648 kb
Host smart-8622c06a-88fb-4481-ad40-72e7e6d8e4b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536851884 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.536851884
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.543206600
Short name T105
Test name
Test status
Simulation time 43726985533 ps
CPU time 65.86 seconds
Started Jun 07 08:01:47 PM PDT 24
Finished Jun 07 08:02:55 PM PDT 24
Peak memory 191984 kb
Host smart-7d1bcc45-89a1-49e8-9dab-fddedb63f9c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543206600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.543206600
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1598529070
Short name T119
Test name
Test status
Simulation time 214885389158 ps
CPU time 329.07 seconds
Started Jun 07 08:01:52 PM PDT 24
Finished Jun 07 08:07:22 PM PDT 24
Peak memory 193208 kb
Host smart-9376457f-0c80-456d-9484-076d850b5288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598529070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1598529070
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.4130166668
Short name T41
Test name
Test status
Simulation time 61678456728 ps
CPU time 459.95 seconds
Started Jun 07 08:02:02 PM PDT 24
Finished Jun 07 08:09:43 PM PDT 24
Peak memory 209664 kb
Host smart-ee6aa2fc-1083-4c98-b415-85227986c4c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130166668 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.4130166668
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.232428725
Short name T17
Test name
Test status
Simulation time 18770146978 ps
CPU time 76.01 seconds
Started Jun 07 08:02:17 PM PDT 24
Finished Jun 07 08:03:35 PM PDT 24
Peak memory 215004 kb
Host smart-ca0f850c-fb34-4866-b1c0-dc9fabf29915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232428725 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.232428725
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2124542068
Short name T116
Test name
Test status
Simulation time 46383560575 ps
CPU time 16.53 seconds
Started Jun 07 08:01:45 PM PDT 24
Finished Jun 07 08:02:03 PM PDT 24
Peak memory 191928 kb
Host smart-22a4b377-d548-43ba-9415-d902b064393b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124542068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2124542068
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1451821433
Short name T131
Test name
Test status
Simulation time 58789412316 ps
CPU time 23.86 seconds
Started Jun 07 08:01:45 PM PDT 24
Finished Jun 07 08:02:11 PM PDT 24
Peak memory 192480 kb
Host smart-eb913947-3f4f-4ae0-943d-bd2319780d2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451821433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1451821433
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1246426096
Short name T149
Test name
Test status
Simulation time 13707616297 ps
CPU time 148.52 seconds
Started Jun 07 08:01:52 PM PDT 24
Finished Jun 07 08:04:23 PM PDT 24
Peak memory 214184 kb
Host smart-1681c194-27dd-4374-b4aa-5671a562e7c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246426096 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1246426096
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1249170634
Short name T106
Test name
Test status
Simulation time 89133998184 ps
CPU time 156.82 seconds
Started Jun 07 08:02:12 PM PDT 24
Finished Jun 07 08:04:51 PM PDT 24
Peak memory 191904 kb
Host smart-bda41af1-67f5-4c1c-a5e2-0f038b852169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249170634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1249170634
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1469605217
Short name T114
Test name
Test status
Simulation time 99006463016 ps
CPU time 95.53 seconds
Started Jun 07 08:02:10 PM PDT 24
Finished Jun 07 08:03:49 PM PDT 24
Peak memory 192992 kb
Host smart-1fa51fbc-cf20-4c8e-8d0d-c81292db658a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469605217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1469605217
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.4019201042
Short name T110
Test name
Test status
Simulation time 121428774911 ps
CPU time 55.29 seconds
Started Jun 07 08:01:39 PM PDT 24
Finished Jun 07 08:02:37 PM PDT 24
Peak memory 192708 kb
Host smart-6c166f16-2e6f-4080-8ab5-9318ab4cc15b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019201042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.4019201042
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2769091932
Short name T101
Test name
Test status
Simulation time 18364297330 ps
CPU time 136.75 seconds
Started Jun 07 08:01:55 PM PDT 24
Finished Jun 07 08:04:14 PM PDT 24
Peak memory 214008 kb
Host smart-7d330275-a200-49e1-9f50-862764726b32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769091932 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2769091932
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3735387474
Short name T128
Test name
Test status
Simulation time 2117574071 ps
CPU time 4.57 seconds
Started Jun 07 08:02:20 PM PDT 24
Finished Jun 07 08:02:27 PM PDT 24
Peak memory 198120 kb
Host smart-046b780c-32db-420d-9ec1-40cf7ab753a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735387474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3735387474
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.780862433
Short name T159
Test name
Test status
Simulation time 370942001611 ps
CPU time 500.75 seconds
Started Jun 07 08:01:50 PM PDT 24
Finished Jun 07 08:10:12 PM PDT 24
Peak memory 191876 kb
Host smart-1adf6314-6dd5-4e5b-8ac3-f2f51ded1180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780862433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.780862433
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.4220516323
Short name T33
Test name
Test status
Simulation time 122874642800 ps
CPU time 208.51 seconds
Started Jun 07 08:02:09 PM PDT 24
Finished Jun 07 08:05:38 PM PDT 24
Peak memory 200256 kb
Host smart-7dd8392e-12cb-40e3-8e69-74babe2ae1e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220516323 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.4220516323
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3202434252
Short name T141
Test name
Test status
Simulation time 191901770141 ps
CPU time 306.36 seconds
Started Jun 07 08:02:25 PM PDT 24
Finished Jun 07 08:07:34 PM PDT 24
Peak memory 192932 kb
Host smart-5a71b9c1-e9e2-4710-a78d-9c73f250c8a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202434252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3202434252
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2665437796
Short name T90
Test name
Test status
Simulation time 133960009609 ps
CPU time 58.2 seconds
Started Jun 07 08:02:20 PM PDT 24
Finished Jun 07 08:03:20 PM PDT 24
Peak memory 191924 kb
Host smart-4836e312-a54b-45bb-8819-ef7a38f15ff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665437796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2665437796
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.602824783
Short name T1
Test name
Test status
Simulation time 338482452479 ps
CPU time 134.96 seconds
Started Jun 07 08:02:20 PM PDT 24
Finished Jun 07 08:04:37 PM PDT 24
Peak memory 192432 kb
Host smart-3e696070-d991-415e-aaa9-80242769a62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602824783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.602824783
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.888552412
Short name T146
Test name
Test status
Simulation time 216118560163 ps
CPU time 55.68 seconds
Started Jun 07 08:02:42 PM PDT 24
Finished Jun 07 08:03:38 PM PDT 24
Peak memory 184204 kb
Host smart-8ceef4d9-d501-4daa-9d22-01ab49decc05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888552412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.888552412
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.276688458
Short name T115
Test name
Test status
Simulation time 128199852551 ps
CPU time 197.41 seconds
Started Jun 07 08:02:35 PM PDT 24
Finished Jun 07 08:05:54 PM PDT 24
Peak memory 200252 kb
Host smart-d15ba3ea-aad6-422b-bf46-4579d08e4b46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276688458 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.276688458
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1705526110
Short name T122
Test name
Test status
Simulation time 114872370201 ps
CPU time 461.74 seconds
Started Jun 07 08:02:21 PM PDT 24
Finished Jun 07 08:10:06 PM PDT 24
Peak memory 211456 kb
Host smart-3d64cc20-295a-443a-9cab-92b05f948c64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705526110 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1705526110
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1712875592
Short name T50
Test name
Test status
Simulation time 69762435543 ps
CPU time 117.69 seconds
Started Jun 07 08:01:52 PM PDT 24
Finished Jun 07 08:03:52 PM PDT 24
Peak memory 191896 kb
Host smart-c7fe9660-be94-4f0e-a4fc-b4b2990edb0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712875592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1712875592
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1335576452
Short name T96
Test name
Test status
Simulation time 369089657786 ps
CPU time 246.57 seconds
Started Jun 07 08:02:01 PM PDT 24
Finished Jun 07 08:06:08 PM PDT 24
Peak memory 192988 kb
Host smart-0496a091-634c-4191-9dd0-1c7d1233b9d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335576452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1335576452
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3323401384
Short name T15
Test name
Test status
Simulation time 73173304005 ps
CPU time 18.49 seconds
Started Jun 07 08:01:42 PM PDT 24
Finished Jun 07 08:02:02 PM PDT 24
Peak memory 191856 kb
Host smart-a2fe27c1-1351-4291-bdd7-df1e4ad311e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323401384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3323401384
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3672286742
Short name T81
Test name
Test status
Simulation time 123478984158 ps
CPU time 501.13 seconds
Started Jun 07 08:02:26 PM PDT 24
Finished Jun 07 08:10:50 PM PDT 24
Peak memory 212256 kb
Host smart-f0de7ece-c7db-4523-9519-ec4531f7f7a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672286742 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3672286742
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3277724918
Short name T107
Test name
Test status
Simulation time 27985322155 ps
CPU time 21.35 seconds
Started Jun 07 08:01:53 PM PDT 24
Finished Jun 07 08:02:16 PM PDT 24
Peak memory 192928 kb
Host smart-16eb47f2-f862-4a74-bb2d-404b657fb7cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277724918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3277724918
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1784133314
Short name T89
Test name
Test status
Simulation time 61331552646 ps
CPU time 116.82 seconds
Started Jun 07 08:02:11 PM PDT 24
Finished Jun 07 08:04:11 PM PDT 24
Peak memory 206772 kb
Host smart-ded04489-0554-4934-abc1-64c30589c58c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784133314 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1784133314
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1421342240
Short name T123
Test name
Test status
Simulation time 76382552550 ps
CPU time 122.15 seconds
Started Jun 07 08:02:13 PM PDT 24
Finished Jun 07 08:04:18 PM PDT 24
Peak memory 192644 kb
Host smart-ac1dac3c-5d36-41d3-a5e8-678d8d8581f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421342240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1421342240
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.4156034896
Short name T112
Test name
Test status
Simulation time 633797218 ps
CPU time 1.51 seconds
Started Jun 07 08:02:19 PM PDT 24
Finished Jun 07 08:02:23 PM PDT 24
Peak memory 196584 kb
Host smart-0051c2c8-ea9a-4c4c-9246-d336700be4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156034896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.4156034896
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.107945248
Short name T152
Test name
Test status
Simulation time 48809407407 ps
CPU time 36.64 seconds
Started Jun 07 08:02:24 PM PDT 24
Finished Jun 07 08:03:03 PM PDT 24
Peak memory 184376 kb
Host smart-46636242-b290-4c07-9a49-63fee7479b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107945248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.107945248
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2429081205
Short name T153
Test name
Test status
Simulation time 86561070630 ps
CPU time 113.9 seconds
Started Jun 07 08:01:38 PM PDT 24
Finished Jun 07 08:03:34 PM PDT 24
Peak memory 191924 kb
Host smart-d4dfee15-42bc-4d05-a4a0-c66b7b2a7233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429081205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2429081205
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1177868712
Short name T135
Test name
Test status
Simulation time 103114209308 ps
CPU time 41.6 seconds
Started Jun 07 08:01:54 PM PDT 24
Finished Jun 07 08:02:38 PM PDT 24
Peak memory 191900 kb
Host smart-cb357f97-f14e-4ad5-8cb8-49eca9be789d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177868712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1177868712
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2351662610
Short name T113
Test name
Test status
Simulation time 464874547 ps
CPU time 1.01 seconds
Started Jun 07 08:01:38 PM PDT 24
Finished Jun 07 08:01:42 PM PDT 24
Peak memory 196608 kb
Host smart-07eab1de-b721-40c5-881a-bb929af95e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351662610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2351662610
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.182454449
Short name T134
Test name
Test status
Simulation time 399565846 ps
CPU time 0.72 seconds
Started Jun 07 08:02:11 PM PDT 24
Finished Jun 07 08:02:15 PM PDT 24
Peak memory 196660 kb
Host smart-12d11e46-cd2e-4cd6-ae41-3227b50843e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182454449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.182454449
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.4150188945
Short name T166
Test name
Test status
Simulation time 173724578240 ps
CPU time 88.91 seconds
Started Jun 07 08:02:27 PM PDT 24
Finished Jun 07 08:03:59 PM PDT 24
Peak memory 192004 kb
Host smart-30620ea0-167d-44ad-bfe4-25cbc6add1fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150188945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.4150188945
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2471007992
Short name T130
Test name
Test status
Simulation time 471313329 ps
CPU time 0.97 seconds
Started Jun 07 08:01:52 PM PDT 24
Finished Jun 07 08:01:55 PM PDT 24
Peak memory 196592 kb
Host smart-e0b17097-8651-42eb-9b9b-db009a5ab402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471007992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2471007992
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.4015503382
Short name T87
Test name
Test status
Simulation time 188051930405 ps
CPU time 355.14 seconds
Started Jun 07 08:02:02 PM PDT 24
Finished Jun 07 08:07:59 PM PDT 24
Peak memory 214916 kb
Host smart-98fb5fda-84e4-41c4-8b1c-dd02b770cc62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015503382 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.4015503382
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2518543264
Short name T151
Test name
Test status
Simulation time 67136496838 ps
CPU time 190.28 seconds
Started Jun 07 08:01:40 PM PDT 24
Finished Jun 07 08:04:53 PM PDT 24
Peak memory 206900 kb
Host smart-72ccb061-358e-4cc4-87ff-19d5bf5b891e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518543264 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2518543264
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2685270852
Short name T127
Test name
Test status
Simulation time 412320168 ps
CPU time 1.15 seconds
Started Jun 07 08:02:26 PM PDT 24
Finished Jun 07 08:02:30 PM PDT 24
Peak memory 196604 kb
Host smart-3aeca7a0-31f5-49e0-ac8a-ff57a8155bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685270852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2685270852
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.174427148
Short name T139
Test name
Test status
Simulation time 573643244 ps
CPU time 1.48 seconds
Started Jun 07 08:01:44 PM PDT 24
Finished Jun 07 08:01:46 PM PDT 24
Peak memory 196592 kb
Host smart-20269499-af46-400c-805d-1ee75a0b6d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174427148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.174427148
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.768214982
Short name T129
Test name
Test status
Simulation time 463949942 ps
CPU time 0.91 seconds
Started Jun 07 08:02:11 PM PDT 24
Finished Jun 07 08:02:14 PM PDT 24
Peak memory 196660 kb
Host smart-61db1f7f-c146-4909-936d-cccea63256a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768214982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.768214982
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1045060084
Short name T8
Test name
Test status
Simulation time 229396858601 ps
CPU time 191.04 seconds
Started Jun 07 08:02:09 PM PDT 24
Finished Jun 07 08:05:22 PM PDT 24
Peak memory 191920 kb
Host smart-79c44262-414b-498b-a8a8-dfaefce3423f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045060084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1045060084
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2229974163
Short name T46
Test name
Test status
Simulation time 528039758 ps
CPU time 0.84 seconds
Started Jun 07 08:02:09 PM PDT 24
Finished Jun 07 08:02:11 PM PDT 24
Peak memory 196620 kb
Host smart-0c43e068-d28c-465d-b8d8-499b8cbac06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229974163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2229974163
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3414066181
Short name T145
Test name
Test status
Simulation time 254437663409 ps
CPU time 128.96 seconds
Started Jun 07 08:01:41 PM PDT 24
Finished Jun 07 08:03:52 PM PDT 24
Peak memory 193024 kb
Host smart-b9684492-5eba-408a-88ae-bab75964dc85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414066181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3414066181
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3826635082
Short name T10
Test name
Test status
Simulation time 41763573522 ps
CPU time 61.49 seconds
Started Jun 07 08:01:45 PM PDT 24
Finished Jun 07 08:02:49 PM PDT 24
Peak memory 191888 kb
Host smart-2d357df9-8c44-4479-aeab-b716d61bb158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826635082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3826635082
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1181761607
Short name T92
Test name
Test status
Simulation time 525154003 ps
CPU time 0.79 seconds
Started Jun 07 08:01:52 PM PDT 24
Finished Jun 07 08:01:54 PM PDT 24
Peak memory 196608 kb
Host smart-f5402716-192d-4d23-9e2c-44ae72c1d601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181761607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1181761607
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3265726732
Short name T125
Test name
Test status
Simulation time 509925891 ps
CPU time 0.78 seconds
Started Jun 07 08:02:09 PM PDT 24
Finished Jun 07 08:02:11 PM PDT 24
Peak memory 196516 kb
Host smart-ffd7e260-62e8-4758-bafa-ed53bf99d463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265726732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3265726732
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3880283820
Short name T133
Test name
Test status
Simulation time 526955079 ps
CPU time 1.43 seconds
Started Jun 07 08:01:38 PM PDT 24
Finished Jun 07 08:01:43 PM PDT 24
Peak memory 196572 kb
Host smart-20e82da5-096b-433f-bc30-def4e7fde724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880283820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3880283820
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.4257156119
Short name T156
Test name
Test status
Simulation time 151858281980 ps
CPU time 260.04 seconds
Started Jun 07 08:02:25 PM PDT 24
Finished Jun 07 08:06:48 PM PDT 24
Peak memory 191952 kb
Host smart-f07ef767-cd84-4bd7-bda0-04ba2cf9f27c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257156119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.4257156119
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.4136092230
Short name T84
Test name
Test status
Simulation time 76630624548 ps
CPU time 425.03 seconds
Started Jun 07 08:02:28 PM PDT 24
Finished Jun 07 08:09:36 PM PDT 24
Peak memory 213216 kb
Host smart-ca579373-8521-460e-9bb7-9b7ce7962357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136092230 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.4136092230
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.805225977
Short name T40
Test name
Test status
Simulation time 372642836 ps
CPU time 0.8 seconds
Started Jun 07 08:01:48 PM PDT 24
Finished Jun 07 08:01:50 PM PDT 24
Peak memory 196620 kb
Host smart-fc090784-a0d7-41ec-bdfd-cc51b06beeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805225977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.805225977
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2196441338
Short name T117
Test name
Test status
Simulation time 231852635465 ps
CPU time 304.87 seconds
Started Jun 07 08:02:00 PM PDT 24
Finished Jun 07 08:07:06 PM PDT 24
Peak memory 191912 kb
Host smart-80b577f0-c991-4717-83dd-dd46873e6020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196441338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2196441338
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.915484794
Short name T137
Test name
Test status
Simulation time 181628051705 ps
CPU time 187.65 seconds
Started Jun 07 08:02:12 PM PDT 24
Finished Jun 07 08:05:23 PM PDT 24
Peak memory 191556 kb
Host smart-9a135d0c-578b-4088-9b41-f69179a81239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915484794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.915484794
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1993372464
Short name T23
Test name
Test status
Simulation time 352497684 ps
CPU time 1.14 seconds
Started Jun 07 08:02:22 PM PDT 24
Finished Jun 07 08:02:26 PM PDT 24
Peak memory 196552 kb
Host smart-4f838459-9eca-4522-aa7c-9443b0856ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993372464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1993372464
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3788269679
Short name T184
Test name
Test status
Simulation time 269254967656 ps
CPU time 98.96 seconds
Started Jun 07 08:02:27 PM PDT 24
Finished Jun 07 08:04:09 PM PDT 24
Peak memory 192604 kb
Host smart-974e33c8-37e6-428f-b9b2-acb5044e94b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788269679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3788269679
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1846865583
Short name T132
Test name
Test status
Simulation time 445224300 ps
CPU time 1.26 seconds
Started Jun 07 08:02:35 PM PDT 24
Finished Jun 07 08:02:38 PM PDT 24
Peak memory 196676 kb
Host smart-5e2f3356-5d5a-4177-b538-6b235e25b82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846865583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1846865583
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1490452766
Short name T165
Test name
Test status
Simulation time 252178513882 ps
CPU time 364.17 seconds
Started Jun 07 08:01:45 PM PDT 24
Finished Jun 07 08:07:51 PM PDT 24
Peak memory 198252 kb
Host smart-0a1d53fe-f307-480f-b927-64d0227af765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490452766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1490452766
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1827521815
Short name T29
Test name
Test status
Simulation time 8896935138 ps
CPU time 5.84 seconds
Started Jun 07 08:28:19 PM PDT 24
Finished Jun 07 08:28:42 PM PDT 24
Peak memory 198124 kb
Host smart-80609c4b-1cc9-4ee8-bfa0-6a8cc070616d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827521815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1827521815
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1851646048
Short name T171
Test name
Test status
Simulation time 299772694249 ps
CPU time 437.57 seconds
Started Jun 07 08:01:38 PM PDT 24
Finished Jun 07 08:08:58 PM PDT 24
Peak memory 192980 kb
Host smart-80a39a66-4e8d-4f64-9dd3-6c7043bebc9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851646048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1851646048
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2436305460
Short name T124
Test name
Test status
Simulation time 385161755 ps
CPU time 0.8 seconds
Started Jun 07 08:01:49 PM PDT 24
Finished Jun 07 08:01:52 PM PDT 24
Peak memory 196596 kb
Host smart-9f8f462f-bd96-4869-b6c2-4e7078158470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436305460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2436305460
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.918745456
Short name T147
Test name
Test status
Simulation time 601224082 ps
CPU time 1.02 seconds
Started Jun 07 08:02:02 PM PDT 24
Finished Jun 07 08:02:04 PM PDT 24
Peak memory 196532 kb
Host smart-dd914217-c670-483e-96b1-ed75f13e4809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918745456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.918745456
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2489422333
Short name T75
Test name
Test status
Simulation time 439128710 ps
CPU time 1.35 seconds
Started Jun 07 08:02:14 PM PDT 24
Finished Jun 07 08:02:18 PM PDT 24
Peak memory 196548 kb
Host smart-42251221-92be-4a2c-af5b-2be43872711e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489422333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2489422333
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.545513145
Short name T187
Test name
Test status
Simulation time 395779199 ps
CPU time 0.76 seconds
Started Jun 07 08:02:19 PM PDT 24
Finished Jun 07 08:02:22 PM PDT 24
Peak memory 196452 kb
Host smart-868b5a9b-46bd-4ba6-9db0-93bb8623fd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545513145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.545513145
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.890664410
Short name T186
Test name
Test status
Simulation time 625739052 ps
CPU time 1.51 seconds
Started Jun 07 08:02:27 PM PDT 24
Finished Jun 07 08:02:31 PM PDT 24
Peak memory 196568 kb
Host smart-2a90c7b9-b82e-4ac7-908e-795b90c6b681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890664410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.890664410
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2833867612
Short name T108
Test name
Test status
Simulation time 511981718 ps
CPU time 1.25 seconds
Started Jun 07 08:02:25 PM PDT 24
Finished Jun 07 08:02:29 PM PDT 24
Peak memory 196528 kb
Host smart-ef7fc2f6-b5e1-436d-a549-0f5e9a54b9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833867612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2833867612
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1896857287
Short name T161
Test name
Test status
Simulation time 382763756 ps
CPU time 0.74 seconds
Started Jun 07 08:02:27 PM PDT 24
Finished Jun 07 08:02:31 PM PDT 24
Peak memory 196552 kb
Host smart-5f49775e-5c66-4759-9226-e40b176b4fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896857287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1896857287
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.758117764
Short name T164
Test name
Test status
Simulation time 279586865291 ps
CPU time 90.91 seconds
Started Jun 07 08:02:23 PM PDT 24
Finished Jun 07 08:03:56 PM PDT 24
Peak memory 193024 kb
Host smart-ccf8e4ed-f4d2-442a-a05d-450ae7d4431f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758117764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.758117764
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2661933374
Short name T3
Test name
Test status
Simulation time 553757335 ps
CPU time 0.82 seconds
Started Jun 07 08:02:26 PM PDT 24
Finished Jun 07 08:02:29 PM PDT 24
Peak memory 196580 kb
Host smart-2378d6e9-c53c-4f70-be92-bf5096aeaf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661933374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2661933374
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2042227733
Short name T142
Test name
Test status
Simulation time 442878157 ps
CPU time 0.71 seconds
Started Jun 07 08:02:37 PM PDT 24
Finished Jun 07 08:02:39 PM PDT 24
Peak memory 196592 kb
Host smart-2db5cd3a-426e-4014-b26a-c69c85fee680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042227733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2042227733
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2157529944
Short name T35
Test name
Test status
Simulation time 260833374219 ps
CPU time 371.83 seconds
Started Jun 07 08:01:39 PM PDT 24
Finished Jun 07 08:07:54 PM PDT 24
Peak memory 210300 kb
Host smart-85075572-017c-45fa-9ea2-f6e00847a52e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157529944 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2157529944
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.677311948
Short name T170
Test name
Test status
Simulation time 442777449 ps
CPU time 0.75 seconds
Started Jun 07 08:01:50 PM PDT 24
Finished Jun 07 08:01:52 PM PDT 24
Peak memory 196528 kb
Host smart-3457f67e-3ffe-496a-acd5-d5d89028a8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677311948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.677311948
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3940940932
Short name T183
Test name
Test status
Simulation time 485546322 ps
CPU time 0.96 seconds
Started Jun 07 08:01:38 PM PDT 24
Finished Jun 07 08:01:40 PM PDT 24
Peak memory 196596 kb
Host smart-abdf5bcd-9a54-4a12-939f-b16fa1bfcfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940940932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3940940932
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.4021962287
Short name T78
Test name
Test status
Simulation time 100000542843 ps
CPU time 144.07 seconds
Started Jun 07 08:01:50 PM PDT 24
Finished Jun 07 08:04:16 PM PDT 24
Peak memory 191908 kb
Host smart-32acc46f-7b7e-428e-80d1-893c5bca383d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021962287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.4021962287
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3009271864
Short name T178
Test name
Test status
Simulation time 655361678 ps
CPU time 0.67 seconds
Started Jun 07 08:01:51 PM PDT 24
Finished Jun 07 08:01:53 PM PDT 24
Peak memory 196548 kb
Host smart-48608214-4c33-4667-89b4-55eb2fdeec37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009271864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3009271864
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3720819498
Short name T174
Test name
Test status
Simulation time 513718700 ps
CPU time 1.36 seconds
Started Jun 07 08:01:56 PM PDT 24
Finished Jun 07 08:01:59 PM PDT 24
Peak memory 196636 kb
Host smart-e1e0b7fc-054b-4a5e-aa13-15e8d9180e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720819498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3720819498
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3539783954
Short name T167
Test name
Test status
Simulation time 578987414 ps
CPU time 0.87 seconds
Started Jun 07 08:01:53 PM PDT 24
Finished Jun 07 08:01:56 PM PDT 24
Peak memory 196564 kb
Host smart-3e943a22-1269-4a06-a699-6d531f12c62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539783954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3539783954
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3081515288
Short name T9
Test name
Test status
Simulation time 720816068 ps
CPU time 0.66 seconds
Started Jun 07 08:02:08 PM PDT 24
Finished Jun 07 08:02:10 PM PDT 24
Peak memory 196648 kb
Host smart-69a2b822-9ee3-43c0-8a24-f7ef078ac77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081515288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3081515288
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1624712745
Short name T155
Test name
Test status
Simulation time 401203379 ps
CPU time 0.9 seconds
Started Jun 07 08:02:08 PM PDT 24
Finished Jun 07 08:02:10 PM PDT 24
Peak memory 196508 kb
Host smart-81b0b754-c072-4551-8292-175bc1b8c01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624712745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1624712745
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2979674348
Short name T150
Test name
Test status
Simulation time 590288492 ps
CPU time 1.55 seconds
Started Jun 07 08:02:08 PM PDT 24
Finished Jun 07 08:02:11 PM PDT 24
Peak memory 196572 kb
Host smart-337692d0-0ea9-4a5c-9ec1-08aa7ffcfdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979674348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2979674348
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1508111348
Short name T163
Test name
Test status
Simulation time 423678401 ps
CPU time 1.26 seconds
Started Jun 07 08:02:10 PM PDT 24
Finished Jun 07 08:02:14 PM PDT 24
Peak memory 196544 kb
Host smart-5601ee85-515d-430a-a145-c5d813bc6661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508111348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1508111348
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1150052170
Short name T180
Test name
Test status
Simulation time 633882858 ps
CPU time 1.15 seconds
Started Jun 07 08:02:11 PM PDT 24
Finished Jun 07 08:02:15 PM PDT 24
Peak memory 196648 kb
Host smart-b14b029b-c513-48e4-a4fc-809538a772fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150052170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1150052170
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2102335349
Short name T154
Test name
Test status
Simulation time 59399317126 ps
CPU time 645.64 seconds
Started Jun 07 08:02:12 PM PDT 24
Finished Jun 07 08:13:01 PM PDT 24
Peak memory 204256 kb
Host smart-a58786d8-cbc2-4278-9467-2fd71d10f597
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102335349 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2102335349
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.375341678
Short name T176
Test name
Test status
Simulation time 409750105 ps
CPU time 0.99 seconds
Started Jun 07 08:02:12 PM PDT 24
Finished Jun 07 08:02:16 PM PDT 24
Peak memory 196644 kb
Host smart-356a70bc-b61e-4c9e-9a23-33366d286f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375341678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.375341678
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.234952196
Short name T136
Test name
Test status
Simulation time 524995207 ps
CPU time 1.4 seconds
Started Jun 07 08:02:19 PM PDT 24
Finished Jun 07 08:02:22 PM PDT 24
Peak memory 196600 kb
Host smart-38d09c45-e8f6-4bd4-b657-478baee9fc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234952196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.234952196
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3364797980
Short name T182
Test name
Test status
Simulation time 430371109 ps
CPU time 0.7 seconds
Started Jun 07 08:02:24 PM PDT 24
Finished Jun 07 08:02:27 PM PDT 24
Peak memory 196408 kb
Host smart-516eaaaa-2d66-4f92-886b-0b83179c3b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364797980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3364797980
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2150400358
Short name T185
Test name
Test status
Simulation time 551558475 ps
CPU time 0.82 seconds
Started Jun 07 08:01:46 PM PDT 24
Finished Jun 07 08:01:49 PM PDT 24
Peak memory 196504 kb
Host smart-f49d9189-f37d-4b45-9fa9-da8edce6cdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150400358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2150400358
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.664750760
Short name T188
Test name
Test status
Simulation time 7757515703 ps
CPU time 11.85 seconds
Started Jun 07 08:28:56 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 198100 kb
Host smart-8521b984-6203-4242-b9fd-9d79aeea1d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664750760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.664750760
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.aon_timer_jump.26618844
Short name T181
Test name
Test status
Simulation time 575841042 ps
CPU time 1.55 seconds
Started Jun 07 08:01:37 PM PDT 24
Finished Jun 07 08:01:41 PM PDT 24
Peak memory 196544 kb
Host smart-75550a40-1db9-46af-91a1-6d745c5ac193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26618844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.26618844
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.495166577
Short name T38
Test name
Test status
Simulation time 348538262 ps
CPU time 1.13 seconds
Started Jun 07 08:01:45 PM PDT 24
Finished Jun 07 08:01:48 PM PDT 24
Peak memory 196568 kb
Host smart-8b3a18d0-c339-407f-bde3-9e88361e5a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495166577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.495166577
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.4097890642
Short name T173
Test name
Test status
Simulation time 505950076 ps
CPU time 1.03 seconds
Started Jun 07 08:01:45 PM PDT 24
Finished Jun 07 08:01:48 PM PDT 24
Peak memory 196652 kb
Host smart-f8fd6fbd-7192-444e-a81b-7e8c54e6ebfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097890642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.4097890642
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1423010612
Short name T179
Test name
Test status
Simulation time 375424659 ps
CPU time 1.14 seconds
Started Jun 07 08:01:51 PM PDT 24
Finished Jun 07 08:01:54 PM PDT 24
Peak memory 196552 kb
Host smart-90477ed8-fb3d-4298-bf7e-acfc5aee93b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423010612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1423010612
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3417536926
Short name T175
Test name
Test status
Simulation time 356478907 ps
CPU time 1.14 seconds
Started Jun 07 08:02:03 PM PDT 24
Finished Jun 07 08:02:05 PM PDT 24
Peak memory 196544 kb
Host smart-db6f31b9-615e-4a5b-acd8-cd81cc577300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417536926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3417536926
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2543484934
Short name T169
Test name
Test status
Simulation time 384823864 ps
CPU time 1.2 seconds
Started Jun 07 08:02:12 PM PDT 24
Finished Jun 07 08:02:16 PM PDT 24
Peak memory 196560 kb
Host smart-a42e28b5-1327-4ea1-ad30-654c7508514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543484934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2543484934
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.23098820
Short name T177
Test name
Test status
Simulation time 651101178 ps
CPU time 0.73 seconds
Started Jun 07 08:02:23 PM PDT 24
Finished Jun 07 08:02:26 PM PDT 24
Peak memory 196600 kb
Host smart-fbab8227-ec6c-4d36-8424-2b7ce1ab013e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23098820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.23098820
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1305814471
Short name T157
Test name
Test status
Simulation time 550632245 ps
CPU time 0.82 seconds
Started Jun 07 08:01:39 PM PDT 24
Finished Jun 07 08:01:42 PM PDT 24
Peak memory 196568 kb
Host smart-9755f2f0-b839-4c7e-a8b2-52975630329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305814471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1305814471
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2058685326
Short name T172
Test name
Test status
Simulation time 38807192266 ps
CPU time 59.69 seconds
Started Jun 07 08:02:26 PM PDT 24
Finished Jun 07 08:03:28 PM PDT 24
Peak memory 191908 kb
Host smart-8108bb9b-8a8e-40ca-9256-a1f50eb326ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058685326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2058685326
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1441028691
Short name T76
Test name
Test status
Simulation time 528917821 ps
CPU time 1.34 seconds
Started Jun 07 08:01:38 PM PDT 24
Finished Jun 07 08:01:42 PM PDT 24
Peak memory 196672 kb
Host smart-f40f680a-6b64-44b8-bad9-24086f18ce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441028691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1441028691
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2119550052
Short name T66
Test name
Test status
Simulation time 603388530 ps
CPU time 1.59 seconds
Started Jun 07 08:28:28 PM PDT 24
Finished Jun 07 08:28:44 PM PDT 24
Peak memory 193940 kb
Host smart-1a78faf9-87a4-4337-ab3b-89184a65c3ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119550052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2119550052
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3437812506
Short name T378
Test name
Test status
Simulation time 6953151596 ps
CPU time 7.18 seconds
Started Jun 07 08:28:45 PM PDT 24
Finished Jun 07 08:29:05 PM PDT 24
Peak memory 195564 kb
Host smart-39ad60a6-d63a-48ec-96f3-41ff34449553
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437812506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3437812506
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.963730605
Short name T392
Test name
Test status
Simulation time 741365352 ps
CPU time 1.88 seconds
Started Jun 07 08:28:30 PM PDT 24
Finished Jun 07 08:28:46 PM PDT 24
Peak memory 183708 kb
Host smart-93860d29-edd5-41eb-937c-caf6fce80425
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963730605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.963730605
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1850134006
Short name T377
Test name
Test status
Simulation time 547453953 ps
CPU time 1.09 seconds
Started Jun 07 08:28:30 PM PDT 24
Finished Jun 07 08:28:45 PM PDT 24
Peak memory 196008 kb
Host smart-ed131e12-1746-42c4-934e-c4438bc593d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850134006 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1850134006
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1610516700
Short name T59
Test name
Test status
Simulation time 411148441 ps
CPU time 0.69 seconds
Started Jun 07 08:28:36 PM PDT 24
Finished Jun 07 08:28:49 PM PDT 24
Peak memory 193268 kb
Host smart-e3e8c877-0d6f-4a02-8104-e0a7379986ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610516700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1610516700
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3356528231
Short name T357
Test name
Test status
Simulation time 438542233 ps
CPU time 1.17 seconds
Started Jun 07 08:28:35 PM PDT 24
Finished Jun 07 08:28:49 PM PDT 24
Peak memory 192860 kb
Host smart-b1e3f45d-7b77-4a76-af6d-fb10165ff3cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356528231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3356528231
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2234674559
Short name T276
Test name
Test status
Simulation time 439775389 ps
CPU time 0.66 seconds
Started Jun 07 08:28:20 PM PDT 24
Finished Jun 07 08:28:38 PM PDT 24
Peak memory 183536 kb
Host smart-9a7af704-8f1d-45ea-957a-309eee8266fe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234674559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2234674559
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2385021858
Short name T323
Test name
Test status
Simulation time 383649137 ps
CPU time 1.06 seconds
Started Jun 07 08:28:31 PM PDT 24
Finished Jun 07 08:28:46 PM PDT 24
Peak memory 183636 kb
Host smart-1a96f5b0-217c-4e27-8358-ddbd0cd5c5bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385021858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2385021858
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1756352412
Short name T69
Test name
Test status
Simulation time 1367931247 ps
CPU time 2.82 seconds
Started Jun 07 08:28:25 PM PDT 24
Finished Jun 07 08:28:44 PM PDT 24
Peak memory 193896 kb
Host smart-a222dc2c-08dd-4c7b-9603-9243211cf996
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756352412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1756352412
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.191730529
Short name T414
Test name
Test status
Simulation time 436148120 ps
CPU time 1.62 seconds
Started Jun 07 08:28:31 PM PDT 24
Finished Jun 07 08:28:47 PM PDT 24
Peak memory 198392 kb
Host smart-d558c122-55c5-4ed0-b0c1-00a34fa7eb77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191730529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.191730529
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3280533891
Short name T30
Test name
Test status
Simulation time 4585331136 ps
CPU time 7.57 seconds
Started Jun 07 08:28:48 PM PDT 24
Finished Jun 07 08:29:08 PM PDT 24
Peak memory 197744 kb
Host smart-f1fc182c-fd11-4524-85be-67c80c42773e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280533891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3280533891
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1998991138
Short name T58
Test name
Test status
Simulation time 550249816 ps
CPU time 1.13 seconds
Started Jun 07 08:28:34 PM PDT 24
Finished Jun 07 08:28:48 PM PDT 24
Peak memory 194572 kb
Host smart-1ea35359-83f3-4195-8ad8-072af6722700
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998991138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1998991138
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2694111478
Short name T397
Test name
Test status
Simulation time 14091134753 ps
CPU time 6.81 seconds
Started Jun 07 08:28:22 PM PDT 24
Finished Jun 07 08:28:46 PM PDT 24
Peak memory 195996 kb
Host smart-bee0c599-2c22-49d5-a000-30e5fc807c6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694111478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2694111478
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.4184225194
Short name T407
Test name
Test status
Simulation time 1245129245 ps
CPU time 2.45 seconds
Started Jun 07 08:28:25 PM PDT 24
Finished Jun 07 08:28:43 PM PDT 24
Peak memory 193140 kb
Host smart-726fd00a-4d0a-4822-ac90-d5f947d66e99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184225194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.4184225194
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1995814693
Short name T333
Test name
Test status
Simulation time 550078189 ps
CPU time 0.97 seconds
Started Jun 07 08:28:47 PM PDT 24
Finished Jun 07 08:29:01 PM PDT 24
Peak memory 196808 kb
Host smart-f569bd06-1348-4443-a8b9-8b7ff87510ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995814693 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1995814693
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1993947126
Short name T367
Test name
Test status
Simulation time 447755909 ps
CPU time 0.7 seconds
Started Jun 07 08:28:42 PM PDT 24
Finished Jun 07 08:28:56 PM PDT 24
Peak memory 192976 kb
Host smart-a9b22c03-7c59-4524-8d2c-f2fd4c4f3371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993947126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1993947126
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2693522888
Short name T411
Test name
Test status
Simulation time 314794400 ps
CPU time 0.63 seconds
Started Jun 07 08:28:41 PM PDT 24
Finished Jun 07 08:28:54 PM PDT 24
Peak memory 192956 kb
Host smart-f3535161-c006-4934-9191-8153c040565c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693522888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2693522888
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.814656423
Short name T331
Test name
Test status
Simulation time 369571981 ps
CPU time 0.63 seconds
Started Jun 07 08:28:43 PM PDT 24
Finished Jun 07 08:28:56 PM PDT 24
Peak memory 183544 kb
Host smart-92b9d961-0adf-4b0d-9719-3f416979ab97
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814656423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.814656423
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4130999784
Short name T282
Test name
Test status
Simulation time 511439231 ps
CPU time 0.71 seconds
Started Jun 07 08:28:39 PM PDT 24
Finished Jun 07 08:28:52 PM PDT 24
Peak memory 183644 kb
Host smart-79b46273-adcd-4524-99c6-600bc7ee79ce
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130999784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.4130999784
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2290680215
Short name T25
Test name
Test status
Simulation time 2372935312 ps
CPU time 1.09 seconds
Started Jun 07 08:28:41 PM PDT 24
Finished Jun 07 08:28:55 PM PDT 24
Peak memory 195100 kb
Host smart-373107cf-c4a9-491c-a2a8-783dfed39d2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290680215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2290680215
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.302218706
Short name T290
Test name
Test status
Simulation time 421098464 ps
CPU time 1.07 seconds
Started Jun 07 08:28:30 PM PDT 24
Finished Jun 07 08:28:45 PM PDT 24
Peak memory 198304 kb
Host smart-d1e4275b-fac7-47a1-af35-6a60ad79cc14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302218706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.302218706
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.805834690
Short name T338
Test name
Test status
Simulation time 577199842 ps
CPU time 1.61 seconds
Started Jun 07 08:28:46 PM PDT 24
Finished Jun 07 08:29:00 PM PDT 24
Peak memory 196408 kb
Host smart-ca75d698-65a2-4b8a-80a0-4e9279b18c50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805834690 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.805834690
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2984174307
Short name T70
Test name
Test status
Simulation time 547096600 ps
CPU time 0.71 seconds
Started Jun 07 08:28:51 PM PDT 24
Finished Jun 07 08:29:07 PM PDT 24
Peak memory 193912 kb
Host smart-830e941c-063d-419e-9de2-48783bdbbc82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984174307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2984174307
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1023464303
Short name T373
Test name
Test status
Simulation time 492224307 ps
CPU time 1.2 seconds
Started Jun 07 08:28:45 PM PDT 24
Finished Jun 07 08:28:59 PM PDT 24
Peak memory 183608 kb
Host smart-c942a595-df9e-413b-acc8-17806cff333e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023464303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1023464303
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1869338584
Short name T72
Test name
Test status
Simulation time 2465650185 ps
CPU time 1.59 seconds
Started Jun 07 08:28:51 PM PDT 24
Finished Jun 07 08:29:08 PM PDT 24
Peak memory 193048 kb
Host smart-0e0330af-d002-427d-a9be-a11b22a4c79e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869338584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1869338584
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2362857680
Short name T389
Test name
Test status
Simulation time 2430767413 ps
CPU time 2.24 seconds
Started Jun 07 08:28:50 PM PDT 24
Finished Jun 07 08:29:07 PM PDT 24
Peak memory 198552 kb
Host smart-e8825aee-54b3-428b-9711-07afa8280980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362857680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2362857680
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.384975395
Short name T192
Test name
Test status
Simulation time 4632632864 ps
CPU time 2.75 seconds
Started Jun 07 08:28:48 PM PDT 24
Finished Jun 07 08:29:04 PM PDT 24
Peak memory 197876 kb
Host smart-4f2fd5c9-8c79-40cc-9ecd-175ce8d6a75e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384975395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.384975395
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.29091570
Short name T286
Test name
Test status
Simulation time 544458568 ps
CPU time 0.99 seconds
Started Jun 07 08:28:53 PM PDT 24
Finished Jun 07 08:29:10 PM PDT 24
Peak memory 197156 kb
Host smart-34078735-41eb-41e8-bed9-3d6c464d74a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29091570 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.29091570
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2828999295
Short name T73
Test name
Test status
Simulation time 492990857 ps
CPU time 1 seconds
Started Jun 07 08:28:50 PM PDT 24
Finished Jun 07 08:29:06 PM PDT 24
Peak memory 193080 kb
Host smart-b25d30f6-70dd-4dc1-97ea-875e97308cec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828999295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2828999295
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3796780765
Short name T393
Test name
Test status
Simulation time 442484156 ps
CPU time 0.85 seconds
Started Jun 07 08:28:45 PM PDT 24
Finished Jun 07 08:28:59 PM PDT 24
Peak memory 183604 kb
Host smart-4c2d9327-9caf-4949-80b8-c6bc66608ea0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796780765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3796780765
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3761790276
Short name T391
Test name
Test status
Simulation time 2483857871 ps
CPU time 2.25 seconds
Started Jun 07 08:28:48 PM PDT 24
Finished Jun 07 08:29:03 PM PDT 24
Peak memory 195000 kb
Host smart-a2c6554c-93e4-4108-b695-bb16f320f9d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761790276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3761790276
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3612601165
Short name T356
Test name
Test status
Simulation time 329574431 ps
CPU time 1.68 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:28:58 PM PDT 24
Peak memory 198416 kb
Host smart-81e961cb-39a9-418f-93d4-d7d0625475cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612601165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3612601165
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.132762011
Short name T311
Test name
Test status
Simulation time 4333976613 ps
CPU time 7.25 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:29:04 PM PDT 24
Peak memory 197664 kb
Host smart-7b37d0dd-030f-41f6-9b02-41a773090f32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132762011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.132762011
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1893836439
Short name T27
Test name
Test status
Simulation time 593519381 ps
CPU time 1.05 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:28:58 PM PDT 24
Peak memory 195760 kb
Host smart-9569941f-b9f7-411a-b9c6-6a0cefbcbf6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893836439 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1893836439
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1153717654
Short name T62
Test name
Test status
Simulation time 386695885 ps
CPU time 0.83 seconds
Started Jun 07 08:28:46 PM PDT 24
Finished Jun 07 08:29:00 PM PDT 24
Peak memory 192888 kb
Host smart-00d252e9-a8a5-4055-ab6b-b313a57bd96c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153717654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1153717654
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1672814727
Short name T352
Test name
Test status
Simulation time 327481604 ps
CPU time 0.62 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:10 PM PDT 24
Peak memory 183632 kb
Host smart-cf9ca38c-24e5-499d-9b91-780ad43ec06a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672814727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1672814727
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1835032342
Short name T355
Test name
Test status
Simulation time 2117241869 ps
CPU time 3.47 seconds
Started Jun 07 08:28:46 PM PDT 24
Finished Jun 07 08:29:02 PM PDT 24
Peak memory 194796 kb
Host smart-ae3f945a-1e0e-43b6-b7af-9c0c201962c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835032342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1835032342
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1180433089
Short name T314
Test name
Test status
Simulation time 567943156 ps
CPU time 2.47 seconds
Started Jun 07 08:28:48 PM PDT 24
Finished Jun 07 08:29:04 PM PDT 24
Peak memory 198388 kb
Host smart-f511a8c5-a219-4e13-9174-41b3036a65bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180433089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1180433089
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2005885567
Short name T362
Test name
Test status
Simulation time 4295406490 ps
CPU time 2.4 seconds
Started Jun 07 08:28:45 PM PDT 24
Finished Jun 07 08:29:00 PM PDT 24
Peak memory 197900 kb
Host smart-fb310109-5c99-4099-9a68-f837c28e840f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005885567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2005885567
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3124281762
Short name T300
Test name
Test status
Simulation time 521361638 ps
CPU time 0.8 seconds
Started Jun 07 08:28:51 PM PDT 24
Finished Jun 07 08:29:07 PM PDT 24
Peak memory 195768 kb
Host smart-4fe4a7c6-85a1-48b3-89ca-e7124375cffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124281762 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3124281762
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3386146350
Short name T55
Test name
Test status
Simulation time 328421761 ps
CPU time 1.12 seconds
Started Jun 07 08:28:45 PM PDT 24
Finished Jun 07 08:28:59 PM PDT 24
Peak memory 193320 kb
Host smart-e3f66ceb-b9e8-4559-8caa-c3255dfd19e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386146350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3386146350
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3109832971
Short name T401
Test name
Test status
Simulation time 392817248 ps
CPU time 0.63 seconds
Started Jun 07 08:28:46 PM PDT 24
Finished Jun 07 08:28:59 PM PDT 24
Peak memory 183604 kb
Host smart-0ce1b6bf-ca16-461f-ac3f-f4502ad7dbac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109832971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3109832971
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.104183770
Short name T380
Test name
Test status
Simulation time 1253464277 ps
CPU time 1.05 seconds
Started Jun 07 08:28:49 PM PDT 24
Finished Jun 07 08:29:05 PM PDT 24
Peak memory 193948 kb
Host smart-d56a6696-760c-433b-92b8-6ccbba3b87ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104183770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.104183770
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2954418429
Short name T320
Test name
Test status
Simulation time 436287492 ps
CPU time 1.97 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:28:59 PM PDT 24
Peak memory 198436 kb
Host smart-bdf92c7c-7ef3-4162-9715-e2984110db1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954418429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2954418429
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3505290785
Short name T329
Test name
Test status
Simulation time 4553822918 ps
CPU time 2.48 seconds
Started Jun 07 08:28:46 PM PDT 24
Finished Jun 07 08:29:01 PM PDT 24
Peak memory 197680 kb
Host smart-c78a963b-f324-4f7d-badd-f4d3a7ef2c22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505290785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3505290785
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1530667184
Short name T416
Test name
Test status
Simulation time 551540947 ps
CPU time 1.05 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:11 PM PDT 24
Peak memory 195784 kb
Host smart-11c98c39-490c-4531-a112-ea5228374ff6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530667184 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1530667184
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1183940419
Short name T68
Test name
Test status
Simulation time 411391834 ps
CPU time 0.74 seconds
Started Jun 07 08:28:50 PM PDT 24
Finished Jun 07 08:29:06 PM PDT 24
Peak memory 192928 kb
Host smart-c3cb1fcd-881d-413d-9665-5aed5b053898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183940419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1183940419
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2002730422
Short name T334
Test name
Test status
Simulation time 443852032 ps
CPU time 1.14 seconds
Started Jun 07 08:28:49 PM PDT 24
Finished Jun 07 08:29:05 PM PDT 24
Peak memory 192804 kb
Host smart-d6f52852-fb61-4cae-8685-3bd80002f014
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002730422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2002730422
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2919377209
Short name T403
Test name
Test status
Simulation time 1435623107 ps
CPU time 1.17 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:11 PM PDT 24
Peak memory 183808 kb
Host smart-056af7d9-a980-45db-8561-c67107ad6359
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919377209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2919377209
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2956222378
Short name T388
Test name
Test status
Simulation time 537944747 ps
CPU time 2.14 seconds
Started Jun 07 08:28:47 PM PDT 24
Finished Jun 07 08:29:02 PM PDT 24
Peak memory 198464 kb
Host smart-1614928c-b7f1-4332-964d-1546cf6ca185
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956222378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2956222378
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2285345028
Short name T382
Test name
Test status
Simulation time 8408850251 ps
CPU time 14.12 seconds
Started Jun 07 08:28:50 PM PDT 24
Finished Jun 07 08:29:19 PM PDT 24
Peak memory 198220 kb
Host smart-5deb3422-ed53-4f6a-9595-e44bc1f9a6ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285345028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2285345028
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.37647843
Short name T298
Test name
Test status
Simulation time 466360993 ps
CPU time 1.46 seconds
Started Jun 07 08:28:53 PM PDT 24
Finished Jun 07 08:29:10 PM PDT 24
Peak memory 195560 kb
Host smart-0541b1ed-aebc-4e41-ba0b-84594eba1c74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37647843 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.37647843
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4261336648
Short name T317
Test name
Test status
Simulation time 524853929 ps
CPU time 1.36 seconds
Started Jun 07 08:28:50 PM PDT 24
Finished Jun 07 08:29:06 PM PDT 24
Peak memory 192924 kb
Host smart-08803e73-deab-4530-966c-782f98e0feaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261336648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.4261336648
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3668883467
Short name T343
Test name
Test status
Simulation time 343627577 ps
CPU time 0.94 seconds
Started Jun 07 08:28:46 PM PDT 24
Finished Jun 07 08:29:00 PM PDT 24
Peak memory 183636 kb
Host smart-8e92ee37-9a1d-4ac4-9d51-dcef17460d23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668883467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3668883467
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1937889143
Short name T369
Test name
Test status
Simulation time 1166695196 ps
CPU time 2.28 seconds
Started Jun 07 08:28:47 PM PDT 24
Finished Jun 07 08:29:03 PM PDT 24
Peak memory 193960 kb
Host smart-230be53e-dba3-40c3-9e11-ef78eba52870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937889143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1937889143
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3194319376
Short name T336
Test name
Test status
Simulation time 380949113 ps
CPU time 1.59 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:28:58 PM PDT 24
Peak memory 198440 kb
Host smart-a2ec1381-c8f7-4188-a543-4aa7732ec861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194319376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3194319376
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4238454686
Short name T363
Test name
Test status
Simulation time 8414146603 ps
CPU time 13.33 seconds
Started Jun 07 08:28:51 PM PDT 24
Finished Jun 07 08:29:19 PM PDT 24
Peak memory 198208 kb
Host smart-1c7ac125-9a2b-4ac8-9e8e-227c06870a61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238454686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.4238454686
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2023474373
Short name T358
Test name
Test status
Simulation time 370700289 ps
CPU time 0.76 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:12 PM PDT 24
Peak memory 195928 kb
Host smart-91c23534-b973-496d-998c-c2c92abf7105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023474373 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2023474373
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1493721135
Short name T64
Test name
Test status
Simulation time 297829144 ps
CPU time 1.05 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:15 PM PDT 24
Peak memory 192032 kb
Host smart-9b695a80-d828-4347-bc2e-a04d912c25c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493721135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1493721135
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.550032230
Short name T408
Test name
Test status
Simulation time 382224020 ps
CPU time 1.08 seconds
Started Jun 07 08:28:49 PM PDT 24
Finished Jun 07 08:29:06 PM PDT 24
Peak memory 183672 kb
Host smart-689b06fb-0aa2-48d1-8252-7d49dc9d4822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550032230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.550032230
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1044277637
Short name T301
Test name
Test status
Simulation time 984093489 ps
CPU time 1.06 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:20 PM PDT 24
Peak memory 193228 kb
Host smart-6a714f6a-8e3e-4f7f-b185-189ac79cd33d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044277637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1044277637
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3591011688
Short name T293
Test name
Test status
Simulation time 422050157 ps
CPU time 1.01 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:15 PM PDT 24
Peak memory 198284 kb
Host smart-6ebe0428-9827-40ab-9ee8-f4d0dc41869e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591011688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3591011688
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3011024336
Short name T313
Test name
Test status
Simulation time 5007617008 ps
CPU time 2.65 seconds
Started Jun 07 08:28:53 PM PDT 24
Finished Jun 07 08:29:11 PM PDT 24
Peak memory 196388 kb
Host smart-cd355c32-4e08-4f08-944c-b7d7c806e057
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011024336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3011024336
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1456640283
Short name T337
Test name
Test status
Simulation time 540567915 ps
CPU time 1.41 seconds
Started Jun 07 08:28:53 PM PDT 24
Finished Jun 07 08:29:10 PM PDT 24
Peak memory 195520 kb
Host smart-214dd0f8-2215-4456-984b-fe2e7529d3af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456640283 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1456640283
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.913466839
Short name T327
Test name
Test status
Simulation time 291191712 ps
CPU time 1.01 seconds
Started Jun 07 08:28:55 PM PDT 24
Finished Jun 07 08:29:14 PM PDT 24
Peak memory 192932 kb
Host smart-9d9678db-a00a-4adb-b655-aab41ddfc43d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913466839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.913466839
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1145439816
Short name T285
Test name
Test status
Simulation time 352773324 ps
CPU time 1.02 seconds
Started Jun 07 08:28:48 PM PDT 24
Finished Jun 07 08:29:05 PM PDT 24
Peak memory 183636 kb
Host smart-3c8f50c4-4887-4e9c-bc1f-f09f46b2b436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145439816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1145439816
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2149427706
Short name T315
Test name
Test status
Simulation time 1090969625 ps
CPU time 1.5 seconds
Started Jun 07 08:28:48 PM PDT 24
Finished Jun 07 08:29:03 PM PDT 24
Peak memory 193424 kb
Host smart-1f55ca90-06e5-4b7a-bd37-e360bdc67c74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149427706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2149427706
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2691215872
Short name T295
Test name
Test status
Simulation time 461353198 ps
CPU time 2.34 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:13 PM PDT 24
Peak memory 198496 kb
Host smart-47da486d-5a07-45ff-aa12-f0c94fb7b372
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691215872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2691215872
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.50483401
Short name T386
Test name
Test status
Simulation time 359920038 ps
CPU time 1.12 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:20 PM PDT 24
Peak memory 195936 kb
Host smart-f909ae83-d8e1-4490-be0d-f45f73f94080
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50483401 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.50483401
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1076737995
Short name T292
Test name
Test status
Simulation time 563617380 ps
CPU time 0.68 seconds
Started Jun 07 08:28:56 PM PDT 24
Finished Jun 07 08:29:14 PM PDT 24
Peak memory 192892 kb
Host smart-b78acacc-1145-447d-98d7-439e931d24a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076737995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1076737995
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3330368628
Short name T364
Test name
Test status
Simulation time 310625745 ps
CPU time 0.64 seconds
Started Jun 07 08:28:51 PM PDT 24
Finished Jun 07 08:29:07 PM PDT 24
Peak memory 183652 kb
Host smart-9a1be9a7-33c9-4d54-a636-53fc4fa03aed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330368628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3330368628
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.4233773660
Short name T303
Test name
Test status
Simulation time 1134342289 ps
CPU time 1.15 seconds
Started Jun 07 08:28:50 PM PDT 24
Finished Jun 07 08:29:06 PM PDT 24
Peak memory 192848 kb
Host smart-d451754e-4281-4d03-9c1c-3a0022306d4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233773660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.4233773660
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.832841385
Short name T305
Test name
Test status
Simulation time 344158805 ps
CPU time 1.68 seconds
Started Jun 07 08:28:48 PM PDT 24
Finished Jun 07 08:29:05 PM PDT 24
Peak memory 198352 kb
Host smart-a681e509-5c48-4778-be19-0c5c15c4ec37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832841385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.832841385
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2031519357
Short name T189
Test name
Test status
Simulation time 4133247569 ps
CPU time 1.9 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:18 PM PDT 24
Peak memory 197844 kb
Host smart-463c6a6f-748e-4b12-9ca5-9af3df097ed0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031519357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2031519357
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.266452322
Short name T341
Test name
Test status
Simulation time 408232558 ps
CPU time 1.19 seconds
Started Jun 07 08:28:53 PM PDT 24
Finished Jun 07 08:29:10 PM PDT 24
Peak memory 195512 kb
Host smart-5a9917ee-247c-48f8-8ed4-1481bfa6067b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266452322 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.266452322
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1965924439
Short name T60
Test name
Test status
Simulation time 457152195 ps
CPU time 0.7 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:17 PM PDT 24
Peak memory 192896 kb
Host smart-a792bda5-1484-441d-ae85-729f9d1d38d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965924439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1965924439
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2430126099
Short name T361
Test name
Test status
Simulation time 296498224 ps
CPU time 0.79 seconds
Started Jun 07 08:29:04 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 183624 kb
Host smart-4cea576b-200e-40df-8572-8d7ece9bab0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430126099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2430126099
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1748998913
Short name T398
Test name
Test status
Simulation time 2648736795 ps
CPU time 6.48 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:23 PM PDT 24
Peak memory 195116 kb
Host smart-c38bcbeb-d2f4-4a55-96b9-4c4c3894a8a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748998913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1748998913
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.675770835
Short name T346
Test name
Test status
Simulation time 942268020 ps
CPU time 1.93 seconds
Started Jun 07 08:28:51 PM PDT 24
Finished Jun 07 08:29:08 PM PDT 24
Peak memory 198528 kb
Host smart-c2d2344f-91e0-4698-89b8-bac8a5178b0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675770835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.675770835
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3319643232
Short name T381
Test name
Test status
Simulation time 448306584 ps
CPU time 0.82 seconds
Started Jun 07 08:28:38 PM PDT 24
Finished Jun 07 08:28:50 PM PDT 24
Peak memory 183684 kb
Host smart-0264b7e3-ed35-459a-a44f-c47c0248c6b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319643232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3319643232
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3049499151
Short name T415
Test name
Test status
Simulation time 14255392058 ps
CPU time 11.78 seconds
Started Jun 07 08:28:36 PM PDT 24
Finished Jun 07 08:29:00 PM PDT 24
Peak memory 196188 kb
Host smart-ea5123d8-991c-4759-a9a9-7c9fd824c75d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049499151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3049499151
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.454516831
Short name T409
Test name
Test status
Simulation time 749845619 ps
CPU time 1.78 seconds
Started Jun 07 08:28:32 PM PDT 24
Finished Jun 07 08:28:48 PM PDT 24
Peak memory 183660 kb
Host smart-60a0db59-3ab0-4c2a-9c99-85ef2d41b7e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454516831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.454516831
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.142617928
Short name T342
Test name
Test status
Simulation time 512370937 ps
CPU time 0.79 seconds
Started Jun 07 08:28:29 PM PDT 24
Finished Jun 07 08:28:45 PM PDT 24
Peak memory 195328 kb
Host smart-354c3fea-037b-4a6a-8fb9-7f52d89cc6b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142617928 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.142617928
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.767337762
Short name T65
Test name
Test status
Simulation time 449276991 ps
CPU time 0.74 seconds
Started Jun 07 08:28:42 PM PDT 24
Finished Jun 07 08:28:56 PM PDT 24
Peak memory 193156 kb
Host smart-653867e7-a9d1-4df0-8a6f-4a8edbda0bc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767337762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.767337762
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1956734916
Short name T396
Test name
Test status
Simulation time 427229886 ps
CPU time 0.55 seconds
Started Jun 07 08:28:34 PM PDT 24
Finished Jun 07 08:28:48 PM PDT 24
Peak memory 183636 kb
Host smart-645b23f0-7615-4792-bceb-465780970bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956734916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1956734916
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.460494145
Short name T412
Test name
Test status
Simulation time 411520267 ps
CPU time 1.21 seconds
Started Jun 07 08:28:39 PM PDT 24
Finished Jun 07 08:28:53 PM PDT 24
Peak memory 183660 kb
Host smart-153c65de-5c79-481f-9219-ed7582279144
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460494145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.460494145
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1505329432
Short name T280
Test name
Test status
Simulation time 372197086 ps
CPU time 0.6 seconds
Started Jun 07 08:28:30 PM PDT 24
Finished Jun 07 08:28:45 PM PDT 24
Peak memory 183584 kb
Host smart-41f417c2-b4af-4687-ab0b-ce1daa8aa611
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505329432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1505329432
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2371097566
Short name T71
Test name
Test status
Simulation time 2651327852 ps
CPU time 2.55 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:28:59 PM PDT 24
Peak memory 194008 kb
Host smart-71502169-659e-4568-86c2-2d638d257112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371097566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2371097566
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1494100416
Short name T339
Test name
Test status
Simulation time 641487968 ps
CPU time 1.82 seconds
Started Jun 07 08:28:40 PM PDT 24
Finished Jun 07 08:28:55 PM PDT 24
Peak memory 198416 kb
Host smart-c543ab5b-d465-40b1-86b2-ce1c9a18d5d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494100416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1494100416
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.516509158
Short name T190
Test name
Test status
Simulation time 8224720840 ps
CPU time 12.89 seconds
Started Jun 07 08:28:28 PM PDT 24
Finished Jun 07 08:28:55 PM PDT 24
Peak memory 198004 kb
Host smart-8f872824-d71e-44b2-b42c-d68d6f3c033a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516509158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.516509158
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.551762427
Short name T277
Test name
Test status
Simulation time 425277995 ps
CPU time 0.65 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:11 PM PDT 24
Peak memory 192788 kb
Host smart-ea90bb1f-ab7c-4421-a4dd-43effd173be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551762427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.551762427
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3896616010
Short name T345
Test name
Test status
Simulation time 416864917 ps
CPU time 0.67 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:15 PM PDT 24
Peak memory 183644 kb
Host smart-0ae0a128-010b-48ce-b610-28703f1181be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896616010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3896616010
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2388495
Short name T349
Test name
Test status
Simulation time 484288033 ps
CPU time 1.3 seconds
Started Jun 07 08:28:56 PM PDT 24
Finished Jun 07 08:29:25 PM PDT 24
Peak memory 183664 kb
Host smart-fdba58c7-5f20-45c7-9884-b086db27f9f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2388495
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2788109455
Short name T400
Test name
Test status
Simulation time 371115477 ps
CPU time 1.08 seconds
Started Jun 07 08:28:56 PM PDT 24
Finished Jun 07 08:29:14 PM PDT 24
Peak memory 183652 kb
Host smart-84cbb5e0-f98a-4518-bec8-6d93d1118d90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788109455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2788109455
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.521870299
Short name T330
Test name
Test status
Simulation time 339691646 ps
CPU time 0.95 seconds
Started Jun 07 08:28:47 PM PDT 24
Finished Jun 07 08:29:01 PM PDT 24
Peak memory 192860 kb
Host smart-0aff4819-ad11-4439-80ec-ab4138881435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521870299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.521870299
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3716479229
Short name T370
Test name
Test status
Simulation time 417378696 ps
CPU time 0.69 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:12 PM PDT 24
Peak memory 183592 kb
Host smart-5086bf38-0cc6-46b1-b518-2363a805aad9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716479229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3716479229
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1652421637
Short name T404
Test name
Test status
Simulation time 292289515 ps
CPU time 0.96 seconds
Started Jun 07 08:28:52 PM PDT 24
Finished Jun 07 08:29:09 PM PDT 24
Peak memory 183644 kb
Host smart-a3ee3ceb-f213-49fd-ac06-3546fa6d62d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652421637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1652421637
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1203121174
Short name T351
Test name
Test status
Simulation time 345767881 ps
CPU time 0.98 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:15 PM PDT 24
Peak memory 183604 kb
Host smart-10eacbfd-259c-4a3c-8bdf-ea9fbbd70b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203121174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1203121174
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2696928576
Short name T318
Test name
Test status
Simulation time 410979487 ps
CPU time 1.14 seconds
Started Jun 07 08:28:55 PM PDT 24
Finished Jun 07 08:29:12 PM PDT 24
Peak memory 183592 kb
Host smart-13e02991-7b4b-4129-97ac-fb8b21e19bc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696928576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2696928576
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.676640638
Short name T283
Test name
Test status
Simulation time 353498151 ps
CPU time 1.08 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:11 PM PDT 24
Peak memory 183604 kb
Host smart-681da5d7-7f96-4b87-9f55-b4749421b6af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676640638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.676640638
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3207548100
Short name T297
Test name
Test status
Simulation time 622923567 ps
CPU time 0.97 seconds
Started Jun 07 08:28:39 PM PDT 24
Finished Jun 07 08:28:52 PM PDT 24
Peak memory 194472 kb
Host smart-a74fc56e-5cf6-4b12-9048-b208b6ac4426
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207548100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3207548100
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3332306236
Short name T67
Test name
Test status
Simulation time 13398147651 ps
CPU time 7 seconds
Started Jun 07 08:28:41 PM PDT 24
Finished Jun 07 08:29:00 PM PDT 24
Peak memory 192124 kb
Host smart-5bff3c8c-2f71-4c0b-8186-ff8e7da6f5f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332306236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3332306236
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.208467259
Short name T296
Test name
Test status
Simulation time 1177751592 ps
CPU time 1.1 seconds
Started Jun 07 08:28:25 PM PDT 24
Finished Jun 07 08:28:42 PM PDT 24
Peak memory 193168 kb
Host smart-8fb6630e-4854-44c7-ba83-5322ac1ee53f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208467259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.208467259
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.509972946
Short name T302
Test name
Test status
Simulation time 506281692 ps
CPU time 0.81 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:28:57 PM PDT 24
Peak memory 196616 kb
Host smart-f9bc7f4e-8c60-4652-9ed3-d3db22152f98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509972946 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.509972946
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1811578034
Short name T53
Test name
Test status
Simulation time 486736524 ps
CPU time 0.77 seconds
Started Jun 07 08:28:37 PM PDT 24
Finished Jun 07 08:28:49 PM PDT 24
Peak memory 192888 kb
Host smart-c6d5efd6-5b82-48f3-b149-27f469dca132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811578034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1811578034
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1193505644
Short name T384
Test name
Test status
Simulation time 270958356 ps
CPU time 0.91 seconds
Started Jun 07 08:28:42 PM PDT 24
Finished Jun 07 08:28:56 PM PDT 24
Peak memory 183616 kb
Host smart-65972d4f-c51a-4cd9-87c6-40e3623154d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193505644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1193505644
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3474630609
Short name T374
Test name
Test status
Simulation time 335559138 ps
CPU time 1.1 seconds
Started Jun 07 08:28:37 PM PDT 24
Finished Jun 07 08:28:50 PM PDT 24
Peak memory 183556 kb
Host smart-d5603799-acf0-4cea-82b1-463abe6dd174
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474630609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3474630609
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2685859614
Short name T319
Test name
Test status
Simulation time 346159308 ps
CPU time 0.56 seconds
Started Jun 07 08:28:34 PM PDT 24
Finished Jun 07 08:28:47 PM PDT 24
Peak memory 183600 kb
Host smart-d95232e0-f998-4e62-a5bf-99a0d77c318c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685859614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2685859614
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4119713395
Short name T353
Test name
Test status
Simulation time 1467732578 ps
CPU time 2.73 seconds
Started Jun 07 08:28:46 PM PDT 24
Finished Jun 07 08:29:02 PM PDT 24
Peak memory 193404 kb
Host smart-9ea9d989-9f0e-4964-860c-4132a754379e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119713395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.4119713395
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2049904680
Short name T417
Test name
Test status
Simulation time 489833970 ps
CPU time 1.43 seconds
Started Jun 07 08:28:41 PM PDT 24
Finished Jun 07 08:28:55 PM PDT 24
Peak memory 198436 kb
Host smart-247f5e4f-eb4a-4e8b-a474-38b01fffbf17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049904680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2049904680
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3360724165
Short name T191
Test name
Test status
Simulation time 7935198179 ps
CPU time 7.66 seconds
Started Jun 07 08:28:43 PM PDT 24
Finished Jun 07 08:29:03 PM PDT 24
Peak memory 198212 kb
Host smart-bc3164b0-60ce-4031-a676-ad194bfb2547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360724165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3360724165
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1140111453
Short name T299
Test name
Test status
Simulation time 263627602 ps
CPU time 0.93 seconds
Started Jun 07 08:28:50 PM PDT 24
Finished Jun 07 08:29:06 PM PDT 24
Peak memory 183560 kb
Host smart-45dcb32b-08e9-40ec-a3ab-e40b3c33a336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140111453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1140111453
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4044251806
Short name T279
Test name
Test status
Simulation time 440918822 ps
CPU time 0.85 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:20 PM PDT 24
Peak memory 183656 kb
Host smart-4d68d890-6968-4666-b2b8-ebe90f08a664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044251806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.4044251806
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1243478016
Short name T383
Test name
Test status
Simulation time 441370344 ps
CPU time 0.74 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:20 PM PDT 24
Peak memory 192860 kb
Host smart-a781421a-658d-4c73-ba29-0c92f65134ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243478016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1243478016
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1992320001
Short name T385
Test name
Test status
Simulation time 479209114 ps
CPU time 0.9 seconds
Started Jun 07 08:28:49 PM PDT 24
Finished Jun 07 08:29:05 PM PDT 24
Peak memory 183592 kb
Host smart-fa2bb2ab-1ec0-461d-bccc-421fa7bb1d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992320001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1992320001
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1936861922
Short name T281
Test name
Test status
Simulation time 459680640 ps
CPU time 0.73 seconds
Started Jun 07 08:28:52 PM PDT 24
Finished Jun 07 08:29:08 PM PDT 24
Peak memory 183640 kb
Host smart-d6e539ff-3f6c-4cda-86b6-955cffa129e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936861922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1936861922
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3055363799
Short name T307
Test name
Test status
Simulation time 287677430 ps
CPU time 1 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:12 PM PDT 24
Peak memory 183624 kb
Host smart-9ce455df-47cc-430a-ad41-3750c64c52b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055363799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3055363799
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3779307898
Short name T310
Test name
Test status
Simulation time 313502702 ps
CPU time 0.64 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:11 PM PDT 24
Peak memory 183624 kb
Host smart-a1c988be-ba62-42e0-8f2a-260ca7e289cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779307898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3779307898
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2508817066
Short name T278
Test name
Test status
Simulation time 502894654 ps
CPU time 1.01 seconds
Started Jun 07 08:28:53 PM PDT 24
Finished Jun 07 08:29:10 PM PDT 24
Peak memory 192828 kb
Host smart-723713ca-b08f-4991-b166-d4fa37c1db97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508817066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2508817066
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1757932350
Short name T316
Test name
Test status
Simulation time 408755719 ps
CPU time 1.22 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:12 PM PDT 24
Peak memory 183656 kb
Host smart-2d67de5e-95f9-4550-8fde-b7a1cf3bccf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757932350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1757932350
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4028607698
Short name T365
Test name
Test status
Simulation time 417877618 ps
CPU time 0.87 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:11 PM PDT 24
Peak memory 192912 kb
Host smart-95332ee7-f3ce-4f90-8bd0-582b2a7fbfa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028607698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4028607698
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2017142523
Short name T63
Test name
Test status
Simulation time 571631773 ps
CPU time 1.05 seconds
Started Jun 07 08:28:40 PM PDT 24
Finished Jun 07 08:28:54 PM PDT 24
Peak memory 183808 kb
Host smart-90d77e36-f0c8-4d18-82da-aee6d6cf2dac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017142523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2017142523
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.235857703
Short name T413
Test name
Test status
Simulation time 11979305291 ps
CPU time 32.42 seconds
Started Jun 07 08:28:38 PM PDT 24
Finished Jun 07 08:29:23 PM PDT 24
Peak memory 192124 kb
Host smart-bc2a1d6a-d721-49cb-9290-e76b3edcc1fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235857703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.235857703
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3586287580
Short name T56
Test name
Test status
Simulation time 1127992176 ps
CPU time 2.33 seconds
Started Jun 07 08:28:41 PM PDT 24
Finished Jun 07 08:28:56 PM PDT 24
Peak memory 193100 kb
Host smart-b6eb0837-33cc-4bba-8c3c-08bc8c897528
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586287580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3586287580
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1605816851
Short name T291
Test name
Test status
Simulation time 443102865 ps
CPU time 1.01 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:28:58 PM PDT 24
Peak memory 197276 kb
Host smart-eefaf4f2-2c56-4cc1-9e68-5b93b5070e42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605816851 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1605816851
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3414827501
Short name T26
Test name
Test status
Simulation time 347436998 ps
CPU time 0.87 seconds
Started Jun 07 08:28:40 PM PDT 24
Finished Jun 07 08:28:54 PM PDT 24
Peak memory 193080 kb
Host smart-0dbdc0bb-0e9c-49c3-a3ee-9861cb736774
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414827501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3414827501
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.557979412
Short name T308
Test name
Test status
Simulation time 563590182 ps
CPU time 0.64 seconds
Started Jun 07 08:28:40 PM PDT 24
Finished Jun 07 08:28:53 PM PDT 24
Peak memory 183644 kb
Host smart-069a9d81-7526-4b86-99ee-d24945510efb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557979412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.557979412
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2204431529
Short name T405
Test name
Test status
Simulation time 347747276 ps
CPU time 1.06 seconds
Started Jun 07 08:28:46 PM PDT 24
Finished Jun 07 08:29:00 PM PDT 24
Peak memory 183576 kb
Host smart-df672b18-946a-4dd8-b0fb-b71940ebc898
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204431529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2204431529
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1761827701
Short name T375
Test name
Test status
Simulation time 396007277 ps
CPU time 0.61 seconds
Started Jun 07 08:28:41 PM PDT 24
Finished Jun 07 08:28:54 PM PDT 24
Peak memory 183624 kb
Host smart-bb6309ef-b42a-48bd-b77e-9c9a2b462693
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761827701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1761827701
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4223034882
Short name T372
Test name
Test status
Simulation time 2344940312 ps
CPU time 1.48 seconds
Started Jun 07 08:28:40 PM PDT 24
Finished Jun 07 08:28:54 PM PDT 24
Peak memory 194336 kb
Host smart-4a506bec-0319-493a-a39f-2f68d91204ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223034882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4223034882
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.51086456
Short name T376
Test name
Test status
Simulation time 407017156 ps
CPU time 1.78 seconds
Started Jun 07 08:28:42 PM PDT 24
Finished Jun 07 08:28:56 PM PDT 24
Peak memory 198364 kb
Host smart-dc70c41c-70dd-4059-8f28-ca58f05744da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51086456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.51086456
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.547157506
Short name T387
Test name
Test status
Simulation time 8048164346 ps
CPU time 12.25 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:29:09 PM PDT 24
Peak memory 198136 kb
Host smart-e2a198ac-0838-4df8-9050-295f4f4bb5aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547157506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.547157506
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.766557575
Short name T335
Test name
Test status
Simulation time 505337131 ps
CPU time 0.95 seconds
Started Jun 07 08:28:49 PM PDT 24
Finished Jun 07 08:29:05 PM PDT 24
Peak memory 192900 kb
Host smart-200f32ab-a7e6-412b-93d9-56bc72528e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766557575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.766557575
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3755201267
Short name T284
Test name
Test status
Simulation time 320788461 ps
CPU time 0.62 seconds
Started Jun 07 08:28:52 PM PDT 24
Finished Jun 07 08:29:08 PM PDT 24
Peak memory 183656 kb
Host smart-7ea8f964-361b-4552-ae36-50ada24c38c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755201267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3755201267
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3580846306
Short name T418
Test name
Test status
Simulation time 316883339 ps
CPU time 0.96 seconds
Started Jun 07 08:28:51 PM PDT 24
Finished Jun 07 08:29:07 PM PDT 24
Peak memory 183636 kb
Host smart-380945ce-2ece-48b3-838f-132eb3ba5eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580846306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3580846306
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.117204397
Short name T289
Test name
Test status
Simulation time 402323964 ps
CPU time 0.67 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:15 PM PDT 24
Peak memory 183644 kb
Host smart-7b353c84-53e1-4b83-8ea3-56a154976f97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117204397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.117204397
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3426916860
Short name T332
Test name
Test status
Simulation time 370161409 ps
CPU time 0.8 seconds
Started Jun 07 08:28:56 PM PDT 24
Finished Jun 07 08:29:14 PM PDT 24
Peak memory 183564 kb
Host smart-ec3b0d66-dd3b-491c-8c40-be702d3218f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426916860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3426916860
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.342593151
Short name T371
Test name
Test status
Simulation time 308486576 ps
CPU time 0.62 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:11 PM PDT 24
Peak memory 183640 kb
Host smart-5f4010d3-16e9-4cb1-b22f-dced19042264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342593151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.342593151
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1501554149
Short name T324
Test name
Test status
Simulation time 371466801 ps
CPU time 0.84 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:17 PM PDT 24
Peak memory 183660 kb
Host smart-bcb8ba28-c45d-4a4c-a4b0-6b739ed93d29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501554149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1501554149
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.416951471
Short name T322
Test name
Test status
Simulation time 403514258 ps
CPU time 0.7 seconds
Started Jun 07 08:29:00 PM PDT 24
Finished Jun 07 08:29:18 PM PDT 24
Peak memory 183660 kb
Host smart-9e49ce87-a1fc-41fe-aab6-849c41307813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416951471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.416951471
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2367015401
Short name T354
Test name
Test status
Simulation time 310554806 ps
CPU time 0.82 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:17 PM PDT 24
Peak memory 192824 kb
Host smart-e0c80a23-1801-4912-9a63-1f21a884c7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367015401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2367015401
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3155886619
Short name T395
Test name
Test status
Simulation time 332498022 ps
CPU time 1.03 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:15 PM PDT 24
Peak memory 183560 kb
Host smart-e2d04a5d-c7c6-4f11-b37c-40e1fbdd500f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155886619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3155886619
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4008214642
Short name T347
Test name
Test status
Simulation time 578800231 ps
CPU time 0.97 seconds
Started Jun 07 08:28:35 PM PDT 24
Finished Jun 07 08:28:49 PM PDT 24
Peak memory 196696 kb
Host smart-43b4be07-963d-420c-b9fb-c57512f49fe2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008214642 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.4008214642
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3336150477
Short name T57
Test name
Test status
Simulation time 541606656 ps
CPU time 0.77 seconds
Started Jun 07 08:28:46 PM PDT 24
Finished Jun 07 08:29:00 PM PDT 24
Peak memory 191940 kb
Host smart-8a417ae8-aa2f-475b-b9f8-4610e0a75cbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336150477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3336150477
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3796761152
Short name T288
Test name
Test status
Simulation time 439294487 ps
CPU time 0.85 seconds
Started Jun 07 08:28:46 PM PDT 24
Finished Jun 07 08:28:59 PM PDT 24
Peak memory 192816 kb
Host smart-73acb333-0378-416c-a537-455402a2b837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796761152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3796761152
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1070442569
Short name T350
Test name
Test status
Simulation time 2427021075 ps
CPU time 3.86 seconds
Started Jun 07 08:28:43 PM PDT 24
Finished Jun 07 08:29:00 PM PDT 24
Peak memory 194332 kb
Host smart-a65984a4-943f-459c-b646-ccd982320937
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070442569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1070442569
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3835504494
Short name T394
Test name
Test status
Simulation time 484306386 ps
CPU time 1.42 seconds
Started Jun 07 08:28:39 PM PDT 24
Finished Jun 07 08:28:52 PM PDT 24
Peak memory 198364 kb
Host smart-9cafc005-d87f-4c5b-9df1-363f3a48ae34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835504494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3835504494
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1293328084
Short name T325
Test name
Test status
Simulation time 8998344910 ps
CPU time 4.14 seconds
Started Jun 07 08:28:40 PM PDT 24
Finished Jun 07 08:28:57 PM PDT 24
Peak memory 198312 kb
Host smart-8104679e-797f-4337-9432-760bc160689a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293328084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1293328084
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2808743514
Short name T348
Test name
Test status
Simulation time 515654594 ps
CPU time 0.96 seconds
Started Jun 07 08:28:45 PM PDT 24
Finished Jun 07 08:28:59 PM PDT 24
Peak memory 198164 kb
Host smart-472b7be4-55ed-44cc-bfaf-6621ee696cec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808743514 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2808743514
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2350623008
Short name T360
Test name
Test status
Simulation time 389233111 ps
CPU time 0.68 seconds
Started Jun 07 08:28:40 PM PDT 24
Finished Jun 07 08:28:52 PM PDT 24
Peak memory 192860 kb
Host smart-43040e9e-aad7-4f31-a77c-72f78785628b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350623008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2350623008
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.547291509
Short name T368
Test name
Test status
Simulation time 1401115815 ps
CPU time 2.9 seconds
Started Jun 07 08:28:43 PM PDT 24
Finished Jun 07 08:28:58 PM PDT 24
Peak memory 193928 kb
Host smart-28d51f28-dd76-4723-a347-e44669c285c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547291509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.547291509
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.267394346
Short name T294
Test name
Test status
Simulation time 569173619 ps
CPU time 1.9 seconds
Started Jun 07 08:28:36 PM PDT 24
Finished Jun 07 08:28:51 PM PDT 24
Peak memory 198416 kb
Host smart-0e589b3b-7ad1-453c-b171-87a6bb5a8203
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267394346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.267394346
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4164593437
Short name T366
Test name
Test status
Simulation time 8432422051 ps
CPU time 4.4 seconds
Started Jun 07 08:28:51 PM PDT 24
Finished Jun 07 08:29:10 PM PDT 24
Peak memory 198120 kb
Host smart-7c5deafe-15c4-4aff-8362-6a6505064545
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164593437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.4164593437
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3434767152
Short name T328
Test name
Test status
Simulation time 459893522 ps
CPU time 1.28 seconds
Started Jun 07 08:28:45 PM PDT 24
Finished Jun 07 08:28:59 PM PDT 24
Peak memory 195848 kb
Host smart-9d9af6d4-86aa-4891-955b-8caaf34ac0d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434767152 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3434767152
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4125151958
Short name T379
Test name
Test status
Simulation time 495846559 ps
CPU time 1.34 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:28:58 PM PDT 24
Peak memory 193412 kb
Host smart-10a3316f-f451-49e2-8090-b5fc7e19ddac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125151958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.4125151958
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1071036479
Short name T326
Test name
Test status
Simulation time 480584469 ps
CPU time 1.3 seconds
Started Jun 07 08:28:49 PM PDT 24
Finished Jun 07 08:29:05 PM PDT 24
Peak memory 183644 kb
Host smart-62dc30f9-fb77-4a60-b4a2-3491250fc841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071036479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1071036479
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3288713328
Short name T309
Test name
Test status
Simulation time 2332647309 ps
CPU time 3.87 seconds
Started Jun 07 08:28:51 PM PDT 24
Finished Jun 07 08:29:10 PM PDT 24
Peak memory 191948 kb
Host smart-56218398-8f29-4867-8c01-409f79cbfa2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288713328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3288713328
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2537809280
Short name T287
Test name
Test status
Simulation time 496020756 ps
CPU time 2.31 seconds
Started Jun 07 08:28:38 PM PDT 24
Finished Jun 07 08:28:52 PM PDT 24
Peak memory 198508 kb
Host smart-191d09cc-8f26-4160-b58f-c2a76fe91399
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537809280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2537809280
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4073257507
Short name T406
Test name
Test status
Simulation time 7930668369 ps
CPU time 12.59 seconds
Started Jun 07 08:28:56 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 198152 kb
Host smart-2c33aeeb-185f-4a70-81f3-51a1feca067a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073257507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.4073257507
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.828781736
Short name T340
Test name
Test status
Simulation time 356843817 ps
CPU time 1.15 seconds
Started Jun 07 08:28:49 PM PDT 24
Finished Jun 07 08:29:05 PM PDT 24
Peak memory 196076 kb
Host smart-86eaf9e8-d512-4976-bff6-00777beb562b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828781736 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.828781736
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.27480569
Short name T399
Test name
Test status
Simulation time 300491893 ps
CPU time 0.93 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:28:57 PM PDT 24
Peak memory 193844 kb
Host smart-b7f08a00-8644-410f-8f66-d7e3d9a5534e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27480569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.27480569
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.897199054
Short name T304
Test name
Test status
Simulation time 337535353 ps
CPU time 0.79 seconds
Started Jun 07 08:28:48 PM PDT 24
Finished Jun 07 08:29:03 PM PDT 24
Peak memory 183672 kb
Host smart-9b6f723c-456f-45be-ad76-cebe90b8e5a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897199054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.897199054
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4083838896
Short name T312
Test name
Test status
Simulation time 1691293415 ps
CPU time 1.21 seconds
Started Jun 07 08:28:48 PM PDT 24
Finished Jun 07 08:29:03 PM PDT 24
Peak memory 193748 kb
Host smart-491086f7-9ba9-4c92-9087-ecb7ffeca739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083838896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4083838896
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.638083471
Short name T410
Test name
Test status
Simulation time 452566369 ps
CPU time 1.76 seconds
Started Jun 07 08:28:49 PM PDT 24
Finished Jun 07 08:29:07 PM PDT 24
Peak memory 198436 kb
Host smart-cc91d68a-ab05-488f-ad22-7fb0225cf684
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638083471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.638083471
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3255776999
Short name T359
Test name
Test status
Simulation time 4377747779 ps
CPU time 7.09 seconds
Started Jun 07 08:28:50 PM PDT 24
Finished Jun 07 08:29:12 PM PDT 24
Peak memory 197908 kb
Host smart-d59b13d8-3697-45c3-9c67-61d3c7f1ba33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255776999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3255776999
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.295841873
Short name T344
Test name
Test status
Simulation time 552554522 ps
CPU time 1.15 seconds
Started Jun 07 08:28:43 PM PDT 24
Finished Jun 07 08:28:58 PM PDT 24
Peak memory 198236 kb
Host smart-e231bace-d0bb-4d06-85f1-06376f2452d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295841873 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.295841873
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.624407354
Short name T61
Test name
Test status
Simulation time 328692206 ps
CPU time 0.8 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:28:57 PM PDT 24
Peak memory 193168 kb
Host smart-7e1fd285-55ed-4438-aaff-93b790a03128
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624407354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.624407354
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2463729108
Short name T321
Test name
Test status
Simulation time 498744996 ps
CPU time 0.71 seconds
Started Jun 07 08:28:44 PM PDT 24
Finished Jun 07 08:28:57 PM PDT 24
Peak memory 183636 kb
Host smart-ba86a3b2-0f65-4bf0-833b-9599e42e43fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463729108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2463729108
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3051559623
Short name T306
Test name
Test status
Simulation time 1190319186 ps
CPU time 2.64 seconds
Started Jun 07 08:28:47 PM PDT 24
Finished Jun 07 08:29:03 PM PDT 24
Peak memory 193492 kb
Host smart-aad81635-13a5-4e31-9989-9f14a1b21a9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051559623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3051559623
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2344101638
Short name T402
Test name
Test status
Simulation time 369428591 ps
CPU time 1.65 seconds
Started Jun 07 08:28:46 PM PDT 24
Finished Jun 07 08:29:00 PM PDT 24
Peak memory 198420 kb
Host smart-1d709033-0a1e-4f90-878b-46ca251712bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344101638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2344101638
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.750406276
Short name T390
Test name
Test status
Simulation time 4071164617 ps
CPU time 5.06 seconds
Started Jun 07 08:28:50 PM PDT 24
Finished Jun 07 08:29:10 PM PDT 24
Peak memory 196824 kb
Host smart-eeca1c12-6268-44ae-8ed4-5cd256a221d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750406276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.750406276
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3735347060
Short name T233
Test name
Test status
Simulation time 23127915771 ps
CPU time 38.05 seconds
Started Jun 07 08:01:38 PM PDT 24
Finished Jun 07 08:02:18 PM PDT 24
Peak memory 191900 kb
Host smart-a928126b-2170-4775-80c7-4c9ff10f07b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735347060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3735347060
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.4257756330
Short name T4
Test name
Test status
Simulation time 588936199 ps
CPU time 1.02 seconds
Started Jun 07 08:01:34 PM PDT 24
Finished Jun 07 08:01:36 PM PDT 24
Peak memory 191808 kb
Host smart-80b06f86-9048-4b06-8441-937c129fe8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257756330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.4257756330
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2449715655
Short name T43
Test name
Test status
Simulation time 24720180412 ps
CPU time 3.57 seconds
Started Jun 07 08:01:37 PM PDT 24
Finished Jun 07 08:01:41 PM PDT 24
Peak memory 191928 kb
Host smart-9a8bb98a-1fad-49ba-8d42-48a01a99bcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449715655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2449715655
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3206996381
Short name T20
Test name
Test status
Simulation time 8104869650 ps
CPU time 7.47 seconds
Started Jun 07 08:01:37 PM PDT 24
Finished Jun 07 08:01:46 PM PDT 24
Peak memory 215964 kb
Host smart-19827e67-7022-4bfb-9232-e538cd9fff0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206996381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3206996381
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.4054227640
Short name T199
Test name
Test status
Simulation time 389123568 ps
CPU time 0.87 seconds
Started Jun 07 08:01:39 PM PDT 24
Finished Jun 07 08:01:43 PM PDT 24
Peak memory 191796 kb
Host smart-023944b1-bb95-4653-9693-ba781288ca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054227640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.4054227640
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.630982956
Short name T228
Test name
Test status
Simulation time 56706417696 ps
CPU time 24.19 seconds
Started Jun 07 08:01:46 PM PDT 24
Finished Jun 07 08:02:13 PM PDT 24
Peak memory 191904 kb
Host smart-c9db96c3-13b6-4c61-a439-48984f087518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630982956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.630982956
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3163949527
Short name T211
Test name
Test status
Simulation time 504888331 ps
CPU time 0.69 seconds
Started Jun 07 08:01:51 PM PDT 24
Finished Jun 07 08:01:53 PM PDT 24
Peak memory 191764 kb
Host smart-b0365a2c-bf30-4999-a8d4-77385187ead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163949527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3163949527
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3338004618
Short name T252
Test name
Test status
Simulation time 46465792957 ps
CPU time 38.36 seconds
Started Jun 07 08:01:46 PM PDT 24
Finished Jun 07 08:02:27 PM PDT 24
Peak memory 191900 kb
Host smart-a2b831dc-2b83-4406-85ec-d2eb537ae59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338004618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3338004618
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3922995948
Short name T225
Test name
Test status
Simulation time 534853775 ps
CPU time 0.8 seconds
Started Jun 07 08:01:45 PM PDT 24
Finished Jun 07 08:01:48 PM PDT 24
Peak memory 191788 kb
Host smart-43f074dc-353b-45ce-baff-f63fc03f4c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922995948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3922995948
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.4259989305
Short name T263
Test name
Test status
Simulation time 7111540079 ps
CPU time 9.07 seconds
Started Jun 07 08:01:47 PM PDT 24
Finished Jun 07 08:01:58 PM PDT 24
Peak memory 191848 kb
Host smart-054a2009-01ca-4285-8e7b-16c7aca3c630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259989305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.4259989305
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1773947160
Short name T195
Test name
Test status
Simulation time 457020188 ps
CPU time 0.78 seconds
Started Jun 07 08:01:46 PM PDT 24
Finished Jun 07 08:01:49 PM PDT 24
Peak memory 191760 kb
Host smart-c5e95ddf-b14a-4860-b77f-4d1433f2987c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773947160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1773947160
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.358473019
Short name T34
Test name
Test status
Simulation time 52069580862 ps
CPU time 389.48 seconds
Started Jun 07 08:01:46 PM PDT 24
Finished Jun 07 08:08:18 PM PDT 24
Peak memory 208192 kb
Host smart-3f9d78c9-273e-486f-b387-afd67eec82e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358473019 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.358473019
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2817460272
Short name T273
Test name
Test status
Simulation time 28785431218 ps
CPU time 24.21 seconds
Started Jun 07 08:01:50 PM PDT 24
Finished Jun 07 08:02:15 PM PDT 24
Peak memory 191928 kb
Host smart-994ff92e-e5ac-4a17-aefe-81bcc316e2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817460272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2817460272
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.405870332
Short name T262
Test name
Test status
Simulation time 546302225 ps
CPU time 0.99 seconds
Started Jun 07 08:01:53 PM PDT 24
Finished Jun 07 08:01:56 PM PDT 24
Peak memory 191784 kb
Host smart-8d5169e7-cd04-4e0a-a893-47d2f47f26e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405870332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.405870332
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3889670656
Short name T202
Test name
Test status
Simulation time 25867928099 ps
CPU time 6.37 seconds
Started Jun 07 08:01:49 PM PDT 24
Finished Jun 07 08:01:57 PM PDT 24
Peak memory 191880 kb
Host smart-c88c343d-f99e-4e62-b145-672af8d9e5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889670656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3889670656
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.946900334
Short name T218
Test name
Test status
Simulation time 477450463 ps
CPU time 1.28 seconds
Started Jun 07 08:01:44 PM PDT 24
Finished Jun 07 08:01:47 PM PDT 24
Peak memory 196572 kb
Host smart-d1e2b0a2-b8f4-422d-b296-51ab01708a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946900334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.946900334
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2646432834
Short name T244
Test name
Test status
Simulation time 9417261054 ps
CPU time 2.59 seconds
Started Jun 07 08:01:55 PM PDT 24
Finished Jun 07 08:02:00 PM PDT 24
Peak memory 191912 kb
Host smart-727d146c-c300-46e0-92b2-13946946efbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646432834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2646432834
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.25815667
Short name T201
Test name
Test status
Simulation time 401500120 ps
CPU time 1.14 seconds
Started Jun 07 08:01:54 PM PDT 24
Finished Jun 07 08:01:57 PM PDT 24
Peak memory 191804 kb
Host smart-60b9e9fd-1edb-4c5b-8627-fe93578ea7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25815667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.25815667
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2151483848
Short name T231
Test name
Test status
Simulation time 33548986157 ps
CPU time 23.1 seconds
Started Jun 07 08:01:53 PM PDT 24
Finished Jun 07 08:02:18 PM PDT 24
Peak memory 191932 kb
Host smart-22183f1f-256e-45b5-b109-6999b847c982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151483848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2151483848
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3968180466
Short name T226
Test name
Test status
Simulation time 442729769 ps
CPU time 1.28 seconds
Started Jun 07 08:01:53 PM PDT 24
Finished Jun 07 08:01:56 PM PDT 24
Peak memory 191784 kb
Host smart-f0c21427-1538-438e-813b-0149ab57df50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968180466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3968180466
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.4126819321
Short name T223
Test name
Test status
Simulation time 8649822656 ps
CPU time 6.96 seconds
Started Jun 07 08:01:52 PM PDT 24
Finished Jun 07 08:02:01 PM PDT 24
Peak memory 191896 kb
Host smart-ef1e7180-6712-47c0-a200-e9dd237f35a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126819321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.4126819321
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.92616708
Short name T198
Test name
Test status
Simulation time 523620678 ps
CPU time 0.97 seconds
Started Jun 07 08:01:53 PM PDT 24
Finished Jun 07 08:01:56 PM PDT 24
Peak memory 191788 kb
Host smart-30537c6c-2c56-4067-b4c8-59a3341cb32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92616708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.92616708
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.362946676
Short name T217
Test name
Test status
Simulation time 12711347307 ps
CPU time 21.48 seconds
Started Jun 07 08:02:02 PM PDT 24
Finished Jun 07 08:02:25 PM PDT 24
Peak memory 191912 kb
Host smart-0eed5da1-5802-43a7-b805-c3d485751eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362946676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.362946676
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3231224741
Short name T243
Test name
Test status
Simulation time 517592013 ps
CPU time 0.79 seconds
Started Jun 07 08:01:53 PM PDT 24
Finished Jun 07 08:01:56 PM PDT 24
Peak memory 191788 kb
Host smart-09356646-df5e-4e6d-9943-57e92335c2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231224741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3231224741
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3965728008
Short name T248
Test name
Test status
Simulation time 27270371994 ps
CPU time 11.84 seconds
Started Jun 07 08:01:52 PM PDT 24
Finished Jun 07 08:02:06 PM PDT 24
Peak memory 191844 kb
Host smart-5f5df4be-9e63-4db6-b755-8d241d30c0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965728008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3965728008
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1025889204
Short name T265
Test name
Test status
Simulation time 356626494 ps
CPU time 1.25 seconds
Started Jun 07 08:01:56 PM PDT 24
Finished Jun 07 08:01:59 PM PDT 24
Peak memory 196528 kb
Host smart-5ad57765-f7fb-4228-9ecd-eb4bcbb2885e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025889204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1025889204
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2383163191
Short name T221
Test name
Test status
Simulation time 20123533240 ps
CPU time 8.72 seconds
Started Jun 07 08:01:40 PM PDT 24
Finished Jun 07 08:01:51 PM PDT 24
Peak memory 191836 kb
Host smart-194294f1-ed2c-44b2-9219-47e39c315948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383163191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2383163191
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1133513906
Short name T22
Test name
Test status
Simulation time 4438189153 ps
CPU time 1.59 seconds
Started Jun 07 08:01:41 PM PDT 24
Finished Jun 07 08:01:44 PM PDT 24
Peak memory 215828 kb
Host smart-e86facf6-1157-4ea5-82c5-54902187ffef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133513906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1133513906
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1782937453
Short name T203
Test name
Test status
Simulation time 495264636 ps
CPU time 0.94 seconds
Started Jun 07 08:01:40 PM PDT 24
Finished Jun 07 08:01:43 PM PDT 24
Peak memory 191740 kb
Host smart-aed6c05a-567b-48eb-9623-c4f8746f8cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782937453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1782937453
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.333829777
Short name T39
Test name
Test status
Simulation time 5110401159 ps
CPU time 7.5 seconds
Started Jun 07 08:01:53 PM PDT 24
Finished Jun 07 08:02:02 PM PDT 24
Peak memory 191904 kb
Host smart-a9a6814d-fb44-4161-a820-be0d9a21a22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333829777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.333829777
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.137148678
Short name T264
Test name
Test status
Simulation time 431627272 ps
CPU time 1.28 seconds
Started Jun 07 08:01:54 PM PDT 24
Finished Jun 07 08:01:57 PM PDT 24
Peak memory 191804 kb
Host smart-978fe5da-ad7d-451d-a9ec-1749e119500e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137148678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.137148678
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2096248758
Short name T267
Test name
Test status
Simulation time 8582288567 ps
CPU time 3.6 seconds
Started Jun 07 08:02:02 PM PDT 24
Finished Jun 07 08:02:07 PM PDT 24
Peak memory 191896 kb
Host smart-3010e97d-b088-4fdb-bcbf-5e732344edda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096248758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2096248758
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1162703232
Short name T205
Test name
Test status
Simulation time 500743782 ps
CPU time 0.7 seconds
Started Jun 07 08:02:00 PM PDT 24
Finished Jun 07 08:02:02 PM PDT 24
Peak memory 191708 kb
Host smart-e0ec5576-6e19-4561-a34e-b13d993fc00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162703232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1162703232
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2556266596
Short name T12
Test name
Test status
Simulation time 32750641000 ps
CPU time 21.62 seconds
Started Jun 07 08:02:03 PM PDT 24
Finished Jun 07 08:02:26 PM PDT 24
Peak memory 191924 kb
Host smart-7448c70c-ba87-49a3-ac68-9f59e3fca9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556266596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2556266596
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3327265930
Short name T216
Test name
Test status
Simulation time 533878096 ps
CPU time 0.79 seconds
Started Jun 07 08:02:01 PM PDT 24
Finished Jun 07 08:02:03 PM PDT 24
Peak memory 191756 kb
Host smart-3b0d23d0-c9bd-4a88-a6ab-982ee2f82d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327265930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3327265930
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.268779744
Short name T5
Test name
Test status
Simulation time 26702964602 ps
CPU time 39.44 seconds
Started Jun 07 08:02:08 PM PDT 24
Finished Jun 07 08:02:48 PM PDT 24
Peak memory 191920 kb
Host smart-5c6af2a4-d777-45e6-9976-292a08c89201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268779744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.268779744
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1681403988
Short name T207
Test name
Test status
Simulation time 372515309 ps
CPU time 0.88 seconds
Started Jun 07 08:02:07 PM PDT 24
Finished Jun 07 08:02:09 PM PDT 24
Peak memory 196576 kb
Host smart-8daaf6f1-cb1e-4c8d-b2e7-c9fce22c90f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681403988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1681403988
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2772243104
Short name T212
Test name
Test status
Simulation time 25338123844 ps
CPU time 10.67 seconds
Started Jun 07 08:02:01 PM PDT 24
Finished Jun 07 08:02:13 PM PDT 24
Peak memory 191848 kb
Host smart-cbf9f60c-f7d6-4ae8-a91a-466cd3941263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772243104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2772243104
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3759461040
Short name T235
Test name
Test status
Simulation time 392553036 ps
CPU time 0.72 seconds
Started Jun 07 08:02:11 PM PDT 24
Finished Jun 07 08:02:14 PM PDT 24
Peak memory 196592 kb
Host smart-71d853ee-54dc-40ab-9c08-253967309d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759461040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3759461040
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3660241869
Short name T270
Test name
Test status
Simulation time 11108252146 ps
CPU time 4.86 seconds
Started Jun 07 08:02:08 PM PDT 24
Finished Jun 07 08:02:14 PM PDT 24
Peak memory 191928 kb
Host smart-6359d7e7-2024-4c61-bf35-7f92b9ff88a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660241869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3660241869
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3803679477
Short name T210
Test name
Test status
Simulation time 392698005 ps
CPU time 0.65 seconds
Started Jun 07 08:02:11 PM PDT 24
Finished Jun 07 08:02:14 PM PDT 24
Peak memory 191816 kb
Host smart-608d3081-95d8-4ab4-ba73-fe882a939923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803679477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3803679477
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1286131216
Short name T237
Test name
Test status
Simulation time 29622365299 ps
CPU time 21.48 seconds
Started Jun 07 08:02:10 PM PDT 24
Finished Jun 07 08:02:34 PM PDT 24
Peak memory 191944 kb
Host smart-9dcf2aa6-5d6a-4f6e-bbbf-c0e6cc9ad24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286131216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1286131216
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3691660058
Short name T194
Test name
Test status
Simulation time 410667082 ps
CPU time 0.89 seconds
Started Jun 07 08:02:13 PM PDT 24
Finished Jun 07 08:02:16 PM PDT 24
Peak memory 191904 kb
Host smart-5dc67f55-3383-4f4a-b1fe-60c3074589b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691660058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3691660058
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.530120998
Short name T200
Test name
Test status
Simulation time 11573828562 ps
CPU time 3.48 seconds
Started Jun 07 08:02:12 PM PDT 24
Finished Jun 07 08:02:18 PM PDT 24
Peak memory 191764 kb
Host smart-ffb4fa4e-f6a3-4401-94d3-0ee119ffb43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530120998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.530120998
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.881096504
Short name T260
Test name
Test status
Simulation time 488387973 ps
CPU time 1.09 seconds
Started Jun 07 08:02:10 PM PDT 24
Finished Jun 07 08:02:14 PM PDT 24
Peak memory 196636 kb
Host smart-e7019686-ddbc-4e5c-8f55-8ffcfb0cb5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881096504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.881096504
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.832225837
Short name T269
Test name
Test status
Simulation time 748401814 ps
CPU time 1.36 seconds
Started Jun 07 08:02:10 PM PDT 24
Finished Jun 07 08:02:15 PM PDT 24
Peak memory 191800 kb
Host smart-094fe8a2-d789-42e3-bcc2-a8c0d59d630d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832225837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.832225837
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1294434808
Short name T266
Test name
Test status
Simulation time 428256408 ps
CPU time 1.25 seconds
Started Jun 07 08:02:12 PM PDT 24
Finished Jun 07 08:02:16 PM PDT 24
Peak memory 191776 kb
Host smart-fa85da61-959b-4979-90b0-889e1bcf3c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294434808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1294434808
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.844893344
Short name T232
Test name
Test status
Simulation time 21050694937 ps
CPU time 9.42 seconds
Started Jun 07 08:02:11 PM PDT 24
Finished Jun 07 08:02:24 PM PDT 24
Peak memory 191892 kb
Host smart-7ab5b18d-0b12-4668-b9ac-47cb7cae753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844893344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.844893344
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3475822784
Short name T196
Test name
Test status
Simulation time 455920133 ps
CPU time 1.22 seconds
Started Jun 07 08:02:10 PM PDT 24
Finished Jun 07 08:02:13 PM PDT 24
Peak memory 191788 kb
Host smart-1e60a92f-c7fc-4c41-b5e1-06789708a5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475822784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3475822784
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.77638024
Short name T204
Test name
Test status
Simulation time 8551119627 ps
CPU time 2.35 seconds
Started Jun 07 08:01:39 PM PDT 24
Finished Jun 07 08:01:44 PM PDT 24
Peak memory 191880 kb
Host smart-c3b59a01-5814-47ba-8862-96ab347e4101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77638024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.77638024
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2505527515
Short name T11
Test name
Test status
Simulation time 4434512005 ps
CPU time 1.58 seconds
Started Jun 07 08:01:40 PM PDT 24
Finished Jun 07 08:01:44 PM PDT 24
Peak memory 215740 kb
Host smart-a85fb156-1bdb-4f6f-b303-861b41f060de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505527515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2505527515
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.610473079
Short name T83
Test name
Test status
Simulation time 436084993 ps
CPU time 0.92 seconds
Started Jun 07 08:01:37 PM PDT 24
Finished Jun 07 08:01:39 PM PDT 24
Peak memory 191744 kb
Host smart-f6114593-2ece-44a4-a28f-1772c1534d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610473079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.610473079
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1166276559
Short name T271
Test name
Test status
Simulation time 28171740706 ps
CPU time 45.31 seconds
Started Jun 07 08:02:11 PM PDT 24
Finished Jun 07 08:03:00 PM PDT 24
Peak memory 191932 kb
Host smart-78484c51-327a-4224-93b7-d42734583597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166276559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1166276559
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3337998145
Short name T272
Test name
Test status
Simulation time 377564905 ps
CPU time 1.17 seconds
Started Jun 07 08:02:11 PM PDT 24
Finished Jun 07 08:02:15 PM PDT 24
Peak memory 191728 kb
Host smart-2902555e-e2c2-402a-bba0-94fd9d077c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337998145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3337998145
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.382260163
Short name T247
Test name
Test status
Simulation time 36855994361 ps
CPU time 16.22 seconds
Started Jun 07 08:02:11 PM PDT 24
Finished Jun 07 08:02:30 PM PDT 24
Peak memory 191904 kb
Host smart-4e7985e1-6c69-4cda-8eb9-83acca7bb96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382260163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.382260163
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1079483477
Short name T24
Test name
Test status
Simulation time 403219601 ps
CPU time 0.73 seconds
Started Jun 07 08:02:12 PM PDT 24
Finished Jun 07 08:02:15 PM PDT 24
Peak memory 191760 kb
Host smart-66ce9411-b260-456b-9ad6-b7002171ef45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079483477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1079483477
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2758567759
Short name T209
Test name
Test status
Simulation time 27936981325 ps
CPU time 12.4 seconds
Started Jun 07 08:02:12 PM PDT 24
Finished Jun 07 08:02:28 PM PDT 24
Peak memory 192040 kb
Host smart-9755d39b-becf-438a-8136-5d0ed98c3e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758567759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2758567759
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1984089944
Short name T258
Test name
Test status
Simulation time 562472920 ps
CPU time 0.79 seconds
Started Jun 07 08:02:13 PM PDT 24
Finished Jun 07 08:02:17 PM PDT 24
Peak memory 196592 kb
Host smart-1f9582d7-235e-4109-8fba-05fb0f5cab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984089944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1984089944
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.533510965
Short name T49
Test name
Test status
Simulation time 26025285300 ps
CPU time 19.34 seconds
Started Jun 07 08:02:09 PM PDT 24
Finished Jun 07 08:02:29 PM PDT 24
Peak memory 191900 kb
Host smart-2d810b66-66c2-48f7-a0fc-f62831049b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533510965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.533510965
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.274499782
Short name T14
Test name
Test status
Simulation time 442481534 ps
CPU time 0.7 seconds
Started Jun 07 08:02:10 PM PDT 24
Finished Jun 07 08:02:13 PM PDT 24
Peak memory 191744 kb
Host smart-f1ff2e4e-1cee-4dff-b6c3-4661e0082c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274499782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.274499782
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3890291354
Short name T229
Test name
Test status
Simulation time 909129942 ps
CPU time 0.73 seconds
Started Jun 07 08:02:23 PM PDT 24
Finished Jun 07 08:02:26 PM PDT 24
Peak memory 191840 kb
Host smart-2b1d5bab-2851-4407-9ddc-0ab48f3ff9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890291354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3890291354
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3717695484
Short name T2
Test name
Test status
Simulation time 466703725 ps
CPU time 0.78 seconds
Started Jun 07 08:02:19 PM PDT 24
Finished Jun 07 08:02:22 PM PDT 24
Peak memory 191788 kb
Host smart-4133fe5b-422e-4475-aa8e-50ee0bde4043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717695484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3717695484
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1022061054
Short name T168
Test name
Test status
Simulation time 497192761 ps
CPU time 1.36 seconds
Started Jun 07 08:02:17 PM PDT 24
Finished Jun 07 08:02:20 PM PDT 24
Peak memory 196524 kb
Host smart-6be3ce42-930b-401e-b196-fa918c2ece93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022061054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1022061054
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3716773803
Short name T255
Test name
Test status
Simulation time 38524073731 ps
CPU time 14.03 seconds
Started Jun 07 08:02:19 PM PDT 24
Finished Jun 07 08:02:35 PM PDT 24
Peak memory 191904 kb
Host smart-19b8d677-db1d-4da4-b19f-0db7c8ebd25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716773803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3716773803
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1807542534
Short name T48
Test name
Test status
Simulation time 484993311 ps
CPU time 1.44 seconds
Started Jun 07 08:02:19 PM PDT 24
Finished Jun 07 08:02:23 PM PDT 24
Peak memory 196568 kb
Host smart-ee9b92dd-8638-4754-ac29-e02674d819d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807542534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1807542534
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1134376053
Short name T234
Test name
Test status
Simulation time 30591705241 ps
CPU time 53.71 seconds
Started Jun 07 08:02:20 PM PDT 24
Finished Jun 07 08:03:16 PM PDT 24
Peak memory 191928 kb
Host smart-92181488-3d94-41aa-a64e-61aac67cbe40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134376053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1134376053
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.626564288
Short name T193
Test name
Test status
Simulation time 405204508 ps
CPU time 0.73 seconds
Started Jun 07 08:02:18 PM PDT 24
Finished Jun 07 08:02:21 PM PDT 24
Peak memory 191792 kb
Host smart-25281598-1599-43bb-b009-3b205df5f7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626564288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.626564288
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.735161878
Short name T254
Test name
Test status
Simulation time 36840356577 ps
CPU time 14.37 seconds
Started Jun 07 08:02:23 PM PDT 24
Finished Jun 07 08:02:40 PM PDT 24
Peak memory 191980 kb
Host smart-0492ad8b-1b47-4e79-8ef4-1167b3dd0e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735161878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.735161878
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1093883828
Short name T197
Test name
Test status
Simulation time 352339498 ps
CPU time 0.8 seconds
Started Jun 07 08:02:20 PM PDT 24
Finished Jun 07 08:02:23 PM PDT 24
Peak memory 191792 kb
Host smart-c42a38f6-2fde-4c5c-802b-4d77ef3e5b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093883828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1093883828
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.970465046
Short name T37
Test name
Test status
Simulation time 114766843991 ps
CPU time 191.22 seconds
Started Jun 07 08:02:17 PM PDT 24
Finished Jun 07 08:05:30 PM PDT 24
Peak memory 199900 kb
Host smart-c272d8d5-39a9-4040-b48b-907dfec5f6d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970465046 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.970465046
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2832660018
Short name T236
Test name
Test status
Simulation time 23406371591 ps
CPU time 34.22 seconds
Started Jun 07 08:02:22 PM PDT 24
Finished Jun 07 08:02:59 PM PDT 24
Peak memory 191936 kb
Host smart-34ab5c8d-1b3e-43f9-b4f1-19285a4c083b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832660018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2832660018
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3423672843
Short name T245
Test name
Test status
Simulation time 566254641 ps
CPU time 0.75 seconds
Started Jun 07 08:02:23 PM PDT 24
Finished Jun 07 08:02:26 PM PDT 24
Peak memory 196532 kb
Host smart-b6ebcce9-69d2-4cbc-a73c-d95ef1fac55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423672843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3423672843
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1981028261
Short name T253
Test name
Test status
Simulation time 30080365292 ps
CPU time 3.11 seconds
Started Jun 07 08:02:19 PM PDT 24
Finished Jun 07 08:02:24 PM PDT 24
Peak memory 191928 kb
Host smart-eb6c3892-ad82-4684-a4fd-dc1a2315af60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981028261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1981028261
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2656275917
Short name T257
Test name
Test status
Simulation time 376121221 ps
CPU time 0.72 seconds
Started Jun 07 08:02:18 PM PDT 24
Finished Jun 07 08:02:21 PM PDT 24
Peak memory 196604 kb
Host smart-5764719e-e561-46c6-b2db-f89b9aebe751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656275917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2656275917
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3655566746
Short name T239
Test name
Test status
Simulation time 12539944665 ps
CPU time 4.54 seconds
Started Jun 07 08:01:34 PM PDT 24
Finished Jun 07 08:01:40 PM PDT 24
Peak memory 191872 kb
Host smart-aa2bd912-dba6-4601-bf61-ba06896fa61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655566746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3655566746
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.147936260
Short name T19
Test name
Test status
Simulation time 4080193924 ps
CPU time 6.61 seconds
Started Jun 07 08:01:38 PM PDT 24
Finished Jun 07 08:01:47 PM PDT 24
Peak memory 215464 kb
Host smart-e6a8885e-2935-404c-a4a1-69fd1e784112
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147936260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.147936260
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.835942587
Short name T227
Test name
Test status
Simulation time 539390924 ps
CPU time 0.94 seconds
Started Jun 07 08:01:40 PM PDT 24
Finished Jun 07 08:01:43 PM PDT 24
Peak memory 196560 kb
Host smart-005df957-dfd3-44ab-be9e-3e967cc55273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835942587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.835942587
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2827132380
Short name T241
Test name
Test status
Simulation time 42313375107 ps
CPU time 15.12 seconds
Started Jun 07 08:02:19 PM PDT 24
Finished Jun 07 08:02:36 PM PDT 24
Peak memory 191928 kb
Host smart-129f6e57-d91f-42e5-8d0b-1d759dd3c88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827132380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2827132380
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2814516017
Short name T268
Test name
Test status
Simulation time 557750160 ps
CPU time 0.76 seconds
Started Jun 07 08:02:21 PM PDT 24
Finished Jun 07 08:02:25 PM PDT 24
Peak memory 196644 kb
Host smart-1caccfc3-33ff-4452-a7a2-9cf0f94e18a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814516017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2814516017
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2006506682
Short name T42
Test name
Test status
Simulation time 441176417 ps
CPU time 1.31 seconds
Started Jun 07 08:02:23 PM PDT 24
Finished Jun 07 08:02:27 PM PDT 24
Peak memory 196552 kb
Host smart-4a672b34-2ce6-42be-b7f3-a7bf8e9b6066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006506682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2006506682
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2290601595
Short name T214
Test name
Test status
Simulation time 13435577524 ps
CPU time 20.16 seconds
Started Jun 07 08:02:27 PM PDT 24
Finished Jun 07 08:02:50 PM PDT 24
Peak memory 191920 kb
Host smart-5c2294ee-a8a5-4544-9ed0-04fcc537d6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290601595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2290601595
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1557419572
Short name T259
Test name
Test status
Simulation time 340848779 ps
CPU time 0.77 seconds
Started Jun 07 08:02:26 PM PDT 24
Finished Jun 07 08:02:29 PM PDT 24
Peak memory 196576 kb
Host smart-42f2eefb-8f44-4d6b-8d8e-2daa653dcbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557419572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1557419572
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3409374445
Short name T222
Test name
Test status
Simulation time 22684113007 ps
CPU time 39.02 seconds
Started Jun 07 08:02:26 PM PDT 24
Finished Jun 07 08:03:08 PM PDT 24
Peak memory 191864 kb
Host smart-ca277dcb-cfe2-4483-9e82-996a897d4582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409374445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3409374445
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2801550911
Short name T261
Test name
Test status
Simulation time 490814733 ps
CPU time 1.34 seconds
Started Jun 07 08:02:23 PM PDT 24
Finished Jun 07 08:02:27 PM PDT 24
Peak memory 191764 kb
Host smart-2e161d5a-0469-4c0f-bee3-0371a21f7836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801550911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2801550911
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3838915488
Short name T224
Test name
Test status
Simulation time 5709065653 ps
CPU time 8.02 seconds
Started Jun 07 08:02:28 PM PDT 24
Finished Jun 07 08:02:39 PM PDT 24
Peak memory 191864 kb
Host smart-3dca9e05-a1c3-436a-9c24-26baf83ac8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838915488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3838915488
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1674849390
Short name T242
Test name
Test status
Simulation time 454814822 ps
CPU time 1.4 seconds
Started Jun 07 08:02:29 PM PDT 24
Finished Jun 07 08:02:33 PM PDT 24
Peak memory 191812 kb
Host smart-e012ff12-8b69-423e-a107-cf5d36d55051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674849390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1674849390
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3295292750
Short name T240
Test name
Test status
Simulation time 33184095719 ps
CPU time 48.1 seconds
Started Jun 07 08:02:30 PM PDT 24
Finished Jun 07 08:03:20 PM PDT 24
Peak memory 191804 kb
Host smart-16d7ab95-35cd-495e-a032-a033206c37af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295292750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3295292750
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1893521023
Short name T256
Test name
Test status
Simulation time 535234186 ps
CPU time 0.65 seconds
Started Jun 07 08:02:26 PM PDT 24
Finished Jun 07 08:02:29 PM PDT 24
Peak memory 191780 kb
Host smart-c7249561-3f02-4e00-a337-b8d9ec1c5c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893521023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1893521023
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_jump.976532408
Short name T162
Test name
Test status
Simulation time 649969107 ps
CPU time 0.66 seconds
Started Jun 07 08:02:28 PM PDT 24
Finished Jun 07 08:02:32 PM PDT 24
Peak memory 196492 kb
Host smart-621d81c5-9b06-4fe3-8b7b-8e978b7cede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976532408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.976532408
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1023208438
Short name T275
Test name
Test status
Simulation time 7163321215 ps
CPU time 3.51 seconds
Started Jun 07 08:02:30 PM PDT 24
Finished Jun 07 08:02:36 PM PDT 24
Peak memory 191832 kb
Host smart-e167e1bb-8f16-46ff-b0c3-8caf526d001c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023208438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1023208438
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2454524529
Short name T274
Test name
Test status
Simulation time 329267090 ps
CPU time 1.14 seconds
Started Jun 07 08:02:25 PM PDT 24
Finished Jun 07 08:02:28 PM PDT 24
Peak memory 196516 kb
Host smart-ce0944e6-4288-4c67-95d4-59cf4d560a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454524529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2454524529
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2853429170
Short name T238
Test name
Test status
Simulation time 43993647986 ps
CPU time 61.67 seconds
Started Jun 07 08:02:25 PM PDT 24
Finished Jun 07 08:03:29 PM PDT 24
Peak memory 191872 kb
Host smart-180d8b1a-04b7-4606-96ee-3d75111ef342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853429170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2853429170
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2455172307
Short name T219
Test name
Test status
Simulation time 450960902 ps
CPU time 0.75 seconds
Started Jun 07 08:02:28 PM PDT 24
Finished Jun 07 08:02:31 PM PDT 24
Peak memory 196408 kb
Host smart-3b4c01c3-0c16-47e1-ac06-1cba78626ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455172307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2455172307
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2371055999
Short name T213
Test name
Test status
Simulation time 48133964643 ps
CPU time 76.43 seconds
Started Jun 07 08:02:29 PM PDT 24
Finished Jun 07 08:03:48 PM PDT 24
Peak memory 191952 kb
Host smart-472c820c-645b-4539-b2db-67e2e40e29fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371055999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2371055999
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.149590075
Short name T230
Test name
Test status
Simulation time 450643542 ps
CPU time 0.86 seconds
Started Jun 07 08:02:26 PM PDT 24
Finished Jun 07 08:02:30 PM PDT 24
Peak memory 191748 kb
Host smart-22c091ab-d647-47d8-8a04-a594349c83ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149590075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.149590075
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1905890861
Short name T45
Test name
Test status
Simulation time 45374927340 ps
CPU time 34.35 seconds
Started Jun 07 08:02:28 PM PDT 24
Finished Jun 07 08:03:05 PM PDT 24
Peak memory 191844 kb
Host smart-c1b7355e-0c5e-4bbe-bfbb-9e7008ead89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905890861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1905890861
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.451831227
Short name T208
Test name
Test status
Simulation time 358110366 ps
CPU time 0.78 seconds
Started Jun 07 08:02:26 PM PDT 24
Finished Jun 07 08:02:29 PM PDT 24
Peak memory 191840 kb
Host smart-bfaf9e2d-cf3f-4ce5-8bc2-8e8a6a2cb6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451831227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.451831227
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2478274166
Short name T44
Test name
Test status
Simulation time 29563963399 ps
CPU time 45.76 seconds
Started Jun 07 08:02:36 PM PDT 24
Finished Jun 07 08:03:22 PM PDT 24
Peak memory 191920 kb
Host smart-134e7dee-a17e-41a1-8254-937b2c9568ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478274166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2478274166
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3409985067
Short name T206
Test name
Test status
Simulation time 344347312 ps
CPU time 0.82 seconds
Started Jun 07 08:02:37 PM PDT 24
Finished Jun 07 08:02:39 PM PDT 24
Peak memory 191760 kb
Host smart-06f16202-0d76-4034-b910-af4a55a3b4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409985067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3409985067
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2694112435
Short name T79
Test name
Test status
Simulation time 5447343563 ps
CPU time 2.66 seconds
Started Jun 07 08:01:38 PM PDT 24
Finished Jun 07 08:01:42 PM PDT 24
Peak memory 191876 kb
Host smart-5b540779-63fb-43ec-8f44-3d079c22b511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694112435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2694112435
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1928630585
Short name T249
Test name
Test status
Simulation time 596546057 ps
CPU time 0.75 seconds
Started Jun 07 08:01:38 PM PDT 24
Finished Jun 07 08:01:41 PM PDT 24
Peak memory 191808 kb
Host smart-7da3083d-10ad-4121-8c51-64db77de5077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928630585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1928630585
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1251167701
Short name T250
Test name
Test status
Simulation time 32974653205 ps
CPU time 28.27 seconds
Started Jun 07 08:01:45 PM PDT 24
Finished Jun 07 08:02:14 PM PDT 24
Peak memory 191888 kb
Host smart-4cf11670-7fa7-4d17-b655-49aa5096db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251167701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1251167701
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1029812400
Short name T251
Test name
Test status
Simulation time 459088104 ps
CPU time 0.82 seconds
Started Jun 07 08:01:38 PM PDT 24
Finished Jun 07 08:01:42 PM PDT 24
Peak memory 196488 kb
Host smart-d4e7ed6d-f4a8-4c5a-a6b2-b687d0a6542a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029812400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1029812400
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1882921602
Short name T246
Test name
Test status
Simulation time 23854419584 ps
CPU time 34.17 seconds
Started Jun 07 08:01:43 PM PDT 24
Finished Jun 07 08:02:18 PM PDT 24
Peak memory 191864 kb
Host smart-7850184a-09d9-43c0-a3ac-9bd59585994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882921602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1882921602
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3869630785
Short name T47
Test name
Test status
Simulation time 447167579 ps
CPU time 0.94 seconds
Started Jun 07 08:01:45 PM PDT 24
Finished Jun 07 08:01:48 PM PDT 24
Peak memory 191804 kb
Host smart-068b25f2-a926-4c7d-bca9-bc35e1ef1169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869630785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3869630785
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3211210328
Short name T6
Test name
Test status
Simulation time 12447552288 ps
CPU time 19.56 seconds
Started Jun 07 08:01:47 PM PDT 24
Finished Jun 07 08:02:09 PM PDT 24
Peak memory 191900 kb
Host smart-edb05ceb-7c54-4172-a722-b7f350bb5508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211210328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3211210328
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2899853246
Short name T82
Test name
Test status
Simulation time 339801292 ps
CPU time 1.11 seconds
Started Jun 07 08:01:46 PM PDT 24
Finished Jun 07 08:01:49 PM PDT 24
Peak memory 191784 kb
Host smart-9ddf9972-9410-4eff-8565-991955eb482a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899853246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2899853246
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1773441525
Short name T215
Test name
Test status
Simulation time 38286784864 ps
CPU time 14.89 seconds
Started Jun 07 08:01:49 PM PDT 24
Finished Jun 07 08:02:06 PM PDT 24
Peak memory 191936 kb
Host smart-8ff3ac51-66a0-466d-8e2f-f3e6b67818f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773441525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1773441525
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3305986985
Short name T220
Test name
Test status
Simulation time 581705662 ps
CPU time 1.49 seconds
Started Jun 07 08:01:47 PM PDT 24
Finished Jun 07 08:01:51 PM PDT 24
Peak memory 191784 kb
Host smart-708f67c1-f8b8-4402-bcd4-6b892081005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305986985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3305986985
Directory /workspace/9.aon_timer_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%