Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	26910	1		T1	182		T2	770		T3	12
bark[1]	420	1		T24	7		T105	42		T119	21
bark[2]	252	1		T45	14		T174	21		T82	21
bark[3]	215	1		T6	39		T30	21		T39	42
bark[4]	1117	1		T11	134		T101	67		T90	302
bark[5]	512	1		T5	160		T186	14		T84	21
bark[6]	747	1		T101	21		T118	42		T116	21
bark[7]	364	1		T1	21		T147	36		T124	42
bark[8]	495	1		T1	58		T29	44		T21	21
bark[9]	423	1		T1	42		T30	49		T21	21
bark[10]	581	1		T4	14		T17	30		T39	21
bark[11]	797	1		T11	105		T90	47		T93	208
bark[12]	558	1		T30	21		T39	49		T90	39
bark[13]	761	1		T154	109		T90	119		T92	222
bark[14]	159	1		T21	21		T118	14		T116	26
bark[15]	321	1		T2	21		T30	21		T154	30
bark[16]	380	1		T9	21		T11	21		T147	44
bark[17]	454	1		T9	7		T181	14		T147	21
bark[18]	787	1		T2	21		T6	30		T185	14
bark[19]	466	1		T148	63		T99	21		T91	21
bark[20]	296	1		T30	33		T118	21		T83	44
bark[21]	165	1		T9	7		T26	14		T95	21
bark[22]	984	1		T11	369		T21	21		T144	14
bark[23]	370	1		T5	56		T148	21		T40	104
bark[24]	494	1		T6	21		T7	40		T39	26
bark[25]	158	1		T44	14		T171	14		T91	21
bark[26]	1789	1		T6	5		T29	280		T39	289
bark[27]	190	1		T91	47		T175	14		T93	26
bark[28]	671	1		T179	14		T148	21		T40	44
bark[29]	179	1		T1	33		T28	14		T40	39
bark[30]	196	1		T17	21		T147	21		T27	14
bark[31]	472	1		T1	21		T6	231		T11	30
bark_0	4377	1		T1	7		T2	45		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	26670	1		T1	182		T2	765		T3	11
bite[1]	509	1		T45	13		T21	21		T91	25
bite[2]	1150	1		T6	230		T148	21		T99	21
bite[3]	1117	1		T29	279		T39	69		T41	46
bite[4]	528	1		T26	13		T40	103		T92	229
bite[5]	331	1		T4	13		T29	4		T179	13
bite[6]	76	1		T108	13		T152	42		T85	21
bite[7]	478	1		T11	6		T30	42		T44	13
bite[8]	76	1		T21	21		T164	13		T121	21
bite[9]	932	1		T24	6		T103	13		T124	13
bite[10]	573	1		T171	13		T90	21		T105	21
bite[11]	566	1		T5	55		T11	104		T147	44
bite[12]	120	1		T1	21		T2	21		T9	6
bite[13]	186	1		T6	38		T91	21		T149	64
bite[14]	236	1		T11	30		T17	30		T190	13
bite[15]	110	1		T28	13		T91	21		T138	13
bite[16]	458	1		T82	151		T142	58		T149	13
bite[17]	664	1		T30	21		T90	301		T105	21
bite[18]	322	1		T123	40		T116	21		T130	21
bite[19]	868	1		T39	309		T91	57		T93	39
bite[20]	461	1		T1	58		T6	21		T30	32
bite[21]	209	1		T81	42		T82	21		T106	21
bite[22]	169	1		T148	21		T91	21		T117	21
bite[23]	406	1		T11	21		T101	21		T118	30
bite[24]	876	1		T39	21		T154	30		T147	21
bite[25]	847	1		T1	21		T7	40		T29	43
bite[26]	280	1		T6	4		T11	138		T47	4
bite[27]	509	1		T11	355		T40	43		T175	21
bite[28]	635	1		T6	30		T9	6		T39	25
bite[29]	491	1		T1	32		T17	21		T91	21
bite[30]	555	1		T1	42		T9	21		T154	109
bite[31]	818	1		T2	21		T5	159		T147	36
bite_0	4834	1		T1	8		T2	50		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	47060	1		T1	364		T2	857		T3	19

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1241	1		T1	23		T9	94		T11	90
prescale[1]	1012	1		T1	23		T21	23		T24	19
prescale[2]	950	1		T5	167		T39	29		T154	40
prescale[3]	717	1		T5	9		T6	72		T30	19
prescale[4]	490	1		T147	23		T81	61		T93	9
prescale[5]	798	1		T1	23		T2	29		T6	2
prescale[6]	543	1		T9	19		T29	20		T40	99
prescale[7]	1646	1		T6	19		T7	64		T11	192
prescale[8]	541	1		T5	20		T11	109		T39	9
prescale[9]	733	1		T1	28		T2	45		T13	9
prescale[10]	946	1		T5	25		T6	198		T7	57
prescale[11]	833	1		T29	61		T41	19		T89	160
prescale[12]	914	1		T30	32		T21	19		T40	119
prescale[13]	620	1		T2	19		T11	163		T39	2
prescale[14]	686	1		T1	37		T2	24		T6	4
prescale[15]	666	1		T2	82		T24	2		T124	19
prescale[16]	526	1		T2	88		T30	9		T24	2
prescale[17]	807	1		T5	2		T9	2		T40	19
prescale[18]	895	1		T1	40		T3	9		T6	2
prescale[19]	264	1		T6	19		T81	30		T116	23
prescale[20]	524	1		T2	44		T39	19		T24	2
prescale[21]	405	1		T9	2		T154	42		T147	23
prescale[22]	795	1		T2	24		T7	29		T9	93
prescale[23]	682	1		T2	2		T11	135		T39	2
prescale[24]	906	1		T9	61		T39	81		T40	9
prescale[25]	264	1		T11	2		T24	2		T83	2
prescale[26]	455	1		T5	2		T12	9		T43	9
prescale[27]	1299	1		T40	45		T123	9		T124	23
prescale[28]	592	1		T2	21		T29	2		T41	12
prescale[29]	498	1		T23	9		T101	37		T91	50
prescale[30]	1060	1		T2	91		T17	19		T29	122
prescale[31]	812	1		T7	19		T39	185		T21	47
prescale_0	22940	1		T1	190		T2	388		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	34919	1		T1	303		T2	614		T3	9
auto[1]	12141	1		T1	61		T2	243		T3	10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	47060	1		T1	364		T2	857		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	27338	1		T1	182		T2	607		T3	14
wkup[1]	236	1		T39	21		T24	21		T94	21
wkup[2]	219	1		T9	21		T118	21		T95	42
wkup[3]	361	1		T1	21		T5	39		T6	21
wkup[4]	287	1		T91	15		T92	21		T153	21
wkup[5]	166	1		T11	8		T179	15		T81	8
wkup[6]	329	1		T9	21		T39	21		T168	15
wkup[7]	270	1		T1	21		T5	30		T147	21
wkup[8]	358	1		T6	35		T101	21		T123	42
wkup[9]	173	1		T2	21		T39	21		T40	21
wkup[10]	135	1		T1	21		T91	15		T82	21
wkup[11]	110	1		T2	30		T4	15		T186	15
wkup[12]	230	1		T6	8		T29	21		T101	30
wkup[13]	308	1		T147	57		T151	21		T47	8
wkup[14]	275	1		T41	42		T47	42		T118	21
wkup[15]	364	1		T2	51		T11	42		T29	51
wkup[16]	262	1		T89	42		T90	21		T91	21
wkup[17]	263	1		T11	21		T89	21		T175	21
wkup[18]	209	1		T39	47		T148	21		T40	21
wkup[19]	295	1		T11	57		T24	21		T148	21
wkup[20]	212	1		T11	31		T17	21		T154	21
wkup[21]	277	1		T17	30		T29	6		T30	21
wkup[22]	237	1		T11	21		T90	26		T91	21
wkup[23]	240	1		T1	21		T5	21		T11	30
wkup[24]	207	1		T40	39		T124	15		T47	47
wkup[25]	282	1		T181	15		T101	21		T47	21
wkup[26]	196	1		T11	26		T90	21		T81	21
wkup[27]	249	1		T2	26		T6	47		T11	21
wkup[28]	261	1		T6	21		T11	21		T92	21
wkup[29]	210	1		T39	21		T90	21		T145	15
wkup[30]	232	1		T40	21		T103	15		T47	21
wkup[31]	259	1		T11	30		T39	47		T24	21
wkup[32]	145	1		T91	31		T118	21		T92	21
wkup[33]	147	1		T11	21		T39	21		T148	21
wkup[34]	227	1		T40	42		T89	21		T91	42
wkup[35]	291	1		T2	21		T5	30		T26	15
wkup[36]	422	1		T5	21		T6	30		T9	30
wkup[37]	282	1		T1	21		T118	30		T94	21
wkup[38]	247	1		T6	30		T9	21		T39	21
wkup[39]	261	1		T2	15		T6	39		T7	21
wkup[40]	229	1		T29	26		T118	26		T83	42
wkup[41]	247	1		T1	21		T47	26		T95	89
wkup[42]	294	1		T17	26		T101	21		T89	31
wkup[43]	222	1		T1	30		T154	21		T99	21
wkup[44]	222	1		T11	42		T24	21		T144	15
wkup[45]	219	1		T5	30		T101	21		T81	21
wkup[46]	318	1		T11	21		T147	21		T124	21
wkup[47]	230	1		T101	21		T89	30		T47	21
wkup[48]	299	1		T29	30		T30	21		T101	21
wkup[49]	124	1		T2	30		T24	8		T105	21
wkup[50]	298	1		T9	29		T30	21		T27	15
wkup[51]	132	1		T6	6		T21	21		T91	21
wkup[52]	318	1		T2	21		T11	30		T21	21
wkup[53]	178	1		T91	21		T95	21		T106	21
wkup[54]	330	1		T11	42		T29	39		T40	21
wkup[55]	321	1		T154	21		T40	21		T101	21
wkup[56]	390	1		T29	15		T39	42		T24	21
wkup[57]	248	1		T9	21		T11	30		T24	21
wkup[58]	325	1		T1	21		T11	8		T30	21
wkup[59]	341	1		T5	21		T45	15		T89	21
wkup[60]	422	1		T9	8		T11	21		T29	21
wkup[61]	213	1		T11	21		T44	15		T123	21
wkup[62]	388	1		T6	21		T11	42		T124	21
wkup[63]	242	1		T147	21		T21	21		T41	8
wkup_0	3438	1		T1	5		T2	35		T3	5