Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.74 99.33 93.67 100.00 98.40 99.51 47.56


Total test records in report: 418
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T50 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3824677243 Jun 09 12:30:21 PM PDT 24 Jun 09 12:30:23 PM PDT 24 458721782 ps
T284 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1866276256 Jun 09 12:30:30 PM PDT 24 Jun 09 12:30:32 PM PDT 24 490164074 ps
T285 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.6167682 Jun 09 12:30:40 PM PDT 24 Jun 09 12:30:41 PM PDT 24 370503951 ps
T286 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4069211534 Jun 09 12:30:32 PM PDT 24 Jun 09 12:30:34 PM PDT 24 345467729 ps
T287 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3172197697 Jun 09 12:30:34 PM PDT 24 Jun 09 12:30:36 PM PDT 24 965100106 ps
T288 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3406302636 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:27 PM PDT 24 500162373 ps
T200 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3302331282 Jun 09 12:30:38 PM PDT 24 Jun 09 12:30:40 PM PDT 24 537223900 ps
T34 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.404864570 Jun 09 12:30:35 PM PDT 24 Jun 09 12:30:47 PM PDT 24 8179305265 ps
T71 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2479778708 Jun 09 12:30:34 PM PDT 24 Jun 09 12:30:35 PM PDT 24 520899671 ps
T72 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2044905734 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:32 PM PDT 24 2359442684 ps
T289 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1027390138 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:36 PM PDT 24 384765585 ps
T290 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2862098570 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:31 PM PDT 24 396270331 ps
T291 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3621027663 Jun 09 12:30:38 PM PDT 24 Jun 09 12:30:41 PM PDT 24 508021016 ps
T73 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2349312015 Jun 09 12:30:37 PM PDT 24 Jun 09 12:30:40 PM PDT 24 1589564967 ps
T35 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3887571268 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:31 PM PDT 24 8814876393 ps
T292 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3965833926 Jun 09 12:30:44 PM PDT 24 Jun 09 12:30:45 PM PDT 24 317496924 ps
T74 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3206431722 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:32 PM PDT 24 1360102200 ps
T293 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2901463565 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:34 PM PDT 24 7833209803 ps
T294 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2982709236 Jun 09 12:30:33 PM PDT 24 Jun 09 12:30:35 PM PDT 24 437081626 ps
T75 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1500966270 Jun 09 12:30:25 PM PDT 24 Jun 09 12:30:29 PM PDT 24 2373228421 ps
T76 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.733624817 Jun 09 12:30:34 PM PDT 24 Jun 09 12:30:37 PM PDT 24 2312813455 ps
T295 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3114317769 Jun 09 12:30:36 PM PDT 24 Jun 09 12:30:38 PM PDT 24 292018383 ps
T77 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.818880391 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:31 PM PDT 24 2432573983 ps
T296 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3350206317 Jun 09 12:30:43 PM PDT 24 Jun 09 12:30:44 PM PDT 24 465402599 ps
T78 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3473377373 Jun 09 12:30:35 PM PDT 24 Jun 09 12:30:37 PM PDT 24 1194709066 ps
T297 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.814905150 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:30 PM PDT 24 314012717 ps
T195 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3925704953 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:44 PM PDT 24 7860134953 ps
T51 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1861002266 Jun 09 12:30:32 PM PDT 24 Jun 09 12:30:38 PM PDT 24 9194114124 ps
T298 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.941354191 Jun 09 12:30:31 PM PDT 24 Jun 09 12:30:33 PM PDT 24 359777793 ps
T299 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4126929524 Jun 09 12:30:34 PM PDT 24 Jun 09 12:30:35 PM PDT 24 522769430 ps
T300 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4084409366 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:31 PM PDT 24 316080824 ps
T301 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2281238670 Jun 09 12:30:27 PM PDT 24 Jun 09 12:30:29 PM PDT 24 307354414 ps
T79 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.394027216 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:33 PM PDT 24 1490232861 ps
T302 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1238781282 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:33 PM PDT 24 477687714 ps
T303 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1517110160 Jun 09 12:30:38 PM PDT 24 Jun 09 12:30:40 PM PDT 24 386453426 ps
T304 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4096048568 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:28 PM PDT 24 1349014290 ps
T305 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2982088765 Jun 09 12:30:38 PM PDT 24 Jun 09 12:30:40 PM PDT 24 348936873 ps
T52 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3909515909 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:31 PM PDT 24 6170945315 ps
T306 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3751557192 Jun 09 12:30:38 PM PDT 24 Jun 09 12:30:39 PM PDT 24 440650429 ps
T307 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2940990846 Jun 09 12:30:35 PM PDT 24 Jun 09 12:30:37 PM PDT 24 342279220 ps
T308 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2649018621 Jun 09 12:30:35 PM PDT 24 Jun 09 12:30:37 PM PDT 24 455091697 ps
T80 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2279297653 Jun 09 12:30:36 PM PDT 24 Jun 09 12:30:38 PM PDT 24 2488491387 ps
T309 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1310911381 Jun 09 12:30:25 PM PDT 24 Jun 09 12:30:27 PM PDT 24 450022664 ps
T53 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1768239678 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:37 PM PDT 24 6770836006 ps
T310 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1567018624 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:30 PM PDT 24 442951792 ps
T311 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2255765877 Jun 09 12:30:21 PM PDT 24 Jun 09 12:30:24 PM PDT 24 471528929 ps
T312 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.327885836 Jun 09 12:30:30 PM PDT 24 Jun 09 12:30:34 PM PDT 24 4412579650 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1984107097 Jun 09 12:30:22 PM PDT 24 Jun 09 12:30:23 PM PDT 24 397900726 ps
T313 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2841712818 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:31 PM PDT 24 529806961 ps
T55 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3442000720 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:30 PM PDT 24 695540492 ps
T314 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3855699720 Jun 09 12:30:31 PM PDT 24 Jun 09 12:30:33 PM PDT 24 523336665 ps
T315 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.561086119 Jun 09 12:30:38 PM PDT 24 Jun 09 12:30:41 PM PDT 24 337712711 ps
T316 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3213165291 Jun 09 12:30:31 PM PDT 24 Jun 09 12:30:33 PM PDT 24 556039464 ps
T317 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.231706564 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:31 PM PDT 24 1147601841 ps
T318 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3291269450 Jun 09 12:30:42 PM PDT 24 Jun 09 12:30:43 PM PDT 24 338563854 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.479543561 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:32 PM PDT 24 937797111 ps
T319 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2370494900 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:28 PM PDT 24 465003125 ps
T320 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3792752868 Jun 09 12:30:38 PM PDT 24 Jun 09 12:30:41 PM PDT 24 444007344 ps
T321 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.4084210373 Jun 09 12:30:27 PM PDT 24 Jun 09 12:30:29 PM PDT 24 439858468 ps
T197 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1120884569 Jun 09 12:30:22 PM PDT 24 Jun 09 12:30:30 PM PDT 24 7894872461 ps
T322 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.827881357 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:36 PM PDT 24 4339434156 ps
T323 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1620683606 Jun 09 12:30:39 PM PDT 24 Jun 09 12:30:44 PM PDT 24 8743820626 ps
T324 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2513136939 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:31 PM PDT 24 374728744 ps
T57 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3771930597 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:30 PM PDT 24 319174918 ps
T325 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2099169113 Jun 09 12:30:32 PM PDT 24 Jun 09 12:30:39 PM PDT 24 328249673 ps
T326 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.621184659 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:32 PM PDT 24 410121612 ps
T327 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.39607128 Jun 09 12:30:30 PM PDT 24 Jun 09 12:30:32 PM PDT 24 296855225 ps
T58 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1211763526 Jun 09 12:30:32 PM PDT 24 Jun 09 12:30:34 PM PDT 24 390606386 ps
T328 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3220484644 Jun 09 12:30:31 PM PDT 24 Jun 09 12:30:33 PM PDT 24 346904419 ps
T329 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2445267910 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:30 PM PDT 24 386540793 ps
T330 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2801751197 Jun 09 12:30:40 PM PDT 24 Jun 09 12:30:41 PM PDT 24 575837911 ps
T331 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.4059255262 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:31 PM PDT 24 448690073 ps
T332 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3929116039 Jun 09 12:30:38 PM PDT 24 Jun 09 12:30:39 PM PDT 24 418849728 ps
T333 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2860202253 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:32 PM PDT 24 741614610 ps
T334 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1706309228 Jun 09 12:30:34 PM PDT 24 Jun 09 12:30:36 PM PDT 24 512121727 ps
T335 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2718014481 Jun 09 12:30:30 PM PDT 24 Jun 09 12:30:36 PM PDT 24 8477975393 ps
T198 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3203376759 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:33 PM PDT 24 3859875570 ps
T336 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3291700034 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:31 PM PDT 24 925252023 ps
T66 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3174547170 Jun 09 12:30:41 PM PDT 24 Jun 09 12:30:42 PM PDT 24 536271495 ps
T337 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1389509911 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:30 PM PDT 24 413641468 ps
T338 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2968048012 Jun 09 12:30:40 PM PDT 24 Jun 09 12:30:42 PM PDT 24 306697892 ps
T67 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1397611230 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:33 PM PDT 24 1963473511 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2206917857 Jun 09 12:30:23 PM PDT 24 Jun 09 12:30:25 PM PDT 24 845720976 ps
T196 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2287214850 Jun 09 12:30:34 PM PDT 24 Jun 09 12:30:42 PM PDT 24 4018797533 ps
T339 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.209783847 Jun 09 12:30:34 PM PDT 24 Jun 09 12:30:36 PM PDT 24 492354004 ps
T340 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1687285201 Jun 09 12:30:39 PM PDT 24 Jun 09 12:30:41 PM PDT 24 354419248 ps
T341 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3563993796 Jun 09 12:30:30 PM PDT 24 Jun 09 12:30:32 PM PDT 24 430199209 ps
T342 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1377202631 Jun 09 12:30:34 PM PDT 24 Jun 09 12:30:36 PM PDT 24 298981466 ps
T343 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1508010048 Jun 09 12:30:32 PM PDT 24 Jun 09 12:30:40 PM PDT 24 4312784866 ps
T344 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.640276991 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:32 PM PDT 24 2186239041 ps
T345 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2126974093 Jun 09 12:30:39 PM PDT 24 Jun 09 12:30:42 PM PDT 24 2274387518 ps
T346 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1007272025 Jun 09 12:30:24 PM PDT 24 Jun 09 12:30:26 PM PDT 24 389584818 ps
T347 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1841552512 Jun 09 12:30:32 PM PDT 24 Jun 09 12:30:34 PM PDT 24 503038882 ps
T348 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.944257011 Jun 09 12:30:40 PM PDT 24 Jun 09 12:30:41 PM PDT 24 467216319 ps
T199 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3094153041 Jun 09 12:30:40 PM PDT 24 Jun 09 12:30:44 PM PDT 24 8004042491 ps
T349 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2204579419 Jun 09 12:30:33 PM PDT 24 Jun 09 12:30:36 PM PDT 24 4307569683 ps
T69 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1558384740 Jun 09 12:30:22 PM PDT 24 Jun 09 12:30:23 PM PDT 24 388170308 ps
T350 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4124956098 Jun 09 12:30:27 PM PDT 24 Jun 09 12:30:31 PM PDT 24 4428020122 ps
T351 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3596239377 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:31 PM PDT 24 281195267 ps
T352 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.636301545 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:30 PM PDT 24 303416673 ps
T353 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1179890942 Jun 09 12:30:13 PM PDT 24 Jun 09 12:30:14 PM PDT 24 364348020 ps
T354 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4187732531 Jun 09 12:30:30 PM PDT 24 Jun 09 12:30:32 PM PDT 24 322661248 ps
T355 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.472786901 Jun 09 12:30:36 PM PDT 24 Jun 09 12:30:39 PM PDT 24 491433235 ps
T356 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3498127846 Jun 09 12:30:37 PM PDT 24 Jun 09 12:30:39 PM PDT 24 507214945 ps
T357 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2769676443 Jun 09 12:30:39 PM PDT 24 Jun 09 12:30:41 PM PDT 24 450146661 ps
T358 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.792341656 Jun 09 12:30:32 PM PDT 24 Jun 09 12:30:35 PM PDT 24 448381628 ps
T359 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1462969448 Jun 09 12:30:32 PM PDT 24 Jun 09 12:30:34 PM PDT 24 679147370 ps
T360 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.989166670 Jun 09 12:30:37 PM PDT 24 Jun 09 12:30:39 PM PDT 24 428812344 ps
T361 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4218148053 Jun 09 12:30:32 PM PDT 24 Jun 09 12:30:34 PM PDT 24 519616702 ps
T362 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2945542467 Jun 09 12:30:38 PM PDT 24 Jun 09 12:30:40 PM PDT 24 504960723 ps
T363 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2654027606 Jun 09 12:30:23 PM PDT 24 Jun 09 12:30:24 PM PDT 24 499458670 ps
T364 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1411511582 Jun 09 12:30:32 PM PDT 24 Jun 09 12:30:34 PM PDT 24 397612816 ps
T70 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3570584488 Jun 09 12:30:36 PM PDT 24 Jun 09 12:30:38 PM PDT 24 363692001 ps
T365 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1200225106 Jun 09 12:30:24 PM PDT 24 Jun 09 12:30:25 PM PDT 24 569717816 ps
T366 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1732281824 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:32 PM PDT 24 576626025 ps
T367 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3231955605 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:31 PM PDT 24 437746567 ps
T368 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4683947 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:32 PM PDT 24 372369114 ps
T68 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.385242202 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:29 PM PDT 24 469342754 ps
T369 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2473240498 Jun 09 12:30:42 PM PDT 24 Jun 09 12:30:43 PM PDT 24 507555282 ps
T370 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.164544286 Jun 09 12:30:38 PM PDT 24 Jun 09 12:30:43 PM PDT 24 2271797044 ps
T371 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4167796227 Jun 09 12:30:33 PM PDT 24 Jun 09 12:30:36 PM PDT 24 570452261 ps
T372 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.179109039 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:31 PM PDT 24 445211715 ps
T373 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2643240064 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:31 PM PDT 24 1231525373 ps
T374 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3501123725 Jun 09 12:30:27 PM PDT 24 Jun 09 12:30:30 PM PDT 24 491578051 ps
T375 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2273608707 Jun 09 12:30:27 PM PDT 24 Jun 09 12:30:43 PM PDT 24 8565973561 ps
T376 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1742759818 Jun 09 12:30:32 PM PDT 24 Jun 09 12:30:34 PM PDT 24 521908896 ps
T377 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.95631522 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:31 PM PDT 24 517651821 ps
T378 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2203565367 Jun 09 12:30:34 PM PDT 24 Jun 09 12:30:36 PM PDT 24 877376949 ps
T379 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2831839138 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:30 PM PDT 24 1218221832 ps
T380 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.968749639 Jun 09 12:30:36 PM PDT 24 Jun 09 12:30:42 PM PDT 24 4174628063 ps
T381 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3077274393 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:31 PM PDT 24 525501976 ps
T382 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.863370722 Jun 09 12:30:38 PM PDT 24 Jun 09 12:30:39 PM PDT 24 519815916 ps
T383 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3992979667 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:27 PM PDT 24 345481584 ps
T384 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.417195658 Jun 09 12:30:27 PM PDT 24 Jun 09 12:30:29 PM PDT 24 451200979 ps
T385 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3095687675 Jun 09 12:30:30 PM PDT 24 Jun 09 12:30:32 PM PDT 24 425212338 ps
T386 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3229210349 Jun 09 12:30:39 PM PDT 24 Jun 09 12:30:40 PM PDT 24 1109231831 ps
T387 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.249593723 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:30 PM PDT 24 438116497 ps
T388 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.835536806 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:30 PM PDT 24 2226832435 ps
T389 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4157310277 Jun 09 12:30:35 PM PDT 24 Jun 09 12:30:38 PM PDT 24 1194563063 ps
T390 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2970973964 Jun 09 12:30:31 PM PDT 24 Jun 09 12:30:33 PM PDT 24 536459935 ps
T391 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2591432143 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:31 PM PDT 24 319943634 ps
T392 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3992513261 Jun 09 12:30:36 PM PDT 24 Jun 09 12:30:38 PM PDT 24 372430540 ps
T393 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4026703446 Jun 09 12:30:31 PM PDT 24 Jun 09 12:30:33 PM PDT 24 502280254 ps
T394 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1149169910 Jun 09 12:30:31 PM PDT 24 Jun 09 12:30:34 PM PDT 24 4584746073 ps
T395 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2307107467 Jun 09 12:30:27 PM PDT 24 Jun 09 12:30:29 PM PDT 24 332006122 ps
T396 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1141127981 Jun 09 12:30:35 PM PDT 24 Jun 09 12:30:38 PM PDT 24 414431708 ps
T397 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.703258093 Jun 09 12:30:27 PM PDT 24 Jun 09 12:30:29 PM PDT 24 361121380 ps
T398 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1190232495 Jun 09 12:30:34 PM PDT 24 Jun 09 12:30:35 PM PDT 24 477807331 ps
T399 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3532824372 Jun 09 12:30:39 PM PDT 24 Jun 09 12:30:41 PM PDT 24 465694158 ps
T400 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3318898311 Jun 09 12:30:30 PM PDT 24 Jun 09 12:30:35 PM PDT 24 9748405735 ps
T401 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.340540485 Jun 09 12:30:30 PM PDT 24 Jun 09 12:30:32 PM PDT 24 377071960 ps
T402 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.693896391 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:28 PM PDT 24 430811548 ps
T403 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3333257799 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:28 PM PDT 24 351823282 ps
T404 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2362005805 Jun 09 12:30:30 PM PDT 24 Jun 09 12:30:39 PM PDT 24 3252302527 ps
T405 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.4034110493 Jun 09 12:30:31 PM PDT 24 Jun 09 12:30:33 PM PDT 24 610447825 ps
T406 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.787464791 Jun 09 12:30:36 PM PDT 24 Jun 09 12:30:38 PM PDT 24 480828981 ps
T407 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1149618082 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:27 PM PDT 24 322317432 ps
T408 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1525222175 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:28 PM PDT 24 549770601 ps
T409 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.647476655 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:32 PM PDT 24 636859494 ps
T410 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4152986562 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:30 PM PDT 24 453602242 ps
T411 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3520770627 Jun 09 12:30:35 PM PDT 24 Jun 09 12:30:37 PM PDT 24 343434877 ps
T412 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3339893555 Jun 09 12:30:35 PM PDT 24 Jun 09 12:30:37 PM PDT 24 396486875 ps
T413 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4074414442 Jun 09 12:30:36 PM PDT 24 Jun 09 12:30:38 PM PDT 24 345371382 ps
T414 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.322056243 Jun 09 12:30:30 PM PDT 24 Jun 09 12:30:32 PM PDT 24 275256292 ps
T415 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2362553140 Jun 09 12:30:23 PM PDT 24 Jun 09 12:30:26 PM PDT 24 1550589879 ps
T416 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.4252363176 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:31 PM PDT 24 475272353 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2799656753 Jun 09 12:30:31 PM PDT 24 Jun 09 12:30:47 PM PDT 24 11423150516 ps
T418 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3181431970 Jun 09 12:30:42 PM PDT 24 Jun 09 12:30:44 PM PDT 24 309020126 ps

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3754120039
Short name T2
Test name
Test status
Simulation time 30353381831 ps
CPU time 239.98 seconds
Started Jun 09 12:34:59 PM PDT 24
Finished Jun 09 12:39:00 PM PDT 24
Peak memory 198636 kb
Host smart-414f39c3-7121-4968-927d-8619558d6637
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754120039 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3754120039
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2464929357
Short name T14
Test name
Test status
Simulation time 4556529143 ps
CPU time 1.77 seconds
Started Jun 09 12:34:54 PM PDT 24
Finished Jun 09 12:34:56 PM PDT 24
Peak memory 215964 kb
Host smart-f98b2b5b-318d-43ea-89a2-fca2c3fd72f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464929357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2464929357
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2527715785
Short name T91
Test name
Test status
Simulation time 231461020385 ps
CPU time 490.2 seconds
Started Jun 09 12:34:53 PM PDT 24
Finished Jun 09 12:43:04 PM PDT 24
Peak memory 203408 kb
Host smart-411bc7a7-f7f5-414d-97bb-46b2bbb201ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527715785 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2527715785
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.343424232
Short name T6
Test name
Test status
Simulation time 67680434608 ps
CPU time 615.36 seconds
Started Jun 09 12:35:08 PM PDT 24
Finished Jun 09 12:45:24 PM PDT 24
Peak memory 211604 kb
Host smart-12de9149-0610-4e09-9cf7-afd9dd316906
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343424232 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.343424232
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1776646992
Short name T1
Test name
Test status
Simulation time 160089324564 ps
CPU time 117.99 seconds
Started Jun 09 12:35:33 PM PDT 24
Finished Jun 09 12:37:32 PM PDT 24
Peak memory 193008 kb
Host smart-ee4510a3-2797-4d1b-8865-1c2e9d69531a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776646992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1776646992
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.404864570
Short name T34
Test name
Test status
Simulation time 8179305265 ps
CPU time 12 seconds
Started Jun 09 12:30:35 PM PDT 24
Finished Jun 09 12:30:47 PM PDT 24
Peak memory 198060 kb
Host smart-ac10ec87-d63f-4f78-979b-63a09141a158
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404864570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.404864570
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1170159900
Short name T120
Test name
Test status
Simulation time 330191520857 ps
CPU time 592.18 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:44:58 PM PDT 24
Peak memory 205068 kb
Host smart-aa9b6475-b74e-4b7e-a20d-f4cc2e6d0de8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170159900 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1170159900
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2734115252
Short name T106
Test name
Test status
Simulation time 79356993554 ps
CPU time 332.56 seconds
Started Jun 09 12:35:02 PM PDT 24
Finished Jun 09 12:40:35 PM PDT 24
Peak memory 214264 kb
Host smart-78a6f4ae-46e2-4e12-aee8-ce45127fde24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734115252 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2734115252
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1693335034
Short name T85
Test name
Test status
Simulation time 64550679263 ps
CPU time 697.8 seconds
Started Jun 09 12:35:36 PM PDT 24
Finished Jun 09 12:47:14 PM PDT 24
Peak memory 204940 kb
Host smart-b45ec76c-ba6b-4f23-84bc-39ae47cfb288
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693335034 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1693335034
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.575751043
Short name T49
Test name
Test status
Simulation time 250824729934 ps
CPU time 639.93 seconds
Started Jun 09 12:35:07 PM PDT 24
Finished Jun 09 12:45:47 PM PDT 24
Peak memory 206060 kb
Host smart-13beb801-f22c-4823-b45d-30f63dec0daf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575751043 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.575751043
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2864752486
Short name T11
Test name
Test status
Simulation time 65718577556 ps
CPU time 383.97 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:41:21 PM PDT 24
Peak memory 201344 kb
Host smart-6ef3acd8-2d64-4beb-a146-7bab7a2d394e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864752486 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2864752486
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3839998014
Short name T121
Test name
Test status
Simulation time 131094279499 ps
CPU time 113.44 seconds
Started Jun 09 12:35:15 PM PDT 24
Finished Jun 09 12:37:09 PM PDT 24
Peak memory 193176 kb
Host smart-54a3c034-66d5-4f5c-9502-a731bfe2c1d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839998014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3839998014
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.921703408
Short name T95
Test name
Test status
Simulation time 95461760784 ps
CPU time 481.7 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:43:00 PM PDT 24
Peak memory 206812 kb
Host smart-426fa373-75d3-417c-9507-f4c03fb2e66c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921703408 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.921703408
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.198833254
Short name T90
Test name
Test status
Simulation time 45352849479 ps
CPU time 269.57 seconds
Started Jun 09 12:35:17 PM PDT 24
Finished Jun 09 12:39:47 PM PDT 24
Peak memory 214996 kb
Host smart-6d595ee5-f21b-4a12-a2dd-6478fa17e74b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198833254 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.198833254
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.758911719
Short name T116
Test name
Test status
Simulation time 56141359594 ps
CPU time 97.7 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:36:45 PM PDT 24
Peak memory 191912 kb
Host smart-3c5a13b5-d502-400b-b012-534a5ccfd74f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758911719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.758911719
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3678911572
Short name T40
Test name
Test status
Simulation time 450408548444 ps
CPU time 378.73 seconds
Started Jun 09 12:35:08 PM PDT 24
Finished Jun 09 12:41:28 PM PDT 24
Peak memory 202248 kb
Host smart-864a74f1-986d-4510-b6be-0850b3e91765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678911572 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3678911572
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.4109437526
Short name T112
Test name
Test status
Simulation time 95554837211 ps
CPU time 37.91 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:35:35 PM PDT 24
Peak memory 198280 kb
Host smart-3164d16d-04e9-48eb-9c8c-a504a2fe253f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109437526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.4109437526
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.235796581
Short name T125
Test name
Test status
Simulation time 30016848329 ps
CPU time 6.33 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:35:02 PM PDT 24
Peak memory 191936 kb
Host smart-5d511ee9-cc5f-454f-ba5c-15fffe15c776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235796581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.235796581
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1200750867
Short name T107
Test name
Test status
Simulation time 173454831040 ps
CPU time 63.52 seconds
Started Jun 09 12:35:11 PM PDT 24
Finished Jun 09 12:36:15 PM PDT 24
Peak memory 192852 kb
Host smart-601540b8-ab82-4c87-b4bf-526975170de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200750867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1200750867
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1355139270
Short name T82
Test name
Test status
Simulation time 155314439753 ps
CPU time 313.72 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:40:11 PM PDT 24
Peak memory 209660 kb
Host smart-425c42cd-07b6-46d6-a312-a996fc183e32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355139270 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1355139270
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2196782692
Short name T153
Test name
Test status
Simulation time 128112935364 ps
CPU time 708.09 seconds
Started Jun 09 12:35:28 PM PDT 24
Finished Jun 09 12:47:16 PM PDT 24
Peak memory 206900 kb
Host smart-a8f92690-ad42-4445-bd3f-31027d74f519
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196782692 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2196782692
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3510805517
Short name T123
Test name
Test status
Simulation time 77695402607 ps
CPU time 180.4 seconds
Started Jun 09 12:34:54 PM PDT 24
Finished Jun 09 12:38:00 PM PDT 24
Peak memory 199412 kb
Host smart-97e13fb5-ad8e-45a6-8d5b-8e128ca3dc46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510805517 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3510805517
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1773463948
Short name T105
Test name
Test status
Simulation time 169656155170 ps
CPU time 120.66 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:36:57 PM PDT 24
Peak memory 192988 kb
Host smart-b4569b5e-95fe-4582-8ca3-1d7e56485b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773463948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1773463948
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1411357722
Short name T39
Test name
Test status
Simulation time 41001913697 ps
CPU time 427.19 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:42:05 PM PDT 24
Peak memory 208280 kb
Host smart-dd3dbe9b-ebcb-4c92-9204-ed3b4c1b65a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411357722 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1411357722
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2856213656
Short name T111
Test name
Test status
Simulation time 59148708165 ps
CPU time 503.27 seconds
Started Jun 09 12:34:59 PM PDT 24
Finished Jun 09 12:43:23 PM PDT 24
Peak memory 201912 kb
Host smart-27c45fa6-8b44-433f-b7bd-4d1358f51bd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856213656 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2856213656
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1131360353
Short name T94
Test name
Test status
Simulation time 908159270136 ps
CPU time 434.8 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:42:12 PM PDT 24
Peak memory 214024 kb
Host smart-8e22dee7-111d-4a90-ac63-fc6e27d6f606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131360353 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1131360353
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3864863039
Short name T127
Test name
Test status
Simulation time 45507879974 ps
CPU time 151.82 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:37:38 PM PDT 24
Peak memory 198556 kb
Host smart-af2992eb-576e-4803-902c-938853c43e9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864863039 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3864863039
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3007185100
Short name T21
Test name
Test status
Simulation time 64872191591 ps
CPU time 103.27 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:36:42 PM PDT 24
Peak memory 191852 kb
Host smart-fa7034ae-99fb-4327-ba62-9d654dfdffa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007185100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3007185100
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2649047263
Short name T118
Test name
Test status
Simulation time 150669968560 ps
CPU time 29.23 seconds
Started Jun 09 12:35:08 PM PDT 24
Finished Jun 09 12:35:38 PM PDT 24
Peak memory 198228 kb
Host smart-3eaa5016-737b-45d8-a8b8-d708d1319393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649047263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2649047263
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.820826263
Short name T47
Test name
Test status
Simulation time 40273509218 ps
CPU time 257.82 seconds
Started Jun 09 12:35:07 PM PDT 24
Finished Jun 09 12:39:26 PM PDT 24
Peak memory 198568 kb
Host smart-a34868b7-403c-4818-a323-c112aadb36b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820826263 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.820826263
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.616633130
Short name T141
Test name
Test status
Simulation time 151272474422 ps
CPU time 50.64 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:35:47 PM PDT 24
Peak memory 192500 kb
Host smart-804e6d31-6c15-46ad-882f-552c381b05a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616633130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.616633130
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.211889498
Short name T101
Test name
Test status
Simulation time 169024643188 ps
CPU time 352.39 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:40:49 PM PDT 24
Peak memory 210292 kb
Host smart-c2b0825d-6bce-48e4-940e-9a6cf71b4fba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211889498 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.211889498
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3713918515
Short name T142
Test name
Test status
Simulation time 44297052047 ps
CPU time 61.38 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:36:07 PM PDT 24
Peak memory 184488 kb
Host smart-0e922e0e-4dc1-4840-8fe2-7e8f74a09925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713918515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3713918515
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3912288792
Short name T129
Test name
Test status
Simulation time 191657267355 ps
CPU time 221.47 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:38:37 PM PDT 24
Peak memory 198176 kb
Host smart-8367ba6a-ef0e-44bc-bcbd-887880daa098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912288792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3912288792
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2544013241
Short name T149
Test name
Test status
Simulation time 5984802002 ps
CPU time 32.27 seconds
Started Jun 09 12:35:14 PM PDT 24
Finished Jun 09 12:35:47 PM PDT 24
Peak memory 214612 kb
Host smart-96308d21-28b1-4770-b210-e757283d734c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544013241 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2544013241
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.499665001
Short name T88
Test name
Test status
Simulation time 65892444006 ps
CPU time 421.8 seconds
Started Jun 09 12:35:10 PM PDT 24
Finished Jun 09 12:42:13 PM PDT 24
Peak memory 206824 kb
Host smart-cd35859c-c40e-4e72-87f6-8f00a8a165ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499665001 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.499665001
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.4285238725
Short name T93
Test name
Test status
Simulation time 38425970060 ps
CPU time 143.25 seconds
Started Jun 09 12:35:00 PM PDT 24
Finished Jun 09 12:37:24 PM PDT 24
Peak memory 214260 kb
Host smart-416e1ea4-ba57-483d-817c-f3d035a2bc22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285238725 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.4285238725
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.32482324
Short name T115
Test name
Test status
Simulation time 85482644256 ps
CPU time 63.71 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:36:03 PM PDT 24
Peak memory 192892 kb
Host smart-52e2cd52-cf60-45f8-b521-7a7a67dec0f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32482324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_al
l.32482324
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.4213278487
Short name T152
Test name
Test status
Simulation time 445525304399 ps
CPU time 168.04 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:37:54 PM PDT 24
Peak memory 192536 kb
Host smart-65e24833-2b02-4e5c-9b91-69cb46ca3714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213278487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.4213278487
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1923834891
Short name T137
Test name
Test status
Simulation time 298984432281 ps
CPU time 492.31 seconds
Started Jun 09 12:35:00 PM PDT 24
Finished Jun 09 12:43:13 PM PDT 24
Peak memory 192476 kb
Host smart-7a663327-0da3-4d71-bbcb-52fa56047036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923834891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1923834891
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1660286944
Short name T132
Test name
Test status
Simulation time 87369452640 ps
CPU time 34.62 seconds
Started Jun 09 12:34:54 PM PDT 24
Finished Jun 09 12:35:29 PM PDT 24
Peak memory 191896 kb
Host smart-fbb0e6f3-f64d-4fdc-962b-09c975f3fa7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660286944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1660286944
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.906204113
Short name T30
Test name
Test status
Simulation time 361034425294 ps
CPU time 597.7 seconds
Started Jun 09 12:35:26 PM PDT 24
Finished Jun 09 12:45:24 PM PDT 24
Peak memory 198208 kb
Host smart-68139a23-2974-4055-98c4-4f5252494434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906204113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.906204113
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2059139062
Short name T113
Test name
Test status
Simulation time 229567936319 ps
CPU time 41.02 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:35:36 PM PDT 24
Peak memory 198192 kb
Host smart-0514fabb-b878-4c35-b4ed-598b0ca1d353
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059139062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2059139062
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3539404863
Short name T87
Test name
Test status
Simulation time 213539263076 ps
CPU time 402.57 seconds
Started Jun 09 12:35:24 PM PDT 24
Finished Jun 09 12:42:07 PM PDT 24
Peak memory 210732 kb
Host smart-6bc03050-a7d0-426a-b946-ffb155e7fd58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539404863 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3539404863
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2590585528
Short name T147
Test name
Test status
Simulation time 50960050792 ps
CPU time 43.98 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:35:42 PM PDT 24
Peak memory 198276 kb
Host smart-16c2a033-56c1-4d06-a2ed-702dc96994f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590585528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2590585528
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1546988275
Short name T133
Test name
Test status
Simulation time 141973928698 ps
CPU time 198.95 seconds
Started Jun 09 12:35:00 PM PDT 24
Finished Jun 09 12:38:20 PM PDT 24
Peak memory 198252 kb
Host smart-d051b3fe-3ae3-44b8-9ab3-d6807db8b07a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546988275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1546988275
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.17042664
Short name T83
Test name
Test status
Simulation time 121885002068 ps
CPU time 414.74 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:41:51 PM PDT 24
Peak memory 207044 kb
Host smart-632288c5-55cf-443f-9b58-410fd556be5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17042664 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.17042664
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2905198597
Short name T92
Test name
Test status
Simulation time 101879724404 ps
CPU time 171.86 seconds
Started Jun 09 12:35:09 PM PDT 24
Finished Jun 09 12:38:06 PM PDT 24
Peak memory 208100 kb
Host smart-6795d549-7b91-417e-8af7-c1e1ec9ed45e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905198597 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2905198597
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.378290421
Short name T148
Test name
Test status
Simulation time 100043848801 ps
CPU time 40.07 seconds
Started Jun 09 12:35:07 PM PDT 24
Finished Jun 09 12:35:48 PM PDT 24
Peak memory 198216 kb
Host smart-2e1be82b-e05b-4481-8020-9dc84a9fbce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378290421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.378290421
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.4110652721
Short name T117
Test name
Test status
Simulation time 97373627318 ps
CPU time 169.44 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:37:55 PM PDT 24
Peak memory 191896 kb
Host smart-dd13b697-f331-4c23-92ed-c632975f9348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110652721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.4110652721
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1846630046
Short name T124
Test name
Test status
Simulation time 258853229286 ps
CPU time 392.54 seconds
Started Jun 09 12:34:53 PM PDT 24
Finished Jun 09 12:41:26 PM PDT 24
Peak memory 193020 kb
Host smart-900c04ce-1a42-45c7-9faf-cc558fd9fd30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846630046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1846630046
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3622612474
Short name T104
Test name
Test status
Simulation time 269823374954 ps
CPU time 97.17 seconds
Started Jun 09 12:35:31 PM PDT 24
Finished Jun 09 12:37:08 PM PDT 24
Peak memory 192824 kb
Host smart-1e7fb313-38aa-4adc-bdd9-a45992bfe7fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622612474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3622612474
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.325224587
Short name T17
Test name
Test status
Simulation time 56725789635 ps
CPU time 14.84 seconds
Started Jun 09 12:35:22 PM PDT 24
Finished Jun 09 12:35:37 PM PDT 24
Peak memory 191872 kb
Host smart-cfd8f8ea-d5f2-4dee-ba88-ae8a0cbddd0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325224587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.325224587
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1111814810
Short name T84
Test name
Test status
Simulation time 45443841942 ps
CPU time 235.75 seconds
Started Jun 09 12:35:09 PM PDT 24
Finished Jun 09 12:39:10 PM PDT 24
Peak memory 214404 kb
Host smart-59c44532-05d9-44a3-b491-2a1ae7f6b0bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111814810 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1111814810
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2599939456
Short name T151
Test name
Test status
Simulation time 202145965459 ps
CPU time 148.28 seconds
Started Jun 09 12:35:07 PM PDT 24
Finished Jun 09 12:37:36 PM PDT 24
Peak memory 192916 kb
Host smart-9bfb0a03-2bc4-4400-8c9e-140fe654e29f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599939456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2599939456
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3442000720
Short name T55
Test name
Test status
Simulation time 695540492 ps
CPU time 0.84 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 194092 kb
Host smart-bfdaeeb2-33f6-4fc8-a24a-f8cfcf74b4ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442000720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3442000720
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1500966270
Short name T75
Test name
Test status
Simulation time 2373228421 ps
CPU time 2.87 seconds
Started Jun 09 12:30:25 PM PDT 24
Finished Jun 09 12:30:29 PM PDT 24
Peak memory 193864 kb
Host smart-148040c6-5d98-4ac5-ac17-b79050b665f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500966270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1500966270
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1404930702
Short name T130
Test name
Test status
Simulation time 49396977822 ps
CPU time 201.85 seconds
Started Jun 09 12:35:13 PM PDT 24
Finished Jun 09 12:38:35 PM PDT 24
Peak memory 206824 kb
Host smart-fbe29d24-d93f-4b51-93a3-71e7554ed680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404930702 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1404930702
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2951030755
Short name T126
Test name
Test status
Simulation time 297531165073 ps
CPU time 120.99 seconds
Started Jun 09 12:35:02 PM PDT 24
Finished Jun 09 12:37:04 PM PDT 24
Peak memory 198256 kb
Host smart-e7f88759-d41a-4c4a-9b97-1e7af2f04f6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951030755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2951030755
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.483087924
Short name T158
Test name
Test status
Simulation time 44743775985 ps
CPU time 95.29 seconds
Started Jun 09 12:35:08 PM PDT 24
Finished Jun 09 12:36:44 PM PDT 24
Peak memory 198588 kb
Host smart-8187ea8f-2502-4864-8f42-58439e3825bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483087924 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.483087924
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2195294320
Short name T61
Test name
Test status
Simulation time 23282523739 ps
CPU time 252.7 seconds
Started Jun 09 12:35:10 PM PDT 24
Finished Jun 09 12:39:27 PM PDT 24
Peak memory 206756 kb
Host smart-c4eaf013-e701-4371-9652-2d25b64c2045
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195294320 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2195294320
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3825749231
Short name T110
Test name
Test status
Simulation time 517420551 ps
CPU time 0.77 seconds
Started Jun 09 12:35:03 PM PDT 24
Finished Jun 09 12:35:04 PM PDT 24
Peak memory 196548 kb
Host smart-67b8c7e2-9a97-4031-af18-78e9f8416266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825749231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3825749231
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3232616844
Short name T134
Test name
Test status
Simulation time 579961569 ps
CPU time 1.03 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:35:08 PM PDT 24
Peak memory 196556 kb
Host smart-28e4a398-ddb5-48a8-9543-37b60aa59823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232616844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3232616844
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.523589199
Short name T63
Test name
Test status
Simulation time 299486510414 ps
CPU time 500.23 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:43:17 PM PDT 24
Peak memory 198232 kb
Host smart-7617f844-8b9b-413a-a56f-d319677149f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523589199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.523589199
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3926623562
Short name T89
Test name
Test status
Simulation time 106888869692 ps
CPU time 425.47 seconds
Started Jun 09 12:35:01 PM PDT 24
Finished Jun 09 12:42:08 PM PDT 24
Peak memory 206796 kb
Host smart-4c0444f9-02cd-4d12-9572-fc3fe9586b4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926623562 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3926623562
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2918853692
Short name T143
Test name
Test status
Simulation time 67069683792 ps
CPU time 120.3 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:37:00 PM PDT 24
Peak memory 198604 kb
Host smart-3c136e6b-ec50-42f4-b5b2-dcbbdd098854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918853692 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2918853692
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.875334333
Short name T41
Test name
Test status
Simulation time 125983554351 ps
CPU time 389.51 seconds
Started Jun 09 12:35:38 PM PDT 24
Finished Jun 09 12:42:07 PM PDT 24
Peak memory 214052 kb
Host smart-d98a1218-b8b5-4c85-98a8-d78fb4265ccd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875334333 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.875334333
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3500580390
Short name T150
Test name
Test status
Simulation time 87575108842 ps
CPU time 28.67 seconds
Started Jun 09 12:35:00 PM PDT 24
Finished Jun 09 12:35:29 PM PDT 24
Peak memory 192552 kb
Host smart-30704da6-09e7-4134-bd09-caabba900af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500580390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3500580390
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2035787594
Short name T48
Test name
Test status
Simulation time 522135849 ps
CPU time 1.37 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:35:01 PM PDT 24
Peak memory 196648 kb
Host smart-2f0622bf-464d-4063-a18e-dd90378ba3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035787594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2035787594
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.635527014
Short name T136
Test name
Test status
Simulation time 170702858598 ps
CPU time 256.28 seconds
Started Jun 09 12:35:38 PM PDT 24
Finished Jun 09 12:39:54 PM PDT 24
Peak memory 192932 kb
Host smart-a7f10c6b-127d-4ad4-8244-d7d4ddac8aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635527014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.635527014
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2698289658
Short name T144
Test name
Test status
Simulation time 465845596 ps
CPU time 0.93 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:06 PM PDT 24
Peak memory 196604 kb
Host smart-4fa1ad08-6f6b-4cba-91bc-eb63ebc47714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698289658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2698289658
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2629911662
Short name T163
Test name
Test status
Simulation time 519452576733 ps
CPU time 370.29 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:41:16 PM PDT 24
Peak memory 193000 kb
Host smart-f3164f55-5262-43da-af9c-0774b7f56db9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629911662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2629911662
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.558987125
Short name T81
Test name
Test status
Simulation time 649933804932 ps
CPU time 555.82 seconds
Started Jun 09 12:35:02 PM PDT 24
Finished Jun 09 12:44:18 PM PDT 24
Peak memory 212440 kb
Host smart-4a4acde6-4368-47dc-90d5-a849af41ce5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558987125 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.558987125
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2383167367
Short name T108
Test name
Test status
Simulation time 505742329 ps
CPU time 0.77 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:35:08 PM PDT 24
Peak memory 196644 kb
Host smart-9a662dcf-f10b-4148-9a7b-9f8e7d463e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383167367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2383167367
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2810116221
Short name T27
Test name
Test status
Simulation time 566386167 ps
CPU time 1.5 seconds
Started Jun 09 12:35:08 PM PDT 24
Finished Jun 09 12:35:10 PM PDT 24
Peak memory 196508 kb
Host smart-519038c1-ab3e-483b-8d7a-f5d5a8c5c6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810116221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2810116221
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1292525247
Short name T28
Test name
Test status
Simulation time 500792503 ps
CPU time 1.22 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:34:59 PM PDT 24
Peak memory 196576 kb
Host smart-0f837fa3-8bb4-4ae8-8a63-3b43221c2055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292525247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1292525247
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.274895049
Short name T138
Test name
Test status
Simulation time 360935245 ps
CPU time 0.78 seconds
Started Jun 09 12:34:54 PM PDT 24
Finished Jun 09 12:34:56 PM PDT 24
Peak memory 196676 kb
Host smart-a9a5685b-cc93-4299-b946-a3f0a5e9beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274895049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.274895049
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.314805607
Short name T162
Test name
Test status
Simulation time 174298882864 ps
CPU time 237.11 seconds
Started Jun 09 12:35:00 PM PDT 24
Finished Jun 09 12:38:58 PM PDT 24
Peak memory 192532 kb
Host smart-6eab789a-8e3a-41f4-a268-26dd1fd0c4c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314805607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.314805607
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3142524573
Short name T29
Test name
Test status
Simulation time 17138527317 ps
CPU time 87.63 seconds
Started Jun 09 12:35:26 PM PDT 24
Finished Jun 09 12:36:54 PM PDT 24
Peak memory 214336 kb
Host smart-bfe86cb0-5552-4b56-846f-f10d16303807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142524573 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3142524573
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3742421740
Short name T122
Test name
Test status
Simulation time 581686886 ps
CPU time 0.83 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:34:59 PM PDT 24
Peak memory 196508 kb
Host smart-c9fa2404-c527-467a-9c40-e8967e71b69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742421740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3742421740
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.830919510
Short name T128
Test name
Test status
Simulation time 19660879122 ps
CPU time 28.72 seconds
Started Jun 09 12:35:19 PM PDT 24
Finished Jun 09 12:35:48 PM PDT 24
Peak memory 198260 kb
Host smart-318cc933-9751-48c2-a14f-1441973ee53d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830919510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.830919510
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.4082872437
Short name T103
Test name
Test status
Simulation time 530321928 ps
CPU time 0.84 seconds
Started Jun 09 12:35:08 PM PDT 24
Finished Jun 09 12:35:09 PM PDT 24
Peak memory 196348 kb
Host smart-4ccdcd45-ea1e-417a-bb12-0db246930d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082872437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.4082872437
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1105588666
Short name T146
Test name
Test status
Simulation time 69209473903 ps
CPU time 67.87 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:36:06 PM PDT 24
Peak memory 198172 kb
Host smart-4f61f871-09b2-48af-b132-51de8b905dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105588666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1105588666
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.157745340
Short name T135
Test name
Test status
Simulation time 158222199674 ps
CPU time 203.84 seconds
Started Jun 09 12:35:41 PM PDT 24
Finished Jun 09 12:39:05 PM PDT 24
Peak memory 191916 kb
Host smart-7bd41533-5e63-4ba2-adc0-8e83de6e0c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157745340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.157745340
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1810686041
Short name T139
Test name
Test status
Simulation time 435037809 ps
CPU time 1.03 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:35:07 PM PDT 24
Peak memory 196656 kb
Host smart-8f0f4e32-56da-4d47-980c-8582c7f7a9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810686041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1810686041
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2630444723
Short name T86
Test name
Test status
Simulation time 120664339336 ps
CPU time 765.78 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:47:50 PM PDT 24
Peak memory 215008 kb
Host smart-843a9d69-6fc2-4f56-abff-6ec3f8d285de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630444723 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2630444723
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2101833229
Short name T99
Test name
Test status
Simulation time 299386303937 ps
CPU time 217.29 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:38:33 PM PDT 24
Peak memory 191836 kb
Host smart-9f105640-0490-4d0f-8832-f4dda4acd891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101833229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2101833229
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.4018212924
Short name T114
Test name
Test status
Simulation time 499107762 ps
CPU time 1.35 seconds
Started Jun 09 12:35:13 PM PDT 24
Finished Jun 09 12:35:15 PM PDT 24
Peak memory 196644 kb
Host smart-0488eb9a-6cac-47ba-9419-f2c721b63f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018212924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4018212924
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2249342321
Short name T96
Test name
Test status
Simulation time 41450550559 ps
CPU time 154.82 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:37:34 PM PDT 24
Peak memory 198612 kb
Host smart-41a7d40a-484b-4214-b05e-9cb293803573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249342321 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2249342321
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2990462233
Short name T154
Test name
Test status
Simulation time 88718526516 ps
CPU time 125.56 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:37:05 PM PDT 24
Peak memory 198284 kb
Host smart-d37fdc44-a73d-472f-8167-25581be8050d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990462233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2990462233
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.9925510
Short name T155
Test name
Test status
Simulation time 153374593236 ps
CPU time 108.56 seconds
Started Jun 09 12:35:03 PM PDT 24
Finished Jun 09 12:36:52 PM PDT 24
Peak memory 191872 kb
Host smart-294f5d92-27b3-4777-80e3-8af07607107b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9925510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.9925510
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3363875004
Short name T9
Test name
Test status
Simulation time 17812126278 ps
CPU time 99.17 seconds
Started Jun 09 12:35:31 PM PDT 24
Finished Jun 09 12:37:10 PM PDT 24
Peak memory 207028 kb
Host smart-cabdd73e-3bcd-45d3-9ccb-ee481f9ced1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363875004 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3363875004
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.62805587
Short name T109
Test name
Test status
Simulation time 528770809 ps
CPU time 0.77 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:35:07 PM PDT 24
Peak memory 196628 kb
Host smart-f830cbce-6dca-4151-9b7a-68474453bf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62805587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.62805587
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.678043699
Short name T140
Test name
Test status
Simulation time 580536125610 ps
CPU time 410.95 seconds
Started Jun 09 12:35:08 PM PDT 24
Finished Jun 09 12:41:59 PM PDT 24
Peak memory 191688 kb
Host smart-95e568f7-07dc-4429-8ccc-1bf813fdf0cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678043699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.678043699
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2395848582
Short name T145
Test name
Test status
Simulation time 375292757 ps
CPU time 1.08 seconds
Started Jun 09 12:34:54 PM PDT 24
Finished Jun 09 12:34:56 PM PDT 24
Peak memory 196632 kb
Host smart-b0f970ef-505c-44a9-8bb8-abcb3b14ea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395848582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2395848582
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1519807089
Short name T119
Test name
Test status
Simulation time 401237222711 ps
CPU time 268.77 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:39:35 PM PDT 24
Peak memory 192416 kb
Host smart-56873618-426e-49e6-883a-1e37fc70fe00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519807089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1519807089
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.4116485140
Short name T169
Test name
Test status
Simulation time 177760095557 ps
CPU time 141.68 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:37:20 PM PDT 24
Peak memory 184152 kb
Host smart-533fe8a0-e51f-497f-b7dc-96b4e5202031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116485140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.4116485140
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3910542808
Short name T5
Test name
Test status
Simulation time 76017985465 ps
CPU time 156.83 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:37:42 PM PDT 24
Peak memory 214024 kb
Host smart-b4bf3e8b-efdb-4673-9567-fca8d331ad07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910542808 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3910542808
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.612034637
Short name T176
Test name
Test status
Simulation time 489745262 ps
CPU time 0.8 seconds
Started Jun 09 12:34:54 PM PDT 24
Finished Jun 09 12:34:56 PM PDT 24
Peak memory 196516 kb
Host smart-92ef050d-b81f-4b4c-95b7-629c69deba7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612034637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.612034637
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.688994115
Short name T24
Test name
Test status
Simulation time 208483781113 ps
CPU time 579.41 seconds
Started Jun 09 12:35:03 PM PDT 24
Finished Jun 09 12:44:43 PM PDT 24
Peak memory 213612 kb
Host smart-0758cff4-e61c-4e71-9eaf-67b252d0a241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688994115 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.688994115
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.351253733
Short name T156
Test name
Test status
Simulation time 407308297198 ps
CPU time 555.32 seconds
Started Jun 09 12:34:54 PM PDT 24
Finished Jun 09 12:44:11 PM PDT 24
Peak memory 191876 kb
Host smart-7132c137-b811-4881-ba44-125046584820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351253733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.351253733
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3780784777
Short name T179
Test name
Test status
Simulation time 461046507 ps
CPU time 1.13 seconds
Started Jun 09 12:34:53 PM PDT 24
Finished Jun 09 12:34:55 PM PDT 24
Peak memory 196552 kb
Host smart-40e87a4a-a3e3-4aeb-9265-5f9c8e2a7abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780784777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3780784777
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1066180959
Short name T181
Test name
Test status
Simulation time 503833334 ps
CPU time 0.89 seconds
Started Jun 09 12:35:09 PM PDT 24
Finished Jun 09 12:35:15 PM PDT 24
Peak memory 196512 kb
Host smart-5f32f7d7-54b3-4dcb-9373-0cb401f908ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066180959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1066180959
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3321030937
Short name T171
Test name
Test status
Simulation time 515757530 ps
CPU time 0.77 seconds
Started Jun 09 12:35:33 PM PDT 24
Finished Jun 09 12:35:34 PM PDT 24
Peak memory 196516 kb
Host smart-aca9a0b4-eaee-4c12-ad16-124f7ad2e6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321030937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3321030937
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1920277646
Short name T131
Test name
Test status
Simulation time 91548281100 ps
CPU time 31.32 seconds
Started Jun 09 12:35:09 PM PDT 24
Finished Jun 09 12:35:41 PM PDT 24
Peak memory 197996 kb
Host smart-dc46e9c0-9ee0-4c1e-b880-e0d89abca740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920277646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1920277646
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.4291964521
Short name T189
Test name
Test status
Simulation time 542448413 ps
CPU time 0.75 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:06 PM PDT 24
Peak memory 196728 kb
Host smart-20c3dd35-0537-4b71-a952-ae1937d9dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291964521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.4291964521
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.7318380
Short name T188
Test name
Test status
Simulation time 441998309 ps
CPU time 0.75 seconds
Started Jun 09 12:35:11 PM PDT 24
Finished Jun 09 12:35:12 PM PDT 24
Peak memory 196416 kb
Host smart-7c584832-bc9c-4cc1-87c4-2a727a4aa63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7318380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.7318380
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1761251970
Short name T45
Test name
Test status
Simulation time 491033861 ps
CPU time 1.43 seconds
Started Jun 09 12:35:34 PM PDT 24
Finished Jun 09 12:35:36 PM PDT 24
Peak memory 196564 kb
Host smart-314e0157-66f7-4f3a-94dd-21e8351f69ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761251970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1761251970
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.4225040504
Short name T175
Test name
Test status
Simulation time 221314783898 ps
CPU time 174.48 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:37:53 PM PDT 24
Peak memory 192920 kb
Host smart-9f469ecd-bf0d-4107-991a-01317f4808cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225040504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.4225040504
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.21496378
Short name T185
Test name
Test status
Simulation time 521523406 ps
CPU time 0.81 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:35:07 PM PDT 24
Peak memory 196520 kb
Host smart-8bbf2ab7-c82a-4443-a149-e6c76442b7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21496378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.21496378
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.4243897647
Short name T182
Test name
Test status
Simulation time 472051671 ps
CPU time 0.68 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:34:58 PM PDT 24
Peak memory 196488 kb
Host smart-794395bf-a009-4a15-8de3-402431ca74c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243897647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.4243897647
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1788290754
Short name T167
Test name
Test status
Simulation time 421458353 ps
CPU time 0.73 seconds
Started Jun 09 12:35:10 PM PDT 24
Finished Jun 09 12:35:11 PM PDT 24
Peak memory 196460 kb
Host smart-bf419949-65ba-47cb-afb4-317a76673d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788290754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1788290754
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.703259459
Short name T173
Test name
Test status
Simulation time 552216998 ps
CPU time 1.38 seconds
Started Jun 09 12:35:03 PM PDT 24
Finished Jun 09 12:35:10 PM PDT 24
Peak memory 196528 kb
Host smart-3e214496-b9ba-496b-b3b4-448828d6c7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703259459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.703259459
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.4284644114
Short name T194
Test name
Test status
Simulation time 465159839 ps
CPU time 0.67 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:06 PM PDT 24
Peak memory 196544 kb
Host smart-1c3590d4-1977-4936-9316-bcd8fecc5dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284644114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4284644114
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3332136858
Short name T174
Test name
Test status
Simulation time 122916892827 ps
CPU time 40.36 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:35:47 PM PDT 24
Peak memory 191828 kb
Host smart-cebe77ff-5d31-4e1e-93c7-7f29c3c30f84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332136858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3332136858
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3125922721
Short name T177
Test name
Test status
Simulation time 456405699 ps
CPU time 0.9 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:06 PM PDT 24
Peak memory 196532 kb
Host smart-a3333298-ff5e-42bb-ba23-e064ad30f605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125922721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3125922721
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.696752308
Short name T7
Test name
Test status
Simulation time 144446776387 ps
CPU time 238.11 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:39:03 PM PDT 24
Peak memory 198228 kb
Host smart-21be789c-1a48-411c-999e-fe277d8ae383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696752308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.696752308
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1600888204
Short name T180
Test name
Test status
Simulation time 459464407 ps
CPU time 0.75 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:06 PM PDT 24
Peak memory 196628 kb
Host smart-db1fc8d4-97ef-4b4a-81f6-d5a2936a1f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600888204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1600888204
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3497647565
Short name T192
Test name
Test status
Simulation time 367809138 ps
CPU time 0.71 seconds
Started Jun 09 12:35:16 PM PDT 24
Finished Jun 09 12:35:17 PM PDT 24
Peak memory 196512 kb
Host smart-1de4aca9-d581-4359-b986-2b968b3ac4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497647565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3497647565
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.442647324
Short name T193
Test name
Test status
Simulation time 384787475 ps
CPU time 1.06 seconds
Started Jun 09 12:35:00 PM PDT 24
Finished Jun 09 12:35:02 PM PDT 24
Peak memory 196540 kb
Host smart-fab28a0d-50ce-444d-8c7c-adc3d71d3803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442647324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.442647324
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.990480164
Short name T160
Test name
Test status
Simulation time 576924013 ps
CPU time 0.69 seconds
Started Jun 09 12:35:09 PM PDT 24
Finished Jun 09 12:35:10 PM PDT 24
Peak memory 196480 kb
Host smart-471edf78-05c1-47a4-8cb4-40ab75005fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990480164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.990480164
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3876326290
Short name T60
Test name
Test status
Simulation time 56709808216 ps
CPU time 70 seconds
Started Jun 09 12:35:08 PM PDT 24
Finished Jun 09 12:36:18 PM PDT 24
Peak memory 198580 kb
Host smart-94117d81-ef85-4059-854d-6447ee9390c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876326290 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3876326290
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3021902600
Short name T184
Test name
Test status
Simulation time 443617099 ps
CPU time 1.24 seconds
Started Jun 09 12:35:02 PM PDT 24
Finished Jun 09 12:35:04 PM PDT 24
Peak memory 196580 kb
Host smart-0d6d87b3-fa30-4ba1-a7f3-cf30f4b99306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021902600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3021902600
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1120884569
Short name T197
Test name
Test status
Simulation time 7894872461 ps
CPU time 6.8 seconds
Started Jun 09 12:30:22 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 197968 kb
Host smart-de55396b-4ae8-46cb-9dd6-42622cc7f82b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120884569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1120884569
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2287214850
Short name T196
Test name
Test status
Simulation time 4018797533 ps
CPU time 7.17 seconds
Started Jun 09 12:30:34 PM PDT 24
Finished Jun 09 12:30:42 PM PDT 24
Peak memory 196700 kb
Host smart-a8adec88-d39f-41b5-bb46-8dc149311899
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287214850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2287214850
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.406569417
Short name T26
Test name
Test status
Simulation time 357427798 ps
CPU time 0.79 seconds
Started Jun 09 12:35:14 PM PDT 24
Finished Jun 09 12:35:15 PM PDT 24
Peak memory 196532 kb
Host smart-92a7c831-be47-4f63-9437-f20fdc2b96e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406569417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.406569417
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1163222500
Short name T157
Test name
Test status
Simulation time 371332142 ps
CPU time 0.71 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:35:07 PM PDT 24
Peak memory 196488 kb
Host smart-f798b8f9-041c-486e-9ee4-d39ceaea099b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163222500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1163222500
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2163676821
Short name T178
Test name
Test status
Simulation time 589505344 ps
CPU time 0.76 seconds
Started Jun 09 12:35:01 PM PDT 24
Finished Jun 09 12:35:03 PM PDT 24
Peak memory 196600 kb
Host smart-a42821cf-df5c-4e7e-9f42-adf8def51518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163676821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2163676821
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.13592733
Short name T159
Test name
Test status
Simulation time 493546259 ps
CPU time 0.94 seconds
Started Jun 09 12:34:59 PM PDT 24
Finished Jun 09 12:35:01 PM PDT 24
Peak memory 196584 kb
Host smart-fa2395c8-2e24-4f00-a7a5-4910c1824858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13592733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.13592733
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1392444626
Short name T168
Test name
Test status
Simulation time 371148081 ps
CPU time 0.73 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:35:00 PM PDT 24
Peak memory 196588 kb
Host smart-b6700a70-a52d-4301-9313-27f88b0e9297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392444626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1392444626
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1949838919
Short name T190
Test name
Test status
Simulation time 613932681 ps
CPU time 0.69 seconds
Started Jun 09 12:35:18 PM PDT 24
Finished Jun 09 12:35:24 PM PDT 24
Peak memory 196512 kb
Host smart-2652a4c6-cf07-4370-9a0a-ac16e21fbb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949838919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1949838919
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3422307008
Short name T186
Test name
Test status
Simulation time 531058641 ps
CPU time 1.43 seconds
Started Jun 09 12:35:00 PM PDT 24
Finished Jun 09 12:35:02 PM PDT 24
Peak memory 196428 kb
Host smart-aa37074a-7af8-4508-9b31-05bc8161fc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422307008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3422307008
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1747023142
Short name T187
Test name
Test status
Simulation time 570802584 ps
CPU time 0.86 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:34:59 PM PDT 24
Peak memory 196564 kb
Host smart-6ee129d2-2ba2-4793-b811-1658a3de7479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747023142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1747023142
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3608314535
Short name T4
Test name
Test status
Simulation time 397252651 ps
CPU time 0.91 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:34:58 PM PDT 24
Peak memory 196496 kb
Host smart-365a6bef-cac6-4a23-bf9d-8d03b5aa6e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608314535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3608314535
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2103353089
Short name T166
Test name
Test status
Simulation time 375621740 ps
CPU time 0.86 seconds
Started Jun 09 12:35:01 PM PDT 24
Finished Jun 09 12:35:03 PM PDT 24
Peak memory 196488 kb
Host smart-f2dea900-1417-447a-9a62-efa3f5a4a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103353089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2103353089
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3240233030
Short name T183
Test name
Test status
Simulation time 550168700 ps
CPU time 1.36 seconds
Started Jun 09 12:35:22 PM PDT 24
Finished Jun 09 12:35:24 PM PDT 24
Peak memory 196532 kb
Host smart-937acf78-d7ef-4ed5-935c-18e35b90e361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240233030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3240233030
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2176574868
Short name T44
Test name
Test status
Simulation time 365923542 ps
CPU time 0.82 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:05 PM PDT 24
Peak memory 196536 kb
Host smart-d52f305c-f3f6-408f-83f3-958be08aa5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176574868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2176574868
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.295201709
Short name T164
Test name
Test status
Simulation time 623645662 ps
CPU time 0.86 seconds
Started Jun 09 12:34:59 PM PDT 24
Finished Jun 09 12:35:05 PM PDT 24
Peak memory 196532 kb
Host smart-5ddd18fc-3261-4e89-92b2-c2b563f0e867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295201709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.295201709
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2428975114
Short name T165
Test name
Test status
Simulation time 651869738 ps
CPU time 0.7 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:34:59 PM PDT 24
Peak memory 196612 kb
Host smart-6169884a-7098-4d05-9262-ead0389739ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428975114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2428975114
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3909515909
Short name T52
Test name
Test status
Simulation time 6170945315 ps
CPU time 2.77 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 192064 kb
Host smart-0998dc4b-a4f4-4ac0-8495-56c9f404e787
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909515909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3909515909
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2206917857
Short name T59
Test name
Test status
Simulation time 845720976 ps
CPU time 1.39 seconds
Started Jun 09 12:30:23 PM PDT 24
Finished Jun 09 12:30:25 PM PDT 24
Peak memory 192844 kb
Host smart-e534ea24-d0e1-42a9-ba81-1c98d48ccd1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206917857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2206917857
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1210315490
Short name T36
Test name
Test status
Simulation time 534227438 ps
CPU time 1.18 seconds
Started Jun 09 12:30:24 PM PDT 24
Finished Jun 09 12:30:25 PM PDT 24
Peak memory 195700 kb
Host smart-d8f2334e-153e-4818-b21b-310dab5cdbc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210315490 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1210315490
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1007272025
Short name T346
Test name
Test status
Simulation time 389584818 ps
CPU time 0.9 seconds
Started Jun 09 12:30:24 PM PDT 24
Finished Jun 09 12:30:26 PM PDT 24
Peak memory 191896 kb
Host smart-cd2e6eaf-e666-449c-b429-711ea859cd9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007272025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1007272025
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1238781282
Short name T302
Test name
Test status
Simulation time 477687714 ps
CPU time 0.85 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 192776 kb
Host smart-ef8df9ea-58b1-4e39-a018-e3346b690d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238781282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1238781282
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1179890942
Short name T353
Test name
Test status
Simulation time 364348020 ps
CPU time 0.79 seconds
Started Jun 09 12:30:13 PM PDT 24
Finished Jun 09 12:30:14 PM PDT 24
Peak memory 183428 kb
Host smart-ce483c11-c941-49ce-a61d-fe53bfb9dfa0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179890942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1179890942
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1310911381
Short name T309
Test name
Test status
Simulation time 450022664 ps
CPU time 0.59 seconds
Started Jun 09 12:30:25 PM PDT 24
Finished Jun 09 12:30:27 PM PDT 24
Peak memory 183512 kb
Host smart-16594975-cc42-483e-86ad-c0dc6eb93cb2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310911381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1310911381
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2362553140
Short name T415
Test name
Test status
Simulation time 1550589879 ps
CPU time 2.81 seconds
Started Jun 09 12:30:23 PM PDT 24
Finished Jun 09 12:30:26 PM PDT 24
Peak memory 194052 kb
Host smart-555d41f2-b931-414d-a338-620f61919bac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362553140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2362553140
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2255765877
Short name T311
Test name
Test status
Simulation time 471528929 ps
CPU time 2.51 seconds
Started Jun 09 12:30:21 PM PDT 24
Finished Jun 09 12:30:24 PM PDT 24
Peak memory 198332 kb
Host smart-0bc5744a-02a9-44b2-9b9b-efb00257e67c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255765877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2255765877
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1211763526
Short name T58
Test name
Test status
Simulation time 390606386 ps
CPU time 0.78 seconds
Started Jun 09 12:30:32 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 193112 kb
Host smart-74bbab2b-b09e-4fd0-af43-339679470c32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211763526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1211763526
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1768239678
Short name T53
Test name
Test status
Simulation time 6770836006 ps
CPU time 10.42 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:37 PM PDT 24
Peak memory 195940 kb
Host smart-b48a18c3-07bd-403c-ba92-43b57febd306
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768239678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1768239678
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2685064312
Short name T283
Test name
Test status
Simulation time 1097055858 ps
CPU time 0.77 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:39 PM PDT 24
Peak memory 193828 kb
Host smart-fe4ea167-9f2d-4ac5-b5f6-e8f6c6df63b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685064312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2685064312
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1411511582
Short name T364
Test name
Test status
Simulation time 397612816 ps
CPU time 0.76 seconds
Started Jun 09 12:30:32 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 195196 kb
Host smart-63773379-7782-404e-acea-df5f74d3a10b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411511582 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1411511582
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1984107097
Short name T54
Test name
Test status
Simulation time 397900726 ps
CPU time 0.83 seconds
Started Jun 09 12:30:22 PM PDT 24
Finished Jun 09 12:30:23 PM PDT 24
Peak memory 192760 kb
Host smart-3d3f5fad-5a80-438f-bab2-8ca13d6c0464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984107097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1984107097
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.249593723
Short name T387
Test name
Test status
Simulation time 438116497 ps
CPU time 0.74 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 183560 kb
Host smart-8477510b-a826-456a-850c-4f2c5b9c7b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249593723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.249593723
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1149618082
Short name T407
Test name
Test status
Simulation time 322317432 ps
CPU time 0.6 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:27 PM PDT 24
Peak memory 183432 kb
Host smart-774280a3-f080-45ef-8b68-c30e7a242597
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149618082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1149618082
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3406302636
Short name T288
Test name
Test status
Simulation time 500162373 ps
CPU time 0.56 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:27 PM PDT 24
Peak memory 183472 kb
Host smart-a82b9e1d-0022-462c-910f-a9b16333233a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406302636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3406302636
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2362005805
Short name T404
Test name
Test status
Simulation time 3252302527 ps
CPU time 7.77 seconds
Started Jun 09 12:30:30 PM PDT 24
Finished Jun 09 12:30:39 PM PDT 24
Peak memory 191944 kb
Host smart-dabf0912-69ab-4067-b3c6-9b8303bbbeea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362005805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2362005805
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4096048568
Short name T304
Test name
Test status
Simulation time 1349014290 ps
CPU time 1.54 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:28 PM PDT 24
Peak memory 198348 kb
Host smart-d35366a7-6db1-4aba-9fac-65edd8c15a51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096048568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.4096048568
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.827881357
Short name T322
Test name
Test status
Simulation time 4339434156 ps
CPU time 7.21 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 197832 kb
Host smart-97b2cd7e-6409-4a58-8204-be375b6c914c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827881357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.827881357
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2513136939
Short name T324
Test name
Test status
Simulation time 374728744 ps
CPU time 0.74 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 195528 kb
Host smart-5e7c962d-cfdd-4d34-a918-d76920588821
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513136939 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2513136939
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1558384740
Short name T69
Test name
Test status
Simulation time 388170308 ps
CPU time 0.9 seconds
Started Jun 09 12:30:22 PM PDT 24
Finished Jun 09 12:30:23 PM PDT 24
Peak memory 192936 kb
Host smart-98aecfe4-21af-4bb9-adb2-7e65f3ec8dd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558384740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1558384740
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2945542467
Short name T362
Test name
Test status
Simulation time 504960723 ps
CPU time 0.74 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:40 PM PDT 24
Peak memory 192732 kb
Host smart-bca2e4d0-bea5-409d-bc43-b2d58e1ab993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945542467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2945542467
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4069211534
Short name T286
Test name
Test status
Simulation time 345467729 ps
CPU time 1.3 seconds
Started Jun 09 12:30:32 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 198304 kb
Host smart-4d652b43-327f-478e-bbf7-c3ca75addb50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069211534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.4069211534
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3925704953
Short name T195
Test name
Test status
Simulation time 7860134953 ps
CPU time 12.86 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:44 PM PDT 24
Peak memory 197996 kb
Host smart-b8fa302b-301a-4851-b476-8975ee9afc0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925704953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3925704953
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1355272015
Short name T282
Test name
Test status
Simulation time 452980764 ps
CPU time 1.01 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:28 PM PDT 24
Peak memory 196256 kb
Host smart-28101beb-04b1-41bd-8b5d-9a8d2b5df34d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355272015 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1355272015
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3333257799
Short name T403
Test name
Test status
Simulation time 351823282 ps
CPU time 0.74 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:28 PM PDT 24
Peak memory 192872 kb
Host smart-a810c478-738d-47bf-a5eb-c20b60b4d23d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333257799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3333257799
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1190232495
Short name T398
Test name
Test status
Simulation time 477807331 ps
CPU time 0.72 seconds
Started Jun 09 12:30:34 PM PDT 24
Finished Jun 09 12:30:35 PM PDT 24
Peak memory 183492 kb
Host smart-fb747ebb-b751-4a31-a533-6dce4fcadd37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190232495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1190232495
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2643240064
Short name T373
Test name
Test status
Simulation time 1231525373 ps
CPU time 2.58 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 193876 kb
Host smart-41a183a0-1b43-439f-b02f-8e51d098203e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643240064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2643240064
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.561086119
Short name T315
Test name
Test status
Simulation time 337712711 ps
CPU time 1.53 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:41 PM PDT 24
Peak memory 198224 kb
Host smart-cf26ea37-e9dd-49df-85cd-bd865d29ddda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561086119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.561086119
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3203376759
Short name T198
Test name
Test status
Simulation time 3859875570 ps
CPU time 3.57 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 196444 kb
Host smart-df21d1f4-2ed7-4d5a-adba-e7351e0d1cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203376759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3203376759
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3302331282
Short name T200
Test name
Test status
Simulation time 537223900 ps
CPU time 1.35 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:40 PM PDT 24
Peak memory 195460 kb
Host smart-d1d7c91c-87f4-4188-a4c6-cc29a02cae5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302331282 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3302331282
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3498127846
Short name T356
Test name
Test status
Simulation time 507214945 ps
CPU time 1.36 seconds
Started Jun 09 12:30:37 PM PDT 24
Finished Jun 09 12:30:39 PM PDT 24
Peak memory 183728 kb
Host smart-d19ac2d9-ed12-4272-a27a-0e7e8a27eedd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498127846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3498127846
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1389509911
Short name T337
Test name
Test status
Simulation time 413641468 ps
CPU time 0.68 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 183512 kb
Host smart-81e43f5e-3164-4971-95a5-27c1a0e7be4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389509911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1389509911
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3229210349
Short name T386
Test name
Test status
Simulation time 1109231831 ps
CPU time 1.24 seconds
Started Jun 09 12:30:39 PM PDT 24
Finished Jun 09 12:30:40 PM PDT 24
Peak memory 192792 kb
Host smart-9d1a6eb9-b080-4f0d-9936-51c9cd727790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229210349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3229210349
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1517110160
Short name T303
Test name
Test status
Simulation time 386453426 ps
CPU time 1.6 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:40 PM PDT 24
Peak memory 198336 kb
Host smart-cd49889b-3172-4eb5-a671-94f916934a88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517110160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1517110160
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.327885836
Short name T312
Test name
Test status
Simulation time 4412579650 ps
CPU time 2.53 seconds
Started Jun 09 12:30:30 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 197616 kb
Host smart-c0aa0472-d925-4466-b927-758c8e1c4d34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327885836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.327885836
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.592044956
Short name T33
Test name
Test status
Simulation time 385071732 ps
CPU time 0.96 seconds
Started Jun 09 12:30:30 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 196400 kb
Host smart-82548c7f-b730-4c21-9bf5-f571688a9ff5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592044956 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.592044956
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.703258093
Short name T397
Test name
Test status
Simulation time 361121380 ps
CPU time 1.18 seconds
Started Jun 09 12:30:27 PM PDT 24
Finished Jun 09 12:30:29 PM PDT 24
Peak memory 193184 kb
Host smart-f669dc0b-db12-4aff-88fd-27f6ca8c31c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703258093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.703258093
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4187732531
Short name T354
Test name
Test status
Simulation time 322661248 ps
CPU time 0.89 seconds
Started Jun 09 12:30:30 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 183516 kb
Host smart-8a508cee-7a60-446f-89d1-de890233a107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187732531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4187732531
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.394027216
Short name T79
Test name
Test status
Simulation time 1490232861 ps
CPU time 3.62 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 183772 kb
Host smart-938de714-1df4-463e-96de-7c834ad2d9ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394027216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.394027216
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.792341656
Short name T358
Test name
Test status
Simulation time 448381628 ps
CPU time 1.75 seconds
Started Jun 09 12:30:32 PM PDT 24
Finished Jun 09 12:30:35 PM PDT 24
Peak memory 198388 kb
Host smart-13b15a2b-0dcc-4491-a292-8e9eff74c7e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792341656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.792341656
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3094153041
Short name T199
Test name
Test status
Simulation time 8004042491 ps
CPU time 3.77 seconds
Started Jun 09 12:30:40 PM PDT 24
Finished Jun 09 12:30:44 PM PDT 24
Peak memory 198096 kb
Host smart-0d17852e-f324-4492-9407-b7f1491eed2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094153041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3094153041
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.417195658
Short name T384
Test name
Test status
Simulation time 451200979 ps
CPU time 0.96 seconds
Started Jun 09 12:30:27 PM PDT 24
Finished Jun 09 12:30:29 PM PDT 24
Peak memory 198244 kb
Host smart-1be5599d-b312-4ca3-b47c-b69a16d105bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417195658 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.417195658
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3771930597
Short name T57
Test name
Test status
Simulation time 319174918 ps
CPU time 0.62 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 192784 kb
Host smart-0ebda52f-2514-45e9-9578-3b71d2fb2fd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771930597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3771930597
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2801751197
Short name T330
Test name
Test status
Simulation time 575837911 ps
CPU time 0.59 seconds
Started Jun 09 12:30:40 PM PDT 24
Finished Jun 09 12:30:41 PM PDT 24
Peak memory 183516 kb
Host smart-44813b3d-748d-4525-8964-d110b14ff298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801751197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2801751197
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.733624817
Short name T76
Test name
Test status
Simulation time 2312813455 ps
CPU time 2.54 seconds
Started Jun 09 12:30:34 PM PDT 24
Finished Jun 09 12:30:37 PM PDT 24
Peak memory 194872 kb
Host smart-ea648295-40e1-488d-a320-7598e6218ccd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733624817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.733624817
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3621027663
Short name T291
Test name
Test status
Simulation time 508021016 ps
CPU time 2.02 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:41 PM PDT 24
Peak memory 198332 kb
Host smart-fa6ee77e-c64e-424f-b0e6-c34430f221f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621027663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3621027663
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3618290192
Short name T31
Test name
Test status
Simulation time 8355516517 ps
CPU time 13.29 seconds
Started Jun 09 12:30:42 PM PDT 24
Finished Jun 09 12:30:55 PM PDT 24
Peak memory 198104 kb
Host smart-7cf94188-b530-4b41-abb9-b5318de5835b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618290192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3618290192
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2970973964
Short name T390
Test name
Test status
Simulation time 536459935 ps
CPU time 0.88 seconds
Started Jun 09 12:30:31 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 196740 kb
Host smart-e2cf4cc0-9600-45f6-b83a-5c59e0e6ee41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970973964 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2970973964
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.385242202
Short name T68
Test name
Test status
Simulation time 469342754 ps
CPU time 1.23 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:29 PM PDT 24
Peak memory 191872 kb
Host smart-154970bb-84ce-4c61-8c81-3a142b228692
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385242202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.385242202
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.621184659
Short name T326
Test name
Test status
Simulation time 410121612 ps
CPU time 1.19 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 192744 kb
Host smart-117a2a56-24af-4d49-80da-d3e91ed2e3c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621184659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.621184659
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2349312015
Short name T73
Test name
Test status
Simulation time 1589564967 ps
CPU time 2.91 seconds
Started Jun 09 12:30:37 PM PDT 24
Finished Jun 09 12:30:40 PM PDT 24
Peak memory 193028 kb
Host smart-7cc0d86c-0357-411e-99fa-985f34a14da5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349312015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2349312015
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4084409366
Short name T300
Test name
Test status
Simulation time 316080824 ps
CPU time 2.06 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 198364 kb
Host smart-bdbde012-3dae-4946-a0ed-34a1df34e906
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084409366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.4084409366
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2445267910
Short name T329
Test name
Test status
Simulation time 386540793 ps
CPU time 0.79 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 196224 kb
Host smart-73e46c52-e6a2-4baa-97be-d89c78cc889e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445267910 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2445267910
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1742759818
Short name T376
Test name
Test status
Simulation time 521908896 ps
CPU time 1.26 seconds
Started Jun 09 12:30:32 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 191864 kb
Host smart-45d97dcf-682b-4393-b42f-1587068473bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742759818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1742759818
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4074414442
Short name T413
Test name
Test status
Simulation time 345371382 ps
CPU time 0.96 seconds
Started Jun 09 12:30:36 PM PDT 24
Finished Jun 09 12:30:38 PM PDT 24
Peak memory 183768 kb
Host smart-c43f207a-d05c-458e-a1d5-157b18576800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074414442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.4074414442
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3473377373
Short name T78
Test name
Test status
Simulation time 1194709066 ps
CPU time 1.79 seconds
Started Jun 09 12:30:35 PM PDT 24
Finished Jun 09 12:30:37 PM PDT 24
Peak memory 193040 kb
Host smart-dcbcfe5f-f129-4b6b-8cec-16d68c5485c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473377373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3473377373
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4167796227
Short name T371
Test name
Test status
Simulation time 570452261 ps
CPU time 2.06 seconds
Started Jun 09 12:30:33 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 198356 kb
Host smart-6539e4cf-c847-4809-868f-f66d7cd37e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167796227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4167796227
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2718014481
Short name T335
Test name
Test status
Simulation time 8477975393 ps
CPU time 5 seconds
Started Jun 09 12:30:30 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 198128 kb
Host smart-5b5db44f-3aff-4aa8-96c6-f17736f653df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718014481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2718014481
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2203565367
Short name T378
Test name
Test status
Simulation time 877376949 ps
CPU time 0.84 seconds
Started Jun 09 12:30:34 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 198232 kb
Host smart-1762b0c4-3eab-4cf8-8759-b822b87ad2e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203565367 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2203565367
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2479778708
Short name T71
Test name
Test status
Simulation time 520899671 ps
CPU time 0.95 seconds
Started Jun 09 12:30:34 PM PDT 24
Finished Jun 09 12:30:35 PM PDT 24
Peak memory 192824 kb
Host smart-3f69a0c0-22ad-4dd4-94f7-36258ef0f615
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479778708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2479778708
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3181431970
Short name T418
Test name
Test status
Simulation time 309020126 ps
CPU time 1.1 seconds
Started Jun 09 12:30:42 PM PDT 24
Finished Jun 09 12:30:44 PM PDT 24
Peak memory 183512 kb
Host smart-cd6173f0-3893-437f-9a50-03fac6947182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181431970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3181431970
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.164544286
Short name T370
Test name
Test status
Simulation time 2271797044 ps
CPU time 5.21 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:43 PM PDT 24
Peak memory 191864 kb
Host smart-9f463b0b-ff0b-4bca-a1b6-d3ed211d35b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164544286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.164544286
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2307107467
Short name T395
Test name
Test status
Simulation time 332006122 ps
CPU time 1.5 seconds
Started Jun 09 12:30:27 PM PDT 24
Finished Jun 09 12:30:29 PM PDT 24
Peak memory 198348 kb
Host smart-2904de77-18bb-4810-a919-cb1dcdbb31d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307107467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2307107467
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1620683606
Short name T323
Test name
Test status
Simulation time 8743820626 ps
CPU time 4.53 seconds
Started Jun 09 12:30:39 PM PDT 24
Finished Jun 09 12:30:44 PM PDT 24
Peak memory 198156 kb
Host smart-6f84d0ab-f42d-43f0-b8c5-8356cf9f2f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620683606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1620683606
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2769676443
Short name T357
Test name
Test status
Simulation time 450146661 ps
CPU time 1.15 seconds
Started Jun 09 12:30:39 PM PDT 24
Finished Jun 09 12:30:41 PM PDT 24
Peak memory 195824 kb
Host smart-bf7f5154-9bd4-42da-8a1e-df8323ab5e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769676443 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2769676443
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3563993796
Short name T341
Test name
Test status
Simulation time 430199209 ps
CPU time 1.19 seconds
Started Jun 09 12:30:30 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 192844 kb
Host smart-5f118f15-2c96-4186-a786-aa75e993d777
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563993796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3563993796
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3114317769
Short name T295
Test name
Test status
Simulation time 292018383 ps
CPU time 0.61 seconds
Started Jun 09 12:30:36 PM PDT 24
Finished Jun 09 12:30:38 PM PDT 24
Peak memory 183508 kb
Host smart-ed8b5f06-7ebd-45f8-b13a-ba09f32b1947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114317769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3114317769
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2279297653
Short name T80
Test name
Test status
Simulation time 2488491387 ps
CPU time 1.62 seconds
Started Jun 09 12:30:36 PM PDT 24
Finished Jun 09 12:30:38 PM PDT 24
Peak memory 193716 kb
Host smart-2b1f053f-5325-4218-808b-90afafe38fd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279297653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2279297653
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.4252363176
Short name T416
Test name
Test status
Simulation time 475272353 ps
CPU time 1.48 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 198316 kb
Host smart-0ef0afeb-74e6-4409-8553-c40bc3752a34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252363176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.4252363176
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3318898311
Short name T400
Test name
Test status
Simulation time 9748405735 ps
CPU time 4.28 seconds
Started Jun 09 12:30:30 PM PDT 24
Finished Jun 09 12:30:35 PM PDT 24
Peak memory 197960 kb
Host smart-dfe23e33-7942-4a9c-9770-48fd49e92f57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318898311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3318898311
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.787464791
Short name T406
Test name
Test status
Simulation time 480828981 ps
CPU time 0.94 seconds
Started Jun 09 12:30:36 PM PDT 24
Finished Jun 09 12:30:38 PM PDT 24
Peak memory 195772 kb
Host smart-8e0456ad-e108-4a5c-b403-c5271c347df7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787464791 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.787464791
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3965833926
Short name T292
Test name
Test status
Simulation time 317496924 ps
CPU time 1.05 seconds
Started Jun 09 12:30:44 PM PDT 24
Finished Jun 09 12:30:45 PM PDT 24
Peak memory 193260 kb
Host smart-61f70c30-90f0-44eb-b6f4-8e558f5189ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965833926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3965833926
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2862098570
Short name T290
Test name
Test status
Simulation time 396270331 ps
CPU time 0.64 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 192732 kb
Host smart-da48ca15-73a0-4cc8-8c98-111e9ca55d18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862098570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2862098570
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3206431722
Short name T74
Test name
Test status
Simulation time 1360102200 ps
CPU time 2.38 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 193328 kb
Host smart-4188cfa2-1371-44a9-bdbf-9a85ba57364f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206431722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3206431722
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1141127981
Short name T396
Test name
Test status
Simulation time 414431708 ps
CPU time 2 seconds
Started Jun 09 12:30:35 PM PDT 24
Finished Jun 09 12:30:38 PM PDT 24
Peak memory 198364 kb
Host smart-2ec7828e-ad1d-46e2-98f9-e20b1aceef19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141127981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1141127981
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3887571268
Short name T35
Test name
Test status
Simulation time 8814876393 ps
CPU time 2.15 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 197984 kb
Host smart-84552437-4522-4ee9-afd1-fb8d46149221
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887571268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3887571268
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1200225106
Short name T365
Test name
Test status
Simulation time 569717816 ps
CPU time 1.04 seconds
Started Jun 09 12:30:24 PM PDT 24
Finished Jun 09 12:30:25 PM PDT 24
Peak memory 192956 kb
Host smart-226df855-d3b0-426f-9016-283847cd4e99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200225106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1200225106
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1397611230
Short name T67
Test name
Test status
Simulation time 1963473511 ps
CPU time 2.58 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 195280 kb
Host smart-99d98680-ffe9-4735-ad44-8b9ee076c8f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397611230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1397611230
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3291700034
Short name T336
Test name
Test status
Simulation time 925252023 ps
CPU time 1.69 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 192832 kb
Host smart-189983f0-b580-46d4-8e1e-758de2542624
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291700034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3291700034
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.4034110493
Short name T405
Test name
Test status
Simulation time 610447825 ps
CPU time 0.93 seconds
Started Jun 09 12:30:31 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 196208 kb
Host smart-1fc46455-4943-47df-b1d0-2a4e582f0d2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034110493 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.4034110493
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3174547170
Short name T66
Test name
Test status
Simulation time 536271495 ps
CPU time 0.8 seconds
Started Jun 09 12:30:41 PM PDT 24
Finished Jun 09 12:30:42 PM PDT 24
Peak memory 193116 kb
Host smart-2d524cb3-ae70-4445-a106-7bce3af45aa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174547170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3174547170
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.322056243
Short name T414
Test name
Test status
Simulation time 275256292 ps
CPU time 0.89 seconds
Started Jun 09 12:30:30 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 192780 kb
Host smart-668f21b7-0b50-4499-8e8b-8dc6e5815360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322056243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.322056243
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3095687675
Short name T385
Test name
Test status
Simulation time 425212338 ps
CPU time 1.12 seconds
Started Jun 09 12:30:30 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 183444 kb
Host smart-9e2b354e-3045-4cb4-95de-a2585eebe716
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095687675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3095687675
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2940990846
Short name T307
Test name
Test status
Simulation time 342279220 ps
CPU time 0.98 seconds
Started Jun 09 12:30:35 PM PDT 24
Finished Jun 09 12:30:37 PM PDT 24
Peak memory 183524 kb
Host smart-8a73d55c-3c4f-4d5b-8306-79ed45572b14
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940990846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2940990846
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4157310277
Short name T389
Test name
Test status
Simulation time 1194563063 ps
CPU time 1.38 seconds
Started Jun 09 12:30:35 PM PDT 24
Finished Jun 09 12:30:38 PM PDT 24
Peak memory 192784 kb
Host smart-a24e2f37-ca04-4e06-bb0b-e230233dd811
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157310277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.4157310277
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3596239377
Short name T351
Test name
Test status
Simulation time 281195267 ps
CPU time 1.59 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 198320 kb
Host smart-bed34828-73d1-4b16-bda3-8b80b4d98d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596239377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3596239377
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2204579419
Short name T349
Test name
Test status
Simulation time 4307569683 ps
CPU time 2.71 seconds
Started Jun 09 12:30:33 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 197492 kb
Host smart-156676d0-db24-4f51-a7ce-a6c988459de3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204579419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2204579419
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.4059255262
Short name T331
Test name
Test status
Simulation time 448690073 ps
CPU time 0.89 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 183512 kb
Host smart-e4f456ce-bc34-4f24-b31f-9e3975b5b2d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059255262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.4059255262
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1525222175
Short name T408
Test name
Test status
Simulation time 549770601 ps
CPU time 0.61 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:28 PM PDT 24
Peak memory 183528 kb
Host smart-5759cb88-f56f-406a-a83d-9b8379e13e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525222175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1525222175
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3532824372
Short name T399
Test name
Test status
Simulation time 465694158 ps
CPU time 0.68 seconds
Started Jun 09 12:30:39 PM PDT 24
Finished Jun 09 12:30:41 PM PDT 24
Peak memory 183492 kb
Host smart-6723a41a-5080-416d-b703-f670dc338ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532824372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3532824372
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2591432143
Short name T391
Test name
Test status
Simulation time 319943634 ps
CPU time 0.78 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 192772 kb
Host smart-0710e54c-8d04-4742-a888-b704fc4b2a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591432143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2591432143
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4218148053
Short name T361
Test name
Test status
Simulation time 519616702 ps
CPU time 0.7 seconds
Started Jun 09 12:30:32 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 183504 kb
Host smart-1f71cfd6-349d-4487-a5ea-c3dde0387bdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218148053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4218148053
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.636301545
Short name T352
Test name
Test status
Simulation time 303416673 ps
CPU time 1.06 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 183524 kb
Host smart-fb955783-4a1d-43a1-97d5-bdb195f84ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636301545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.636301545
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1567018624
Short name T310
Test name
Test status
Simulation time 442951792 ps
CPU time 0.67 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 183516 kb
Host smart-78ee50a9-4c59-458a-b885-d24f23e382d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567018624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1567018624
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4026703446
Short name T393
Test name
Test status
Simulation time 502280254 ps
CPU time 0.59 seconds
Started Jun 09 12:30:31 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 183512 kb
Host smart-872ebec8-b6d3-46ea-8f41-1a818a9d6502
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026703446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.4026703446
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1841552512
Short name T347
Test name
Test status
Simulation time 503038882 ps
CPU time 0.74 seconds
Started Jun 09 12:30:32 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 183512 kb
Host smart-8004dd27-aa1f-463b-8478-cdee56f945c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841552512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1841552512
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3231955605
Short name T367
Test name
Test status
Simulation time 437746567 ps
CPU time 0.72 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 183512 kb
Host smart-20144c06-bb13-4b54-b287-152c1f1a0a80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231955605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3231955605
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1706309228
Short name T334
Test name
Test status
Simulation time 512121727 ps
CPU time 0.89 seconds
Started Jun 09 12:30:34 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 193828 kb
Host smart-02276c91-aab8-415e-b2e4-ca1435a11265
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706309228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1706309228
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1861002266
Short name T51
Test name
Test status
Simulation time 9194114124 ps
CPU time 5.61 seconds
Started Jun 09 12:30:32 PM PDT 24
Finished Jun 09 12:30:38 PM PDT 24
Peak memory 195912 kb
Host smart-9a684254-eafb-405b-8459-ce897741a64b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861002266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1861002266
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2860202253
Short name T333
Test name
Test status
Simulation time 741614610 ps
CPU time 1.73 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 192804 kb
Host smart-37fe8ffe-eb85-4668-a382-bf7854c375ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860202253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2860202253
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.412281671
Short name T37
Test name
Test status
Simulation time 437752192 ps
CPU time 1.02 seconds
Started Jun 09 12:30:27 PM PDT 24
Finished Jun 09 12:30:29 PM PDT 24
Peak memory 196216 kb
Host smart-63bed21c-1240-403c-a8ee-928941a70c0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412281671 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.412281671
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3824677243
Short name T50
Test name
Test status
Simulation time 458721782 ps
CPU time 1.24 seconds
Started Jun 09 12:30:21 PM PDT 24
Finished Jun 09 12:30:23 PM PDT 24
Peak memory 193388 kb
Host smart-f28b4db3-61f6-4b83-b1f9-6382aac2189c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824677243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3824677243
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.39607128
Short name T327
Test name
Test status
Simulation time 296855225 ps
CPU time 0.99 seconds
Started Jun 09 12:30:30 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 183468 kb
Host smart-1bcdd646-a3d0-4e73-8a67-ceb4b147e1db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39607128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.39607128
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2281238670
Short name T301
Test name
Test status
Simulation time 307354414 ps
CPU time 0.73 seconds
Started Jun 09 12:30:27 PM PDT 24
Finished Jun 09 12:30:29 PM PDT 24
Peak memory 183428 kb
Host smart-2d58b5eb-24de-4606-98ae-81071e32de3c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281238670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2281238670
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4683947
Short name T368
Test name
Test status
Simulation time 372369114 ps
CPU time 1.09 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 183556 kb
Host smart-e1b3fb99-6457-4dcd-9500-e6bd8c581518
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4683947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.4683947
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.835536806
Short name T388
Test name
Test status
Simulation time 2226832435 ps
CPU time 1.56 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 194972 kb
Host smart-44425e5c-e11f-44d8-b331-985a390a2559
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835536806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.835536806
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3792752868
Short name T320
Test name
Test status
Simulation time 444007344 ps
CPU time 2.07 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:41 PM PDT 24
Peak memory 198304 kb
Host smart-524ac936-59a1-444d-9570-dacc2000a8cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792752868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3792752868
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4124956098
Short name T350
Test name
Test status
Simulation time 4428020122 ps
CPU time 2.3 seconds
Started Jun 09 12:30:27 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 196972 kb
Host smart-8970c34b-bbe0-410b-ae5a-542cdac4ef4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124956098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.4124956098
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.95631522
Short name T377
Test name
Test status
Simulation time 517651821 ps
CPU time 0.71 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 183512 kb
Host smart-db5886c0-1fda-4ea1-b3af-b3bde0f42664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95631522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.95631522
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3992513261
Short name T392
Test name
Test status
Simulation time 372430540 ps
CPU time 0.66 seconds
Started Jun 09 12:30:36 PM PDT 24
Finished Jun 09 12:30:38 PM PDT 24
Peak memory 192732 kb
Host smart-c37295c9-a3f5-457e-b941-b3ed15f8cfc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992513261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3992513261
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.814905150
Short name T297
Test name
Test status
Simulation time 314012717 ps
CPU time 1.03 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 183520 kb
Host smart-ba9f29fe-4479-441b-a133-2a68e31d3e4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814905150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.814905150
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.179109039
Short name T372
Test name
Test status
Simulation time 445211715 ps
CPU time 0.81 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 192764 kb
Host smart-de3d78d0-d627-4541-8ec5-ab040f7c0488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179109039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.179109039
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.944257011
Short name T348
Test name
Test status
Simulation time 467216319 ps
CPU time 0.75 seconds
Started Jun 09 12:30:40 PM PDT 24
Finished Jun 09 12:30:41 PM PDT 24
Peak memory 192728 kb
Host smart-e2d500dd-b1f8-4ccd-9770-5be14fe1d970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944257011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.944257011
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3291269450
Short name T318
Test name
Test status
Simulation time 338563854 ps
CPU time 0.99 seconds
Started Jun 09 12:30:42 PM PDT 24
Finished Jun 09 12:30:43 PM PDT 24
Peak memory 183556 kb
Host smart-033f3223-c57e-4d21-8d6e-14827f096c39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291269450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3291269450
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3077274393
Short name T381
Test name
Test status
Simulation time 525501976 ps
CPU time 0.72 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 183532 kb
Host smart-9b6edf94-f77d-47d9-9c3a-9c39887aa097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077274393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3077274393
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.989166670
Short name T360
Test name
Test status
Simulation time 428812344 ps
CPU time 1.13 seconds
Started Jun 09 12:30:37 PM PDT 24
Finished Jun 09 12:30:39 PM PDT 24
Peak memory 192688 kb
Host smart-212cf671-0f0d-4a10-8508-6707b03ff167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989166670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.989166670
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3520770627
Short name T411
Test name
Test status
Simulation time 343434877 ps
CPU time 0.82 seconds
Started Jun 09 12:30:35 PM PDT 24
Finished Jun 09 12:30:37 PM PDT 24
Peak memory 183556 kb
Host smart-cb1632e6-2ccf-44df-8243-7b676cd93af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520770627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3520770627
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3929116039
Short name T332
Test name
Test status
Simulation time 418849728 ps
CPU time 1.09 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:39 PM PDT 24
Peak memory 183500 kb
Host smart-2a1d5a3b-417a-4221-b7ee-959148a3d084
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929116039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3929116039
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.647476655
Short name T409
Test name
Test status
Simulation time 636859494 ps
CPU time 1.4 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 194096 kb
Host smart-ffceb85a-04a6-45c6-9234-8a0ca3c96d8f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647476655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.647476655
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2799656753
Short name T417
Test name
Test status
Simulation time 11423150516 ps
CPU time 15.11 seconds
Started Jun 09 12:30:31 PM PDT 24
Finished Jun 09 12:30:47 PM PDT 24
Peak memory 192024 kb
Host smart-2d547d5e-862e-4453-8a84-0617e3259d01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799656753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2799656753
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.479543561
Short name T56
Test name
Test status
Simulation time 937797111 ps
CPU time 1.32 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 183772 kb
Host smart-55fcf4e4-7561-4727-a0e0-5ebe1cedc203
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479543561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.479543561
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2982709236
Short name T294
Test name
Test status
Simulation time 437081626 ps
CPU time 1.34 seconds
Started Jun 09 12:30:33 PM PDT 24
Finished Jun 09 12:30:35 PM PDT 24
Peak memory 196200 kb
Host smart-950c090a-bdb6-4731-88cd-1d64e2e4629e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982709236 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2982709236
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4126929524
Short name T299
Test name
Test status
Simulation time 522769430 ps
CPU time 0.78 seconds
Started Jun 09 12:30:34 PM PDT 24
Finished Jun 09 12:30:35 PM PDT 24
Peak memory 183720 kb
Host smart-cea0b958-080b-4708-915f-5b05b8c1b973
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126929524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.4126929524
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.693896391
Short name T402
Test name
Test status
Simulation time 430811548 ps
CPU time 1.14 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:28 PM PDT 24
Peak memory 192692 kb
Host smart-9b59a906-6f7b-4c62-b885-8888f87255f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693896391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.693896391
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2654027606
Short name T363
Test name
Test status
Simulation time 499458670 ps
CPU time 0.71 seconds
Started Jun 09 12:30:23 PM PDT 24
Finished Jun 09 12:30:24 PM PDT 24
Peak memory 183484 kb
Host smart-be1f23b2-f62b-49fb-ac27-ff945d65237c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654027606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2654027606
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1866276256
Short name T284
Test name
Test status
Simulation time 490164074 ps
CPU time 1.32 seconds
Started Jun 09 12:30:30 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 183508 kb
Host smart-f525655a-c94f-483c-9cdb-8472e48aa6aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866276256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1866276256
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.640276991
Short name T344
Test name
Test status
Simulation time 2186239041 ps
CPU time 5.09 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 193932 kb
Host smart-eed823c6-c6de-455f-a2ba-e1595fbc3e62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640276991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.640276991
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4152986562
Short name T410
Test name
Test status
Simulation time 453602242 ps
CPU time 1.44 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 198352 kb
Host smart-94d6f338-6cf9-4538-a9f4-e6095e58ecfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152986562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4152986562
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.968749639
Short name T380
Test name
Test status
Simulation time 4174628063 ps
CPU time 4.46 seconds
Started Jun 09 12:30:36 PM PDT 24
Finished Jun 09 12:30:42 PM PDT 24
Peak memory 197740 kb
Host smart-88fdb21d-0c4d-4fd3-adea-ab4378cb8174
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968749639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.968749639
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.6167682
Short name T285
Test name
Test status
Simulation time 370503951 ps
CPU time 0.84 seconds
Started Jun 09 12:30:40 PM PDT 24
Finished Jun 09 12:30:41 PM PDT 24
Peak memory 192744 kb
Host smart-a7fc94b6-e18c-4954-8953-1f9441a0b472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6167682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.6167682
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3350206317
Short name T296
Test name
Test status
Simulation time 465402599 ps
CPU time 0.86 seconds
Started Jun 09 12:30:43 PM PDT 24
Finished Jun 09 12:30:44 PM PDT 24
Peak memory 183536 kb
Host smart-d7f8a660-cc54-49eb-8ea8-999e664d3b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350206317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3350206317
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2982088765
Short name T305
Test name
Test status
Simulation time 348936873 ps
CPU time 1.12 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:40 PM PDT 24
Peak memory 183512 kb
Host smart-fdeaa7f3-fd21-49d5-8917-28aedc07529b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982088765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2982088765
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3751557192
Short name T306
Test name
Test status
Simulation time 440650429 ps
CPU time 0.55 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:39 PM PDT 24
Peak memory 192756 kb
Host smart-5606e86c-9744-461f-b674-46fcf77ba47f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751557192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3751557192
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2473240498
Short name T369
Test name
Test status
Simulation time 507555282 ps
CPU time 0.74 seconds
Started Jun 09 12:30:42 PM PDT 24
Finished Jun 09 12:30:43 PM PDT 24
Peak memory 183528 kb
Host smart-164e7e76-10fb-4c21-b381-348fbc4ecd48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473240498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2473240498
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.941354191
Short name T298
Test name
Test status
Simulation time 359777793 ps
CPU time 0.6 seconds
Started Jun 09 12:30:31 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 183480 kb
Host smart-53d15311-ec60-4faf-84b9-b0cc66c52050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941354191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.941354191
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1377202631
Short name T342
Test name
Test status
Simulation time 298981466 ps
CPU time 0.64 seconds
Started Jun 09 12:30:34 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 183500 kb
Host smart-8f932ecf-404b-4ee7-b032-a526cd71945a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377202631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1377202631
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3855699720
Short name T314
Test name
Test status
Simulation time 523336665 ps
CPU time 0.78 seconds
Started Jun 09 12:30:31 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 183496 kb
Host smart-e0959507-15e5-47f5-a211-5af96f68afc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855699720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3855699720
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2649018621
Short name T308
Test name
Test status
Simulation time 455091697 ps
CPU time 0.69 seconds
Started Jun 09 12:30:35 PM PDT 24
Finished Jun 09 12:30:37 PM PDT 24
Peak memory 183524 kb
Host smart-8766f641-f0d5-4f68-ac78-1df83b8e20ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649018621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2649018621
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1687285201
Short name T340
Test name
Test status
Simulation time 354419248 ps
CPU time 1.04 seconds
Started Jun 09 12:30:39 PM PDT 24
Finished Jun 09 12:30:41 PM PDT 24
Peak memory 183496 kb
Host smart-a9e5465b-877d-4817-b84c-811792776729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687285201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1687285201
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3213165291
Short name T316
Test name
Test status
Simulation time 556039464 ps
CPU time 1.11 seconds
Started Jun 09 12:30:31 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 197128 kb
Host smart-c4d13c28-a3bf-48d4-b70f-9f22ecba523a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213165291 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3213165291
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3339893555
Short name T412
Test name
Test status
Simulation time 396486875 ps
CPU time 0.79 seconds
Started Jun 09 12:30:35 PM PDT 24
Finished Jun 09 12:30:37 PM PDT 24
Peak memory 183960 kb
Host smart-86fa3700-ccc5-427a-bfb7-664230827171
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339893555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3339893555
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.4084210373
Short name T321
Test name
Test status
Simulation time 439858468 ps
CPU time 0.67 seconds
Started Jun 09 12:30:27 PM PDT 24
Finished Jun 09 12:30:29 PM PDT 24
Peak memory 183524 kb
Host smart-23556dcc-e293-4b64-ae22-3ae31e010320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084210373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.4084210373
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2044905734
Short name T72
Test name
Test status
Simulation time 2359442684 ps
CPU time 3.01 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 194212 kb
Host smart-e5e76440-96c0-494e-bbc8-fdc3b0a5eb1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044905734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2044905734
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3172197697
Short name T287
Test name
Test status
Simulation time 965100106 ps
CPU time 1.98 seconds
Started Jun 09 12:30:34 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 198344 kb
Host smart-8b3f6fb7-046d-4896-a610-21a0af084471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172197697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3172197697
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1462969448
Short name T359
Test name
Test status
Simulation time 679147370 ps
CPU time 0.95 seconds
Started Jun 09 12:30:32 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 198248 kb
Host smart-c09fa847-ce7f-4d36-b197-f3bb8f019e36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462969448 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1462969448
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2968048012
Short name T338
Test name
Test status
Simulation time 306697892 ps
CPU time 1.13 seconds
Started Jun 09 12:30:40 PM PDT 24
Finished Jun 09 12:30:42 PM PDT 24
Peak memory 192900 kb
Host smart-f851988c-7b40-40a1-b0a0-7aabe8e3e41e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968048012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2968048012
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3220484644
Short name T328
Test name
Test status
Simulation time 346904419 ps
CPU time 0.69 seconds
Started Jun 09 12:30:31 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 183520 kb
Host smart-f8a809fa-067a-41c5-bfbe-458a39bac06e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220484644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3220484644
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.818880391
Short name T77
Test name
Test status
Simulation time 2432573983 ps
CPU time 4.16 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 194724 kb
Host smart-c0f3b669-fe44-464a-83bb-c52ae5f7816a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818880391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.818880391
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1732281824
Short name T366
Test name
Test status
Simulation time 576626025 ps
CPU time 1.45 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 198304 kb
Host smart-54b48c74-d0a5-4c7e-8d09-ec8583e0f333
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732281824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1732281824
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1149169910
Short name T394
Test name
Test status
Simulation time 4584746073 ps
CPU time 2.34 seconds
Started Jun 09 12:30:31 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 196600 kb
Host smart-42a5a194-e988-49b1-a848-e674b922dcea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149169910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1149169910
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3889157321
Short name T32
Test name
Test status
Simulation time 358238185 ps
CPU time 0.77 seconds
Started Jun 09 12:30:31 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 195648 kb
Host smart-829889c7-231b-4479-85a9-2a2e923d4ddb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889157321 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3889157321
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3992979667
Short name T383
Test name
Test status
Simulation time 345481584 ps
CPU time 0.68 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:27 PM PDT 24
Peak memory 192844 kb
Host smart-f6512d85-6e7b-437f-a6ab-3ad539c5a723
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992979667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3992979667
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2099169113
Short name T325
Test name
Test status
Simulation time 328249673 ps
CPU time 1.03 seconds
Started Jun 09 12:30:32 PM PDT 24
Finished Jun 09 12:30:39 PM PDT 24
Peak memory 192772 kb
Host smart-44fae726-c39f-49f6-b4e5-924ad37faaa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099169113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2099169113
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.231706564
Short name T317
Test name
Test status
Simulation time 1147601841 ps
CPU time 0.89 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 193876 kb
Host smart-786e0c95-4261-48df-816e-f89ed4492092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231706564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.231706564
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3501123725
Short name T374
Test name
Test status
Simulation time 491578051 ps
CPU time 1.22 seconds
Started Jun 09 12:30:27 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 197592 kb
Host smart-ef65b0ff-1e2c-482f-9b6f-d4224fad529d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501123725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3501123725
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1508010048
Short name T343
Test name
Test status
Simulation time 4312784866 ps
CPU time 6.73 seconds
Started Jun 09 12:30:32 PM PDT 24
Finished Jun 09 12:30:40 PM PDT 24
Peak memory 197888 kb
Host smart-df18a0b7-5feb-4ad9-8742-08a0ba0e63e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508010048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1508010048
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2841712818
Short name T313
Test name
Test status
Simulation time 529806961 ps
CPU time 0.92 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 197124 kb
Host smart-87a7f0e0-f25f-4f04-95dd-35a854689149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841712818 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2841712818
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3570584488
Short name T70
Test name
Test status
Simulation time 363692001 ps
CPU time 1.15 seconds
Started Jun 09 12:30:36 PM PDT 24
Finished Jun 09 12:30:38 PM PDT 24
Peak memory 193808 kb
Host smart-d7b4ed44-52ab-42d0-990b-e300021e3a14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570584488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3570584488
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2370494900
Short name T319
Test name
Test status
Simulation time 465003125 ps
CPU time 1.05 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:28 PM PDT 24
Peak memory 183560 kb
Host smart-1cbd41d3-0eb1-433c-bf74-477d93e2cdc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370494900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2370494900
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2126974093
Short name T345
Test name
Test status
Simulation time 2274387518 ps
CPU time 2.51 seconds
Started Jun 09 12:30:39 PM PDT 24
Finished Jun 09 12:30:42 PM PDT 24
Peak memory 195112 kb
Host smart-c458ddd1-34d2-4a02-9de5-67707e3b37dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126974093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2126974093
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.472786901
Short name T355
Test name
Test status
Simulation time 491433235 ps
CPU time 1.77 seconds
Started Jun 09 12:30:36 PM PDT 24
Finished Jun 09 12:30:39 PM PDT 24
Peak memory 198328 kb
Host smart-3aa04ce0-1cac-4b74-a425-179f46f22f1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472786901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.472786901
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2901463565
Short name T293
Test name
Test status
Simulation time 7833209803 ps
CPU time 6.72 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 198096 kb
Host smart-3e6f2d16-3a1f-4668-aba6-5d81c81e291e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901463565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2901463565
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.209783847
Short name T339
Test name
Test status
Simulation time 492354004 ps
CPU time 1.29 seconds
Started Jun 09 12:30:34 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 195036 kb
Host smart-e152b40a-dffe-43fb-bfbd-ae547aeb0127
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209783847 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.209783847
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.863370722
Short name T382
Test name
Test status
Simulation time 519815916 ps
CPU time 0.93 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:39 PM PDT 24
Peak memory 183728 kb
Host smart-c0f9aa84-561e-4d50-a407-e6279c7cb15d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863370722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.863370722
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.340540485
Short name T401
Test name
Test status
Simulation time 377071960 ps
CPU time 0.64 seconds
Started Jun 09 12:30:30 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 183504 kb
Host smart-824111e0-bce1-4237-a623-f2698f961bba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340540485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.340540485
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2831839138
Short name T379
Test name
Test status
Simulation time 1218221832 ps
CPU time 1.69 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 192828 kb
Host smart-e3bc8a32-3840-445c-91b0-a66f635b4506
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831839138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2831839138
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1027390138
Short name T289
Test name
Test status
Simulation time 384765585 ps
CPU time 2.4 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 198328 kb
Host smart-e263a52d-88fd-4108-8761-0897b0ea6c95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027390138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1027390138
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2273608707
Short name T375
Test name
Test status
Simulation time 8565973561 ps
CPU time 14.67 seconds
Started Jun 09 12:30:27 PM PDT 24
Finished Jun 09 12:30:43 PM PDT 24
Peak memory 197900 kb
Host smart-6836b5e3-f9c4-478d-b01e-49f1b289733d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273608707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2273608707
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1257101535
Short name T227
Test name
Test status
Simulation time 41900044080 ps
CPU time 33.06 seconds
Started Jun 09 12:35:01 PM PDT 24
Finished Jun 09 12:35:35 PM PDT 24
Peak memory 191896 kb
Host smart-50274eac-f578-4419-90f8-85df2879a945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257101535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1257101535
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2187169709
Short name T254
Test name
Test status
Simulation time 560786914 ps
CPU time 1.43 seconds
Started Jun 09 12:35:14 PM PDT 24
Finished Jun 09 12:35:16 PM PDT 24
Peak memory 191772 kb
Host smart-35270503-3def-4e2f-a142-0b3ab8e0af3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187169709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2187169709
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3714963101
Short name T3
Test name
Test status
Simulation time 24074293533 ps
CPU time 20.62 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:26 PM PDT 24
Peak memory 191900 kb
Host smart-4d174d58-8223-4eea-8a72-b80a001f046f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714963101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3714963101
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1193093602
Short name T18
Test name
Test status
Simulation time 3885717349 ps
CPU time 6.85 seconds
Started Jun 09 12:34:48 PM PDT 24
Finished Jun 09 12:34:55 PM PDT 24
Peak memory 215508 kb
Host smart-88378102-abb4-471b-9847-27447ebca697
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193093602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1193093602
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3532438759
Short name T277
Test name
Test status
Simulation time 575605948 ps
CPU time 0.92 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:34:58 PM PDT 24
Peak memory 191792 kb
Host smart-4f3d1b3a-60e2-446e-93ff-3f370359c807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532438759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3532438759
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.998823920
Short name T273
Test name
Test status
Simulation time 32355432186 ps
CPU time 50.71 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:35:47 PM PDT 24
Peak memory 191876 kb
Host smart-c7021c02-1637-4ac4-8960-bc93e81002a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998823920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.998823920
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3845457721
Short name T242
Test name
Test status
Simulation time 567239033 ps
CPU time 1.02 seconds
Started Jun 09 12:35:07 PM PDT 24
Finished Jun 09 12:35:08 PM PDT 24
Peak memory 196568 kb
Host smart-2e066f2f-0cff-474d-9867-4883888dfd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845457721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3845457721
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2042190188
Short name T234
Test name
Test status
Simulation time 16776905032 ps
CPU time 27.54 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:35:26 PM PDT 24
Peak memory 191864 kb
Host smart-f6f2ed0c-ab7c-480a-bcf1-fb9af08579bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042190188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2042190188
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2628867041
Short name T8
Test name
Test status
Simulation time 412930522 ps
CPU time 1.11 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:35:00 PM PDT 24
Peak memory 191768 kb
Host smart-6d455d69-2790-4f46-aa86-bef0fe1a3029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628867041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2628867041
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.939911116
Short name T42
Test name
Test status
Simulation time 35508563127 ps
CPU time 49.77 seconds
Started Jun 09 12:34:54 PM PDT 24
Finished Jun 09 12:35:45 PM PDT 24
Peak memory 191880 kb
Host smart-8ced7d28-c666-4e22-86cc-70e560e7ee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939911116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.939911116
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.145295863
Short name T276
Test name
Test status
Simulation time 448386430 ps
CPU time 0.75 seconds
Started Jun 09 12:35:10 PM PDT 24
Finished Jun 09 12:35:11 PM PDT 24
Peak memory 196504 kb
Host smart-e9f31a37-0f0b-4f23-a80e-4a0cbfa22cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145295863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.145295863
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1819490912
Short name T205
Test name
Test status
Simulation time 59370525098 ps
CPU time 22.18 seconds
Started Jun 09 12:35:03 PM PDT 24
Finished Jun 09 12:35:26 PM PDT 24
Peak memory 192068 kb
Host smart-605d0cf6-feef-4f71-8d09-b713c74b3adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819490912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1819490912
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1151514277
Short name T245
Test name
Test status
Simulation time 524321235 ps
CPU time 0.98 seconds
Started Jun 09 12:34:53 PM PDT 24
Finished Jun 09 12:34:55 PM PDT 24
Peak memory 196524 kb
Host smart-fc76e3df-d042-4e74-9a3f-ff7bc03e1e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151514277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1151514277
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2751730926
Short name T256
Test name
Test status
Simulation time 23893306663 ps
CPU time 38.49 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:35:44 PM PDT 24
Peak memory 191832 kb
Host smart-d6bc8b5c-904e-4969-8c5e-fd2fd08c5a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751730926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2751730926
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2061409216
Short name T250
Test name
Test status
Simulation time 378339342 ps
CPU time 0.71 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:34:56 PM PDT 24
Peak memory 191720 kb
Host smart-150db04a-9cfb-4663-beb8-7bfddd336e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061409216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2061409216
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3181598995
Short name T172
Test name
Test status
Simulation time 552518547 ps
CPU time 0.65 seconds
Started Jun 09 12:35:07 PM PDT 24
Finished Jun 09 12:35:09 PM PDT 24
Peak memory 196564 kb
Host smart-7909dbc8-eaff-43c4-bb9a-dfb689803f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181598995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3181598995
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.910483328
Short name T263
Test name
Test status
Simulation time 28890672951 ps
CPU time 49.09 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 191892 kb
Host smart-f5687566-a220-4b6b-bb3c-56e3863bf9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910483328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.910483328
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.542544110
Short name T258
Test name
Test status
Simulation time 449465763 ps
CPU time 0.64 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:35:07 PM PDT 24
Peak memory 191768 kb
Host smart-67fb747d-528c-4b1d-a092-0a108d2fc3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542544110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.542544110
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.801318128
Short name T224
Test name
Test status
Simulation time 27649300364 ps
CPU time 11.41 seconds
Started Jun 09 12:34:59 PM PDT 24
Finished Jun 09 12:35:11 PM PDT 24
Peak memory 191916 kb
Host smart-15c8a745-7d2f-46ac-80ae-0383f114397b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801318128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.801318128
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3345407049
Short name T38
Test name
Test status
Simulation time 522482915 ps
CPU time 1.42 seconds
Started Jun 09 12:34:59 PM PDT 24
Finished Jun 09 12:35:01 PM PDT 24
Peak memory 191752 kb
Host smart-e42d867f-e3dd-410c-b99f-f4ef48beab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345407049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3345407049
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2570015640
Short name T264
Test name
Test status
Simulation time 58259950948 ps
CPU time 90.32 seconds
Started Jun 09 12:35:07 PM PDT 24
Finished Jun 09 12:36:38 PM PDT 24
Peak memory 191880 kb
Host smart-6ac95fa2-1efc-4fcc-8f5e-5d878adef72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570015640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2570015640
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3337335485
Short name T255
Test name
Test status
Simulation time 479041851 ps
CPU time 0.81 seconds
Started Jun 09 12:35:03 PM PDT 24
Finished Jun 09 12:35:04 PM PDT 24
Peak memory 196732 kb
Host smart-80ecf4f3-8a1a-46c5-92b5-c151d5060586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337335485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3337335485
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2100291088
Short name T211
Test name
Test status
Simulation time 19337530933 ps
CPU time 5.6 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:35:04 PM PDT 24
Peak memory 191908 kb
Host smart-1a777576-5310-411d-983c-f54e991b7d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100291088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2100291088
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3751572564
Short name T252
Test name
Test status
Simulation time 460443139 ps
CPU time 1.26 seconds
Started Jun 09 12:34:54 PM PDT 24
Finished Jun 09 12:34:56 PM PDT 24
Peak memory 191736 kb
Host smart-165a9e27-801b-4bda-aa74-8f64e523412d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751572564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3751572564
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2168567078
Short name T12
Test name
Test status
Simulation time 51999886419 ps
CPU time 24.17 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:35:22 PM PDT 24
Peak memory 191892 kb
Host smart-33b43b24-c88e-4799-b50d-d42efc08843d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168567078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2168567078
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1134606394
Short name T97
Test name
Test status
Simulation time 526132850 ps
CPU time 0.98 seconds
Started Jun 09 12:34:59 PM PDT 24
Finished Jun 09 12:35:00 PM PDT 24
Peak memory 191796 kb
Host smart-9dea5dfb-45d1-40d1-936f-6819a6fb97d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134606394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1134606394
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2136589785
Short name T247
Test name
Test status
Simulation time 508514287 ps
CPU time 0.78 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:34:57 PM PDT 24
Peak memory 191800 kb
Host smart-f5d53b18-2d0e-4046-a1c4-f424abc48076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136589785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2136589785
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.420744175
Short name T15
Test name
Test status
Simulation time 4556110522 ps
CPU time 1.17 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:34:59 PM PDT 24
Peak memory 215832 kb
Host smart-30d6af6c-7f0e-4ece-b63f-5f4ef078c706
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420744175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.420744175
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1800960083
Short name T10
Test name
Test status
Simulation time 545310489 ps
CPU time 1.35 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:06 PM PDT 24
Peak memory 191764 kb
Host smart-982c1ff8-e92f-4494-bb62-b0295d43d6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800960083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1800960083
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.850733805
Short name T218
Test name
Test status
Simulation time 423558798 ps
CPU time 1.24 seconds
Started Jun 09 12:35:11 PM PDT 24
Finished Jun 09 12:35:13 PM PDT 24
Peak memory 191712 kb
Host smart-31248e1f-6ed2-45a8-97cc-43ac48295a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850733805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.850733805
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1780088948
Short name T216
Test name
Test status
Simulation time 350740648 ps
CPU time 1.13 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:35:07 PM PDT 24
Peak memory 191780 kb
Host smart-6d3a5933-4ccd-4d3e-bcc9-2fd7ae663329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780088948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1780088948
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3136577524
Short name T279
Test name
Test status
Simulation time 53812253643 ps
CPU time 39.77 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:35:37 PM PDT 24
Peak memory 191912 kb
Host smart-40ab1268-7962-4f49-a93b-96190dade2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136577524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3136577524
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3075908879
Short name T212
Test name
Test status
Simulation time 539465058 ps
CPU time 0.79 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:06 PM PDT 24
Peak memory 196572 kb
Host smart-e08a511e-0083-4c30-bdb0-e021c37e2255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075908879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3075908879
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1651262429
Short name T161
Test name
Test status
Simulation time 483861042 ps
CPU time 0.77 seconds
Started Jun 09 12:35:18 PM PDT 24
Finished Jun 09 12:35:19 PM PDT 24
Peak memory 196536 kb
Host smart-17f56b69-e590-46d3-a81f-53b057bebc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651262429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1651262429
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3018831703
Short name T235
Test name
Test status
Simulation time 16693862213 ps
CPU time 3.43 seconds
Started Jun 09 12:35:08 PM PDT 24
Finished Jun 09 12:35:12 PM PDT 24
Peak memory 191892 kb
Host smart-1cdc63ed-795d-47d2-ae0e-3a254294535c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018831703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3018831703
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2338249801
Short name T208
Test name
Test status
Simulation time 562925197 ps
CPU time 0.79 seconds
Started Jun 09 12:35:09 PM PDT 24
Finished Jun 09 12:35:10 PM PDT 24
Peak memory 191756 kb
Host smart-62087d08-7514-413e-bd76-36e9d2b21e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338249801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2338249801
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1030396088
Short name T269
Test name
Test status
Simulation time 3590631274 ps
CPU time 5.67 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:35:03 PM PDT 24
Peak memory 191924 kb
Host smart-fe36cc7e-67ae-4b27-956d-e2453139fe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030396088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1030396088
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2549894729
Short name T274
Test name
Test status
Simulation time 588048933 ps
CPU time 0.74 seconds
Started Jun 09 12:35:29 PM PDT 24
Finished Jun 09 12:35:30 PM PDT 24
Peak memory 191772 kb
Host smart-395bfe05-c632-4f41-9f7c-d7f5a7557456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549894729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2549894729
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2771003089
Short name T240
Test name
Test status
Simulation time 26949336145 ps
CPU time 38.63 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:44 PM PDT 24
Peak memory 191904 kb
Host smart-8c635cca-7141-4f64-a137-252df3e2a78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771003089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2771003089
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2887216038
Short name T233
Test name
Test status
Simulation time 462104156 ps
CPU time 1.24 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:35:00 PM PDT 24
Peak memory 191752 kb
Host smart-359fee98-5ae0-45dd-9840-8e3e930402da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887216038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2887216038
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.4243786113
Short name T219
Test name
Test status
Simulation time 46713388533 ps
CPU time 18.08 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:35:24 PM PDT 24
Peak memory 191856 kb
Host smart-f4371f0f-1f20-4331-8a18-5e54215e948d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243786113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.4243786113
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2965826386
Short name T253
Test name
Test status
Simulation time 603178227 ps
CPU time 0.79 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:34:57 PM PDT 24
Peak memory 196548 kb
Host smart-fc0fd429-4c59-4750-a25e-33dd0a48c394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965826386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2965826386
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.4148214318
Short name T64
Test name
Test status
Simulation time 31838792582 ps
CPU time 32.18 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:35:28 PM PDT 24
Peak memory 191872 kb
Host smart-64c1acd2-8dd2-4453-9b3a-e2fe9518c51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148214318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.4148214318
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.601965820
Short name T236
Test name
Test status
Simulation time 359889294 ps
CPU time 0.84 seconds
Started Jun 09 12:35:25 PM PDT 24
Finished Jun 09 12:35:27 PM PDT 24
Peak memory 191768 kb
Host smart-f07581d6-bab9-4cad-9e5c-c9bba65c7c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601965820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.601965820
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3888613999
Short name T226
Test name
Test status
Simulation time 50307097416 ps
CPU time 85.19 seconds
Started Jun 09 12:35:27 PM PDT 24
Finished Jun 09 12:36:52 PM PDT 24
Peak memory 191808 kb
Host smart-c60b6964-dcf6-4dbb-b429-aba692664426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888613999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3888613999
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.839860667
Short name T206
Test name
Test status
Simulation time 526728665 ps
CPU time 1.47 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:35:03 PM PDT 24
Peak memory 191788 kb
Host smart-467a4db3-e39a-41c8-a7ef-14b2a315fbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839860667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.839860667
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.4020101069
Short name T244
Test name
Test status
Simulation time 21718281476 ps
CPU time 32.37 seconds
Started Jun 09 12:35:33 PM PDT 24
Finished Jun 09 12:36:06 PM PDT 24
Peak memory 191920 kb
Host smart-4cbf1081-689c-44be-941c-955e8f45232e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020101069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.4020101069
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2769001227
Short name T246
Test name
Test status
Simulation time 533944279 ps
CPU time 1.05 seconds
Started Jun 09 12:35:01 PM PDT 24
Finished Jun 09 12:35:02 PM PDT 24
Peak memory 196564 kb
Host smart-e0b9d2cb-a8cf-4680-92bb-f1efcc2ed6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769001227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2769001227
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3807144155
Short name T217
Test name
Test status
Simulation time 35584784412 ps
CPU time 24.73 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:35:23 PM PDT 24
Peak memory 191892 kb
Host smart-ee13a246-e1d4-4e3e-96d6-c6c4ec0b84c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807144155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3807144155
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3219127821
Short name T210
Test name
Test status
Simulation time 477586440 ps
CPU time 0.77 seconds
Started Jun 09 12:35:14 PM PDT 24
Finished Jun 09 12:35:15 PM PDT 24
Peak memory 191732 kb
Host smart-eff0e68b-e5b8-4f1f-a2be-9a968677aa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219127821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3219127821
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.479680148
Short name T214
Test name
Test status
Simulation time 17629452243 ps
CPU time 6.1 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:11 PM PDT 24
Peak memory 191912 kb
Host smart-86a9fc4e-3f2c-4cf3-bb9c-c6712594cfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479680148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.479680148
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3713478196
Short name T19
Test name
Test status
Simulation time 3943090901 ps
CPU time 2.24 seconds
Started Jun 09 12:35:03 PM PDT 24
Finished Jun 09 12:35:06 PM PDT 24
Peak memory 215456 kb
Host smart-6c3ccf8a-4bd5-44bb-8c75-6e97e57fdd03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713478196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3713478196
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.497787074
Short name T266
Test name
Test status
Simulation time 400252715 ps
CPU time 0.86 seconds
Started Jun 09 12:34:50 PM PDT 24
Finished Jun 09 12:34:52 PM PDT 24
Peak memory 191764 kb
Host smart-9790fd8b-9aa7-4114-98b7-717fd02e80e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497787074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.497787074
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.945550972
Short name T213
Test name
Test status
Simulation time 59797747123 ps
CPU time 45.23 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:35:44 PM PDT 24
Peak memory 191896 kb
Host smart-e75928aa-2aa4-4146-bae4-8fdeaa6079fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945550972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.945550972
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.890574098
Short name T25
Test name
Test status
Simulation time 356121886 ps
CPU time 1.09 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:06 PM PDT 24
Peak memory 191712 kb
Host smart-7da182e7-b4b9-4db5-92d5-585394811303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890574098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.890574098
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3951035551
Short name T222
Test name
Test status
Simulation time 57432178923 ps
CPU time 20.68 seconds
Started Jun 09 12:35:27 PM PDT 24
Finished Jun 09 12:35:48 PM PDT 24
Peak memory 191868 kb
Host smart-38cb2803-0187-4bdb-833a-1a163a13c9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951035551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3951035551
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1942868796
Short name T278
Test name
Test status
Simulation time 391896762 ps
CPU time 1.21 seconds
Started Jun 09 12:35:07 PM PDT 24
Finished Jun 09 12:35:09 PM PDT 24
Peak memory 191756 kb
Host smart-9c50fff9-ddb1-40c2-8912-9a785b0f79f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942868796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1942868796
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1110862609
Short name T209
Test name
Test status
Simulation time 24697017872 ps
CPU time 9.47 seconds
Started Jun 09 12:35:28 PM PDT 24
Finished Jun 09 12:35:38 PM PDT 24
Peak memory 191892 kb
Host smart-26572055-a3cc-453a-95f8-4f89dac2b902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110862609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1110862609
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3991208957
Short name T65
Test name
Test status
Simulation time 493261771 ps
CPU time 0.67 seconds
Started Jun 09 12:35:18 PM PDT 24
Finished Jun 09 12:35:19 PM PDT 24
Peak memory 196540 kb
Host smart-1db53bda-7058-4f2a-9746-4d3cbbbf0379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991208957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3991208957
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3658919333
Short name T62
Test name
Test status
Simulation time 21767222550 ps
CPU time 17.18 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:35:23 PM PDT 24
Peak memory 191852 kb
Host smart-39dd89c6-ff78-4270-b1a1-69dc4a43ea3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658919333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3658919333
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1664608845
Short name T265
Test name
Test status
Simulation time 609869043 ps
CPU time 0.8 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:35:07 PM PDT 24
Peak memory 191672 kb
Host smart-5cfadb53-94e7-4c30-b4cd-e2418c341db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664608845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1664608845
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2779866396
Short name T102
Test name
Test status
Simulation time 33442788163 ps
CPU time 45.55 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:35:42 PM PDT 24
Peak memory 191896 kb
Host smart-865f62d7-31de-4db4-8ff5-f401830edbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779866396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2779866396
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.517240785
Short name T270
Test name
Test status
Simulation time 410033889 ps
CPU time 0.85 seconds
Started Jun 09 12:35:33 PM PDT 24
Finished Jun 09 12:35:34 PM PDT 24
Peak memory 191744 kb
Host smart-90c7b5b1-e0ff-4289-9616-5b3f12ad118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517240785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.517240785
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1738472992
Short name T20
Test name
Test status
Simulation time 1737257742 ps
CPU time 1.12 seconds
Started Jun 09 12:34:54 PM PDT 24
Finished Jun 09 12:34:55 PM PDT 24
Peak memory 191732 kb
Host smart-3a5763fa-4fdd-46be-b119-1d5fe9edfff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738472992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1738472992
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1588708202
Short name T229
Test name
Test status
Simulation time 588941028 ps
CPU time 0.8 seconds
Started Jun 09 12:35:16 PM PDT 24
Finished Jun 09 12:35:17 PM PDT 24
Peak memory 191744 kb
Host smart-0f7bfae2-5e31-47df-888c-0f5bdd4df19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588708202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1588708202
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2103292463
Short name T204
Test name
Test status
Simulation time 30135176913 ps
CPU time 45.95 seconds
Started Jun 09 12:35:33 PM PDT 24
Finished Jun 09 12:36:19 PM PDT 24
Peak memory 191808 kb
Host smart-5998cfb8-7bc1-4047-bcf3-f1c15ba4ceac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103292463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2103292463
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2697112790
Short name T232
Test name
Test status
Simulation time 603875946 ps
CPU time 0.98 seconds
Started Jun 09 12:35:35 PM PDT 24
Finished Jun 09 12:35:36 PM PDT 24
Peak memory 191668 kb
Host smart-83279ef0-7908-406e-96bc-15162ab9c965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697112790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2697112790
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2103902520
Short name T260
Test name
Test status
Simulation time 35326502347 ps
CPU time 19.06 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:24 PM PDT 24
Peak memory 191896 kb
Host smart-b7a83275-19a9-43e3-8540-ffa38e3b41a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103902520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2103902520
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.688758991
Short name T220
Test name
Test status
Simulation time 616240106 ps
CPU time 1.59 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:07 PM PDT 24
Peak memory 191516 kb
Host smart-319b8d95-ce97-424c-bbcd-5dc94ac7a724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688758991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.688758991
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3786995068
Short name T228
Test name
Test status
Simulation time 146524416280 ps
CPU time 61.26 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:36:08 PM PDT 24
Peak memory 198216 kb
Host smart-2ad8939e-7091-4190-90c5-0b6e9101adae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786995068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3786995068
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.344635685
Short name T43
Test name
Test status
Simulation time 33560644733 ps
CPU time 55.05 seconds
Started Jun 09 12:34:59 PM PDT 24
Finished Jun 09 12:35:55 PM PDT 24
Peak memory 191892 kb
Host smart-2320beaf-927c-433d-9c33-799804a9560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344635685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.344635685
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3823724030
Short name T202
Test name
Test status
Simulation time 597547144 ps
CPU time 0.77 seconds
Started Jun 09 12:34:57 PM PDT 24
Finished Jun 09 12:34:59 PM PDT 24
Peak memory 191772 kb
Host smart-19aca1d6-237e-4bbc-80a5-c6ffe057f48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823724030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3823724030
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.4025419317
Short name T243
Test name
Test status
Simulation time 36216870258 ps
CPU time 12.3 seconds
Started Jun 09 12:35:01 PM PDT 24
Finished Jun 09 12:35:14 PM PDT 24
Peak memory 191920 kb
Host smart-fd5abe2c-e142-482e-9199-50f1c72459db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025419317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.4025419317
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2705938706
Short name T203
Test name
Test status
Simulation time 406289840 ps
CPU time 0.74 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:35:00 PM PDT 24
Peak memory 196564 kb
Host smart-98f90219-15fe-49e0-b51d-96074ffdaa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705938706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2705938706
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2133786336
Short name T280
Test name
Test status
Simulation time 22297794551 ps
CPU time 36.03 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:35:32 PM PDT 24
Peak memory 191848 kb
Host smart-5bf1f6d8-815d-4ba8-a1c6-16d386fe953d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133786336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2133786336
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3823190555
Short name T16
Test name
Test status
Simulation time 4082996019 ps
CPU time 2.34 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:34:59 PM PDT 24
Peak memory 215472 kb
Host smart-4baf2cb5-c924-4548-9783-8b5bc7fb2dbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823190555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3823190555
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1215720187
Short name T215
Test name
Test status
Simulation time 519758770 ps
CPU time 1.39 seconds
Started Jun 09 12:34:56 PM PDT 24
Finished Jun 09 12:34:58 PM PDT 24
Peak memory 196616 kb
Host smart-eac1564f-a399-497f-8874-488b82eca795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215720187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1215720187
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1350560832
Short name T191
Test name
Test status
Simulation time 402531968 ps
CPU time 1.31 seconds
Started Jun 09 12:35:03 PM PDT 24
Finished Jun 09 12:35:05 PM PDT 24
Peak memory 196540 kb
Host smart-1e9b418a-b831-4ee7-812e-f2c77d6ba846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350560832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1350560832
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3309864189
Short name T230
Test name
Test status
Simulation time 7550386886 ps
CPU time 6.64 seconds
Started Jun 09 12:35:17 PM PDT 24
Finished Jun 09 12:35:24 PM PDT 24
Peak memory 191912 kb
Host smart-bee0c47f-b1d6-4e9b-8a0e-abe7c73a4aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309864189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3309864189
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1980736002
Short name T207
Test name
Test status
Simulation time 553466027 ps
CPU time 1.03 seconds
Started Jun 09 12:35:07 PM PDT 24
Finished Jun 09 12:35:09 PM PDT 24
Peak memory 191752 kb
Host smart-645036fb-1a41-46d3-b0ca-3a6e8a1553bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980736002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1980736002
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3900910980
Short name T237
Test name
Test status
Simulation time 16159662855 ps
CPU time 21.6 seconds
Started Jun 09 12:35:02 PM PDT 24
Finished Jun 09 12:35:24 PM PDT 24
Peak memory 191896 kb
Host smart-6fa49424-cfd9-41df-821a-62f92da6295d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900910980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3900910980
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.617223071
Short name T268
Test name
Test status
Simulation time 558924108 ps
CPU time 1.51 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:35:09 PM PDT 24
Peak memory 196560 kb
Host smart-047e3738-5d03-4d56-bf0e-8d1e005d0e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617223071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.617223071
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3517583818
Short name T267
Test name
Test status
Simulation time 36429082898 ps
CPU time 13.26 seconds
Started Jun 09 12:35:02 PM PDT 24
Finished Jun 09 12:35:16 PM PDT 24
Peak memory 191824 kb
Host smart-062d43fa-3054-46fe-9d58-d9f70fa98227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517583818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3517583818
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.4027185883
Short name T261
Test name
Test status
Simulation time 425279693 ps
CPU time 1.31 seconds
Started Jun 09 12:35:28 PM PDT 24
Finished Jun 09 12:35:30 PM PDT 24
Peak memory 191756 kb
Host smart-faa4cae1-9358-4cbd-adcb-dd51225914e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027185883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.4027185883
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3852751007
Short name T46
Test name
Test status
Simulation time 34063901950 ps
CPU time 27.07 seconds
Started Jun 09 12:35:01 PM PDT 24
Finished Jun 09 12:35:28 PM PDT 24
Peak memory 191892 kb
Host smart-48f8ac03-129b-4970-80bc-6603e81f5cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852751007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3852751007
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2678615778
Short name T262
Test name
Test status
Simulation time 348591609 ps
CPU time 1.15 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:34:58 PM PDT 24
Peak memory 191752 kb
Host smart-425f6c21-e559-4c3d-b23d-8a26da61afe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678615778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2678615778
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.891560378
Short name T248
Test name
Test status
Simulation time 24404807987 ps
CPU time 8.44 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:35:16 PM PDT 24
Peak memory 191904 kb
Host smart-d6c19ce8-43a4-44a3-8f19-8196a7af13dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891560378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.891560378
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3078953775
Short name T251
Test name
Test status
Simulation time 565783825 ps
CPU time 1.06 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:35:08 PM PDT 24
Peak memory 196532 kb
Host smart-19b98bfe-544b-4e10-a941-4154b9fb3e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078953775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3078953775
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1426265664
Short name T13
Test name
Test status
Simulation time 17891846281 ps
CPU time 15.23 seconds
Started Jun 09 12:35:01 PM PDT 24
Finished Jun 09 12:35:17 PM PDT 24
Peak memory 191924 kb
Host smart-b1d59678-ac67-4818-ac2c-03528661f7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426265664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1426265664
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2320799520
Short name T259
Test name
Test status
Simulation time 643128446 ps
CPU time 0.59 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:35:00 PM PDT 24
Peak memory 191780 kb
Host smart-026d3859-e165-4d2d-87eb-c0868d014971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320799520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2320799520
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3548075649
Short name T22
Test name
Test status
Simulation time 43129515824 ps
CPU time 31.93 seconds
Started Jun 09 12:35:04 PM PDT 24
Finished Jun 09 12:35:37 PM PDT 24
Peak memory 191904 kb
Host smart-27cb2676-6e04-4998-863a-16e245e20308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548075649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3548075649
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.95317768
Short name T98
Test name
Test status
Simulation time 475914406 ps
CPU time 0.91 seconds
Started Jun 09 12:34:59 PM PDT 24
Finished Jun 09 12:35:01 PM PDT 24
Peak memory 191788 kb
Host smart-b4d82339-7632-448e-9913-24f35568c0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95317768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.95317768
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.186281484
Short name T271
Test name
Test status
Simulation time 12767801632 ps
CPU time 5.61 seconds
Started Jun 09 12:35:08 PM PDT 24
Finished Jun 09 12:35:14 PM PDT 24
Peak memory 191832 kb
Host smart-e77b2d07-1cb3-4a36-908f-ea92454b7662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186281484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.186281484
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.509995645
Short name T223
Test name
Test status
Simulation time 370438156 ps
CPU time 1.06 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:35:07 PM PDT 24
Peak memory 191688 kb
Host smart-c8d0cadb-0803-4c47-be0f-0cf8f92726da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509995645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.509995645
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.969480550
Short name T225
Test name
Test status
Simulation time 1773884578 ps
CPU time 3.3 seconds
Started Jun 09 12:35:03 PM PDT 24
Finished Jun 09 12:35:07 PM PDT 24
Peak memory 191772 kb
Host smart-7c93a420-dbcb-4725-be5a-7d9695341839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969480550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.969480550
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2588365195
Short name T238
Test name
Test status
Simulation time 367885557 ps
CPU time 0.7 seconds
Started Jun 09 12:35:02 PM PDT 24
Finished Jun 09 12:35:03 PM PDT 24
Peak memory 191784 kb
Host smart-7ed1a72a-ae9b-46c3-a9f5-2c79824ef949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588365195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2588365195
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.253711728
Short name T257
Test name
Test status
Simulation time 38233361027 ps
CPU time 58.66 seconds
Started Jun 09 12:35:20 PM PDT 24
Finished Jun 09 12:36:19 PM PDT 24
Peak memory 191888 kb
Host smart-980fb34a-1e78-4a13-869a-10063d765060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253711728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.253711728
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3021290227
Short name T281
Test name
Test status
Simulation time 494823856 ps
CPU time 0.75 seconds
Started Jun 09 12:34:59 PM PDT 24
Finished Jun 09 12:35:00 PM PDT 24
Peak memory 191776 kb
Host smart-a183770b-d029-4fda-b4b9-23df5037a97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021290227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3021290227
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.4256718471
Short name T241
Test name
Test status
Simulation time 18032204817 ps
CPU time 26.77 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:35:26 PM PDT 24
Peak memory 191876 kb
Host smart-952ad469-1ccc-4463-a5f8-ac1f65f7db07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256718471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4256718471
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3028180268
Short name T272
Test name
Test status
Simulation time 460791017 ps
CPU time 1.23 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:35:08 PM PDT 24
Peak memory 191764 kb
Host smart-557cef6c-6d6b-4f26-a85f-97ea24f96c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028180268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3028180268
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2522388286
Short name T239
Test name
Test status
Simulation time 25761150001 ps
CPU time 42.97 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:35:49 PM PDT 24
Peak memory 191920 kb
Host smart-5f0276b7-746b-4c14-903e-f75cbbae4b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522388286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2522388286
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.157196595
Short name T201
Test name
Test status
Simulation time 641389440 ps
CPU time 0.69 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:35:08 PM PDT 24
Peak memory 191768 kb
Host smart-03da7344-bf0c-47f2-b583-4c956973dcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157196595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.157196595
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3941599195
Short name T221
Test name
Test status
Simulation time 5401396625 ps
CPU time 2.71 seconds
Started Jun 09 12:35:06 PM PDT 24
Finished Jun 09 12:35:10 PM PDT 24
Peak memory 191884 kb
Host smart-4e740696-ec19-4010-8850-0f4545fda2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941599195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3941599195
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.4045800937
Short name T275
Test name
Test status
Simulation time 545915646 ps
CPU time 1.39 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:35:08 PM PDT 24
Peak memory 191764 kb
Host smart-13af2695-b573-4e8c-8de0-a1d62e3c8bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045800937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.4045800937
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2917284788
Short name T170
Test name
Test status
Simulation time 545080150 ps
CPU time 0.84 seconds
Started Jun 09 12:34:58 PM PDT 24
Finished Jun 09 12:35:00 PM PDT 24
Peak memory 196672 kb
Host smart-817d29cc-404f-48f9-b270-55dfd8598886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917284788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2917284788
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.403417647
Short name T23
Test name
Test status
Simulation time 56763590175 ps
CPU time 21.99 seconds
Started Jun 09 12:35:10 PM PDT 24
Finished Jun 09 12:35:36 PM PDT 24
Peak memory 191892 kb
Host smart-344bec69-825c-4713-ac2a-9ad2d328a4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403417647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.403417647
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1230762514
Short name T100
Test name
Test status
Simulation time 624323240 ps
CPU time 0.81 seconds
Started Jun 09 12:35:03 PM PDT 24
Finished Jun 09 12:35:04 PM PDT 24
Peak memory 191764 kb
Host smart-617f7b29-656d-436b-857e-95bc5c2679d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230762514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1230762514
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2366203740
Short name T231
Test name
Test status
Simulation time 5281802024 ps
CPU time 8.54 seconds
Started Jun 09 12:34:55 PM PDT 24
Finished Jun 09 12:35:04 PM PDT 24
Peak memory 191876 kb
Host smart-0775a4b1-37ae-4ccc-ac01-63cbac143079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366203740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2366203740
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3868228717
Short name T249
Test name
Test status
Simulation time 612579044 ps
CPU time 0.64 seconds
Started Jun 09 12:35:05 PM PDT 24
Finished Jun 09 12:35:07 PM PDT 24
Peak memory 191772 kb
Host smart-d5822249-ab7a-4571-a868-2ca01b74c9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868228717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3868228717
Directory /workspace/9.aon_timer_smoke/latest
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