Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	0	34	100.00	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	31562	1		T1	12		T3	11		T4	522
bark[1]	575	1		T6	21		T7	21		T9	21
bark[2]	359	1		T26	21		T16	130		T93	21
bark[3]	247	1		T151	21		T99	21		T89	35
bark[4]	339	1		T8	21		T16	21		T39	89
bark[5]	712	1		T25	67		T27	42		T16	7
bark[6]	374	1		T24	21		T16	21		T36	21
bark[7]	133	1		T45	14		T138	91		T82	7
bark[8]	529	1		T22	14		T16	21		T39	21
bark[9]	373	1		T24	21		T25	52		T26	30
bark[10]	432	1		T5	32		T25	21		T168	14
bark[11]	534	1		T8	56		T27	21		T33	104
bark[12]	869	1		T2	14		T26	42		T35	221
bark[13]	266	1		T9	21		T25	39		T15	68
bark[14]	829	1		T5	42		T35	86		T120	51
bark[15]	736	1		T5	21		T8	42		T15	236
bark[16]	655	1		T6	21		T96	21		T40	14
bark[17]	690	1		T6	42		T38	320		T89	130
bark[18]	372	1		T9	80		T24	14		T42	26
bark[19]	237	1		T103	21		T88	21		T42	26
bark[20]	178	1		T27	21		T33	5		T34	7
bark[21]	874	1		T16	21		T79	21		T39	21
bark[22]	1015	1		T7	42		T26	21		T15	21
bark[23]	1040	1		T9	21		T40	70		T182	32
bark[24]	317	1		T6	30		T7	35		T96	19
bark[25]	491	1		T7	48		T26	14		T15	21
bark[26]	1009	1		T100	14		T27	21		T15	275
bark[27]	499	1		T14	14		T35	237		T37	26
bark[28]	386	1		T179	14		T178	14		T89	198
bark[29]	356	1		T112	21		T88	21		T124	82
bark[30]	263	1		T9	21		T16	60		T148	21
bark[31]	225	1		T5	21		T24	40		T77	14
bark_0	4510	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	30601	1		T1	11		T3	10		T4	517
bite[1]	442	1		T25	39		T112	21		T126	53
bite[2]	465	1		T6	42		T25	21		T16	6
bite[3]	698	1		T8	56		T96	21		T26	13
bite[4]	1152	1		T100	13		T15	224		T88	223
bite[5]	253	1		T8	21		T9	80		T24	21
bite[6]	262	1		T40	21		T79	21		T138	90
bite[7]	679	1		T27	21		T16	21		T103	35
bite[8]	711	1		T7	21		T15	21		T35	246
bite[9]	730	1		T6	21		T7	35		T9	21
bite[10]	635	1		T6	30		T40	70		T27	21
bite[11]	547	1		T7	42		T22	13		T14	13
bite[12]	175	1		T26	21		T35	4		T93	21
bite[13]	386	1		T24	53		T79	21		T182	51
bite[14]	653	1		T15	67		T103	21		T38	319
bite[15]	335	1		T16	21		T35	6		T120	21
bite[16]	444	1		T8	21		T16	108		T34	236
bite[17]	785	1		T5	42		T16	21		T35	236
bite[18]	313	1		T7	48		T42	26		T98	56
bite[19]	617	1		T9	42		T179	13		T123	30
bite[20]	198	1		T33	4		T46	46		T101	49
bite[21]	363	1		T26	21		T34	6		T80	13
bite[22]	877	1		T5	21		T9	21		T96	18
bite[23]	304	1		T78	13		T39	134		T110	21
bite[24]	459	1		T37	85		T47	13		T127	87
bite[25]	305	1		T77	13		T164	60		T89	183
bite[26]	692	1		T2	13		T5	31		T27	21
bite[27]	477	1		T16	30		T112	21		T146	21
bite[28]	397	1		T8	21		T15	21		T16	21
bite[29]	524	1		T27	21		T15	274		T112	21
bite[30]	660	1		T6	21		T15	235		T16	39
bite[31]	870	1		T5	21		T25	67		T120	30
bite_0	4977	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	51986	1		T1	19		T2	21		T3	18

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	0	34	100.00

User Defined Bins for prescale_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale_max	88	1		T112	88		-	-		-	-
prescale[0]	1538	1		T4	60		T96	19		T15	37
prescale[1]	1262	1		T8	40		T16	182		T103	19
prescale[2]	834	1		T6	24		T27	19		T16	58
prescale[3]	1315	1		T6	9		T15	19		T16	63
prescale[4]	993	1		T25	40		T40	23		T27	19
prescale[5]	738	1		T15	55		T16	41		T33	65
prescale[6]	729	1		T96	24		T16	193		T36	2
prescale[7]	746	1		T148	19		T88	198		T123	40
prescale[8]	825	1		T9	58		T25	46		T15	40
prescale[9]	961	1		T4	19		T192	9		T40	19
prescale[10]	1002	1		T6	23		T24	37		T36	147
prescale[11]	1319	1		T5	41		T24	23		T40	45
prescale[12]	838	1		T4	116		T193	9		T96	19
prescale[13]	601	1		T4	45		T96	40		T16	2
prescale[14]	517	1		T6	37		T24	19		T148	9
prescale[15]	434	1		T4	9		T9	9		T35	51
prescale[16]	752	1		T4	2		T40	47		T26	19
prescale[17]	459	1		T4	2		T24	19		T15	51
prescale[18]	541	1		T15	51		T93	9		T38	19
prescale[19]	1013	1		T4	19		T9	19		T40	19
prescale[20]	906	1		T96	19		T26	23		T15	19
prescale[21]	371	1		T4	19		T27	28		T34	19
prescale[22]	770	1		T1	9		T27	19		T15	19
prescale[23]	854	1		T96	19		T27	65		T33	44
prescale[24]	468	1		T13	9		T194	9		T15	40
prescale[25]	1171	1		T5	19		T6	19		T41	9
prescale[26]	931	1		T7	19		T15	20		T34	112
prescale[27]	710	1		T25	23		T40	28		T34	78
prescale[28]	675	1		T12	9		T24	29		T96	32
prescale[29]	1040	1		T9	23		T15	204		T34	19
prescale[30]	504	1		T24	42		T26	19		T112	19
prescale[31]	813	1		T5	44		T9	59		T34	40
prescale_0	25356	1		T1	10		T2	21		T3	18

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	39142	1		T1	9		T2	21		T3	18
auto[1]	12844	1		T1	10		T4	72		T5	78

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	51986	1		T1	19		T2	21		T3	18

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30351	1		T1	14		T2	1		T3	13
wkup[1]	177	1		T8	21		T35	21		T39	21
wkup[2]	245	1		T5	21		T40	21		T16	21
wkup[3]	270	1		T2	15		T7	21		T35	6
wkup[4]	322	1		T6	21		T7	35		T15	21
wkup[5]	266	1		T25	42		T36	21		T38	21
wkup[6]	251	1		T35	30		T36	21		T38	8
wkup[7]	150	1		T152	21		T101	21		T106	21
wkup[8]	226	1		T7	21		T25	26		T27	21
wkup[9]	216	1		T4	21		T16	21		T33	6
wkup[10]	222	1		T16	21		T148	21		T182	21
wkup[11]	242	1		T179	15		T35	21		T37	21
wkup[12]	263	1		T7	21		T96	21		T15	21
wkup[13]	271	1		T5	21		T40	21		T39	21
wkup[14]	279	1		T15	21		T16	30		T33	21
wkup[15]	438	1		T34	21		T35	50		T36	21
wkup[16]	277	1		T16	8		T36	24		T37	42
wkup[17]	378	1		T8	35		T15	21		T16	21
wkup[18]	235	1		T15	21		T89	21		T122	21
wkup[19]	263	1		T6	21		T25	21		T168	15
wkup[20]	187	1		T39	21		T124	21		T42	77
wkup[21]	243	1		T9	21		T24	21		T40	15
wkup[22]	313	1		T8	21		T40	21		T15	21
wkup[23]	286	1		T4	21		T15	21		T39	47
wkup[24]	423	1		T40	21		T36	21		T79	30
wkup[25]	345	1		T34	21		T103	35		T78	15
wkup[26]	214	1		T35	8		T88	42		T42	21
wkup[27]	203	1		T111	21		T101	21		T106	26
wkup[28]	334	1		T15	42		T34	21		T38	21
wkup[29]	254	1		T4	42		T35	26		T39	21
wkup[30]	261	1		T35	30		T126	26		T42	38
wkup[31]	223	1		T38	21		T39	30		T126	21
wkup[32]	198	1		T4	21		T14	15		T24	21
wkup[33]	399	1		T9	21		T33	42		T120	30
wkup[34]	337	1		T27	21		T15	36		T36	56
wkup[35]	360	1		T4	21		T15	21		T103	15
wkup[36]	355	1		T6	30		T26	21		T15	21
wkup[37]	264	1		T26	30		T15	30		T16	42
wkup[38]	306	1		T15	21		T34	8		T38	21
wkup[39]	281	1		T22	15		T16	47		T33	21
wkup[40]	566	1		T5	21		T96	20		T26	21
wkup[41]	204	1		T15	21		T39	21		T126	15
wkup[42]	245	1		T6	21		T26	15		T27	21
wkup[43]	434	1		T8	21		T25	21		T15	42
wkup[44]	237	1		T182	30		T158	8		T138	21
wkup[45]	188	1		T16	39		T35	20		T117	15
wkup[46]	326	1		T27	21		T15	21		T33	26
wkup[47]	377	1		T9	21		T24	15		T35	26
wkup[48]	350	1		T25	26		T15	21		T16	21
wkup[49]	289	1		T4	8		T5	21		T34	15
wkup[50]	389	1		T4	26		T8	42		T9	21
wkup[51]	385	1		T96	21		T112	21		T36	26
wkup[52]	309	1		T27	21		T35	21		T38	44
wkup[53]	281	1		T7	30		T15	21		T16	21
wkup[54]	201	1		T9	21		T16	30		T38	21
wkup[55]	293	1		T33	21		T93	21		T38	21
wkup[56]	270	1		T5	21		T24	21		T34	21
wkup[57]	305	1		T26	21		T16	21		T36	21
wkup[58]	363	1		T5	21		T15	21		T35	26
wkup[59]	254	1		T15	21		T35	21		T112	21
wkup[60]	182	1		T9	21		T33	8		T39	21
wkup[61]	215	1		T99	21		T164	21		T89	15
wkup[62]	371	1		T6	21		T34	15		T112	21
wkup[63]	315	1		T15	35		T16	21		T34	21
wkup_0	3509	1		T1	5		T2	5		T3	5