Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.08 99.33 93.67 100.00 98.40 99.51 49.57


Total test records in report: 418
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T280 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.594003401 Jun 10 06:31:32 PM PDT 24 Jun 10 06:31:33 PM PDT 24 480202257 ps
T281 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3845278731 Jun 10 06:32:50 PM PDT 24 Jun 10 06:32:51 PM PDT 24 451062746 ps
T282 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3364925617 Jun 10 06:32:52 PM PDT 24 Jun 10 06:32:53 PM PDT 24 464387832 ps
T283 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.366192479 Jun 10 06:32:47 PM PDT 24 Jun 10 06:32:48 PM PDT 24 415245704 ps
T284 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1490474164 Jun 10 06:32:54 PM PDT 24 Jun 10 06:32:56 PM PDT 24 499479262 ps
T68 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.935760094 Jun 10 06:32:33 PM PDT 24 Jun 10 06:32:38 PM PDT 24 2113157817 ps
T285 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4276117456 Jun 10 06:31:42 PM PDT 24 Jun 10 06:31:43 PM PDT 24 318382308 ps
T69 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1086007646 Jun 10 06:32:37 PM PDT 24 Jun 10 06:32:38 PM PDT 24 304360655 ps
T70 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.167256953 Jun 10 06:32:32 PM PDT 24 Jun 10 06:32:33 PM PDT 24 445753656 ps
T71 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1352037282 Jun 10 06:32:21 PM PDT 24 Jun 10 06:32:24 PM PDT 24 1228999041 ps
T72 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4221281659 Jun 10 06:32:12 PM PDT 24 Jun 10 06:32:17 PM PDT 24 1218249516 ps
T31 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.138670774 Jun 10 06:32:20 PM PDT 24 Jun 10 06:32:22 PM PDT 24 4430344084 ps
T286 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1650378894 Jun 10 06:32:37 PM PDT 24 Jun 10 06:32:38 PM PDT 24 382959124 ps
T287 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2232000627 Jun 10 06:31:35 PM PDT 24 Jun 10 06:31:37 PM PDT 24 507936058 ps
T288 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3064682787 Jun 10 06:32:02 PM PDT 24 Jun 10 06:32:05 PM PDT 24 644565366 ps
T289 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1296456100 Jun 10 06:32:48 PM PDT 24 Jun 10 06:32:49 PM PDT 24 492055997 ps
T73 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2135381666 Jun 10 06:31:42 PM PDT 24 Jun 10 06:31:43 PM PDT 24 1676102186 ps
T53 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1570566887 Jun 10 06:31:48 PM PDT 24 Jun 10 06:31:49 PM PDT 24 405651147 ps
T74 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2303002063 Jun 10 06:32:30 PM PDT 24 Jun 10 06:32:32 PM PDT 24 500541471 ps
T290 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2357111401 Jun 10 06:31:35 PM PDT 24 Jun 10 06:31:37 PM PDT 24 492464404 ps
T291 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3262180782 Jun 10 06:31:41 PM PDT 24 Jun 10 06:31:42 PM PDT 24 340626042 ps
T186 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2333101806 Jun 10 06:32:14 PM PDT 24 Jun 10 06:32:19 PM PDT 24 4794700575 ps
T292 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1109507326 Jun 10 06:31:39 PM PDT 24 Jun 10 06:31:40 PM PDT 24 268097012 ps
T293 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1205922547 Jun 10 06:32:30 PM PDT 24 Jun 10 06:32:33 PM PDT 24 796151093 ps
T294 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.13134706 Jun 10 06:32:44 PM PDT 24 Jun 10 06:32:45 PM PDT 24 382543987 ps
T295 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3404513911 Jun 10 06:32:11 PM PDT 24 Jun 10 06:32:13 PM PDT 24 515771799 ps
T296 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3627360818 Jun 10 06:32:18 PM PDT 24 Jun 10 06:32:20 PM PDT 24 528071146 ps
T297 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3636173601 Jun 10 06:32:22 PM PDT 24 Jun 10 06:32:23 PM PDT 24 493821761 ps
T187 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2779017057 Jun 10 06:31:44 PM PDT 24 Jun 10 06:31:49 PM PDT 24 8296318859 ps
T188 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.334532259 Jun 10 06:31:34 PM PDT 24 Jun 10 06:31:38 PM PDT 24 8246965891 ps
T75 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3075829675 Jun 10 06:31:57 PM PDT 24 Jun 10 06:31:58 PM PDT 24 962287117 ps
T298 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2418447336 Jun 10 06:32:32 PM PDT 24 Jun 10 06:32:33 PM PDT 24 550635995 ps
T299 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1893924959 Jun 10 06:32:29 PM PDT 24 Jun 10 06:32:31 PM PDT 24 324263815 ps
T300 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2948583410 Jun 10 06:32:41 PM PDT 24 Jun 10 06:32:43 PM PDT 24 1511638133 ps
T301 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.617214982 Jun 10 06:32:28 PM PDT 24 Jun 10 06:32:29 PM PDT 24 497763567 ps
T302 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3677622239 Jun 10 06:32:50 PM PDT 24 Jun 10 06:32:51 PM PDT 24 512435330 ps
T303 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2017854393 Jun 10 06:32:28 PM PDT 24 Jun 10 06:32:31 PM PDT 24 2186269498 ps
T304 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4184467028 Jun 10 06:32:49 PM PDT 24 Jun 10 06:32:50 PM PDT 24 485068639 ps
T54 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2837541789 Jun 10 06:32:12 PM PDT 24 Jun 10 06:32:13 PM PDT 24 532896403 ps
T305 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1973619201 Jun 10 06:32:03 PM PDT 24 Jun 10 06:32:05 PM PDT 24 425068324 ps
T55 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.184381026 Jun 10 06:32:16 PM PDT 24 Jun 10 06:32:18 PM PDT 24 447636639 ps
T306 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3207278856 Jun 10 06:32:54 PM PDT 24 Jun 10 06:32:55 PM PDT 24 283321736 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3949383301 Jun 10 06:31:56 PM PDT 24 Jun 10 06:32:18 PM PDT 24 7934175483 ps
T307 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2841354796 Jun 10 06:32:30 PM PDT 24 Jun 10 06:32:33 PM PDT 24 4458377835 ps
T308 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3599924959 Jun 10 06:32:42 PM PDT 24 Jun 10 06:32:54 PM PDT 24 8101278513 ps
T309 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1995492417 Jun 10 06:31:46 PM PDT 24 Jun 10 06:31:47 PM PDT 24 535943419 ps
T310 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.509509887 Jun 10 06:32:24 PM PDT 24 Jun 10 06:32:39 PM PDT 24 8386656074 ps
T311 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3030515789 Jun 10 06:32:34 PM PDT 24 Jun 10 06:32:40 PM PDT 24 8373190155 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1973341861 Jun 10 06:31:45 PM PDT 24 Jun 10 06:31:46 PM PDT 24 387038703 ps
T312 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.571885686 Jun 10 06:32:25 PM PDT 24 Jun 10 06:32:27 PM PDT 24 623390247 ps
T313 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1923004330 Jun 10 06:31:56 PM PDT 24 Jun 10 06:31:57 PM PDT 24 457613618 ps
T314 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2956930186 Jun 10 06:32:29 PM PDT 24 Jun 10 06:32:37 PM PDT 24 4372550138 ps
T315 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.838802881 Jun 10 06:32:20 PM PDT 24 Jun 10 06:32:22 PM PDT 24 440541073 ps
T316 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.417622776 Jun 10 06:32:36 PM PDT 24 Jun 10 06:32:39 PM PDT 24 2564159361 ps
T317 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1079881477 Jun 10 06:32:17 PM PDT 24 Jun 10 06:32:18 PM PDT 24 393568823 ps
T318 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2232595927 Jun 10 06:32:13 PM PDT 24 Jun 10 06:32:15 PM PDT 24 547385792 ps
T319 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4063656614 Jun 10 06:32:50 PM PDT 24 Jun 10 06:32:51 PM PDT 24 453795232 ps
T320 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.4182706600 Jun 10 06:32:04 PM PDT 24 Jun 10 06:32:07 PM PDT 24 2640485971 ps
T321 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1360743857 Jun 10 06:32:14 PM PDT 24 Jun 10 06:32:15 PM PDT 24 453282830 ps
T58 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3477152593 Jun 10 06:32:40 PM PDT 24 Jun 10 06:32:41 PM PDT 24 490771842 ps
T322 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2009829889 Jun 10 06:32:46 PM PDT 24 Jun 10 06:32:48 PM PDT 24 418180003 ps
T323 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4155580277 Jun 10 06:32:22 PM PDT 24 Jun 10 06:32:23 PM PDT 24 364702554 ps
T324 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3470628112 Jun 10 06:32:26 PM PDT 24 Jun 10 06:32:27 PM PDT 24 509637814 ps
T325 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1007578220 Jun 10 06:32:17 PM PDT 24 Jun 10 06:32:21 PM PDT 24 2545537183 ps
T59 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1075802097 Jun 10 06:32:28 PM PDT 24 Jun 10 06:32:30 PM PDT 24 509758410 ps
T326 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3481466160 Jun 10 06:32:46 PM PDT 24 Jun 10 06:32:47 PM PDT 24 287022885 ps
T327 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.545909954 Jun 10 06:32:43 PM PDT 24 Jun 10 06:32:44 PM PDT 24 455566325 ps
T328 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.36948106 Jun 10 06:31:49 PM PDT 24 Jun 10 06:31:50 PM PDT 24 369385514 ps
T329 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1804182429 Jun 10 06:32:23 PM PDT 24 Jun 10 06:32:24 PM PDT 24 457286583 ps
T330 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1378886123 Jun 10 06:32:43 PM PDT 24 Jun 10 06:32:44 PM PDT 24 523826745 ps
T331 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3311490547 Jun 10 06:32:47 PM PDT 24 Jun 10 06:32:49 PM PDT 24 692499912 ps
T332 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1932452581 Jun 10 06:32:09 PM PDT 24 Jun 10 06:32:10 PM PDT 24 475288401 ps
T333 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1662803536 Jun 10 06:31:32 PM PDT 24 Jun 10 06:31:33 PM PDT 24 428152057 ps
T334 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2607046047 Jun 10 06:32:49 PM PDT 24 Jun 10 06:32:51 PM PDT 24 348476768 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.435624264 Jun 10 06:31:37 PM PDT 24 Jun 10 06:32:12 PM PDT 24 13752814195 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2419300148 Jun 10 06:31:43 PM PDT 24 Jun 10 06:31:46 PM PDT 24 1189029627 ps
T335 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3815956704 Jun 10 06:31:53 PM PDT 24 Jun 10 06:31:56 PM PDT 24 1114874552 ps
T336 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.117310531 Jun 10 06:32:32 PM PDT 24 Jun 10 06:32:34 PM PDT 24 1455812984 ps
T337 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2770747882 Jun 10 06:32:16 PM PDT 24 Jun 10 06:32:17 PM PDT 24 536445264 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1245000312 Jun 10 06:31:40 PM PDT 24 Jun 10 06:31:41 PM PDT 24 550369797 ps
T338 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3066947559 Jun 10 06:32:54 PM PDT 24 Jun 10 06:32:55 PM PDT 24 461219256 ps
T339 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3759471524 Jun 10 06:32:27 PM PDT 24 Jun 10 06:32:28 PM PDT 24 363679725 ps
T340 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1297118128 Jun 10 06:32:26 PM PDT 24 Jun 10 06:32:28 PM PDT 24 564908257 ps
T341 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.249131774 Jun 10 06:32:49 PM PDT 24 Jun 10 06:32:51 PM PDT 24 463957031 ps
T342 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2283299358 Jun 10 06:32:02 PM PDT 24 Jun 10 06:32:04 PM PDT 24 422729542 ps
T190 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1416987597 Jun 10 06:32:10 PM PDT 24 Jun 10 06:32:17 PM PDT 24 8511384383 ps
T343 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.118560930 Jun 10 06:32:54 PM PDT 24 Jun 10 06:32:55 PM PDT 24 474609882 ps
T344 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1692659428 Jun 10 06:31:42 PM PDT 24 Jun 10 06:31:45 PM PDT 24 7652112862 ps
T345 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2083811278 Jun 10 06:32:08 PM PDT 24 Jun 10 06:32:09 PM PDT 24 374325748 ps
T346 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1042723356 Jun 10 06:32:19 PM PDT 24 Jun 10 06:32:21 PM PDT 24 354581952 ps
T347 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2692833703 Jun 10 06:32:20 PM PDT 24 Jun 10 06:32:23 PM PDT 24 408067526 ps
T348 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.725780442 Jun 10 06:32:22 PM PDT 24 Jun 10 06:32:23 PM PDT 24 1174311514 ps
T349 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1023219133 Jun 10 06:31:48 PM PDT 24 Jun 10 06:31:49 PM PDT 24 733411322 ps
T350 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.425060877 Jun 10 06:32:00 PM PDT 24 Jun 10 06:32:05 PM PDT 24 8320398762 ps
T351 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.443073055 Jun 10 06:32:14 PM PDT 24 Jun 10 06:32:15 PM PDT 24 503645806 ps
T352 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.621820003 Jun 10 06:31:37 PM PDT 24 Jun 10 06:31:38 PM PDT 24 446726047 ps
T353 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.789364765 Jun 10 06:32:47 PM PDT 24 Jun 10 06:32:49 PM PDT 24 563020589 ps
T354 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3020642775 Jun 10 06:31:36 PM PDT 24 Jun 10 06:31:37 PM PDT 24 704756675 ps
T355 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.892692486 Jun 10 06:31:45 PM PDT 24 Jun 10 06:31:46 PM PDT 24 455772470 ps
T66 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1435730561 Jun 10 06:32:33 PM PDT 24 Jun 10 06:32:35 PM PDT 24 461546311 ps
T356 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4040123680 Jun 10 06:31:35 PM PDT 24 Jun 10 06:31:36 PM PDT 24 455191373 ps
T357 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2430361700 Jun 10 06:32:08 PM PDT 24 Jun 10 06:32:10 PM PDT 24 3044607154 ps
T358 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.16905748 Jun 10 06:32:29 PM PDT 24 Jun 10 06:32:30 PM PDT 24 398541393 ps
T359 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.514712488 Jun 10 06:32:55 PM PDT 24 Jun 10 06:32:57 PM PDT 24 411055084 ps
T360 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.216426403 Jun 10 06:32:49 PM PDT 24 Jun 10 06:32:50 PM PDT 24 303807165 ps
T361 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3914286909 Jun 10 06:31:52 PM PDT 24 Jun 10 06:31:53 PM PDT 24 491545327 ps
T362 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2475826883 Jun 10 06:31:54 PM PDT 24 Jun 10 06:31:55 PM PDT 24 434652190 ps
T363 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2538709257 Jun 10 06:31:59 PM PDT 24 Jun 10 06:32:00 PM PDT 24 421122493 ps
T60 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2511577589 Jun 10 06:32:16 PM PDT 24 Jun 10 06:32:17 PM PDT 24 408039046 ps
T364 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.57314401 Jun 10 06:32:20 PM PDT 24 Jun 10 06:32:21 PM PDT 24 454088064 ps
T365 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1136480092 Jun 10 06:32:35 PM PDT 24 Jun 10 06:32:36 PM PDT 24 686477622 ps
T366 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3674260999 Jun 10 06:31:40 PM PDT 24 Jun 10 06:31:42 PM PDT 24 348554401 ps
T367 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2906176223 Jun 10 06:32:52 PM PDT 24 Jun 10 06:32:53 PM PDT 24 340087836 ps
T368 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1692126492 Jun 10 06:31:53 PM PDT 24 Jun 10 06:31:54 PM PDT 24 430830030 ps
T369 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.392735088 Jun 10 06:31:54 PM PDT 24 Jun 10 06:31:58 PM PDT 24 4254394092 ps
T370 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.22543592 Jun 10 06:32:46 PM PDT 24 Jun 10 06:32:47 PM PDT 24 394525528 ps
T371 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2241557953 Jun 10 06:32:02 PM PDT 24 Jun 10 06:32:15 PM PDT 24 7924532321 ps
T372 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.668804145 Jun 10 06:31:37 PM PDT 24 Jun 10 06:31:38 PM PDT 24 399118148 ps
T373 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1420732822 Jun 10 06:32:54 PM PDT 24 Jun 10 06:32:56 PM PDT 24 490757759 ps
T374 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.955161218 Jun 10 06:31:44 PM PDT 24 Jun 10 06:31:45 PM PDT 24 565171069 ps
T61 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2086412353 Jun 10 06:31:42 PM PDT 24 Jun 10 06:31:45 PM PDT 24 3310284207 ps
T375 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2710437069 Jun 10 06:31:32 PM PDT 24 Jun 10 06:31:34 PM PDT 24 813958794 ps
T376 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3713547605 Jun 10 06:32:23 PM PDT 24 Jun 10 06:32:24 PM PDT 24 371003777 ps
T377 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3506107825 Jun 10 06:32:00 PM PDT 24 Jun 10 06:32:04 PM PDT 24 2835449301 ps
T378 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1815983989 Jun 10 06:32:14 PM PDT 24 Jun 10 06:32:17 PM PDT 24 751065743 ps
T379 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1230716602 Jun 10 06:32:27 PM PDT 24 Jun 10 06:32:29 PM PDT 24 1317914124 ps
T380 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1278488855 Jun 10 06:31:32 PM PDT 24 Jun 10 06:31:34 PM PDT 24 510586991 ps
T381 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1792888849 Jun 10 06:31:52 PM PDT 24 Jun 10 06:32:04 PM PDT 24 7293374134 ps
T382 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3528712860 Jun 10 06:32:08 PM PDT 24 Jun 10 06:32:10 PM PDT 24 410520798 ps
T383 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3645836860 Jun 10 06:32:40 PM PDT 24 Jun 10 06:32:41 PM PDT 24 397383215 ps
T384 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1037232585 Jun 10 06:32:37 PM PDT 24 Jun 10 06:32:51 PM PDT 24 7959139253 ps
T385 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1005033327 Jun 10 06:31:32 PM PDT 24 Jun 10 06:31:33 PM PDT 24 444289359 ps
T386 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1240111589 Jun 10 06:32:28 PM PDT 24 Jun 10 06:32:30 PM PDT 24 436145366 ps
T387 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2010283617 Jun 10 06:31:39 PM PDT 24 Jun 10 06:31:42 PM PDT 24 725085374 ps
T388 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2208348518 Jun 10 06:32:51 PM PDT 24 Jun 10 06:32:52 PM PDT 24 425248805 ps
T389 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3904052494 Jun 10 06:31:31 PM PDT 24 Jun 10 06:31:32 PM PDT 24 289721765 ps
T189 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3304973273 Jun 10 06:31:44 PM PDT 24 Jun 10 06:31:48 PM PDT 24 4072842114 ps
T390 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3876314620 Jun 10 06:32:45 PM PDT 24 Jun 10 06:32:46 PM PDT 24 506948423 ps
T391 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1535224949 Jun 10 06:32:30 PM PDT 24 Jun 10 06:32:44 PM PDT 24 7886713485 ps
T392 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1038478384 Jun 10 06:31:49 PM PDT 24 Jun 10 06:31:51 PM PDT 24 1228314410 ps
T393 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2269000930 Jun 10 06:31:55 PM PDT 24 Jun 10 06:31:56 PM PDT 24 319353929 ps
T394 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.779189172 Jun 10 06:32:24 PM PDT 24 Jun 10 06:32:26 PM PDT 24 422707435 ps
T395 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1445194528 Jun 10 06:32:54 PM PDT 24 Jun 10 06:32:56 PM PDT 24 374265979 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3940440247 Jun 10 06:31:45 PM PDT 24 Jun 10 06:31:47 PM PDT 24 2041258291 ps
T397 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2872037853 Jun 10 06:32:43 PM PDT 24 Jun 10 06:32:44 PM PDT 24 524103741 ps
T62 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1771430887 Jun 10 06:31:33 PM PDT 24 Jun 10 06:31:34 PM PDT 24 426423892 ps
T398 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.986684512 Jun 10 06:31:37 PM PDT 24 Jun 10 06:31:39 PM PDT 24 2014311894 ps
T399 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1459867587 Jun 10 06:32:17 PM PDT 24 Jun 10 06:32:24 PM PDT 24 2776448016 ps
T191 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2482391279 Jun 10 06:32:16 PM PDT 24 Jun 10 06:32:19 PM PDT 24 9368189986 ps
T400 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1268205927 Jun 10 06:31:53 PM PDT 24 Jun 10 06:31:55 PM PDT 24 549789080 ps
T401 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1604806283 Jun 10 06:32:03 PM PDT 24 Jun 10 06:32:04 PM PDT 24 415169806 ps
T402 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3719746500 Jun 10 06:31:47 PM PDT 24 Jun 10 06:31:49 PM PDT 24 562191482 ps
T403 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3288786923 Jun 10 06:31:57 PM PDT 24 Jun 10 06:31:58 PM PDT 24 414539251 ps
T404 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2755801028 Jun 10 06:32:03 PM PDT 24 Jun 10 06:32:04 PM PDT 24 458919466 ps
T405 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3695142063 Jun 10 06:31:54 PM PDT 24 Jun 10 06:31:55 PM PDT 24 536732270 ps
T406 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2699799789 Jun 10 06:31:36 PM PDT 24 Jun 10 06:31:37 PM PDT 24 483746470 ps
T407 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1245405121 Jun 10 06:32:33 PM PDT 24 Jun 10 06:32:35 PM PDT 24 464362977 ps
T408 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3426907379 Jun 10 06:32:48 PM PDT 24 Jun 10 06:32:49 PM PDT 24 316805480 ps
T409 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.186794085 Jun 10 06:32:58 PM PDT 24 Jun 10 06:32:59 PM PDT 24 440302331 ps
T410 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3216892151 Jun 10 06:31:35 PM PDT 24 Jun 10 06:31:37 PM PDT 24 543850793 ps
T411 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2756557632 Jun 10 06:32:37 PM PDT 24 Jun 10 06:32:40 PM PDT 24 359094109 ps
T412 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2591603890 Jun 10 06:32:30 PM PDT 24 Jun 10 06:32:31 PM PDT 24 1062456918 ps
T413 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1088061069 Jun 10 06:31:42 PM PDT 24 Jun 10 06:31:47 PM PDT 24 8163833600 ps
T414 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1756494436 Jun 10 06:32:09 PM PDT 24 Jun 10 06:32:10 PM PDT 24 492115882 ps
T415 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2318043885 Jun 10 06:32:29 PM PDT 24 Jun 10 06:32:31 PM PDT 24 564226324 ps
T416 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3008740173 Jun 10 06:32:33 PM PDT 24 Jun 10 06:32:34 PM PDT 24 511454373 ps
T417 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.848480588 Jun 10 06:31:53 PM PDT 24 Jun 10 06:31:55 PM PDT 24 486126234 ps
T418 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4123625277 Jun 10 06:32:53 PM PDT 24 Jun 10 06:32:55 PM PDT 24 266089469 ps

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2305421308
Short name T4
Test name
Test status
Simulation time 5023189856 ps
CPU time 28.5 seconds
Started Jun 10 06:31:27 PM PDT 24
Finished Jun 10 06:31:56 PM PDT 24
Peak memory 206892 kb
Host smart-2b20b0dc-091e-4c77-a140-92202b44a385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305421308 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2305421308
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.4171040905
Short name T5
Test name
Test status
Simulation time 359376093675 ps
CPU time 59.77 seconds
Started Jun 10 06:30:23 PM PDT 24
Finished Jun 10 06:31:24 PM PDT 24
Peak memory 192536 kb
Host smart-8cbb7558-6d27-42ad-a2f9-ff6fa16c9d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171040905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.4171040905
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3772314617
Short name T30
Test name
Test status
Simulation time 7784879588 ps
CPU time 7.45 seconds
Started Jun 10 06:32:11 PM PDT 24
Finished Jun 10 06:32:18 PM PDT 24
Peak memory 198076 kb
Host smart-b15f98fb-6ebf-43d5-a470-c503d10e0860
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772314617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3772314617
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3878408602
Short name T42
Test name
Test status
Simulation time 284588673960 ps
CPU time 474.44 seconds
Started Jun 10 06:29:10 PM PDT 24
Finished Jun 10 06:37:05 PM PDT 24
Peak memory 206828 kb
Host smart-1a90fa45-b95a-4caa-83eb-3c61c4390a89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878408602 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3878408602
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2532082343
Short name T16
Test name
Test status
Simulation time 188695433903 ps
CPU time 1031.32 seconds
Started Jun 10 06:30:47 PM PDT 24
Finished Jun 10 06:47:59 PM PDT 24
Peak memory 210596 kb
Host smart-c1b35ed8-0022-4328-be09-6afca2b8e743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532082343 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2532082343
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2859559755
Short name T39
Test name
Test status
Simulation time 170263661893 ps
CPU time 339.62 seconds
Started Jun 10 06:29:49 PM PDT 24
Finished Jun 10 06:35:29 PM PDT 24
Peak memory 206824 kb
Host smart-b0fa99e4-daa4-4f0f-8854-30462212633c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859559755 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2859559755
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3609890272
Short name T15
Test name
Test status
Simulation time 66465371978 ps
CPU time 351.82 seconds
Started Jun 10 06:29:52 PM PDT 24
Finished Jun 10 06:35:45 PM PDT 24
Peak memory 209120 kb
Host smart-fc3d3a1f-a576-4b2b-877e-6e959f26cd1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609890272 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3609890272
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2985254901
Short name T89
Test name
Test status
Simulation time 58952603086 ps
CPU time 437.32 seconds
Started Jun 10 06:31:08 PM PDT 24
Finished Jun 10 06:38:26 PM PDT 24
Peak memory 209076 kb
Host smart-7a0b94d4-71fb-4ad5-89ce-14f86e1505f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985254901 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2985254901
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.4034701528
Short name T90
Test name
Test status
Simulation time 213370637526 ps
CPU time 535.97 seconds
Started Jun 10 06:29:34 PM PDT 24
Finished Jun 10 06:38:30 PM PDT 24
Peak memory 206816 kb
Host smart-d66dbee5-3e68-447d-8007-3dbb92c9006d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034701528 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.4034701528
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.938990445
Short name T105
Test name
Test status
Simulation time 312506154990 ps
CPU time 505.63 seconds
Started Jun 10 06:30:11 PM PDT 24
Finished Jun 10 06:38:37 PM PDT 24
Peak memory 211824 kb
Host smart-da1c434d-5a39-42ee-8d91-5b9f406b8761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938990445 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.938990445
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3091090021
Short name T111
Test name
Test status
Simulation time 343473716312 ps
CPU time 669.54 seconds
Started Jun 10 06:29:39 PM PDT 24
Finished Jun 10 06:40:49 PM PDT 24
Peak memory 205732 kb
Host smart-e66881ae-7ee7-46f7-b0df-88cf02bc8bbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091090021 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3091090021
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.4145670190
Short name T17
Test name
Test status
Simulation time 4186157439 ps
CPU time 1.51 seconds
Started Jun 10 06:29:14 PM PDT 24
Finished Jun 10 06:29:16 PM PDT 24
Peak memory 215500 kb
Host smart-81034692-0dcd-4f6b-a901-1f0285f2c123
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145670190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4145670190
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2485532183
Short name T86
Test name
Test status
Simulation time 37120836038 ps
CPU time 221.93 seconds
Started Jun 10 06:29:18 PM PDT 24
Finished Jun 10 06:33:00 PM PDT 24
Peak memory 214868 kb
Host smart-a8b0e020-f484-4fe3-b4f6-4d9d0d525d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485532183 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2485532183
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2325734483
Short name T26
Test name
Test status
Simulation time 56204300996 ps
CPU time 94.37 seconds
Started Jun 10 06:30:49 PM PDT 24
Finished Jun 10 06:32:24 PM PDT 24
Peak memory 192856 kb
Host smart-1a893127-c3a3-4116-b4fd-a133c9af6fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325734483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2325734483
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1486759214
Short name T37
Test name
Test status
Simulation time 701842374625 ps
CPU time 188.94 seconds
Started Jun 10 06:30:38 PM PDT 24
Finished Jun 10 06:33:47 PM PDT 24
Peak memory 199556 kb
Host smart-794f364a-c9e4-4af2-b574-b09920a1b660
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486759214 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1486759214
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1638103599
Short name T141
Test name
Test status
Simulation time 243875174272 ps
CPU time 508.08 seconds
Started Jun 10 06:31:05 PM PDT 24
Finished Jun 10 06:39:34 PM PDT 24
Peak memory 214084 kb
Host smart-cb79db02-c6d8-4924-945c-998ad4145be2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638103599 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1638103599
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2667582446
Short name T87
Test name
Test status
Simulation time 159384928262 ps
CPU time 653.93 seconds
Started Jun 10 06:31:10 PM PDT 24
Finished Jun 10 06:42:05 PM PDT 24
Peak memory 206140 kb
Host smart-467d20db-dc99-4d62-8228-e0fe9a60946b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667582446 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2667582446
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3003447848
Short name T32
Test name
Test status
Simulation time 348020034 ps
CPU time 0.64 seconds
Started Jun 10 06:32:05 PM PDT 24
Finished Jun 10 06:32:06 PM PDT 24
Peak memory 192888 kb
Host smart-c2072a1e-df28-4ef3-853a-17190fedd182
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003447848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3003447848
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3015970016
Short name T98
Test name
Test status
Simulation time 111175377859 ps
CPU time 41.46 seconds
Started Jun 10 06:31:03 PM PDT 24
Finished Jun 10 06:31:44 PM PDT 24
Peak memory 193032 kb
Host smart-8b74c251-470b-4f70-ad44-9aee54bf9b89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015970016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3015970016
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.788145125
Short name T6
Test name
Test status
Simulation time 92998827742 ps
CPU time 120.87 seconds
Started Jun 10 06:31:32 PM PDT 24
Finished Jun 10 06:33:33 PM PDT 24
Peak memory 191876 kb
Host smart-0449fcb0-9ef6-445e-922a-db58c6920240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788145125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.788145125
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.348844603
Short name T101
Test name
Test status
Simulation time 60502900348 ps
CPU time 377.66 seconds
Started Jun 10 06:29:59 PM PDT 24
Finished Jun 10 06:36:17 PM PDT 24
Peak memory 208880 kb
Host smart-57300029-1d3b-4016-b825-6ebbe2754edf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348844603 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.348844603
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3865409258
Short name T79
Test name
Test status
Simulation time 286479438538 ps
CPU time 246.22 seconds
Started Jun 10 06:30:52 PM PDT 24
Finished Jun 10 06:34:59 PM PDT 24
Peak memory 191944 kb
Host smart-3c6db6f4-f676-4e69-96d8-8a35ebc7fc88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865409258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3865409258
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2346577586
Short name T126
Test name
Test status
Simulation time 124619353314 ps
CPU time 568.83 seconds
Started Jun 10 06:30:40 PM PDT 24
Finished Jun 10 06:40:10 PM PDT 24
Peak memory 204440 kb
Host smart-a9aa4ad9-9674-400c-aec7-8fb0bbd70053
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346577586 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2346577586
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3101875062
Short name T35
Test name
Test status
Simulation time 70044555085 ps
CPU time 527.81 seconds
Started Jun 10 06:31:29 PM PDT 24
Finished Jun 10 06:40:18 PM PDT 24
Peak memory 202600 kb
Host smart-a5652948-3f33-4d60-9858-9e680ae288db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101875062 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3101875062
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2010401407
Short name T112
Test name
Test status
Simulation time 109636217286 ps
CPU time 30.17 seconds
Started Jun 10 06:31:18 PM PDT 24
Finished Jun 10 06:31:49 PM PDT 24
Peak memory 198296 kb
Host smart-383e27ab-0a53-49c9-b0af-e307f4934480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010401407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2010401407
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2355923876
Short name T38
Test name
Test status
Simulation time 272774462678 ps
CPU time 526.08 seconds
Started Jun 10 06:30:52 PM PDT 24
Finished Jun 10 06:39:39 PM PDT 24
Peak memory 212168 kb
Host smart-b1a5c1ce-b174-4864-abe6-5450ab3de321
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355923876 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2355923876
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2052331065
Short name T91
Test name
Test status
Simulation time 189063534235 ps
CPU time 51.94 seconds
Started Jun 10 06:30:36 PM PDT 24
Finished Jun 10 06:31:28 PM PDT 24
Peak memory 198552 kb
Host smart-b960990a-1215-44d2-8541-e6ddc52f495c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052331065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2052331065
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2360166806
Short name T27
Test name
Test status
Simulation time 112693176559 ps
CPU time 82.75 seconds
Started Jun 10 06:31:19 PM PDT 24
Finished Jun 10 06:32:43 PM PDT 24
Peak memory 198244 kb
Host smart-54771063-eac1-47d2-bc48-ae2233a1260f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360166806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2360166806
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.149568252
Short name T122
Test name
Test status
Simulation time 58527170364 ps
CPU time 422.4 seconds
Started Jun 10 06:31:22 PM PDT 24
Finished Jun 10 06:38:25 PM PDT 24
Peak memory 209136 kb
Host smart-b3b9d1ce-eb40-4c35-afad-317c4ad06abe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149568252 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.149568252
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2472241703
Short name T113
Test name
Test status
Simulation time 137926619365 ps
CPU time 109.82 seconds
Started Jun 10 06:29:23 PM PDT 24
Finished Jun 10 06:31:13 PM PDT 24
Peak memory 193016 kb
Host smart-1edc43da-1f56-4970-b653-2ab7b5885431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472241703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2472241703
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2043467721
Short name T142
Test name
Test status
Simulation time 103103592535 ps
CPU time 227.72 seconds
Started Jun 10 06:29:30 PM PDT 24
Finished Jun 10 06:33:18 PM PDT 24
Peak memory 200476 kb
Host smart-9374dd11-e4ec-4bfe-8900-177823429fd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043467721 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2043467721
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.4217685809
Short name T36
Test name
Test status
Simulation time 54323477083 ps
CPU time 381.8 seconds
Started Jun 10 06:31:33 PM PDT 24
Finished Jun 10 06:37:55 PM PDT 24
Peak memory 206804 kb
Host smart-8a63fd5f-5107-42ff-97ae-e6ba736de649
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217685809 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.4217685809
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2320620637
Short name T99
Test name
Test status
Simulation time 136326216234 ps
CPU time 286.33 seconds
Started Jun 10 06:30:05 PM PDT 24
Finished Jun 10 06:34:51 PM PDT 24
Peak memory 209504 kb
Host smart-b09add30-dfc3-4c0d-a639-61b56874ef78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320620637 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2320620637
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2972932403
Short name T106
Test name
Test status
Simulation time 235736709345 ps
CPU time 170.84 seconds
Started Jun 10 06:29:22 PM PDT 24
Finished Jun 10 06:32:13 PM PDT 24
Peak memory 208200 kb
Host smart-7c07f326-6cfe-42cb-847b-0e45f32be2ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972932403 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2972932403
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.799246083
Short name T97
Test name
Test status
Simulation time 43172263314 ps
CPU time 284.1 seconds
Started Jun 10 06:31:02 PM PDT 24
Finished Jun 10 06:35:46 PM PDT 24
Peak memory 206868 kb
Host smart-42cdabff-711b-49cd-a2c2-6edbc7d151cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799246083 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.799246083
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3771275591
Short name T82
Test name
Test status
Simulation time 73779989343 ps
CPU time 575.11 seconds
Started Jun 10 06:29:33 PM PDT 24
Finished Jun 10 06:39:09 PM PDT 24
Peak memory 211916 kb
Host smart-f16a444f-e3f2-41f4-a94d-3d47f1efd20b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771275591 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3771275591
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2473718580
Short name T116
Test name
Test status
Simulation time 239491241532 ps
CPU time 323.44 seconds
Started Jun 10 06:29:10 PM PDT 24
Finished Jun 10 06:34:34 PM PDT 24
Peak memory 191960 kb
Host smart-d7df2a6c-d56c-404a-8707-7b55ee787d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473718580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2473718580
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.231067135
Short name T24
Test name
Test status
Simulation time 104605846527 ps
CPU time 47.13 seconds
Started Jun 10 06:30:13 PM PDT 24
Finished Jun 10 06:31:01 PM PDT 24
Peak memory 191880 kb
Host smart-f81ffe2f-b598-4443-a127-00142f02f220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231067135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.231067135
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1835818514
Short name T46
Test name
Test status
Simulation time 273892711394 ps
CPU time 586.49 seconds
Started Jun 10 06:31:04 PM PDT 24
Finished Jun 10 06:40:51 PM PDT 24
Peak memory 212976 kb
Host smart-210c7512-0f55-4e8b-b768-93777555bea1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835818514 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1835818514
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2313530779
Short name T25
Test name
Test status
Simulation time 93904842952 ps
CPU time 8.48 seconds
Started Jun 10 06:30:22 PM PDT 24
Finished Jun 10 06:30:30 PM PDT 24
Peak memory 192400 kb
Host smart-46e26a79-314d-41b8-8cd6-92ea26d164de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313530779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2313530779
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1708757131
Short name T123
Test name
Test status
Simulation time 116684436277 ps
CPU time 11.59 seconds
Started Jun 10 06:30:38 PM PDT 24
Finished Jun 10 06:30:50 PM PDT 24
Peak memory 198268 kb
Host smart-6a845e31-96e8-437b-8ef3-90610e396604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708757131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1708757131
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.940937941
Short name T83
Test name
Test status
Simulation time 263808536371 ps
CPU time 412.74 seconds
Started Jun 10 06:31:24 PM PDT 24
Finished Jun 10 06:38:17 PM PDT 24
Peak memory 206796 kb
Host smart-d848d01a-b6c0-48fc-8680-e0a2ef61ac6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940937941 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.940937941
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1761074276
Short name T118
Test name
Test status
Simulation time 396388060520 ps
CPU time 596.26 seconds
Started Jun 10 06:31:19 PM PDT 24
Finished Jun 10 06:41:16 PM PDT 24
Peak memory 213452 kb
Host smart-ab24633f-a736-4c3a-a06c-cea565b58b08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761074276 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1761074276
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1788618242
Short name T85
Test name
Test status
Simulation time 51510806549 ps
CPU time 547.43 seconds
Started Jun 10 06:31:20 PM PDT 24
Finished Jun 10 06:40:28 PM PDT 24
Peak memory 201628 kb
Host smart-1cc1d523-c142-42aa-a26f-ef6d9a4dc213
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788618242 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1788618242
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2657308846
Short name T8
Test name
Test status
Simulation time 6698412303 ps
CPU time 3.15 seconds
Started Jun 10 06:30:01 PM PDT 24
Finished Jun 10 06:30:04 PM PDT 24
Peak memory 191940 kb
Host smart-38313406-19a2-4692-a8ab-1194e2802617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657308846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2657308846
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.4268096830
Short name T155
Test name
Test status
Simulation time 37978266712 ps
CPU time 414.32 seconds
Started Jun 10 06:30:11 PM PDT 24
Finished Jun 10 06:37:06 PM PDT 24
Peak memory 214124 kb
Host smart-8c4d4d55-df5d-497c-be11-b9dd8fb3f0e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268096830 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.4268096830
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2372845468
Short name T9
Test name
Test status
Simulation time 219215563453 ps
CPU time 77.69 seconds
Started Jun 10 06:30:19 PM PDT 24
Finished Jun 10 06:31:37 PM PDT 24
Peak memory 193028 kb
Host smart-d9a23197-d1cc-4a46-b7be-b7f80050868e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372845468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2372845468
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1604102452
Short name T132
Test name
Test status
Simulation time 4261043449 ps
CPU time 6.96 seconds
Started Jun 10 06:30:51 PM PDT 24
Finished Jun 10 06:30:59 PM PDT 24
Peak memory 191856 kb
Host smart-24e67081-e805-4014-8fc2-164b750e8b1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604102452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1604102452
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3110614317
Short name T120
Test name
Test status
Simulation time 145099782915 ps
CPU time 51.25 seconds
Started Jun 10 06:29:33 PM PDT 24
Finished Jun 10 06:30:24 PM PDT 24
Peak memory 198272 kb
Host smart-eb867f20-8583-4f78-8e5a-b1e27f90e7b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110614317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3110614317
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.845903376
Short name T103
Test name
Test status
Simulation time 190645705139 ps
CPU time 245.79 seconds
Started Jun 10 06:31:06 PM PDT 24
Finished Jun 10 06:35:12 PM PDT 24
Peak memory 198236 kb
Host smart-e2fff0e8-19f7-4cb5-bd01-2bc7b9a9376a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845903376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.845903376
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1514020712
Short name T92
Test name
Test status
Simulation time 376909710457 ps
CPU time 564.61 seconds
Started Jun 10 06:31:12 PM PDT 24
Finished Jun 10 06:40:37 PM PDT 24
Peak memory 192408 kb
Host smart-3a404cc3-9427-4a48-a7f0-77e2d1729606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514020712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1514020712
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2517879428
Short name T164
Test name
Test status
Simulation time 261719214711 ps
CPU time 114.28 seconds
Started Jun 10 06:29:30 PM PDT 24
Finished Jun 10 06:31:24 PM PDT 24
Peak memory 198288 kb
Host smart-d3f3dd98-156c-4518-bdfb-b98b0e8070a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517879428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2517879428
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.95740436
Short name T110
Test name
Test status
Simulation time 16643473059 ps
CPU time 6.44 seconds
Started Jun 10 06:29:38 PM PDT 24
Finished Jun 10 06:29:44 PM PDT 24
Peak memory 198232 kb
Host smart-0397e18b-b043-4ae4-b9b7-11899b7b1774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95740436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all
.95740436
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.4285650765
Short name T128
Test name
Test status
Simulation time 19392986120 ps
CPU time 150.4 seconds
Started Jun 10 06:30:25 PM PDT 24
Finished Jun 10 06:32:56 PM PDT 24
Peak memory 214408 kb
Host smart-dd7641ae-d02a-4bd9-a2a2-228aa1c9827e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285650765 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.4285650765
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.500802667
Short name T49
Test name
Test status
Simulation time 255469479427 ps
CPU time 379.07 seconds
Started Jun 10 06:31:24 PM PDT 24
Finished Jun 10 06:37:44 PM PDT 24
Peak memory 184172 kb
Host smart-17146dfd-48c0-4833-bc33-e8ee35d7f246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500802667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.500802667
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2513110211
Short name T7
Test name
Test status
Simulation time 39811988724 ps
CPU time 14.25 seconds
Started Jun 10 06:31:28 PM PDT 24
Finished Jun 10 06:31:43 PM PDT 24
Peak memory 184692 kb
Host smart-cddcd992-e3c7-4077-a240-cb6f104f81f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513110211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2513110211
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.4061943912
Short name T43
Test name
Test status
Simulation time 70738850580 ps
CPU time 547.25 seconds
Started Jun 10 06:30:55 PM PDT 24
Finished Jun 10 06:40:03 PM PDT 24
Peak memory 203148 kb
Host smart-88990e97-457e-4aef-afd0-1299259d9c02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061943912 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.4061943912
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1582633270
Short name T127
Test name
Test status
Simulation time 261922435744 ps
CPU time 735.45 seconds
Started Jun 10 06:30:36 PM PDT 24
Finished Jun 10 06:42:52 PM PDT 24
Peak memory 207340 kb
Host smart-2dbbdedb-a8af-454c-88db-325bca20ee0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582633270 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1582633270
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1933099736
Short name T137
Test name
Test status
Simulation time 108389341957 ps
CPU time 262.3 seconds
Started Jun 10 06:31:16 PM PDT 24
Finished Jun 10 06:35:39 PM PDT 24
Peak memory 201188 kb
Host smart-81c42f82-acf4-47fc-a1b0-ffcae5305591
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933099736 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1933099736
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2962070487
Short name T159
Test name
Test status
Simulation time 390932154182 ps
CPU time 68.38 seconds
Started Jun 10 06:31:22 PM PDT 24
Finished Jun 10 06:32:31 PM PDT 24
Peak memory 192672 kb
Host smart-a837e307-f107-4a00-9182-11499527b363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962070487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2962070487
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3998977837
Short name T88
Test name
Test status
Simulation time 99492473032 ps
CPU time 195.26 seconds
Started Jun 10 06:30:43 PM PDT 24
Finished Jun 10 06:33:59 PM PDT 24
Peak memory 206848 kb
Host smart-c07e84d2-1173-4f73-88a7-9e91819249d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998977837 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3998977837
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.4212587744
Short name T95
Test name
Test status
Simulation time 97405328801 ps
CPU time 71.55 seconds
Started Jun 10 06:31:11 PM PDT 24
Finished Jun 10 06:32:23 PM PDT 24
Peak memory 191912 kb
Host smart-9e0c63a8-23bf-4a91-8097-ab7dd2c997ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212587744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.4212587744
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.506575560
Short name T94
Test name
Test status
Simulation time 294064636849 ps
CPU time 113.42 seconds
Started Jun 10 06:30:09 PM PDT 24
Finished Jun 10 06:32:03 PM PDT 24
Peak memory 198280 kb
Host smart-bc6c3988-5478-4335-9306-2bc3de50a86e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506575560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.506575560
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3378321775
Short name T138
Test name
Test status
Simulation time 31264627410 ps
CPU time 251.24 seconds
Started Jun 10 06:30:19 PM PDT 24
Finished Jun 10 06:34:31 PM PDT 24
Peak memory 206832 kb
Host smart-a786bd10-d664-45d8-a33d-a40274cc8d19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378321775 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3378321775
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.230296278
Short name T107
Test name
Test status
Simulation time 28876832737 ps
CPU time 254.65 seconds
Started Jun 10 06:30:53 PM PDT 24
Finished Jun 10 06:35:08 PM PDT 24
Peak memory 214072 kb
Host smart-ffc86f1b-2b86-45a6-9ae0-76c3ac072642
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230296278 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.230296278
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.401550729
Short name T33
Test name
Test status
Simulation time 63688913502 ps
CPU time 301.36 seconds
Started Jun 10 06:29:45 PM PDT 24
Finished Jun 10 06:34:46 PM PDT 24
Peak memory 213980 kb
Host smart-82a07f9e-10af-493f-a494-c9e385f7cfae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401550729 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.401550729
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3708281163
Short name T143
Test name
Test status
Simulation time 142519185734 ps
CPU time 57.18 seconds
Started Jun 10 06:31:15 PM PDT 24
Finished Jun 10 06:32:12 PM PDT 24
Peak memory 193036 kb
Host smart-d9600084-7c64-45fd-99f6-9bcffe083d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708281163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3708281163
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3283249461
Short name T129
Test name
Test status
Simulation time 200677694684 ps
CPU time 84.63 seconds
Started Jun 10 06:29:55 PM PDT 24
Finished Jun 10 06:31:19 PM PDT 24
Peak memory 193040 kb
Host smart-f5bec362-5ac8-49f6-91d5-074a83d0635e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283249461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3283249461
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1199700581
Short name T135
Test name
Test status
Simulation time 530351121 ps
CPU time 0.8 seconds
Started Jun 10 06:31:02 PM PDT 24
Finished Jun 10 06:31:04 PM PDT 24
Peak memory 196600 kb
Host smart-a75f1982-e483-4dc6-8f49-b0b79e057539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199700581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1199700581
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1265288911
Short name T170
Test name
Test status
Simulation time 160786850962 ps
CPU time 263.04 seconds
Started Jun 10 06:31:09 PM PDT 24
Finished Jun 10 06:35:32 PM PDT 24
Peak memory 191924 kb
Host smart-f6c91867-5ae0-4e1f-82a3-dc48d86d3faa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265288911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1265288911
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3635037382
Short name T115
Test name
Test status
Simulation time 405710204 ps
CPU time 0.86 seconds
Started Jun 10 06:31:17 PM PDT 24
Finished Jun 10 06:31:18 PM PDT 24
Peak memory 196564 kb
Host smart-12ea38ce-886d-4696-b4f9-321364472c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635037382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3635037382
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2046628508
Short name T148
Test name
Test status
Simulation time 381986792889 ps
CPU time 494.39 seconds
Started Jun 10 06:29:48 PM PDT 24
Finished Jun 10 06:38:03 PM PDT 24
Peak memory 192028 kb
Host smart-53d4f0be-ebc3-4e98-8b60-a02a79132ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046628508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2046628508
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.952706592
Short name T145
Test name
Test status
Simulation time 410965837 ps
CPU time 1.19 seconds
Started Jun 10 06:29:58 PM PDT 24
Finished Jun 10 06:29:59 PM PDT 24
Peak memory 196584 kb
Host smart-431b7839-0bd4-43f5-b503-4035e4a6cd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952706592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.952706592
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2320460225
Short name T165
Test name
Test status
Simulation time 28663944394 ps
CPU time 9.41 seconds
Started Jun 10 06:29:56 PM PDT 24
Finished Jun 10 06:30:06 PM PDT 24
Peak memory 191848 kb
Host smart-f256b41f-df9b-4c22-8f35-4840d9d9398e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320460225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2320460225
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.565364349
Short name T133
Test name
Test status
Simulation time 344661998 ps
CPU time 0.86 seconds
Started Jun 10 06:30:15 PM PDT 24
Finished Jun 10 06:30:17 PM PDT 24
Peak memory 196672 kb
Host smart-325db26d-966e-45b6-8b63-594a5a0b7c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565364349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.565364349
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3524881195
Short name T146
Test name
Test status
Simulation time 376017871554 ps
CPU time 137.71 seconds
Started Jun 10 06:29:29 PM PDT 24
Finished Jun 10 06:31:47 PM PDT 24
Peak memory 184720 kb
Host smart-e5a69ed0-3a45-4570-9451-1dda8779064c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524881195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3524881195
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2379840132
Short name T139
Test name
Test status
Simulation time 563967224 ps
CPU time 0.82 seconds
Started Jun 10 06:31:04 PM PDT 24
Finished Jun 10 06:31:05 PM PDT 24
Peak memory 196588 kb
Host smart-5c1b2d4d-a96f-475d-b142-de32284d3bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379840132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2379840132
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3659868136
Short name T166
Test name
Test status
Simulation time 59474717809 ps
CPU time 169.97 seconds
Started Jun 10 06:31:20 PM PDT 24
Finished Jun 10 06:34:11 PM PDT 24
Peak memory 206832 kb
Host smart-f485b14c-5493-4610-ad5a-8a70dfe4809b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659868136 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3659868136
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.158493576
Short name T144
Test name
Test status
Simulation time 370663613 ps
CPU time 1.14 seconds
Started Jun 10 06:31:19 PM PDT 24
Finished Jun 10 06:31:21 PM PDT 24
Peak memory 196576 kb
Host smart-9080bfed-f889-4229-b7e3-b592c1c086ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158493576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.158493576
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2562495969
Short name T96
Test name
Test status
Simulation time 214301581214 ps
CPU time 84.9 seconds
Started Jun 10 06:31:24 PM PDT 24
Finished Jun 10 06:32:49 PM PDT 24
Peak memory 191904 kb
Host smart-83dbd8ca-267b-492f-80f1-e67bc0006b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562495969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2562495969
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3982896055
Short name T109
Test name
Test status
Simulation time 589610957 ps
CPU time 0.8 seconds
Started Jun 10 06:29:52 PM PDT 24
Finished Jun 10 06:29:53 PM PDT 24
Peak memory 196680 kb
Host smart-f47762b6-fc11-4c4f-a76b-4d122c6d1c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982896055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3982896055
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.907692344
Short name T93
Test name
Test status
Simulation time 59113649014 ps
CPU time 52.79 seconds
Started Jun 10 06:30:12 PM PDT 24
Finished Jun 10 06:31:05 PM PDT 24
Peak memory 184168 kb
Host smart-c4f6265c-e02f-404e-9fde-a9c63e488c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907692344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.907692344
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2187337597
Short name T162
Test name
Test status
Simulation time 73787937341 ps
CPU time 646.11 seconds
Started Jun 10 06:29:28 PM PDT 24
Finished Jun 10 06:40:14 PM PDT 24
Peak memory 203512 kb
Host smart-2cdd4a43-e6c0-4f70-b72a-57c3a4408566
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187337597 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2187337597
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2538654057
Short name T124
Test name
Test status
Simulation time 130578734059 ps
CPU time 163.5 seconds
Started Jun 10 06:31:08 PM PDT 24
Finished Jun 10 06:33:52 PM PDT 24
Peak memory 192640 kb
Host smart-aaefc1d1-b320-47bc-b970-6fc40aba0a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538654057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2538654057
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3899397522
Short name T108
Test name
Test status
Simulation time 473337169 ps
CPU time 0.64 seconds
Started Jun 10 06:29:31 PM PDT 24
Finished Jun 10 06:29:32 PM PDT 24
Peak memory 196584 kb
Host smart-08ea2f17-97e1-445b-9887-c316e0551cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899397522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3899397522
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1322673186
Short name T114
Test name
Test status
Simulation time 343105380 ps
CPU time 1.11 seconds
Started Jun 10 06:29:59 PM PDT 24
Finished Jun 10 06:30:00 PM PDT 24
Peak memory 196624 kb
Host smart-fc0e169b-33b1-44d5-ac61-a000494ef26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322673186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1322673186
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2723259283
Short name T152
Test name
Test status
Simulation time 261187523096 ps
CPU time 346.16 seconds
Started Jun 10 06:30:34 PM PDT 24
Finished Jun 10 06:36:21 PM PDT 24
Peak memory 198300 kb
Host smart-9326c523-181f-41f3-b5f8-cd80f124a71a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723259283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2723259283
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.48182517
Short name T154
Test name
Test status
Simulation time 326332607475 ps
CPU time 132.7 seconds
Started Jun 10 06:30:48 PM PDT 24
Finished Jun 10 06:33:01 PM PDT 24
Peak memory 193028 kb
Host smart-419810c5-ee85-4902-9dea-7f0e47479933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48182517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_al
l.48182517
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3363184098
Short name T130
Test name
Test status
Simulation time 402087033 ps
CPU time 0.64 seconds
Started Jun 10 06:30:44 PM PDT 24
Finished Jun 10 06:30:45 PM PDT 24
Peak memory 196524 kb
Host smart-5ecc581c-fe70-46fa-8ebc-3436f17df3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363184098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3363184098
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.78469101
Short name T40
Test name
Test status
Simulation time 380885387939 ps
CPU time 562.81 seconds
Started Jun 10 06:30:59 PM PDT 24
Finished Jun 10 06:40:22 PM PDT 24
Peak memory 198272 kb
Host smart-21a18222-a559-40b2-af34-a1b269a4a7e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78469101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_al
l.78469101
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2497301072
Short name T125
Test name
Test status
Simulation time 335536392 ps
CPU time 1.04 seconds
Started Jun 10 06:31:14 PM PDT 24
Finished Jun 10 06:31:15 PM PDT 24
Peak memory 196596 kb
Host smart-b11f841c-f5e2-4ff7-9a98-0aff9cb2dae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497301072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2497301072
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.4036887648
Short name T140
Test name
Test status
Simulation time 31821340513 ps
CPU time 26.12 seconds
Started Jun 10 06:29:18 PM PDT 24
Finished Jun 10 06:29:44 PM PDT 24
Peak memory 198344 kb
Host smart-9c97faa7-126b-4f23-b42b-fa407d94f0c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036887648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.4036887648
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1408719605
Short name T119
Test name
Test status
Simulation time 389128974 ps
CPU time 1.11 seconds
Started Jun 10 06:30:09 PM PDT 24
Finished Jun 10 06:30:11 PM PDT 24
Peak memory 196596 kb
Host smart-5bbc6e12-a13b-4a30-8d68-394b1bc091b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408719605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1408719605
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.4133315031
Short name T100
Test name
Test status
Simulation time 428059025 ps
CPU time 0.72 seconds
Started Jun 10 06:30:30 PM PDT 24
Finished Jun 10 06:30:31 PM PDT 24
Peak memory 196588 kb
Host smart-b2715c14-850c-4993-8fb7-e9893c0d8cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133315031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.4133315031
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2320681569
Short name T182
Test name
Test status
Simulation time 60694271677 ps
CPU time 5.73 seconds
Started Jun 10 06:30:27 PM PDT 24
Finished Jun 10 06:30:33 PM PDT 24
Peak memory 192996 kb
Host smart-653f6867-42a4-45a9-9d5c-02068fdf9a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320681569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2320681569
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2759162238
Short name T153
Test name
Test status
Simulation time 227644511338 ps
CPU time 150.29 seconds
Started Jun 10 06:30:33 PM PDT 24
Finished Jun 10 06:33:03 PM PDT 24
Peak memory 192984 kb
Host smart-e9468db6-487d-409f-989c-d96061175548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759162238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2759162238
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3512422072
Short name T117
Test name
Test status
Simulation time 433535137 ps
CPU time 0.9 seconds
Started Jun 10 06:30:37 PM PDT 24
Finished Jun 10 06:30:38 PM PDT 24
Peak memory 196592 kb
Host smart-70200242-4758-4d30-9068-ea15334bbfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512422072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3512422072
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2688747386
Short name T34
Test name
Test status
Simulation time 104690802515 ps
CPU time 248.27 seconds
Started Jun 10 06:30:45 PM PDT 24
Finished Jun 10 06:34:53 PM PDT 24
Peak memory 215012 kb
Host smart-075fcb2f-9ce6-4ffb-a4c1-6c6170bc7370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688747386 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2688747386
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2030727957
Short name T134
Test name
Test status
Simulation time 548296178 ps
CPU time 1.44 seconds
Started Jun 10 06:30:44 PM PDT 24
Finished Jun 10 06:30:45 PM PDT 24
Peak memory 196664 kb
Host smart-5dcd51c0-5978-4ec4-a996-e76809b4b02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030727957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2030727957
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1753359831
Short name T131
Test name
Test status
Simulation time 469992962 ps
CPU time 0.97 seconds
Started Jun 10 06:29:49 PM PDT 24
Finished Jun 10 06:29:50 PM PDT 24
Peak memory 196588 kb
Host smart-27d8cf6c-27a1-493f-a3b3-7a19ca2a31dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753359831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1753359831
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1836513001
Short name T121
Test name
Test status
Simulation time 146033120311 ps
CPU time 106.9 seconds
Started Jun 10 06:30:25 PM PDT 24
Finished Jun 10 06:32:12 PM PDT 24
Peak memory 193040 kb
Host smart-6dd0fbd3-e747-4594-ae53-eeb41f389b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836513001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1836513001
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.467844073
Short name T102
Test name
Test status
Simulation time 413646005 ps
CPU time 0.87 seconds
Started Jun 10 06:30:31 PM PDT 24
Finished Jun 10 06:30:32 PM PDT 24
Peak memory 196612 kb
Host smart-9e2e3f40-34a9-4096-a55f-f8db8d775b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467844073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.467844073
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1240399354
Short name T181
Test name
Test status
Simulation time 412907689 ps
CPU time 0.91 seconds
Started Jun 10 06:30:51 PM PDT 24
Finished Jun 10 06:30:53 PM PDT 24
Peak memory 196588 kb
Host smart-e5d8bb84-bbce-457a-ac1c-d2a50c577377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240399354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1240399354
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.423124375
Short name T149
Test name
Test status
Simulation time 465258177 ps
CPU time 0.75 seconds
Started Jun 10 06:31:29 PM PDT 24
Finished Jun 10 06:31:30 PM PDT 24
Peak memory 196632 kb
Host smart-4ac20e6e-ba5c-4367-8d1d-ab5fb74103e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423124375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.423124375
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1119582316
Short name T178
Test name
Test status
Simulation time 656879721 ps
CPU time 0.7 seconds
Started Jun 10 06:29:07 PM PDT 24
Finished Jun 10 06:29:08 PM PDT 24
Peak memory 196580 kb
Host smart-50399d07-5702-447d-b8dd-89d9e4442381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119582316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1119582316
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.21066568
Short name T169
Test name
Test status
Simulation time 594256488 ps
CPU time 1.1 seconds
Started Jun 10 06:29:19 PM PDT 24
Finished Jun 10 06:29:20 PM PDT 24
Peak memory 196572 kb
Host smart-8d004f76-7da0-4af7-b0c3-e0b777e33de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21066568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.21066568
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2270349238
Short name T52
Test name
Test status
Simulation time 255051017742 ps
CPU time 669.45 seconds
Started Jun 10 06:30:01 PM PDT 24
Finished Jun 10 06:41:11 PM PDT 24
Peak memory 215028 kb
Host smart-1b3ed975-09b1-43f4-b326-420068fc249c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270349238 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2270349238
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2169919916
Short name T179
Test name
Test status
Simulation time 429327195 ps
CPU time 0.72 seconds
Started Jun 10 06:30:04 PM PDT 24
Finished Jun 10 06:30:05 PM PDT 24
Peak memory 196580 kb
Host smart-ae06ab1e-17c7-439b-abf7-2e1dd34fa1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169919916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2169919916
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.864586421
Short name T147
Test name
Test status
Simulation time 461847633 ps
CPU time 0.95 seconds
Started Jun 10 06:30:16 PM PDT 24
Finished Jun 10 06:30:18 PM PDT 24
Peak memory 196576 kb
Host smart-725dedfc-3909-4df7-b0f0-6295b222e9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864586421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.864586421
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2490663460
Short name T158
Test name
Test status
Simulation time 25809694148 ps
CPU time 207.58 seconds
Started Jun 10 06:30:14 PM PDT 24
Finished Jun 10 06:33:42 PM PDT 24
Peak memory 206872 kb
Host smart-84dff526-994e-4390-af33-21872cca5772
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490663460 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2490663460
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1456653767
Short name T78
Test name
Test status
Simulation time 624210752 ps
CPU time 1.04 seconds
Started Jun 10 06:30:26 PM PDT 24
Finished Jun 10 06:30:27 PM PDT 24
Peak memory 196648 kb
Host smart-4f6077f7-03c4-48d9-b493-f753de91372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456653767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1456653767
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.363246223
Short name T22
Test name
Test status
Simulation time 576621033 ps
CPU time 1.54 seconds
Started Jun 10 06:30:27 PM PDT 24
Finished Jun 10 06:30:28 PM PDT 24
Peak memory 196592 kb
Host smart-4558bad7-5f15-40e5-b4c7-3a9d5c2c6ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363246223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.363246223
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2687715492
Short name T161
Test name
Test status
Simulation time 399164383 ps
CPU time 1.12 seconds
Started Jun 10 06:29:24 PM PDT 24
Finished Jun 10 06:29:26 PM PDT 24
Peak memory 196664 kb
Host smart-b0f0ede9-b8d8-4c1b-80a4-053a153515db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687715492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2687715492
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3689873170
Short name T172
Test name
Test status
Simulation time 450978805 ps
CPU time 0.78 seconds
Started Jun 10 06:30:56 PM PDT 24
Finished Jun 10 06:30:57 PM PDT 24
Peak memory 196660 kb
Host smart-db2deb17-89e6-4028-8c1d-8f2526c8a5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689873170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3689873170
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1205695767
Short name T151
Test name
Test status
Simulation time 160430149885 ps
CPU time 256.93 seconds
Started Jun 10 06:31:07 PM PDT 24
Finished Jun 10 06:35:24 PM PDT 24
Peak memory 192828 kb
Host smart-6da5d82e-bd25-4ab1-8fd9-c00c3b620c57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205695767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1205695767
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1413119092
Short name T184
Test name
Test status
Simulation time 527964943 ps
CPU time 1.36 seconds
Started Jun 10 06:31:07 PM PDT 24
Finished Jun 10 06:31:09 PM PDT 24
Peak memory 196608 kb
Host smart-03810615-ad84-464a-ba24-7821eb4e9371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413119092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1413119092
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1123793547
Short name T136
Test name
Test status
Simulation time 496370305 ps
CPU time 1.37 seconds
Started Jun 10 06:31:11 PM PDT 24
Finished Jun 10 06:31:13 PM PDT 24
Peak memory 196656 kb
Host smart-929484c9-96d5-465d-879a-3d05307778a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123793547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1123793547
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3179480630
Short name T168
Test name
Test status
Simulation time 469961402 ps
CPU time 1.34 seconds
Started Jun 10 06:31:16 PM PDT 24
Finished Jun 10 06:31:18 PM PDT 24
Peak memory 196632 kb
Host smart-7dd7ff4e-1aaf-480d-9ad7-a6fda193f1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179480630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3179480630
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.515478436
Short name T163
Test name
Test status
Simulation time 580879048 ps
CPU time 1.01 seconds
Started Jun 10 06:31:18 PM PDT 24
Finished Jun 10 06:31:20 PM PDT 24
Peak memory 196504 kb
Host smart-3a7b610b-bcab-415a-a50a-048aec37cf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515478436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.515478436
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2259531060
Short name T157
Test name
Test status
Simulation time 459510953 ps
CPU time 0.73 seconds
Started Jun 10 06:31:30 PM PDT 24
Finished Jun 10 06:31:31 PM PDT 24
Peak memory 196568 kb
Host smart-e7d1262a-8891-49d8-8fea-2b74b7f24d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259531060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2259531060
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3209458848
Short name T14
Test name
Test status
Simulation time 478503156 ps
CPU time 0.78 seconds
Started Jun 10 06:31:42 PM PDT 24
Finished Jun 10 06:31:43 PM PDT 24
Peak memory 196556 kb
Host smart-1f147958-dd17-4bfd-a299-1c5933dbcc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209458848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3209458848
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1173224982
Short name T171
Test name
Test status
Simulation time 168013278446 ps
CPU time 250.17 seconds
Started Jun 10 06:29:35 PM PDT 24
Finished Jun 10 06:33:46 PM PDT 24
Peak memory 198212 kb
Host smart-59da6152-31b2-40ca-863d-59be68641520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173224982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1173224982
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1883929402
Short name T45
Test name
Test status
Simulation time 549513904 ps
CPU time 0.81 seconds
Started Jun 10 06:29:36 PM PDT 24
Finished Jun 10 06:29:37 PM PDT 24
Peak memory 196576 kb
Host smart-dac7be1e-6e56-4415-86fe-0cab70ca0263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883929402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1883929402
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3944346142
Short name T2
Test name
Test status
Simulation time 387890206 ps
CPU time 0.87 seconds
Started Jun 10 06:29:42 PM PDT 24
Finished Jun 10 06:29:43 PM PDT 24
Peak memory 196584 kb
Host smart-6a7ca58c-52e8-4e08-b62b-49e6fbb6484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944346142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3944346142
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.334532259
Short name T188
Test name
Test status
Simulation time 8246965891 ps
CPU time 4.21 seconds
Started Jun 10 06:31:34 PM PDT 24
Finished Jun 10 06:31:38 PM PDT 24
Peak memory 198220 kb
Host smart-43f98885-9195-4300-9475-261b8dbae17c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334532259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.334532259
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1003999587
Short name T160
Test name
Test status
Simulation time 389467930 ps
CPU time 0.78 seconds
Started Jun 10 06:30:04 PM PDT 24
Finished Jun 10 06:30:05 PM PDT 24
Peak memory 196584 kb
Host smart-db68f3e5-0877-4a7e-866b-418ac8644c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003999587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1003999587
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3244645564
Short name T47
Test name
Test status
Simulation time 522115116 ps
CPU time 1.4 seconds
Started Jun 10 06:30:11 PM PDT 24
Finished Jun 10 06:30:13 PM PDT 24
Peak memory 196568 kb
Host smart-aabbde2b-08ae-47a2-a7ab-2691ee973def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244645564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3244645564
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2388466895
Short name T84
Test name
Test status
Simulation time 145892000689 ps
CPU time 254.31 seconds
Started Jun 10 06:30:24 PM PDT 24
Finished Jun 10 06:34:38 PM PDT 24
Peak memory 206784 kb
Host smart-94a4b7b2-c25e-4e90-bc0c-d2d0d06c9cb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388466895 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2388466895
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1126748176
Short name T173
Test name
Test status
Simulation time 544431294 ps
CPU time 0.79 seconds
Started Jun 10 06:30:30 PM PDT 24
Finished Jun 10 06:30:31 PM PDT 24
Peak memory 196560 kb
Host smart-f7e237a4-e107-4905-bcd7-99d135700a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126748176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1126748176
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3997416277
Short name T174
Test name
Test status
Simulation time 453305816 ps
CPU time 1.23 seconds
Started Jun 10 06:31:26 PM PDT 24
Finished Jun 10 06:31:27 PM PDT 24
Peak memory 196488 kb
Host smart-761005c8-e051-4496-8ab9-ebddb212b2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997416277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3997416277
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2734030354
Short name T77
Test name
Test status
Simulation time 396423343 ps
CPU time 0.77 seconds
Started Jun 10 06:29:34 PM PDT 24
Finished Jun 10 06:29:35 PM PDT 24
Peak memory 196568 kb
Host smart-8aa7b260-8921-4c4c-b2bd-2e08601b3711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734030354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2734030354
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1771430887
Short name T62
Test name
Test status
Simulation time 426423892 ps
CPU time 0.85 seconds
Started Jun 10 06:31:33 PM PDT 24
Finished Jun 10 06:31:34 PM PDT 24
Peak memory 193952 kb
Host smart-4a6e7807-c2ff-40b1-a2a3-fa00a9ac2608
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771430887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1771430887
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2086412353
Short name T61
Test name
Test status
Simulation time 3310284207 ps
CPU time 3.32 seconds
Started Jun 10 06:31:42 PM PDT 24
Finished Jun 10 06:31:45 PM PDT 24
Peak memory 195572 kb
Host smart-b900349c-698a-48a5-9d49-f86df433935b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086412353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2086412353
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2710437069
Short name T375
Test name
Test status
Simulation time 813958794 ps
CPU time 1 seconds
Started Jun 10 06:31:32 PM PDT 24
Finished Jun 10 06:31:34 PM PDT 24
Peak memory 192016 kb
Host smart-644813bf-37f8-4159-b2be-0b77e77b733e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710437069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2710437069
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.668804145
Short name T372
Test name
Test status
Simulation time 399118148 ps
CPU time 0.73 seconds
Started Jun 10 06:31:37 PM PDT 24
Finished Jun 10 06:31:38 PM PDT 24
Peak memory 195524 kb
Host smart-86879e25-87d2-4eba-a531-0bfdd104044b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668804145 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.668804145
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1005033327
Short name T385
Test name
Test status
Simulation time 444289359 ps
CPU time 0.9 seconds
Started Jun 10 06:31:32 PM PDT 24
Finished Jun 10 06:31:33 PM PDT 24
Peak memory 193952 kb
Host smart-2bd46f39-8dea-4172-8a51-6350f25501ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005033327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1005033327
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3904052494
Short name T389
Test name
Test status
Simulation time 289721765 ps
CPU time 0.79 seconds
Started Jun 10 06:31:31 PM PDT 24
Finished Jun 10 06:31:32 PM PDT 24
Peak memory 192852 kb
Host smart-f8358429-39e1-4859-9cc8-86ab2e2eb953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904052494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3904052494
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.594003401
Short name T280
Test name
Test status
Simulation time 480202257 ps
CPU time 1.23 seconds
Started Jun 10 06:31:32 PM PDT 24
Finished Jun 10 06:31:33 PM PDT 24
Peak memory 183564 kb
Host smart-3d1ce890-9fcf-4ec2-93aa-422668422f06
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594003401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.594003401
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1662803536
Short name T333
Test name
Test status
Simulation time 428152057 ps
CPU time 0.79 seconds
Started Jun 10 06:31:32 PM PDT 24
Finished Jun 10 06:31:33 PM PDT 24
Peak memory 183608 kb
Host smart-65f19fcc-8b77-4b0c-b050-df59c2cdec90
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662803536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1662803536
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.986684512
Short name T398
Test name
Test status
Simulation time 2014311894 ps
CPU time 1.85 seconds
Started Jun 10 06:31:37 PM PDT 24
Finished Jun 10 06:31:39 PM PDT 24
Peak memory 183896 kb
Host smart-83aa747d-50d5-4551-a65c-829f7f2da1e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986684512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.986684512
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1278488855
Short name T380
Test name
Test status
Simulation time 510586991 ps
CPU time 2.13 seconds
Started Jun 10 06:31:32 PM PDT 24
Finished Jun 10 06:31:34 PM PDT 24
Peak memory 198468 kb
Host smart-105a7e47-99aa-4796-b388-7b1fcbde3c29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278488855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1278488855
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2357111401
Short name T290
Test name
Test status
Simulation time 492464404 ps
CPU time 1.11 seconds
Started Jun 10 06:31:35 PM PDT 24
Finished Jun 10 06:31:37 PM PDT 24
Peak memory 183584 kb
Host smart-b62f85e0-a75e-47b1-9e6b-fd45bd056107
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357111401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2357111401
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.435624264
Short name T63
Test name
Test status
Simulation time 13752814195 ps
CPU time 34.85 seconds
Started Jun 10 06:31:37 PM PDT 24
Finished Jun 10 06:32:12 PM PDT 24
Peak memory 196120 kb
Host smart-96fe01bb-da56-4cde-89d1-a6ebda78c34d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435624264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.435624264
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3020642775
Short name T354
Test name
Test status
Simulation time 704756675 ps
CPU time 0.82 seconds
Started Jun 10 06:31:36 PM PDT 24
Finished Jun 10 06:31:37 PM PDT 24
Peak memory 183664 kb
Host smart-25f27326-a762-4721-8872-cdf5ad246e65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020642775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3020642775
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3216892151
Short name T410
Test name
Test status
Simulation time 543850793 ps
CPU time 1.36 seconds
Started Jun 10 06:31:35 PM PDT 24
Finished Jun 10 06:31:37 PM PDT 24
Peak memory 195264 kb
Host smart-8739001b-57d8-4e8d-8810-6c14dcba2594
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216892151 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3216892151
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.621820003
Short name T352
Test name
Test status
Simulation time 446726047 ps
CPU time 0.74 seconds
Started Jun 10 06:31:37 PM PDT 24
Finished Jun 10 06:31:38 PM PDT 24
Peak memory 192996 kb
Host smart-12d31d6e-73e2-4b80-a5bb-3963e29635af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621820003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.621820003
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2699799789
Short name T406
Test name
Test status
Simulation time 483746470 ps
CPU time 0.8 seconds
Started Jun 10 06:31:36 PM PDT 24
Finished Jun 10 06:31:37 PM PDT 24
Peak memory 192824 kb
Host smart-2549c8ed-4502-4366-a02d-fa3b1d42c38a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699799789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2699799789
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4040123680
Short name T356
Test name
Test status
Simulation time 455191373 ps
CPU time 0.73 seconds
Started Jun 10 06:31:35 PM PDT 24
Finished Jun 10 06:31:36 PM PDT 24
Peak memory 183532 kb
Host smart-c274ab6b-6951-484d-be1c-59a31a78c25c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040123680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.4040123680
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4276117456
Short name T285
Test name
Test status
Simulation time 318382308 ps
CPU time 0.96 seconds
Started Jun 10 06:31:42 PM PDT 24
Finished Jun 10 06:31:43 PM PDT 24
Peak memory 183644 kb
Host smart-d5ecad66-c656-4d73-a087-77ecbeb70534
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276117456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.4276117456
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2135381666
Short name T73
Test name
Test status
Simulation time 1676102186 ps
CPU time 0.94 seconds
Started Jun 10 06:31:42 PM PDT 24
Finished Jun 10 06:31:43 PM PDT 24
Peak memory 192940 kb
Host smart-0f4c24a6-4c31-48e6-96a2-39a4b5a937f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135381666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2135381666
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2232000627
Short name T287
Test name
Test status
Simulation time 507936058 ps
CPU time 1.66 seconds
Started Jun 10 06:31:35 PM PDT 24
Finished Jun 10 06:31:37 PM PDT 24
Peak memory 198460 kb
Host smart-6a5257d2-a732-4f6e-9a73-8824eb8f2599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232000627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2232000627
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1088061069
Short name T413
Test name
Test status
Simulation time 8163833600 ps
CPU time 4.41 seconds
Started Jun 10 06:31:42 PM PDT 24
Finished Jun 10 06:31:47 PM PDT 24
Peak memory 198100 kb
Host smart-9e56aa1d-9139-4de8-acfb-60899bffb36f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088061069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1088061069
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1079881477
Short name T317
Test name
Test status
Simulation time 393568823 ps
CPU time 0.93 seconds
Started Jun 10 06:32:17 PM PDT 24
Finished Jun 10 06:32:18 PM PDT 24
Peak memory 196168 kb
Host smart-74293e99-af10-4064-839b-03a05335400c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079881477 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1079881477
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.184381026
Short name T55
Test name
Test status
Simulation time 447636639 ps
CPU time 1.21 seconds
Started Jun 10 06:32:16 PM PDT 24
Finished Jun 10 06:32:18 PM PDT 24
Peak memory 193184 kb
Host smart-cfc7abe7-23ca-4aca-9d77-30f6aed38d3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184381026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.184381026
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.57314401
Short name T364
Test name
Test status
Simulation time 454088064 ps
CPU time 0.83 seconds
Started Jun 10 06:32:20 PM PDT 24
Finished Jun 10 06:32:21 PM PDT 24
Peak memory 183620 kb
Host smart-6b1e3ead-41c5-41c8-b337-6dd429115a16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57314401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.57314401
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1007578220
Short name T325
Test name
Test status
Simulation time 2545537183 ps
CPU time 4.19 seconds
Started Jun 10 06:32:17 PM PDT 24
Finished Jun 10 06:32:21 PM PDT 24
Peak memory 191984 kb
Host smart-5672f21f-073d-4cc5-970b-b30df6616467
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007578220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1007578220
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3627360818
Short name T296
Test name
Test status
Simulation time 528071146 ps
CPU time 1.86 seconds
Started Jun 10 06:32:18 PM PDT 24
Finished Jun 10 06:32:20 PM PDT 24
Peak memory 198444 kb
Host smart-d17f1b66-6cc4-4eee-bd00-85833e3e3eeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627360818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3627360818
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2482391279
Short name T191
Test name
Test status
Simulation time 9368189986 ps
CPU time 2.84 seconds
Started Jun 10 06:32:16 PM PDT 24
Finished Jun 10 06:32:19 PM PDT 24
Peak memory 198260 kb
Host smart-04a6629d-39e7-483c-9507-c51bf4e40698
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482391279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2482391279
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3636173601
Short name T297
Test name
Test status
Simulation time 493821761 ps
CPU time 1.39 seconds
Started Jun 10 06:32:22 PM PDT 24
Finished Jun 10 06:32:23 PM PDT 24
Peak memory 196420 kb
Host smart-a9a99ec8-43c1-4ab5-83ec-717580d88122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636173601 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3636173601
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3713547605
Short name T376
Test name
Test status
Simulation time 371003777 ps
CPU time 0.81 seconds
Started Jun 10 06:32:23 PM PDT 24
Finished Jun 10 06:32:24 PM PDT 24
Peak memory 192948 kb
Host smart-7fce5f50-7a06-415d-ab03-2c46531331e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713547605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3713547605
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1804182429
Short name T329
Test name
Test status
Simulation time 457286583 ps
CPU time 0.71 seconds
Started Jun 10 06:32:23 PM PDT 24
Finished Jun 10 06:32:24 PM PDT 24
Peak memory 183644 kb
Host smart-22c9e028-b54b-4095-a7ed-c52af2f4b504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804182429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1804182429
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.725780442
Short name T348
Test name
Test status
Simulation time 1174311514 ps
CPU time 1.18 seconds
Started Jun 10 06:32:22 PM PDT 24
Finished Jun 10 06:32:23 PM PDT 24
Peak memory 192896 kb
Host smart-afdb22c9-e0a4-4696-95dc-0fcee6d4c6e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725780442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.725780442
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.838802881
Short name T315
Test name
Test status
Simulation time 440541073 ps
CPU time 1.7 seconds
Started Jun 10 06:32:20 PM PDT 24
Finished Jun 10 06:32:22 PM PDT 24
Peak memory 198336 kb
Host smart-ce15a3cd-85ae-4fe1-99ef-d2c52da85f49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838802881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.838802881
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.138670774
Short name T31
Test name
Test status
Simulation time 4430344084 ps
CPU time 2.46 seconds
Started Jun 10 06:32:20 PM PDT 24
Finished Jun 10 06:32:22 PM PDT 24
Peak memory 196796 kb
Host smart-707c6491-6e5a-4943-b82f-ee7d0459ecbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138670774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.138670774
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.571885686
Short name T312
Test name
Test status
Simulation time 623390247 ps
CPU time 1.04 seconds
Started Jun 10 06:32:25 PM PDT 24
Finished Jun 10 06:32:27 PM PDT 24
Peak memory 196220 kb
Host smart-deede0fb-44df-49d3-b6fe-60765ae9025e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571885686 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.571885686
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1042723356
Short name T346
Test name
Test status
Simulation time 354581952 ps
CPU time 1.19 seconds
Started Jun 10 06:32:19 PM PDT 24
Finished Jun 10 06:32:21 PM PDT 24
Peak memory 192992 kb
Host smart-e35afefa-11ad-450c-8acf-a7f094d2e9ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042723356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1042723356
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4155580277
Short name T323
Test name
Test status
Simulation time 364702554 ps
CPU time 0.69 seconds
Started Jun 10 06:32:22 PM PDT 24
Finished Jun 10 06:32:23 PM PDT 24
Peak memory 192856 kb
Host smart-febb639a-97e7-443d-b279-bbfbfdbe7d89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155580277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.4155580277
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1352037282
Short name T71
Test name
Test status
Simulation time 1228999041 ps
CPU time 2.66 seconds
Started Jun 10 06:32:21 PM PDT 24
Finished Jun 10 06:32:24 PM PDT 24
Peak memory 193728 kb
Host smart-a8bce378-4f64-4832-a617-1f63737f9080
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352037282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1352037282
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2692833703
Short name T347
Test name
Test status
Simulation time 408067526 ps
CPU time 2.43 seconds
Started Jun 10 06:32:20 PM PDT 24
Finished Jun 10 06:32:23 PM PDT 24
Peak memory 198464 kb
Host smart-0beaaa23-2be4-42a1-ba5f-de6fc315349b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692833703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2692833703
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.229948154
Short name T29
Test name
Test status
Simulation time 4527137759 ps
CPU time 2.75 seconds
Started Jun 10 06:32:22 PM PDT 24
Finished Jun 10 06:32:25 PM PDT 24
Peak memory 197676 kb
Host smart-d33274a8-7a98-4f9e-9aa0-01942462180c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229948154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.229948154
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.779189172
Short name T394
Test name
Test status
Simulation time 422707435 ps
CPU time 0.96 seconds
Started Jun 10 06:32:24 PM PDT 24
Finished Jun 10 06:32:26 PM PDT 24
Peak memory 196224 kb
Host smart-63469d0d-632c-4f52-9e17-cef3b8429a82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779189172 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.779189172
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2303002063
Short name T74
Test name
Test status
Simulation time 500541471 ps
CPU time 0.99 seconds
Started Jun 10 06:32:30 PM PDT 24
Finished Jun 10 06:32:32 PM PDT 24
Peak memory 193900 kb
Host smart-c33c8d7a-496b-4c7c-aafc-1442eb730477
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303002063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2303002063
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3470628112
Short name T324
Test name
Test status
Simulation time 509637814 ps
CPU time 0.73 seconds
Started Jun 10 06:32:26 PM PDT 24
Finished Jun 10 06:32:27 PM PDT 24
Peak memory 183612 kb
Host smart-4b30f00c-4020-414a-a62f-c8ad0aeb32e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470628112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3470628112
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1230716602
Short name T379
Test name
Test status
Simulation time 1317914124 ps
CPU time 1.49 seconds
Started Jun 10 06:32:27 PM PDT 24
Finished Jun 10 06:32:29 PM PDT 24
Peak memory 193452 kb
Host smart-0cbb7355-82fe-4af5-86ba-85b00d6404ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230716602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1230716602
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1297118128
Short name T340
Test name
Test status
Simulation time 564908257 ps
CPU time 1.8 seconds
Started Jun 10 06:32:26 PM PDT 24
Finished Jun 10 06:32:28 PM PDT 24
Peak memory 198428 kb
Host smart-f164cd46-2c89-43f6-aecf-31e5dd7b7960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297118128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1297118128
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.509509887
Short name T310
Test name
Test status
Simulation time 8386656074 ps
CPU time 14.13 seconds
Started Jun 10 06:32:24 PM PDT 24
Finished Jun 10 06:32:39 PM PDT 24
Peak memory 198104 kb
Host smart-1a9fe96f-6d1f-4fca-9c01-43946ac1ed19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509509887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.509509887
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2318043885
Short name T415
Test name
Test status
Simulation time 564226324 ps
CPU time 1.49 seconds
Started Jun 10 06:32:29 PM PDT 24
Finished Jun 10 06:32:31 PM PDT 24
Peak memory 196388 kb
Host smart-84e0a1d6-5c5d-4cf7-b02e-a74cc4f991bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318043885 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2318043885
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3500373593
Short name T28
Test name
Test status
Simulation time 425658544 ps
CPU time 0.73 seconds
Started Jun 10 06:32:28 PM PDT 24
Finished Jun 10 06:32:29 PM PDT 24
Peak memory 193312 kb
Host smart-59f2707c-f979-47ef-b754-b5f43db95fd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500373593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3500373593
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.617214982
Short name T301
Test name
Test status
Simulation time 497763567 ps
CPU time 1.27 seconds
Started Jun 10 06:32:28 PM PDT 24
Finished Jun 10 06:32:29 PM PDT 24
Peak memory 192796 kb
Host smart-56bc8ace-a096-474b-9b9c-a8dc6eec240d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617214982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.617214982
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2591603890
Short name T412
Test name
Test status
Simulation time 1062456918 ps
CPU time 1.34 seconds
Started Jun 10 06:32:30 PM PDT 24
Finished Jun 10 06:32:31 PM PDT 24
Peak memory 192932 kb
Host smart-435fdbe6-b803-426e-a761-26cd01d4f9e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591603890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2591603890
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1240111589
Short name T386
Test name
Test status
Simulation time 436145366 ps
CPU time 2.29 seconds
Started Jun 10 06:32:28 PM PDT 24
Finished Jun 10 06:32:30 PM PDT 24
Peak memory 198376 kb
Host smart-a330fb4b-8aca-49ef-9dc5-be5979b30ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240111589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1240111589
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2841354796
Short name T307
Test name
Test status
Simulation time 4458377835 ps
CPU time 2.72 seconds
Started Jun 10 06:32:30 PM PDT 24
Finished Jun 10 06:32:33 PM PDT 24
Peak memory 197864 kb
Host smart-80f4bb87-bcf4-4cda-bba3-1e00bc590b31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841354796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2841354796
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3759471524
Short name T339
Test name
Test status
Simulation time 363679725 ps
CPU time 0.86 seconds
Started Jun 10 06:32:27 PM PDT 24
Finished Jun 10 06:32:28 PM PDT 24
Peak memory 195592 kb
Host smart-4db291ef-7bd2-4ff4-b082-3cc5eabb0708
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759471524 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3759471524
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1075802097
Short name T59
Test name
Test status
Simulation time 509758410 ps
CPU time 0.99 seconds
Started Jun 10 06:32:28 PM PDT 24
Finished Jun 10 06:32:30 PM PDT 24
Peak memory 192900 kb
Host smart-80414598-6fca-4a35-b5f9-1455337f790e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075802097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1075802097
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.16905748
Short name T358
Test name
Test status
Simulation time 398541393 ps
CPU time 0.67 seconds
Started Jun 10 06:32:29 PM PDT 24
Finished Jun 10 06:32:30 PM PDT 24
Peak memory 183592 kb
Host smart-b1b1bc3c-3dd6-43db-9986-a70a1b1779fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16905748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.16905748
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2017854393
Short name T303
Test name
Test status
Simulation time 2186269498 ps
CPU time 2.98 seconds
Started Jun 10 06:32:28 PM PDT 24
Finished Jun 10 06:32:31 PM PDT 24
Peak memory 194960 kb
Host smart-c947510f-fbe5-4af6-9522-7003d777f0fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017854393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2017854393
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1893924959
Short name T299
Test name
Test status
Simulation time 324263815 ps
CPU time 1.41 seconds
Started Jun 10 06:32:29 PM PDT 24
Finished Jun 10 06:32:31 PM PDT 24
Peak memory 198504 kb
Host smart-f8cc1aa7-de3d-4597-a8af-f0b42035f0ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893924959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1893924959
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1535224949
Short name T391
Test name
Test status
Simulation time 7886713485 ps
CPU time 12.86 seconds
Started Jun 10 06:32:30 PM PDT 24
Finished Jun 10 06:32:44 PM PDT 24
Peak memory 198316 kb
Host smart-aec89bdc-6e2e-4c1a-ae1e-dd6bf447e94b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535224949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1535224949
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1136480092
Short name T365
Test name
Test status
Simulation time 686477622 ps
CPU time 0.98 seconds
Started Jun 10 06:32:35 PM PDT 24
Finished Jun 10 06:32:36 PM PDT 24
Peak memory 198352 kb
Host smart-9a04337e-8f57-4dc7-998d-326f8b0a1513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136480092 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1136480092
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.167256953
Short name T70
Test name
Test status
Simulation time 445753656 ps
CPU time 1.33 seconds
Started Jun 10 06:32:32 PM PDT 24
Finished Jun 10 06:32:33 PM PDT 24
Peak memory 192924 kb
Host smart-0e3579f1-acc1-4e91-8f2c-8c2a6eec1c3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167256953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.167256953
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1245405121
Short name T407
Test name
Test status
Simulation time 464362977 ps
CPU time 0.73 seconds
Started Jun 10 06:32:33 PM PDT 24
Finished Jun 10 06:32:35 PM PDT 24
Peak memory 192848 kb
Host smart-c4382fe5-f59a-41b5-8526-6736db48df39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245405121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1245405121
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.935760094
Short name T68
Test name
Test status
Simulation time 2113157817 ps
CPU time 4.76 seconds
Started Jun 10 06:32:33 PM PDT 24
Finished Jun 10 06:32:38 PM PDT 24
Peak memory 193888 kb
Host smart-2001d09e-8ef2-4a89-abb7-98f462f17f8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935760094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.935760094
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2562245611
Short name T279
Test name
Test status
Simulation time 558809894 ps
CPU time 1.99 seconds
Started Jun 10 06:32:28 PM PDT 24
Finished Jun 10 06:32:30 PM PDT 24
Peak memory 198440 kb
Host smart-749ab55c-402d-4eb8-b87a-07bdc8426e49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562245611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2562245611
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2956930186
Short name T314
Test name
Test status
Simulation time 4372550138 ps
CPU time 7.55 seconds
Started Jun 10 06:32:29 PM PDT 24
Finished Jun 10 06:32:37 PM PDT 24
Peak memory 197732 kb
Host smart-cb82eafa-81de-4155-a71c-d46d5ac57f69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956930186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2956930186
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2418447336
Short name T298
Test name
Test status
Simulation time 550635995 ps
CPU time 0.94 seconds
Started Jun 10 06:32:32 PM PDT 24
Finished Jun 10 06:32:33 PM PDT 24
Peak memory 197284 kb
Host smart-85d72c06-791a-4911-8ab2-2242e60ff440
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418447336 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2418447336
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1435730561
Short name T66
Test name
Test status
Simulation time 461546311 ps
CPU time 0.73 seconds
Started Jun 10 06:32:33 PM PDT 24
Finished Jun 10 06:32:35 PM PDT 24
Peak memory 183808 kb
Host smart-7d092f5b-88e3-4a62-a01f-fcd0927b8e8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435730561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1435730561
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3008740173
Short name T416
Test name
Test status
Simulation time 511454373 ps
CPU time 1.29 seconds
Started Jun 10 06:32:33 PM PDT 24
Finished Jun 10 06:32:34 PM PDT 24
Peak memory 192828 kb
Host smart-409d451f-3dcd-4e38-aabb-96dd0ff02bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008740173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3008740173
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.117310531
Short name T336
Test name
Test status
Simulation time 1455812984 ps
CPU time 1.68 seconds
Started Jun 10 06:32:32 PM PDT 24
Finished Jun 10 06:32:34 PM PDT 24
Peak memory 193784 kb
Host smart-bb51fc50-8b7a-42b7-9de5-8f1f9d2c8838
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117310531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.117310531
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1205922547
Short name T293
Test name
Test status
Simulation time 796151093 ps
CPU time 2.4 seconds
Started Jun 10 06:32:30 PM PDT 24
Finished Jun 10 06:32:33 PM PDT 24
Peak memory 198424 kb
Host smart-54ec7b82-2a7d-4978-b5b2-5f3d7521bbbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205922547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1205922547
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3030515789
Short name T311
Test name
Test status
Simulation time 8373190155 ps
CPU time 5.28 seconds
Started Jun 10 06:32:34 PM PDT 24
Finished Jun 10 06:32:40 PM PDT 24
Peak memory 197980 kb
Host smart-dad45d2f-5aef-40d0-844f-e72bbd1cee3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030515789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3030515789
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.789364765
Short name T353
Test name
Test status
Simulation time 563020589 ps
CPU time 1.56 seconds
Started Jun 10 06:32:47 PM PDT 24
Finished Jun 10 06:32:49 PM PDT 24
Peak memory 196468 kb
Host smart-c31abb97-7a96-4b1c-8fad-579e58c4e174
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789364765 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.789364765
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1086007646
Short name T69
Test name
Test status
Simulation time 304360655 ps
CPU time 1.09 seconds
Started Jun 10 06:32:37 PM PDT 24
Finished Jun 10 06:32:38 PM PDT 24
Peak memory 192900 kb
Host smart-d813fe1a-7677-4fd1-ba25-15b02406d2d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086007646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1086007646
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1650378894
Short name T286
Test name
Test status
Simulation time 382959124 ps
CPU time 0.7 seconds
Started Jun 10 06:32:37 PM PDT 24
Finished Jun 10 06:32:38 PM PDT 24
Peak memory 183600 kb
Host smart-9f7eeda4-efb5-4843-ac03-b4ef41d5543f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650378894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1650378894
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.417622776
Short name T316
Test name
Test status
Simulation time 2564159361 ps
CPU time 2.56 seconds
Started Jun 10 06:32:36 PM PDT 24
Finished Jun 10 06:32:39 PM PDT 24
Peak memory 191968 kb
Host smart-f110b35e-9c93-4b0b-a59c-48cc7d8833d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417622776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.417622776
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2756557632
Short name T411
Test name
Test status
Simulation time 359094109 ps
CPU time 2.64 seconds
Started Jun 10 06:32:37 PM PDT 24
Finished Jun 10 06:32:40 PM PDT 24
Peak memory 198436 kb
Host smart-2a1e9c79-54c3-4dd5-a0d1-257b632e2542
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756557632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2756557632
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1037232585
Short name T384
Test name
Test status
Simulation time 7959139253 ps
CPU time 13.75 seconds
Started Jun 10 06:32:37 PM PDT 24
Finished Jun 10 06:32:51 PM PDT 24
Peak memory 198144 kb
Host smart-c25f7c1e-7e0f-4e2f-b787-efb17af27c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037232585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1037232585
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3645836860
Short name T383
Test name
Test status
Simulation time 397383215 ps
CPU time 0.81 seconds
Started Jun 10 06:32:40 PM PDT 24
Finished Jun 10 06:32:41 PM PDT 24
Peak memory 196748 kb
Host smart-7dbdb5d3-156d-4276-90e4-6a1d22e2f504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645836860 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3645836860
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3477152593
Short name T58
Test name
Test status
Simulation time 490771842 ps
CPU time 0.93 seconds
Started Jun 10 06:32:40 PM PDT 24
Finished Jun 10 06:32:41 PM PDT 24
Peak memory 193228 kb
Host smart-0bc153f1-474f-4e58-81f7-3e340e5808bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477152593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3477152593
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2872037853
Short name T397
Test name
Test status
Simulation time 524103741 ps
CPU time 0.92 seconds
Started Jun 10 06:32:43 PM PDT 24
Finished Jun 10 06:32:44 PM PDT 24
Peak memory 183640 kb
Host smart-009f896c-f2b2-455b-9224-0414ccd71278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872037853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2872037853
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2948583410
Short name T300
Test name
Test status
Simulation time 1511638133 ps
CPU time 1.75 seconds
Started Jun 10 06:32:41 PM PDT 24
Finished Jun 10 06:32:43 PM PDT 24
Peak memory 191792 kb
Host smart-0848d5d0-66df-4142-bd15-b198fd9bab14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948583410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2948583410
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3311490547
Short name T331
Test name
Test status
Simulation time 692499912 ps
CPU time 1.68 seconds
Started Jun 10 06:32:47 PM PDT 24
Finished Jun 10 06:32:49 PM PDT 24
Peak memory 198516 kb
Host smart-dc7bb61e-d368-4f31-ba48-a1530b6e3458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311490547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3311490547
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3599924959
Short name T308
Test name
Test status
Simulation time 8101278513 ps
CPU time 11.79 seconds
Started Jun 10 06:32:42 PM PDT 24
Finished Jun 10 06:32:54 PM PDT 24
Peak memory 198000 kb
Host smart-1fc878e7-a6e1-4797-886d-770d4b226331
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599924959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3599924959
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1973341861
Short name T57
Test name
Test status
Simulation time 387038703 ps
CPU time 0.93 seconds
Started Jun 10 06:31:45 PM PDT 24
Finished Jun 10 06:31:46 PM PDT 24
Peak memory 193264 kb
Host smart-9f30d3e2-6159-4825-ad7a-1f52f0350a22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973341861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1973341861
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1692659428
Short name T344
Test name
Test status
Simulation time 7652112862 ps
CPU time 2.76 seconds
Started Jun 10 06:31:42 PM PDT 24
Finished Jun 10 06:31:45 PM PDT 24
Peak memory 192064 kb
Host smart-11ddf231-04e3-4cac-b31e-2980570ac8e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692659428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1692659428
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2419300148
Short name T64
Test name
Test status
Simulation time 1189029627 ps
CPU time 2.61 seconds
Started Jun 10 06:31:43 PM PDT 24
Finished Jun 10 06:31:46 PM PDT 24
Peak memory 193220 kb
Host smart-e9613129-34f1-466f-a0ee-b5bd52430443
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419300148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2419300148
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.955161218
Short name T374
Test name
Test status
Simulation time 565171069 ps
CPU time 0.88 seconds
Started Jun 10 06:31:44 PM PDT 24
Finished Jun 10 06:31:45 PM PDT 24
Peak memory 196340 kb
Host smart-db124baa-597e-4d61-82c8-1bf71cd7c3c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955161218 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.955161218
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1245000312
Short name T65
Test name
Test status
Simulation time 550369797 ps
CPU time 0.79 seconds
Started Jun 10 06:31:40 PM PDT 24
Finished Jun 10 06:31:41 PM PDT 24
Peak memory 193372 kb
Host smart-a8b49116-71f2-4a44-b958-124fdfbd4be5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245000312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1245000312
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3262180782
Short name T291
Test name
Test status
Simulation time 340626042 ps
CPU time 0.91 seconds
Started Jun 10 06:31:41 PM PDT 24
Finished Jun 10 06:31:42 PM PDT 24
Peak memory 192844 kb
Host smart-d435be6c-3ade-411a-b43d-b009e2b6be3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262180782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3262180782
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3674260999
Short name T366
Test name
Test status
Simulation time 348554401 ps
CPU time 0.99 seconds
Started Jun 10 06:31:40 PM PDT 24
Finished Jun 10 06:31:42 PM PDT 24
Peak memory 183528 kb
Host smart-27f7bca4-6e41-4f5a-b277-72e8d19ce29c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674260999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3674260999
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1109507326
Short name T292
Test name
Test status
Simulation time 268097012 ps
CPU time 0.93 seconds
Started Jun 10 06:31:39 PM PDT 24
Finished Jun 10 06:31:40 PM PDT 24
Peak memory 183624 kb
Host smart-1ee0abd1-426c-4a50-969b-dbdadf9e74c1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109507326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1109507326
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3940440247
Short name T396
Test name
Test status
Simulation time 2041258291 ps
CPU time 2.12 seconds
Started Jun 10 06:31:45 PM PDT 24
Finished Jun 10 06:31:47 PM PDT 24
Peak memory 194724 kb
Host smart-7ec2020a-16a5-4b63-8cc4-e5b86a5aa474
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940440247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3940440247
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2010283617
Short name T387
Test name
Test status
Simulation time 725085374 ps
CPU time 1.92 seconds
Started Jun 10 06:31:39 PM PDT 24
Finished Jun 10 06:31:42 PM PDT 24
Peak memory 198468 kb
Host smart-36d431d8-bb35-48ed-b7d0-f3ba2d1afdcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010283617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2010283617
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3304973273
Short name T189
Test name
Test status
Simulation time 4072842114 ps
CPU time 3.25 seconds
Started Jun 10 06:31:44 PM PDT 24
Finished Jun 10 06:31:48 PM PDT 24
Peak memory 197744 kb
Host smart-5462c873-abc2-470c-93d3-8c132b897c9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304973273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3304973273
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3715593448
Short name T278
Test name
Test status
Simulation time 393021336 ps
CPU time 0.7 seconds
Started Jun 10 06:32:45 PM PDT 24
Finished Jun 10 06:32:46 PM PDT 24
Peak memory 183600 kb
Host smart-a0795ff6-f1f4-4b7a-a3d6-072b20d06794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715593448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3715593448
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.22543592
Short name T370
Test name
Test status
Simulation time 394525528 ps
CPU time 0.67 seconds
Started Jun 10 06:32:46 PM PDT 24
Finished Jun 10 06:32:47 PM PDT 24
Peak memory 183632 kb
Host smart-d0344d20-b796-4ce2-bf79-51bc31a625dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22543592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.22543592
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1378886123
Short name T330
Test name
Test status
Simulation time 523826745 ps
CPU time 0.74 seconds
Started Jun 10 06:32:43 PM PDT 24
Finished Jun 10 06:32:44 PM PDT 24
Peak memory 183640 kb
Host smart-89892cb2-9979-4ec4-835e-1e5c18fbe14c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378886123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1378886123
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3481466160
Short name T326
Test name
Test status
Simulation time 287022885 ps
CPU time 0.61 seconds
Started Jun 10 06:32:46 PM PDT 24
Finished Jun 10 06:32:47 PM PDT 24
Peak memory 183628 kb
Host smart-ea39332d-1259-4dfb-b708-2b2d20e9a03c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481466160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3481466160
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.366192479
Short name T283
Test name
Test status
Simulation time 415245704 ps
CPU time 0.72 seconds
Started Jun 10 06:32:47 PM PDT 24
Finished Jun 10 06:32:48 PM PDT 24
Peak memory 192852 kb
Host smart-ce0c8319-5807-432a-9610-ba29d2a9e958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366192479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.366192479
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3876314620
Short name T390
Test name
Test status
Simulation time 506948423 ps
CPU time 0.66 seconds
Started Jun 10 06:32:45 PM PDT 24
Finished Jun 10 06:32:46 PM PDT 24
Peak memory 183628 kb
Host smart-171bf18e-b4ff-48ed-8e89-d5a77d0a8c59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876314620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3876314620
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.545909954
Short name T327
Test name
Test status
Simulation time 455566325 ps
CPU time 0.69 seconds
Started Jun 10 06:32:43 PM PDT 24
Finished Jun 10 06:32:44 PM PDT 24
Peak memory 192860 kb
Host smart-63cf3a5d-ec35-4b7c-8d0b-47d33d42cfae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545909954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.545909954
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2009829889
Short name T322
Test name
Test status
Simulation time 418180003 ps
CPU time 1.11 seconds
Started Jun 10 06:32:46 PM PDT 24
Finished Jun 10 06:32:48 PM PDT 24
Peak memory 183620 kb
Host smart-e30b36b7-7127-4338-a5df-53d85a0c8b39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009829889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2009829889
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.216426403
Short name T360
Test name
Test status
Simulation time 303807165 ps
CPU time 0.65 seconds
Started Jun 10 06:32:49 PM PDT 24
Finished Jun 10 06:32:50 PM PDT 24
Peak memory 183596 kb
Host smart-664f1fa5-1142-4d97-8c6f-3bc9986df46f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216426403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.216426403
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.13134706
Short name T294
Test name
Test status
Simulation time 382543987 ps
CPU time 0.57 seconds
Started Jun 10 06:32:44 PM PDT 24
Finished Jun 10 06:32:45 PM PDT 24
Peak memory 183712 kb
Host smart-9a10d2a2-f641-4a4f-8647-2121585a3fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13134706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.13134706
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3719746500
Short name T402
Test name
Test status
Simulation time 562191482 ps
CPU time 1.49 seconds
Started Jun 10 06:31:47 PM PDT 24
Finished Jun 10 06:31:49 PM PDT 24
Peak memory 183672 kb
Host smart-f02b176c-0cf0-4f9d-a659-03ba5a8f0914
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719746500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3719746500
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1792888849
Short name T381
Test name
Test status
Simulation time 7293374134 ps
CPU time 11.37 seconds
Started Jun 10 06:31:52 PM PDT 24
Finished Jun 10 06:32:04 PM PDT 24
Peak memory 183952 kb
Host smart-f71fb7c6-8f51-4729-b9ca-ab4e83c4f231
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792888849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1792888849
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1023219133
Short name T349
Test name
Test status
Simulation time 733411322 ps
CPU time 0.83 seconds
Started Jun 10 06:31:48 PM PDT 24
Finished Jun 10 06:31:49 PM PDT 24
Peak memory 183660 kb
Host smart-4b1ccc11-f984-4d4c-bbc3-94ba08bce040
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023219133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1023219133
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1268205927
Short name T400
Test name
Test status
Simulation time 549789080 ps
CPU time 0.88 seconds
Started Jun 10 06:31:53 PM PDT 24
Finished Jun 10 06:31:55 PM PDT 24
Peak memory 197124 kb
Host smart-2584e6aa-044b-470f-b51e-6ca6d5251d42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268205927 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1268205927
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1570566887
Short name T53
Test name
Test status
Simulation time 405651147 ps
CPU time 1.24 seconds
Started Jun 10 06:31:48 PM PDT 24
Finished Jun 10 06:31:49 PM PDT 24
Peak memory 192904 kb
Host smart-665e205c-a79e-4282-bfed-b90b797511a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570566887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1570566887
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1995492417
Short name T309
Test name
Test status
Simulation time 535943419 ps
CPU time 0.6 seconds
Started Jun 10 06:31:46 PM PDT 24
Finished Jun 10 06:31:47 PM PDT 24
Peak memory 183604 kb
Host smart-156ac0dc-07cf-405b-822b-c463c7af7b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995492417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1995492417
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.848480588
Short name T417
Test name
Test status
Simulation time 486126234 ps
CPU time 1.33 seconds
Started Jun 10 06:31:53 PM PDT 24
Finished Jun 10 06:31:55 PM PDT 24
Peak memory 183564 kb
Host smart-73eaf15c-045e-4e75-be2e-66f2198dc289
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848480588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.848480588
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.36948106
Short name T328
Test name
Test status
Simulation time 369385514 ps
CPU time 0.76 seconds
Started Jun 10 06:31:49 PM PDT 24
Finished Jun 10 06:31:50 PM PDT 24
Peak memory 183640 kb
Host smart-ec3c791c-b632-4441-bc20-ccba9818102b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36948106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wal
k.36948106
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1038478384
Short name T392
Test name
Test status
Simulation time 1228314410 ps
CPU time 1.11 seconds
Started Jun 10 06:31:49 PM PDT 24
Finished Jun 10 06:31:51 PM PDT 24
Peak memory 192924 kb
Host smart-edeaf5ed-ebca-4084-abe2-f7d80c47b5c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038478384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1038478384
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.892692486
Short name T355
Test name
Test status
Simulation time 455772470 ps
CPU time 1.07 seconds
Started Jun 10 06:31:45 PM PDT 24
Finished Jun 10 06:31:46 PM PDT 24
Peak memory 198288 kb
Host smart-10558d31-5baa-4bbb-a50d-7ad5f7dff695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892692486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.892692486
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2779017057
Short name T187
Test name
Test status
Simulation time 8296318859 ps
CPU time 5.01 seconds
Started Jun 10 06:31:44 PM PDT 24
Finished Jun 10 06:31:49 PM PDT 24
Peak memory 197884 kb
Host smart-5665c264-3683-410a-8ef8-bd4dabfc1e48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779017057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2779017057
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3426907379
Short name T408
Test name
Test status
Simulation time 316805480 ps
CPU time 0.64 seconds
Started Jun 10 06:32:48 PM PDT 24
Finished Jun 10 06:32:49 PM PDT 24
Peak memory 192824 kb
Host smart-4652d469-4998-453c-b455-b20d0bf775a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426907379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3426907379
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3677622239
Short name T302
Test name
Test status
Simulation time 512435330 ps
CPU time 0.72 seconds
Started Jun 10 06:32:50 PM PDT 24
Finished Jun 10 06:32:51 PM PDT 24
Peak memory 183588 kb
Host smart-0c442996-a565-457f-bfa4-12c5125f8c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677622239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3677622239
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2208348518
Short name T388
Test name
Test status
Simulation time 425248805 ps
CPU time 0.82 seconds
Started Jun 10 06:32:51 PM PDT 24
Finished Jun 10 06:32:52 PM PDT 24
Peak memory 192824 kb
Host smart-ebe9d78a-a850-4df3-af89-b6d20fe8bec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208348518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2208348518
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1296456100
Short name T289
Test name
Test status
Simulation time 492055997 ps
CPU time 0.68 seconds
Started Jun 10 06:32:48 PM PDT 24
Finished Jun 10 06:32:49 PM PDT 24
Peak memory 183636 kb
Host smart-289668bb-a88c-4458-984b-21dfa88f2124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296456100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1296456100
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4063656614
Short name T319
Test name
Test status
Simulation time 453795232 ps
CPU time 0.62 seconds
Started Jun 10 06:32:50 PM PDT 24
Finished Jun 10 06:32:51 PM PDT 24
Peak memory 183632 kb
Host smart-96195d96-824a-4eb5-a52d-fba4b002d609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063656614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.4063656614
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.249131774
Short name T341
Test name
Test status
Simulation time 463957031 ps
CPU time 1.01 seconds
Started Jun 10 06:32:49 PM PDT 24
Finished Jun 10 06:32:51 PM PDT 24
Peak memory 183624 kb
Host smart-011ea3a0-00ac-4b4e-951f-8b56cacbf860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249131774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.249131774
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3845278731
Short name T281
Test name
Test status
Simulation time 451062746 ps
CPU time 1.03 seconds
Started Jun 10 06:32:50 PM PDT 24
Finished Jun 10 06:32:51 PM PDT 24
Peak memory 183632 kb
Host smart-71fbf5fc-4709-4c38-9edb-c84b2774f4de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845278731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3845278731
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2607046047
Short name T334
Test name
Test status
Simulation time 348476768 ps
CPU time 1.05 seconds
Started Jun 10 06:32:49 PM PDT 24
Finished Jun 10 06:32:51 PM PDT 24
Peak memory 192840 kb
Host smart-6ae1a999-0133-4931-8f2f-85d75a6eb250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607046047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2607046047
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4184467028
Short name T304
Test name
Test status
Simulation time 485068639 ps
CPU time 1.27 seconds
Started Jun 10 06:32:49 PM PDT 24
Finished Jun 10 06:32:50 PM PDT 24
Peak memory 183656 kb
Host smart-441230aa-47dd-4d62-a2aa-7ef9027f7686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184467028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4184467028
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3207278856
Short name T306
Test name
Test status
Simulation time 283321736 ps
CPU time 0.98 seconds
Started Jun 10 06:32:54 PM PDT 24
Finished Jun 10 06:32:55 PM PDT 24
Peak memory 183632 kb
Host smart-cad8f998-b70c-4c55-a899-527afb25b94a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207278856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3207278856
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3288786923
Short name T403
Test name
Test status
Simulation time 414539251 ps
CPU time 0.86 seconds
Started Jun 10 06:31:57 PM PDT 24
Finished Jun 10 06:31:58 PM PDT 24
Peak memory 193128 kb
Host smart-c8293084-5f09-440a-a092-d5bc4a59927a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288786923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3288786923
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3949383301
Short name T56
Test name
Test status
Simulation time 7934175483 ps
CPU time 22.44 seconds
Started Jun 10 06:31:56 PM PDT 24
Finished Jun 10 06:32:18 PM PDT 24
Peak memory 195556 kb
Host smart-7b490baf-53ed-49ff-a3b4-e6400b1f0688
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949383301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3949383301
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3815956704
Short name T335
Test name
Test status
Simulation time 1114874552 ps
CPU time 2.03 seconds
Started Jun 10 06:31:53 PM PDT 24
Finished Jun 10 06:31:56 PM PDT 24
Peak memory 193052 kb
Host smart-7aaa60b1-bb6f-4724-b52d-e00e0583fc47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815956704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3815956704
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1923004330
Short name T313
Test name
Test status
Simulation time 457613618 ps
CPU time 0.68 seconds
Started Jun 10 06:31:56 PM PDT 24
Finished Jun 10 06:31:57 PM PDT 24
Peak memory 195284 kb
Host smart-92474fd3-b183-4fb9-b32d-d0bda4936a73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923004330 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1923004330
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3695142063
Short name T405
Test name
Test status
Simulation time 536732270 ps
CPU time 0.65 seconds
Started Jun 10 06:31:54 PM PDT 24
Finished Jun 10 06:31:55 PM PDT 24
Peak memory 193340 kb
Host smart-69940408-c0ec-4787-871c-a2cdd0ce7df3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695142063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3695142063
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3914286909
Short name T361
Test name
Test status
Simulation time 491545327 ps
CPU time 0.67 seconds
Started Jun 10 06:31:52 PM PDT 24
Finished Jun 10 06:31:53 PM PDT 24
Peak memory 183652 kb
Host smart-46c7963d-24ae-44c3-bb64-3b6317b07c35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914286909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3914286909
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1692126492
Short name T368
Test name
Test status
Simulation time 430830030 ps
CPU time 0.67 seconds
Started Jun 10 06:31:53 PM PDT 24
Finished Jun 10 06:31:54 PM PDT 24
Peak memory 183568 kb
Host smart-758213e3-faad-4c20-9c0a-83c3b162a862
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692126492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1692126492
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2475826883
Short name T362
Test name
Test status
Simulation time 434652190 ps
CPU time 0.7 seconds
Started Jun 10 06:31:54 PM PDT 24
Finished Jun 10 06:31:55 PM PDT 24
Peak memory 183632 kb
Host smart-4ae0ec8c-fd5d-46e9-b3a2-e00bce90dfcb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475826883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2475826883
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3075829675
Short name T75
Test name
Test status
Simulation time 962287117 ps
CPU time 1.47 seconds
Started Jun 10 06:31:57 PM PDT 24
Finished Jun 10 06:31:58 PM PDT 24
Peak memory 192924 kb
Host smart-452b19a6-0d92-42e4-9beb-6db7ef066f6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075829675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3075829675
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2269000930
Short name T393
Test name
Test status
Simulation time 319353929 ps
CPU time 1.65 seconds
Started Jun 10 06:31:55 PM PDT 24
Finished Jun 10 06:31:56 PM PDT 24
Peak memory 198456 kb
Host smart-18a415d6-1987-4c8d-b42d-f175208d8bc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269000930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2269000930
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.392735088
Short name T369
Test name
Test status
Simulation time 4254394092 ps
CPU time 4.22 seconds
Started Jun 10 06:31:54 PM PDT 24
Finished Jun 10 06:31:58 PM PDT 24
Peak memory 197880 kb
Host smart-9d3790a1-2ae3-427e-bf55-bb1938088358
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392735088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.392735088
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4123625277
Short name T418
Test name
Test status
Simulation time 266089469 ps
CPU time 0.93 seconds
Started Jun 10 06:32:53 PM PDT 24
Finished Jun 10 06:32:55 PM PDT 24
Peak memory 183632 kb
Host smart-573fa04c-fe90-4a94-ac3b-d59d387bfe5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123625277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4123625277
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3066947559
Short name T338
Test name
Test status
Simulation time 461219256 ps
CPU time 0.93 seconds
Started Jun 10 06:32:54 PM PDT 24
Finished Jun 10 06:32:55 PM PDT 24
Peak memory 183604 kb
Host smart-00318667-43c4-418f-a2a4-68d384442408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066947559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3066947559
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1420732822
Short name T373
Test name
Test status
Simulation time 490757759 ps
CPU time 1.25 seconds
Started Jun 10 06:32:54 PM PDT 24
Finished Jun 10 06:32:56 PM PDT 24
Peak memory 183632 kb
Host smart-0539a076-e23f-418e-be06-4ca454744884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420732822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1420732822
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1445194528
Short name T395
Test name
Test status
Simulation time 374265979 ps
CPU time 1.07 seconds
Started Jun 10 06:32:54 PM PDT 24
Finished Jun 10 06:32:56 PM PDT 24
Peak memory 192828 kb
Host smart-7263dff0-1857-4630-acf2-ae8aee6f9d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445194528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1445194528
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2906176223
Short name T367
Test name
Test status
Simulation time 340087836 ps
CPU time 1.04 seconds
Started Jun 10 06:32:52 PM PDT 24
Finished Jun 10 06:32:53 PM PDT 24
Peak memory 192808 kb
Host smart-d9196b2e-f036-4772-beb4-a58d2ebb52e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906176223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2906176223
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.118560930
Short name T343
Test name
Test status
Simulation time 474609882 ps
CPU time 0.89 seconds
Started Jun 10 06:32:54 PM PDT 24
Finished Jun 10 06:32:55 PM PDT 24
Peak memory 183580 kb
Host smart-b0ded580-7ebe-443c-8dc0-3ec8c51b04e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118560930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.118560930
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.186794085
Short name T409
Test name
Test status
Simulation time 440302331 ps
CPU time 0.69 seconds
Started Jun 10 06:32:58 PM PDT 24
Finished Jun 10 06:32:59 PM PDT 24
Peak memory 192852 kb
Host smart-39e98f58-5950-475c-b152-9ead8aff766c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186794085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.186794085
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.514712488
Short name T359
Test name
Test status
Simulation time 411055084 ps
CPU time 1.2 seconds
Started Jun 10 06:32:55 PM PDT 24
Finished Jun 10 06:32:57 PM PDT 24
Peak memory 183636 kb
Host smart-6c1b8f48-4ad1-4216-9f34-38b1e0364564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514712488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.514712488
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3364925617
Short name T282
Test name
Test status
Simulation time 464387832 ps
CPU time 0.72 seconds
Started Jun 10 06:32:52 PM PDT 24
Finished Jun 10 06:32:53 PM PDT 24
Peak memory 183568 kb
Host smart-c6210bdc-60ed-4ea0-a538-6fed7e22516e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364925617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3364925617
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1490474164
Short name T284
Test name
Test status
Simulation time 499479262 ps
CPU time 0.92 seconds
Started Jun 10 06:32:54 PM PDT 24
Finished Jun 10 06:32:56 PM PDT 24
Peak memory 183524 kb
Host smart-a8716f67-dc48-415d-9f3e-c56ffba56179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490474164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1490474164
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1973619201
Short name T305
Test name
Test status
Simulation time 425068324 ps
CPU time 1.43 seconds
Started Jun 10 06:32:03 PM PDT 24
Finished Jun 10 06:32:05 PM PDT 24
Peak memory 196212 kb
Host smart-85591e51-bbb9-4107-9914-9081b18eb6a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973619201 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1973619201
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1711243619
Short name T67
Test name
Test status
Simulation time 458746118 ps
CPU time 0.76 seconds
Started Jun 10 06:31:59 PM PDT 24
Finished Jun 10 06:32:00 PM PDT 24
Peak memory 192872 kb
Host smart-6e757d45-bcfb-43e5-9f86-43dc36c08788
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711243619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1711243619
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2538709257
Short name T363
Test name
Test status
Simulation time 421122493 ps
CPU time 1.08 seconds
Started Jun 10 06:31:59 PM PDT 24
Finished Jun 10 06:32:00 PM PDT 24
Peak memory 183636 kb
Host smart-ea1c2aee-9d8b-4c1c-99b3-c4cfe8487849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538709257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2538709257
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3506107825
Short name T377
Test name
Test status
Simulation time 2835449301 ps
CPU time 3.99 seconds
Started Jun 10 06:32:00 PM PDT 24
Finished Jun 10 06:32:04 PM PDT 24
Peak memory 194300 kb
Host smart-d370e268-05ad-483d-8c83-8e6548f152ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506107825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3506107825
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3064682787
Short name T288
Test name
Test status
Simulation time 644565366 ps
CPU time 2.42 seconds
Started Jun 10 06:32:02 PM PDT 24
Finished Jun 10 06:32:05 PM PDT 24
Peak memory 198464 kb
Host smart-ecc084e8-d83d-4cf5-a024-7a9e36d26e26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064682787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3064682787
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.425060877
Short name T350
Test name
Test status
Simulation time 8320398762 ps
CPU time 4.4 seconds
Started Jun 10 06:32:00 PM PDT 24
Finished Jun 10 06:32:05 PM PDT 24
Peak memory 198088 kb
Host smart-c8eeb456-6640-4aca-a5cf-d3b6d0f5de95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425060877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.425060877
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2755801028
Short name T404
Test name
Test status
Simulation time 458919466 ps
CPU time 1.37 seconds
Started Jun 10 06:32:03 PM PDT 24
Finished Jun 10 06:32:04 PM PDT 24
Peak memory 197488 kb
Host smart-4d81786f-9dae-4089-b079-031d061dc6d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755801028 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2755801028
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1604806283
Short name T401
Test name
Test status
Simulation time 415169806 ps
CPU time 0.74 seconds
Started Jun 10 06:32:03 PM PDT 24
Finished Jun 10 06:32:04 PM PDT 24
Peak memory 183636 kb
Host smart-3a37bd7f-4189-4f8f-99eb-7ac77282eb78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604806283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1604806283
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.4182706600
Short name T320
Test name
Test status
Simulation time 2640485971 ps
CPU time 2.92 seconds
Started Jun 10 06:32:04 PM PDT 24
Finished Jun 10 06:32:07 PM PDT 24
Peak memory 194672 kb
Host smart-5493a2e5-fee4-43be-ba3c-d2ccb1723b47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182706600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.4182706600
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2283299358
Short name T342
Test name
Test status
Simulation time 422729542 ps
CPU time 1.31 seconds
Started Jun 10 06:32:02 PM PDT 24
Finished Jun 10 06:32:04 PM PDT 24
Peak memory 198288 kb
Host smart-a22ad230-ef45-4539-ba0a-19cd989a2116
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283299358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2283299358
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2241557953
Short name T371
Test name
Test status
Simulation time 7924532321 ps
CPU time 12.18 seconds
Started Jun 10 06:32:02 PM PDT 24
Finished Jun 10 06:32:15 PM PDT 24
Peak memory 198012 kb
Host smart-2ac0bc2d-c09c-490d-9196-b6f8888288e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241557953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2241557953
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1932452581
Short name T332
Test name
Test status
Simulation time 475288401 ps
CPU time 1.08 seconds
Started Jun 10 06:32:09 PM PDT 24
Finished Jun 10 06:32:10 PM PDT 24
Peak memory 195880 kb
Host smart-a492a4f8-a8c1-4496-bd2b-98773bebfbb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932452581 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1932452581
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1756494436
Short name T414
Test name
Test status
Simulation time 492115882 ps
CPU time 0.76 seconds
Started Jun 10 06:32:09 PM PDT 24
Finished Jun 10 06:32:10 PM PDT 24
Peak memory 193216 kb
Host smart-41a99c1d-a604-408d-81ac-641bcd6d5b91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756494436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1756494436
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2083811278
Short name T345
Test name
Test status
Simulation time 374325748 ps
CPU time 0.8 seconds
Started Jun 10 06:32:08 PM PDT 24
Finished Jun 10 06:32:09 PM PDT 24
Peak memory 183616 kb
Host smart-5856a9bb-8a8a-43b8-ae24-c4947342dc4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083811278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2083811278
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2430361700
Short name T357
Test name
Test status
Simulation time 3044607154 ps
CPU time 1.26 seconds
Started Jun 10 06:32:08 PM PDT 24
Finished Jun 10 06:32:10 PM PDT 24
Peak memory 194880 kb
Host smart-65c12ad9-644f-4b6f-8c0b-3b6e97ac2847
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430361700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2430361700
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3528712860
Short name T382
Test name
Test status
Simulation time 410520798 ps
CPU time 2.26 seconds
Started Jun 10 06:32:08 PM PDT 24
Finished Jun 10 06:32:10 PM PDT 24
Peak memory 198460 kb
Host smart-1ec9ae54-5cfd-42d1-87fd-66ab92d23ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528712860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3528712860
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1416987597
Short name T190
Test name
Test status
Simulation time 8511384383 ps
CPU time 6.81 seconds
Started Jun 10 06:32:10 PM PDT 24
Finished Jun 10 06:32:17 PM PDT 24
Peak memory 198180 kb
Host smart-c92aea86-5fef-46fb-bf43-8c1b009e1d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416987597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1416987597
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1360743857
Short name T321
Test name
Test status
Simulation time 453282830 ps
CPU time 1.28 seconds
Started Jun 10 06:32:14 PM PDT 24
Finished Jun 10 06:32:15 PM PDT 24
Peak memory 196024 kb
Host smart-5f362108-8951-4b60-8927-758738b463de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360743857 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1360743857
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2837541789
Short name T54
Test name
Test status
Simulation time 532896403 ps
CPU time 0.61 seconds
Started Jun 10 06:32:12 PM PDT 24
Finished Jun 10 06:32:13 PM PDT 24
Peak memory 193292 kb
Host smart-085550a2-522f-4727-ad94-ccb9c8f80799
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837541789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2837541789
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.443073055
Short name T351
Test name
Test status
Simulation time 503645806 ps
CPU time 0.79 seconds
Started Jun 10 06:32:14 PM PDT 24
Finished Jun 10 06:32:15 PM PDT 24
Peak memory 183636 kb
Host smart-e0302ebe-b62f-4e0d-a9ed-45676a68bfd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443073055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.443073055
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4221281659
Short name T72
Test name
Test status
Simulation time 1218249516 ps
CPU time 3.8 seconds
Started Jun 10 06:32:12 PM PDT 24
Finished Jun 10 06:32:17 PM PDT 24
Peak memory 183704 kb
Host smart-d9729567-fd69-463f-9c1e-08dc5a150ccd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221281659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4221281659
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2232595927
Short name T318
Test name
Test status
Simulation time 547385792 ps
CPU time 1.97 seconds
Started Jun 10 06:32:13 PM PDT 24
Finished Jun 10 06:32:15 PM PDT 24
Peak memory 198476 kb
Host smart-5fc9f53e-8e84-431c-8ec2-6b77dec5785e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232595927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2232595927
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2333101806
Short name T186
Test name
Test status
Simulation time 4794700575 ps
CPU time 4.74 seconds
Started Jun 10 06:32:14 PM PDT 24
Finished Jun 10 06:32:19 PM PDT 24
Peak memory 197832 kb
Host smart-2f97bfb9-1e2d-41f1-910c-62231ba8540c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333101806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2333101806
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2770747882
Short name T337
Test name
Test status
Simulation time 536445264 ps
CPU time 0.98 seconds
Started Jun 10 06:32:16 PM PDT 24
Finished Jun 10 06:32:17 PM PDT 24
Peak memory 196396 kb
Host smart-993aa961-1919-492f-802f-aa6c08633479
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770747882 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2770747882
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2511577589
Short name T60
Test name
Test status
Simulation time 408039046 ps
CPU time 1.17 seconds
Started Jun 10 06:32:16 PM PDT 24
Finished Jun 10 06:32:17 PM PDT 24
Peak memory 192980 kb
Host smart-a50403f3-65e4-4474-b9c5-50ac3bddc71a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511577589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2511577589
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3404513911
Short name T295
Test name
Test status
Simulation time 515771799 ps
CPU time 1.43 seconds
Started Jun 10 06:32:11 PM PDT 24
Finished Jun 10 06:32:13 PM PDT 24
Peak memory 183640 kb
Host smart-42afdd3f-1f10-4c29-a98d-6417972ae3e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404513911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3404513911
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1459867587
Short name T399
Test name
Test status
Simulation time 2776448016 ps
CPU time 6.02 seconds
Started Jun 10 06:32:17 PM PDT 24
Finished Jun 10 06:32:24 PM PDT 24
Peak memory 193912 kb
Host smart-b0fb7d6a-7234-464b-9aa3-c75b0cb1252d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459867587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1459867587
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1815983989
Short name T378
Test name
Test status
Simulation time 751065743 ps
CPU time 2.27 seconds
Started Jun 10 06:32:14 PM PDT 24
Finished Jun 10 06:32:17 PM PDT 24
Peak memory 198440 kb
Host smart-a7260cce-2db3-418b-a21f-084135375453
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815983989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1815983989
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1201479601
Short name T246
Test name
Test status
Simulation time 28150051900 ps
CPU time 40.02 seconds
Started Jun 10 06:29:09 PM PDT 24
Finished Jun 10 06:29:49 PM PDT 24
Peak memory 191920 kb
Host smart-3f841159-72c7-449b-a3f6-b9be12ef0f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201479601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1201479601
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2643807769
Short name T197
Test name
Test status
Simulation time 416459071 ps
CPU time 0.73 seconds
Started Jun 10 06:29:04 PM PDT 24
Finished Jun 10 06:29:05 PM PDT 24
Peak memory 191792 kb
Host smart-d03ae910-5a57-4bba-b203-e7dcffa931a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643807769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2643807769
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1307792399
Short name T266
Test name
Test status
Simulation time 34853633540 ps
CPU time 58.88 seconds
Started Jun 10 06:29:18 PM PDT 24
Finished Jun 10 06:30:17 PM PDT 24
Peak memory 191852 kb
Host smart-75888f69-a73a-40d6-a74d-0ecc264f36be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307792399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1307792399
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.449834597
Short name T20
Test name
Test status
Simulation time 8020929466 ps
CPU time 6.85 seconds
Started Jun 10 06:29:17 PM PDT 24
Finished Jun 10 06:29:24 PM PDT 24
Peak memory 215928 kb
Host smart-54b0fcec-b002-4921-9014-6991a5a86c3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449834597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.449834597
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3324700552
Short name T23
Test name
Test status
Simulation time 491509125 ps
CPU time 1.39 seconds
Started Jun 10 06:29:15 PM PDT 24
Finished Jun 10 06:29:17 PM PDT 24
Peak memory 191820 kb
Host smart-58bb9f6c-53f6-48e3-b79a-11c67b92e487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324700552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3324700552
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2895688742
Short name T256
Test name
Test status
Simulation time 10075000589 ps
CPU time 2.91 seconds
Started Jun 10 06:29:52 PM PDT 24
Finished Jun 10 06:29:56 PM PDT 24
Peak memory 191944 kb
Host smart-ef44c75d-0eba-46b4-ba70-4424d5473601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895688742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2895688742
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3534815277
Short name T217
Test name
Test status
Simulation time 578271238 ps
CPU time 0.85 seconds
Started Jun 10 06:29:49 PM PDT 24
Finished Jun 10 06:29:50 PM PDT 24
Peak memory 191768 kb
Host smart-6f3fdb52-605e-4ebd-bd76-42c403b2df08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534815277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3534815277
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3810541458
Short name T201
Test name
Test status
Simulation time 11702575382 ps
CPU time 5.2 seconds
Started Jun 10 06:29:57 PM PDT 24
Finished Jun 10 06:30:03 PM PDT 24
Peak memory 191904 kb
Host smart-a52b166a-44a0-4514-b2cf-b40383a2d9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810541458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3810541458
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.196279741
Short name T258
Test name
Test status
Simulation time 451510851 ps
CPU time 1.19 seconds
Started Jun 10 06:29:58 PM PDT 24
Finished Jun 10 06:29:59 PM PDT 24
Peak memory 191808 kb
Host smart-df6e082f-b702-43da-a9f1-ab4c3665f15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196279741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.196279741
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3876664305
Short name T226
Test name
Test status
Simulation time 27846452926 ps
CPU time 42.95 seconds
Started Jun 10 06:29:56 PM PDT 24
Finished Jun 10 06:30:39 PM PDT 24
Peak memory 191944 kb
Host smart-73860fa2-6f0b-4886-9974-bcf438cd0fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876664305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3876664305
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1763130842
Short name T231
Test name
Test status
Simulation time 606727917 ps
CPU time 1.54 seconds
Started Jun 10 06:29:56 PM PDT 24
Finished Jun 10 06:29:58 PM PDT 24
Peak memory 191712 kb
Host smart-6e26c4e6-592e-4503-99a2-6d0933176321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763130842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1763130842
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.829377609
Short name T41
Test name
Test status
Simulation time 49902973820 ps
CPU time 57.97 seconds
Started Jun 10 06:30:05 PM PDT 24
Finished Jun 10 06:31:04 PM PDT 24
Peak memory 191940 kb
Host smart-384eed0c-cf88-45d6-a943-a98be9b8b836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829377609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.829377609
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.492996325
Short name T257
Test name
Test status
Simulation time 431679416 ps
CPU time 0.91 seconds
Started Jun 10 06:29:59 PM PDT 24
Finished Jun 10 06:30:01 PM PDT 24
Peak memory 191804 kb
Host smart-4a9d76a7-394f-4dd0-9e72-abbebe7ed831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492996325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.492996325
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.456672959
Short name T207
Test name
Test status
Simulation time 5429967197 ps
CPU time 2.86 seconds
Started Jun 10 06:30:05 PM PDT 24
Finished Jun 10 06:30:08 PM PDT 24
Peak memory 191892 kb
Host smart-7d621a1a-ce2e-41c1-b9e3-6fe4c58bef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456672959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.456672959
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2716148508
Short name T261
Test name
Test status
Simulation time 377571922 ps
CPU time 0.76 seconds
Started Jun 10 06:30:04 PM PDT 24
Finished Jun 10 06:30:05 PM PDT 24
Peak memory 191772 kb
Host smart-897b7dd9-8acd-452a-8fa7-e2eb6bfaa796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716148508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2716148508
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1805517540
Short name T175
Test name
Test status
Simulation time 492458846 ps
CPU time 0.82 seconds
Started Jun 10 06:30:08 PM PDT 24
Finished Jun 10 06:30:09 PM PDT 24
Peak memory 196576 kb
Host smart-fdb410b5-e773-4275-aed1-421388954193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805517540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1805517540
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3770279336
Short name T251
Test name
Test status
Simulation time 5995010486 ps
CPU time 3.03 seconds
Started Jun 10 06:30:09 PM PDT 24
Finished Jun 10 06:30:13 PM PDT 24
Peak memory 191920 kb
Host smart-e31057fd-a84f-4182-bd6f-b31fb3e1c8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770279336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3770279336
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.389109231
Short name T216
Test name
Test status
Simulation time 614374165 ps
CPU time 0.82 seconds
Started Jun 10 06:30:09 PM PDT 24
Finished Jun 10 06:30:10 PM PDT 24
Peak memory 191824 kb
Host smart-c0691bcd-158a-4af4-9f8e-ffe83c42d5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389109231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.389109231
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1681240603
Short name T253
Test name
Test status
Simulation time 48055899500 ps
CPU time 19.7 seconds
Started Jun 10 06:30:08 PM PDT 24
Finished Jun 10 06:30:28 PM PDT 24
Peak memory 191912 kb
Host smart-f108accf-c757-4631-9b3e-324104fa154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681240603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1681240603
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2935551627
Short name T269
Test name
Test status
Simulation time 535892322 ps
CPU time 0.66 seconds
Started Jun 10 06:30:08 PM PDT 24
Finished Jun 10 06:30:09 PM PDT 24
Peak memory 191788 kb
Host smart-a3b38d01-2411-4b04-ae31-28b17cf6a984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935551627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2935551627
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3833516823
Short name T44
Test name
Test status
Simulation time 39946107961 ps
CPU time 16.8 seconds
Started Jun 10 06:30:12 PM PDT 24
Finished Jun 10 06:30:29 PM PDT 24
Peak memory 191924 kb
Host smart-c8d993b7-c9db-4f8b-ac6a-f556db5ae5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833516823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3833516823
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2898106106
Short name T196
Test name
Test status
Simulation time 406149116 ps
CPU time 0.73 seconds
Started Jun 10 06:30:11 PM PDT 24
Finished Jun 10 06:30:13 PM PDT 24
Peak memory 196560 kb
Host smart-963dadf3-7c93-4745-82c5-52946b336701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898106106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2898106106
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.4141554328
Short name T264
Test name
Test status
Simulation time 32227000163 ps
CPU time 49.22 seconds
Started Jun 10 06:30:15 PM PDT 24
Finished Jun 10 06:31:05 PM PDT 24
Peak memory 191916 kb
Host smart-0eb0475a-a84d-47ee-9a9e-f8e53f37d6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141554328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.4141554328
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3494511325
Short name T250
Test name
Test status
Simulation time 460962137 ps
CPU time 1.29 seconds
Started Jun 10 06:30:15 PM PDT 24
Finished Jun 10 06:30:17 PM PDT 24
Peak memory 191788 kb
Host smart-d7d13f32-7d23-4a16-ba65-7f79f489f3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494511325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3494511325
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2888323841
Short name T260
Test name
Test status
Simulation time 25813504092 ps
CPU time 38.64 seconds
Started Jun 10 06:30:16 PM PDT 24
Finished Jun 10 06:30:54 PM PDT 24
Peak memory 191944 kb
Host smart-3e222d6e-2c2c-4a55-a192-5f8319627f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888323841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2888323841
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.461027597
Short name T228
Test name
Test status
Simulation time 537770387 ps
CPU time 1.4 seconds
Started Jun 10 06:30:16 PM PDT 24
Finished Jun 10 06:30:17 PM PDT 24
Peak memory 191788 kb
Host smart-9a76aed3-71f9-4b9a-bc5c-4854accff98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461027597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.461027597
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2156383101
Short name T104
Test name
Test status
Simulation time 458996708 ps
CPU time 1.33 seconds
Started Jun 10 06:29:22 PM PDT 24
Finished Jun 10 06:29:24 PM PDT 24
Peak memory 196712 kb
Host smart-e810e637-9300-4ddb-a4ac-2051f2386785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156383101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2156383101
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2670069493
Short name T234
Test name
Test status
Simulation time 34502931778 ps
CPU time 26.83 seconds
Started Jun 10 06:29:23 PM PDT 24
Finished Jun 10 06:29:50 PM PDT 24
Peak memory 191872 kb
Host smart-fd15f0a3-f6e6-4407-8f3a-ff64aab9fd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670069493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2670069493
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1844089415
Short name T11
Test name
Test status
Simulation time 7760224395 ps
CPU time 7.4 seconds
Started Jun 10 06:29:25 PM PDT 24
Finished Jun 10 06:29:32 PM PDT 24
Peak memory 215896 kb
Host smart-184f666a-4eae-4c3e-9a74-75129ca3d859
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844089415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1844089415
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3033534049
Short name T50
Test name
Test status
Simulation time 562200106 ps
CPU time 1.44 seconds
Started Jun 10 06:29:22 PM PDT 24
Finished Jun 10 06:29:23 PM PDT 24
Peak memory 191788 kb
Host smart-b6557c31-4ddf-47be-84e7-d376330f266d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033534049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3033534049
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.771366862
Short name T227
Test name
Test status
Simulation time 56490708290 ps
CPU time 83.94 seconds
Started Jun 10 06:30:25 PM PDT 24
Finished Jun 10 06:31:49 PM PDT 24
Peak memory 191984 kb
Host smart-c2efc88a-fbf5-4075-a087-05a01d7da3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771366862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.771366862
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2831276331
Short name T203
Test name
Test status
Simulation time 427406776 ps
CPU time 1.19 seconds
Started Jun 10 06:30:25 PM PDT 24
Finished Jun 10 06:30:27 PM PDT 24
Peak memory 191800 kb
Host smart-6c80ff41-159f-4266-b176-85a956f868d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831276331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2831276331
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2373947777
Short name T273
Test name
Test status
Simulation time 23657338073 ps
CPU time 16.89 seconds
Started Jun 10 06:30:30 PM PDT 24
Finished Jun 10 06:30:47 PM PDT 24
Peak memory 191884 kb
Host smart-9fb40be2-316e-445d-9832-39aa47679510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373947777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2373947777
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.4221623972
Short name T204
Test name
Test status
Simulation time 468921447 ps
CPU time 0.74 seconds
Started Jun 10 06:30:29 PM PDT 24
Finished Jun 10 06:30:30 PM PDT 24
Peak memory 191776 kb
Host smart-11f3dc48-c8e4-4632-aa5d-2160a2f3794e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221623972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4221623972
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3442602719
Short name T275
Test name
Test status
Simulation time 38045824819 ps
CPU time 53.19 seconds
Started Jun 10 06:30:24 PM PDT 24
Finished Jun 10 06:31:18 PM PDT 24
Peak memory 191908 kb
Host smart-2bdb310c-78c2-4996-afb7-f853c01fded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442602719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3442602719
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1951273762
Short name T262
Test name
Test status
Simulation time 374942398 ps
CPU time 1.16 seconds
Started Jun 10 06:30:25 PM PDT 24
Finished Jun 10 06:30:26 PM PDT 24
Peak memory 196564 kb
Host smart-766964e0-12d5-4073-a786-b3d8c4f20905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951273762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1951273762
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.4013813198
Short name T205
Test name
Test status
Simulation time 40478450914 ps
CPU time 15 seconds
Started Jun 10 06:30:27 PM PDT 24
Finished Jun 10 06:30:42 PM PDT 24
Peak memory 191868 kb
Host smart-bf9eff12-36f7-4cb5-a1c8-6abe8cacee33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013813198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.4013813198
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3106911890
Short name T236
Test name
Test status
Simulation time 461294214 ps
CPU time 0.7 seconds
Started Jun 10 06:30:29 PM PDT 24
Finished Jun 10 06:30:30 PM PDT 24
Peak memory 196536 kb
Host smart-5417aa49-c0c6-4fab-9597-e26018b4758b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106911890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3106911890
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1949777053
Short name T272
Test name
Test status
Simulation time 23165336041 ps
CPU time 4.6 seconds
Started Jun 10 06:30:33 PM PDT 24
Finished Jun 10 06:30:38 PM PDT 24
Peak memory 191912 kb
Host smart-0eabd2bd-9101-444d-ad37-88bccb4bb3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949777053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1949777053
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1763357030
Short name T224
Test name
Test status
Simulation time 480668775 ps
CPU time 1.27 seconds
Started Jun 10 06:30:33 PM PDT 24
Finished Jun 10 06:30:34 PM PDT 24
Peak memory 191756 kb
Host smart-5d76d491-b42a-40ea-91ed-d4a0a7a71cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763357030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1763357030
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1842288815
Short name T1
Test name
Test status
Simulation time 28502739037 ps
CPU time 40.98 seconds
Started Jun 10 06:30:36 PM PDT 24
Finished Jun 10 06:31:17 PM PDT 24
Peak memory 191932 kb
Host smart-63a51305-2075-417e-a7d5-2e76623e7a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842288815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1842288815
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1593717799
Short name T270
Test name
Test status
Simulation time 586136291 ps
CPU time 0.64 seconds
Started Jun 10 06:30:39 PM PDT 24
Finished Jun 10 06:30:40 PM PDT 24
Peak memory 196568 kb
Host smart-c26b8ace-f288-487e-806d-ed6cc5cfbea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593717799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1593717799
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3285798498
Short name T180
Test name
Test status
Simulation time 557298992 ps
CPU time 1.03 seconds
Started Jun 10 06:30:36 PM PDT 24
Finished Jun 10 06:30:37 PM PDT 24
Peak memory 196516 kb
Host smart-f7d78efa-40de-41b9-9eea-90cc76988c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285798498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3285798498
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1020224675
Short name T219
Test name
Test status
Simulation time 37472523611 ps
CPU time 48.35 seconds
Started Jun 10 06:30:36 PM PDT 24
Finished Jun 10 06:31:25 PM PDT 24
Peak memory 191852 kb
Host smart-13e2fff9-2fb4-4e11-bfe1-d8956ea08fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020224675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1020224675
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.886874295
Short name T237
Test name
Test status
Simulation time 496883909 ps
CPU time 1.35 seconds
Started Jun 10 06:30:39 PM PDT 24
Finished Jun 10 06:30:41 PM PDT 24
Peak memory 196592 kb
Host smart-570af6c2-7cf6-4ad1-b8bb-96f726729ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886874295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.886874295
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3758400294
Short name T176
Test name
Test status
Simulation time 562744466 ps
CPU time 0.84 seconds
Started Jun 10 06:30:38 PM PDT 24
Finished Jun 10 06:30:39 PM PDT 24
Peak memory 196540 kb
Host smart-52c56faa-3a7f-4ca5-99ac-57290921f0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758400294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3758400294
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2405749379
Short name T218
Test name
Test status
Simulation time 27630453879 ps
CPU time 10.34 seconds
Started Jun 10 06:30:39 PM PDT 24
Finished Jun 10 06:30:50 PM PDT 24
Peak memory 191904 kb
Host smart-f93eee84-0a99-4e03-bb91-b7fa17016664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405749379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2405749379
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3625292338
Short name T222
Test name
Test status
Simulation time 562585168 ps
CPU time 1 seconds
Started Jun 10 06:30:41 PM PDT 24
Finished Jun 10 06:30:42 PM PDT 24
Peak memory 191792 kb
Host smart-fbedc269-aa89-4f63-8887-e4af0b6d6b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625292338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3625292338
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3002035335
Short name T177
Test name
Test status
Simulation time 574675034 ps
CPU time 0.88 seconds
Started Jun 10 06:30:43 PM PDT 24
Finished Jun 10 06:30:45 PM PDT 24
Peak memory 196656 kb
Host smart-689d512b-7d6d-4b2c-865e-56092073a456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002035335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3002035335
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3342721521
Short name T235
Test name
Test status
Simulation time 2032367107 ps
CPU time 1.33 seconds
Started Jun 10 06:30:39 PM PDT 24
Finished Jun 10 06:30:41 PM PDT 24
Peak memory 191808 kb
Host smart-a18bf301-4462-4e78-a65e-4275a0b7aa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342721521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3342721521
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2188159661
Short name T265
Test name
Test status
Simulation time 351781174 ps
CPU time 0.71 seconds
Started Jun 10 06:30:38 PM PDT 24
Finished Jun 10 06:30:38 PM PDT 24
Peak memory 191768 kb
Host smart-32efacfa-0d2c-463b-a302-ae33a6893898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188159661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2188159661
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.368506337
Short name T241
Test name
Test status
Simulation time 1281073139 ps
CPU time 1.8 seconds
Started Jun 10 06:30:43 PM PDT 24
Finished Jun 10 06:30:45 PM PDT 24
Peak memory 191832 kb
Host smart-004a43c0-b778-485f-95cd-ed374a62bd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368506337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.368506337
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2798511699
Short name T3
Test name
Test status
Simulation time 510617601 ps
CPU time 1.27 seconds
Started Jun 10 06:30:43 PM PDT 24
Finished Jun 10 06:30:44 PM PDT 24
Peak memory 191796 kb
Host smart-740b2237-1ef1-42d0-bdf6-5b8be7e03a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798511699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2798511699
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.968535332
Short name T183
Test name
Test status
Simulation time 550452579872 ps
CPU time 187.48 seconds
Started Jun 10 06:30:45 PM PDT 24
Finished Jun 10 06:33:52 PM PDT 24
Peak memory 198260 kb
Host smart-48b9f8c0-27b1-402c-892b-7c9aa2e85a5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968535332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.968535332
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1253460456
Short name T245
Test name
Test status
Simulation time 29505970976 ps
CPU time 39.92 seconds
Started Jun 10 06:29:28 PM PDT 24
Finished Jun 10 06:30:08 PM PDT 24
Peak memory 195972 kb
Host smart-44524b66-e2dd-41c6-943a-f057ab446431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253460456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1253460456
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.4129576163
Short name T19
Test name
Test status
Simulation time 7974336518 ps
CPU time 1.9 seconds
Started Jun 10 06:29:31 PM PDT 24
Finished Jun 10 06:29:33 PM PDT 24
Peak memory 215892 kb
Host smart-888713c2-dc29-4f8c-bf62-b2e8cfdae513
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129576163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.4129576163
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.93889627
Short name T200
Test name
Test status
Simulation time 412885329 ps
CPU time 0.76 seconds
Started Jun 10 06:29:24 PM PDT 24
Finished Jun 10 06:29:25 PM PDT 24
Peak memory 191808 kb
Host smart-8390ad5a-397e-4cfc-98df-c2170040b21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93889627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.93889627
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4199853990
Short name T268
Test name
Test status
Simulation time 16118588431 ps
CPU time 12.71 seconds
Started Jun 10 06:30:44 PM PDT 24
Finished Jun 10 06:30:57 PM PDT 24
Peak memory 191948 kb
Host smart-1d15affd-b871-4dba-864b-2185a53a121a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199853990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4199853990
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1732172828
Short name T198
Test name
Test status
Simulation time 408962330 ps
CPU time 0.75 seconds
Started Jun 10 06:30:44 PM PDT 24
Finished Jun 10 06:30:45 PM PDT 24
Peak memory 196588 kb
Host smart-98e12edb-e35e-4e89-947b-075d17a74ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732172828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1732172828
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1694499094
Short name T267
Test name
Test status
Simulation time 32024667659 ps
CPU time 12.92 seconds
Started Jun 10 06:30:48 PM PDT 24
Finished Jun 10 06:31:01 PM PDT 24
Peak memory 191888 kb
Host smart-c34f32cd-a8eb-43d9-ae5c-61fd46ecfc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694499094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1694499094
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2966426531
Short name T259
Test name
Test status
Simulation time 538856411 ps
CPU time 0.91 seconds
Started Jun 10 06:30:46 PM PDT 24
Finished Jun 10 06:30:48 PM PDT 24
Peak memory 191808 kb
Host smart-647a4b65-244d-419a-b325-76b04101712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966426531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2966426531
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3318305591
Short name T167
Test name
Test status
Simulation time 414005287 ps
CPU time 1.15 seconds
Started Jun 10 06:30:51 PM PDT 24
Finished Jun 10 06:30:52 PM PDT 24
Peak memory 196540 kb
Host smart-ce17395c-4533-4d76-badb-25e6229842ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318305591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3318305591
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1140983796
Short name T210
Test name
Test status
Simulation time 29623581301 ps
CPU time 3.3 seconds
Started Jun 10 06:30:52 PM PDT 24
Finished Jun 10 06:30:56 PM PDT 24
Peak memory 196920 kb
Host smart-8e0d5bcd-86a0-4c11-b76d-d7eee52da1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140983796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1140983796
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3778744670
Short name T240
Test name
Test status
Simulation time 429148835 ps
CPU time 1.16 seconds
Started Jun 10 06:30:51 PM PDT 24
Finished Jun 10 06:30:52 PM PDT 24
Peak memory 196584 kb
Host smart-d9f9d0f8-d175-428f-80b1-b51645807566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778744670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3778744670
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1992782545
Short name T213
Test name
Test status
Simulation time 38372680071 ps
CPU time 13.6 seconds
Started Jun 10 06:30:54 PM PDT 24
Finished Jun 10 06:31:08 PM PDT 24
Peak memory 191916 kb
Host smart-488cbacc-e1b3-4945-bdd4-7c80bfe72d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992782545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1992782545
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1903812734
Short name T206
Test name
Test status
Simulation time 597224009 ps
CPU time 1.53 seconds
Started Jun 10 06:30:53 PM PDT 24
Finished Jun 10 06:30:55 PM PDT 24
Peak memory 191768 kb
Host smart-43685dbe-2a17-4f9f-93ca-8d45f3dc168d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903812734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1903812734
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3924387459
Short name T156
Test name
Test status
Simulation time 396074204 ps
CPU time 0.73 seconds
Started Jun 10 06:30:58 PM PDT 24
Finished Jun 10 06:30:59 PM PDT 24
Peak memory 196652 kb
Host smart-b885f3e4-5995-4ed7-8e31-62530d4485b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924387459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3924387459
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1925510302
Short name T221
Test name
Test status
Simulation time 6287219444 ps
CPU time 9.71 seconds
Started Jun 10 06:31:01 PM PDT 24
Finished Jun 10 06:31:11 PM PDT 24
Peak memory 191912 kb
Host smart-97fdb976-85be-4faa-b79a-c4cca0afc74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925510302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1925510302
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3187105044
Short name T238
Test name
Test status
Simulation time 404979718 ps
CPU time 0.74 seconds
Started Jun 10 06:31:00 PM PDT 24
Finished Jun 10 06:31:01 PM PDT 24
Peak memory 191796 kb
Host smart-c03390e3-6655-4b2a-bd34-21d103f81656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187105044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3187105044
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1494109225
Short name T239
Test name
Test status
Simulation time 30626599674 ps
CPU time 5.11 seconds
Started Jun 10 06:31:07 PM PDT 24
Finished Jun 10 06:31:12 PM PDT 24
Peak memory 191928 kb
Host smart-1a0021a9-9ec1-4712-b3e6-3858931305fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494109225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1494109225
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2009844062
Short name T254
Test name
Test status
Simulation time 515156612 ps
CPU time 0.95 seconds
Started Jun 10 06:31:03 PM PDT 24
Finished Jun 10 06:31:05 PM PDT 24
Peak memory 191776 kb
Host smart-b3f552d3-8227-4d20-83cb-a34a6d949ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009844062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2009844062
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2559443004
Short name T185
Test name
Test status
Simulation time 481780428 ps
CPU time 0.96 seconds
Started Jun 10 06:31:07 PM PDT 24
Finished Jun 10 06:31:08 PM PDT 24
Peak memory 196564 kb
Host smart-756ff279-c83f-4003-b0a1-ec491d79916a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559443004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2559443004
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.233964354
Short name T248
Test name
Test status
Simulation time 10452799325 ps
CPU time 4.83 seconds
Started Jun 10 06:31:05 PM PDT 24
Finished Jun 10 06:31:10 PM PDT 24
Peak memory 191928 kb
Host smart-5e224ece-6b60-4033-99d3-cd67010cca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233964354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.233964354
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.875958402
Short name T212
Test name
Test status
Simulation time 388100808 ps
CPU time 0.7 seconds
Started Jun 10 06:31:03 PM PDT 24
Finished Jun 10 06:31:04 PM PDT 24
Peak memory 196600 kb
Host smart-09da60dd-dd18-4e6d-b6cb-45e61e1619f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875958402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.875958402
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1460073371
Short name T271
Test name
Test status
Simulation time 50560291659 ps
CPU time 9.61 seconds
Started Jun 10 06:31:08 PM PDT 24
Finished Jun 10 06:31:17 PM PDT 24
Peak memory 191928 kb
Host smart-0891b65b-5359-4f8e-83d6-4a4acb0cc37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460073371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1460073371
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.974797066
Short name T10
Test name
Test status
Simulation time 450357387 ps
CPU time 0.87 seconds
Started Jun 10 06:31:04 PM PDT 24
Finished Jun 10 06:31:05 PM PDT 24
Peak memory 191744 kb
Host smart-455108fe-b749-46c7-92bf-349bf3ee0f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974797066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.974797066
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.950049574
Short name T220
Test name
Test status
Simulation time 41178883681 ps
CPU time 55.48 seconds
Started Jun 10 06:31:07 PM PDT 24
Finished Jun 10 06:32:03 PM PDT 24
Peak memory 191912 kb
Host smart-d2e448c5-b299-453f-88be-2813980edaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950049574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.950049574
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2459621365
Short name T229
Test name
Test status
Simulation time 506277550 ps
CPU time 1.28 seconds
Started Jun 10 06:31:07 PM PDT 24
Finished Jun 10 06:31:09 PM PDT 24
Peak memory 196488 kb
Host smart-dbece5b4-93c8-47ac-9fe6-3f2eecd9891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459621365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2459621365
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1011448835
Short name T209
Test name
Test status
Simulation time 34787439194 ps
CPU time 4.69 seconds
Started Jun 10 06:31:12 PM PDT 24
Finished Jun 10 06:31:17 PM PDT 24
Peak memory 191908 kb
Host smart-1a9aed3a-acec-45c0-a71f-d8f070d8975f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011448835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1011448835
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1867811023
Short name T249
Test name
Test status
Simulation time 501206350 ps
CPU time 1.22 seconds
Started Jun 10 06:31:06 PM PDT 24
Finished Jun 10 06:31:08 PM PDT 24
Peak memory 196608 kb
Host smart-75eaba5c-8016-4641-8c48-3964a93de4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867811023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1867811023
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3251499175
Short name T214
Test name
Test status
Simulation time 46798262951 ps
CPU time 18.04 seconds
Started Jun 10 06:29:30 PM PDT 24
Finished Jun 10 06:29:48 PM PDT 24
Peak memory 191928 kb
Host smart-6808de5b-1c9a-400f-9271-955164913128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251499175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3251499175
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1951186808
Short name T18
Test name
Test status
Simulation time 7506828337 ps
CPU time 11.11 seconds
Started Jun 10 06:29:33 PM PDT 24
Finished Jun 10 06:29:44 PM PDT 24
Peak memory 215992 kb
Host smart-81d6c025-c997-439f-8b03-270c001d46d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951186808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1951186808
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.706769454
Short name T255
Test name
Test status
Simulation time 575511767 ps
CPU time 0.82 seconds
Started Jun 10 06:29:32 PM PDT 24
Finished Jun 10 06:29:33 PM PDT 24
Peak memory 191824 kb
Host smart-afa4f88a-1c64-4ecc-ba75-7a0e3ecc779b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706769454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.706769454
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3991985390
Short name T12
Test name
Test status
Simulation time 54208421684 ps
CPU time 29.05 seconds
Started Jun 10 06:31:11 PM PDT 24
Finished Jun 10 06:31:40 PM PDT 24
Peak memory 191920 kb
Host smart-584fcf69-0924-45fb-8c0f-dcbc4d68ee6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991985390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3991985390
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3056564323
Short name T223
Test name
Test status
Simulation time 469303321 ps
CPU time 0.72 seconds
Started Jun 10 06:31:13 PM PDT 24
Finished Jun 10 06:31:14 PM PDT 24
Peak memory 191776 kb
Host smart-9658291e-690d-4435-8b8a-c631447c6d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056564323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3056564323
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2215112256
Short name T199
Test name
Test status
Simulation time 9488248340 ps
CPU time 4.12 seconds
Started Jun 10 06:31:15 PM PDT 24
Finished Jun 10 06:31:20 PM PDT 24
Peak memory 191916 kb
Host smart-6aa96588-72a5-4f84-b738-4a9d8117a468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215112256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2215112256
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3718827393
Short name T208
Test name
Test status
Simulation time 396225237 ps
CPU time 0.72 seconds
Started Jun 10 06:31:17 PM PDT 24
Finished Jun 10 06:31:19 PM PDT 24
Peak memory 196540 kb
Host smart-d4011ac0-0040-4b95-acb2-a1ae5f6f949e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718827393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3718827393
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1307677811
Short name T277
Test name
Test status
Simulation time 19205122734 ps
CPU time 2.6 seconds
Started Jun 10 06:31:16 PM PDT 24
Finished Jun 10 06:31:19 PM PDT 24
Peak memory 191908 kb
Host smart-38999f0e-2eb8-4860-923c-958d493cc625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307677811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1307677811
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1080518761
Short name T195
Test name
Test status
Simulation time 380181129 ps
CPU time 1.07 seconds
Started Jun 10 06:31:16 PM PDT 24
Finished Jun 10 06:31:17 PM PDT 24
Peak memory 191752 kb
Host smart-1f063c9d-49eb-42d3-86cb-af3021b3892b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080518761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1080518761
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2729030203
Short name T244
Test name
Test status
Simulation time 11046461372 ps
CPU time 4.51 seconds
Started Jun 10 06:31:21 PM PDT 24
Finished Jun 10 06:31:25 PM PDT 24
Peak memory 191916 kb
Host smart-174bb35b-05c7-4485-889a-2e00326a1c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729030203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2729030203
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4104221451
Short name T232
Test name
Test status
Simulation time 577162334 ps
CPU time 1.36 seconds
Started Jun 10 06:31:16 PM PDT 24
Finished Jun 10 06:31:18 PM PDT 24
Peak memory 196584 kb
Host smart-eb4e9c0d-e807-46ab-9171-a49135d635a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104221451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4104221451
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3036829941
Short name T80
Test name
Test status
Simulation time 607967616 ps
CPU time 0.75 seconds
Started Jun 10 06:31:20 PM PDT 24
Finished Jun 10 06:31:21 PM PDT 24
Peak memory 196548 kb
Host smart-c7282938-8878-4656-bb54-26bca7672962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036829941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3036829941
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2882295407
Short name T247
Test name
Test status
Simulation time 13304495169 ps
CPU time 5.33 seconds
Started Jun 10 06:31:20 PM PDT 24
Finished Jun 10 06:31:26 PM PDT 24
Peak memory 191848 kb
Host smart-264ba1ea-cfa0-422e-84ae-1e92564993d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882295407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2882295407
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.857492188
Short name T252
Test name
Test status
Simulation time 595418424 ps
CPU time 1.36 seconds
Started Jun 10 06:31:24 PM PDT 24
Finished Jun 10 06:31:26 PM PDT 24
Peak memory 191788 kb
Host smart-fc79c416-e08e-4a16-a47a-3a0367bb7254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857492188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.857492188
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.4084287477
Short name T233
Test name
Test status
Simulation time 19523346715 ps
CPU time 5.2 seconds
Started Jun 10 06:31:20 PM PDT 24
Finished Jun 10 06:31:26 PM PDT 24
Peak memory 191884 kb
Host smart-483c6f1c-6ce3-48d1-9833-f9ee549b4e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084287477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4084287477
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2519082361
Short name T51
Test name
Test status
Simulation time 389395677 ps
CPU time 1.16 seconds
Started Jun 10 06:31:20 PM PDT 24
Finished Jun 10 06:31:22 PM PDT 24
Peak memory 196552 kb
Host smart-8ab5911c-21a0-4ade-b971-e594d4f83cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519082361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2519082361
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2521120638
Short name T76
Test name
Test status
Simulation time 21988276858 ps
CPU time 35.54 seconds
Started Jun 10 06:31:25 PM PDT 24
Finished Jun 10 06:32:01 PM PDT 24
Peak memory 191916 kb
Host smart-8c1a14a9-0320-4e19-82a9-5b41c6422260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521120638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2521120638
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2797705625
Short name T150
Test name
Test status
Simulation time 524609480 ps
CPU time 0.89 seconds
Started Jun 10 06:31:24 PM PDT 24
Finished Jun 10 06:31:25 PM PDT 24
Peak memory 191772 kb
Host smart-c75bbbfb-79c1-4d45-b291-f51aafa53810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797705625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2797705625
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1764952888
Short name T193
Test name
Test status
Simulation time 24041548368 ps
CPU time 8.99 seconds
Started Jun 10 06:31:23 PM PDT 24
Finished Jun 10 06:31:33 PM PDT 24
Peak memory 191836 kb
Host smart-e83ffae4-2ca2-4b45-b1fc-de3ba21ad39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764952888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1764952888
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.309901953
Short name T225
Test name
Test status
Simulation time 523197103 ps
CPU time 0.97 seconds
Started Jun 10 06:31:27 PM PDT 24
Finished Jun 10 06:31:28 PM PDT 24
Peak memory 191824 kb
Host smart-3a898d84-6717-450d-a14c-cf286d8f5881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309901953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.309901953
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3184068661
Short name T194
Test name
Test status
Simulation time 31824220036 ps
CPU time 54.38 seconds
Started Jun 10 06:31:29 PM PDT 24
Finished Jun 10 06:32:24 PM PDT 24
Peak memory 191852 kb
Host smart-35e3cf0c-a9cd-46dd-a351-efd86316297f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184068661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3184068661
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1772195396
Short name T230
Test name
Test status
Simulation time 565158366 ps
CPU time 1.55 seconds
Started Jun 10 06:31:29 PM PDT 24
Finished Jun 10 06:31:31 PM PDT 24
Peak memory 191792 kb
Host smart-04cbd877-3622-40c7-ad93-9f94253fc270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772195396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1772195396
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.4122797422
Short name T243
Test name
Test status
Simulation time 3417459389 ps
CPU time 3.33 seconds
Started Jun 10 06:31:30 PM PDT 24
Finished Jun 10 06:31:33 PM PDT 24
Peak memory 191932 kb
Host smart-3665e893-9b67-4696-97b3-444a9e67516f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122797422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.4122797422
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.4262755264
Short name T21
Test name
Test status
Simulation time 496248675 ps
CPU time 0.89 seconds
Started Jun 10 06:31:28 PM PDT 24
Finished Jun 10 06:31:29 PM PDT 24
Peak memory 191768 kb
Host smart-4828de21-a0a8-4beb-86b7-ba7d33ac18b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262755264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4262755264
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1589573677
Short name T48
Test name
Test status
Simulation time 565634062 ps
CPU time 1.31 seconds
Started Jun 10 06:29:35 PM PDT 24
Finished Jun 10 06:29:36 PM PDT 24
Peak memory 196552 kb
Host smart-4820a879-12ed-4cbf-9d92-0565e28cc3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589573677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1589573677
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1074642023
Short name T192
Test name
Test status
Simulation time 11901597153 ps
CPU time 5.43 seconds
Started Jun 10 06:29:34 PM PDT 24
Finished Jun 10 06:29:40 PM PDT 24
Peak memory 191952 kb
Host smart-3220486e-75a6-46bb-afc9-83233fda2779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074642023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1074642023
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2482697434
Short name T81
Test name
Test status
Simulation time 547288458 ps
CPU time 0.97 seconds
Started Jun 10 06:29:34 PM PDT 24
Finished Jun 10 06:29:35 PM PDT 24
Peak memory 191796 kb
Host smart-7462ab0e-7166-4159-afa8-87b97e6cce51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482697434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2482697434
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2408846569
Short name T13
Test name
Test status
Simulation time 31748860541 ps
CPU time 10.86 seconds
Started Jun 10 06:29:34 PM PDT 24
Finished Jun 10 06:29:46 PM PDT 24
Peak memory 191924 kb
Host smart-dc56fa8f-1cc6-4856-9855-9b2659ebbe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408846569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2408846569
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3353433955
Short name T202
Test name
Test status
Simulation time 422555883 ps
CPU time 0.73 seconds
Started Jun 10 06:29:35 PM PDT 24
Finished Jun 10 06:29:36 PM PDT 24
Peak memory 191784 kb
Host smart-b8b8f7ab-a413-4ce2-a1af-f37830734eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353433955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3353433955
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3808961434
Short name T274
Test name
Test status
Simulation time 51811800634 ps
CPU time 72.69 seconds
Started Jun 10 06:29:36 PM PDT 24
Finished Jun 10 06:30:49 PM PDT 24
Peak memory 191932 kb
Host smart-fa7d5e73-9d58-4ac2-b899-e314023dc56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808961434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3808961434
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.21176036
Short name T263
Test name
Test status
Simulation time 459108107 ps
CPU time 1.26 seconds
Started Jun 10 06:29:39 PM PDT 24
Finished Jun 10 06:29:41 PM PDT 24
Peak memory 196580 kb
Host smart-57d85da4-d6e1-4b5f-bd15-0d0cb4b777f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21176036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.21176036
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.4054265886
Short name T276
Test name
Test status
Simulation time 36386045894 ps
CPU time 14.35 seconds
Started Jun 10 06:29:41 PM PDT 24
Finished Jun 10 06:29:55 PM PDT 24
Peak memory 191980 kb
Host smart-fc5c0f17-0ee2-4f49-96f1-f0a663510cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054265886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.4054265886
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1771904343
Short name T215
Test name
Test status
Simulation time 398284815 ps
CPU time 0.89 seconds
Started Jun 10 06:29:38 PM PDT 24
Finished Jun 10 06:29:40 PM PDT 24
Peak memory 191800 kb
Host smart-5a09aaa3-26da-44b4-9be4-ea27553a75ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771904343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1771904343
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.664644664
Short name T211
Test name
Test status
Simulation time 13513398133 ps
CPU time 9.49 seconds
Started Jun 10 06:29:49 PM PDT 24
Finished Jun 10 06:29:59 PM PDT 24
Peak memory 191912 kb
Host smart-2da9140c-4ce7-40e4-b516-924a13939803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664644664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.664644664
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.740427892
Short name T242
Test name
Test status
Simulation time 422510411 ps
CPU time 1.15 seconds
Started Jun 10 06:29:47 PM PDT 24
Finished Jun 10 06:29:49 PM PDT 24
Peak memory 191900 kb
Host smart-8d9c9322-0ea7-4a0a-99e9-db5eacc729b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740427892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.740427892
Directory /workspace/9.aon_timer_smoke/latest
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