Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	32472	1		T1	11		T2	157		T3	796
bark[1]	677	1		T43	26		T96	14		T20	14
bark[2]	497	1		T2	21		T10	26		T37	54
bark[3]	488	1		T145	14		T103	21		T98	21
bark[4]	550	1		T7	21		T29	21		T98	47
bark[5]	447	1		T2	21		T10	21		T37	74
bark[6]	452	1		T10	26		T43	44		T38	163
bark[7]	150	1		T4	52		T156	14		T111	14
bark[8]	617	1		T2	42		T30	5		T36	21
bark[9]	969	1		T10	21		T114	21		T116	60
bark[10]	660	1		T41	68		T139	14		T150	14
bark[11]	112	1		T3	30		T116	21		T84	21
bark[12]	217	1		T3	26		T7	14		T44	21
bark[13]	1364	1		T6	21		T12	14		T29	21
bark[14]	954	1		T5	14		T30	263		T121	14
bark[15]	382	1		T45	14		T38	26		T123	14
bark[16]	930	1		T30	51		T175	14		T103	40
bark[17]	233	1		T7	21		T126	14		T38	21
bark[18]	639	1		T9	105		T10	148		T160	26
bark[19]	437	1		T6	44		T7	21		T43	21
bark[20]	355	1		T44	59		T114	21		T26	42
bark[21]	351	1		T39	21		T105	68		T160	49
bark[22]	915	1		T10	83		T38	49		T23	21
bark[23]	402	1		T3	25		T146	258		T115	21
bark[24]	363	1		T6	19		T10	80		T40	99
bark[25]	112	1		T28	14		T114	14		T105	14
bark[26]	494	1		T2	21		T3	21		T36	21
bark[27]	602	1		T9	30		T10	21		T105	21
bark[28]	240	1		T7	21		T36	65		T26	21
bark[29]	321	1		T7	26		T30	21		T43	19
bark[30]	602	1		T30	21		T38	47		T128	21
bark[31]	901	1		T3	189		T6	21		T44	23
bark_0	4660	1		T1	7		T2	7		T3	94

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	32840	1		T1	10		T2	156		T3	789
bite[1]	467	1		T3	188		T6	21		T10	21
bite[2]	775	1		T6	44		T30	4		T114	13
bite[3]	982	1		T6	21		T38	21		T26	21
bite[4]	114	1		T7	21		T105	21		T100	30
bite[5]	959	1		T9	84		T10	61		T40	214
bite[6]	247	1		T2	21		T10	26		T12	13
bite[7]	416	1		T3	49		T114	66		T116	30
bite[8]	306	1		T30	21		T43	18		T37	53
bite[9]	316	1		T2	21		T29	21		T44	21
bite[10]	169	1		T160	25		T25	21		T117	13
bite[11]	548	1		T2	21		T5	13		T30	312
bite[12]	232	1		T114	21		T39	43		T119	35
bite[13]	200	1		T7	21		T10	79		T23	21
bite[14]	482	1		T7	26		T10	21		T44	21
bite[15]	980	1		T3	21		T43	44		T44	22
bite[16]	380	1		T86	21		T140	26		T125	13
bite[17]	220	1		T36	21		T98	26		T99	6
bite[18]	604	1		T7	21		T126	13		T98	21
bite[19]	312	1		T38	48		T116	21		T128	21
bite[20]	506	1		T10	21		T37	21		T38	25
bite[21]	979	1		T30	21		T45	13		T161	13
bite[22]	1384	1		T2	21		T3	30		T7	21
bite[23]	434	1		T10	26		T86	69		T111	13
bite[24]	222	1		T2	21		T7	13		T103	21
bite[25]	143	1		T10	21		T38	21		T103	21
bite[26]	451	1		T9	30		T10	147		T28	13
bite[27]	577	1		T43	26		T103	40		T26	21
bite[28]	248	1		T38	26		T86	21		T115	18
bite[29]	544	1		T21	254		T81	25		T87	21
bite[30]	697	1		T6	18		T9	21		T181	13
bite[31]	671	1		T145	13		T38	25		T114	21
bite_0	5160	1		T1	8		T2	8		T3	104

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	53565	1		T1	18		T2	269		T3	1181

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1017	1		T2	37		T9	19		T10	73
prescale[1]	1582	1		T3	58		T10	44		T30	19
prescale[2]	894	1		T3	140		T44	19		T40	19
prescale[3]	916	1		T9	19		T10	43		T30	37
prescale[4]	701	1		T3	19		T4	2		T6	29
prescale[5]	1168	1		T9	19		T30	148		T38	83
prescale[6]	800	1		T3	19		T30	44		T36	40
prescale[7]	1050	1		T44	23		T38	2		T40	123
prescale[8]	547	1		T3	2		T9	19		T29	47
prescale[9]	900	1		T3	81		T10	39		T39	40
prescale[10]	806	1		T3	2		T11	9		T30	21
prescale[11]	857	1		T3	19		T10	19		T42	9
prescale[12]	946	1		T3	2		T13	9		T44	19
prescale[13]	1101	1		T2	19		T6	67		T30	254
prescale[14]	929	1		T10	24		T29	19		T30	61
prescale[15]	503	1		T3	2		T10	19		T37	2
prescale[16]	1458	1		T3	65		T10	311		T29	19
prescale[17]	998	1		T3	40		T30	21		T37	21
prescale[18]	638	1		T2	23		T116	24		T40	19
prescale[19]	898	1		T3	27		T10	2		T37	24
prescale[20]	898	1		T3	2		T4	2		T10	94
prescale[21]	907	1		T4	4		T10	159		T30	19
prescale[22]	765	1		T10	9		T43	59		T38	19
prescale[23]	889	1		T2	24		T3	74		T10	61
prescale[24]	851	1		T191	9		T36	81		T116	33
prescale[25]	1122	1		T9	24		T10	19		T30	37
prescale[26]	486	1		T4	19		T10	2		T30	43
prescale[27]	1087	1		T3	113		T44	58		T160	2
prescale[28]	1122	1		T2	61		T3	37		T4	6
prescale[29]	742	1		T3	74		T10	2		T37	2
prescale[30]	585	1		T4	2		T7	54		T37	21
prescale[31]	1443	1		T3	40		T4	2		T9	9
prescale_0	23959	1		T1	18		T2	105		T3	365

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40349	1		T1	18		T2	111		T3	966
auto[1]	13216	1		T2	158		T3	215		T4	126

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	53565	1		T1	18		T2	269		T3	1181

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	32862	1		T1	13		T2	159		T3	761
wkup[1]	190	1		T160	21		T21	21		T81	21
wkup[2]	171	1		T151	42		T111	21		T115	21
wkup[3]	239	1		T9	21		T30	21		T39	21
wkup[4]	229	1		T10	21		T126	15		T146	26
wkup[5]	291	1		T30	21		T38	42		T114	21
wkup[6]	290	1		T6	21		T10	30		T37	21
wkup[7]	209	1		T9	21		T40	21		T25	21
wkup[8]	306	1		T3	15		T9	30		T43	20
wkup[9]	361	1		T30	8		T86	21		T25	21
wkup[10]	246	1		T3	30		T10	30		T38	8
wkup[11]	191	1		T25	21		T122	21		T87	21
wkup[12]	301	1		T6	21		T7	21		T38	26
wkup[13]	301	1		T3	21		T10	42		T30	21
wkup[14]	183	1		T38	21		T175	15		T103	21
wkup[15]	227	1		T10	30		T81	21		T150	15
wkup[16]	355	1		T2	21		T6	20		T30	21
wkup[17]	341	1		T38	21		T103	21		T146	20
wkup[18]	276	1		T3	21		T10	21		T37	21
wkup[19]	233	1		T4	26		T28	15		T36	21
wkup[20]	225	1		T3	42		T10	21		T114	36
wkup[21]	258	1		T10	26		T44	21		T40	21
wkup[22]	328	1		T3	21		T105	15		T20	15
wkup[23]	360	1		T3	21		T7	21		T30	21
wkup[24]	251	1		T7	26		T41	21		T86	21
wkup[25]	329	1		T3	30		T10	30		T37	21
wkup[26]	383	1		T3	26		T7	15		T30	26
wkup[27]	265	1		T10	30		T40	21		T86	21
wkup[28]	245	1		T36	21		T86	21		T115	26
wkup[29]	314	1		T3	21		T30	21		T40	51
wkup[30]	284	1		T2	21		T21	21		T133	30
wkup[31]	359	1		T3	35		T10	30		T30	6
wkup[32]	439	1		T98	21		T160	40		T119	35
wkup[33]	204	1		T10	21		T138	15		T158	8
wkup[34]	235	1		T7	21		T9	21		T43	44
wkup[35]	294	1		T30	21		T43	26		T86	21
wkup[36]	349	1		T39	21		T119	30		T21	21
wkup[37]	314	1		T45	15		T38	8		T39	21
wkup[38]	369	1		T10	21		T30	15		T36	42
wkup[39]	304	1		T7	26		T30	21		T145	15
wkup[40]	209	1		T2	21		T103	21		T181	15
wkup[41]	173	1		T116	21		T86	21		T160	26
wkup[42]	221	1		T29	21		T39	21		T40	44
wkup[43]	314	1		T10	21		T29	21		T161	15
wkup[44]	284	1		T10	35		T116	30		T86	21
wkup[45]	238	1		T4	21		T10	26		T30	30
wkup[46]	181	1		T178	15		T110	21		T140	26
wkup[47]	258	1		T2	21		T30	21		T98	21
wkup[48]	179	1		T114	26		T41	21		T86	33
wkup[49]	283	1		T6	21		T38	31		T156	15
wkup[50]	261	1		T2	21		T44	24		T39	21
wkup[51]	361	1		T10	21		T30	21		T139	15
wkup[52]	312	1		T10	21		T36	21		T37	21
wkup[53]	232	1		T3	21		T38	26		T114	21
wkup[54]	319	1		T10	21		T43	21		T38	21
wkup[55]	333	1		T7	21		T10	26		T36	21
wkup[56]	241	1		T103	30		T146	26		T82	15
wkup[57]	162	1		T30	21		T38	21		T21	21
wkup[58]	255	1		T3	21		T38	21		T39	21
wkup[59]	208	1		T5	15		T146	21		T154	21
wkup[60]	143	1		T39	21		T41	21		T140	21
wkup[61]	296	1		T10	21		T37	30		T41	21
wkup[62]	197	1		T38	30		T40	21		T21	21
wkup[63]	353	1		T3	21		T12	15		T30	30
wkup_0	3641	1		T1	5		T2	5		T3	74