Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.02 99.33 93.67 100.00 98.40 99.51 49.19


Total test records in report: 420
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T192 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2649547650 Jun 11 01:47:54 PM PDT 24 Jun 11 01:47:56 PM PDT 24 798796330 ps
T282 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3980598034 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:16 PM PDT 24 486071854 ps
T34 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1892396447 Jun 11 01:48:07 PM PDT 24 Jun 11 01:48:14 PM PDT 24 4333954955 ps
T57 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1775346555 Jun 11 01:48:02 PM PDT 24 Jun 11 01:48:05 PM PDT 24 372136178 ps
T35 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1404759704 Jun 11 01:47:57 PM PDT 24 Jun 11 01:48:03 PM PDT 24 7762279020 ps
T186 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1789369049 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:07 PM PDT 24 4606895855 ps
T283 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1214711603 Jun 11 01:47:51 PM PDT 24 Jun 11 01:47:53 PM PDT 24 495967425 ps
T284 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1345170410 Jun 11 01:48:01 PM PDT 24 Jun 11 01:48:05 PM PDT 24 558632901 ps
T285 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3127691202 Jun 11 01:47:54 PM PDT 24 Jun 11 01:47:57 PM PDT 24 583987768 ps
T286 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1066244033 Jun 11 01:48:10 PM PDT 24 Jun 11 01:48:15 PM PDT 24 484891236 ps
T72 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2310748940 Jun 11 01:48:04 PM PDT 24 Jun 11 01:48:07 PM PDT 24 2405601567 ps
T287 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.361413211 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:15 PM PDT 24 507821446 ps
T73 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2551576403 Jun 11 01:48:06 PM PDT 24 Jun 11 01:48:09 PM PDT 24 475227486 ps
T288 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.848318160 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:16 PM PDT 24 520380211 ps
T188 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.663486118 Jun 11 01:47:56 PM PDT 24 Jun 11 01:48:00 PM PDT 24 8603812116 ps
T289 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2929213170 Jun 11 01:48:08 PM PDT 24 Jun 11 01:48:11 PM PDT 24 348775094 ps
T290 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.909809488 Jun 11 01:47:48 PM PDT 24 Jun 11 01:47:51 PM PDT 24 371175004 ps
T291 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2591915809 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:01 PM PDT 24 584724148 ps
T58 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1123139281 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:01 PM PDT 24 444814792 ps
T187 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.286790219 Jun 11 01:47:57 PM PDT 24 Jun 11 01:48:12 PM PDT 24 8408986462 ps
T292 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1998800123 Jun 11 01:47:59 PM PDT 24 Jun 11 01:48:15 PM PDT 24 8019942777 ps
T293 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4188208773 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:08 PM PDT 24 442594322 ps
T294 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3623955853 Jun 11 01:47:55 PM PDT 24 Jun 11 01:47:58 PM PDT 24 383963524 ps
T295 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3312209826 Jun 11 01:47:54 PM PDT 24 Jun 11 01:47:56 PM PDT 24 610679655 ps
T74 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1564344086 Jun 11 01:48:04 PM PDT 24 Jun 11 01:48:08 PM PDT 24 1231844265 ps
T296 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1899211861 Jun 11 01:48:04 PM PDT 24 Jun 11 01:48:07 PM PDT 24 326678164 ps
T75 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1672520476 Jun 11 01:48:09 PM PDT 24 Jun 11 01:48:13 PM PDT 24 2358430976 ps
T297 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3592861639 Jun 11 01:47:55 PM PDT 24 Jun 11 01:47:57 PM PDT 24 820661287 ps
T298 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3387270308 Jun 11 01:47:55 PM PDT 24 Jun 11 01:47:57 PM PDT 24 470448808 ps
T299 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.646929361 Jun 11 01:48:02 PM PDT 24 Jun 11 01:48:04 PM PDT 24 380682633 ps
T300 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2572712946 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:01 PM PDT 24 323189179 ps
T301 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1966960195 Jun 11 01:48:09 PM PDT 24 Jun 11 01:48:13 PM PDT 24 540765803 ps
T76 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.521477381 Jun 11 01:48:07 PM PDT 24 Jun 11 01:48:09 PM PDT 24 364648786 ps
T302 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3066244758 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:00 PM PDT 24 344363629 ps
T303 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4192813342 Jun 11 01:48:10 PM PDT 24 Jun 11 01:48:14 PM PDT 24 336491797 ps
T59 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.709375542 Jun 11 01:48:01 PM PDT 24 Jun 11 01:48:04 PM PDT 24 477958112 ps
T304 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3729058455 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:14 PM PDT 24 371629864 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4178851321 Jun 11 01:47:53 PM PDT 24 Jun 11 01:47:55 PM PDT 24 476849232 ps
T305 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3713328307 Jun 11 01:47:46 PM PDT 24 Jun 11 01:47:49 PM PDT 24 673043522 ps
T306 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.157976304 Jun 11 01:48:05 PM PDT 24 Jun 11 01:48:08 PM PDT 24 318934814 ps
T307 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2500745915 Jun 11 01:48:02 PM PDT 24 Jun 11 01:48:05 PM PDT 24 455554194 ps
T308 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3850336113 Jun 11 01:47:47 PM PDT 24 Jun 11 01:47:49 PM PDT 24 383476948 ps
T77 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4102579074 Jun 11 01:47:59 PM PDT 24 Jun 11 01:48:05 PM PDT 24 1682895486 ps
T309 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1946037406 Jun 11 01:47:59 PM PDT 24 Jun 11 01:48:03 PM PDT 24 754488909 ps
T310 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2340859839 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:01 PM PDT 24 508514719 ps
T311 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2102938528 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:07 PM PDT 24 359858783 ps
T312 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.390889726 Jun 11 01:48:09 PM PDT 24 Jun 11 01:48:12 PM PDT 24 454017814 ps
T313 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1062265854 Jun 11 01:48:07 PM PDT 24 Jun 11 01:48:10 PM PDT 24 417146574 ps
T61 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2509997297 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:02 PM PDT 24 291938097 ps
T314 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3429854269 Jun 11 01:48:06 PM PDT 24 Jun 11 01:48:08 PM PDT 24 302480280 ps
T315 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3586954887 Jun 11 01:47:55 PM PDT 24 Jun 11 01:47:57 PM PDT 24 579646202 ps
T189 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.697952 Jun 11 01:47:59 PM PDT 24 Jun 11 01:48:14 PM PDT 24 7584309908 ps
T62 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2340461473 Jun 11 01:47:55 PM PDT 24 Jun 11 01:48:09 PM PDT 24 10602853818 ps
T316 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.925911803 Jun 11 01:48:01 PM PDT 24 Jun 11 01:48:04 PM PDT 24 449656636 ps
T78 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1952731808 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:07 PM PDT 24 1986828783 ps
T317 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.770536790 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:06 PM PDT 24 624480521 ps
T318 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.4125442480 Jun 11 01:48:00 PM PDT 24 Jun 11 01:48:02 PM PDT 24 339210435 ps
T319 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4135003363 Jun 11 01:48:09 PM PDT 24 Jun 11 01:48:12 PM PDT 24 489616661 ps
T320 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.570299726 Jun 11 01:48:02 PM PDT 24 Jun 11 01:48:06 PM PDT 24 598115045 ps
T321 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4245881947 Jun 11 01:47:52 PM PDT 24 Jun 11 01:47:54 PM PDT 24 355624209 ps
T63 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1966407396 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:01 PM PDT 24 441602279 ps
T322 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2974288294 Jun 11 01:48:09 PM PDT 24 Jun 11 01:48:13 PM PDT 24 593836579 ps
T323 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.653433266 Jun 11 01:47:57 PM PDT 24 Jun 11 01:48:00 PM PDT 24 412019228 ps
T324 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1642862026 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:06 PM PDT 24 382017011 ps
T79 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1713031984 Jun 11 01:47:46 PM PDT 24 Jun 11 01:47:49 PM PDT 24 2396128543 ps
T190 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1017963556 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:21 PM PDT 24 8184050052 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3477789347 Jun 11 01:48:00 PM PDT 24 Jun 11 01:48:03 PM PDT 24 691542577 ps
T325 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2017153481 Jun 11 01:47:57 PM PDT 24 Jun 11 01:48:00 PM PDT 24 519354663 ps
T326 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1397942446 Jun 11 01:48:06 PM PDT 24 Jun 11 01:48:12 PM PDT 24 8535227402 ps
T327 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.865202793 Jun 11 01:47:56 PM PDT 24 Jun 11 01:47:59 PM PDT 24 431197693 ps
T71 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3290622583 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:01 PM PDT 24 729441502 ps
T328 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3226465067 Jun 11 01:47:57 PM PDT 24 Jun 11 01:47:59 PM PDT 24 358681344 ps
T329 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2654926177 Jun 11 01:47:51 PM PDT 24 Jun 11 01:47:54 PM PDT 24 478019018 ps
T330 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2377484039 Jun 11 01:47:56 PM PDT 24 Jun 11 01:48:00 PM PDT 24 890823608 ps
T331 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.410842966 Jun 11 01:48:02 PM PDT 24 Jun 11 01:48:04 PM PDT 24 303592886 ps
T332 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1350428225 Jun 11 01:48:12 PM PDT 24 Jun 11 01:48:16 PM PDT 24 447052493 ps
T333 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2575500999 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:05 PM PDT 24 501647089 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4062669313 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:01 PM PDT 24 582584070 ps
T334 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1921516127 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:07 PM PDT 24 533325357 ps
T335 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.925785454 Jun 11 01:48:01 PM PDT 24 Jun 11 01:48:04 PM PDT 24 361798415 ps
T336 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.5323965 Jun 11 01:47:46 PM PDT 24 Jun 11 01:47:48 PM PDT 24 441517036 ps
T67 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.63323311 Jun 11 01:47:52 PM PDT 24 Jun 11 01:48:05 PM PDT 24 7370168867 ps
T337 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.816110461 Jun 11 01:47:57 PM PDT 24 Jun 11 01:48:00 PM PDT 24 580991121 ps
T338 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1244082878 Jun 11 01:48:01 PM PDT 24 Jun 11 01:48:10 PM PDT 24 4233388224 ps
T339 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1837617179 Jun 11 01:47:53 PM PDT 24 Jun 11 01:47:55 PM PDT 24 560945711 ps
T340 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3109311637 Jun 11 01:48:13 PM PDT 24 Jun 11 01:48:18 PM PDT 24 272486913 ps
T341 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2990894707 Jun 11 01:47:48 PM PDT 24 Jun 11 01:47:50 PM PDT 24 330928881 ps
T342 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2547355736 Jun 11 01:47:45 PM PDT 24 Jun 11 01:47:48 PM PDT 24 471580612 ps
T343 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3190048357 Jun 11 01:48:06 PM PDT 24 Jun 11 01:48:08 PM PDT 24 570310935 ps
T344 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3100842000 Jun 11 01:48:09 PM PDT 24 Jun 11 01:48:12 PM PDT 24 394759407 ps
T345 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3573132482 Jun 11 01:47:55 PM PDT 24 Jun 11 01:47:58 PM PDT 24 509125857 ps
T346 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1599387657 Jun 11 01:48:13 PM PDT 24 Jun 11 01:48:18 PM PDT 24 401974319 ps
T347 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1443322767 Jun 11 01:48:08 PM PDT 24 Jun 11 01:48:11 PM PDT 24 653381806 ps
T348 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.259006439 Jun 11 01:48:05 PM PDT 24 Jun 11 01:48:09 PM PDT 24 1449813589 ps
T68 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3651387275 Jun 11 01:48:01 PM PDT 24 Jun 11 01:48:04 PM PDT 24 502887339 ps
T349 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2750796960 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:00 PM PDT 24 1768393215 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3619756222 Jun 11 01:47:47 PM PDT 24 Jun 11 01:47:50 PM PDT 24 1140456003 ps
T350 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2530571733 Jun 11 01:47:56 PM PDT 24 Jun 11 01:47:59 PM PDT 24 321055767 ps
T351 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2006056981 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:16 PM PDT 24 527619605 ps
T352 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2842377205 Jun 11 01:47:57 PM PDT 24 Jun 11 01:48:06 PM PDT 24 8450471085 ps
T353 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3773076223 Jun 11 01:48:01 PM PDT 24 Jun 11 01:48:06 PM PDT 24 8251031747 ps
T354 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1640413482 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:11 PM PDT 24 3834972802 ps
T355 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2398772528 Jun 11 01:48:01 PM PDT 24 Jun 11 01:48:05 PM PDT 24 1088210312 ps
T356 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.695264396 Jun 11 01:48:10 PM PDT 24 Jun 11 01:48:15 PM PDT 24 387560159 ps
T357 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.435868903 Jun 11 01:47:50 PM PDT 24 Jun 11 01:47:53 PM PDT 24 1425838815 ps
T69 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2732940257 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:02 PM PDT 24 1176002529 ps
T358 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.96049512 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:15 PM PDT 24 374033395 ps
T359 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1229830023 Jun 11 01:48:12 PM PDT 24 Jun 11 01:48:16 PM PDT 24 382812417 ps
T360 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.545371070 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:01 PM PDT 24 385502520 ps
T361 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3099857436 Jun 11 01:47:47 PM PDT 24 Jun 11 01:47:49 PM PDT 24 381535291 ps
T362 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1720898357 Jun 11 01:47:53 PM PDT 24 Jun 11 01:47:55 PM PDT 24 353553345 ps
T363 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1049062765 Jun 11 01:47:59 PM PDT 24 Jun 11 01:48:02 PM PDT 24 563317919 ps
T364 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2657292655 Jun 11 01:48:13 PM PDT 24 Jun 11 01:48:18 PM PDT 24 487520959 ps
T365 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2983074545 Jun 11 01:47:48 PM PDT 24 Jun 11 01:48:13 PM PDT 24 14166400854 ps
T70 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1081185850 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:15 PM PDT 24 498013869 ps
T366 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.503154010 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:06 PM PDT 24 423753734 ps
T367 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.474699449 Jun 11 01:47:56 PM PDT 24 Jun 11 01:47:59 PM PDT 24 715213437 ps
T368 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.899253089 Jun 11 01:48:10 PM PDT 24 Jun 11 01:48:14 PM PDT 24 422371550 ps
T369 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.110350971 Jun 11 01:48:10 PM PDT 24 Jun 11 01:48:14 PM PDT 24 393251296 ps
T370 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2169246439 Jun 11 01:47:47 PM PDT 24 Jun 11 01:48:02 PM PDT 24 8395918305 ps
T371 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3736611777 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:16 PM PDT 24 475290698 ps
T372 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3489599173 Jun 11 01:48:09 PM PDT 24 Jun 11 01:48:12 PM PDT 24 290111724 ps
T373 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.218099056 Jun 11 01:48:06 PM PDT 24 Jun 11 01:48:09 PM PDT 24 2126216792 ps
T374 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1080228180 Jun 11 01:47:55 PM PDT 24 Jun 11 01:47:58 PM PDT 24 1318035331 ps
T375 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2093908815 Jun 11 01:47:51 PM PDT 24 Jun 11 01:47:53 PM PDT 24 496154405 ps
T376 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.24081129 Jun 11 01:48:00 PM PDT 24 Jun 11 01:48:03 PM PDT 24 1399174450 ps
T377 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3235555139 Jun 11 01:48:02 PM PDT 24 Jun 11 01:48:04 PM PDT 24 458583127 ps
T378 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.847970723 Jun 11 01:47:51 PM PDT 24 Jun 11 01:47:52 PM PDT 24 278938323 ps
T379 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.21071607 Jun 11 01:48:13 PM PDT 24 Jun 11 01:48:18 PM PDT 24 331072028 ps
T380 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.611699642 Jun 11 01:47:59 PM PDT 24 Jun 11 01:48:03 PM PDT 24 491826478 ps
T381 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.398752040 Jun 11 01:47:55 PM PDT 24 Jun 11 01:47:57 PM PDT 24 291382558 ps
T382 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2556416628 Jun 11 01:47:59 PM PDT 24 Jun 11 01:48:04 PM PDT 24 8451961906 ps
T383 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3677134777 Jun 11 01:48:12 PM PDT 24 Jun 11 01:48:17 PM PDT 24 505724670 ps
T384 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2002045428 Jun 11 01:47:52 PM PDT 24 Jun 11 01:47:53 PM PDT 24 626790491 ps
T385 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3749453325 Jun 11 01:48:02 PM PDT 24 Jun 11 01:48:05 PM PDT 24 347712496 ps
T386 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3138375209 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:01 PM PDT 24 319771904 ps
T387 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.940386471 Jun 11 01:47:57 PM PDT 24 Jun 11 01:48:00 PM PDT 24 1293615667 ps
T388 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1212210161 Jun 11 01:47:57 PM PDT 24 Jun 11 01:48:00 PM PDT 24 334538969 ps
T389 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2011952471 Jun 11 01:47:52 PM PDT 24 Jun 11 01:47:54 PM PDT 24 409192666 ps
T390 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.564661544 Jun 11 01:47:57 PM PDT 24 Jun 11 01:48:00 PM PDT 24 363591520 ps
T391 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1217799032 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:03 PM PDT 24 556204124 ps
T392 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3368113157 Jun 11 01:48:06 PM PDT 24 Jun 11 01:48:10 PM PDT 24 526757580 ps
T393 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2824956447 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:01 PM PDT 24 457167070 ps
T394 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1350743050 Jun 11 01:48:12 PM PDT 24 Jun 11 01:48:16 PM PDT 24 381267574 ps
T395 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2875172360 Jun 11 01:48:12 PM PDT 24 Jun 11 01:48:17 PM PDT 24 1408674242 ps
T396 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1115026152 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:15 PM PDT 24 543582886 ps
T397 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1974039777 Jun 11 01:47:51 PM PDT 24 Jun 11 01:47:53 PM PDT 24 293792711 ps
T398 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3459171870 Jun 11 01:47:51 PM PDT 24 Jun 11 01:48:03 PM PDT 24 8958667630 ps
T399 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1739492150 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:06 PM PDT 24 440663739 ps
T400 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1994984512 Jun 11 01:48:07 PM PDT 24 Jun 11 01:48:10 PM PDT 24 398037389 ps
T401 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3727242223 Jun 11 01:47:57 PM PDT 24 Jun 11 01:48:00 PM PDT 24 360119125 ps
T402 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.651394674 Jun 11 01:48:04 PM PDT 24 Jun 11 01:48:08 PM PDT 24 502712459 ps
T403 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4093390088 Jun 11 01:48:04 PM PDT 24 Jun 11 01:48:07 PM PDT 24 364711730 ps
T404 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3317678087 Jun 11 01:47:56 PM PDT 24 Jun 11 01:47:59 PM PDT 24 424758525 ps
T405 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4025389373 Jun 11 01:47:53 PM PDT 24 Jun 11 01:47:55 PM PDT 24 579243302 ps
T406 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1392624585 Jun 11 01:47:55 PM PDT 24 Jun 11 01:47:59 PM PDT 24 1840457196 ps
T407 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.267879122 Jun 11 01:47:55 PM PDT 24 Jun 11 01:47:57 PM PDT 24 361902677 ps
T408 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2478412346 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:13 PM PDT 24 8229698743 ps
T409 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1467859070 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:07 PM PDT 24 7257566031 ps
T410 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1489578342 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:02 PM PDT 24 2258390980 ps
T411 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.694391908 Jun 11 01:48:05 PM PDT 24 Jun 11 01:48:09 PM PDT 24 1159193974 ps
T412 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3662956942 Jun 11 01:48:05 PM PDT 24 Jun 11 01:48:09 PM PDT 24 609834688 ps
T413 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2305405446 Jun 11 01:47:57 PM PDT 24 Jun 11 01:48:03 PM PDT 24 4118772839 ps
T414 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3689046674 Jun 11 01:47:55 PM PDT 24 Jun 11 01:48:10 PM PDT 24 8281330135 ps
T415 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2947370230 Jun 11 01:47:47 PM PDT 24 Jun 11 01:47:49 PM PDT 24 489281583 ps
T416 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2228814334 Jun 11 01:47:57 PM PDT 24 Jun 11 01:48:00 PM PDT 24 637501432 ps
T417 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1233440154 Jun 11 01:47:59 PM PDT 24 Jun 11 01:48:02 PM PDT 24 604484275 ps
T418 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1260540116 Jun 11 01:47:58 PM PDT 24 Jun 11 01:48:03 PM PDT 24 2350654278 ps
T419 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1639814518 Jun 11 01:48:07 PM PDT 24 Jun 11 01:48:12 PM PDT 24 2949568842 ps
T420 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3493764170 Jun 11 01:48:03 PM PDT 24 Jun 11 01:48:06 PM PDT 24 359053355 ps

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2823121958
Short name T10
Test name
Test status
Simulation time 120704963710 ps
CPU time 493.11 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:51:14 PM PDT 24
Peak memory 203584 kb
Host smart-c6aec358-7fb6-49f8-a9ee-b3c97281e802
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823121958 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2823121958
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.525919134
Short name T2
Test name
Test status
Simulation time 120889131821 ps
CPU time 46.09 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:43:41 PM PDT 24
Peak memory 191920 kb
Host smart-65bd075a-3bf8-4a3e-a640-7597252c28b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525919134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.525919134
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1892396447
Short name T34
Test name
Test status
Simulation time 4333954955 ps
CPU time 5.53 seconds
Started Jun 11 01:48:07 PM PDT 24
Finished Jun 11 01:48:14 PM PDT 24
Peak memory 197484 kb
Host smart-b7e3a6ea-448a-4e5b-9a20-0a1c4afa2492
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892396447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1892396447
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.336982524
Short name T38
Test name
Test status
Simulation time 278352217898 ps
CPU time 587.94 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:52:44 PM PDT 24
Peak memory 204780 kb
Host smart-babe93d8-3e64-4660-9831-de843b4762a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336982524 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.336982524
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.356614116
Short name T46
Test name
Test status
Simulation time 71222414376 ps
CPU time 467.16 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:50:42 PM PDT 24
Peak memory 214180 kb
Host smart-cd2a5a7a-8116-424a-a17f-5e95255c7cc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356614116 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.356614116
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.4019349730
Short name T86
Test name
Test status
Simulation time 129757855756 ps
CPU time 469.3 seconds
Started Jun 11 01:42:37 PM PDT 24
Finished Jun 11 01:50:27 PM PDT 24
Peak memory 203808 kb
Host smart-2e8b9b11-6f29-4723-9cdd-0ffbaf420d33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019349730 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.4019349730
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2295607316
Short name T85
Test name
Test status
Simulation time 502977652276 ps
CPU time 714.81 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:54:55 PM PDT 24
Peak memory 206936 kb
Host smart-d66675c4-91ee-4d1f-954d-687f964a5e7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295607316 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2295607316
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1469713515
Short name T7
Test name
Test status
Simulation time 240183504205 ps
CPU time 386.73 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:49:25 PM PDT 24
Peak memory 192472 kb
Host smart-cdbf612a-134f-442a-9e0f-4db9b9398bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469713515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1469713515
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2320635970
Short name T56
Test name
Test status
Simulation time 651958073506 ps
CPU time 616.29 seconds
Started Jun 11 01:42:47 PM PDT 24
Finished Jun 11 01:53:05 PM PDT 24
Peak memory 205112 kb
Host smart-88f1c0b8-b5a8-49bc-8d17-c9657e46adaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320635970 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2320635970
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.426405609
Short name T3
Test name
Test status
Simulation time 77484125304 ps
CPU time 613.61 seconds
Started Jun 11 01:42:59 PM PDT 24
Finished Jun 11 01:53:17 PM PDT 24
Peak memory 206712 kb
Host smart-ea39211f-7e71-4902-acd7-58f2c32d532e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426405609 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.426405609
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.835916010
Short name T18
Test name
Test status
Simulation time 4247185160 ps
CPU time 6.53 seconds
Started Jun 11 01:42:42 PM PDT 24
Finished Jun 11 01:42:49 PM PDT 24
Peak memory 215420 kb
Host smart-9dc32b9c-0411-4744-8d8c-1064a64f66ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835916010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.835916010
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.152321044
Short name T104
Test name
Test status
Simulation time 176097647220 ps
CPU time 65.57 seconds
Started Jun 11 01:43:20 PM PDT 24
Finished Jun 11 01:44:26 PM PDT 24
Peak memory 193256 kb
Host smart-eccfe608-4eaa-4ad9-9a6f-0cf0463ee1b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152321044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.152321044
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.842483059
Short name T98
Test name
Test status
Simulation time 82219466050 ps
CPU time 55.51 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:43:56 PM PDT 24
Peak memory 192504 kb
Host smart-fcb76c34-8c63-4b25-8e2b-63ab5338f6d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842483059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.842483059
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2442142245
Short name T140
Test name
Test status
Simulation time 87861224015 ps
CPU time 535.15 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:52:02 PM PDT 24
Peak memory 212528 kb
Host smart-e0d89a64-6ecc-4360-a357-856f534d2477
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442142245 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2442142245
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2528507684
Short name T103
Test name
Test status
Simulation time 10955646634 ps
CPU time 17.21 seconds
Started Jun 11 01:43:04 PM PDT 24
Finished Jun 11 01:43:23 PM PDT 24
Peak memory 197864 kb
Host smart-2b72e922-996d-4703-961d-075690b19b79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528507684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2528507684
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.923208358
Short name T88
Test name
Test status
Simulation time 298726512595 ps
CPU time 596.15 seconds
Started Jun 11 01:42:46 PM PDT 24
Finished Jun 11 01:52:44 PM PDT 24
Peak memory 204896 kb
Host smart-e2df85c6-47cc-4ea3-9ee3-d8250c202c23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923208358 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.923208358
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2636777067
Short name T95
Test name
Test status
Simulation time 108676060913 ps
CPU time 185.21 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:45:57 PM PDT 24
Peak memory 184656 kb
Host smart-228acdae-e27b-4a5a-b141-b4ff892f83f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636777067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2636777067
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3294357440
Short name T90
Test name
Test status
Simulation time 65851774939 ps
CPU time 410.94 seconds
Started Jun 11 01:43:01 PM PDT 24
Finished Jun 11 01:49:55 PM PDT 24
Peak memory 208784 kb
Host smart-7e8c27e5-5d59-4723-9088-bd7c4ac9815c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294357440 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3294357440
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3281471515
Short name T115
Test name
Test status
Simulation time 510943977946 ps
CPU time 771.31 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:55:45 PM PDT 24
Peak memory 198212 kb
Host smart-540b0b20-692b-4f0a-ba53-691bc672fd64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281471515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3281471515
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3615129764
Short name T137
Test name
Test status
Simulation time 95238050155 ps
CPU time 360 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:48:52 PM PDT 24
Peak memory 210564 kb
Host smart-e6743b9c-c09e-4cc5-bd1b-aa178a840691
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615129764 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3615129764
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3349843188
Short name T53
Test name
Test status
Simulation time 5828488731 ps
CPU time 4.57 seconds
Started Jun 11 01:43:00 PM PDT 24
Finished Jun 11 01:43:08 PM PDT 24
Peak memory 192624 kb
Host smart-19cdd0a2-d2f6-4524-804a-8807b8be68aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349843188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3349843188
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1311456192
Short name T105
Test name
Test status
Simulation time 208449342625 ps
CPU time 174.17 seconds
Started Jun 11 01:42:42 PM PDT 24
Finished Jun 11 01:45:38 PM PDT 24
Peak memory 198300 kb
Host smart-d3db2299-1f84-4c17-94ed-ae47010525ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311456192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1311456192
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1274181083
Short name T120
Test name
Test status
Simulation time 154936932124 ps
CPU time 319.91 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:48:13 PM PDT 24
Peak memory 206860 kb
Host smart-47d6c94b-bea3-4183-b4ec-ff1c5103ec4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274181083 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1274181083
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2429126876
Short name T100
Test name
Test status
Simulation time 178493048525 ps
CPU time 75.04 seconds
Started Jun 11 01:43:30 PM PDT 24
Finished Jun 11 01:44:46 PM PDT 24
Peak memory 198280 kb
Host smart-9dfbfb09-370f-4a67-a988-7893946b62ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429126876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2429126876
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1798032909
Short name T99
Test name
Test status
Simulation time 196168121226 ps
CPU time 416.83 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:49:54 PM PDT 24
Peak memory 210932 kb
Host smart-195ad37b-0bdc-4a89-8e61-2b715e332918
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798032909 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1798032909
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.278810974
Short name T23
Test name
Test status
Simulation time 329640468218 ps
CPU time 139.05 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:45:15 PM PDT 24
Peak memory 191908 kb
Host smart-00ace56b-c8d3-461b-b399-2a40a99f64bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278810974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.278810974
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1722369491
Short name T87
Test name
Test status
Simulation time 100569764921 ps
CPU time 727.76 seconds
Started Jun 11 01:43:05 PM PDT 24
Finished Jun 11 01:55:14 PM PDT 24
Peak memory 206668 kb
Host smart-c3c73940-1b24-46a9-b216-26a17cf82852
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722369491 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1722369491
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.664096041
Short name T107
Test name
Test status
Simulation time 136392400249 ps
CPU time 298.78 seconds
Started Jun 11 01:43:19 PM PDT 24
Finished Jun 11 01:48:19 PM PDT 24
Peak memory 210048 kb
Host smart-9e6c7090-09b5-48cb-8e52-e500a3c76de1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664096041 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.664096041
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2342173061
Short name T6
Test name
Test status
Simulation time 161414033973 ps
CPU time 54.38 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:43:48 PM PDT 24
Peak memory 191852 kb
Host smart-2a2d3c26-0f5c-4e7c-bd1c-c0281dac04de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342173061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2342173061
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1437132365
Short name T102
Test name
Test status
Simulation time 92891087565 ps
CPU time 480.41 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:50:59 PM PDT 24
Peak memory 212624 kb
Host smart-a1b954a5-0b8a-4f98-b07c-e7e05379a889
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437132365 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1437132365
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2814265908
Short name T114
Test name
Test status
Simulation time 667973791460 ps
CPU time 575.68 seconds
Started Jun 11 01:42:46 PM PDT 24
Finished Jun 11 01:52:24 PM PDT 24
Peak memory 192940 kb
Host smart-fdc6513d-1e6c-49d0-8ec3-325ee9c21a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814265908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2814265908
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.236174078
Short name T25
Test name
Test status
Simulation time 83437538372 ps
CPU time 334.27 seconds
Started Jun 11 01:43:02 PM PDT 24
Finished Jun 11 01:48:39 PM PDT 24
Peak memory 201476 kb
Host smart-f1ee4fa7-d397-47a5-9d3d-da13e98c8043
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236174078 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.236174078
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3561436522
Short name T9
Test name
Test status
Simulation time 60464022751 ps
CPU time 58.98 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:43:58 PM PDT 24
Peak memory 184144 kb
Host smart-bf5306d1-14d5-4ea1-aa83-1ec447d9f6e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561436522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3561436522
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.744497591
Short name T113
Test name
Test status
Simulation time 60903475410 ps
CPU time 88.71 seconds
Started Jun 11 01:42:45 PM PDT 24
Finished Jun 11 01:44:15 PM PDT 24
Peak memory 184120 kb
Host smart-5f1eed39-f913-4d52-946c-961d26258300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744497591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.744497591
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.4040954846
Short name T119
Test name
Test status
Simulation time 192077135035 ps
CPU time 267.25 seconds
Started Jun 11 01:42:58 PM PDT 24
Finished Jun 11 01:47:29 PM PDT 24
Peak memory 198252 kb
Host smart-4477bac6-dfcb-4a78-89a7-135f02c2bc13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040954846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.4040954846
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1447948507
Short name T122
Test name
Test status
Simulation time 313816008468 ps
CPU time 142.54 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:45:22 PM PDT 24
Peak memory 192840 kb
Host smart-4f2acb85-9fe2-4978-88d1-1b1bbd38cee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447948507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1447948507
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3116903619
Short name T44
Test name
Test status
Simulation time 129005050871 ps
CPU time 184.36 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:46:03 PM PDT 24
Peak memory 198496 kb
Host smart-3f50c769-16e3-4651-8951-bafea5c58e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116903619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3116903619
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.898053066
Short name T30
Test name
Test status
Simulation time 230721676041 ps
CPU time 966.57 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:59:06 PM PDT 24
Peak memory 215004 kb
Host smart-163bcdc9-3df9-441e-963e-a7fbe8edf3f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898053066 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.898053066
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1942239459
Short name T109
Test name
Test status
Simulation time 467204781551 ps
CPU time 72.87 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:44:13 PM PDT 24
Peak memory 198260 kb
Host smart-019447d0-3abf-455f-bbd4-696407e0d0b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942239459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1942239459
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2161732881
Short name T92
Test name
Test status
Simulation time 10313611995 ps
CPU time 107.15 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:44:42 PM PDT 24
Peak memory 215044 kb
Host smart-ec36a32a-fde3-462b-8b3c-8cb1d96719b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161732881 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2161732881
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2228158765
Short name T21
Test name
Test status
Simulation time 224765606412 ps
CPU time 476.07 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:50:59 PM PDT 24
Peak memory 211848 kb
Host smart-1ca20738-90a3-4f35-8df2-e224f26a52f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228158765 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2228158765
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.255728263
Short name T108
Test name
Test status
Simulation time 267765081398 ps
CPU time 98.08 seconds
Started Jun 11 01:43:24 PM PDT 24
Finished Jun 11 01:45:03 PM PDT 24
Peak memory 192952 kb
Host smart-a32ddfb2-2ba3-4894-b98d-8a7a1f5b0394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255728263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.255728263
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3177900337
Short name T110
Test name
Test status
Simulation time 59709286636 ps
CPU time 24.83 seconds
Started Jun 11 01:43:09 PM PDT 24
Finished Jun 11 01:43:35 PM PDT 24
Peak memory 198264 kb
Host smart-6840d956-538a-4a8b-9a89-f2bee1ab73cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177900337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3177900337
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2569992636
Short name T106
Test name
Test status
Simulation time 272357874349 ps
CPU time 194.22 seconds
Started Jun 11 01:43:16 PM PDT 24
Finished Jun 11 01:46:31 PM PDT 24
Peak memory 198216 kb
Host smart-8585992e-0bd6-47fe-a2c7-beabc7b77682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569992636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2569992636
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2811357661
Short name T83
Test name
Test status
Simulation time 62514841745 ps
CPU time 636.47 seconds
Started Jun 11 01:43:03 PM PDT 24
Finished Jun 11 01:53:41 PM PDT 24
Peak memory 214184 kb
Host smart-7af7ff64-e136-4663-a7a1-5fefa1047ebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811357661 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2811357661
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3064047372
Short name T157
Test name
Test status
Simulation time 359201109621 ps
CPU time 610.43 seconds
Started Jun 11 01:43:24 PM PDT 24
Finished Jun 11 01:53:35 PM PDT 24
Peak memory 205972 kb
Host smart-b270c6e9-9860-42e2-b420-9bf960f8ce21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064047372 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3064047372
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.334973017
Short name T84
Test name
Test status
Simulation time 154545406000 ps
CPU time 547.48 seconds
Started Jun 11 01:42:42 PM PDT 24
Finished Jun 11 01:51:50 PM PDT 24
Peak memory 207076 kb
Host smart-8a161c13-4311-4e54-a9fa-697d67711080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334973017 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.334973017
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3463226594
Short name T116
Test name
Test status
Simulation time 94453734029 ps
CPU time 143.15 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:45:23 PM PDT 24
Peak memory 198204 kb
Host smart-cdc6e8dc-6e3c-4a7f-b224-92b081684580
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463226594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3463226594
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2655859527
Short name T47
Test name
Test status
Simulation time 165022162193 ps
CPU time 49.89 seconds
Started Jun 11 01:42:47 PM PDT 24
Finished Jun 11 01:43:39 PM PDT 24
Peak memory 192572 kb
Host smart-d50b1c88-8d5c-4cb9-a729-9f717bcf865b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655859527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2655859527
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.438124651
Short name T132
Test name
Test status
Simulation time 69600449613 ps
CPU time 498.25 seconds
Started Jun 11 01:42:56 PM PDT 24
Finished Jun 11 01:51:19 PM PDT 24
Peak memory 214628 kb
Host smart-39988898-9d8b-4d57-a91f-5b1d9c84fed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438124651 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.438124651
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2388377356
Short name T93
Test name
Test status
Simulation time 71726416254 ps
CPU time 176.63 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:45:58 PM PDT 24
Peak memory 207156 kb
Host smart-48afd7f9-06ef-463e-adb1-e399795c15c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388377356 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2388377356
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.663961127
Short name T37
Test name
Test status
Simulation time 230338537033 ps
CPU time 470.83 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:50:47 PM PDT 24
Peak memory 211528 kb
Host smart-2fb1c427-dab1-4b1e-968f-ba205c621ea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663961127 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.663961127
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1392469450
Short name T101
Test name
Test status
Simulation time 207796987699 ps
CPU time 19.26 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:43:20 PM PDT 24
Peak memory 192972 kb
Host smart-0fa7c237-82d4-49d0-b011-c2489fd6b9e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392469450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1392469450
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1652117586
Short name T143
Test name
Test status
Simulation time 247451171140 ps
CPU time 392.39 seconds
Started Jun 11 01:42:58 PM PDT 24
Finished Jun 11 01:49:35 PM PDT 24
Peak memory 198256 kb
Host smart-ea2d9b83-126c-49f0-9f91-97c7e11e6c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652117586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1652117586
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3476086357
Short name T81
Test name
Test status
Simulation time 39722308350 ps
CPU time 407.67 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:49:47 PM PDT 24
Peak memory 199528 kb
Host smart-b5a93dfd-1bbc-4d6a-bf12-1da6ee2034da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476086357 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3476086357
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.679827516
Short name T129
Test name
Test status
Simulation time 341283890258 ps
CPU time 537.63 seconds
Started Jun 11 01:42:46 PM PDT 24
Finished Jun 11 01:51:45 PM PDT 24
Peak memory 192928 kb
Host smart-09de03bd-1b2d-4d08-bb07-ab1ec6540ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679827516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.679827516
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1600333605
Short name T39
Test name
Test status
Simulation time 74751208858 ps
CPU time 146.87 seconds
Started Jun 11 01:42:56 PM PDT 24
Finished Jun 11 01:45:28 PM PDT 24
Peak memory 206884 kb
Host smart-d8a26614-25a1-44c1-8c41-45a9675b64f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600333605 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1600333605
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3447748382
Short name T55
Test name
Test status
Simulation time 26419837342 ps
CPU time 280.33 seconds
Started Jun 11 01:43:19 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 207200 kb
Host smart-970c52b1-04ee-47c0-bba3-748334286b7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447748382 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3447748382
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2340461473
Short name T62
Test name
Test status
Simulation time 10602853818 ps
CPU time 13.2 seconds
Started Jun 11 01:47:55 PM PDT 24
Finished Jun 11 01:48:09 PM PDT 24
Peak memory 195868 kb
Host smart-a7da5486-aa2a-4960-9f13-c498a896d027
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340461473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2340461473
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1406399316
Short name T134
Test name
Test status
Simulation time 19393347078 ps
CPU time 159.51 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:45:32 PM PDT 24
Peak memory 206860 kb
Host smart-767ba846-9617-43b0-a3a4-a301498cf55c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406399316 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1406399316
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2858100929
Short name T146
Test name
Test status
Simulation time 86042038912 ps
CPU time 961.6 seconds
Started Jun 11 01:42:45 PM PDT 24
Finished Jun 11 01:58:47 PM PDT 24
Peak memory 214992 kb
Host smart-f43a1557-0eac-42e4-99eb-94978fc5262a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858100929 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2858100929
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1806677663
Short name T124
Test name
Test status
Simulation time 69965255594 ps
CPU time 53.4 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:43:49 PM PDT 24
Peak memory 191848 kb
Host smart-fd78021f-a733-4720-bccf-7ebfa264c42b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806677663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1806677663
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1713031984
Short name T79
Test name
Test status
Simulation time 2396128543 ps
CPU time 1.56 seconds
Started Jun 11 01:47:46 PM PDT 24
Finished Jun 11 01:47:49 PM PDT 24
Peak memory 191876 kb
Host smart-251b9836-fedf-47de-919e-803366e8f733
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713031984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1713031984
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1101892424
Short name T43
Test name
Test status
Simulation time 67660973768 ps
CPU time 95.95 seconds
Started Jun 11 01:43:19 PM PDT 24
Finished Jun 11 01:44:56 PM PDT 24
Peak memory 192920 kb
Host smart-3ab440f4-b766-4eb5-a19c-4e250d03cb49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101892424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1101892424
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2936356881
Short name T167
Test name
Test status
Simulation time 105675483342 ps
CPU time 11.32 seconds
Started Jun 11 01:42:43 PM PDT 24
Finished Jun 11 01:42:55 PM PDT 24
Peak memory 191880 kb
Host smart-9751848d-35f0-4a47-9b48-cb87347b6d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936356881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2936356881
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3200914204
Short name T29
Test name
Test status
Simulation time 48103510930 ps
CPU time 16.46 seconds
Started Jun 11 01:42:48 PM PDT 24
Finished Jun 11 01:43:07 PM PDT 24
Peak memory 192908 kb
Host smart-ccf04b6e-f7c9-472e-a4e9-f4a2027aa9f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200914204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3200914204
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2819169212
Short name T135
Test name
Test status
Simulation time 710283643220 ps
CPU time 179.02 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:45:58 PM PDT 24
Peak memory 192892 kb
Host smart-03269292-c226-467d-9fb7-7dcf78f8782e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819169212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2819169212
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2190762938
Short name T154
Test name
Test status
Simulation time 837761380526 ps
CPU time 1186.08 seconds
Started Jun 11 01:42:56 PM PDT 24
Finished Jun 11 02:02:47 PM PDT 24
Peak memory 191928 kb
Host smart-db3b9da9-a5f8-46df-9214-f035376de83d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190762938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2190762938
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.4064764368
Short name T41
Test name
Test status
Simulation time 233254694029 ps
CPU time 199.83 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:46:18 PM PDT 24
Peak memory 208540 kb
Host smart-f6da99ac-dd03-41fe-b95e-aabd128ecbf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064764368 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.4064764368
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.4034760152
Short name T40
Test name
Test status
Simulation time 31947763951 ps
CPU time 224.18 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:46:36 PM PDT 24
Peak memory 198768 kb
Host smart-104f7457-eaef-4b09-af2a-d4f58de6d509
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034760152 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.4034760152
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2186381568
Short name T27
Test name
Test status
Simulation time 743021330984 ps
CPU time 179.79 seconds
Started Jun 11 01:42:45 PM PDT 24
Finished Jun 11 01:45:47 PM PDT 24
Peak memory 192544 kb
Host smart-a10285c6-afa7-4d5f-8322-231d62234fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186381568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2186381568
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.4138806959
Short name T48
Test name
Test status
Simulation time 544427960 ps
CPU time 0.86 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:42:55 PM PDT 24
Peak memory 196652 kb
Host smart-9004dacf-6cd9-42e9-8ae6-aeaaea68dd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138806959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.4138806959
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1608411274
Short name T151
Test name
Test status
Simulation time 315443781814 ps
CPU time 656.21 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:53:54 PM PDT 24
Peak memory 206824 kb
Host smart-fd4a3b55-e499-42cb-8a8e-c39d9497ed1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608411274 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1608411274
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3324994562
Short name T127
Test name
Test status
Simulation time 390636508 ps
CPU time 0.87 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:42:55 PM PDT 24
Peak memory 196608 kb
Host smart-cd723bbf-2ef9-42ae-9597-a954afb71546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324994562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3324994562
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.624605899
Short name T172
Test name
Test status
Simulation time 421299695136 ps
CPU time 298.28 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:47:57 PM PDT 24
Peak memory 192612 kb
Host smart-df663960-73b9-439b-b487-20883e8c9744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624605899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.624605899
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1687064396
Short name T111
Test name
Test status
Simulation time 250924867275 ps
CPU time 197.19 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:46:20 PM PDT 24
Peak memory 191944 kb
Host smart-e626f05e-514c-4528-9cb3-9d0adb41ae4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687064396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1687064396
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3412504093
Short name T89
Test name
Test status
Simulation time 197776619400 ps
CPU time 495.81 seconds
Started Jun 11 01:42:43 PM PDT 24
Finished Jun 11 01:51:00 PM PDT 24
Peak memory 203056 kb
Host smart-06ea76b9-6f3d-4d37-848f-398f2fade0f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412504093 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3412504093
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2324122121
Short name T142
Test name
Test status
Simulation time 583307076 ps
CPU time 1.24 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:42:57 PM PDT 24
Peak memory 196616 kb
Host smart-fb63304a-78c2-486b-8cdc-2e1165ed25df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324122121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2324122121
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.994494534
Short name T130
Test name
Test status
Simulation time 418763124 ps
CPU time 0.79 seconds
Started Jun 11 01:42:46 PM PDT 24
Finished Jun 11 01:42:49 PM PDT 24
Peak memory 196520 kb
Host smart-f94e0bca-ed3a-43ab-8a4f-8995216f826b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994494534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.994494534
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.286645877
Short name T162
Test name
Test status
Simulation time 105246036605 ps
CPU time 301.38 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:47:55 PM PDT 24
Peak memory 200632 kb
Host smart-b9c70ce8-e5c4-4d3b-9d34-dba316374227
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286645877 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.286645877
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1318195690
Short name T158
Test name
Test status
Simulation time 42464659314 ps
CPU time 459.5 seconds
Started Jun 11 01:42:48 PM PDT 24
Finished Jun 11 01:50:31 PM PDT 24
Peak memory 206864 kb
Host smart-6e34b597-41fa-4d96-9d5c-a2189db8ea22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318195690 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1318195690
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3204625266
Short name T133
Test name
Test status
Simulation time 158612748886 ps
CPU time 101.47 seconds
Started Jun 11 01:43:00 PM PDT 24
Finished Jun 11 01:44:45 PM PDT 24
Peak memory 191884 kb
Host smart-8081de19-9265-4a83-818d-d177e1c29e32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204625266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3204625266
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3952779059
Short name T26
Test name
Test status
Simulation time 217605475552 ps
CPU time 28.01 seconds
Started Jun 11 01:43:11 PM PDT 24
Finished Jun 11 01:43:40 PM PDT 24
Peak memory 191844 kb
Host smart-e1b7aa17-3985-4fed-b61d-d956397b0ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952779059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3952779059
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3796957047
Short name T139
Test name
Test status
Simulation time 443581356 ps
CPU time 0.7 seconds
Started Jun 11 01:43:10 PM PDT 24
Finished Jun 11 01:43:12 PM PDT 24
Peak memory 196584 kb
Host smart-eb19c5e7-f933-440f-a80d-59ed6536a417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796957047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3796957047
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1721114784
Short name T112
Test name
Test status
Simulation time 553359535690 ps
CPU time 199.89 seconds
Started Jun 11 01:43:04 PM PDT 24
Finished Jun 11 01:46:26 PM PDT 24
Peak memory 191912 kb
Host smart-64727aa5-2f88-46b6-afb7-281ab5b390cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721114784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1721114784
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3619943115
Short name T91
Test name
Test status
Simulation time 562403488 ps
CPU time 1.4 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:43:02 PM PDT 24
Peak memory 196628 kb
Host smart-61f6e3f7-d83a-4fdc-bdcd-134a2775c453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619943115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3619943115
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2523020305
Short name T128
Test name
Test status
Simulation time 496421328256 ps
CPU time 256.45 seconds
Started Jun 11 01:42:56 PM PDT 24
Finished Jun 11 01:47:17 PM PDT 24
Peak memory 198300 kb
Host smart-47807975-1207-4adc-8df2-b0cac4458b4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523020305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2523020305
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2136260917
Short name T150
Test name
Test status
Simulation time 188702408063 ps
CPU time 289.61 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:47:47 PM PDT 24
Peak memory 193024 kb
Host smart-cc3c6bcc-60d2-4292-a1b2-f3e5698b43d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136260917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2136260917
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2601183089
Short name T144
Test name
Test status
Simulation time 385797130 ps
CPU time 1.27 seconds
Started Jun 11 01:42:56 PM PDT 24
Finished Jun 11 01:43:02 PM PDT 24
Peak memory 196576 kb
Host smart-fad6c030-94ac-48ca-bcb1-a1920ae1611a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601183089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2601183089
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.449366853
Short name T12
Test name
Test status
Simulation time 576971796 ps
CPU time 0.78 seconds
Started Jun 11 01:43:02 PM PDT 24
Finished Jun 11 01:43:05 PM PDT 24
Peak memory 196612 kb
Host smart-deb6b740-056d-4bef-aeb0-78e91bddc9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449366853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.449366853
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3975009548
Short name T123
Test name
Test status
Simulation time 567879794 ps
CPU time 0.96 seconds
Started Jun 11 01:43:16 PM PDT 24
Finished Jun 11 01:43:18 PM PDT 24
Peak memory 196504 kb
Host smart-9cfeeb40-f8b0-4453-ab95-21cd42305ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975009548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3975009548
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3329354052
Short name T117
Test name
Test status
Simulation time 399649397 ps
CPU time 0.79 seconds
Started Jun 11 01:42:39 PM PDT 24
Finished Jun 11 01:42:40 PM PDT 24
Peak memory 196608 kb
Host smart-74d74922-f503-487a-8443-5990607eef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329354052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3329354052
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3337287817
Short name T118
Test name
Test status
Simulation time 62335673630 ps
CPU time 23.4 seconds
Started Jun 11 01:42:46 PM PDT 24
Finished Jun 11 01:43:12 PM PDT 24
Peak memory 198120 kb
Host smart-5f9404ba-5927-4662-86bf-e65d83bd1acc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337287817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3337287817
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2451317453
Short name T160
Test name
Test status
Simulation time 112454111922 ps
CPU time 186.17 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:46:05 PM PDT 24
Peak memory 200088 kb
Host smart-cfb3bc28-3ce3-468c-9d28-bf48fb5b815d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451317453 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2451317453
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1743159608
Short name T149
Test name
Test status
Simulation time 112710453878 ps
CPU time 88.03 seconds
Started Jun 11 01:43:01 PM PDT 24
Finished Jun 11 01:44:32 PM PDT 24
Peak memory 184176 kb
Host smart-cf71bfeb-3f9b-4bc8-bd67-2c193469d4dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743159608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1743159608
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.457773627
Short name T145
Test name
Test status
Simulation time 413056194 ps
CPU time 0.75 seconds
Started Jun 11 01:43:02 PM PDT 24
Finished Jun 11 01:43:06 PM PDT 24
Peak memory 196628 kb
Host smart-14397298-ae5c-4b3e-a730-87f5eb0753a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457773627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.457773627
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.544208460
Short name T96
Test name
Test status
Simulation time 474083731 ps
CPU time 0.72 seconds
Started Jun 11 01:42:47 PM PDT 24
Finished Jun 11 01:42:50 PM PDT 24
Peak memory 196584 kb
Host smart-86b0acd6-cca7-4623-96ce-85caba6052ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544208460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.544208460
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1857174748
Short name T36
Test name
Test status
Simulation time 50506253507 ps
CPU time 199.17 seconds
Started Jun 11 01:42:45 PM PDT 24
Finished Jun 11 01:46:06 PM PDT 24
Peak memory 214152 kb
Host smart-cff4343c-cce0-4c53-8a75-41bdb5e8ff3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857174748 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1857174748
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3214754983
Short name T94
Test name
Test status
Simulation time 568383759 ps
CPU time 0.74 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:42:56 PM PDT 24
Peak memory 196772 kb
Host smart-437cbae2-ebe3-49ab-ad6f-81f547cc5624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214754983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3214754983
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1028648470
Short name T131
Test name
Test status
Simulation time 290173383346 ps
CPU time 54.98 seconds
Started Jun 11 01:43:00 PM PDT 24
Finished Jun 11 01:43:58 PM PDT 24
Peak memory 193004 kb
Host smart-7447e82c-3968-4f91-8b9b-2065d50ba759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028648470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1028648470
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2151409892
Short name T121
Test name
Test status
Simulation time 645864908 ps
CPU time 0.62 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:42:58 PM PDT 24
Peak memory 196608 kb
Host smart-65d8c7b0-ab8e-4b82-91d8-f891922a0d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151409892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2151409892
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.842092147
Short name T159
Test name
Test status
Simulation time 43028851198 ps
CPU time 57.31 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:43:54 PM PDT 24
Peak memory 191920 kb
Host smart-90d1811c-760f-46bb-a657-bcaa1eec4091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842092147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.842092147
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.4047469514
Short name T136
Test name
Test status
Simulation time 375765614 ps
CPU time 1.23 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:42:53 PM PDT 24
Peak memory 196468 kb
Host smart-bb4d9fa9-5bd1-4394-9483-f3a9a43aa377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047469514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.4047469514
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.4084464810
Short name T126
Test name
Test status
Simulation time 611674719 ps
CPU time 0.82 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:42:59 PM PDT 24
Peak memory 196624 kb
Host smart-b5fe2459-9d03-4c76-8e9b-8a7672e15c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084464810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.4084464810
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.4055628654
Short name T125
Test name
Test status
Simulation time 390884672 ps
CPU time 0.83 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:42:52 PM PDT 24
Peak memory 196484 kb
Host smart-84301827-d5fe-474c-83e1-50b49865a83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055628654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.4055628654
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1711769243
Short name T4
Test name
Test status
Simulation time 57981915702 ps
CPU time 369.26 seconds
Started Jun 11 01:43:02 PM PDT 24
Finished Jun 11 01:49:14 PM PDT 24
Peak memory 208456 kb
Host smart-dc3df6d7-b6b9-460a-b17c-ce9bdb36d8e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711769243 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1711769243
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3890594118
Short name T141
Test name
Test status
Simulation time 410086706 ps
CPU time 1.19 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:42:53 PM PDT 24
Peak memory 196620 kb
Host smart-0f8a26c4-da91-417e-a02e-17beefbcf4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890594118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3890594118
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.55520863
Short name T179
Test name
Test status
Simulation time 387268825 ps
CPU time 0.75 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:43:02 PM PDT 24
Peak memory 196580 kb
Host smart-7204612c-a120-43a8-9123-cdfcdc6278b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55520863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.55520863
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1418715028
Short name T20
Test name
Test status
Simulation time 492082056 ps
CPU time 1.39 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:42:59 PM PDT 24
Peak memory 196544 kb
Host smart-8b021b65-f160-40ed-9a1d-fc5bd3b1a354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418715028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1418715028
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.718564091
Short name T156
Test name
Test status
Simulation time 403892794 ps
CPU time 1.13 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:42:58 PM PDT 24
Peak memory 196560 kb
Host smart-20a5f12e-9485-4257-8371-d7501e379346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718564091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.718564091
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3117406134
Short name T169
Test name
Test status
Simulation time 644483721 ps
CPU time 1.04 seconds
Started Jun 11 01:43:02 PM PDT 24
Finished Jun 11 01:43:06 PM PDT 24
Peak memory 196580 kb
Host smart-a7f815f8-74a5-4503-a7d5-33ff567f3eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117406134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3117406134
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3445347605
Short name T175
Test name
Test status
Simulation time 556502586 ps
CPU time 1.21 seconds
Started Jun 11 01:43:02 PM PDT 24
Finished Jun 11 01:43:06 PM PDT 24
Peak memory 196548 kb
Host smart-bedb1459-fc20-4825-8e4d-55532259e243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445347605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3445347605
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1174725297
Short name T28
Test name
Test status
Simulation time 361882504 ps
CPU time 0.9 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:42:56 PM PDT 24
Peak memory 196524 kb
Host smart-f6008da9-2200-4fd5-b043-56e443764fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174725297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1174725297
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.834173811
Short name T5
Test name
Test status
Simulation time 538512734 ps
CPU time 0.63 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:42:54 PM PDT 24
Peak memory 196832 kb
Host smart-6d7b6416-efb0-4ead-85e0-ebd1b21a8447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834173811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.834173811
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3291278257
Short name T182
Test name
Test status
Simulation time 573710196 ps
CPU time 0.79 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:42:54 PM PDT 24
Peak memory 196592 kb
Host smart-f4fa4b46-3243-4934-896d-f9be7d90eb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291278257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3291278257
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.793477984
Short name T138
Test name
Test status
Simulation time 547827252 ps
CPU time 1.04 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:43:00 PM PDT 24
Peak memory 196484 kb
Host smart-f593f18e-2231-4bde-a8d7-83f5459ee1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793477984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.793477984
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.4116964711
Short name T165
Test name
Test status
Simulation time 462850952 ps
CPU time 1.4 seconds
Started Jun 11 01:42:56 PM PDT 24
Finished Jun 11 01:43:03 PM PDT 24
Peak memory 196556 kb
Host smart-2866db13-c7fe-4a1b-9d82-c94468b79163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116964711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4116964711
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.802066337
Short name T168
Test name
Test status
Simulation time 377148771 ps
CPU time 0.73 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:43:01 PM PDT 24
Peak memory 196636 kb
Host smart-3a4b62f9-f244-47b0-b39e-17851ee82168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802066337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.802066337
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.4289549711
Short name T155
Test name
Test status
Simulation time 379560112 ps
CPU time 1.27 seconds
Started Jun 11 01:42:57 PM PDT 24
Finished Jun 11 01:43:03 PM PDT 24
Peak memory 196532 kb
Host smart-e4a48268-f4b4-455d-a902-ee27b0deb388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289549711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.4289549711
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3251044091
Short name T184
Test name
Test status
Simulation time 123808207268 ps
CPU time 231.78 seconds
Started Jun 11 01:42:40 PM PDT 24
Finished Jun 11 01:46:33 PM PDT 24
Peak memory 215004 kb
Host smart-41744b27-4cb8-4a9a-bbb8-3f14ab1fd37d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251044091 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3251044091
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2742861500
Short name T181
Test name
Test status
Simulation time 582504581 ps
CPU time 0.98 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:42:55 PM PDT 24
Peak memory 196520 kb
Host smart-98eff8b2-ca08-4992-a1c9-90ed0d0376c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742861500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2742861500
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.4245090739
Short name T174
Test name
Test status
Simulation time 574580320 ps
CPU time 1.49 seconds
Started Jun 11 01:43:03 PM PDT 24
Finished Jun 11 01:43:07 PM PDT 24
Peak memory 196572 kb
Host smart-ef127ec4-3946-4c26-916f-43b6f44b1543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245090739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.4245090739
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1058348569
Short name T97
Test name
Test status
Simulation time 535918881 ps
CPU time 0.79 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:43:02 PM PDT 24
Peak memory 196572 kb
Host smart-c7d41964-3050-4a75-909f-29dcd274aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058348569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1058348569
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1830400599
Short name T82
Test name
Test status
Simulation time 18252786666 ps
CPU time 134.75 seconds
Started Jun 11 01:43:14 PM PDT 24
Finished Jun 11 01:45:29 PM PDT 24
Peak memory 206848 kb
Host smart-7b6ed18e-5c3d-4d3f-95b8-6ba625aa91b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830400599 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1830400599
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1644614988
Short name T163
Test name
Test status
Simulation time 133213127926 ps
CPU time 65.14 seconds
Started Jun 11 01:43:26 PM PDT 24
Finished Jun 11 01:44:32 PM PDT 24
Peak memory 191952 kb
Host smart-f10d47ec-0100-4f7f-a347-96c074ac91e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644614988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1644614988
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.697952
Short name T189
Test name
Test status
Simulation time 7584309908 ps
CPU time 13.35 seconds
Started Jun 11 01:47:59 PM PDT 24
Finished Jun 11 01:48:14 PM PDT 24
Peak memory 198220 kb
Host smart-2a203b2c-5758-45e7-91c9-7582a195c756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_in
tg_err.697952
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3539856569
Short name T54
Test name
Test status
Simulation time 349419214 ps
CPU time 1.15 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:43:00 PM PDT 24
Peak memory 196560 kb
Host smart-e39e2de4-f2ad-4ff7-8af4-28c99b25d1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539856569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3539856569
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1262112972
Short name T180
Test name
Test status
Simulation time 486062649 ps
CPU time 0.75 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:42:55 PM PDT 24
Peak memory 196388 kb
Host smart-7cbf2949-3ef6-41e5-8df3-8c712c0e3f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262112972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1262112972
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1521159828
Short name T164
Test name
Test status
Simulation time 534352251 ps
CPU time 1.45 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:42:57 PM PDT 24
Peak memory 196552 kb
Host smart-5b9f4211-c857-4af4-810b-d73fa0d52b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521159828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1521159828
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2639712210
Short name T19
Test name
Test status
Simulation time 605267768 ps
CPU time 0.7 seconds
Started Jun 11 01:42:46 PM PDT 24
Finished Jun 11 01:42:48 PM PDT 24
Peak memory 196544 kb
Host smart-09b5da9e-a2ea-4464-8e57-153d0d17249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639712210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2639712210
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3631580038
Short name T185
Test name
Test status
Simulation time 441830627 ps
CPU time 0.72 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:42:54 PM PDT 24
Peak memory 196652 kb
Host smart-a3f9fbb3-6485-4120-93c3-ddb932da51c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631580038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3631580038
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1664132628
Short name T45
Test name
Test status
Simulation time 555344270 ps
CPU time 1.06 seconds
Started Jun 11 01:42:58 PM PDT 24
Finished Jun 11 01:43:04 PM PDT 24
Peak memory 196404 kb
Host smart-23cba474-e20a-4c2f-a330-09f46e0aee52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664132628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1664132628
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1249292046
Short name T176
Test name
Test status
Simulation time 388520728 ps
CPU time 0.7 seconds
Started Jun 11 01:43:00 PM PDT 24
Finished Jun 11 01:43:04 PM PDT 24
Peak memory 196548 kb
Host smart-f1b50fb3-fd92-4e39-b5fc-929279ffae74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249292046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1249292046
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1838316138
Short name T161
Test name
Test status
Simulation time 364533630 ps
CPU time 1.15 seconds
Started Jun 11 01:43:01 PM PDT 24
Finished Jun 11 01:43:05 PM PDT 24
Peak memory 196620 kb
Host smart-a42659d0-cc3d-4a4b-add4-930f1c4b5714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838316138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1838316138
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3360735080
Short name T153
Test name
Test status
Simulation time 563293153 ps
CPU time 0.79 seconds
Started Jun 11 01:43:14 PM PDT 24
Finished Jun 11 01:43:15 PM PDT 24
Peak memory 196556 kb
Host smart-198e1872-cf21-4593-8914-c248ff08bc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360735080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3360735080
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1219642968
Short name T173
Test name
Test status
Simulation time 553049578 ps
CPU time 1.36 seconds
Started Jun 11 01:42:47 PM PDT 24
Finished Jun 11 01:42:51 PM PDT 24
Peak memory 196204 kb
Host smart-af98e8b1-4293-40ca-b696-4ad0f9b83e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219642968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1219642968
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1271950983
Short name T171
Test name
Test status
Simulation time 179468047950 ps
CPU time 286.66 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:47:41 PM PDT 24
Peak memory 198028 kb
Host smart-21925cd1-1472-41b5-8f8f-b35223f98c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271950983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1271950983
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4228260106
Short name T166
Test name
Test status
Simulation time 582681140 ps
CPU time 0.84 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:43:02 PM PDT 24
Peak memory 196548 kb
Host smart-7ea74bf5-8947-4612-84af-29b4c52cd453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228260106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4228260106
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3347647943
Short name T24
Test name
Test status
Simulation time 357201858 ps
CPU time 1.13 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:42:54 PM PDT 24
Peak memory 196660 kb
Host smart-24680c62-d058-4eca-8b89-104d004eb9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347647943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3347647943
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3713328307
Short name T305
Test name
Test status
Simulation time 673043522 ps
CPU time 2.23 seconds
Started Jun 11 01:47:46 PM PDT 24
Finished Jun 11 01:47:49 PM PDT 24
Peak memory 193748 kb
Host smart-2ea21061-8ae8-4ff7-8d5e-8754b00a90f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713328307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3713328307
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.63323311
Short name T67
Test name
Test status
Simulation time 7370168867 ps
CPU time 12.29 seconds
Started Jun 11 01:47:52 PM PDT 24
Finished Jun 11 01:48:05 PM PDT 24
Peak memory 195980 kb
Host smart-7ce651bc-e3c6-4a5d-979b-7e25461949dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63323311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit
_bash.63323311
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4025389373
Short name T405
Test name
Test status
Simulation time 579243302 ps
CPU time 1.38 seconds
Started Jun 11 01:47:53 PM PDT 24
Finished Jun 11 01:47:55 PM PDT 24
Peak memory 183680 kb
Host smart-1eaf4507-131b-417c-bac5-c634a5b41172
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025389373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.4025389373
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3127691202
Short name T285
Test name
Test status
Simulation time 583987768 ps
CPU time 1.49 seconds
Started Jun 11 01:47:54 PM PDT 24
Finished Jun 11 01:47:57 PM PDT 24
Peak memory 195884 kb
Host smart-30a72a90-1245-43a9-bc4d-da945ded1f11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127691202 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3127691202
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2002045428
Short name T384
Test name
Test status
Simulation time 626790491 ps
CPU time 0.67 seconds
Started Jun 11 01:47:52 PM PDT 24
Finished Jun 11 01:47:53 PM PDT 24
Peak memory 192992 kb
Host smart-337e8f20-4a56-4cb7-a829-863e78baaeb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002045428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2002045428
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.847970723
Short name T378
Test name
Test status
Simulation time 278938323 ps
CPU time 0.94 seconds
Started Jun 11 01:47:51 PM PDT 24
Finished Jun 11 01:47:52 PM PDT 24
Peak memory 183552 kb
Host smart-b411b69f-7d47-448f-99c6-256f2efbe909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847970723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.847970723
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2530571733
Short name T350
Test name
Test status
Simulation time 321055767 ps
CPU time 1.07 seconds
Started Jun 11 01:47:56 PM PDT 24
Finished Jun 11 01:47:59 PM PDT 24
Peak memory 183548 kb
Host smart-787dc653-c7c8-45c6-a5e4-a9bcabc2a8b6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530571733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2530571733
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1720898357
Short name T362
Test name
Test status
Simulation time 353553345 ps
CPU time 1.06 seconds
Started Jun 11 01:47:53 PM PDT 24
Finished Jun 11 01:47:55 PM PDT 24
Peak memory 183632 kb
Host smart-56e1bd06-b75a-44f5-b008-7c536bcc0a76
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720898357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1720898357
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1080228180
Short name T374
Test name
Test status
Simulation time 1318035331 ps
CPU time 1.7 seconds
Started Jun 11 01:47:55 PM PDT 24
Finished Jun 11 01:47:58 PM PDT 24
Peak memory 193920 kb
Host smart-75d460ea-b947-4f26-8c3b-a4f68fb7e8c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080228180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1080228180
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.474699449
Short name T367
Test name
Test status
Simulation time 715213437 ps
CPU time 2.03 seconds
Started Jun 11 01:47:56 PM PDT 24
Finished Jun 11 01:47:59 PM PDT 24
Peak memory 198464 kb
Host smart-88bab3b3-46c4-4e69-b1d4-603db2dc22a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474699449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.474699449
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2842377205
Short name T352
Test name
Test status
Simulation time 8450471085 ps
CPU time 7.02 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:48:06 PM PDT 24
Peak memory 198116 kb
Host smart-f491b485-57c7-4141-b3cd-be5148f93338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842377205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2842377205
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3586954887
Short name T315
Test name
Test status
Simulation time 579646202 ps
CPU time 0.9 seconds
Started Jun 11 01:47:55 PM PDT 24
Finished Jun 11 01:47:57 PM PDT 24
Peak memory 183588 kb
Host smart-d826fd04-720a-47e9-b6a7-a15c58f9298a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586954887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3586954887
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3592861639
Short name T297
Test name
Test status
Simulation time 820661287 ps
CPU time 0.91 seconds
Started Jun 11 01:47:55 PM PDT 24
Finished Jun 11 01:47:57 PM PDT 24
Peak memory 183688 kb
Host smart-e5c67a22-0da3-4542-b5a3-c971eb520b12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592861639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3592861639
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3623955853
Short name T294
Test name
Test status
Simulation time 383963524 ps
CPU time 1.25 seconds
Started Jun 11 01:47:55 PM PDT 24
Finished Jun 11 01:47:58 PM PDT 24
Peak memory 195896 kb
Host smart-897ba366-5c86-4abb-b04c-240c486f5b5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623955853 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3623955853
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2011952471
Short name T389
Test name
Test status
Simulation time 409192666 ps
CPU time 0.85 seconds
Started Jun 11 01:47:52 PM PDT 24
Finished Jun 11 01:47:54 PM PDT 24
Peak memory 183716 kb
Host smart-6acbcf3d-3508-458f-a802-c4c9be943daa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011952471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2011952471
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2947370230
Short name T415
Test name
Test status
Simulation time 489281583 ps
CPU time 0.71 seconds
Started Jun 11 01:47:47 PM PDT 24
Finished Jun 11 01:47:49 PM PDT 24
Peak memory 183632 kb
Host smart-87b04b83-569a-4ce2-aba9-b50f58f21547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947370230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2947370230
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.865202793
Short name T327
Test name
Test status
Simulation time 431197693 ps
CPU time 0.81 seconds
Started Jun 11 01:47:56 PM PDT 24
Finished Jun 11 01:47:59 PM PDT 24
Peak memory 183476 kb
Host smart-4c8e7cf3-07dc-4791-be12-080329b6304e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865202793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.865202793
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2990894707
Short name T341
Test name
Test status
Simulation time 330928881 ps
CPU time 1.04 seconds
Started Jun 11 01:47:48 PM PDT 24
Finished Jun 11 01:47:50 PM PDT 24
Peak memory 183636 kb
Host smart-8cca2b38-bb8e-45a5-9f5d-3856eebb8604
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990894707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2990894707
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2654926177
Short name T329
Test name
Test status
Simulation time 478019018 ps
CPU time 2.13 seconds
Started Jun 11 01:47:51 PM PDT 24
Finished Jun 11 01:47:54 PM PDT 24
Peak memory 198408 kb
Host smart-54a2b183-5695-44e7-a628-4ac67d20aa09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654926177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2654926177
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3689046674
Short name T414
Test name
Test status
Simulation time 8281330135 ps
CPU time 14.23 seconds
Started Jun 11 01:47:55 PM PDT 24
Finished Jun 11 01:48:10 PM PDT 24
Peak memory 197928 kb
Host smart-f2ba10dd-5068-490c-9aa8-e69166cf77a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689046674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3689046674
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1233440154
Short name T417
Test name
Test status
Simulation time 604484275 ps
CPU time 0.86 seconds
Started Jun 11 01:47:59 PM PDT 24
Finished Jun 11 01:48:02 PM PDT 24
Peak memory 196644 kb
Host smart-c99662fd-a3b7-422f-936a-5ba02f267a4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233440154 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1233440154
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2591915809
Short name T291
Test name
Test status
Simulation time 584724148 ps
CPU time 0.62 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:01 PM PDT 24
Peak memory 193208 kb
Host smart-46c2e364-d44a-4ce6-8daa-384070a80964
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591915809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2591915809
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.653433266
Short name T323
Test name
Test status
Simulation time 412019228 ps
CPU time 0.87 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 183636 kb
Host smart-d0de8b7f-4754-4fde-8756-78bccd36187a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653433266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.653433266
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2310748940
Short name T72
Test name
Test status
Simulation time 2405601567 ps
CPU time 1.5 seconds
Started Jun 11 01:48:04 PM PDT 24
Finished Jun 11 01:48:07 PM PDT 24
Peak memory 195012 kb
Host smart-89108961-29bb-47fd-ba3f-1b8ee3a456eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310748940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2310748940
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2228814334
Short name T416
Test name
Test status
Simulation time 637501432 ps
CPU time 1.22 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 198400 kb
Host smart-6da66213-5d10-410e-a7a9-f4827ed51223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228814334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2228814334
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1998800123
Short name T292
Test name
Test status
Simulation time 8019942777 ps
CPU time 13.14 seconds
Started Jun 11 01:47:59 PM PDT 24
Finished Jun 11 01:48:15 PM PDT 24
Peak memory 198144 kb
Host smart-d27d1480-f833-4e2e-92de-6e2139558a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998800123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1998800123
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.770536790
Short name T317
Test name
Test status
Simulation time 624480521 ps
CPU time 1 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:06 PM PDT 24
Peak memory 197416 kb
Host smart-d1a3a9b0-f3bb-408a-afa7-ea29fe91531c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770536790 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.770536790
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2551576403
Short name T73
Test name
Test status
Simulation time 475227486 ps
CPU time 0.7 seconds
Started Jun 11 01:48:06 PM PDT 24
Finished Jun 11 01:48:09 PM PDT 24
Peak memory 192920 kb
Host smart-d9593fa0-69eb-4993-95fa-fa326e5bec3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551576403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2551576403
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3290094988
Short name T281
Test name
Test status
Simulation time 527182779 ps
CPU time 0.74 seconds
Started Jun 11 01:48:00 PM PDT 24
Finished Jun 11 01:48:03 PM PDT 24
Peak memory 183588 kb
Host smart-72771970-5420-4c41-a618-48deab074b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290094988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3290094988
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2398772528
Short name T355
Test name
Test status
Simulation time 1088210312 ps
CPU time 2.28 seconds
Started Jun 11 01:48:01 PM PDT 24
Finished Jun 11 01:48:05 PM PDT 24
Peak memory 192904 kb
Host smart-d4200d38-7494-4df3-9874-54936fdaca6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398772528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2398772528
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1217799032
Short name T391
Test name
Test status
Simulation time 556204124 ps
CPU time 2.48 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:03 PM PDT 24
Peak memory 198436 kb
Host smart-510305c8-3923-4f45-8347-948e9eb62f75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217799032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1217799032
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2556416628
Short name T382
Test name
Test status
Simulation time 8451961906 ps
CPU time 2.66 seconds
Started Jun 11 01:47:59 PM PDT 24
Finished Jun 11 01:48:04 PM PDT 24
Peak memory 197896 kb
Host smart-7edbc3d4-d4a4-4ebf-8938-75c5688a3c1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556416628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2556416628
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3493764170
Short name T420
Test name
Test status
Simulation time 359053355 ps
CPU time 0.78 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:06 PM PDT 24
Peak memory 195500 kb
Host smart-0857f3d7-0b39-4695-a019-37c6ad6d59b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493764170 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3493764170
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2509997297
Short name T61
Test name
Test status
Simulation time 291938097 ps
CPU time 0.98 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:02 PM PDT 24
Peak memory 192912 kb
Host smart-bc5ee92f-eca4-46a5-89aa-0aff3ebdc57b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509997297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2509997297
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4093390088
Short name T403
Test name
Test status
Simulation time 364711730 ps
CPU time 1.09 seconds
Started Jun 11 01:48:04 PM PDT 24
Finished Jun 11 01:48:07 PM PDT 24
Peak memory 192788 kb
Host smart-038c387e-1447-48c8-8d88-410a28a9295b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093390088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.4093390088
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2875172360
Short name T395
Test name
Test status
Simulation time 1408674242 ps
CPU time 1.39 seconds
Started Jun 11 01:48:12 PM PDT 24
Finished Jun 11 01:48:17 PM PDT 24
Peak memory 193928 kb
Host smart-3452c8db-2488-450e-a1a9-0f80665ba6d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875172360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2875172360
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1921516127
Short name T334
Test name
Test status
Simulation time 533325357 ps
CPU time 1.81 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:07 PM PDT 24
Peak memory 198600 kb
Host smart-82ffd630-9aca-4e1c-b2fe-112d8194c811
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921516127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1921516127
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2575500999
Short name T333
Test name
Test status
Simulation time 501647089 ps
CPU time 0.82 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:05 PM PDT 24
Peak memory 195408 kb
Host smart-206898e2-a6a3-4106-93ff-7a701a5eba25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575500999 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2575500999
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3651387275
Short name T68
Test name
Test status
Simulation time 502887339 ps
CPU time 1.07 seconds
Started Jun 11 01:48:01 PM PDT 24
Finished Jun 11 01:48:04 PM PDT 24
Peak memory 193076 kb
Host smart-54acb1be-0931-46c3-a8fd-efb0b9377a2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651387275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3651387275
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3235555139
Short name T377
Test name
Test status
Simulation time 458583127 ps
CPU time 0.62 seconds
Started Jun 11 01:48:02 PM PDT 24
Finished Jun 11 01:48:04 PM PDT 24
Peak memory 183480 kb
Host smart-6df9f7e8-3f96-4fa5-93d3-2ac0bea86b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235555139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3235555139
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.940386471
Short name T387
Test name
Test status
Simulation time 1293615667 ps
CPU time 1.24 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 192780 kb
Host smart-76fb1b8f-1054-4ca8-a5db-50bb2575fabf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940386471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.940386471
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.651394674
Short name T402
Test name
Test status
Simulation time 502712459 ps
CPU time 1.71 seconds
Started Jun 11 01:48:04 PM PDT 24
Finished Jun 11 01:48:08 PM PDT 24
Peak memory 198516 kb
Host smart-00fb2cdd-f29e-4347-b241-e99f7a14d057
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651394674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.651394674
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.562091446
Short name T31
Test name
Test status
Simulation time 3809698309 ps
CPU time 1.89 seconds
Started Jun 11 01:48:04 PM PDT 24
Finished Jun 11 01:48:08 PM PDT 24
Peak memory 197012 kb
Host smart-84611eff-339c-4241-a83f-a012ff7c203c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562091446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.562091446
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2974288294
Short name T322
Test name
Test status
Simulation time 593836579 ps
CPU time 1.44 seconds
Started Jun 11 01:48:09 PM PDT 24
Finished Jun 11 01:48:13 PM PDT 24
Peak memory 196320 kb
Host smart-88e5a079-fa4f-4e6f-b8a0-ced937b3ad29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974288294 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2974288294
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3645182780
Short name T33
Test name
Test status
Simulation time 406770317 ps
CPU time 1.19 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:06 PM PDT 24
Peak memory 192880 kb
Host smart-63d8f318-4c3f-48b1-87f7-0edd9f57b033
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645182780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3645182780
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.611699642
Short name T380
Test name
Test status
Simulation time 491826478 ps
CPU time 1.36 seconds
Started Jun 11 01:47:59 PM PDT 24
Finished Jun 11 01:48:03 PM PDT 24
Peak memory 192844 kb
Host smart-69b4e2db-1163-4ad2-a54f-ae1f42fd5b57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611699642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.611699642
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1672520476
Short name T75
Test name
Test status
Simulation time 2358430976 ps
CPU time 2.14 seconds
Started Jun 11 01:48:09 PM PDT 24
Finished Jun 11 01:48:13 PM PDT 24
Peak memory 192136 kb
Host smart-19cd2230-8d61-4b4a-8279-c07a0f0a736d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672520476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1672520476
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2102938528
Short name T311
Test name
Test status
Simulation time 359858783 ps
CPU time 2.38 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:07 PM PDT 24
Peak memory 198404 kb
Host smart-5a7823e5-6701-4800-9b36-21ba0f6753f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102938528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2102938528
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1640413482
Short name T354
Test name
Test status
Simulation time 3834972802 ps
CPU time 6.78 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:11 PM PDT 24
Peak memory 197572 kb
Host smart-c6e094cd-a264-43af-93db-d06de1a139e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640413482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1640413482
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3190048357
Short name T343
Test name
Test status
Simulation time 570310935 ps
CPU time 0.8 seconds
Started Jun 11 01:48:06 PM PDT 24
Finished Jun 11 01:48:08 PM PDT 24
Peak memory 195420 kb
Host smart-009b251f-dd51-4599-9fee-62fd4bf8757e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190048357 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3190048357
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1966407396
Short name T63
Test name
Test status
Simulation time 441602279 ps
CPU time 1.17 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:01 PM PDT 24
Peak memory 183744 kb
Host smart-5fa77631-a977-4df0-aaff-8bec4bd92d00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966407396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1966407396
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.157976304
Short name T306
Test name
Test status
Simulation time 318934814 ps
CPU time 0.94 seconds
Started Jun 11 01:48:05 PM PDT 24
Finished Jun 11 01:48:08 PM PDT 24
Peak memory 183632 kb
Host smart-34e9255e-0f9e-4b7f-aaf4-0930477b5950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157976304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.157976304
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1564344086
Short name T74
Test name
Test status
Simulation time 1231844265 ps
CPU time 2.31 seconds
Started Jun 11 01:48:04 PM PDT 24
Finished Jun 11 01:48:08 PM PDT 24
Peak memory 183644 kb
Host smart-76619115-f253-4255-bb58-628669f0f4b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564344086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1564344086
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.570299726
Short name T320
Test name
Test status
Simulation time 598115045 ps
CPU time 1.67 seconds
Started Jun 11 01:48:02 PM PDT 24
Finished Jun 11 01:48:06 PM PDT 24
Peak memory 198336 kb
Host smart-3247926e-048e-4eaf-a415-90625d9b7be2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570299726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.570299726
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1397942446
Short name T326
Test name
Test status
Simulation time 8535227402 ps
CPU time 4.46 seconds
Started Jun 11 01:48:06 PM PDT 24
Finished Jun 11 01:48:12 PM PDT 24
Peak memory 198160 kb
Host smart-221a6923-c668-470b-ae3d-4718d22aa1f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397942446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1397942446
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1966960195
Short name T301
Test name
Test status
Simulation time 540765803 ps
CPU time 1.44 seconds
Started Jun 11 01:48:09 PM PDT 24
Finished Jun 11 01:48:13 PM PDT 24
Peak memory 197280 kb
Host smart-1b75707e-50dd-4bf9-880b-699f605829c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966960195 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1966960195
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3368113157
Short name T392
Test name
Test status
Simulation time 526757580 ps
CPU time 1.53 seconds
Started Jun 11 01:48:06 PM PDT 24
Finished Jun 11 01:48:10 PM PDT 24
Peak memory 193944 kb
Host smart-7869eb66-ae40-4e23-a6c6-ed9f6f9e3d4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368113157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3368113157
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3489599173
Short name T372
Test name
Test status
Simulation time 290111724 ps
CPU time 0.73 seconds
Started Jun 11 01:48:09 PM PDT 24
Finished Jun 11 01:48:12 PM PDT 24
Peak memory 183792 kb
Host smart-7327b6ad-567f-49c4-ac3c-4f9fc4389a4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489599173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3489599173
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.259006439
Short name T348
Test name
Test status
Simulation time 1449813589 ps
CPU time 2.2 seconds
Started Jun 11 01:48:05 PM PDT 24
Finished Jun 11 01:48:09 PM PDT 24
Peak memory 192932 kb
Host smart-c2bafd8f-fee1-407f-8da0-5cc3c8dbdbdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259006439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.259006439
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3662956942
Short name T412
Test name
Test status
Simulation time 609834688 ps
CPU time 1.38 seconds
Started Jun 11 01:48:05 PM PDT 24
Finished Jun 11 01:48:09 PM PDT 24
Peak memory 198412 kb
Host smart-1d222518-ab85-48d1-8324-ef92a141eb58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662956942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3662956942
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1789369049
Short name T186
Test name
Test status
Simulation time 4606895855 ps
CPU time 1.49 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:07 PM PDT 24
Peak memory 198036 kb
Host smart-2a56fe57-2c97-467b-b845-565f13f10cc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789369049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1789369049
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.96049512
Short name T358
Test name
Test status
Simulation time 374033395 ps
CPU time 1.18 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:15 PM PDT 24
Peak memory 195224 kb
Host smart-206cb9ad-7a79-4ae3-b2f3-9754c2efebc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96049512 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.96049512
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1081185850
Short name T70
Test name
Test status
Simulation time 498013869 ps
CPU time 0.81 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:15 PM PDT 24
Peak memory 192852 kb
Host smart-b433c43d-30d1-4f8f-b00e-798eb0e089f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081185850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1081185850
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2572712946
Short name T300
Test name
Test status
Simulation time 323189179 ps
CPU time 0.64 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:01 PM PDT 24
Peak memory 183612 kb
Host smart-6671a2f8-8a9d-43a0-b286-aa536467dae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572712946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2572712946
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1639814518
Short name T419
Test name
Test status
Simulation time 2949568842 ps
CPU time 2.92 seconds
Started Jun 11 01:48:07 PM PDT 24
Finished Jun 11 01:48:12 PM PDT 24
Peak memory 195252 kb
Host smart-3ca226f0-e7a1-40f7-aba7-74a9e2de9a97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639814518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1639814518
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1443322767
Short name T347
Test name
Test status
Simulation time 653381806 ps
CPU time 1.47 seconds
Started Jun 11 01:48:08 PM PDT 24
Finished Jun 11 01:48:11 PM PDT 24
Peak memory 198268 kb
Host smart-fcf93e8f-3bd7-4167-becb-d584fd2aceaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443322767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1443322767
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1017963556
Short name T190
Test name
Test status
Simulation time 8184050052 ps
CPU time 7.31 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:21 PM PDT 24
Peak memory 197692 kb
Host smart-07bad87a-b743-44bc-a77c-e3d14081b9fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017963556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1017963556
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1062265854
Short name T313
Test name
Test status
Simulation time 417146574 ps
CPU time 1.21 seconds
Started Jun 11 01:48:07 PM PDT 24
Finished Jun 11 01:48:10 PM PDT 24
Peak memory 195472 kb
Host smart-e4ad467f-a8ab-4d44-9b4a-d722ab959e4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062265854 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1062265854
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.521477381
Short name T76
Test name
Test status
Simulation time 364648786 ps
CPU time 0.62 seconds
Started Jun 11 01:48:07 PM PDT 24
Finished Jun 11 01:48:09 PM PDT 24
Peak memory 192924 kb
Host smart-76439618-07c5-475e-8dc0-8f84fd0af0da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521477381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.521477381
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3429854269
Short name T314
Test name
Test status
Simulation time 302480280 ps
CPU time 0.77 seconds
Started Jun 11 01:48:06 PM PDT 24
Finished Jun 11 01:48:08 PM PDT 24
Peak memory 183624 kb
Host smart-c4415db8-25ed-4f88-a54a-6a3d0493b664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429854269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3429854269
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.218099056
Short name T373
Test name
Test status
Simulation time 2126216792 ps
CPU time 1.15 seconds
Started Jun 11 01:48:06 PM PDT 24
Finished Jun 11 01:48:09 PM PDT 24
Peak memory 194912 kb
Host smart-dc9997f9-21d2-4d22-9f98-352084417500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218099056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.218099056
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3736611777
Short name T371
Test name
Test status
Simulation time 475290698 ps
CPU time 1.91 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:16 PM PDT 24
Peak memory 198128 kb
Host smart-213f27d5-7114-4537-9891-10f08e3b5880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736611777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3736611777
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.503154010
Short name T366
Test name
Test status
Simulation time 423753734 ps
CPU time 1.49 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:06 PM PDT 24
Peak memory 196736 kb
Host smart-534f996c-2b4f-46fc-ac0a-683a3bbce00d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503154010 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.503154010
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1775346555
Short name T57
Test name
Test status
Simulation time 372136178 ps
CPU time 1.16 seconds
Started Jun 11 01:48:02 PM PDT 24
Finished Jun 11 01:48:05 PM PDT 24
Peak memory 192860 kb
Host smart-cc21f154-d63e-44d3-b052-df1f274e4c18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775346555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1775346555
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.925785454
Short name T335
Test name
Test status
Simulation time 361798415 ps
CPU time 0.65 seconds
Started Jun 11 01:48:01 PM PDT 24
Finished Jun 11 01:48:04 PM PDT 24
Peak memory 183612 kb
Host smart-54563c63-cda2-418a-8651-633859a15b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925785454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.925785454
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.24081129
Short name T376
Test name
Test status
Simulation time 1399174450 ps
CPU time 0.89 seconds
Started Jun 11 01:48:00 PM PDT 24
Finished Jun 11 01:48:03 PM PDT 24
Peak memory 183644 kb
Host smart-dedb1210-1597-43fa-b26d-473010244ac5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24081129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_
timer_same_csr_outstanding.24081129
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1345170410
Short name T284
Test name
Test status
Simulation time 558632901 ps
CPU time 2.24 seconds
Started Jun 11 01:48:01 PM PDT 24
Finished Jun 11 01:48:05 PM PDT 24
Peak memory 198416 kb
Host smart-6f219cb7-b4db-46c1-9ab5-97b8daa81eba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345170410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1345170410
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2478412346
Short name T408
Test name
Test status
Simulation time 8229698743 ps
CPU time 7.14 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:13 PM PDT 24
Peak memory 198044 kb
Host smart-81dd6f82-3dce-4342-acc8-4fc7faac9a26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478412346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2478412346
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3477789347
Short name T64
Test name
Test status
Simulation time 691542577 ps
CPU time 1.03 seconds
Started Jun 11 01:48:00 PM PDT 24
Finished Jun 11 01:48:03 PM PDT 24
Peak memory 194400 kb
Host smart-d27b9c67-465b-4019-99b8-80d2e21ddd7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477789347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3477789347
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3619756222
Short name T65
Test name
Test status
Simulation time 1140456003 ps
CPU time 1.81 seconds
Started Jun 11 01:47:47 PM PDT 24
Finished Jun 11 01:47:50 PM PDT 24
Peak memory 196072 kb
Host smart-1c01e55f-8f26-4335-a8b7-9625fb31f921
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619756222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3619756222
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2732940257
Short name T69
Test name
Test status
Simulation time 1176002529 ps
CPU time 1.55 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:02 PM PDT 24
Peak memory 193088 kb
Host smart-f2e6b6dd-6cd3-4764-bba3-5f417a7c2362
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732940257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2732940257
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1837617179
Short name T339
Test name
Test status
Simulation time 560945711 ps
CPU time 1.33 seconds
Started Jun 11 01:47:53 PM PDT 24
Finished Jun 11 01:47:55 PM PDT 24
Peak memory 195696 kb
Host smart-8e61f56a-4598-4349-8c35-76497e48211a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837617179 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1837617179
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2093908815
Short name T375
Test name
Test status
Simulation time 496154405 ps
CPU time 0.96 seconds
Started Jun 11 01:47:51 PM PDT 24
Finished Jun 11 01:47:53 PM PDT 24
Peak memory 193052 kb
Host smart-226c9754-48cd-4a34-b24a-2206ee355eec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093908815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2093908815
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1214711603
Short name T283
Test name
Test status
Simulation time 495967425 ps
CPU time 0.88 seconds
Started Jun 11 01:47:51 PM PDT 24
Finished Jun 11 01:47:53 PM PDT 24
Peak memory 183580 kb
Host smart-2e4c0678-0af7-4c90-97b4-b4c9bd1abf91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214711603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1214711603
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.5323965
Short name T336
Test name
Test status
Simulation time 441517036 ps
CPU time 1.19 seconds
Started Jun 11 01:47:46 PM PDT 24
Finished Jun 11 01:47:48 PM PDT 24
Peak memory 183516 kb
Host smart-795874ed-caae-49b8-a777-3c189b071aec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5323965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_t
imer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_time
r_mem_partial_access.5323965
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3850336113
Short name T308
Test name
Test status
Simulation time 383476948 ps
CPU time 1.04 seconds
Started Jun 11 01:47:47 PM PDT 24
Finished Jun 11 01:47:49 PM PDT 24
Peak memory 183616 kb
Host smart-89329060-808f-49fb-a3a5-2b18dc001f53
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850336113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3850336113
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.435868903
Short name T357
Test name
Test status
Simulation time 1425838815 ps
CPU time 1.54 seconds
Started Jun 11 01:47:50 PM PDT 24
Finished Jun 11 01:47:53 PM PDT 24
Peak memory 193908 kb
Host smart-87ad9236-93da-42d7-a352-0159d1c8b738
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435868903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.435868903
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4245881947
Short name T321
Test name
Test status
Simulation time 355624209 ps
CPU time 1.35 seconds
Started Jun 11 01:47:52 PM PDT 24
Finished Jun 11 01:47:54 PM PDT 24
Peak memory 198276 kb
Host smart-0750a052-45bf-4573-bbdc-264e3ccc6ae2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245881947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.4245881947
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2169246439
Short name T370
Test name
Test status
Simulation time 8395918305 ps
CPU time 13.69 seconds
Started Jun 11 01:47:47 PM PDT 24
Finished Jun 11 01:48:02 PM PDT 24
Peak memory 198128 kb
Host smart-4535a82f-31ca-4e4d-9062-0683a7bf2b93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169246439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2169246439
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.4125442480
Short name T318
Test name
Test status
Simulation time 339210435 ps
CPU time 0.8 seconds
Started Jun 11 01:48:00 PM PDT 24
Finished Jun 11 01:48:02 PM PDT 24
Peak memory 183608 kb
Host smart-eacdd677-b27b-4329-b758-b1536572d30c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125442480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.4125442480
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1739492150
Short name T399
Test name
Test status
Simulation time 440663739 ps
CPU time 0.75 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:06 PM PDT 24
Peak memory 183796 kb
Host smart-53bd1c55-34db-42d8-94ca-ebd23e9db37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739492150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1739492150
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.646929361
Short name T299
Test name
Test status
Simulation time 380682633 ps
CPU time 0.67 seconds
Started Jun 11 01:48:02 PM PDT 24
Finished Jun 11 01:48:04 PM PDT 24
Peak memory 183804 kb
Host smart-9f1fc855-e74c-4f74-829d-189134b836f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646929361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.646929361
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3138375209
Short name T386
Test name
Test status
Simulation time 319771904 ps
CPU time 0.77 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:01 PM PDT 24
Peak memory 192848 kb
Host smart-d1393b73-ed82-4e74-afe0-cc48fa8daa45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138375209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3138375209
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1642862026
Short name T324
Test name
Test status
Simulation time 382017011 ps
CPU time 0.72 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:06 PM PDT 24
Peak memory 193012 kb
Host smart-34409522-87de-4f8b-9a49-ce5448e0f451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642862026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1642862026
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1899211861
Short name T296
Test name
Test status
Simulation time 326678164 ps
CPU time 0.63 seconds
Started Jun 11 01:48:04 PM PDT 24
Finished Jun 11 01:48:07 PM PDT 24
Peak memory 183568 kb
Host smart-2a27a7b7-9102-42be-9aba-697a88b976f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899211861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1899211861
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2500745915
Short name T307
Test name
Test status
Simulation time 455554194 ps
CPU time 0.7 seconds
Started Jun 11 01:48:02 PM PDT 24
Finished Jun 11 01:48:05 PM PDT 24
Peak memory 192792 kb
Host smart-1f2f3636-2860-4c8b-ba20-5792d032839e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500745915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2500745915
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3677134777
Short name T383
Test name
Test status
Simulation time 505724670 ps
CPU time 1.23 seconds
Started Jun 11 01:48:12 PM PDT 24
Finished Jun 11 01:48:17 PM PDT 24
Peak memory 192820 kb
Host smart-0940ee04-054c-4ab3-b1a1-b9046e61ed42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677134777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3677134777
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.390889726
Short name T312
Test name
Test status
Simulation time 454017814 ps
CPU time 0.9 seconds
Started Jun 11 01:48:09 PM PDT 24
Finished Jun 11 01:48:12 PM PDT 24
Peak memory 183520 kb
Host smart-5fa17086-1f44-4053-bc35-358e5899fa32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390889726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.390889726
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2929213170
Short name T289
Test name
Test status
Simulation time 348775094 ps
CPU time 1.05 seconds
Started Jun 11 01:48:08 PM PDT 24
Finished Jun 11 01:48:11 PM PDT 24
Peak memory 183624 kb
Host smart-7ee9ee5b-8345-4219-80eb-e39fd9720a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929213170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2929213170
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2649547650
Short name T192
Test name
Test status
Simulation time 798796330 ps
CPU time 0.89 seconds
Started Jun 11 01:47:54 PM PDT 24
Finished Jun 11 01:47:56 PM PDT 24
Peak memory 194440 kb
Host smart-2a1f93ae-c9b5-4d63-a4f4-a5802994738c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649547650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2649547650
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2983074545
Short name T365
Test name
Test status
Simulation time 14166400854 ps
CPU time 23.87 seconds
Started Jun 11 01:47:48 PM PDT 24
Finished Jun 11 01:48:13 PM PDT 24
Peak memory 192096 kb
Host smart-55a94b44-461a-4ab0-9a05-08aaac76a968
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983074545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2983074545
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2377484039
Short name T330
Test name
Test status
Simulation time 890823608 ps
CPU time 1.83 seconds
Started Jun 11 01:47:56 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 183696 kb
Host smart-1f170aaf-3754-4265-b231-6e923f3f45b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377484039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2377484039
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1032424086
Short name T32
Test name
Test status
Simulation time 529197226 ps
CPU time 0.95 seconds
Started Jun 11 01:47:54 PM PDT 24
Finished Jun 11 01:47:56 PM PDT 24
Peak memory 197680 kb
Host smart-b1ecba16-8395-485b-ae49-9b8a5c609ea9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032424086 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1032424086
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.267879122
Short name T407
Test name
Test status
Simulation time 361902677 ps
CPU time 1.19 seconds
Started Jun 11 01:47:55 PM PDT 24
Finished Jun 11 01:47:57 PM PDT 24
Peak memory 193052 kb
Host smart-d5e254a2-c31b-4500-b5b0-2315243080a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267879122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.267879122
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.398752040
Short name T381
Test name
Test status
Simulation time 291382558 ps
CPU time 0.85 seconds
Started Jun 11 01:47:55 PM PDT 24
Finished Jun 11 01:47:57 PM PDT 24
Peak memory 183520 kb
Host smart-72928ec1-2481-4567-aa9d-da138789f373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398752040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.398752040
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1974039777
Short name T397
Test name
Test status
Simulation time 293792711 ps
CPU time 0.91 seconds
Started Jun 11 01:47:51 PM PDT 24
Finished Jun 11 01:47:53 PM PDT 24
Peak memory 183540 kb
Host smart-1c8052eb-c83a-4dd1-80f7-2828d162c05b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974039777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1974039777
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2547355736
Short name T342
Test name
Test status
Simulation time 471580612 ps
CPU time 0.68 seconds
Started Jun 11 01:47:45 PM PDT 24
Finished Jun 11 01:47:48 PM PDT 24
Peak memory 183604 kb
Host smart-7e7c8c25-845a-4443-bd0a-e935ba5e5bd8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547355736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2547355736
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1260540116
Short name T418
Test name
Test status
Simulation time 2350654278 ps
CPU time 3.17 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:03 PM PDT 24
Peak memory 194820 kb
Host smart-b0fe3d51-f569-4c90-8f23-090a3a8776b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260540116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1260540116
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.909809488
Short name T290
Test name
Test status
Simulation time 371175004 ps
CPU time 2.56 seconds
Started Jun 11 01:47:48 PM PDT 24
Finished Jun 11 01:47:51 PM PDT 24
Peak memory 198408 kb
Host smart-1ee71d65-db5d-4349-bcd5-d6cce20aca65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909809488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.909809488
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3459171870
Short name T398
Test name
Test status
Simulation time 8958667630 ps
CPU time 11.31 seconds
Started Jun 11 01:47:51 PM PDT 24
Finished Jun 11 01:48:03 PM PDT 24
Peak memory 197884 kb
Host smart-044874cc-51f4-44ed-85de-836837491d89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459171870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3459171870
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.21071607
Short name T379
Test name
Test status
Simulation time 331072028 ps
CPU time 0.76 seconds
Started Jun 11 01:48:13 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 183352 kb
Host smart-89d14b5d-485e-45e7-bc6d-98c6dc81ce39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21071607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.21071607
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1350428225
Short name T332
Test name
Test status
Simulation time 447052493 ps
CPU time 0.7 seconds
Started Jun 11 01:48:12 PM PDT 24
Finished Jun 11 01:48:16 PM PDT 24
Peak memory 192844 kb
Host smart-5b095685-3f00-4da1-a4ef-3fa6ed76ed98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350428225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1350428225
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4192813342
Short name T303
Test name
Test status
Simulation time 336491797 ps
CPU time 0.69 seconds
Started Jun 11 01:48:10 PM PDT 24
Finished Jun 11 01:48:14 PM PDT 24
Peak memory 192852 kb
Host smart-ecda07d2-2d61-42e1-b0a8-a09266981720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192813342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.4192813342
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3729058455
Short name T304
Test name
Test status
Simulation time 371629864 ps
CPU time 0.58 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:14 PM PDT 24
Peak memory 183608 kb
Host smart-c2bed321-771e-4fe2-9e54-27027726f8f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729058455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3729058455
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.848318160
Short name T288
Test name
Test status
Simulation time 520380211 ps
CPU time 0.73 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:16 PM PDT 24
Peak memory 183600 kb
Host smart-5c856590-7c75-48a5-b762-1830cf871133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848318160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.848318160
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2657292655
Short name T364
Test name
Test status
Simulation time 487520959 ps
CPU time 0.71 seconds
Started Jun 11 01:48:13 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 183792 kb
Host smart-cbd60084-8f88-44d5-8a8a-36a71f677d47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657292655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2657292655
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1115026152
Short name T396
Test name
Test status
Simulation time 543582886 ps
CPU time 0.63 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:15 PM PDT 24
Peak memory 192796 kb
Host smart-ba0369fb-4d5c-458c-b034-b5e07b3ce055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115026152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1115026152
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3980598034
Short name T282
Test name
Test status
Simulation time 486071854 ps
CPU time 0.91 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:16 PM PDT 24
Peak memory 183600 kb
Host smart-76c88bb6-0365-4be6-a24a-2e20c7796b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980598034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3980598034
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1229830023
Short name T359
Test name
Test status
Simulation time 382812417 ps
CPU time 0.67 seconds
Started Jun 11 01:48:12 PM PDT 24
Finished Jun 11 01:48:16 PM PDT 24
Peak memory 183624 kb
Host smart-afc904d3-87a3-47ab-b84c-c8eb07c93220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229830023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1229830023
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.361413211
Short name T287
Test name
Test status
Simulation time 507821446 ps
CPU time 0.61 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:15 PM PDT 24
Peak memory 183580 kb
Host smart-ac4da9da-5885-44be-b7dc-2ba700b51f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361413211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.361413211
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4062669313
Short name T66
Test name
Test status
Simulation time 582584070 ps
CPU time 1.28 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:01 PM PDT 24
Peak memory 194580 kb
Host smart-3958f16c-3dbc-421e-ac05-159811385fc6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062669313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.4062669313
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1467859070
Short name T409
Test name
Test status
Simulation time 7257566031 ps
CPU time 7.02 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:07 PM PDT 24
Peak memory 195520 kb
Host smart-cc8b08d0-a94c-487a-87ca-66d12cb1d87b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467859070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1467859070
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3290622583
Short name T71
Test name
Test status
Simulation time 729441502 ps
CPU time 0.85 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:01 PM PDT 24
Peak memory 183620 kb
Host smart-f23255b9-9357-4e32-8c79-6091ac2feb1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290622583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3290622583
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3312209826
Short name T295
Test name
Test status
Simulation time 610679655 ps
CPU time 1.24 seconds
Started Jun 11 01:47:54 PM PDT 24
Finished Jun 11 01:47:56 PM PDT 24
Peak memory 198428 kb
Host smart-5fe77966-22f6-4383-8b3f-8159cdb782cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312209826 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3312209826
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4178851321
Short name T60
Test name
Test status
Simulation time 476849232 ps
CPU time 0.59 seconds
Started Jun 11 01:47:53 PM PDT 24
Finished Jun 11 01:47:55 PM PDT 24
Peak memory 192864 kb
Host smart-72d12f90-4796-4ea4-b25d-7eb6f34c4e75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178851321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.4178851321
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3387270308
Short name T298
Test name
Test status
Simulation time 470448808 ps
CPU time 0.76 seconds
Started Jun 11 01:47:55 PM PDT 24
Finished Jun 11 01:47:57 PM PDT 24
Peak memory 192836 kb
Host smart-17180236-0c51-4af8-a053-14d34d78799d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387270308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3387270308
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2017153481
Short name T325
Test name
Test status
Simulation time 519354663 ps
CPU time 1.3 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 183476 kb
Host smart-cb5fb47a-501b-4989-a37b-9334a4865658
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017153481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2017153481
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1632168778
Short name T280
Test name
Test status
Simulation time 436760948 ps
CPU time 0.66 seconds
Started Jun 11 01:47:54 PM PDT 24
Finished Jun 11 01:47:55 PM PDT 24
Peak memory 183596 kb
Host smart-e138258e-7aec-4f8f-8977-aa1e974c5778
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632168778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1632168778
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1392624585
Short name T406
Test name
Test status
Simulation time 1840457196 ps
CPU time 3.61 seconds
Started Jun 11 01:47:55 PM PDT 24
Finished Jun 11 01:47:59 PM PDT 24
Peak memory 194684 kb
Host smart-8a31b06a-ce62-4b1d-89df-b23db25eb39d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392624585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1392624585
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3099857436
Short name T361
Test name
Test status
Simulation time 381535291 ps
CPU time 1.74 seconds
Started Jun 11 01:47:47 PM PDT 24
Finished Jun 11 01:47:49 PM PDT 24
Peak memory 198308 kb
Host smart-516200a2-23ac-45b4-bb94-e80c740df19a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099857436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3099857436
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.663486118
Short name T188
Test name
Test status
Simulation time 8603812116 ps
CPU time 2.46 seconds
Started Jun 11 01:47:56 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 198072 kb
Host smart-f7252dd8-b0e7-42a2-a66d-dbdc723d29b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663486118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.663486118
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1350743050
Short name T394
Test name
Test status
Simulation time 381267574 ps
CPU time 0.8 seconds
Started Jun 11 01:48:12 PM PDT 24
Finished Jun 11 01:48:16 PM PDT 24
Peak memory 183604 kb
Host smart-4baf5caa-49b2-4d70-81f7-1313334f04d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350743050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1350743050
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1066244033
Short name T286
Test name
Test status
Simulation time 484891236 ps
CPU time 0.83 seconds
Started Jun 11 01:48:10 PM PDT 24
Finished Jun 11 01:48:15 PM PDT 24
Peak memory 192820 kb
Host smart-bc49b4d4-1763-45f3-8a83-0fd6cebefd94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066244033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1066244033
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1599387657
Short name T346
Test name
Test status
Simulation time 401974319 ps
CPU time 0.83 seconds
Started Jun 11 01:48:13 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 183276 kb
Host smart-195b4773-f32e-439c-9cb1-812c52b5b485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599387657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1599387657
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3100842000
Short name T344
Test name
Test status
Simulation time 394759407 ps
CPU time 0.65 seconds
Started Jun 11 01:48:09 PM PDT 24
Finished Jun 11 01:48:12 PM PDT 24
Peak memory 183576 kb
Host smart-d4c15d67-c38b-4da3-8ab6-afc26414b4c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100842000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3100842000
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1994984512
Short name T400
Test name
Test status
Simulation time 398037389 ps
CPU time 1.06 seconds
Started Jun 11 01:48:07 PM PDT 24
Finished Jun 11 01:48:10 PM PDT 24
Peak memory 183572 kb
Host smart-a6ad7ecb-45b2-4478-9c47-a2bd4eb912bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994984512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1994984512
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.110350971
Short name T369
Test name
Test status
Simulation time 393251296 ps
CPU time 1.11 seconds
Started Jun 11 01:48:10 PM PDT 24
Finished Jun 11 01:48:14 PM PDT 24
Peak memory 183588 kb
Host smart-1d4de9bf-8d7e-46c0-969c-703af2b10fe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110350971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.110350971
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.899253089
Short name T368
Test name
Test status
Simulation time 422371550 ps
CPU time 1.12 seconds
Started Jun 11 01:48:10 PM PDT 24
Finished Jun 11 01:48:14 PM PDT 24
Peak memory 183592 kb
Host smart-6370189e-d66e-46a1-84a1-731aa310cce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899253089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.899253089
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3109311637
Short name T340
Test name
Test status
Simulation time 272486913 ps
CPU time 0.97 seconds
Started Jun 11 01:48:13 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 192812 kb
Host smart-3565f8b0-8f9c-47b2-a11c-d3247f796148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109311637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3109311637
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.695264396
Short name T356
Test name
Test status
Simulation time 387560159 ps
CPU time 1.12 seconds
Started Jun 11 01:48:10 PM PDT 24
Finished Jun 11 01:48:15 PM PDT 24
Peak memory 183568 kb
Host smart-ba3f601f-3238-44fb-a835-66d36579ddaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695264396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.695264396
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2006056981
Short name T351
Test name
Test status
Simulation time 527619605 ps
CPU time 0.72 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:16 PM PDT 24
Peak memory 192788 kb
Host smart-fb0c2635-0641-408e-b8cc-f7fa9d1291c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006056981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2006056981
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2340859839
Short name T310
Test name
Test status
Simulation time 508514719 ps
CPU time 1.06 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:01 PM PDT 24
Peak memory 196244 kb
Host smart-9dc275e2-1054-4489-b2d0-26ad76714346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340859839 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2340859839
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1123139281
Short name T58
Test name
Test status
Simulation time 444814792 ps
CPU time 0.89 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:01 PM PDT 24
Peak memory 193144 kb
Host smart-f2601575-3a0f-4f37-b97b-109d7d26a071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123139281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1123139281
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3226465067
Short name T328
Test name
Test status
Simulation time 358681344 ps
CPU time 0.85 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:47:59 PM PDT 24
Peak memory 183548 kb
Host smart-bea72875-381c-43c2-8d6d-c10afac8fbbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226465067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3226465067
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1489578342
Short name T410
Test name
Test status
Simulation time 2258390980 ps
CPU time 2 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:02 PM PDT 24
Peak memory 194820 kb
Host smart-54444f6e-e3e3-4ef1-b3dc-c57d88e96563
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489578342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1489578342
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3573132482
Short name T345
Test name
Test status
Simulation time 509125857 ps
CPU time 2.23 seconds
Started Jun 11 01:47:55 PM PDT 24
Finished Jun 11 01:47:58 PM PDT 24
Peak memory 198392 kb
Host smart-e6f76966-818c-4253-9c7f-2b470bad9a2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573132482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3573132482
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1404759704
Short name T35
Test name
Test status
Simulation time 7762279020 ps
CPU time 4.07 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:48:03 PM PDT 24
Peak memory 198036 kb
Host smart-903153fe-9a20-4b27-8c4b-7b4a104fa27c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404759704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1404759704
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.816110461
Short name T337
Test name
Test status
Simulation time 580991121 ps
CPU time 1.41 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 196364 kb
Host smart-2f2f1b0e-a229-460c-98b5-fb9f160b5482
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816110461 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.816110461
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3066244758
Short name T302
Test name
Test status
Simulation time 344363629 ps
CPU time 0.89 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 193892 kb
Host smart-71fae317-f5bc-4970-ac54-44a7af47822f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066244758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3066244758
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1212210161
Short name T388
Test name
Test status
Simulation time 334538969 ps
CPU time 0.59 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 183604 kb
Host smart-8605986c-47d7-409a-940e-5fedde741f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212210161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1212210161
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.694391908
Short name T411
Test name
Test status
Simulation time 1159193974 ps
CPU time 2.31 seconds
Started Jun 11 01:48:05 PM PDT 24
Finished Jun 11 01:48:09 PM PDT 24
Peak memory 193248 kb
Host smart-90c58f1b-5b54-4f9d-8369-ef90c5699bba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694391908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.694391908
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1946037406
Short name T309
Test name
Test status
Simulation time 754488909 ps
CPU time 1.7 seconds
Started Jun 11 01:47:59 PM PDT 24
Finished Jun 11 01:48:03 PM PDT 24
Peak memory 198440 kb
Host smart-6be04ea7-deee-4310-af2a-be3528d3bc7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946037406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1946037406
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.286790219
Short name T187
Test name
Test status
Simulation time 8408986462 ps
CPU time 13.1 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:48:12 PM PDT 24
Peak memory 197988 kb
Host smart-10fce109-9f93-4f70-a059-734be9a094f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286790219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.286790219
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1049062765
Short name T363
Test name
Test status
Simulation time 563317919 ps
CPU time 1.15 seconds
Started Jun 11 01:47:59 PM PDT 24
Finished Jun 11 01:48:02 PM PDT 24
Peak memory 197984 kb
Host smart-f42d8ff9-18b3-42ad-9f8e-2bd619f66617
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049062765 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1049062765
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.709375542
Short name T59
Test name
Test status
Simulation time 477958112 ps
CPU time 0.82 seconds
Started Jun 11 01:48:01 PM PDT 24
Finished Jun 11 01:48:04 PM PDT 24
Peak memory 193016 kb
Host smart-41ebf041-5e90-4a02-a980-5ee493188d73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709375542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.709375542
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.410842966
Short name T331
Test name
Test status
Simulation time 303592886 ps
CPU time 0.73 seconds
Started Jun 11 01:48:02 PM PDT 24
Finished Jun 11 01:48:04 PM PDT 24
Peak memory 183632 kb
Host smart-5d0214ad-1e97-4a75-a236-2ecb42b28377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410842966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.410842966
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2750796960
Short name T349
Test name
Test status
Simulation time 1768393215 ps
CPU time 0.92 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 193148 kb
Host smart-15ce35f8-a57d-49ae-bf02-ab5178a4bb7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750796960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2750796960
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3317678087
Short name T404
Test name
Test status
Simulation time 424758525 ps
CPU time 1.28 seconds
Started Jun 11 01:47:56 PM PDT 24
Finished Jun 11 01:47:59 PM PDT 24
Peak memory 198304 kb
Host smart-b54f39c7-353a-4035-8c8f-b9c51be593e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317678087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3317678087
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3773076223
Short name T353
Test name
Test status
Simulation time 8251031747 ps
CPU time 3.88 seconds
Started Jun 11 01:48:01 PM PDT 24
Finished Jun 11 01:48:06 PM PDT 24
Peak memory 197900 kb
Host smart-971df51a-71e7-4ffd-8365-83a3fb755485
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773076223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3773076223
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3727242223
Short name T401
Test name
Test status
Simulation time 360119125 ps
CPU time 1.11 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 195588 kb
Host smart-6359e6c4-e8ef-41be-8bb4-88d573d30b0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727242223 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3727242223
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2824956447
Short name T393
Test name
Test status
Simulation time 457167070 ps
CPU time 1.26 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:01 PM PDT 24
Peak memory 192892 kb
Host smart-25d1a92f-6383-46b9-94af-4ee54d580cbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824956447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2824956447
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.925911803
Short name T316
Test name
Test status
Simulation time 449656636 ps
CPU time 0.94 seconds
Started Jun 11 01:48:01 PM PDT 24
Finished Jun 11 01:48:04 PM PDT 24
Peak memory 183628 kb
Host smart-20676f4f-8ba9-4ced-a33d-bef674686278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925911803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.925911803
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4102579074
Short name T77
Test name
Test status
Simulation time 1682895486 ps
CPU time 4.01 seconds
Started Jun 11 01:47:59 PM PDT 24
Finished Jun 11 01:48:05 PM PDT 24
Peak memory 193732 kb
Host smart-8eef966b-e866-4f6b-89e4-794cd29d67bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102579074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4102579074
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4188208773
Short name T293
Test name
Test status
Simulation time 442594322 ps
CPU time 2.9 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:08 PM PDT 24
Peak memory 198404 kb
Host smart-1a3690a9-7021-47dc-bdd0-7519dae0f47d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188208773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4188208773
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1244082878
Short name T338
Test name
Test status
Simulation time 4233388224 ps
CPU time 7.89 seconds
Started Jun 11 01:48:01 PM PDT 24
Finished Jun 11 01:48:10 PM PDT 24
Peak memory 197772 kb
Host smart-5e7273fe-c989-46b1-9c7c-f4ff499419ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244082878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1244082878
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4135003363
Short name T319
Test name
Test status
Simulation time 489616661 ps
CPU time 1.34 seconds
Started Jun 11 01:48:09 PM PDT 24
Finished Jun 11 01:48:12 PM PDT 24
Peak memory 195912 kb
Host smart-ebd656fd-9ea9-4156-9d2e-435e1d31d98a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135003363 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.4135003363
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.564661544
Short name T390
Test name
Test status
Simulation time 363591520 ps
CPU time 1.06 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:48:00 PM PDT 24
Peak memory 191952 kb
Host smart-3d5d697e-7e5f-4c17-b88c-86ca76f65c9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564661544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.564661544
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3749453325
Short name T385
Test name
Test status
Simulation time 347712496 ps
CPU time 0.97 seconds
Started Jun 11 01:48:02 PM PDT 24
Finished Jun 11 01:48:05 PM PDT 24
Peak memory 183632 kb
Host smart-61e3e54a-3111-45e5-b853-7b5d6364bdd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749453325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3749453325
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1952731808
Short name T78
Test name
Test status
Simulation time 1986828783 ps
CPU time 2.08 seconds
Started Jun 11 01:48:03 PM PDT 24
Finished Jun 11 01:48:07 PM PDT 24
Peak memory 194268 kb
Host smart-ddb36919-9f50-4feb-a0e4-845ca1bf8139
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952731808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1952731808
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.545371070
Short name T360
Test name
Test status
Simulation time 385502520 ps
CPU time 1.86 seconds
Started Jun 11 01:47:58 PM PDT 24
Finished Jun 11 01:48:01 PM PDT 24
Peak memory 198324 kb
Host smart-68aba991-a475-4ff1-855c-91c27a063571
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545371070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.545371070
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2305405446
Short name T413
Test name
Test status
Simulation time 4118772839 ps
CPU time 4.71 seconds
Started Jun 11 01:47:57 PM PDT 24
Finished Jun 11 01:48:03 PM PDT 24
Peak memory 197712 kb
Host smart-3dd233bb-829d-4564-a2b4-56256e3049a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305405446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2305405446
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1129622894
Short name T212
Test name
Test status
Simulation time 60274351239 ps
CPU time 92.65 seconds
Started Jun 11 01:42:47 PM PDT 24
Finished Jun 11 01:44:22 PM PDT 24
Peak memory 191892 kb
Host smart-d7c870bf-5456-42b1-afcc-d179d3cb6d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129622894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1129622894
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3185048251
Short name T238
Test name
Test status
Simulation time 359375519 ps
CPU time 0.79 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:42:57 PM PDT 24
Peak memory 191708 kb
Host smart-cfca6e17-c5c2-440d-9a71-6e1b669d4aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185048251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3185048251
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.6336160
Short name T249
Test name
Test status
Simulation time 10074979349 ps
CPU time 1.41 seconds
Started Jun 11 01:42:34 PM PDT 24
Finished Jun 11 01:42:36 PM PDT 24
Peak memory 191904 kb
Host smart-8f68bd48-044f-49f9-a873-943929d593f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6336160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.6336160
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2767145023
Short name T16
Test name
Test status
Simulation time 8712282666 ps
CPU time 4.24 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:42:59 PM PDT 24
Peak memory 215988 kb
Host smart-fa695ab7-c4f2-48bf-bb48-0a1802ea64d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767145023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2767145023
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.361870821
Short name T1
Test name
Test status
Simulation time 513173899 ps
CPU time 1.5 seconds
Started Jun 11 01:42:41 PM PDT 24
Finished Jun 11 01:42:43 PM PDT 24
Peak memory 196564 kb
Host smart-1e622908-9cbc-4b85-8452-2d0dc4442f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361870821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.361870821
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2206660401
Short name T51
Test name
Test status
Simulation time 4152926967 ps
CPU time 2.2 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:43:00 PM PDT 24
Peak memory 191916 kb
Host smart-ff8ec710-43df-42df-a9eb-aad96bd93b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206660401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2206660401
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1166828581
Short name T278
Test name
Test status
Simulation time 459160037 ps
CPU time 1.27 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:42:55 PM PDT 24
Peak memory 196612 kb
Host smart-7bfca81b-50b2-4667-aca0-b02a414c7e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166828581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1166828581
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.747232768
Short name T262
Test name
Test status
Simulation time 40001465385 ps
CPU time 28.6 seconds
Started Jun 11 01:42:48 PM PDT 24
Finished Jun 11 01:43:19 PM PDT 24
Peak memory 191916 kb
Host smart-5e439769-562d-48ef-a4e9-bdd3604a9c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747232768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.747232768
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.4017901396
Short name T258
Test name
Test status
Simulation time 537562225 ps
CPU time 0.79 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:42:59 PM PDT 24
Peak memory 191748 kb
Host smart-b21f2297-a650-454f-8c19-3a2669ee46db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017901396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.4017901396
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.255064606
Short name T13
Test name
Test status
Simulation time 24974716679 ps
CPU time 39.87 seconds
Started Jun 11 01:42:44 PM PDT 24
Finished Jun 11 01:43:25 PM PDT 24
Peak memory 191888 kb
Host smart-37a020a2-c8ec-4f48-b599-d3eed95a7dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255064606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.255064606
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2705709525
Short name T246
Test name
Test status
Simulation time 395435952 ps
CPU time 1.2 seconds
Started Jun 11 01:42:56 PM PDT 24
Finished Jun 11 01:43:03 PM PDT 24
Peak memory 196480 kb
Host smart-00b72bf1-2392-4137-a849-c36a16b32638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705709525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2705709525
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.787425505
Short name T215
Test name
Test status
Simulation time 36090624735 ps
CPU time 29.37 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:43:26 PM PDT 24
Peak memory 191940 kb
Host smart-40f8af4c-9214-4444-aad2-3e6462d9492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787425505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.787425505
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.706176628
Short name T195
Test name
Test status
Simulation time 414265902 ps
CPU time 1.25 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:43:00 PM PDT 24
Peak memory 191796 kb
Host smart-ac3c7e23-f4b5-49c7-8e05-9a8c6528301b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706176628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.706176628
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1739758292
Short name T221
Test name
Test status
Simulation time 13490876620 ps
CPU time 23.83 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:43:16 PM PDT 24
Peak memory 191916 kb
Host smart-7831eae8-68b2-498b-ba22-ce204d479da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739758292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1739758292
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.313991790
Short name T224
Test name
Test status
Simulation time 436438634 ps
CPU time 0.93 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:42:53 PM PDT 24
Peak memory 191984 kb
Host smart-b2f08cfb-89d3-4eba-ac9a-8be82129eb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313991790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.313991790
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.170750851
Short name T209
Test name
Test status
Simulation time 12110600128 ps
CPU time 18.73 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:43:20 PM PDT 24
Peak memory 191908 kb
Host smart-7026165a-ce7a-421f-ab6d-83f80a660714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170750851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.170750851
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3753304638
Short name T223
Test name
Test status
Simulation time 539867659 ps
CPU time 1.02 seconds
Started Jun 11 01:42:48 PM PDT 24
Finished Jun 11 01:42:52 PM PDT 24
Peak memory 191760 kb
Host smart-a9a63dbb-7ef0-46e1-883f-caed340b990c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753304638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3753304638
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.742892791
Short name T199
Test name
Test status
Simulation time 41285895543 ps
CPU time 17.4 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:43:09 PM PDT 24
Peak memory 191916 kb
Host smart-f9e33d74-c156-4448-81a1-6053788d24a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742892791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.742892791
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3213075366
Short name T275
Test name
Test status
Simulation time 597376691 ps
CPU time 0.82 seconds
Started Jun 11 01:42:48 PM PDT 24
Finished Jun 11 01:42:51 PM PDT 24
Peak memory 191776 kb
Host smart-24eca2d0-eafb-4f8e-9866-d75d82a4d67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213075366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3213075366
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3887195644
Short name T252
Test name
Test status
Simulation time 39733454703 ps
CPU time 14.59 seconds
Started Jun 11 01:42:44 PM PDT 24
Finished Jun 11 01:42:59 PM PDT 24
Peak memory 191888 kb
Host smart-27bd1287-73ef-4e0c-b17f-83e32a5e1e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887195644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3887195644
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3354877185
Short name T222
Test name
Test status
Simulation time 537645533 ps
CPU time 0.72 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:42:54 PM PDT 24
Peak memory 191968 kb
Host smart-89fdc162-51e6-44fe-87d8-4f293bcb451e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354877185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3354877185
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1651354398
Short name T227
Test name
Test status
Simulation time 2794947635 ps
CPU time 1.73 seconds
Started Jun 11 01:42:48 PM PDT 24
Finished Jun 11 01:42:52 PM PDT 24
Peak memory 191924 kb
Host smart-3a19086e-76de-42a2-b64b-a147c0ad8565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651354398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1651354398
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1511223699
Short name T276
Test name
Test status
Simulation time 577251442 ps
CPU time 1.03 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:43:00 PM PDT 24
Peak memory 191764 kb
Host smart-12d7e65c-a9e1-42d4-9f02-ba2e23f77074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511223699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1511223699
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.4172065409
Short name T210
Test name
Test status
Simulation time 20977796082 ps
CPU time 27.86 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:43:25 PM PDT 24
Peak memory 191892 kb
Host smart-0905fc64-6aa6-42e9-983a-f01697201737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172065409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.4172065409
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2790046894
Short name T264
Test name
Test status
Simulation time 338764893 ps
CPU time 1.05 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:42:55 PM PDT 24
Peak memory 191752 kb
Host smart-2b05899c-c53c-418a-b1e6-3088c8edccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790046894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2790046894
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.529249032
Short name T250
Test name
Test status
Simulation time 39439093204 ps
CPU time 32.19 seconds
Started Jun 11 01:42:36 PM PDT 24
Finished Jun 11 01:43:09 PM PDT 24
Peak memory 191908 kb
Host smart-41b91e36-0f0d-4f89-8d9f-45336330d694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529249032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.529249032
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3208329626
Short name T14
Test name
Test status
Simulation time 8769557814 ps
CPU time 7.58 seconds
Started Jun 11 01:42:44 PM PDT 24
Finished Jun 11 01:42:52 PM PDT 24
Peak memory 215916 kb
Host smart-01279caa-4f22-4f04-9b35-70939ef4234f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208329626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3208329626
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1103183681
Short name T205
Test name
Test status
Simulation time 550184839 ps
CPU time 0.82 seconds
Started Jun 11 01:42:40 PM PDT 24
Finished Jun 11 01:42:42 PM PDT 24
Peak memory 196560 kb
Host smart-c3c27930-6f71-49dd-8cc8-849a15c37ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103183681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1103183681
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2953173684
Short name T233
Test name
Test status
Simulation time 16946213170 ps
CPU time 7.45 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:43:00 PM PDT 24
Peak memory 191940 kb
Host smart-a9506069-5f71-4e62-b71f-2507fb1578cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953173684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2953173684
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3606571159
Short name T196
Test name
Test status
Simulation time 592214831 ps
CPU time 1.44 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:42:55 PM PDT 24
Peak memory 191712 kb
Host smart-e21a0830-2a37-40f9-942b-66dfc0a4fe90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606571159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3606571159
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.4143217388
Short name T271
Test name
Test status
Simulation time 29493141338 ps
CPU time 27.19 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:43:21 PM PDT 24
Peak memory 191896 kb
Host smart-343bdc97-086f-4e5d-8275-471a8b2f5821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143217388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4143217388
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.967614979
Short name T220
Test name
Test status
Simulation time 541966583 ps
CPU time 0.95 seconds
Started Jun 11 01:42:47 PM PDT 24
Finished Jun 11 01:42:50 PM PDT 24
Peak memory 191816 kb
Host smart-ca1c70eb-7d1b-4b7b-8301-e901d9efeecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967614979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.967614979
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2725512913
Short name T239
Test name
Test status
Simulation time 27543394328 ps
CPU time 12.68 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:43:11 PM PDT 24
Peak memory 191932 kb
Host smart-acf4926e-207a-4b34-80b5-5cfc2d20039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725512913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2725512913
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3474349309
Short name T22
Test name
Test status
Simulation time 480910614 ps
CPU time 1.34 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:42:57 PM PDT 24
Peak memory 191780 kb
Host smart-2c032dad-949f-49d5-877f-554dbf82ceb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474349309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3474349309
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3281656505
Short name T204
Test name
Test status
Simulation time 45085239566 ps
CPU time 35.26 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:43:34 PM PDT 24
Peak memory 191872 kb
Host smart-9e84df49-869c-478f-bbb1-f443464af2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281656505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3281656505
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.184443466
Short name T232
Test name
Test status
Simulation time 470196045 ps
CPU time 1.24 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:43:00 PM PDT 24
Peak memory 191808 kb
Host smart-f0561e96-c51a-4030-9d89-286aaeeac234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184443466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.184443466
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1959344509
Short name T225
Test name
Test status
Simulation time 33445553560 ps
CPU time 13.02 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:43:13 PM PDT 24
Peak memory 191872 kb
Host smart-68f20348-c736-494e-a789-feb053406cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959344509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1959344509
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2192043902
Short name T219
Test name
Test status
Simulation time 525980697 ps
CPU time 0.92 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:42:59 PM PDT 24
Peak memory 196500 kb
Host smart-4dc831a7-8d4b-4ee0-9b67-fa6ab5cdfc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192043902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2192043902
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_jump.914140005
Short name T178
Test name
Test status
Simulation time 462011819 ps
CPU time 1.36 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:42:55 PM PDT 24
Peak memory 196576 kb
Host smart-37de7b33-d7e5-42ae-a50b-b93566548caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914140005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.914140005
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1096352225
Short name T191
Test name
Test status
Simulation time 31200024307 ps
CPU time 25.95 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:43:25 PM PDT 24
Peak memory 191824 kb
Host smart-9c694629-6252-42a3-a7bd-2a0ec243e552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096352225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1096352225
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3806389240
Short name T8
Test name
Test status
Simulation time 399000708 ps
CPU time 1.15 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:43:02 PM PDT 24
Peak memory 191736 kb
Host smart-b4e394ba-6ac7-4b7b-8770-7830920faf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806389240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3806389240
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.443578912
Short name T202
Test name
Test status
Simulation time 46286192630 ps
CPU time 17.39 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:43:14 PM PDT 24
Peak memory 191912 kb
Host smart-2b2b20d6-f8d9-4581-96dc-e7652ca23016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443578912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.443578912
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2607411460
Short name T255
Test name
Test status
Simulation time 550516451 ps
CPU time 0.78 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:43:01 PM PDT 24
Peak memory 191788 kb
Host smart-80c949f7-d8d6-406a-b676-c699b5328e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607411460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2607411460
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2248210296
Short name T272
Test name
Test status
Simulation time 17292201747 ps
CPU time 26.48 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:43:26 PM PDT 24
Peak memory 191880 kb
Host smart-cdf366f5-f19f-4b04-bc60-84a7501365aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248210296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2248210296
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.366684415
Short name T266
Test name
Test status
Simulation time 408139868 ps
CPU time 0.72 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:43:00 PM PDT 24
Peak memory 191700 kb
Host smart-ca4b28de-3f77-4a47-8914-2d2404a9d5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366684415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.366684415
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1569623147
Short name T274
Test name
Test status
Simulation time 13905269299 ps
CPU time 21.89 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:43:22 PM PDT 24
Peak memory 191912 kb
Host smart-10fbbbff-ffa8-46ce-b3a2-5709b5047700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569623147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1569623147
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.293119572
Short name T147
Test name
Test status
Simulation time 521205923 ps
CPU time 0.83 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:42:53 PM PDT 24
Peak memory 191768 kb
Host smart-41a8d2bf-b154-4218-8cd1-ea15c7421b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293119572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.293119572
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1765878257
Short name T256
Test name
Test status
Simulation time 29176875098 ps
CPU time 50.54 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:43:47 PM PDT 24
Peak memory 191936 kb
Host smart-894208e9-107c-488e-a127-009e3b31feb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765878257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1765878257
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2298404252
Short name T236
Test name
Test status
Simulation time 587942810 ps
CPU time 1.54 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:42:58 PM PDT 24
Peak memory 191968 kb
Host smart-780aaa85-3882-4a2d-a24d-c20c23e21762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298404252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2298404252
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2748424805
Short name T177
Test name
Test status
Simulation time 411079697 ps
CPU time 0.78 seconds
Started Jun 11 01:42:48 PM PDT 24
Finished Jun 11 01:42:52 PM PDT 24
Peak memory 196520 kb
Host smart-783b21dc-265c-4357-ba7d-04379a79fefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748424805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2748424805
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1510674745
Short name T207
Test name
Test status
Simulation time 2654123466 ps
CPU time 1.78 seconds
Started Jun 11 01:42:48 PM PDT 24
Finished Jun 11 01:42:53 PM PDT 24
Peak memory 191916 kb
Host smart-05c04a0a-a1bb-44f9-a766-6fc3a3adbf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510674745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1510674745
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2893731669
Short name T17
Test name
Test status
Simulation time 4632111350 ps
CPU time 1.87 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:42:55 PM PDT 24
Peak memory 215976 kb
Host smart-2430b883-767d-412b-bd44-577a3ddad573
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893731669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2893731669
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2283985960
Short name T231
Test name
Test status
Simulation time 423468636 ps
CPU time 1.19 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:42:57 PM PDT 24
Peak memory 196596 kb
Host smart-5a34e1a3-9433-4490-a4bd-06eae488a66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283985960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2283985960
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.278408251
Short name T247
Test name
Test status
Simulation time 25309302937 ps
CPU time 18.55 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:43:17 PM PDT 24
Peak memory 191912 kb
Host smart-04e07184-a784-41a8-abcd-ab602fc5dfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278408251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.278408251
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.66721062
Short name T197
Test name
Test status
Simulation time 543895136 ps
CPU time 1.48 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:42:59 PM PDT 24
Peak memory 196568 kb
Host smart-6a9d3592-7363-4865-8478-3f919a485b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66721062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.66721062
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3782730602
Short name T240
Test name
Test status
Simulation time 34456562725 ps
CPU time 27.57 seconds
Started Jun 11 01:42:48 PM PDT 24
Finished Jun 11 01:43:18 PM PDT 24
Peak memory 196892 kb
Host smart-13c5243a-3ff9-407a-b574-b077d1153a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782730602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3782730602
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.4073999584
Short name T208
Test name
Test status
Simulation time 483242772 ps
CPU time 1.39 seconds
Started Jun 11 01:42:56 PM PDT 24
Finished Jun 11 01:43:02 PM PDT 24
Peak memory 191776 kb
Host smart-98e3ddd7-41f1-4f15-8974-46477997c5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073999584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.4073999584
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2910706299
Short name T273
Test name
Test status
Simulation time 52661489544 ps
CPU time 88.43 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:44:27 PM PDT 24
Peak memory 191932 kb
Host smart-b688a5ba-61e1-47c2-86ec-e07c4e6c28cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910706299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2910706299
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1516310535
Short name T203
Test name
Test status
Simulation time 632276759 ps
CPU time 0.82 seconds
Started Jun 11 01:42:56 PM PDT 24
Finished Jun 11 01:43:02 PM PDT 24
Peak memory 191812 kb
Host smart-e791f70d-e357-4cf5-9bd5-d3caa2691aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516310535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1516310535
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2873746228
Short name T183
Test name
Test status
Simulation time 415355942 ps
CPU time 1.16 seconds
Started Jun 11 01:42:50 PM PDT 24
Finished Jun 11 01:42:55 PM PDT 24
Peak memory 196556 kb
Host smart-dd0b18b1-a2ca-49fe-9fd4-d3634f0d01c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873746228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2873746228
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3451314132
Short name T257
Test name
Test status
Simulation time 38938890749 ps
CPU time 5.52 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:43:04 PM PDT 24
Peak memory 191920 kb
Host smart-3ef44c1a-a363-49c2-a669-62771025b22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451314132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3451314132
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3779513858
Short name T234
Test name
Test status
Simulation time 521405488 ps
CPU time 0.68 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:42:59 PM PDT 24
Peak memory 196512 kb
Host smart-7df56be5-0cd7-46d0-ad3d-6dd714b64eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779513858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3779513858
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2200716384
Short name T152
Test name
Test status
Simulation time 478975517 ps
CPU time 1.25 seconds
Started Jun 11 01:43:03 PM PDT 24
Finished Jun 11 01:43:06 PM PDT 24
Peak memory 196552 kb
Host smart-1e791cda-b4e8-436b-862a-7112db611d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200716384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2200716384
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.4090501271
Short name T228
Test name
Test status
Simulation time 30403698791 ps
CPU time 44.13 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:43:44 PM PDT 24
Peak memory 191876 kb
Host smart-667ba8c7-d5db-492f-86db-4ad9a83c10f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090501271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4090501271
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.4186882263
Short name T263
Test name
Test status
Simulation time 481046276 ps
CPU time 0.63 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:43:00 PM PDT 24
Peak memory 191684 kb
Host smart-d282f69e-61d9-48ad-9d8c-ef9373da3de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186882263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4186882263
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.256348162
Short name T226
Test name
Test status
Simulation time 37440497980 ps
CPU time 33.28 seconds
Started Jun 11 01:43:01 PM PDT 24
Finished Jun 11 01:43:37 PM PDT 24
Peak memory 191900 kb
Host smart-247afbce-0a2d-4ac3-aba2-dfc7552d22b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256348162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.256348162
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.406668895
Short name T193
Test name
Test status
Simulation time 553692649 ps
CPU time 0.95 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:43:00 PM PDT 24
Peak memory 191792 kb
Host smart-7ee92f8a-a512-416b-a13c-a65579470815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406668895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.406668895
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.644464517
Short name T269
Test name
Test status
Simulation time 7512879337 ps
CPU time 7.18 seconds
Started Jun 11 01:42:56 PM PDT 24
Finished Jun 11 01:43:09 PM PDT 24
Peak memory 191792 kb
Host smart-6b8ee8dc-2734-44c3-abe4-fce02378617c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644464517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.644464517
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2550228067
Short name T245
Test name
Test status
Simulation time 369213219 ps
CPU time 1.19 seconds
Started Jun 11 01:43:02 PM PDT 24
Finished Jun 11 01:43:06 PM PDT 24
Peak memory 191788 kb
Host smart-65704cfc-798e-4bd5-bb77-7753b8321f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550228067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2550228067
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2797169526
Short name T211
Test name
Test status
Simulation time 48854671855 ps
CPU time 45.93 seconds
Started Jun 11 01:43:01 PM PDT 24
Finished Jun 11 01:43:50 PM PDT 24
Peak memory 191888 kb
Host smart-0ff90392-f1c2-43d9-a8eb-fdaf8a950ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797169526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2797169526
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.4145817647
Short name T261
Test name
Test status
Simulation time 537851272 ps
CPU time 1.5 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:43:01 PM PDT 24
Peak memory 196532 kb
Host smart-e7a4d3df-bbbb-4b34-9ca3-c06f5e002b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145817647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.4145817647
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1117688534
Short name T42
Test name
Test status
Simulation time 21620905339 ps
CPU time 33.58 seconds
Started Jun 11 01:43:01 PM PDT 24
Finished Jun 11 01:43:37 PM PDT 24
Peak memory 192080 kb
Host smart-3c0431d5-c67d-49b4-be14-2d9b271d6d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117688534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1117688534
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1706201514
Short name T214
Test name
Test status
Simulation time 374707968 ps
CPU time 1.13 seconds
Started Jun 11 01:43:04 PM PDT 24
Finished Jun 11 01:43:07 PM PDT 24
Peak memory 191492 kb
Host smart-9e433ad3-9c00-4a52-b3b3-02f77a90b635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706201514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1706201514
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3748844077
Short name T277
Test name
Test status
Simulation time 57370804907 ps
CPU time 41.57 seconds
Started Jun 11 01:43:07 PM PDT 24
Finished Jun 11 01:43:49 PM PDT 24
Peak memory 191916 kb
Host smart-a9bbee7c-df73-4f12-be1f-a2afe59a636f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748844077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3748844077
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2251911928
Short name T270
Test name
Test status
Simulation time 436936450 ps
CPU time 0.74 seconds
Started Jun 11 01:42:56 PM PDT 24
Finished Jun 11 01:43:02 PM PDT 24
Peak memory 191732 kb
Host smart-b167736c-b4c0-4124-a98a-847e5a115e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251911928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2251911928
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1562994118
Short name T243
Test name
Test status
Simulation time 33775800244 ps
CPU time 48.36 seconds
Started Jun 11 01:42:46 PM PDT 24
Finished Jun 11 01:43:36 PM PDT 24
Peak memory 191892 kb
Host smart-78313503-0e06-4b9a-bfa3-d5a14bc3623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562994118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1562994118
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2569562107
Short name T15
Test name
Test status
Simulation time 7326767935 ps
CPU time 6.48 seconds
Started Jun 11 01:42:47 PM PDT 24
Finished Jun 11 01:42:56 PM PDT 24
Peak memory 215996 kb
Host smart-f042de63-2fb0-4020-a531-8ab0b05a7189
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569562107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2569562107
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.941081078
Short name T265
Test name
Test status
Simulation time 426417245 ps
CPU time 0.79 seconds
Started Jun 11 01:42:49 PM PDT 24
Finished Jun 11 01:42:53 PM PDT 24
Peak memory 196504 kb
Host smart-72df185d-4413-4ac7-8462-a24434e498a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941081078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.941081078
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_jump.248667465
Short name T170
Test name
Test status
Simulation time 552285829 ps
CPU time 1.39 seconds
Started Jun 11 01:43:04 PM PDT 24
Finished Jun 11 01:43:07 PM PDT 24
Peak memory 196560 kb
Host smart-cac948a2-de6c-48d2-a442-9df7a9ac3bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248667465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.248667465
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3288499783
Short name T244
Test name
Test status
Simulation time 59205388163 ps
CPU time 81.02 seconds
Started Jun 11 01:42:55 PM PDT 24
Finished Jun 11 01:44:22 PM PDT 24
Peak memory 191896 kb
Host smart-63305134-b395-42d5-8cfa-c9249b2a1388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288499783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3288499783
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1663101755
Short name T80
Test name
Test status
Simulation time 496007539 ps
CPU time 1.34 seconds
Started Jun 11 01:42:58 PM PDT 24
Finished Jun 11 01:43:03 PM PDT 24
Peak memory 196516 kb
Host smart-e00dcb36-7156-4c37-8149-2b186ed5b9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663101755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1663101755
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2733448291
Short name T260
Test name
Test status
Simulation time 39279872848 ps
CPU time 68.84 seconds
Started Jun 11 01:43:03 PM PDT 24
Finished Jun 11 01:44:14 PM PDT 24
Peak memory 191892 kb
Host smart-1ea05483-61ee-42a6-836c-54565356495e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733448291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2733448291
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.4048262893
Short name T229
Test name
Test status
Simulation time 619672169 ps
CPU time 0.69 seconds
Started Jun 11 01:43:11 PM PDT 24
Finished Jun 11 01:43:12 PM PDT 24
Peak memory 191736 kb
Host smart-60a0b1b9-2247-4a2d-9330-0efcea423774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048262893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.4048262893
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.975829395
Short name T254
Test name
Test status
Simulation time 10085022842 ps
CPU time 14.46 seconds
Started Jun 11 01:43:02 PM PDT 24
Finished Jun 11 01:43:22 PM PDT 24
Peak memory 191856 kb
Host smart-9d23cdef-76ce-4681-96ae-43929b47b68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975829395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.975829395
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.4233812542
Short name T241
Test name
Test status
Simulation time 551500875 ps
CPU time 0.83 seconds
Started Jun 11 01:43:03 PM PDT 24
Finished Jun 11 01:43:06 PM PDT 24
Peak memory 196584 kb
Host smart-bb909129-05b3-465b-8265-65c2bd1024a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233812542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.4233812542
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2405191286
Short name T268
Test name
Test status
Simulation time 1447959064 ps
CPU time 2.92 seconds
Started Jun 11 01:42:56 PM PDT 24
Finished Jun 11 01:43:04 PM PDT 24
Peak memory 191740 kb
Host smart-881a4268-57d2-471c-b462-eac30730a588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405191286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2405191286
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2993685160
Short name T279
Test name
Test status
Simulation time 359149502 ps
CPU time 0.87 seconds
Started Jun 11 01:43:03 PM PDT 24
Finished Jun 11 01:43:06 PM PDT 24
Peak memory 191752 kb
Host smart-58691d01-a5ef-46e0-b1b1-b958b4edb525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993685160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2993685160
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2070547148
Short name T217
Test name
Test status
Simulation time 37378459228 ps
CPU time 13.58 seconds
Started Jun 11 01:43:02 PM PDT 24
Finished Jun 11 01:43:18 PM PDT 24
Peak memory 191764 kb
Host smart-9b163b51-bff9-4a67-9fb2-d36ad989477b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070547148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2070547148
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.185396507
Short name T198
Test name
Test status
Simulation time 494564316 ps
CPU time 0.95 seconds
Started Jun 11 01:43:03 PM PDT 24
Finished Jun 11 01:43:06 PM PDT 24
Peak memory 191808 kb
Host smart-4baa6abe-af16-430b-8975-b8cde64e90e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185396507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.185396507
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3149119812
Short name T200
Test name
Test status
Simulation time 30922077874 ps
CPU time 23.21 seconds
Started Jun 11 01:43:18 PM PDT 24
Finished Jun 11 01:43:42 PM PDT 24
Peak memory 191908 kb
Host smart-71124506-7571-4447-9562-05929b0f91d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149119812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3149119812
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2623131779
Short name T216
Test name
Test status
Simulation time 381016397 ps
CPU time 1.22 seconds
Started Jun 11 01:43:16 PM PDT 24
Finished Jun 11 01:43:17 PM PDT 24
Peak memory 191776 kb
Host smart-e6dd665c-9a7a-4c15-9c8d-063f22bd395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623131779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2623131779
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.967010681
Short name T253
Test name
Test status
Simulation time 28103830917 ps
CPU time 9.16 seconds
Started Jun 11 01:42:53 PM PDT 24
Finished Jun 11 01:43:07 PM PDT 24
Peak memory 191844 kb
Host smart-7bcc92c4-0303-443c-9a17-0664bf10a5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967010681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.967010681
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3478072310
Short name T201
Test name
Test status
Simulation time 417966846 ps
CPU time 1.17 seconds
Started Jun 11 01:43:06 PM PDT 24
Finished Jun 11 01:43:08 PM PDT 24
Peak memory 191776 kb
Host smart-70c07286-b4f0-48b8-9c44-74fbe0b4a1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478072310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3478072310
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1931165293
Short name T49
Test name
Test status
Simulation time 31721678181 ps
CPU time 50.55 seconds
Started Jun 11 01:43:07 PM PDT 24
Finished Jun 11 01:43:59 PM PDT 24
Peak memory 191824 kb
Host smart-d9f7e03b-b308-4876-9da8-4ad766165724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931165293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1931165293
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1528234718
Short name T248
Test name
Test status
Simulation time 568354380 ps
CPU time 1.48 seconds
Started Jun 11 01:43:14 PM PDT 24
Finished Jun 11 01:43:16 PM PDT 24
Peak memory 191768 kb
Host smart-8814c673-df5b-4b9c-9bd9-3a172d14704b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528234718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1528234718
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.4143484034
Short name T251
Test name
Test status
Simulation time 1081400783 ps
CPU time 0.95 seconds
Started Jun 11 01:43:25 PM PDT 24
Finished Jun 11 01:43:27 PM PDT 24
Peak memory 191788 kb
Host smart-1413a895-6e74-4643-a6af-0a283b4a42f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143484034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4143484034
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1939703979
Short name T50
Test name
Test status
Simulation time 619874084 ps
CPU time 0.68 seconds
Started Jun 11 01:43:05 PM PDT 24
Finished Jun 11 01:43:07 PM PDT 24
Peak memory 191796 kb
Host smart-d4ddc1d7-2aca-4b40-9fcf-af274b90f1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939703979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1939703979
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2085646245
Short name T235
Test name
Test status
Simulation time 10942571887 ps
CPU time 3.73 seconds
Started Jun 11 01:43:21 PM PDT 24
Finished Jun 11 01:43:25 PM PDT 24
Peak memory 191912 kb
Host smart-50ff1660-6d0a-4ec4-a0e2-ba2716551c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085646245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2085646245
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1188424278
Short name T213
Test name
Test status
Simulation time 565128033 ps
CPU time 1.42 seconds
Started Jun 11 01:43:22 PM PDT 24
Finished Jun 11 01:43:24 PM PDT 24
Peak memory 191812 kb
Host smart-c9e9ec04-eef2-4e65-bafd-84f88469c363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188424278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1188424278
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1590616738
Short name T259
Test name
Test status
Simulation time 52311228120 ps
CPU time 79.85 seconds
Started Jun 11 01:42:54 PM PDT 24
Finished Jun 11 01:44:18 PM PDT 24
Peak memory 191944 kb
Host smart-aacea2c1-487b-43bf-88f5-e2ed76192504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590616738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1590616738
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.114026630
Short name T242
Test name
Test status
Simulation time 569123653 ps
CPU time 0.79 seconds
Started Jun 11 01:42:40 PM PDT 24
Finished Jun 11 01:42:42 PM PDT 24
Peak memory 191724 kb
Host smart-dab84021-8255-42b5-99e3-6cf3b90df79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114026630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.114026630
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1743287657
Short name T11
Test name
Test status
Simulation time 21326929426 ps
CPU time 18.42 seconds
Started Jun 11 01:42:47 PM PDT 24
Finished Jun 11 01:43:08 PM PDT 24
Peak memory 191628 kb
Host smart-eafd082e-f9ad-43c7-837f-cf0c5655e23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743287657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1743287657
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1638882171
Short name T218
Test name
Test status
Simulation time 516914634 ps
CPU time 1.34 seconds
Started Jun 11 01:42:47 PM PDT 24
Finished Jun 11 01:42:51 PM PDT 24
Peak memory 191788 kb
Host smart-96437d91-eeb6-4d93-bb4e-f06a9e1ffa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638882171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1638882171
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1549039536
Short name T237
Test name
Test status
Simulation time 2819002599 ps
CPU time 1.58 seconds
Started Jun 11 01:42:43 PM PDT 24
Finished Jun 11 01:42:45 PM PDT 24
Peak memory 191880 kb
Host smart-5e7e54da-a7bb-4456-bdbc-a6ad3e7ea0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549039536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1549039536
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3272813295
Short name T148
Test name
Test status
Simulation time 554581073 ps
CPU time 0.7 seconds
Started Jun 11 01:42:45 PM PDT 24
Finished Jun 11 01:42:46 PM PDT 24
Peak memory 191760 kb
Host smart-2eee099c-22de-4049-bdc9-39aa40ba21dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272813295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3272813295
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1343293063
Short name T267
Test name
Test status
Simulation time 3106214700 ps
CPU time 5.58 seconds
Started Jun 11 01:42:47 PM PDT 24
Finished Jun 11 01:42:55 PM PDT 24
Peak memory 191920 kb
Host smart-97cbe731-0d63-456d-8aa7-bddbdcbf97d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343293063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1343293063
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.245559724
Short name T194
Test name
Test status
Simulation time 531159760 ps
CPU time 0.75 seconds
Started Jun 11 01:42:52 PM PDT 24
Finished Jun 11 01:42:57 PM PDT 24
Peak memory 196236 kb
Host smart-4c1a960b-b45c-4f39-8a4f-ee30949834c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245559724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.245559724
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2679156018
Short name T52
Test name
Test status
Simulation time 43919625720 ps
CPU time 30.25 seconds
Started Jun 11 01:42:46 PM PDT 24
Finished Jun 11 01:43:19 PM PDT 24
Peak memory 198272 kb
Host smart-713d37dc-c2c5-4145-bf89-4ef44de834d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679156018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2679156018
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1438586187
Short name T206
Test name
Test status
Simulation time 25884503537 ps
CPU time 8.34 seconds
Started Jun 11 01:42:40 PM PDT 24
Finished Jun 11 01:42:49 PM PDT 24
Peak memory 192108 kb
Host smart-ab2a0e34-3669-4538-a895-b3c1593a3a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438586187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1438586187
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3457299970
Short name T230
Test name
Test status
Simulation time 611537487 ps
CPU time 0.82 seconds
Started Jun 11 01:42:51 PM PDT 24
Finished Jun 11 01:42:57 PM PDT 24
Peak memory 191772 kb
Host smart-36c58d2a-5fe0-4204-9d4e-eae788ff8785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457299970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3457299970
Directory /workspace/9.aon_timer_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%