Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	28589	1		T1	34		T3	12		T4	12
bark[1]	636	1		T16	26		T42	276		T144	30
bark[2]	539	1		T10	30		T42	26		T147	35
bark[3]	376	1		T23	42		T178	21		T176	101
bark[4]	710	1		T2	14		T15	14		T164	21
bark[5]	357	1		T48	21		T52	122		T145	21
bark[6]	332	1		T176	39		T114	21		T112	51
bark[7]	460	1		T46	76		T96	14		T42	21
bark[8]	469	1		T10	30		T20	152		T23	21
bark[9]	383	1		T13	14		T43	14		T46	33
bark[10]	710	1		T52	170		T93	53		T150	31
bark[11]	252	1		T26	14		T27	62		T48	26
bark[12]	716	1		T1	257		T31	14		T49	52
bark[13]	399	1		T23	21		T25	83		T42	148
bark[14]	639	1		T16	21		T29	100		T93	21
bark[15]	487	1		T23	21		T51	26		T176	21
bark[16]	643	1		T5	21		T16	21		T48	26
bark[17]	329	1		T10	48		T178	30		T158	53
bark[18]	1609	1		T42	177		T158	850		T146	21
bark[19]	274	1		T138	47		T154	26		T135	47
bark[20]	391	1		T14	14		T23	21		T40	26
bark[21]	491	1		T23	30		T27	7		T178	14
bark[22]	129	1		T78	14		T84	26		T138	26
bark[23]	510	1		T23	21		T49	21		T114	21
bark[24]	714	1		T10	21		T25	14		T190	14
bark[25]	524	1		T27	21		T138	21		T146	21
bark[26]	438	1		T16	21		T27	47		T102	51
bark[27]	359	1		T1	21		T10	35		T23	14
bark[28]	602	1		T24	14		T42	67		T147	173
bark[29]	91	1		T46	21		T42	30		T185	14
bark[30]	339	1		T5	35		T42	7		T114	21
bark[31]	751	1		T25	240		T176	21		T163	14
bark_0	4661	1		T1	42		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	28073	1		T1	31		T3	11		T4	11
bite[1]	154	1		T138	21		T106	21		T149	21
bite[2]	359	1		T23	30		T178	30		T96	13
bite[3]	454	1		T26	13		T176	122		T102	81
bite[4]	747	1		T23	21		T183	245		T85	163
bite[5]	446	1		T16	21		T46	76		T49	21
bite[6]	879	1		T119	13		T154	21		T101	21
bite[7]	483	1		T15	13		T23	21		T48	26
bite[8]	613	1		T25	239		T42	25		T163	13
bite[9]	694	1		T14	13		T42	176		T52	169
bite[10]	378	1		T5	42		T31	13		T190	13
bite[11]	383	1		T24	13		T27	6		T145	21
bite[12]	434	1		T10	30		T178	21		T150	21
bite[13]	1315	1		T159	13		T158	849		T129	21
bite[14]	505	1		T29	98		T48	26		T178	13
bite[15]	400	1		T1	277		T49	21		T135	47
bite[16]	401	1		T13	13		T147	190		T109	21
bite[17]	442	1		T30	25		T48	21		T134	26
bite[18]	643	1		T2	13		T16	47		T41	180
bite[19]	315	1		T78	13		T23	21		T51	26
bite[20]	676	1		T5	13		T10	30		T16	21
bite[21]	705	1		T27	21		T164	21		T120	22
bite[22]	506	1		T178	21		T42	27		T102	21
bite[23]	565	1		T10	42		T43	13		T27	46
bite[24]	441	1		T10	48		T20	152		T46	21
bite[25]	212	1		T23	13		T25	13		T176	21
bite[26]	429	1		T10	13		T27	61		T147	35
bite[27]	230	1		T176	39		T146	21		T177	13
bite[28]	343	1		T23	42		T93	21		T155	25
bite[29]	578	1		T23	42		T40	145		T147	172
bite[30]	291	1		T29	99		T42	66		T144	21
bite[31]	657	1		T25	82		T46	32		T49	31
bite_0	5158	1		T1	46		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	48909	1		T1	354		T2	21		T3	19

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1137	1		T23	37		T48	9		T42	84
prescale[1]	871	1		T29	20		T49	23		T178	40
prescale[2]	504	1		T1	63		T26	19		T30	40
prescale[3]	789	1		T20	27		T25	58		T29	2
prescale[4]	1432	1		T1	143		T11	2		T25	19
prescale[5]	595	1		T5	28		T26	19		T29	2
prescale[6]	461	1		T11	20		T16	24		T25	9
prescale[7]	783	1		T5	28		T50	19		T42	19
prescale[8]	601	1		T7	9		T10	19		T28	9
prescale[9]	477	1		T25	87		T27	23		T51	9
prescale[10]	1272	1		T1	49		T5	28		T10	32
prescale[11]	788	1		T11	20		T16	2		T29	2
prescale[12]	571	1		T10	51		T41	2		T163	24
prescale[13]	911	1		T16	40		T25	29		T40	39
prescale[14]	872	1		T16	2		T25	9		T26	37
prescale[15]	380	1		T1	20		T25	37		T42	2
prescale[16]	690	1		T25	54		T29	19		T40	16
prescale[17]	562	1		T4	9		T10	19		T20	61
prescale[18]	952	1		T3	9		T10	53		T12	9
prescale[19]	808	1		T1	2		T8	9		T16	45
prescale[20]	1070	1		T30	2		T49	19		T50	19
prescale[21]	400	1		T25	41		T27	2		T164	38
prescale[22]	685	1		T25	19		T27	110		T49	50
prescale[23]	798	1		T11	2		T20	23		T16	2
prescale[24]	735	1		T1	2		T27	40		T46	9
prescale[25]	607	1		T20	49		T42	2		T158	19
prescale[26]	225	1		T51	46		T158	24		T150	23
prescale[27]	539	1		T11	2		T41	38		T183	2
prescale[28]	845	1		T16	77		T25	82		T26	58
prescale[29]	664	1		T6	9		T20	85		T25	88
prescale[30]	837	1		T41	4		T196	9		T183	136
prescale[31]	869	1		T5	42		T16	19		T25	47
prescale_0	25179	1		T1	75		T2	21		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	37054	1		T1	270		T2	9		T3	19
auto[1]	11855	1		T1	84		T2	12		T4	10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	48909	1		T1	354		T2	21		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	28704	1		T1	201		T2	1		T3	14
wkup[1]	173	1		T20	21		T147	21		T112	21
wkup[2]	248	1		T10	30		T11	26		T29	21
wkup[3]	306	1		T29	21		T163	21		T147	21
wkup[4]	329	1		T10	21		T42	30		T147	26
wkup[5]	169	1		T30	26		T183	38		T79	21
wkup[6]	174	1		T166	15		T87	21		T140	40
wkup[7]	327	1		T10	21		T11	21		T41	31
wkup[8]	244	1		T23	21		T25	21		T84	21
wkup[9]	248	1		T14	15		T16	26		T42	21
wkup[10]	258	1		T23	21		T26	15		T30	21
wkup[11]	276	1		T1	21		T20	21		T16	21
wkup[12]	179	1		T85	8		T114	21		T88	21
wkup[13]	160	1		T16	8		T29	30		T49	21
wkup[14]	224	1		T25	21		T42	21		T93	21
wkup[15]	335	1		T29	21		T178	30		T183	21
wkup[16]	357	1		T25	21		T40	40		T84	21
wkup[17]	129	1		T2	15		T178	21		T146	21
wkup[18]	380	1		T26	21		T30	21		T51	26
wkup[19]	276	1		T27	41		T183	21		T120	24
wkup[20]	332	1		T42	30		T147	35		T158	51
wkup[21]	272	1		T20	21		T114	21		T112	21
wkup[22]	251	1		T178	36		T183	21		T158	15
wkup[23]	407	1		T11	21		T23	21		T16	21
wkup[24]	408	1		T5	15		T10	15		T27	8
wkup[25]	293	1		T85	21		T138	21		T87	21
wkup[26]	202	1		T25	42		T29	21		T42	8
wkup[27]	278	1		T25	21		T158	21		T150	21
wkup[28]	331	1		T1	26		T29	21		T52	21
wkup[29]	317	1		T42	21		T93	33		T85	51
wkup[30]	176	1		T31	15		T52	15		T138	21
wkup[31]	242	1		T25	21		T49	31		T41	8
wkup[32]	260	1		T29	21		T84	21		T150	31
wkup[33]	328	1		T27	42		T144	30		T158	26
wkup[34]	218	1		T20	21		T93	21		T143	21
wkup[35]	387	1		T10	30		T144	21		T84	21
wkup[36]	157	1		T16	21		T25	15		T85	21
wkup[37]	131	1		T15	15		T23	21		T42	21
wkup[38]	406	1		T1	21		T5	21		T25	72
wkup[39]	314	1		T29	21		T93	21		T138	21
wkup[40]	265	1		T48	26		T159	15		T154	15
wkup[41]	225	1		T20	21		T41	21		T42	21
wkup[42]	212	1		T25	21		T46	21		T48	39
wkup[43]	113	1		T20	21		T41	21		T176	21
wkup[44]	209	1		T52	21		T91	21		T109	21
wkup[45]	269	1		T183	6		T52	21		T154	42
wkup[46]	397	1		T23	51		T16	21		T147	21
wkup[47]	328	1		T42	35		T102	30		T138	21
wkup[48]	223	1		T43	15		T42	21		T87	47
wkup[49]	140	1		T23	21		T27	21		T29	21
wkup[50]	226	1		T24	15		T49	21		T154	26
wkup[51]	305	1		T16	21		T29	21		T30	15
wkup[52]	191	1		T42	21		T101	21		T109	47
wkup[53]	355	1		T13	15		T23	15		T25	21
wkup[54]	252	1		T26	39		T41	51		T147	21
wkup[55]	315	1		T48	35		T42	21		T163	21
wkup[56]	256	1		T1	30		T25	21		T40	21
wkup[57]	323	1		T5	21		T78	15		T25	21
wkup[58]	218	1		T41	26		T42	42		T84	21
wkup[59]	271	1		T20	30		T42	21		T164	21
wkup[60]	183	1		T40	21		T178	21		T147	21
wkup[61]	184	1		T190	15		T52	21		T131	15
wkup[62]	348	1		T1	21		T25	21		T42	21
wkup[63]	255	1		T10	21		T25	21		T29	21
wkup_0	3640	1		T1	34		T2	5		T3	5