Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.85 99.33 93.67 100.00 98.40 99.51 48.20


Total test records in report: 424
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T33 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2943429412 Jun 13 02:16:43 PM PDT 24 Jun 13 02:16:51 PM PDT 24 548942002 ps
T286 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2268587317 Jun 13 02:16:35 PM PDT 24 Jun 13 02:16:41 PM PDT 24 1317009297 ps
T37 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2270542970 Jun 13 02:16:31 PM PDT 24 Jun 13 02:16:38 PM PDT 24 575357081 ps
T287 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1283980848 Jun 13 02:16:39 PM PDT 24 Jun 13 02:16:45 PM PDT 24 490759264 ps
T38 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.849726553 Jun 13 02:16:27 PM PDT 24 Jun 13 02:16:42 PM PDT 24 7122572991 ps
T39 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4222874290 Jun 13 02:16:56 PM PDT 24 Jun 13 02:17:05 PM PDT 24 434814036 ps
T288 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3505455757 Jun 13 02:16:25 PM PDT 24 Jun 13 02:16:30 PM PDT 24 442249665 ps
T289 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.430435761 Jun 13 02:16:49 PM PDT 24 Jun 13 02:17:00 PM PDT 24 494621498 ps
T34 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1597475224 Jun 13 02:16:20 PM PDT 24 Jun 13 02:16:29 PM PDT 24 3822258748 ps
T290 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1699063404 Jun 13 02:16:36 PM PDT 24 Jun 13 02:16:44 PM PDT 24 469242976 ps
T291 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3588844622 Jun 13 02:16:54 PM PDT 24 Jun 13 02:17:02 PM PDT 24 483375553 ps
T292 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3213033566 Jun 13 02:16:23 PM PDT 24 Jun 13 02:16:29 PM PDT 24 536989959 ps
T55 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.802824181 Jun 13 02:16:31 PM PDT 24 Jun 13 02:16:42 PM PDT 24 13108479004 ps
T69 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2099861127 Jun 13 02:16:46 PM PDT 24 Jun 13 02:16:54 PM PDT 24 1173800717 ps
T293 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.140276480 Jun 13 02:16:39 PM PDT 24 Jun 13 02:16:46 PM PDT 24 473414393 ps
T35 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.852606509 Jun 13 02:16:55 PM PDT 24 Jun 13 02:17:10 PM PDT 24 4692148967 ps
T294 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3600076572 Jun 13 02:16:55 PM PDT 24 Jun 13 02:17:04 PM PDT 24 461404496 ps
T295 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.210855784 Jun 13 02:16:38 PM PDT 24 Jun 13 02:16:45 PM PDT 24 438740329 ps
T296 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.930372666 Jun 13 02:16:37 PM PDT 24 Jun 13 02:16:44 PM PDT 24 541826226 ps
T70 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3264099897 Jun 13 02:16:47 PM PDT 24 Jun 13 02:16:55 PM PDT 24 431157807 ps
T297 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.934398633 Jun 13 02:16:22 PM PDT 24 Jun 13 02:16:28 PM PDT 24 379962098 ps
T298 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3991121432 Jun 13 02:16:26 PM PDT 24 Jun 13 02:16:32 PM PDT 24 356265197 ps
T299 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3466159947 Jun 13 02:16:54 PM PDT 24 Jun 13 02:17:03 PM PDT 24 388662971 ps
T300 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.778695415 Jun 13 02:17:02 PM PDT 24 Jun 13 02:17:09 PM PDT 24 287036856 ps
T56 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4051447626 Jun 13 02:16:57 PM PDT 24 Jun 13 02:17:05 PM PDT 24 359989276 ps
T301 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3070915870 Jun 13 02:16:50 PM PDT 24 Jun 13 02:16:59 PM PDT 24 1048288115 ps
T302 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.979503080 Jun 13 02:16:25 PM PDT 24 Jun 13 02:16:30 PM PDT 24 347802266 ps
T303 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3812038830 Jun 13 02:17:05 PM PDT 24 Jun 13 02:17:12 PM PDT 24 461378449 ps
T36 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.447811475 Jun 13 02:16:57 PM PDT 24 Jun 13 02:17:07 PM PDT 24 8739307652 ps
T304 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1551457470 Jun 13 02:16:45 PM PDT 24 Jun 13 02:16:53 PM PDT 24 451792812 ps
T305 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.712359186 Jun 13 02:16:44 PM PDT 24 Jun 13 02:16:54 PM PDT 24 548837207 ps
T57 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2911343093 Jun 13 02:16:26 PM PDT 24 Jun 13 02:16:31 PM PDT 24 649452830 ps
T306 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2576474061 Jun 13 02:16:34 PM PDT 24 Jun 13 02:16:41 PM PDT 24 548696574 ps
T307 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2236843619 Jun 13 02:16:54 PM PDT 24 Jun 13 02:17:03 PM PDT 24 295367330 ps
T308 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.95023819 Jun 13 02:16:55 PM PDT 24 Jun 13 02:17:04 PM PDT 24 306959486 ps
T71 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1448493573 Jun 13 02:16:45 PM PDT 24 Jun 13 02:16:54 PM PDT 24 833781919 ps
T309 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3552349836 Jun 13 02:16:25 PM PDT 24 Jun 13 02:16:30 PM PDT 24 483400361 ps
T310 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2039682168 Jun 13 02:16:24 PM PDT 24 Jun 13 02:16:30 PM PDT 24 719980641 ps
T311 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3112779650 Jun 13 02:16:37 PM PDT 24 Jun 13 02:16:43 PM PDT 24 483222855 ps
T312 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3453501772 Jun 13 02:16:54 PM PDT 24 Jun 13 02:17:03 PM PDT 24 435141278 ps
T313 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3626938569 Jun 13 02:16:22 PM PDT 24 Jun 13 02:16:26 PM PDT 24 459160489 ps
T72 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2365997267 Jun 13 02:16:37 PM PDT 24 Jun 13 02:16:44 PM PDT 24 379039263 ps
T73 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1593963225 Jun 13 02:16:26 PM PDT 24 Jun 13 02:16:32 PM PDT 24 2204375455 ps
T74 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1546692454 Jun 13 02:16:23 PM PDT 24 Jun 13 02:16:31 PM PDT 24 2051009915 ps
T75 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1359826812 Jun 13 02:16:48 PM PDT 24 Jun 13 02:16:57 PM PDT 24 355471995 ps
T314 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.827082243 Jun 13 02:17:06 PM PDT 24 Jun 13 02:17:12 PM PDT 24 348024030 ps
T315 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.963308477 Jun 13 02:16:54 PM PDT 24 Jun 13 02:17:02 PM PDT 24 778075232 ps
T76 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2681062262 Jun 13 02:16:48 PM PDT 24 Jun 13 02:16:57 PM PDT 24 1016558292 ps
T58 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2231517831 Jun 13 02:16:43 PM PDT 24 Jun 13 02:16:50 PM PDT 24 473951339 ps
T193 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2323049456 Jun 13 02:16:29 PM PDT 24 Jun 13 02:16:42 PM PDT 24 8177948409 ps
T316 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2394655966 Jun 13 02:16:37 PM PDT 24 Jun 13 02:16:45 PM PDT 24 760782450 ps
T317 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3736134475 Jun 13 02:16:16 PM PDT 24 Jun 13 02:16:18 PM PDT 24 365184065 ps
T318 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.645435918 Jun 13 02:16:27 PM PDT 24 Jun 13 02:16:32 PM PDT 24 574746117 ps
T319 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1713464672 Jun 13 02:17:05 PM PDT 24 Jun 13 02:17:12 PM PDT 24 480591150 ps
T320 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1630860723 Jun 13 02:16:56 PM PDT 24 Jun 13 02:17:04 PM PDT 24 295779027 ps
T77 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2868596616 Jun 13 02:16:55 PM PDT 24 Jun 13 02:17:03 PM PDT 24 385802177 ps
T321 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.696393617 Jun 13 02:16:42 PM PDT 24 Jun 13 02:16:49 PM PDT 24 373694614 ps
T322 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3072261831 Jun 13 02:16:42 PM PDT 24 Jun 13 02:16:50 PM PDT 24 499247422 ps
T323 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.950984349 Jun 13 02:16:49 PM PDT 24 Jun 13 02:16:57 PM PDT 24 400685366 ps
T324 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2420514442 Jun 13 02:16:42 PM PDT 24 Jun 13 02:16:49 PM PDT 24 606486363 ps
T325 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1097906451 Jun 13 02:17:05 PM PDT 24 Jun 13 02:17:12 PM PDT 24 389598178 ps
T326 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4277957408 Jun 13 02:16:36 PM PDT 24 Jun 13 02:16:43 PM PDT 24 396634069 ps
T327 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2553858275 Jun 13 02:16:32 PM PDT 24 Jun 13 02:16:37 PM PDT 24 399793445 ps
T328 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.273185513 Jun 13 02:16:26 PM PDT 24 Jun 13 02:16:31 PM PDT 24 380350447 ps
T329 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2751760041 Jun 13 02:16:46 PM PDT 24 Jun 13 02:16:54 PM PDT 24 434427224 ps
T330 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2935557810 Jun 13 02:16:51 PM PDT 24 Jun 13 02:17:01 PM PDT 24 402605845 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.829306262 Jun 13 02:16:21 PM PDT 24 Jun 13 02:16:31 PM PDT 24 12168943937 ps
T331 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4247725443 Jun 13 02:16:25 PM PDT 24 Jun 13 02:16:29 PM PDT 24 466201244 ps
T332 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2292565137 Jun 13 02:16:26 PM PDT 24 Jun 13 02:16:32 PM PDT 24 2317342569 ps
T333 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2134150086 Jun 13 02:16:44 PM PDT 24 Jun 13 02:16:53 PM PDT 24 286162275 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2979335574 Jun 13 02:16:25 PM PDT 24 Jun 13 02:16:44 PM PDT 24 7125732543 ps
T334 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3365165484 Jun 13 02:16:32 PM PDT 24 Jun 13 02:16:38 PM PDT 24 436567326 ps
T194 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3038851275 Jun 13 02:16:50 PM PDT 24 Jun 13 02:17:00 PM PDT 24 4423024671 ps
T335 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1888102206 Jun 13 02:16:42 PM PDT 24 Jun 13 02:16:50 PM PDT 24 886688442 ps
T336 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.820719928 Jun 13 02:16:51 PM PDT 24 Jun 13 02:17:00 PM PDT 24 420364292 ps
T337 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.991580974 Jun 13 02:16:57 PM PDT 24 Jun 13 02:17:05 PM PDT 24 349920387 ps
T338 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3585912556 Jun 13 02:16:54 PM PDT 24 Jun 13 02:17:02 PM PDT 24 465636781 ps
T195 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3855159910 Jun 13 02:16:20 PM PDT 24 Jun 13 02:16:35 PM PDT 24 8481964031 ps
T339 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3916331260 Jun 13 02:16:54 PM PDT 24 Jun 13 02:17:03 PM PDT 24 1343777926 ps
T340 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3438264239 Jun 13 02:17:03 PM PDT 24 Jun 13 02:17:10 PM PDT 24 337279635 ps
T341 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2572534650 Jun 13 02:16:36 PM PDT 24 Jun 13 02:16:42 PM PDT 24 433854852 ps
T342 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2613770339 Jun 13 02:16:46 PM PDT 24 Jun 13 02:16:54 PM PDT 24 457106973 ps
T343 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.826078579 Jun 13 02:16:54 PM PDT 24 Jun 13 02:17:03 PM PDT 24 439305690 ps
T344 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3103353182 Jun 13 02:16:42 PM PDT 24 Jun 13 02:16:50 PM PDT 24 2105537672 ps
T345 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4052346911 Jun 13 02:16:36 PM PDT 24 Jun 13 02:16:44 PM PDT 24 2446954581 ps
T346 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3940255822 Jun 13 02:16:41 PM PDT 24 Jun 13 02:16:48 PM PDT 24 352591583 ps
T347 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1983771964 Jun 13 02:16:48 PM PDT 24 Jun 13 02:16:57 PM PDT 24 1386714565 ps
T61 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.581306004 Jun 13 02:16:38 PM PDT 24 Jun 13 02:16:45 PM PDT 24 397893661 ps
T348 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3707654213 Jun 13 02:17:03 PM PDT 24 Jun 13 02:17:10 PM PDT 24 439365047 ps
T349 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1103685168 Jun 13 02:16:31 PM PDT 24 Jun 13 02:16:37 PM PDT 24 435555700 ps
T350 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1893457765 Jun 13 02:16:44 PM PDT 24 Jun 13 02:16:52 PM PDT 24 350796868 ps
T351 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.371145331 Jun 13 02:17:02 PM PDT 24 Jun 13 02:17:08 PM PDT 24 479272706 ps
T191 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4028760331 Jun 13 02:16:36 PM PDT 24 Jun 13 02:16:46 PM PDT 24 7994720872 ps
T352 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2002333404 Jun 13 02:16:32 PM PDT 24 Jun 13 02:16:44 PM PDT 24 4340615329 ps
T353 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.170786850 Jun 13 02:16:37 PM PDT 24 Jun 13 02:16:45 PM PDT 24 1207621967 ps
T354 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.598900298 Jun 13 02:16:37 PM PDT 24 Jun 13 02:16:44 PM PDT 24 2168432094 ps
T355 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3173681631 Jun 13 02:16:44 PM PDT 24 Jun 13 02:16:58 PM PDT 24 4152057598 ps
T64 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1956538266 Jun 13 02:16:29 PM PDT 24 Jun 13 02:16:36 PM PDT 24 1300024015 ps
T356 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.516111187 Jun 13 02:16:26 PM PDT 24 Jun 13 02:16:34 PM PDT 24 4201356021 ps
T65 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1067644581 Jun 13 02:16:25 PM PDT 24 Jun 13 02:16:30 PM PDT 24 859213691 ps
T357 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2071836612 Jun 13 02:16:49 PM PDT 24 Jun 13 02:16:59 PM PDT 24 3784629818 ps
T358 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2427817613 Jun 13 02:16:25 PM PDT 24 Jun 13 02:16:30 PM PDT 24 487471885 ps
T359 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3870625300 Jun 13 02:17:01 PM PDT 24 Jun 13 02:17:08 PM PDT 24 356417559 ps
T192 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4223507628 Jun 13 02:16:46 PM PDT 24 Jun 13 02:16:57 PM PDT 24 7847277455 ps
T360 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.391960375 Jun 13 02:17:05 PM PDT 24 Jun 13 02:17:12 PM PDT 24 333265783 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3138821057 Jun 13 02:16:40 PM PDT 24 Jun 13 02:16:48 PM PDT 24 700365218 ps
T361 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3909284329 Jun 13 02:16:45 PM PDT 24 Jun 13 02:17:02 PM PDT 24 8432792946 ps
T362 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.443147468 Jun 13 02:16:32 PM PDT 24 Jun 13 02:16:38 PM PDT 24 405508256 ps
T363 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.308794976 Jun 13 02:17:05 PM PDT 24 Jun 13 02:17:12 PM PDT 24 408091746 ps
T364 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1884067923 Jun 13 02:16:18 PM PDT 24 Jun 13 02:16:23 PM PDT 24 436302604 ps
T365 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2905940389 Jun 13 02:16:36 PM PDT 24 Jun 13 02:16:43 PM PDT 24 585605188 ps
T366 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1778299821 Jun 13 02:16:54 PM PDT 24 Jun 13 02:17:03 PM PDT 24 426569928 ps
T367 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3337197532 Jun 13 02:16:29 PM PDT 24 Jun 13 02:16:35 PM PDT 24 470352706 ps
T368 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3988490908 Jun 13 02:16:43 PM PDT 24 Jun 13 02:16:51 PM PDT 24 591202465 ps
T369 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1995510880 Jun 13 02:16:27 PM PDT 24 Jun 13 02:16:32 PM PDT 24 442796440 ps
T370 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3903019410 Jun 13 02:16:36 PM PDT 24 Jun 13 02:16:42 PM PDT 24 2446309304 ps
T371 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2768698551 Jun 13 02:16:54 PM PDT 24 Jun 13 02:17:03 PM PDT 24 424372204 ps
T372 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1202316617 Jun 13 02:16:21 PM PDT 24 Jun 13 02:16:26 PM PDT 24 383212902 ps
T373 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3919001579 Jun 13 02:16:39 PM PDT 24 Jun 13 02:16:45 PM PDT 24 510595153 ps
T374 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.838497219 Jun 13 02:16:44 PM PDT 24 Jun 13 02:16:55 PM PDT 24 1375656357 ps
T375 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1149176733 Jun 13 02:16:53 PM PDT 24 Jun 13 02:17:03 PM PDT 24 572099464 ps
T376 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2010430669 Jun 13 02:16:49 PM PDT 24 Jun 13 02:16:58 PM PDT 24 445061519 ps
T377 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2376158808 Jun 13 02:16:37 PM PDT 24 Jun 13 02:16:45 PM PDT 24 409805407 ps
T378 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3104710509 Jun 13 02:16:31 PM PDT 24 Jun 13 02:16:42 PM PDT 24 2075017400 ps
T379 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1474527348 Jun 13 02:16:34 PM PDT 24 Jun 13 02:16:39 PM PDT 24 540826414 ps
T380 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3106358475 Jun 13 02:16:31 PM PDT 24 Jun 13 02:16:37 PM PDT 24 389820874 ps
T381 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.370101876 Jun 13 02:16:49 PM PDT 24 Jun 13 02:16:57 PM PDT 24 1183917316 ps
T382 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1233550489 Jun 13 02:16:32 PM PDT 24 Jun 13 02:16:37 PM PDT 24 426685441 ps
T383 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3163995061 Jun 13 02:16:36 PM PDT 24 Jun 13 02:16:50 PM PDT 24 4352411421 ps
T384 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1723327077 Jun 13 02:16:49 PM PDT 24 Jun 13 02:16:59 PM PDT 24 485027147 ps
T67 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3647615676 Jun 13 02:16:27 PM PDT 24 Jun 13 02:16:32 PM PDT 24 575226391 ps
T385 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.801942157 Jun 13 02:16:44 PM PDT 24 Jun 13 02:16:53 PM PDT 24 4621336827 ps
T386 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2612364693 Jun 13 02:16:46 PM PDT 24 Jun 13 02:17:00 PM PDT 24 4625053158 ps
T387 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3946437147 Jun 13 02:16:27 PM PDT 24 Jun 13 02:16:33 PM PDT 24 1257627429 ps
T388 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1886591408 Jun 13 02:16:31 PM PDT 24 Jun 13 02:16:38 PM PDT 24 1089505918 ps
T389 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1073135571 Jun 13 02:17:01 PM PDT 24 Jun 13 02:17:08 PM PDT 24 456059973 ps
T390 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2697303424 Jun 13 02:16:34 PM PDT 24 Jun 13 02:16:40 PM PDT 24 403165517 ps
T391 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1527463714 Jun 13 02:16:55 PM PDT 24 Jun 13 02:17:04 PM PDT 24 338055786 ps
T392 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4120400928 Jun 13 02:16:46 PM PDT 24 Jun 13 02:16:54 PM PDT 24 339147713 ps
T393 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2581766873 Jun 13 02:16:25 PM PDT 24 Jun 13 02:16:31 PM PDT 24 503142890 ps
T394 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2647197156 Jun 13 02:16:36 PM PDT 24 Jun 13 02:16:43 PM PDT 24 474253957 ps
T395 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3478047779 Jun 13 02:16:25 PM PDT 24 Jun 13 02:16:43 PM PDT 24 8512153087 ps
T396 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3294110601 Jun 13 02:16:53 PM PDT 24 Jun 13 02:17:00 PM PDT 24 451829341 ps
T397 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3434038214 Jun 13 02:16:37 PM PDT 24 Jun 13 02:16:48 PM PDT 24 4088416064 ps
T68 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.828826952 Jun 13 02:16:19 PM PDT 24 Jun 13 02:16:24 PM PDT 24 550390368 ps
T398 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2552135951 Jun 13 02:17:06 PM PDT 24 Jun 13 02:17:13 PM PDT 24 479341737 ps
T399 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4256669783 Jun 13 02:16:43 PM PDT 24 Jun 13 02:16:50 PM PDT 24 397351983 ps
T400 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4188083147 Jun 13 02:16:44 PM PDT 24 Jun 13 02:16:54 PM PDT 24 410454413 ps
T401 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3874763832 Jun 13 02:16:30 PM PDT 24 Jun 13 02:16:36 PM PDT 24 775223134 ps
T402 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1252225662 Jun 13 02:16:47 PM PDT 24 Jun 13 02:16:55 PM PDT 24 885836304 ps
T403 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.955358160 Jun 13 02:16:37 PM PDT 24 Jun 13 02:17:01 PM PDT 24 14052134014 ps
T404 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1403104599 Jun 13 02:16:55 PM PDT 24 Jun 13 02:17:04 PM PDT 24 359616095 ps
T405 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3160559890 Jun 13 02:17:07 PM PDT 24 Jun 13 02:17:14 PM PDT 24 436890697 ps
T406 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1564906135 Jun 13 02:17:06 PM PDT 24 Jun 13 02:17:13 PM PDT 24 305055950 ps
T407 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.89385009 Jun 13 02:16:26 PM PDT 24 Jun 13 02:16:31 PM PDT 24 438562369 ps
T408 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1487502178 Jun 13 02:17:03 PM PDT 24 Jun 13 02:17:10 PM PDT 24 311618671 ps
T409 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.698023139 Jun 13 02:17:06 PM PDT 24 Jun 13 02:17:16 PM PDT 24 2348932630 ps
T410 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1132541363 Jun 13 02:16:29 PM PDT 24 Jun 13 02:16:37 PM PDT 24 1130067673 ps
T62 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1658260964 Jun 13 02:16:49 PM PDT 24 Jun 13 02:16:57 PM PDT 24 377852656 ps
T411 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3464084820 Jun 13 02:16:46 PM PDT 24 Jun 13 02:16:55 PM PDT 24 1173473955 ps
T412 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2155774131 Jun 13 02:16:41 PM PDT 24 Jun 13 02:16:48 PM PDT 24 461889233 ps
T413 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.359300385 Jun 13 02:16:35 PM PDT 24 Jun 13 02:16:40 PM PDT 24 4675410024 ps
T414 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1543214177 Jun 13 02:16:57 PM PDT 24 Jun 13 02:17:05 PM PDT 24 457377961 ps
T415 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1373151350 Jun 13 02:16:21 PM PDT 24 Jun 13 02:16:25 PM PDT 24 585532759 ps
T416 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1761545088 Jun 13 02:16:44 PM PDT 24 Jun 13 02:16:52 PM PDT 24 793016861 ps
T417 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1295229360 Jun 13 02:16:29 PM PDT 24 Jun 13 02:16:35 PM PDT 24 317582167 ps
T418 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1054183919 Jun 13 02:16:42 PM PDT 24 Jun 13 02:16:51 PM PDT 24 467708849 ps
T63 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2178639122 Jun 13 02:16:44 PM PDT 24 Jun 13 02:16:52 PM PDT 24 302270971 ps
T419 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2704793066 Jun 13 02:16:32 PM PDT 24 Jun 13 02:16:40 PM PDT 24 2738580168 ps
T420 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3852270833 Jun 13 02:16:19 PM PDT 24 Jun 13 02:16:23 PM PDT 24 1114313285 ps
T421 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.53810088 Jun 13 02:16:57 PM PDT 24 Jun 13 02:17:05 PM PDT 24 378421341 ps
T422 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.429384811 Jun 13 02:16:30 PM PDT 24 Jun 13 02:16:37 PM PDT 24 388257031 ps
T423 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4004639629 Jun 13 02:17:07 PM PDT 24 Jun 13 02:17:14 PM PDT 24 508361220 ps
T424 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.569541907 Jun 13 02:16:49 PM PDT 24 Jun 13 02:17:10 PM PDT 24 8030107525 ps

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1839580833
Short name T1
Test name
Test status
Simulation time 26038762066 ps
CPU time 194.42 seconds
Started Jun 13 02:07:04 PM PDT 24
Finished Jun 13 02:10:19 PM PDT 24
Peak memory 214664 kb
Host smart-5f067217-7cc4-4a30-87f1-42df96ee7701
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839580833 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1839580833
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3034222251
Short name T11
Test name
Test status
Simulation time 70599358271 ps
CPU time 283.74 seconds
Started Jun 13 02:06:56 PM PDT 24
Finished Jun 13 02:11:40 PM PDT 24
Peak memory 207388 kb
Host smart-c68fb546-278b-4c12-9ebb-6b73570aad52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034222251 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3034222251
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2773837368
Short name T10
Test name
Test status
Simulation time 111857969218 ps
CPU time 39.14 seconds
Started Jun 13 02:07:17 PM PDT 24
Finished Jun 13 02:07:57 PM PDT 24
Peak memory 193576 kb
Host smart-453ffcdd-3ed3-4343-80fe-22a05deb15cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773837368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2773837368
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1597475224
Short name T34
Test name
Test status
Simulation time 3822258748 ps
CPU time 5.88 seconds
Started Jun 13 02:16:20 PM PDT 24
Finished Jun 13 02:16:29 PM PDT 24
Peak memory 196032 kb
Host smart-eb48ba66-e2f9-42ec-a5c3-950b15c95f1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597475224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1597475224
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1140036715
Short name T52
Test name
Test status
Simulation time 45778541220 ps
CPU time 361.76 seconds
Started Jun 13 02:07:28 PM PDT 24
Finished Jun 13 02:13:32 PM PDT 24
Peak memory 207504 kb
Host smart-79982a77-380e-4fef-a5e4-5cdf5d73e239
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140036715 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1140036715
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1852216216
Short name T23
Test name
Test status
Simulation time 5783575953 ps
CPU time 9.75 seconds
Started Jun 13 02:07:39 PM PDT 24
Finished Jun 13 02:07:49 PM PDT 24
Peak memory 184980 kb
Host smart-8e59f354-e03e-4a4c-b5f8-f6394ff5ac90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852216216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1852216216
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2889148078
Short name T42
Test name
Test status
Simulation time 356051523683 ps
CPU time 774.02 seconds
Started Jun 13 02:07:02 PM PDT 24
Finished Jun 13 02:19:57 PM PDT 24
Peak memory 207872 kb
Host smart-4e1f4196-6cce-48df-8d6d-7ee11ec14e99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889148078 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2889148078
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.4073225987
Short name T87
Test name
Test status
Simulation time 37554336302 ps
CPU time 275.19 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:12:06 PM PDT 24
Peak memory 207348 kb
Host smart-b1b54929-ca14-4785-bcb9-c1c1da13f4ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073225987 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.4073225987
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3181781159
Short name T79
Test name
Test status
Simulation time 80157278533 ps
CPU time 665.45 seconds
Started Jun 13 02:07:53 PM PDT 24
Finished Jun 13 02:19:00 PM PDT 24
Peak memory 215552 kb
Host smart-7de5a79d-c79e-4ebd-8766-6357b5386b08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181781159 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3181781159
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2002481558
Short name T105
Test name
Test status
Simulation time 64870947492 ps
CPU time 85.72 seconds
Started Jun 13 02:08:07 PM PDT 24
Finished Jun 13 02:09:35 PM PDT 24
Peak memory 193668 kb
Host smart-e83e15fb-30ae-45fa-bf41-13966dffd752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002481558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2002481558
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2491094850
Short name T92
Test name
Test status
Simulation time 85372915605 ps
CPU time 349.77 seconds
Started Jun 13 02:07:39 PM PDT 24
Finished Jun 13 02:13:31 PM PDT 24
Peak memory 210736 kb
Host smart-40a4754f-74a1-42c2-97a3-e195b249abe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491094850 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2491094850
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2438939803
Short name T19
Test name
Test status
Simulation time 7874018176 ps
CPU time 12.96 seconds
Started Jun 13 02:06:57 PM PDT 24
Finished Jun 13 02:07:11 PM PDT 24
Peak memory 216488 kb
Host smart-1ac21462-dab2-4c8b-bd17-9789ab012554
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438939803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2438939803
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.119195491
Short name T114
Test name
Test status
Simulation time 320229645023 ps
CPU time 175.32 seconds
Started Jun 13 02:07:09 PM PDT 24
Finished Jun 13 02:10:06 PM PDT 24
Peak memory 193472 kb
Host smart-77b0abd8-f176-4cc5-8b80-eba04b2b5fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119195491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.119195491
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2704761811
Short name T140
Test name
Test status
Simulation time 19508358766 ps
CPU time 196.31 seconds
Started Jun 13 02:07:33 PM PDT 24
Finished Jun 13 02:10:52 PM PDT 24
Peak memory 207368 kb
Host smart-c95bc99c-39b6-4c83-b760-858a95c1d9c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704761811 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2704761811
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1637190997
Short name T89
Test name
Test status
Simulation time 601237074968 ps
CPU time 838.74 seconds
Started Jun 13 02:07:33 PM PDT 24
Finished Jun 13 02:21:34 PM PDT 24
Peak memory 215524 kb
Host smart-b008c113-6be8-42f3-b5d1-105b543937f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637190997 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1637190997
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3789979518
Short name T54
Test name
Test status
Simulation time 101438874814 ps
CPU time 702.28 seconds
Started Jun 13 02:07:47 PM PDT 24
Finished Jun 13 02:19:31 PM PDT 24
Peak memory 205936 kb
Host smart-74e177dc-2dd3-4e58-ae47-01d54790c7f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789979518 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3789979518
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3073276869
Short name T5
Test name
Test status
Simulation time 138526441380 ps
CPU time 43.32 seconds
Started Jun 13 02:07:48 PM PDT 24
Finished Jun 13 02:08:32 PM PDT 24
Peak memory 192456 kb
Host smart-13dc3c97-ef1f-4944-b7f5-523ed138c743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073276869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3073276869
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1857288005
Short name T83
Test name
Test status
Simulation time 122507027232 ps
CPU time 165.88 seconds
Started Jun 13 02:07:22 PM PDT 24
Finished Jun 13 02:10:10 PM PDT 24
Peak memory 208852 kb
Host smart-53a27608-4c4f-4a88-b316-74a15b97fbd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857288005 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1857288005
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.550828119
Short name T126
Test name
Test status
Simulation time 13978121456 ps
CPU time 6.2 seconds
Started Jun 13 02:07:00 PM PDT 24
Finished Jun 13 02:07:07 PM PDT 24
Peak memory 193188 kb
Host smart-6e102bc7-3fec-48b9-be32-dee8d025ed76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550828119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.550828119
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3100517030
Short name T103
Test name
Test status
Simulation time 178997041088 ps
CPU time 184.65 seconds
Started Jun 13 02:07:46 PM PDT 24
Finished Jun 13 02:10:53 PM PDT 24
Peak memory 208728 kb
Host smart-484fcea9-4757-441c-a673-024af243e1de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100517030 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3100517030
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1175084726
Short name T90
Test name
Test status
Simulation time 81114469378 ps
CPU time 696.3 seconds
Started Jun 13 02:08:05 PM PDT 24
Finished Jun 13 02:19:43 PM PDT 24
Peak memory 214360 kb
Host smart-3f52f797-d94a-4ef4-857f-e59e98ae7271
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175084726 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1175084726
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1386822324
Short name T147
Test name
Test status
Simulation time 86333632065 ps
CPU time 175.72 seconds
Started Jun 13 02:07:05 PM PDT 24
Finished Jun 13 02:10:02 PM PDT 24
Peak memory 200388 kb
Host smart-13bd211b-bd3e-4502-8c21-49f04abb1a90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386822324 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1386822324
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.793714845
Short name T80
Test name
Test status
Simulation time 304930416281 ps
CPU time 766.26 seconds
Started Jun 13 02:07:08 PM PDT 24
Finished Jun 13 02:19:55 PM PDT 24
Peak memory 207928 kb
Host smart-5533de09-717a-4d48-8161-122d6c3024a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793714845 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.793714845
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1133669454
Short name T41
Test name
Test status
Simulation time 49554784331 ps
CPU time 281.59 seconds
Started Jun 13 02:07:39 PM PDT 24
Finished Jun 13 02:12:21 PM PDT 24
Peak memory 207524 kb
Host smart-888b5c2a-13a8-4084-b14e-7f7b9fa99afd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133669454 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1133669454
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2378872087
Short name T124
Test name
Test status
Simulation time 4300651798 ps
CPU time 7.1 seconds
Started Jun 13 02:08:06 PM PDT 24
Finished Jun 13 02:08:14 PM PDT 24
Peak memory 192972 kb
Host smart-31968fb0-8e1f-4e4f-9ed7-28ea5c81b8ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378872087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2378872087
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2833447979
Short name T129
Test name
Test status
Simulation time 140309950463 ps
CPU time 58.04 seconds
Started Jun 13 02:07:20 PM PDT 24
Finished Jun 13 02:08:19 PM PDT 24
Peak memory 198732 kb
Host smart-9a30e211-a935-4b12-a385-770eb7441988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833447979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2833447979
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1070471503
Short name T118
Test name
Test status
Simulation time 53841937215 ps
CPU time 372.48 seconds
Started Jun 13 02:08:11 PM PDT 24
Finished Jun 13 02:14:24 PM PDT 24
Peak memory 200796 kb
Host smart-7960c380-e967-4bc2-9837-64843140317d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070471503 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1070471503
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2209035228
Short name T115
Test name
Test status
Simulation time 90022464235 ps
CPU time 464.58 seconds
Started Jun 13 02:07:27 PM PDT 24
Finished Jun 13 02:15:14 PM PDT 24
Peak memory 204628 kb
Host smart-352a9b22-a1f6-4423-929d-8219e50f4522
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209035228 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2209035228
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2231517831
Short name T58
Test name
Test status
Simulation time 473951339 ps
CPU time 0.73 seconds
Started Jun 13 02:16:43 PM PDT 24
Finished Jun 13 02:16:50 PM PDT 24
Peak memory 192764 kb
Host smart-1247a4bd-46b0-4327-b0d4-57008b82df55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231517831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2231517831
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2341819179
Short name T130
Test name
Test status
Simulation time 30855122656 ps
CPU time 65.16 seconds
Started Jun 13 02:07:35 PM PDT 24
Finished Jun 13 02:08:42 PM PDT 24
Peak memory 207364 kb
Host smart-cf48e744-a57c-4184-95cb-bbae43e5185e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341819179 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2341819179
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3155504423
Short name T146
Test name
Test status
Simulation time 178555940103 ps
CPU time 258.43 seconds
Started Jun 13 02:07:58 PM PDT 24
Finished Jun 13 02:12:18 PM PDT 24
Peak memory 198804 kb
Host smart-b9ea2e89-d027-42c5-b6ff-5e5a26fb25d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155504423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3155504423
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2963505274
Short name T116
Test name
Test status
Simulation time 88616809015 ps
CPU time 372.36 seconds
Started Jun 13 02:07:58 PM PDT 24
Finished Jun 13 02:14:12 PM PDT 24
Peak memory 202868 kb
Host smart-eaec5397-131f-44a5-8965-0fe6a8ea85db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963505274 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2963505274
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.75027270
Short name T127
Test name
Test status
Simulation time 33510293042 ps
CPU time 251.15 seconds
Started Jun 13 02:07:16 PM PDT 24
Finished Jun 13 02:11:28 PM PDT 24
Peak memory 214656 kb
Host smart-a6f2c20c-fbe9-4fb9-9ea8-f56f71e3980c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75027270 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.75027270
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3565400274
Short name T149
Test name
Test status
Simulation time 466123384226 ps
CPU time 330.72 seconds
Started Jun 13 02:07:21 PM PDT 24
Finished Jun 13 02:12:53 PM PDT 24
Peak memory 184884 kb
Host smart-f340bfb0-5f01-42a9-afdd-9a736eb3ec05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565400274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3565400274
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2100919399
Short name T141
Test name
Test status
Simulation time 118481306572 ps
CPU time 168.47 seconds
Started Jun 13 02:07:30 PM PDT 24
Finished Jun 13 02:10:20 PM PDT 24
Peak memory 185284 kb
Host smart-2aa3f95d-a4a4-40fb-8bb4-babb7f36d1de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100919399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2100919399
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.77686952
Short name T108
Test name
Test status
Simulation time 164404253756 ps
CPU time 220.72 seconds
Started Jun 13 02:07:04 PM PDT 24
Finished Jun 13 02:10:46 PM PDT 24
Peak memory 198812 kb
Host smart-e51392e6-d6bb-4a55-a3f2-82badbc9cfb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77686952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all
.77686952
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.732259342
Short name T95
Test name
Test status
Simulation time 158058889687 ps
CPU time 303.86 seconds
Started Jun 13 02:07:22 PM PDT 24
Finished Jun 13 02:12:27 PM PDT 24
Peak memory 201888 kb
Host smart-fe533ed6-45a2-41ad-8837-2b877da2fca0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732259342 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.732259342
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3784063541
Short name T27
Test name
Test status
Simulation time 113787810719 ps
CPU time 204.38 seconds
Started Jun 13 02:07:36 PM PDT 24
Finished Jun 13 02:11:03 PM PDT 24
Peak memory 200900 kb
Host smart-c6a1ffcb-85e2-47ff-a2de-4bb6c0306ae8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784063541 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3784063541
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.951461316
Short name T155
Test name
Test status
Simulation time 605969938284 ps
CPU time 1340.13 seconds
Started Jun 13 02:07:35 PM PDT 24
Finished Jun 13 02:29:58 PM PDT 24
Peak memory 215588 kb
Host smart-5d323ab0-0c58-4998-a636-8c10ddcbd063
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951461316 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.951461316
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1887331877
Short name T101
Test name
Test status
Simulation time 16244213246 ps
CPU time 5.57 seconds
Started Jun 13 02:07:35 PM PDT 24
Finished Jun 13 02:07:43 PM PDT 24
Peak memory 192456 kb
Host smart-a0d6c3b6-45f8-4ca0-84ac-b7476b06401a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887331877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1887331877
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2969600551
Short name T106
Test name
Test status
Simulation time 181237764802 ps
CPU time 60.33 seconds
Started Jun 13 02:07:33 PM PDT 24
Finished Jun 13 02:08:36 PM PDT 24
Peak memory 198844 kb
Host smart-bc86cd3a-5f94-42fe-8472-3374a354f8d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969600551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2969600551
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.4274505028
Short name T93
Test name
Test status
Simulation time 42099214973 ps
CPU time 68.29 seconds
Started Jun 13 02:08:01 PM PDT 24
Finished Jun 13 02:09:11 PM PDT 24
Peak memory 193564 kb
Host smart-cbe0d00f-01e0-48f4-9fb2-1f51e0423970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274505028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.4274505028
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3738640289
Short name T88
Test name
Test status
Simulation time 41752716864 ps
CPU time 310.02 seconds
Started Jun 13 02:07:22 PM PDT 24
Finished Jun 13 02:12:34 PM PDT 24
Peak memory 207396 kb
Host smart-e76241c9-12ba-4616-9d23-ea36c00200ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738640289 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3738640289
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1018245752
Short name T143
Test name
Test status
Simulation time 89680768802 ps
CPU time 51.72 seconds
Started Jun 13 02:07:04 PM PDT 24
Finished Jun 13 02:07:57 PM PDT 24
Peak memory 192412 kb
Host smart-749206b3-54bc-4003-9712-5e84e416f59e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018245752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1018245752
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1870653980
Short name T145
Test name
Test status
Simulation time 75892072388 ps
CPU time 105.26 seconds
Started Jun 13 02:07:53 PM PDT 24
Finished Jun 13 02:09:41 PM PDT 24
Peak memory 192428 kb
Host smart-22919a6d-8aa5-40a5-a1ef-3405063ea7de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870653980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1870653980
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1808477819
Short name T25
Test name
Test status
Simulation time 338760763811 ps
CPU time 160.27 seconds
Started Jun 13 02:07:09 PM PDT 24
Finished Jun 13 02:09:51 PM PDT 24
Peak memory 207300 kb
Host smart-34daf695-a43f-49ce-ae7c-49a8feb92ffc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808477819 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1808477819
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2363331445
Short name T139
Test name
Test status
Simulation time 221588413806 ps
CPU time 207.11 seconds
Started Jun 13 02:07:14 PM PDT 24
Finished Jun 13 02:10:42 PM PDT 24
Peak memory 192524 kb
Host smart-f2746682-68dc-43fb-ab5c-2af6bf6238d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363331445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2363331445
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3719763156
Short name T82
Test name
Test status
Simulation time 278025567750 ps
CPU time 445.55 seconds
Started Jun 13 02:06:57 PM PDT 24
Finished Jun 13 02:14:23 PM PDT 24
Peak memory 207372 kb
Host smart-48561d4d-9209-448f-a810-6d6d6c18185a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719763156 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3719763156
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1579841266
Short name T121
Test name
Test status
Simulation time 37755378990 ps
CPU time 280.38 seconds
Started Jun 13 02:07:11 PM PDT 24
Finished Jun 13 02:11:52 PM PDT 24
Peak memory 199304 kb
Host smart-efcdba78-99e2-4ca8-b3f1-bb26b584cc4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579841266 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1579841266
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3895451157
Short name T102
Test name
Test status
Simulation time 142671139386 ps
CPU time 40.38 seconds
Started Jun 13 02:07:40 PM PDT 24
Finished Jun 13 02:08:21 PM PDT 24
Peak memory 198792 kb
Host smart-4ded032f-0ead-4924-a9fe-3975c8d2a792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895451157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3895451157
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.433576412
Short name T109
Test name
Test status
Simulation time 212112727403 ps
CPU time 159.74 seconds
Started Jun 13 02:07:49 PM PDT 24
Finished Jun 13 02:10:30 PM PDT 24
Peak memory 193020 kb
Host smart-a29a1e84-24a1-403b-93df-3d874acf1be4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433576412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.433576412
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3453476042
Short name T120
Test name
Test status
Simulation time 84374478323 ps
CPU time 67.91 seconds
Started Jun 13 02:07:47 PM PDT 24
Finished Jun 13 02:08:56 PM PDT 24
Peak memory 198832 kb
Host smart-9a8eff3a-a8d2-49d7-87bd-58b37f358809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453476042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3453476042
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2040346279
Short name T142
Test name
Test status
Simulation time 456417638378 ps
CPU time 324.71 seconds
Started Jun 13 02:07:35 PM PDT 24
Finished Jun 13 02:13:01 PM PDT 24
Peak memory 193208 kb
Host smart-a90c1b39-ca53-44fc-9568-ce862d74aef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040346279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2040346279
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.4065619293
Short name T20
Test name
Test status
Simulation time 737839189042 ps
CPU time 865.5 seconds
Started Jun 13 02:07:08 PM PDT 24
Finished Jun 13 02:21:35 PM PDT 24
Peak memory 198976 kb
Host smart-f7d875f6-d6f8-4e83-b572-6d28d18e4265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065619293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.4065619293
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1188888558
Short name T158
Test name
Test status
Simulation time 53898039414 ps
CPU time 606.3 seconds
Started Jun 13 02:07:09 PM PDT 24
Finished Jun 13 02:17:17 PM PDT 24
Peak memory 203636 kb
Host smart-c5057fef-8be5-4781-9fbb-7a58e392914e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188888558 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1188888558
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2563054850
Short name T53
Test name
Test status
Simulation time 106161311526 ps
CPU time 543.8 seconds
Started Jun 13 02:07:53 PM PDT 24
Finished Jun 13 02:16:59 PM PDT 24
Peak memory 201544 kb
Host smart-49babade-3f31-479a-8389-4631e7641875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563054850 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2563054850
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3224835531
Short name T81
Test name
Test status
Simulation time 92392706921 ps
CPU time 298.6 seconds
Started Jun 13 02:07:03 PM PDT 24
Finished Jun 13 02:12:02 PM PDT 24
Peak memory 209116 kb
Host smart-c85857f3-b085-439e-a1b3-a2cec17f6738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224835531 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3224835531
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2949178030
Short name T85
Test name
Test status
Simulation time 41393024783 ps
CPU time 155.09 seconds
Started Jun 13 02:07:55 PM PDT 24
Finished Jun 13 02:10:32 PM PDT 24
Peak memory 215504 kb
Host smart-cdbf71da-a99e-45ca-8072-c1b62cf1bf5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949178030 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2949178030
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.194031421
Short name T161
Test name
Test status
Simulation time 118750031567 ps
CPU time 157.09 seconds
Started Jun 13 02:06:57 PM PDT 24
Finished Jun 13 02:09:35 PM PDT 24
Peak memory 192452 kb
Host smart-92cd3da6-b67d-40c8-ada5-620f85fe8eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194031421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.194031421
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.22550656
Short name T112
Test name
Test status
Simulation time 252653552129 ps
CPU time 325.27 seconds
Started Jun 13 02:07:31 PM PDT 24
Finished Jun 13 02:12:59 PM PDT 24
Peak memory 193200 kb
Host smart-2d04b015-6865-440a-8d4b-e8c2aed73c2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22550656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_al
l.22550656
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2942667868
Short name T150
Test name
Test status
Simulation time 224851879598 ps
CPU time 75.98 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:08:47 PM PDT 24
Peak memory 192436 kb
Host smart-9881df5f-c627-43ae-8a35-7ae5da321511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942667868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2942667868
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3918400809
Short name T132
Test name
Test status
Simulation time 45477766216 ps
CPU time 376.68 seconds
Started Jun 13 02:07:03 PM PDT 24
Finished Jun 13 02:13:20 PM PDT 24
Peak memory 207404 kb
Host smart-d0b657e7-2686-4ce7-90e9-47e075442be6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918400809 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3918400809
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2490746138
Short name T134
Test name
Test status
Simulation time 140417284959 ps
CPU time 80.47 seconds
Started Jun 13 02:07:27 PM PDT 24
Finished Jun 13 02:08:49 PM PDT 24
Peak memory 198948 kb
Host smart-b59affdc-4ae7-4567-ad39-1f0e2a027230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490746138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2490746138
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.241404600
Short name T135
Test name
Test status
Simulation time 145076059582 ps
CPU time 41.86 seconds
Started Jun 13 02:07:53 PM PDT 24
Finished Jun 13 02:08:37 PM PDT 24
Peak memory 193460 kb
Host smart-ae5a2ad1-acc6-4d9b-909b-9fd5bc216c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241404600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.241404600
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.944082907
Short name T136
Test name
Test status
Simulation time 47948964122 ps
CPU time 546.43 seconds
Started Jun 13 02:07:51 PM PDT 24
Finished Jun 13 02:16:58 PM PDT 24
Peak memory 210552 kb
Host smart-22ca97a4-6bc7-4f5c-a511-d6c9155a38d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944082907 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.944082907
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2452472477
Short name T125
Test name
Test status
Simulation time 491200132 ps
CPU time 1.27 seconds
Started Jun 13 02:07:05 PM PDT 24
Finished Jun 13 02:07:08 PM PDT 24
Peak memory 197140 kb
Host smart-047f8c09-1c65-4213-8729-0b79302d493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452472477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2452472477
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1927810601
Short name T46
Test name
Test status
Simulation time 263312210848 ps
CPU time 198.19 seconds
Started Jun 13 02:07:35 PM PDT 24
Finished Jun 13 02:10:55 PM PDT 24
Peak memory 192504 kb
Host smart-8e96de38-939f-44c2-921e-c2e3932faaa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927810601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1927810601
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.239272413
Short name T138
Test name
Test status
Simulation time 3924249323 ps
CPU time 3.74 seconds
Started Jun 13 02:07:49 PM PDT 24
Finished Jun 13 02:07:54 PM PDT 24
Peak memory 192480 kb
Host smart-19df8ba5-9d13-46d1-b8af-02b692cc653b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239272413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.239272413
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1441274479
Short name T29
Test name
Test status
Simulation time 38176035391 ps
CPU time 273.74 seconds
Started Jun 13 02:07:52 PM PDT 24
Finished Jun 13 02:12:27 PM PDT 24
Peak memory 199160 kb
Host smart-766aca02-0bff-4471-9402-e908ab713ee4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441274479 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1441274479
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1406733474
Short name T91
Test name
Test status
Simulation time 104271108665 ps
CPU time 262.9 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:11:53 PM PDT 24
Peak memory 210000 kb
Host smart-29caebb3-13d8-42d8-8b8b-1e0002e8af64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406733474 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1406733474
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.60963942
Short name T2
Test name
Test status
Simulation time 610365173 ps
CPU time 0.78 seconds
Started Jun 13 02:07:30 PM PDT 24
Finished Jun 13 02:07:33 PM PDT 24
Peak memory 197116 kb
Host smart-f58a5eef-adef-41aa-b228-2d5218c9a935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60963942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.60963942
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1968640356
Short name T96
Test name
Test status
Simulation time 369929536 ps
CPU time 0.73 seconds
Started Jun 13 02:07:34 PM PDT 24
Finished Jun 13 02:07:37 PM PDT 24
Peak memory 197120 kb
Host smart-3e2d7b4b-0880-4355-83a0-988728beeb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968640356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1968640356
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3685766735
Short name T48
Test name
Test status
Simulation time 6566494078 ps
CPU time 2.13 seconds
Started Jun 13 02:07:33 PM PDT 24
Finished Jun 13 02:07:38 PM PDT 24
Peak memory 198760 kb
Host smart-a0cb7f93-7729-4055-80a0-ae14d1c484b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685766735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3685766735
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.557859321
Short name T144
Test name
Test status
Simulation time 97903438260 ps
CPU time 78.28 seconds
Started Jun 13 02:07:12 PM PDT 24
Finished Jun 13 02:08:31 PM PDT 24
Peak memory 192928 kb
Host smart-f475b311-a4ee-4493-bb9d-7c567fdae9c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557859321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.557859321
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3502308269
Short name T183
Test name
Test status
Simulation time 92099669714 ps
CPU time 256.14 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:11:48 PM PDT 24
Peak memory 209896 kb
Host smart-4c083597-7a18-44dd-a313-773ce27009ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502308269 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3502308269
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.551675929
Short name T133
Test name
Test status
Simulation time 118965555328 ps
CPU time 78.46 seconds
Started Jun 13 02:07:27 PM PDT 24
Finished Jun 13 02:08:47 PM PDT 24
Peak memory 193576 kb
Host smart-44d3b6ad-91ef-4454-9822-d61b07255991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551675929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.551675929
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2683905729
Short name T123
Test name
Test status
Simulation time 204671332893 ps
CPU time 70.52 seconds
Started Jun 13 02:07:36 PM PDT 24
Finished Jun 13 02:08:49 PM PDT 24
Peak memory 193548 kb
Host smart-2514f1e3-51ed-406b-9676-d0fc9ed2e738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683905729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2683905729
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2528268807
Short name T100
Test name
Test status
Simulation time 540211258 ps
CPU time 1.42 seconds
Started Jun 13 02:07:53 PM PDT 24
Finished Jun 13 02:07:55 PM PDT 24
Peak memory 197128 kb
Host smart-1947e151-6ec0-4207-8c61-faedb7225725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528268807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2528268807
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2501430276
Short name T152
Test name
Test status
Simulation time 378858085 ps
CPU time 0.86 seconds
Started Jun 13 02:07:04 PM PDT 24
Finished Jun 13 02:07:06 PM PDT 24
Peak memory 197128 kb
Host smart-b0ef74c5-68cf-458b-9ad2-38319fe709c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501430276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2501430276
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1367394127
Short name T137
Test name
Test status
Simulation time 497714334 ps
CPU time 0.95 seconds
Started Jun 13 02:06:58 PM PDT 24
Finished Jun 13 02:06:59 PM PDT 24
Peak memory 197160 kb
Host smart-cd6012ae-f6f9-4edb-b213-cb70f19ff33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367394127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1367394127
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.4147572337
Short name T111
Test name
Test status
Simulation time 489888132 ps
CPU time 1.33 seconds
Started Jun 13 02:07:22 PM PDT 24
Finished Jun 13 02:07:25 PM PDT 24
Peak memory 197096 kb
Host smart-15369d1f-1860-42c3-9efe-9fff01e849f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147572337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.4147572337
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.753253798
Short name T26
Test name
Test status
Simulation time 458504486654 ps
CPU time 88.93 seconds
Started Jun 13 02:07:24 PM PDT 24
Finished Jun 13 02:08:54 PM PDT 24
Peak memory 192428 kb
Host smart-83a098c5-e415-498b-a6b4-62b10fc81381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753253798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.753253798
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3460862881
Short name T122
Test name
Test status
Simulation time 565810684 ps
CPU time 0.76 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:07:32 PM PDT 24
Peak memory 197148 kb
Host smart-fec5398b-a979-4d3c-b458-f9c374820975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460862881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3460862881
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2668150877
Short name T113
Test name
Test status
Simulation time 530860256 ps
CPU time 0.65 seconds
Started Jun 13 02:07:32 PM PDT 24
Finished Jun 13 02:07:35 PM PDT 24
Peak memory 197112 kb
Host smart-914576a0-f26b-4bfa-a780-0ae8551f7209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668150877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2668150877
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.4033420437
Short name T153
Test name
Test status
Simulation time 378411755 ps
CPU time 0.87 seconds
Started Jun 13 02:07:33 PM PDT 24
Finished Jun 13 02:07:37 PM PDT 24
Peak memory 197152 kb
Host smart-7f5cff2e-1bfe-4f28-84ce-d3005e606996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033420437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.4033420437
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1309964064
Short name T148
Test name
Test status
Simulation time 394565835 ps
CPU time 1.14 seconds
Started Jun 13 02:07:32 PM PDT 24
Finished Jun 13 02:07:36 PM PDT 24
Peak memory 197224 kb
Host smart-9e7b0eda-9334-4435-a142-183bba7e14de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309964064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1309964064
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2451299941
Short name T154
Test name
Test status
Simulation time 133595228713 ps
CPU time 49.79 seconds
Started Jun 13 02:07:55 PM PDT 24
Finished Jun 13 02:08:46 PM PDT 24
Peak memory 192428 kb
Host smart-ab0f97ee-6d06-43d5-8d4f-4e56900337c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451299941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2451299941
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3046734483
Short name T13
Test name
Test status
Simulation time 450866494 ps
CPU time 0.79 seconds
Started Jun 13 02:07:59 PM PDT 24
Finished Jun 13 02:08:01 PM PDT 24
Peak memory 197040 kb
Host smart-a504ecf8-ce4f-4730-89ac-d5ca0b0b0426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046734483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3046734483
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.901041202
Short name T16
Test name
Test status
Simulation time 64220259741 ps
CPU time 210.65 seconds
Started Jun 13 02:07:09 PM PDT 24
Finished Jun 13 02:10:41 PM PDT 24
Peak memory 207384 kb
Host smart-c3712a12-8eb6-4fd1-98b7-bb75838ae78e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901041202 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.901041202
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.321189368
Short name T117
Test name
Test status
Simulation time 591509291 ps
CPU time 1.06 seconds
Started Jun 13 02:07:17 PM PDT 24
Finished Jun 13 02:07:19 PM PDT 24
Peak memory 197248 kb
Host smart-f730dc71-ca23-4adb-9e1e-857e29a7341b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321189368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.321189368
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3347017631
Short name T163
Test name
Test status
Simulation time 181735941019 ps
CPU time 266.82 seconds
Started Jun 13 02:07:22 PM PDT 24
Finished Jun 13 02:11:50 PM PDT 24
Peak memory 193300 kb
Host smart-7d114378-24ab-4878-bb7c-483be0ac52e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347017631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3347017631
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1061815730
Short name T179
Test name
Test status
Simulation time 78205916982 ps
CPU time 10.2 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:07:41 PM PDT 24
Peak memory 193480 kb
Host smart-367e4c7e-c4b6-4dce-826b-f0d678d3e2ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061815730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1061815730
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.30847493
Short name T107
Test name
Test status
Simulation time 507140171 ps
CPU time 0.78 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:07:31 PM PDT 24
Peak memory 197136 kb
Host smart-d93024f1-7956-46aa-90a5-aea6bbd5d634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30847493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.30847493
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.418303071
Short name T49
Test name
Test status
Simulation time 177065862049 ps
CPU time 270.01 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:12:02 PM PDT 24
Peak memory 192416 kb
Host smart-ecb4ed41-5fca-48fc-8079-b801cd85397b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418303071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.418303071
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3065070009
Short name T84
Test name
Test status
Simulation time 56825792724 ps
CPU time 423 seconds
Started Jun 13 02:07:35 PM PDT 24
Finished Jun 13 02:14:40 PM PDT 24
Peak memory 207360 kb
Host smart-980e35e7-d792-4ebc-858b-f758f3dd8b6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065070009 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3065070009
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2025401483
Short name T24
Test name
Test status
Simulation time 485899316 ps
CPU time 0.77 seconds
Started Jun 13 02:07:40 PM PDT 24
Finished Jun 13 02:07:42 PM PDT 24
Peak memory 197124 kb
Host smart-a1f66e6f-a414-4ba2-94d8-e71540ff1637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025401483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2025401483
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.269974155
Short name T86
Test name
Test status
Simulation time 33300797677 ps
CPU time 248.01 seconds
Started Jun 13 02:07:59 PM PDT 24
Finished Jun 13 02:12:10 PM PDT 24
Peak memory 199168 kb
Host smart-f94697f2-8bb4-423e-bb3a-17fab85e2f32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269974155 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.269974155
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3439992727
Short name T178
Test name
Test status
Simulation time 36098609387 ps
CPU time 57.16 seconds
Started Jun 13 02:07:04 PM PDT 24
Finished Jun 13 02:08:03 PM PDT 24
Peak memory 193472 kb
Host smart-ff26461e-b323-4740-8922-2b3a673c9d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439992727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3439992727
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3840799491
Short name T176
Test name
Test status
Simulation time 47964472688 ps
CPU time 69.48 seconds
Started Jun 13 02:07:18 PM PDT 24
Finished Jun 13 02:08:28 PM PDT 24
Peak memory 198788 kb
Host smart-2ed45475-47d9-4b15-bfeb-5ac3b2fc173c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840799491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3840799491
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2844698878
Short name T119
Test name
Test status
Simulation time 400775993 ps
CPU time 1.23 seconds
Started Jun 13 02:07:21 PM PDT 24
Finished Jun 13 02:07:23 PM PDT 24
Peak memory 197116 kb
Host smart-a3ed87aa-c3e8-4982-9806-53b7d48d6c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844698878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2844698878
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1645866765
Short name T94
Test name
Test status
Simulation time 413002469 ps
CPU time 0.78 seconds
Started Jun 13 02:07:35 PM PDT 24
Finished Jun 13 02:07:38 PM PDT 24
Peak memory 197220 kb
Host smart-7e54bab5-8e72-4c18-a643-cb5fd7a39dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645866765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1645866765
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3738136278
Short name T184
Test name
Test status
Simulation time 176677396663 ps
CPU time 57.92 seconds
Started Jun 13 02:07:27 PM PDT 24
Finished Jun 13 02:08:27 PM PDT 24
Peak memory 192496 kb
Host smart-9c396315-2484-4dbc-8d3d-6886aca526ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738136278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3738136278
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.893897593
Short name T128
Test name
Test status
Simulation time 386840086 ps
CPU time 0.89 seconds
Started Jun 13 02:07:41 PM PDT 24
Finished Jun 13 02:07:44 PM PDT 24
Peak memory 197112 kb
Host smart-60fa1d61-dd27-4343-95c7-abd58dc6c125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893897593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.893897593
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1253704670
Short name T131
Test name
Test status
Simulation time 476480329 ps
CPU time 0.8 seconds
Started Jun 13 02:07:54 PM PDT 24
Finished Jun 13 02:07:57 PM PDT 24
Peak memory 197148 kb
Host smart-d1eb6574-e991-4f9c-b6f8-0d52911c1f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253704670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1253704670
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1250543830
Short name T151
Test name
Test status
Simulation time 66978776917 ps
CPU time 92.18 seconds
Started Jun 13 02:07:55 PM PDT 24
Finished Jun 13 02:09:30 PM PDT 24
Peak memory 198824 kb
Host smart-f80d862d-9094-42ea-923a-bd94265008f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250543830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1250543830
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.506502464
Short name T110
Test name
Test status
Simulation time 583071013 ps
CPU time 0.8 seconds
Started Jun 13 02:08:06 PM PDT 24
Finished Jun 13 02:08:08 PM PDT 24
Peak memory 197244 kb
Host smart-bca737f5-df58-40a9-a58d-b32413813bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506502464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.506502464
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.48605353
Short name T51
Test name
Test status
Simulation time 101380969576 ps
CPU time 161.04 seconds
Started Jun 13 02:07:04 PM PDT 24
Finished Jun 13 02:09:47 PM PDT 24
Peak memory 192388 kb
Host smart-45d3d470-ab2b-41ea-8125-d4ccaaa28712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48605353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all
.48605353
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.4005909802
Short name T164
Test name
Test status
Simulation time 98084727636 ps
CPU time 63.05 seconds
Started Jun 13 02:07:09 PM PDT 24
Finished Jun 13 02:08:14 PM PDT 24
Peak memory 192420 kb
Host smart-2e5e0b24-9cd1-47c8-9b84-efee1acb2d2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005909802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.4005909802
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3836202914
Short name T170
Test name
Test status
Simulation time 606914995 ps
CPU time 0.86 seconds
Started Jun 13 02:07:15 PM PDT 24
Finished Jun 13 02:07:17 PM PDT 24
Peak memory 197076 kb
Host smart-e0f45fe5-2b49-4a74-b87a-01152aabacc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836202914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3836202914
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3088867035
Short name T97
Test name
Test status
Simulation time 593697166 ps
CPU time 0.8 seconds
Started Jun 13 02:07:24 PM PDT 24
Finished Jun 13 02:07:26 PM PDT 24
Peak memory 197160 kb
Host smart-9a96fd14-d7d7-4eaf-a319-840157c1570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088867035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3088867035
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3297759254
Short name T165
Test name
Test status
Simulation time 392537266 ps
CPU time 0.74 seconds
Started Jun 13 02:07:27 PM PDT 24
Finished Jun 13 02:07:28 PM PDT 24
Peak memory 197164 kb
Host smart-581a200e-6e8e-4e85-bcd3-716ba2a69ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297759254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3297759254
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3468094647
Short name T30
Test name
Test status
Simulation time 70646338566 ps
CPU time 443.22 seconds
Started Jun 13 02:07:33 PM PDT 24
Finished Jun 13 02:14:59 PM PDT 24
Peak memory 208628 kb
Host smart-32758f25-7f53-4029-9492-d780be42a928
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468094647 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3468094647
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1992364469
Short name T185
Test name
Test status
Simulation time 422036365 ps
CPU time 0.93 seconds
Started Jun 13 02:07:48 PM PDT 24
Finished Jun 13 02:07:50 PM PDT 24
Peak memory 197196 kb
Host smart-78a00c1c-12a9-4d86-abc6-d47bdadfbb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992364469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1992364469
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3972285724
Short name T175
Test name
Test status
Simulation time 628834815 ps
CPU time 0.91 seconds
Started Jun 13 02:07:47 PM PDT 24
Finished Jun 13 02:07:49 PM PDT 24
Peak memory 197076 kb
Host smart-8d39713d-f755-4076-b945-2e5beaaeb1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972285724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3972285724
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2142286248
Short name T98
Test name
Test status
Simulation time 495754944 ps
CPU time 0.82 seconds
Started Jun 13 02:07:46 PM PDT 24
Finished Jun 13 02:07:48 PM PDT 24
Peak memory 197228 kb
Host smart-1bfd8daa-20c8-4e2c-9b09-b482cb036d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142286248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2142286248
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.815738265
Short name T31
Test name
Test status
Simulation time 528403873 ps
CPU time 1.02 seconds
Started Jun 13 02:08:03 PM PDT 24
Finished Jun 13 02:08:05 PM PDT 24
Peak memory 197124 kb
Host smart-f437a886-e288-41da-9376-d9d9aa1e0eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815738265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.815738265
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4028760331
Short name T191
Test name
Test status
Simulation time 7994720872 ps
CPU time 4.43 seconds
Started Jun 13 02:16:36 PM PDT 24
Finished Jun 13 02:16:46 PM PDT 24
Peak memory 197880 kb
Host smart-fd27ebee-70a8-4b88-b835-81e8a8eaed18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028760331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.4028760331
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3985668076
Short name T78
Test name
Test status
Simulation time 447155002 ps
CPU time 1.28 seconds
Started Jun 13 02:06:59 PM PDT 24
Finished Jun 13 02:07:01 PM PDT 24
Peak memory 197168 kb
Host smart-890275e0-2877-431c-a694-b30fee8f43d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985668076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3985668076
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1023275092
Short name T182
Test name
Test status
Simulation time 145384377727 ps
CPU time 24.42 seconds
Started Jun 13 02:07:10 PM PDT 24
Finished Jun 13 02:07:36 PM PDT 24
Peak memory 198832 kb
Host smart-45a4908d-e263-4e20-a7c8-4ab39d6d8195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023275092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1023275092
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.339184855
Short name T180
Test name
Test status
Simulation time 519674479 ps
CPU time 1.43 seconds
Started Jun 13 02:07:14 PM PDT 24
Finished Jun 13 02:07:17 PM PDT 24
Peak memory 197084 kb
Host smart-5547f230-515a-4eb4-a453-09c77c4d362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339184855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.339184855
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1513841426
Short name T174
Test name
Test status
Simulation time 505174403 ps
CPU time 0.79 seconds
Started Jun 13 02:06:57 PM PDT 24
Finished Jun 13 02:06:58 PM PDT 24
Peak memory 197084 kb
Host smart-04936681-67e4-43f1-9341-9587be323b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513841426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1513841426
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.712944065
Short name T14
Test name
Test status
Simulation time 415434964 ps
CPU time 0.65 seconds
Started Jun 13 02:07:27 PM PDT 24
Finished Jun 13 02:07:30 PM PDT 24
Peak memory 197124 kb
Host smart-d9fbbfdb-30b3-4f78-8df7-951f0a4eff8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712944065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.712944065
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.4012020289
Short name T157
Test name
Test status
Simulation time 16835586648 ps
CPU time 137.75 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:09:48 PM PDT 24
Peak memory 207328 kb
Host smart-1a271a9d-c17a-4a10-99ee-13c6e7eaf0f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012020289 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.4012020289
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.465019089
Short name T40
Test name
Test status
Simulation time 80884895242 ps
CPU time 241.39 seconds
Started Jun 13 02:07:30 PM PDT 24
Finished Jun 13 02:11:34 PM PDT 24
Peak memory 209096 kb
Host smart-472c14ca-3b5c-49d3-885d-946adee227c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465019089 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.465019089
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.4248419957
Short name T160
Test name
Test status
Simulation time 584906580 ps
CPU time 0.82 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:07:32 PM PDT 24
Peak memory 197180 kb
Host smart-2db593c9-0614-4a59-a8d1-2ad7ab4c847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248419957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.4248419957
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3308430833
Short name T167
Test name
Test status
Simulation time 122247624071 ps
CPU time 41.52 seconds
Started Jun 13 02:07:04 PM PDT 24
Finished Jun 13 02:07:46 PM PDT 24
Peak memory 192628 kb
Host smart-af9f577e-5090-4709-9966-c28987229d2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308430833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3308430833
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.4031132305
Short name T166
Test name
Test status
Simulation time 539198928 ps
CPU time 1.39 seconds
Started Jun 13 02:07:33 PM PDT 24
Finished Jun 13 02:07:37 PM PDT 24
Peak memory 197108 kb
Host smart-d7a537b5-7992-4799-a0d7-f68348029586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031132305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4031132305
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1293287270
Short name T181
Test name
Test status
Simulation time 577628682 ps
CPU time 1.48 seconds
Started Jun 13 02:07:33 PM PDT 24
Finished Jun 13 02:07:38 PM PDT 24
Peak memory 197108 kb
Host smart-0e3771df-c87d-43f8-a3ae-9cc6311cfab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293287270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1293287270
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1791458426
Short name T15
Test name
Test status
Simulation time 497144128 ps
CPU time 0.98 seconds
Started Jun 13 02:07:54 PM PDT 24
Finished Jun 13 02:07:57 PM PDT 24
Peak memory 197216 kb
Host smart-f09be6a2-ee13-40b7-8179-28cff619c69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791458426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1791458426
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.308753170
Short name T104
Test name
Test status
Simulation time 359836168 ps
CPU time 0.74 seconds
Started Jun 13 02:08:07 PM PDT 24
Finished Jun 13 02:08:10 PM PDT 24
Peak memory 197160 kb
Host smart-1d0efc9d-7984-4c96-833a-bf6dbc21df57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308753170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.308753170
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1822676072
Short name T156
Test name
Test status
Simulation time 506369252 ps
CPU time 1.22 seconds
Started Jun 13 02:07:03 PM PDT 24
Finished Jun 13 02:07:05 PM PDT 24
Peak memory 197072 kb
Host smart-24c3953c-0083-4e38-9c79-14d47e3f0601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822676072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1822676072
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.344552151
Short name T159
Test name
Test status
Simulation time 388334876 ps
CPU time 0.76 seconds
Started Jun 13 02:07:06 PM PDT 24
Finished Jun 13 02:07:08 PM PDT 24
Peak memory 197064 kb
Host smart-9c1cf167-6ca1-4ef3-9d24-b0d2b70cb419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344552151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.344552151
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2215244289
Short name T189
Test name
Test status
Simulation time 468248637 ps
CPU time 0.75 seconds
Started Jun 13 02:07:08 PM PDT 24
Finished Jun 13 02:07:10 PM PDT 24
Peak memory 197104 kb
Host smart-21ab964a-4eaf-4858-b5d9-686e19f42762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215244289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2215244289
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.860556
Short name T43
Test name
Test status
Simulation time 456531219 ps
CPU time 0.76 seconds
Started Jun 13 02:07:10 PM PDT 24
Finished Jun 13 02:07:12 PM PDT 24
Peak memory 197208 kb
Host smart-27daaab3-e39a-40de-8deb-9a04de2c962d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.860556
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3457724432
Short name T188
Test name
Test status
Simulation time 531399903 ps
CPU time 0.75 seconds
Started Jun 13 02:07:21 PM PDT 24
Finished Jun 13 02:07:23 PM PDT 24
Peak memory 197064 kb
Host smart-c4e9d705-94b8-4c78-bed0-6f86c6d8f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457724432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3457724432
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2545075691
Short name T168
Test name
Test status
Simulation time 275973581942 ps
CPU time 90.83 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:09:02 PM PDT 24
Peak memory 192428 kb
Host smart-175cb5e8-580b-44fc-b39d-a7125127eb7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545075691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2545075691
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2389129150
Short name T169
Test name
Test status
Simulation time 467512876 ps
CPU time 0.96 seconds
Started Jun 13 02:07:30 PM PDT 24
Finished Jun 13 02:07:33 PM PDT 24
Peak memory 197128 kb
Host smart-cd60ab1c-7d88-4ae1-85a6-adf7177afcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389129150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2389129150
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.29442402
Short name T99
Test name
Test status
Simulation time 591958115 ps
CPU time 1.13 seconds
Started Jun 13 02:07:06 PM PDT 24
Finished Jun 13 02:07:08 PM PDT 24
Peak memory 197256 kb
Host smart-f896696c-a18b-4c90-8150-976b4bcfc35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29442402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.29442402
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1187990560
Short name T171
Test name
Test status
Simulation time 382606061 ps
CPU time 1.12 seconds
Started Jun 13 02:07:10 PM PDT 24
Finished Jun 13 02:07:13 PM PDT 24
Peak memory 197132 kb
Host smart-077d6800-fc74-4f37-ac61-5915a0c608cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187990560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1187990560
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.828826952
Short name T68
Test name
Test status
Simulation time 550390368 ps
CPU time 1.39 seconds
Started Jun 13 02:16:19 PM PDT 24
Finished Jun 13 02:16:24 PM PDT 24
Peak memory 183584 kb
Host smart-9d9f7b33-f910-44a2-aebe-105d2cd688a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828826952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.828826952
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.829306262
Short name T59
Test name
Test status
Simulation time 12168943937 ps
CPU time 6.19 seconds
Started Jun 13 02:16:21 PM PDT 24
Finished Jun 13 02:16:31 PM PDT 24
Peak memory 196220 kb
Host smart-624ca806-18cb-4d99-9ad6-9794b4be903d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829306262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.829306262
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3852270833
Short name T420
Test name
Test status
Simulation time 1114313285 ps
CPU time 1.42 seconds
Started Jun 13 02:16:19 PM PDT 24
Finished Jun 13 02:16:23 PM PDT 24
Peak memory 192928 kb
Host smart-5748ee7e-482b-4cf4-88fc-2ca6960f911b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852270833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3852270833
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1202316617
Short name T372
Test name
Test status
Simulation time 383212902 ps
CPU time 1.15 seconds
Started Jun 13 02:16:21 PM PDT 24
Finished Jun 13 02:16:26 PM PDT 24
Peak memory 195680 kb
Host smart-902ec658-7994-497a-b2fc-6c1805dbab4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202316617 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1202316617
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1373151350
Short name T415
Test name
Test status
Simulation time 585532759 ps
CPU time 0.81 seconds
Started Jun 13 02:16:21 PM PDT 24
Finished Jun 13 02:16:25 PM PDT 24
Peak memory 192872 kb
Host smart-dd382063-e6be-4f71-aa5c-5dbfb6928fb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373151350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1373151350
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3626938569
Short name T313
Test name
Test status
Simulation time 459160489 ps
CPU time 0.74 seconds
Started Jun 13 02:16:22 PM PDT 24
Finished Jun 13 02:16:26 PM PDT 24
Peak memory 183360 kb
Host smart-c5b13894-1ac4-4a12-a5c4-7cfff8fae1f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626938569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3626938569
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3736134475
Short name T317
Test name
Test status
Simulation time 365184065 ps
CPU time 0.57 seconds
Started Jun 13 02:16:16 PM PDT 24
Finished Jun 13 02:16:18 PM PDT 24
Peak memory 183268 kb
Host smart-c8a551f9-dbf9-4dbb-9e3b-1dc7214aca21
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736134475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3736134475
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1884067923
Short name T364
Test name
Test status
Simulation time 436302604 ps
CPU time 0.71 seconds
Started Jun 13 02:16:18 PM PDT 24
Finished Jun 13 02:16:23 PM PDT 24
Peak memory 183336 kb
Host smart-680f4f8e-f559-4539-b551-44b35fb9a75c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884067923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1884067923
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1546692454
Short name T74
Test name
Test status
Simulation time 2051009915 ps
CPU time 4.15 seconds
Started Jun 13 02:16:23 PM PDT 24
Finished Jun 13 02:16:31 PM PDT 24
Peak memory 191596 kb
Host smart-bed4a523-edd8-4143-b14b-24662a48b063
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546692454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1546692454
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3213033566
Short name T292
Test name
Test status
Simulation time 536989959 ps
CPU time 2.21 seconds
Started Jun 13 02:16:23 PM PDT 24
Finished Jun 13 02:16:29 PM PDT 24
Peak memory 198200 kb
Host smart-f9f504a7-b1da-4380-af3f-ffdcdb378570
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213033566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3213033566
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2911343093
Short name T57
Test name
Test status
Simulation time 649452830 ps
CPU time 0.98 seconds
Started Jun 13 02:16:26 PM PDT 24
Finished Jun 13 02:16:31 PM PDT 24
Peak memory 191600 kb
Host smart-c7feaf34-6ae6-43e8-8666-b9044b1cfcf4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911343093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2911343093
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2979335574
Short name T60
Test name
Test status
Simulation time 7125732543 ps
CPU time 15.07 seconds
Started Jun 13 02:16:25 PM PDT 24
Finished Jun 13 02:16:44 PM PDT 24
Peak memory 191820 kb
Host smart-1a8b24b7-c2f6-4be3-95b7-789113a0c6e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979335574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2979335574
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1067644581
Short name T65
Test name
Test status
Simulation time 859213691 ps
CPU time 1.22 seconds
Started Jun 13 02:16:25 PM PDT 24
Finished Jun 13 02:16:30 PM PDT 24
Peak memory 192892 kb
Host smart-9c6dcb7b-cc25-407d-9879-0829ed7b63ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067644581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1067644581
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2427817613
Short name T358
Test name
Test status
Simulation time 487471885 ps
CPU time 0.86 seconds
Started Jun 13 02:16:25 PM PDT 24
Finished Jun 13 02:16:30 PM PDT 24
Peak memory 196572 kb
Host smart-fb2fc6ab-7bb7-4561-acc9-47b35b882c99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427817613 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2427817613
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3337197532
Short name T367
Test name
Test status
Simulation time 470352706 ps
CPU time 0.93 seconds
Started Jun 13 02:16:29 PM PDT 24
Finished Jun 13 02:16:35 PM PDT 24
Peak memory 192628 kb
Host smart-63eb4a7d-a125-4c65-ad9c-de98ee5c6011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337197532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3337197532
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.89385009
Short name T407
Test name
Test status
Simulation time 438562369 ps
CPU time 1.19 seconds
Started Jun 13 02:16:26 PM PDT 24
Finished Jun 13 02:16:31 PM PDT 24
Peak memory 183360 kb
Host smart-461574f0-358b-4625-8ceb-8b9f8c5496b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89385009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.89385009
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.273185513
Short name T328
Test name
Test status
Simulation time 380350447 ps
CPU time 1.12 seconds
Started Jun 13 02:16:26 PM PDT 24
Finished Jun 13 02:16:31 PM PDT 24
Peak memory 183264 kb
Host smart-4153147e-bd26-4850-b615-204d3c302a74
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273185513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.273185513
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4247725443
Short name T331
Test name
Test status
Simulation time 466201244 ps
CPU time 0.7 seconds
Started Jun 13 02:16:25 PM PDT 24
Finished Jun 13 02:16:29 PM PDT 24
Peak memory 183316 kb
Host smart-439bbd77-b5b2-48af-8832-3c6e3e13e855
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247725443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.4247725443
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1593963225
Short name T73
Test name
Test status
Simulation time 2204375455 ps
CPU time 1.46 seconds
Started Jun 13 02:16:26 PM PDT 24
Finished Jun 13 02:16:32 PM PDT 24
Peak memory 193636 kb
Host smart-adc39690-1177-4d35-819a-5b3fe33a7a5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593963225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1593963225
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.934398633
Short name T297
Test name
Test status
Simulation time 379962098 ps
CPU time 2.59 seconds
Started Jun 13 02:16:22 PM PDT 24
Finished Jun 13 02:16:28 PM PDT 24
Peak memory 198216 kb
Host smart-b74ba0b4-8ba0-4a49-9c9d-3441cad305ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934398633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.934398633
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3855159910
Short name T195
Test name
Test status
Simulation time 8481964031 ps
CPU time 12.03 seconds
Started Jun 13 02:16:20 PM PDT 24
Finished Jun 13 02:16:35 PM PDT 24
Peak memory 197668 kb
Host smart-7c661eb5-dbbd-4dde-96bd-f936d2b9ab2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855159910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3855159910
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1551457470
Short name T304
Test name
Test status
Simulation time 451792812 ps
CPU time 0.94 seconds
Started Jun 13 02:16:45 PM PDT 24
Finished Jun 13 02:16:53 PM PDT 24
Peak memory 195996 kb
Host smart-9ecc5010-61e7-4322-b578-229b8f9e0a3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551457470 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1551457470
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4256669783
Short name T399
Test name
Test status
Simulation time 397351983 ps
CPU time 0.83 seconds
Started Jun 13 02:16:43 PM PDT 24
Finished Jun 13 02:16:50 PM PDT 24
Peak memory 183340 kb
Host smart-7310e56b-1cfb-4ce9-b05d-225d0bb230e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256669783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.4256669783
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1448493573
Short name T71
Test name
Test status
Simulation time 833781919 ps
CPU time 1.6 seconds
Started Jun 13 02:16:45 PM PDT 24
Finished Jun 13 02:16:54 PM PDT 24
Peak memory 183556 kb
Host smart-bed87a7e-d523-4634-afdf-0854c224f845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448493573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1448493573
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3988490908
Short name T368
Test name
Test status
Simulation time 591202465 ps
CPU time 1.49 seconds
Started Jun 13 02:16:43 PM PDT 24
Finished Jun 13 02:16:51 PM PDT 24
Peak memory 198216 kb
Host smart-df6cf418-cba1-4344-8548-4d9126d0d1c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988490908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3988490908
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3909284329
Short name T361
Test name
Test status
Simulation time 8432792946 ps
CPU time 9.53 seconds
Started Jun 13 02:16:45 PM PDT 24
Finished Jun 13 02:17:02 PM PDT 24
Peak memory 197872 kb
Host smart-308c3d4c-d367-4d04-9410-d302b97af379
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909284329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3909284329
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2613770339
Short name T342
Test name
Test status
Simulation time 457106973 ps
CPU time 0.79 seconds
Started Jun 13 02:16:46 PM PDT 24
Finished Jun 13 02:16:54 PM PDT 24
Peak memory 195380 kb
Host smart-986525e1-2fa8-4c37-b28d-e37d3eb120b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613770339 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2613770339
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2420514442
Short name T324
Test name
Test status
Simulation time 606486363 ps
CPU time 0.69 seconds
Started Jun 13 02:16:42 PM PDT 24
Finished Jun 13 02:16:49 PM PDT 24
Peak memory 192948 kb
Host smart-222b91f8-f88d-47b7-b7c1-9b333691aa61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420514442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2420514442
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.696393617
Short name T321
Test name
Test status
Simulation time 373694614 ps
CPU time 0.58 seconds
Started Jun 13 02:16:42 PM PDT 24
Finished Jun 13 02:16:49 PM PDT 24
Peak memory 192560 kb
Host smart-be9f4523-57f7-4f58-a2cc-6f7a33763130
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696393617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.696393617
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.838497219
Short name T374
Test name
Test status
Simulation time 1375656357 ps
CPU time 2.96 seconds
Started Jun 13 02:16:44 PM PDT 24
Finished Jun 13 02:16:55 PM PDT 24
Peak memory 192936 kb
Host smart-c7120854-3e34-4271-aa3b-7a753fbfc3f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838497219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.838497219
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4188083147
Short name T400
Test name
Test status
Simulation time 410454413 ps
CPU time 2.72 seconds
Started Jun 13 02:16:44 PM PDT 24
Finished Jun 13 02:16:54 PM PDT 24
Peak memory 198220 kb
Host smart-eccc4849-aacf-4456-a77e-48f188e2fa52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188083147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.4188083147
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4223507628
Short name T192
Test name
Test status
Simulation time 7847277455 ps
CPU time 4.28 seconds
Started Jun 13 02:16:46 PM PDT 24
Finished Jun 13 02:16:57 PM PDT 24
Peak memory 197808 kb
Host smart-adb51445-f879-4b04-81ab-b956a99e6f40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223507628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.4223507628
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2943429412
Short name T33
Test name
Test status
Simulation time 548942002 ps
CPU time 0.75 seconds
Started Jun 13 02:16:43 PM PDT 24
Finished Jun 13 02:16:51 PM PDT 24
Peak memory 195768 kb
Host smart-eb10e8ab-fd0b-42a7-9dca-da6e07c758a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943429412 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2943429412
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2178639122
Short name T63
Test name
Test status
Simulation time 302270971 ps
CPU time 1.12 seconds
Started Jun 13 02:16:44 PM PDT 24
Finished Jun 13 02:16:52 PM PDT 24
Peak memory 193040 kb
Host smart-b9a82bd0-14bc-4b1f-938d-ddaea8979ffd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178639122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2178639122
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2134150086
Short name T333
Test name
Test status
Simulation time 286162275 ps
CPU time 0.76 seconds
Started Jun 13 02:16:44 PM PDT 24
Finished Jun 13 02:16:53 PM PDT 24
Peak memory 192508 kb
Host smart-d74bee7e-ef1c-4c45-a896-3a0f1e18a1d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134150086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2134150086
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1761545088
Short name T416
Test name
Test status
Simulation time 793016861 ps
CPU time 1.28 seconds
Started Jun 13 02:16:44 PM PDT 24
Finished Jun 13 02:16:52 PM PDT 24
Peak memory 192628 kb
Host smart-598b316f-7c3f-402a-89cb-23c3bee62fdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761545088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1761545088
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1888102206
Short name T335
Test name
Test status
Simulation time 886688442 ps
CPU time 1.98 seconds
Started Jun 13 02:16:42 PM PDT 24
Finished Jun 13 02:16:50 PM PDT 24
Peak memory 198208 kb
Host smart-48a969f3-e74a-4e64-a931-a4bcce5e5e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888102206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1888102206
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3173681631
Short name T355
Test name
Test status
Simulation time 4152057598 ps
CPU time 6.73 seconds
Started Jun 13 02:16:44 PM PDT 24
Finished Jun 13 02:16:58 PM PDT 24
Peak memory 197252 kb
Host smart-480cc445-00a4-44a1-ba22-e084dcbd08e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173681631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3173681631
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3072261831
Short name T322
Test name
Test status
Simulation time 499247422 ps
CPU time 1.15 seconds
Started Jun 13 02:16:42 PM PDT 24
Finished Jun 13 02:16:50 PM PDT 24
Peak memory 196876 kb
Host smart-d2bfe321-402b-484d-b8ab-69493402d9fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072261831 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3072261831
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3940255822
Short name T346
Test name
Test status
Simulation time 352591583 ps
CPU time 0.82 seconds
Started Jun 13 02:16:41 PM PDT 24
Finished Jun 13 02:16:48 PM PDT 24
Peak memory 192920 kb
Host smart-87ae9ea2-61bb-46ae-be54-0bb40d786ddf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940255822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3940255822
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4120400928
Short name T392
Test name
Test status
Simulation time 339147713 ps
CPU time 0.61 seconds
Started Jun 13 02:16:46 PM PDT 24
Finished Jun 13 02:16:54 PM PDT 24
Peak memory 183344 kb
Host smart-8cb9187f-a286-4023-9b73-350aeaacd663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120400928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4120400928
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3464084820
Short name T411
Test name
Test status
Simulation time 1173473955 ps
CPU time 1.05 seconds
Started Jun 13 02:16:46 PM PDT 24
Finished Jun 13 02:16:55 PM PDT 24
Peak memory 193468 kb
Host smart-23229d90-bb09-457a-9dff-ad71cd40a711
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464084820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3464084820
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.712359186
Short name T305
Test name
Test status
Simulation time 548837207 ps
CPU time 1.78 seconds
Started Jun 13 02:16:44 PM PDT 24
Finished Jun 13 02:16:54 PM PDT 24
Peak memory 198248 kb
Host smart-2c343420-b647-4aac-8330-a080e0b81631
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712359186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.712359186
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.801942157
Short name T385
Test name
Test status
Simulation time 4621336827 ps
CPU time 2.07 seconds
Started Jun 13 02:16:44 PM PDT 24
Finished Jun 13 02:16:53 PM PDT 24
Peak memory 197584 kb
Host smart-06f21813-2981-4f2a-826f-60cae198b453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801942157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.801942157
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3070915870
Short name T301
Test name
Test status
Simulation time 1048288115 ps
CPU time 1.61 seconds
Started Jun 13 02:16:50 PM PDT 24
Finished Jun 13 02:16:59 PM PDT 24
Peak memory 198220 kb
Host smart-a7beab3b-fbcf-4caf-9fee-5abcb9ae3331
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070915870 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3070915870
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3264099897
Short name T70
Test name
Test status
Simulation time 431157807 ps
CPU time 0.85 seconds
Started Jun 13 02:16:47 PM PDT 24
Finished Jun 13 02:16:55 PM PDT 24
Peak memory 192792 kb
Host smart-00db08f6-9439-456f-97d2-bdd374e6b23d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264099897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3264099897
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1893457765
Short name T350
Test name
Test status
Simulation time 350796868 ps
CPU time 1.04 seconds
Started Jun 13 02:16:44 PM PDT 24
Finished Jun 13 02:16:52 PM PDT 24
Peak memory 183328 kb
Host smart-f7d75d25-636d-4dc5-bcb6-2476d1f61de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893457765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1893457765
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2099861127
Short name T69
Test name
Test status
Simulation time 1173800717 ps
CPU time 1.05 seconds
Started Jun 13 02:16:46 PM PDT 24
Finished Jun 13 02:16:54 PM PDT 24
Peak memory 193404 kb
Host smart-f32686de-8a37-43ff-904f-bb8db12684c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099861127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2099861127
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1054183919
Short name T418
Test name
Test status
Simulation time 467708849 ps
CPU time 1.88 seconds
Started Jun 13 02:16:42 PM PDT 24
Finished Jun 13 02:16:51 PM PDT 24
Peak memory 198188 kb
Host smart-4947a366-6a2e-4921-abf9-7fa03545393e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054183919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1054183919
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2612364693
Short name T386
Test name
Test status
Simulation time 4625053158 ps
CPU time 6.53 seconds
Started Jun 13 02:16:46 PM PDT 24
Finished Jun 13 02:17:00 PM PDT 24
Peak memory 197156 kb
Host smart-8a3b0c18-d304-44bc-bdcb-fef9df173645
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612364693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2612364693
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4247878049
Short name T32
Test name
Test status
Simulation time 448958116 ps
CPU time 0.88 seconds
Started Jun 13 02:16:49 PM PDT 24
Finished Jun 13 02:16:57 PM PDT 24
Peak memory 196588 kb
Host smart-b2c3879d-7906-45d8-b4c0-005344af8f9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247878049 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.4247878049
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.820719928
Short name T336
Test name
Test status
Simulation time 420364292 ps
CPU time 1.21 seconds
Started Jun 13 02:16:51 PM PDT 24
Finished Jun 13 02:17:00 PM PDT 24
Peak memory 192628 kb
Host smart-9ef2f574-ab8b-49dd-bf47-4435bae7d9ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820719928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.820719928
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.950984349
Short name T323
Test name
Test status
Simulation time 400685366 ps
CPU time 1.04 seconds
Started Jun 13 02:16:49 PM PDT 24
Finished Jun 13 02:16:57 PM PDT 24
Peak memory 183356 kb
Host smart-90772a3a-cb35-4eb7-be96-09ff601fdc06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950984349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.950984349
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1983771964
Short name T347
Test name
Test status
Simulation time 1386714565 ps
CPU time 1.38 seconds
Started Jun 13 02:16:48 PM PDT 24
Finished Jun 13 02:16:57 PM PDT 24
Peak memory 192800 kb
Host smart-cd1f454a-18d0-4721-ab5b-e016da8e373b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983771964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1983771964
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.430435761
Short name T289
Test name
Test status
Simulation time 494621498 ps
CPU time 2.43 seconds
Started Jun 13 02:16:49 PM PDT 24
Finished Jun 13 02:17:00 PM PDT 24
Peak memory 198228 kb
Host smart-d5b92c39-2584-4752-87dd-f5b42b3edf41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430435761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.430435761
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2071836612
Short name T357
Test name
Test status
Simulation time 3784629818 ps
CPU time 2.32 seconds
Started Jun 13 02:16:49 PM PDT 24
Finished Jun 13 02:16:59 PM PDT 24
Peak memory 196036 kb
Host smart-f732bafa-1dd1-4a36-8fdf-3e8ad288accb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071836612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2071836612
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1252225662
Short name T402
Test name
Test status
Simulation time 885836304 ps
CPU time 1.17 seconds
Started Jun 13 02:16:47 PM PDT 24
Finished Jun 13 02:16:55 PM PDT 24
Peak memory 198184 kb
Host smart-a133b0e9-5f5a-4d05-8b16-d88c3a5b1679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252225662 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1252225662
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1658260964
Short name T62
Test name
Test status
Simulation time 377852656 ps
CPU time 0.71 seconds
Started Jun 13 02:16:49 PM PDT 24
Finished Jun 13 02:16:57 PM PDT 24
Peak memory 191696 kb
Host smart-775ba266-a784-417f-a36a-79fb4d52ab94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658260964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1658260964
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2010430669
Short name T376
Test name
Test status
Simulation time 445061519 ps
CPU time 0.69 seconds
Started Jun 13 02:16:49 PM PDT 24
Finished Jun 13 02:16:58 PM PDT 24
Peak memory 183336 kb
Host smart-74c7a908-d99f-40d5-83c1-07cc2e8cd7a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010430669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2010430669
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2681062262
Short name T76
Test name
Test status
Simulation time 1016558292 ps
CPU time 1.18 seconds
Started Jun 13 02:16:48 PM PDT 24
Finished Jun 13 02:16:57 PM PDT 24
Peak memory 193184 kb
Host smart-a26946a4-5c6f-4864-beaa-386ee8deb030
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681062262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2681062262
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2935557810
Short name T330
Test name
Test status
Simulation time 402605845 ps
CPU time 1.9 seconds
Started Jun 13 02:16:51 PM PDT 24
Finished Jun 13 02:17:01 PM PDT 24
Peak memory 198220 kb
Host smart-a98d4c30-7591-471d-8c98-71d8991c1f09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935557810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2935557810
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3038851275
Short name T194
Test name
Test status
Simulation time 4423024671 ps
CPU time 2.31 seconds
Started Jun 13 02:16:50 PM PDT 24
Finished Jun 13 02:17:00 PM PDT 24
Peak memory 196404 kb
Host smart-99154433-7400-448f-88c1-5b77dfe4c10d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038851275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3038851275
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.963308477
Short name T315
Test name
Test status
Simulation time 778075232 ps
CPU time 1.13 seconds
Started Jun 13 02:16:54 PM PDT 24
Finished Jun 13 02:17:02 PM PDT 24
Peak memory 198020 kb
Host smart-48262278-7821-470b-9efc-d4765f7cd47d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963308477 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.963308477
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1359826812
Short name T75
Test name
Test status
Simulation time 355471995 ps
CPU time 1.12 seconds
Started Jun 13 02:16:48 PM PDT 24
Finished Jun 13 02:16:57 PM PDT 24
Peak memory 191692 kb
Host smart-e2373ca0-f6e7-4c17-b49d-c37b8dbc7e3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359826812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1359826812
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2751760041
Short name T329
Test name
Test status
Simulation time 434427224 ps
CPU time 0.85 seconds
Started Jun 13 02:16:46 PM PDT 24
Finished Jun 13 02:16:54 PM PDT 24
Peak memory 183352 kb
Host smart-14d85f00-ea79-4258-9ddb-2138cd6779bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751760041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2751760041
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.370101876
Short name T381
Test name
Test status
Simulation time 1183917316 ps
CPU time 1.32 seconds
Started Jun 13 02:16:49 PM PDT 24
Finished Jun 13 02:16:57 PM PDT 24
Peak memory 193492 kb
Host smart-03583c1c-d64a-46e9-a36f-b3025b86afd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370101876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.370101876
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1723327077
Short name T384
Test name
Test status
Simulation time 485027147 ps
CPU time 1.52 seconds
Started Jun 13 02:16:49 PM PDT 24
Finished Jun 13 02:16:59 PM PDT 24
Peak memory 198208 kb
Host smart-1fcd44ce-c03d-46cd-a88e-8baad0e80c65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723327077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1723327077
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.569541907
Short name T424
Test name
Test status
Simulation time 8030107525 ps
CPU time 13.59 seconds
Started Jun 13 02:16:49 PM PDT 24
Finished Jun 13 02:17:10 PM PDT 24
Peak memory 197896 kb
Host smart-042042f8-2494-44dd-ae48-77f92d903115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569541907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.569541907
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2768698551
Short name T371
Test name
Test status
Simulation time 424372204 ps
CPU time 1.38 seconds
Started Jun 13 02:16:54 PM PDT 24
Finished Jun 13 02:17:03 PM PDT 24
Peak memory 195484 kb
Host smart-cc196508-f323-4b52-adb9-30907b6ed32d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768698551 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2768698551
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4051447626
Short name T56
Test name
Test status
Simulation time 359989276 ps
CPU time 0.72 seconds
Started Jun 13 02:16:57 PM PDT 24
Finished Jun 13 02:17:05 PM PDT 24
Peak memory 193116 kb
Host smart-ac89fe8d-c4a5-437a-b746-caa05eb20949
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051447626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.4051447626
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.826078579
Short name T343
Test name
Test status
Simulation time 439305690 ps
CPU time 1.12 seconds
Started Jun 13 02:16:54 PM PDT 24
Finished Jun 13 02:17:03 PM PDT 24
Peak memory 183316 kb
Host smart-2daab73f-2907-4bbf-a3a6-cd3fd88b6c5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826078579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.826078579
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.698023139
Short name T409
Test name
Test status
Simulation time 2348932630 ps
CPU time 3.86 seconds
Started Jun 13 02:17:06 PM PDT 24
Finished Jun 13 02:17:16 PM PDT 24
Peak memory 194740 kb
Host smart-c62a1084-0028-44ef-b6b2-18d2f0622f95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698023139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.698023139
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1149176733
Short name T375
Test name
Test status
Simulation time 572099464 ps
CPU time 2.94 seconds
Started Jun 13 02:16:53 PM PDT 24
Finished Jun 13 02:17:03 PM PDT 24
Peak memory 198120 kb
Host smart-fe9e2f9f-be0b-4f38-99c1-10fa0fef5319
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149176733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1149176733
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.852606509
Short name T35
Test name
Test status
Simulation time 4692148967 ps
CPU time 7.85 seconds
Started Jun 13 02:16:55 PM PDT 24
Finished Jun 13 02:17:10 PM PDT 24
Peak memory 196324 kb
Host smart-27bf17d2-a42d-4618-99db-b13dc056eef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852606509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.852606509
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4222874290
Short name T39
Test name
Test status
Simulation time 434814036 ps
CPU time 1.33 seconds
Started Jun 13 02:16:56 PM PDT 24
Finished Jun 13 02:17:05 PM PDT 24
Peak memory 195436 kb
Host smart-d6410b71-2106-4df6-9ba0-82624f15f05c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222874290 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.4222874290
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2868596616
Short name T77
Test name
Test status
Simulation time 385802177 ps
CPU time 0.87 seconds
Started Jun 13 02:16:55 PM PDT 24
Finished Jun 13 02:17:03 PM PDT 24
Peak memory 193116 kb
Host smart-4bce286f-71dc-41e4-99bf-487e2fc627ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868596616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2868596616
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2236843619
Short name T307
Test name
Test status
Simulation time 295367330 ps
CPU time 0.75 seconds
Started Jun 13 02:16:54 PM PDT 24
Finished Jun 13 02:17:03 PM PDT 24
Peak memory 192568 kb
Host smart-bf3175a4-43bd-4c55-a038-977bb7a713d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236843619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2236843619
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3916331260
Short name T339
Test name
Test status
Simulation time 1343777926 ps
CPU time 2.35 seconds
Started Jun 13 02:16:54 PM PDT 24
Finished Jun 13 02:17:03 PM PDT 24
Peak memory 193144 kb
Host smart-aa952216-9a87-453f-a0f9-4f3973ebc8d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916331260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3916331260
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3588844622
Short name T291
Test name
Test status
Simulation time 483375553 ps
CPU time 1.26 seconds
Started Jun 13 02:16:54 PM PDT 24
Finished Jun 13 02:17:02 PM PDT 24
Peak memory 198028 kb
Host smart-b995e841-30ef-4760-be16-b2642d505044
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588844622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3588844622
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.447811475
Short name T36
Test name
Test status
Simulation time 8739307652 ps
CPU time 2.19 seconds
Started Jun 13 02:16:57 PM PDT 24
Finished Jun 13 02:17:07 PM PDT 24
Peak memory 197652 kb
Host smart-99b63f3c-f36c-43cb-b29b-b4f2c95d6fd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447811475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.447811475
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3647615676
Short name T67
Test name
Test status
Simulation time 575226391 ps
CPU time 1.08 seconds
Started Jun 13 02:16:27 PM PDT 24
Finished Jun 13 02:16:32 PM PDT 24
Peak memory 193988 kb
Host smart-071a8a58-4fcd-4c7e-b53e-e5fc4dae50b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647615676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3647615676
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.849726553
Short name T38
Test name
Test status
Simulation time 7122572991 ps
CPU time 11.28 seconds
Started Jun 13 02:16:27 PM PDT 24
Finished Jun 13 02:16:42 PM PDT 24
Peak memory 196088 kb
Host smart-c78a82ec-a09e-4827-bc01-6b1c1f54886c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849726553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.849726553
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3946437147
Short name T387
Test name
Test status
Simulation time 1257627429 ps
CPU time 2.39 seconds
Started Jun 13 02:16:27 PM PDT 24
Finished Jun 13 02:16:33 PM PDT 24
Peak memory 192864 kb
Host smart-4a9c227c-adfb-4e66-ae77-2be67549dea1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946437147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3946437147
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.645435918
Short name T318
Test name
Test status
Simulation time 574746117 ps
CPU time 1.16 seconds
Started Jun 13 02:16:27 PM PDT 24
Finished Jun 13 02:16:32 PM PDT 24
Peak memory 195904 kb
Host smart-20daacc1-b1e2-41db-8103-492113d6401b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645435918 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.645435918
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1995510880
Short name T369
Test name
Test status
Simulation time 442796440 ps
CPU time 1.39 seconds
Started Jun 13 02:16:27 PM PDT 24
Finished Jun 13 02:16:32 PM PDT 24
Peak memory 192796 kb
Host smart-8faf71d6-5033-48c9-a528-046f8384f095
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995510880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1995510880
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2581766873
Short name T393
Test name
Test status
Simulation time 503142890 ps
CPU time 1.32 seconds
Started Jun 13 02:16:25 PM PDT 24
Finished Jun 13 02:16:31 PM PDT 24
Peak memory 183340 kb
Host smart-29304e82-26a0-4d69-9f74-a734128f8f75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581766873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2581766873
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3552349836
Short name T309
Test name
Test status
Simulation time 483400361 ps
CPU time 1.24 seconds
Started Jun 13 02:16:25 PM PDT 24
Finished Jun 13 02:16:30 PM PDT 24
Peak memory 183232 kb
Host smart-8e410f4e-a70a-46c8-a7d9-79dd63ae215d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552349836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3552349836
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3505455757
Short name T288
Test name
Test status
Simulation time 442249665 ps
CPU time 0.69 seconds
Started Jun 13 02:16:25 PM PDT 24
Finished Jun 13 02:16:30 PM PDT 24
Peak memory 183344 kb
Host smart-528c4be7-ec6d-4cd4-9c9d-f51a529d98aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505455757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3505455757
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2292565137
Short name T332
Test name
Test status
Simulation time 2317342569 ps
CPU time 2.04 seconds
Started Jun 13 02:16:26 PM PDT 24
Finished Jun 13 02:16:32 PM PDT 24
Peak memory 193508 kb
Host smart-0561536f-4ffd-44a2-911a-1628a36e946e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292565137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2292565137
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3991121432
Short name T298
Test name
Test status
Simulation time 356265197 ps
CPU time 1.93 seconds
Started Jun 13 02:16:26 PM PDT 24
Finished Jun 13 02:16:32 PM PDT 24
Peak memory 198212 kb
Host smart-acda7bb5-742c-4528-bacc-6f8de793cd88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991121432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3991121432
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3478047779
Short name T395
Test name
Test status
Simulation time 8512153087 ps
CPU time 13.49 seconds
Started Jun 13 02:16:25 PM PDT 24
Finished Jun 13 02:16:43 PM PDT 24
Peak memory 197972 kb
Host smart-16e5b98f-4130-4384-a617-aaec7e536086
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478047779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3478047779
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3294110601
Short name T396
Test name
Test status
Simulation time 451829341 ps
CPU time 0.66 seconds
Started Jun 13 02:16:53 PM PDT 24
Finished Jun 13 02:17:00 PM PDT 24
Peak memory 183312 kb
Host smart-a871f815-d9ce-44c1-875b-766f9d6dbeb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294110601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3294110601
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3453501772
Short name T312
Test name
Test status
Simulation time 435141278 ps
CPU time 1.24 seconds
Started Jun 13 02:16:54 PM PDT 24
Finished Jun 13 02:17:03 PM PDT 24
Peak memory 183348 kb
Host smart-d64a7ec8-6df5-4e88-8f75-252ffccf156f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453501772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3453501772
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2552135951
Short name T398
Test name
Test status
Simulation time 479341737 ps
CPU time 0.86 seconds
Started Jun 13 02:17:06 PM PDT 24
Finished Jun 13 02:17:13 PM PDT 24
Peak memory 183332 kb
Host smart-01f91517-f4d2-4352-b34f-77f1c6fe4517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552135951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2552135951
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3585912556
Short name T338
Test name
Test status
Simulation time 465636781 ps
CPU time 1.19 seconds
Started Jun 13 02:16:54 PM PDT 24
Finished Jun 13 02:17:02 PM PDT 24
Peak memory 192568 kb
Host smart-420dda09-e5a3-46f4-aa74-47839edbc4d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585912556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3585912556
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1527463714
Short name T391
Test name
Test status
Simulation time 338055786 ps
CPU time 1.11 seconds
Started Jun 13 02:16:55 PM PDT 24
Finished Jun 13 02:17:04 PM PDT 24
Peak memory 192568 kb
Host smart-97c866c3-b4b4-4134-a2c4-f2c473abe984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527463714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1527463714
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3466159947
Short name T299
Test name
Test status
Simulation time 388662971 ps
CPU time 1.18 seconds
Started Jun 13 02:16:54 PM PDT 24
Finished Jun 13 02:17:03 PM PDT 24
Peak memory 183352 kb
Host smart-894a1909-ec31-4975-9f18-efc139b56cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466159947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3466159947
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1543214177
Short name T414
Test name
Test status
Simulation time 457377961 ps
CPU time 0.72 seconds
Started Jun 13 02:16:57 PM PDT 24
Finished Jun 13 02:17:05 PM PDT 24
Peak memory 183348 kb
Host smart-d0a36585-87b5-4e06-a188-221ffeb757b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543214177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1543214177
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.991580974
Short name T337
Test name
Test status
Simulation time 349920387 ps
CPU time 0.66 seconds
Started Jun 13 02:16:57 PM PDT 24
Finished Jun 13 02:17:05 PM PDT 24
Peak memory 183352 kb
Host smart-cd22facc-f1ca-4544-b92c-aa1ced2295f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991580974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.991580974
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.827082243
Short name T314
Test name
Test status
Simulation time 348024030 ps
CPU time 0.78 seconds
Started Jun 13 02:17:06 PM PDT 24
Finished Jun 13 02:17:12 PM PDT 24
Peak memory 183336 kb
Host smart-0d7295ae-ad09-4417-8680-e3d4ce672b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827082243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.827082243
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1097906451
Short name T325
Test name
Test status
Simulation time 389598178 ps
CPU time 1.02 seconds
Started Jun 13 02:17:05 PM PDT 24
Finished Jun 13 02:17:12 PM PDT 24
Peak memory 183332 kb
Host smart-059d0720-43bc-4c6e-8334-8f3b1f8223f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097906451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1097906451
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3874763832
Short name T401
Test name
Test status
Simulation time 775223134 ps
CPU time 0.96 seconds
Started Jun 13 02:16:30 PM PDT 24
Finished Jun 13 02:16:36 PM PDT 24
Peak memory 183360 kb
Host smart-c6bf0fcc-83ff-4031-9e5b-d676c8ab1ff0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874763832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3874763832
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.955358160
Short name T403
Test name
Test status
Simulation time 14052134014 ps
CPU time 18.15 seconds
Started Jun 13 02:16:37 PM PDT 24
Finished Jun 13 02:17:01 PM PDT 24
Peak memory 195988 kb
Host smart-e5cf7a28-aa65-4b1c-95b7-c124c700f276
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955358160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.955358160
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1956538266
Short name T64
Test name
Test status
Simulation time 1300024015 ps
CPU time 1.09 seconds
Started Jun 13 02:16:29 PM PDT 24
Finished Jun 13 02:16:36 PM PDT 24
Peak memory 192536 kb
Host smart-8e2e5ef9-f0c6-48dd-a126-cc6c28cb7f8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956538266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1956538266
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.443147468
Short name T362
Test name
Test status
Simulation time 405508256 ps
CPU time 0.98 seconds
Started Jun 13 02:16:32 PM PDT 24
Finished Jun 13 02:16:38 PM PDT 24
Peak memory 195588 kb
Host smart-9837b18a-0ef3-4c11-8566-97a9590e8ca0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443147468 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.443147468
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3106358475
Short name T380
Test name
Test status
Simulation time 389820874 ps
CPU time 0.82 seconds
Started Jun 13 02:16:31 PM PDT 24
Finished Jun 13 02:16:37 PM PDT 24
Peak memory 192628 kb
Host smart-af4b2551-5e00-48c2-87ef-39fa4c28f8c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106358475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3106358475
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1295229360
Short name T417
Test name
Test status
Simulation time 317582167 ps
CPU time 0.9 seconds
Started Jun 13 02:16:29 PM PDT 24
Finished Jun 13 02:16:35 PM PDT 24
Peak memory 183340 kb
Host smart-3aa2d0e6-b586-40ac-893a-51c51d09be69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295229360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1295229360
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.979503080
Short name T302
Test name
Test status
Simulation time 347802266 ps
CPU time 0.61 seconds
Started Jun 13 02:16:25 PM PDT 24
Finished Jun 13 02:16:30 PM PDT 24
Peak memory 183260 kb
Host smart-402f725a-4d5a-4ccb-8804-6f216dbbbe37
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979503080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.979503080
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2155774131
Short name T412
Test name
Test status
Simulation time 461889233 ps
CPU time 1.08 seconds
Started Jun 13 02:16:41 PM PDT 24
Finished Jun 13 02:16:48 PM PDT 24
Peak memory 183296 kb
Host smart-b5c5467a-caeb-4d93-8d83-f2fe3dbf2e4e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155774131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2155774131
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3104710509
Short name T378
Test name
Test status
Simulation time 2075017400 ps
CPU time 5.79 seconds
Started Jun 13 02:16:31 PM PDT 24
Finished Jun 13 02:16:42 PM PDT 24
Peak memory 193448 kb
Host smart-8011078e-a21c-454d-a4bf-4f08b1735ce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104710509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3104710509
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2039682168
Short name T310
Test name
Test status
Simulation time 719980641 ps
CPU time 1.99 seconds
Started Jun 13 02:16:24 PM PDT 24
Finished Jun 13 02:16:30 PM PDT 24
Peak memory 198256 kb
Host smart-996d715a-738a-432a-ad15-6d79866283c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039682168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2039682168
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.516111187
Short name T356
Test name
Test status
Simulation time 4201356021 ps
CPU time 4.08 seconds
Started Jun 13 02:16:26 PM PDT 24
Finished Jun 13 02:16:34 PM PDT 24
Peak memory 197432 kb
Host smart-cd7b3b64-4d51-463a-b3f8-ac5b94095d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516111187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.516111187
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1630860723
Short name T320
Test name
Test status
Simulation time 295779027 ps
CPU time 0.72 seconds
Started Jun 13 02:16:56 PM PDT 24
Finished Jun 13 02:17:04 PM PDT 24
Peak memory 183360 kb
Host smart-31eebee8-0bce-4c3e-bde3-734efd347b11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630860723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1630860723
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1564906135
Short name T406
Test name
Test status
Simulation time 305055950 ps
CPU time 0.86 seconds
Started Jun 13 02:17:06 PM PDT 24
Finished Jun 13 02:17:13 PM PDT 24
Peak memory 192552 kb
Host smart-e154891e-bd42-4308-aad8-9b269eadcabb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564906135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1564906135
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.95023819
Short name T308
Test name
Test status
Simulation time 306959486 ps
CPU time 0.91 seconds
Started Jun 13 02:16:55 PM PDT 24
Finished Jun 13 02:17:04 PM PDT 24
Peak memory 183344 kb
Host smart-bcbb2b60-f9b0-4c98-ad34-99e9379e14c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95023819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.95023819
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.53810088
Short name T421
Test name
Test status
Simulation time 378421341 ps
CPU time 1.05 seconds
Started Jun 13 02:16:57 PM PDT 24
Finished Jun 13 02:17:05 PM PDT 24
Peak memory 183352 kb
Host smart-0362ada8-c659-45f4-8811-661dc543f974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53810088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.53810088
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1778299821
Short name T366
Test name
Test status
Simulation time 426569928 ps
CPU time 1.21 seconds
Started Jun 13 02:16:54 PM PDT 24
Finished Jun 13 02:17:03 PM PDT 24
Peak memory 183300 kb
Host smart-766f4f99-430f-40a0-8e7b-d76dee725a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778299821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1778299821
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3600076572
Short name T294
Test name
Test status
Simulation time 461404496 ps
CPU time 1.25 seconds
Started Jun 13 02:16:55 PM PDT 24
Finished Jun 13 02:17:04 PM PDT 24
Peak memory 183356 kb
Host smart-7f09e078-ded6-4ce3-9598-1f83e72c1454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600076572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3600076572
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3812038830
Short name T303
Test name
Test status
Simulation time 461378449 ps
CPU time 0.82 seconds
Started Jun 13 02:17:05 PM PDT 24
Finished Jun 13 02:17:12 PM PDT 24
Peak memory 183332 kb
Host smart-2450c177-0391-49b0-a3e8-eb55107bfaaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812038830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3812038830
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1403104599
Short name T404
Test name
Test status
Simulation time 359616095 ps
CPU time 1.12 seconds
Started Jun 13 02:16:55 PM PDT 24
Finished Jun 13 02:17:04 PM PDT 24
Peak memory 192564 kb
Host smart-9912a685-72a1-4a78-9c86-9b3500443cf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403104599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1403104599
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.308794976
Short name T363
Test name
Test status
Simulation time 408091746 ps
CPU time 1.17 seconds
Started Jun 13 02:17:05 PM PDT 24
Finished Jun 13 02:17:12 PM PDT 24
Peak memory 183336 kb
Host smart-b4dcc5fe-7347-44ba-a861-220623eba6cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308794976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.308794976
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3438264239
Short name T340
Test name
Test status
Simulation time 337279635 ps
CPU time 1.07 seconds
Started Jun 13 02:17:03 PM PDT 24
Finished Jun 13 02:17:10 PM PDT 24
Peak memory 183348 kb
Host smart-d441bb95-209a-42f5-86bb-17d437677147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438264239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3438264239
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3138821057
Short name T66
Test name
Test status
Simulation time 700365218 ps
CPU time 0.86 seconds
Started Jun 13 02:16:40 PM PDT 24
Finished Jun 13 02:16:48 PM PDT 24
Peak memory 193688 kb
Host smart-15c99fbe-97af-4896-9268-8445cecb1fe5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138821057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3138821057
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.802824181
Short name T55
Test name
Test status
Simulation time 13108479004 ps
CPU time 6.39 seconds
Started Jun 13 02:16:31 PM PDT 24
Finished Jun 13 02:16:42 PM PDT 24
Peak memory 191820 kb
Host smart-f2292ee1-d01d-4981-a8bb-566f5ebccb1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802824181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.802824181
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1132541363
Short name T410
Test name
Test status
Simulation time 1130067673 ps
CPU time 2.28 seconds
Started Jun 13 02:16:29 PM PDT 24
Finished Jun 13 02:16:37 PM PDT 24
Peak memory 192776 kb
Host smart-7a6e5032-566e-4281-bb75-83f73980f0b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132541363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1132541363
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3365165484
Short name T334
Test name
Test status
Simulation time 436567326 ps
CPU time 1.29 seconds
Started Jun 13 02:16:32 PM PDT 24
Finished Jun 13 02:16:38 PM PDT 24
Peak memory 195520 kb
Host smart-d695e50c-97ab-4ae3-ba66-a6f3e7d4d423
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365165484 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3365165484
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2697303424
Short name T390
Test name
Test status
Simulation time 403165517 ps
CPU time 1.14 seconds
Started Jun 13 02:16:34 PM PDT 24
Finished Jun 13 02:16:40 PM PDT 24
Peak memory 191692 kb
Host smart-f9d05a10-e559-41c6-8924-9bdf0d8303fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697303424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2697303424
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2553858275
Short name T327
Test name
Test status
Simulation time 399793445 ps
CPU time 0.68 seconds
Started Jun 13 02:16:32 PM PDT 24
Finished Jun 13 02:16:37 PM PDT 24
Peak memory 183348 kb
Host smart-3ae14d19-d8c0-4fdd-9f9e-0ee1aade850f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553858275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2553858275
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1233550489
Short name T382
Test name
Test status
Simulation time 426685441 ps
CPU time 0.69 seconds
Started Jun 13 02:16:32 PM PDT 24
Finished Jun 13 02:16:37 PM PDT 24
Peak memory 183264 kb
Host smart-a0863f22-041d-4078-88cb-ccb6b65b231a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233550489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1233550489
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.429384811
Short name T422
Test name
Test status
Simulation time 388257031 ps
CPU time 1 seconds
Started Jun 13 02:16:30 PM PDT 24
Finished Jun 13 02:16:37 PM PDT 24
Peak memory 183332 kb
Host smart-5be9c146-9453-4b59-bdd5-403d17645f41
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429384811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.429384811
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1886591408
Short name T388
Test name
Test status
Simulation time 1089505918 ps
CPU time 1.88 seconds
Started Jun 13 02:16:31 PM PDT 24
Finished Jun 13 02:16:38 PM PDT 24
Peak memory 192848 kb
Host smart-aaf00da5-09c8-4f34-94dd-7b9c2b075fa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886591408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1886591408
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2268587317
Short name T286
Test name
Test status
Simulation time 1317009297 ps
CPU time 2.22 seconds
Started Jun 13 02:16:35 PM PDT 24
Finished Jun 13 02:16:41 PM PDT 24
Peak memory 198212 kb
Host smart-802fc24a-d2d3-4752-9d5d-ec140a471cef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268587317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2268587317
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2002333404
Short name T352
Test name
Test status
Simulation time 4340615329 ps
CPU time 7.57 seconds
Started Jun 13 02:16:32 PM PDT 24
Finished Jun 13 02:16:44 PM PDT 24
Peak memory 196348 kb
Host smart-62abc1b7-3481-4b38-8dd1-d07667d28076
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002333404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2002333404
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3707654213
Short name T348
Test name
Test status
Simulation time 439365047 ps
CPU time 1.15 seconds
Started Jun 13 02:17:03 PM PDT 24
Finished Jun 13 02:17:10 PM PDT 24
Peak memory 183352 kb
Host smart-5c73337c-aae5-4fdb-84ad-88cac4994212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707654213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3707654213
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4004639629
Short name T423
Test name
Test status
Simulation time 508361220 ps
CPU time 1.3 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:17:14 PM PDT 24
Peak memory 183332 kb
Host smart-9a8fa3fa-7ba0-40c2-a52d-e4b93018eee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004639629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.4004639629
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1487502178
Short name T408
Test name
Test status
Simulation time 311618671 ps
CPU time 0.68 seconds
Started Jun 13 02:17:03 PM PDT 24
Finished Jun 13 02:17:10 PM PDT 24
Peak memory 192512 kb
Host smart-3a8c542f-b678-47bc-acf1-bff3bca2d9d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487502178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1487502178
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1073135571
Short name T389
Test name
Test status
Simulation time 456059973 ps
CPU time 0.97 seconds
Started Jun 13 02:17:01 PM PDT 24
Finished Jun 13 02:17:08 PM PDT 24
Peak memory 183336 kb
Host smart-fb64cc77-cf7f-4704-96e7-fc8c926c3c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073135571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1073135571
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.371145331
Short name T351
Test name
Test status
Simulation time 479272706 ps
CPU time 0.84 seconds
Started Jun 13 02:17:02 PM PDT 24
Finished Jun 13 02:17:08 PM PDT 24
Peak memory 183352 kb
Host smart-e2083f71-2cb8-4354-bc92-32c604d1d4c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371145331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.371145331
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.778695415
Short name T300
Test name
Test status
Simulation time 287036856 ps
CPU time 0.91 seconds
Started Jun 13 02:17:02 PM PDT 24
Finished Jun 13 02:17:09 PM PDT 24
Peak memory 183356 kb
Host smart-3af3d85c-e00e-4339-b408-9cde6c738c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778695415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.778695415
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1713464672
Short name T319
Test name
Test status
Simulation time 480591150 ps
CPU time 1.28 seconds
Started Jun 13 02:17:05 PM PDT 24
Finished Jun 13 02:17:12 PM PDT 24
Peak memory 192568 kb
Host smart-78603ece-347a-47de-8bf3-365c8ee07505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713464672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1713464672
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3160559890
Short name T405
Test name
Test status
Simulation time 436890697 ps
CPU time 1.11 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:17:14 PM PDT 24
Peak memory 183332 kb
Host smart-a7d8f897-9b38-4ac9-9858-b4ef0a9b3499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160559890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3160559890
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.391960375
Short name T360
Test name
Test status
Simulation time 333265783 ps
CPU time 0.81 seconds
Started Jun 13 02:17:05 PM PDT 24
Finished Jun 13 02:17:12 PM PDT 24
Peak memory 192564 kb
Host smart-e012feab-c0e4-4f26-a51a-f57365e7e19c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391960375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.391960375
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3870625300
Short name T359
Test name
Test status
Simulation time 356417559 ps
CPU time 0.65 seconds
Started Jun 13 02:17:01 PM PDT 24
Finished Jun 13 02:17:08 PM PDT 24
Peak memory 183352 kb
Host smart-889d65a0-6d54-4cf6-a12f-ad6ed5249394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870625300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3870625300
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2270542970
Short name T37
Test name
Test status
Simulation time 575357081 ps
CPU time 1.54 seconds
Started Jun 13 02:16:31 PM PDT 24
Finished Jun 13 02:16:38 PM PDT 24
Peak memory 196004 kb
Host smart-f052efe3-2560-4ef3-b051-e73e22a2bbb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270542970 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2270542970
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2905940389
Short name T365
Test name
Test status
Simulation time 585605188 ps
CPU time 0.66 seconds
Started Jun 13 02:16:36 PM PDT 24
Finished Jun 13 02:16:43 PM PDT 24
Peak memory 183704 kb
Host smart-6d668554-e55f-4e87-b501-b61081ee6b6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905940389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2905940389
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1474527348
Short name T379
Test name
Test status
Simulation time 540826414 ps
CPU time 0.71 seconds
Started Jun 13 02:16:34 PM PDT 24
Finished Jun 13 02:16:39 PM PDT 24
Peak memory 192584 kb
Host smart-437b1824-d735-4979-b13e-5082dc2211b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474527348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1474527348
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2704793066
Short name T419
Test name
Test status
Simulation time 2738580168 ps
CPU time 3.74 seconds
Started Jun 13 02:16:32 PM PDT 24
Finished Jun 13 02:16:40 PM PDT 24
Peak memory 194184 kb
Host smart-b6744a56-21fe-4831-81af-ba214d624ce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704793066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2704793066
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2576474061
Short name T306
Test name
Test status
Simulation time 548696574 ps
CPU time 2.68 seconds
Started Jun 13 02:16:34 PM PDT 24
Finished Jun 13 02:16:41 PM PDT 24
Peak memory 198212 kb
Host smart-a8e4da0b-b708-4ba0-987e-75a817a47275
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576474061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2576474061
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2323049456
Short name T193
Test name
Test status
Simulation time 8177948409 ps
CPU time 6.88 seconds
Started Jun 13 02:16:29 PM PDT 24
Finished Jun 13 02:16:42 PM PDT 24
Peak memory 198004 kb
Host smart-a3285025-fca3-455d-895c-37adc3b09138
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323049456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2323049456
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.140276480
Short name T293
Test name
Test status
Simulation time 473414393 ps
CPU time 0.88 seconds
Started Jun 13 02:16:39 PM PDT 24
Finished Jun 13 02:16:46 PM PDT 24
Peak memory 195648 kb
Host smart-f60ad6b2-c508-4f10-971c-5fd74f1820a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140276480 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.140276480
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4277957408
Short name T326
Test name
Test status
Simulation time 396634069 ps
CPU time 0.7 seconds
Started Jun 13 02:16:36 PM PDT 24
Finished Jun 13 02:16:43 PM PDT 24
Peak memory 183512 kb
Host smart-a28f54ec-23bf-434c-b3a0-5216f58af4f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277957408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.4277957408
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1103685168
Short name T349
Test name
Test status
Simulation time 435555700 ps
CPU time 0.62 seconds
Started Jun 13 02:16:31 PM PDT 24
Finished Jun 13 02:16:37 PM PDT 24
Peak memory 192560 kb
Host smart-4f22c28d-57c8-4760-bbd0-84713875e391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103685168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1103685168
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3903019410
Short name T370
Test name
Test status
Simulation time 2446309304 ps
CPU time 0.92 seconds
Started Jun 13 02:16:36 PM PDT 24
Finished Jun 13 02:16:42 PM PDT 24
Peak memory 193404 kb
Host smart-35fd3fd1-ca15-4b24-9d7c-4e2e5f2dc276
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903019410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3903019410
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1699063404
Short name T290
Test name
Test status
Simulation time 469242976 ps
CPU time 1.73 seconds
Started Jun 13 02:16:36 PM PDT 24
Finished Jun 13 02:16:44 PM PDT 24
Peak memory 198204 kb
Host smart-bb0d0b7b-1e57-4bb7-ad1c-fba1b056f485
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699063404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1699063404
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.359300385
Short name T413
Test name
Test status
Simulation time 4675410024 ps
CPU time 1.85 seconds
Started Jun 13 02:16:35 PM PDT 24
Finished Jun 13 02:16:40 PM PDT 24
Peak memory 197168 kb
Host smart-e480ed5e-aebb-4978-b331-087819d2758f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359300385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.359300385
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.930372666
Short name T296
Test name
Test status
Simulation time 541826226 ps
CPU time 0.9 seconds
Started Jun 13 02:16:37 PM PDT 24
Finished Jun 13 02:16:44 PM PDT 24
Peak memory 195876 kb
Host smart-2293000d-6322-4bcc-9a39-500307601e4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930372666 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.930372666
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.581306004
Short name T61
Test name
Test status
Simulation time 397893661 ps
CPU time 0.72 seconds
Started Jun 13 02:16:38 PM PDT 24
Finished Jun 13 02:16:45 PM PDT 24
Peak memory 192628 kb
Host smart-1ace38c2-ffdd-496f-846f-513762f4f632
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581306004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.581306004
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2572534650
Short name T341
Test name
Test status
Simulation time 433854852 ps
CPU time 0.62 seconds
Started Jun 13 02:16:36 PM PDT 24
Finished Jun 13 02:16:42 PM PDT 24
Peak memory 183368 kb
Host smart-8400af21-1e25-47a7-8f64-6c41dc68db36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572534650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2572534650
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3103353182
Short name T344
Test name
Test status
Simulation time 2105537672 ps
CPU time 2.04 seconds
Started Jun 13 02:16:42 PM PDT 24
Finished Jun 13 02:16:50 PM PDT 24
Peak memory 192688 kb
Host smart-1f3d2f4d-d11b-465d-9ac1-3f2cac692f88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103353182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3103353182
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.170786850
Short name T353
Test name
Test status
Simulation time 1207621967 ps
CPU time 2.26 seconds
Started Jun 13 02:16:37 PM PDT 24
Finished Jun 13 02:16:45 PM PDT 24
Peak memory 198196 kb
Host smart-dd456926-e588-401d-ad1e-9a17ca2c3a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170786850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.170786850
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3163995061
Short name T383
Test name
Test status
Simulation time 4352411421 ps
CPU time 7.36 seconds
Started Jun 13 02:16:36 PM PDT 24
Finished Jun 13 02:16:50 PM PDT 24
Peak memory 197500 kb
Host smart-2e7ea57b-1a03-402a-92e3-3f1be8eb238d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163995061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3163995061
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3112779650
Short name T311
Test name
Test status
Simulation time 483222855 ps
CPU time 0.94 seconds
Started Jun 13 02:16:37 PM PDT 24
Finished Jun 13 02:16:43 PM PDT 24
Peak memory 194892 kb
Host smart-0de66258-d12a-43e9-ba20-ce8dd06b1d7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112779650 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3112779650
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2647197156
Short name T394
Test name
Test status
Simulation time 474253957 ps
CPU time 1.3 seconds
Started Jun 13 02:16:36 PM PDT 24
Finished Jun 13 02:16:43 PM PDT 24
Peak memory 192688 kb
Host smart-91de335d-8583-452c-a49b-a9b17d310794
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647197156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2647197156
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1283980848
Short name T287
Test name
Test status
Simulation time 490759264 ps
CPU time 0.67 seconds
Started Jun 13 02:16:39 PM PDT 24
Finished Jun 13 02:16:45 PM PDT 24
Peak memory 183348 kb
Host smart-7d2c56cf-e299-4862-bcb7-d9f8270a6fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283980848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1283980848
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4052346911
Short name T345
Test name
Test status
Simulation time 2446954581 ps
CPU time 2.86 seconds
Started Jun 13 02:16:36 PM PDT 24
Finished Jun 13 02:16:44 PM PDT 24
Peak memory 191684 kb
Host smart-9b867907-e831-428b-92d5-405be3d2dce0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052346911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4052346911
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2376158808
Short name T377
Test name
Test status
Simulation time 409805407 ps
CPU time 1.28 seconds
Started Jun 13 02:16:37 PM PDT 24
Finished Jun 13 02:16:45 PM PDT 24
Peak memory 198064 kb
Host smart-b57674f4-2653-4dcd-8e59-87cb1b3718bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376158808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2376158808
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3434038214
Short name T397
Test name
Test status
Simulation time 4088416064 ps
CPU time 5.52 seconds
Started Jun 13 02:16:37 PM PDT 24
Finished Jun 13 02:16:48 PM PDT 24
Peak memory 197168 kb
Host smart-e164745d-fc47-4b4c-b97b-efd3fe4e005c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434038214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3434038214
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.210855784
Short name T295
Test name
Test status
Simulation time 438740329 ps
CPU time 0.96 seconds
Started Jun 13 02:16:38 PM PDT 24
Finished Jun 13 02:16:45 PM PDT 24
Peak memory 197528 kb
Host smart-4dfc151f-8a7e-4d57-8ab2-a477a125245d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210855784 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.210855784
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2365997267
Short name T72
Test name
Test status
Simulation time 379039263 ps
CPU time 1.15 seconds
Started Jun 13 02:16:37 PM PDT 24
Finished Jun 13 02:16:44 PM PDT 24
Peak memory 192704 kb
Host smart-79e295f7-fcbe-4152-ad9b-344c8ff5e47a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365997267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2365997267
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3919001579
Short name T373
Test name
Test status
Simulation time 510595153 ps
CPU time 0.69 seconds
Started Jun 13 02:16:39 PM PDT 24
Finished Jun 13 02:16:45 PM PDT 24
Peak memory 183344 kb
Host smart-22a405f3-ed9e-4694-bfa8-360e0f3e3918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919001579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3919001579
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.598900298
Short name T354
Test name
Test status
Simulation time 2168432094 ps
CPU time 1.69 seconds
Started Jun 13 02:16:37 PM PDT 24
Finished Jun 13 02:16:44 PM PDT 24
Peak memory 193532 kb
Host smart-d6531f5d-cffd-44a8-bf38-192611e5633b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598900298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.598900298
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2394655966
Short name T316
Test name
Test status
Simulation time 760782450 ps
CPU time 1.71 seconds
Started Jun 13 02:16:37 PM PDT 24
Finished Jun 13 02:16:45 PM PDT 24
Peak memory 198164 kb
Host smart-7a90100b-5869-409c-a88c-677b7f39ff54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394655966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2394655966
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2558219857
Short name T278
Test name
Test status
Simulation time 9062895457 ps
CPU time 4.1 seconds
Started Jun 13 02:07:01 PM PDT 24
Finished Jun 13 02:07:06 PM PDT 24
Peak memory 192452 kb
Host smart-823fb1fe-7367-478e-8d02-2e62c89a89ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558219857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2558219857
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1889634749
Short name T205
Test name
Test status
Simulation time 549264432 ps
CPU time 0.85 seconds
Started Jun 13 02:06:56 PM PDT 24
Finished Jun 13 02:06:57 PM PDT 24
Peak memory 197176 kb
Host smart-82d6e2d6-7487-4e73-8ba4-79ac0291853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889634749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1889634749
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.326899248
Short name T201
Test name
Test status
Simulation time 21521806232 ps
CPU time 15.95 seconds
Started Jun 13 02:06:58 PM PDT 24
Finished Jun 13 02:07:15 PM PDT 24
Peak memory 192484 kb
Host smart-ba4db25d-3306-4b3e-9c46-2c7316523191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326899248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.326899248
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.213628408
Short name T22
Test name
Test status
Simulation time 4102844942 ps
CPU time 6.78 seconds
Started Jun 13 02:06:59 PM PDT 24
Finished Jun 13 02:07:06 PM PDT 24
Peak memory 216016 kb
Host smart-417f785e-d8a9-4725-bfb8-22a13e276277
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213628408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.213628408
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1290009503
Short name T261
Test name
Test status
Simulation time 595904830 ps
CPU time 1.5 seconds
Started Jun 13 02:06:59 PM PDT 24
Finished Jun 13 02:07:02 PM PDT 24
Peak memory 192372 kb
Host smart-91318fa8-58fd-489f-a829-520e9e980afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290009503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1290009503
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2757674100
Short name T218
Test name
Test status
Simulation time 45850407357 ps
CPU time 69.14 seconds
Started Jun 13 02:07:10 PM PDT 24
Finished Jun 13 02:08:21 PM PDT 24
Peak memory 192484 kb
Host smart-d49fd257-db42-4f76-8ee4-55e9102d6064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757674100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2757674100
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3235042513
Short name T269
Test name
Test status
Simulation time 498171408 ps
CPU time 1.31 seconds
Started Jun 13 02:07:09 PM PDT 24
Finished Jun 13 02:07:11 PM PDT 24
Peak memory 197140 kb
Host smart-d8f83eec-13b6-4cb3-8a7c-9a1a99a24fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235042513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3235042513
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2301808973
Short name T173
Test name
Test status
Simulation time 398829097 ps
CPU time 1.02 seconds
Started Jun 13 02:07:10 PM PDT 24
Finished Jun 13 02:07:13 PM PDT 24
Peak memory 197108 kb
Host smart-3a3087b7-980a-452b-a7ad-f7792024095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301808973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2301808973
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.4195369859
Short name T3
Test name
Test status
Simulation time 35817225155 ps
CPU time 48.48 seconds
Started Jun 13 02:07:09 PM PDT 24
Finished Jun 13 02:07:59 PM PDT 24
Peak memory 192416 kb
Host smart-c2dfea36-4c42-4242-859f-b22fe786b303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195369859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.4195369859
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2006789978
Short name T268
Test name
Test status
Simulation time 556171510 ps
CPU time 1.39 seconds
Started Jun 13 02:07:09 PM PDT 24
Finished Jun 13 02:07:12 PM PDT 24
Peak memory 197176 kb
Host smart-8ef4c698-6734-410e-a4e6-9a1122c895dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006789978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2006789978
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.50501426
Short name T249
Test name
Test status
Simulation time 44947627654 ps
CPU time 35.96 seconds
Started Jun 13 02:07:09 PM PDT 24
Finished Jun 13 02:07:47 PM PDT 24
Peak memory 192476 kb
Host smart-342e5b23-56b6-4139-a866-e788883518dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50501426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.50501426
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.986114746
Short name T231
Test name
Test status
Simulation time 487121007 ps
CPU time 1.29 seconds
Started Jun 13 02:07:12 PM PDT 24
Finished Jun 13 02:07:14 PM PDT 24
Peak memory 192348 kb
Host smart-248aefb8-918e-4b5f-8dbc-9757b9cc192c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986114746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.986114746
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.4294571372
Short name T207
Test name
Test status
Simulation time 19628542041 ps
CPU time 31.72 seconds
Started Jun 13 02:07:14 PM PDT 24
Finished Jun 13 02:07:48 PM PDT 24
Peak memory 192476 kb
Host smart-114ccf56-2423-43bb-b45e-fcef70d5b1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294571372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.4294571372
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1175479676
Short name T248
Test name
Test status
Simulation time 529241106 ps
CPU time 1.31 seconds
Started Jun 13 02:07:17 PM PDT 24
Finished Jun 13 02:07:19 PM PDT 24
Peak memory 192364 kb
Host smart-e6309c08-a99c-4a61-9c57-05f512c4a917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175479676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1175479676
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.532061739
Short name T12
Test name
Test status
Simulation time 23824526359 ps
CPU time 17.56 seconds
Started Jun 13 02:07:14 PM PDT 24
Finished Jun 13 02:07:32 PM PDT 24
Peak memory 192464 kb
Host smart-51b1ee64-7d03-4e1f-a476-8923067b385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532061739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.532061739
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2389988337
Short name T276
Test name
Test status
Simulation time 384115571 ps
CPU time 0.81 seconds
Started Jun 13 02:07:14 PM PDT 24
Finished Jun 13 02:07:17 PM PDT 24
Peak memory 197104 kb
Host smart-b845b4af-f369-4e53-bc96-ace4088f935d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389988337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2389988337
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2053471664
Short name T229
Test name
Test status
Simulation time 14367161422 ps
CPU time 5.12 seconds
Started Jun 13 02:07:16 PM PDT 24
Finished Jun 13 02:07:22 PM PDT 24
Peak memory 192440 kb
Host smart-18399a54-3efd-43dd-ae93-31151ea63814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053471664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2053471664
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1435913898
Short name T44
Test name
Test status
Simulation time 600248597 ps
CPU time 0.79 seconds
Started Jun 13 02:07:14 PM PDT 24
Finished Jun 13 02:07:17 PM PDT 24
Peak memory 192352 kb
Host smart-54baa66c-3da2-4d7b-9266-4735b5a9e68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435913898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1435913898
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.954789981
Short name T237
Test name
Test status
Simulation time 7403583512 ps
CPU time 1.21 seconds
Started Jun 13 02:07:21 PM PDT 24
Finished Jun 13 02:07:23 PM PDT 24
Peak memory 192464 kb
Host smart-45f17779-f919-4716-bc48-778031f06bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954789981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.954789981
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.308199819
Short name T219
Test name
Test status
Simulation time 582498999 ps
CPU time 0.77 seconds
Started Jun 13 02:07:21 PM PDT 24
Finished Jun 13 02:07:23 PM PDT 24
Peak memory 197124 kb
Host smart-ff0757f3-1c90-4b79-93a0-085e33d6b07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308199819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.308199819
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2726356527
Short name T243
Test name
Test status
Simulation time 27313208593 ps
CPU time 10.9 seconds
Started Jun 13 02:07:23 PM PDT 24
Finished Jun 13 02:07:35 PM PDT 24
Peak memory 192476 kb
Host smart-a5c39cef-2fb0-42b4-bcc9-fcb3f7201c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726356527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2726356527
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1732525271
Short name T200
Test name
Test status
Simulation time 407566635 ps
CPU time 0.74 seconds
Started Jun 13 02:07:20 PM PDT 24
Finished Jun 13 02:07:22 PM PDT 24
Peak memory 192356 kb
Host smart-aea53057-0beb-46e9-8f1b-238216333dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732525271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1732525271
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2239213268
Short name T236
Test name
Test status
Simulation time 35394485054 ps
CPU time 55.57 seconds
Started Jun 13 02:07:23 PM PDT 24
Finished Jun 13 02:08:20 PM PDT 24
Peak memory 192464 kb
Host smart-9276eae5-933e-450b-9892-7cb193559555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239213268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2239213268
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1416746176
Short name T252
Test name
Test status
Simulation time 358680386 ps
CPU time 1.06 seconds
Started Jun 13 02:07:23 PM PDT 24
Finished Jun 13 02:07:25 PM PDT 24
Peak memory 192368 kb
Host smart-e4622736-09f0-4ce6-9493-b3e9e3dc5a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416746176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1416746176
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.304674679
Short name T267
Test name
Test status
Simulation time 29124326361 ps
CPU time 10.91 seconds
Started Jun 13 02:07:23 PM PDT 24
Finished Jun 13 02:07:35 PM PDT 24
Peak memory 192400 kb
Host smart-5e0b93d4-e476-431c-b1c8-0053feaf3d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304674679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.304674679
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3815728990
Short name T206
Test name
Test status
Simulation time 328345763 ps
CPU time 1.09 seconds
Started Jun 13 02:07:22 PM PDT 24
Finished Jun 13 02:07:24 PM PDT 24
Peak memory 197176 kb
Host smart-1aa2828d-c1d7-406a-81dc-dcfc3f2053f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815728990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3815728990
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2466967520
Short name T241
Test name
Test status
Simulation time 9757782957 ps
CPU time 14.54 seconds
Started Jun 13 02:06:58 PM PDT 24
Finished Jun 13 02:07:14 PM PDT 24
Peak memory 192452 kb
Host smart-31f247c2-0e89-40ec-939e-0f355c6eef46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466967520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2466967520
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1200331842
Short name T21
Test name
Test status
Simulation time 8357215278 ps
CPU time 3.68 seconds
Started Jun 13 02:06:58 PM PDT 24
Finished Jun 13 02:07:03 PM PDT 24
Peak memory 216520 kb
Host smart-4c99259e-e0d6-4c0e-954e-99fd35062584
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200331842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1200331842
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1059199360
Short name T203
Test name
Test status
Simulation time 422358538 ps
CPU time 1.2 seconds
Started Jun 13 02:06:58 PM PDT 24
Finished Jun 13 02:07:00 PM PDT 24
Peak memory 192328 kb
Host smart-3a6d8d95-9b82-4d57-9c17-c4f3d9c2b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059199360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1059199360
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.136605803
Short name T50
Test name
Test status
Simulation time 76492606407 ps
CPU time 115.79 seconds
Started Jun 13 02:07:00 PM PDT 24
Finished Jun 13 02:08:56 PM PDT 24
Peak memory 198772 kb
Host smart-4d0dc233-e8f5-4122-9fb9-bd3e9a599945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136605803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.136605803
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.521567574
Short name T238
Test name
Test status
Simulation time 17918897502 ps
CPU time 22.41 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:07:54 PM PDT 24
Peak memory 192432 kb
Host smart-c0d2ea69-6ccc-437d-94a9-e8c56412eb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521567574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.521567574
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3901008236
Short name T283
Test name
Test status
Simulation time 544207034 ps
CPU time 1.37 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:07:32 PM PDT 24
Peak memory 192328 kb
Host smart-a23a3feb-6738-438d-9bb9-660e40796658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901008236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3901008236
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1817106066
Short name T187
Test name
Test status
Simulation time 63908421573 ps
CPU time 333.94 seconds
Started Jun 13 02:07:28 PM PDT 24
Finished Jun 13 02:13:03 PM PDT 24
Peak memory 215040 kb
Host smart-6f36a355-06df-4abb-b589-7ee59b4ff7b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817106066 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1817106066
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2894576089
Short name T227
Test name
Test status
Simulation time 20583787444 ps
CPU time 8.32 seconds
Started Jun 13 02:07:27 PM PDT 24
Finished Jun 13 02:07:37 PM PDT 24
Peak memory 192484 kb
Host smart-edece5a8-1679-4f9d-a2e1-317d9f9108d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894576089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2894576089
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2896248816
Short name T275
Test name
Test status
Simulation time 609231721 ps
CPU time 0.78 seconds
Started Jun 13 02:07:28 PM PDT 24
Finished Jun 13 02:07:31 PM PDT 24
Peak memory 192344 kb
Host smart-75003811-4d20-4033-b8dd-dae138be0937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896248816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2896248816
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2273504961
Short name T215
Test name
Test status
Simulation time 405363136445 ps
CPU time 643.6 seconds
Started Jun 13 02:07:28 PM PDT 24
Finished Jun 13 02:18:13 PM PDT 24
Peak memory 198808 kb
Host smart-6df6962e-8d48-4054-bf23-cbfcb1c06d76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273504961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2273504961
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3401461979
Short name T211
Test name
Test status
Simulation time 12395875641 ps
CPU time 19.53 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:07:51 PM PDT 24
Peak memory 192428 kb
Host smart-ef7068f2-0b16-4573-9f54-ed37b90d2a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401461979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3401461979
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1642274340
Short name T224
Test name
Test status
Simulation time 554733891 ps
CPU time 0.94 seconds
Started Jun 13 02:07:28 PM PDT 24
Finished Jun 13 02:07:31 PM PDT 24
Peak memory 192344 kb
Host smart-f29c9150-66ff-4fed-ae16-ca85286d77ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642274340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1642274340
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1708476590
Short name T190
Test name
Test status
Simulation time 478814518 ps
CPU time 1.2 seconds
Started Jun 13 02:07:27 PM PDT 24
Finished Jun 13 02:07:30 PM PDT 24
Peak memory 197120 kb
Host smart-1380e80f-f912-4b74-865e-cd8a3a78ba6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708476590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1708476590
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.86811189
Short name T274
Test name
Test status
Simulation time 25025948489 ps
CPU time 17.56 seconds
Started Jun 13 02:07:30 PM PDT 24
Finished Jun 13 02:07:50 PM PDT 24
Peak memory 192476 kb
Host smart-7a5fe1e8-8130-4907-977d-cf42e29f14b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86811189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.86811189
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2263065146
Short name T279
Test name
Test status
Simulation time 517839192 ps
CPU time 0.75 seconds
Started Jun 13 02:07:30 PM PDT 24
Finished Jun 13 02:07:33 PM PDT 24
Peak memory 197152 kb
Host smart-e6627232-4509-4063-bb24-54cacc783fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263065146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2263065146
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2650924975
Short name T253
Test name
Test status
Simulation time 5400148848 ps
CPU time 2.91 seconds
Started Jun 13 02:07:27 PM PDT 24
Finished Jun 13 02:07:31 PM PDT 24
Peak memory 192368 kb
Host smart-0fa4c12d-7147-4450-b8d5-bc29ec021fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650924975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2650924975
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1641187326
Short name T265
Test name
Test status
Simulation time 401873529 ps
CPU time 0.72 seconds
Started Jun 13 02:07:28 PM PDT 24
Finished Jun 13 02:07:31 PM PDT 24
Peak memory 197152 kb
Host smart-b51a2467-d78f-4b5c-a0cc-786b06f725ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641187326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1641187326
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2504627225
Short name T198
Test name
Test status
Simulation time 16502502893 ps
CPU time 6.05 seconds
Started Jun 13 02:07:31 PM PDT 24
Finished Jun 13 02:07:40 PM PDT 24
Peak memory 192464 kb
Host smart-a6d29425-7dcf-4a84-b0c0-ed7afdda163a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504627225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2504627225
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4203761807
Short name T277
Test name
Test status
Simulation time 370448923 ps
CPU time 0.86 seconds
Started Jun 13 02:07:26 PM PDT 24
Finished Jun 13 02:07:28 PM PDT 24
Peak memory 197156 kb
Host smart-7ab3a810-05f4-44a5-ae7a-b9d285eaf51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203761807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4203761807
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1081893898
Short name T254
Test name
Test status
Simulation time 15533672962 ps
CPU time 21.14 seconds
Started Jun 13 02:07:30 PM PDT 24
Finished Jun 13 02:07:54 PM PDT 24
Peak memory 192464 kb
Host smart-de71aadc-1961-4186-9f0e-82f5a112d033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081893898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1081893898
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3195553591
Short name T259
Test name
Test status
Simulation time 419878200 ps
CPU time 0.79 seconds
Started Jun 13 02:07:27 PM PDT 24
Finished Jun 13 02:07:29 PM PDT 24
Peak memory 192368 kb
Host smart-c131135b-1c1f-4369-90ea-58dcdc3748ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195553591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3195553591
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2673520617
Short name T162
Test name
Test status
Simulation time 476110157 ps
CPU time 1.35 seconds
Started Jun 13 02:07:27 PM PDT 24
Finished Jun 13 02:07:29 PM PDT 24
Peak memory 197088 kb
Host smart-61c71bd5-7431-4d17-a23e-f89d386fd770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673520617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2673520617
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.64874351
Short name T197
Test name
Test status
Simulation time 14192996095 ps
CPU time 20.35 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:07:51 PM PDT 24
Peak memory 192492 kb
Host smart-29bd4690-7748-4006-91c5-5edee7277519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64874351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.64874351
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1783025082
Short name T266
Test name
Test status
Simulation time 411106344 ps
CPU time 0.73 seconds
Started Jun 13 02:07:29 PM PDT 24
Finished Jun 13 02:07:32 PM PDT 24
Peak memory 192340 kb
Host smart-dc565c1f-be5c-4a3c-8418-e05294794788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783025082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1783025082
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.899164418
Short name T7
Test name
Test status
Simulation time 16931870336 ps
CPU time 24.09 seconds
Started Jun 13 02:07:28 PM PDT 24
Finished Jun 13 02:07:54 PM PDT 24
Peak memory 192428 kb
Host smart-6d4f80dc-d385-4894-b724-a460c48fd83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899164418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.899164418
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2282556065
Short name T240
Test name
Test status
Simulation time 490630566 ps
CPU time 0.79 seconds
Started Jun 13 02:07:30 PM PDT 24
Finished Jun 13 02:07:33 PM PDT 24
Peak memory 192328 kb
Host smart-af3fb47f-407e-499a-80fb-e0c96fa31579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282556065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2282556065
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2620489894
Short name T204
Test name
Test status
Simulation time 3924105272 ps
CPU time 3.27 seconds
Started Jun 13 02:07:32 PM PDT 24
Finished Jun 13 02:07:38 PM PDT 24
Peak memory 192432 kb
Host smart-17e4f50d-4007-4f6e-8e55-b20d1baf6b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620489894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2620489894
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1860892047
Short name T284
Test name
Test status
Simulation time 441237829 ps
CPU time 0.74 seconds
Started Jun 13 02:07:27 PM PDT 24
Finished Jun 13 02:07:28 PM PDT 24
Peak memory 192352 kb
Host smart-19158f67-6de7-4d46-9780-79d9e50dc03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860892047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1860892047
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1926315251
Short name T246
Test name
Test status
Simulation time 20066478980 ps
CPU time 27.56 seconds
Started Jun 13 02:07:00 PM PDT 24
Finished Jun 13 02:07:28 PM PDT 24
Peak memory 192448 kb
Host smart-2693f93d-4293-4d48-9f37-9df7f9eaeae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926315251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1926315251
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3017227083
Short name T17
Test name
Test status
Simulation time 4084369079 ps
CPU time 6.06 seconds
Started Jun 13 02:07:08 PM PDT 24
Finished Jun 13 02:07:14 PM PDT 24
Peak memory 216060 kb
Host smart-950a2155-ec20-4712-8056-50d74a9714a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017227083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3017227083
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.225747646
Short name T208
Test name
Test status
Simulation time 502346112 ps
CPU time 0.67 seconds
Started Jun 13 02:06:57 PM PDT 24
Finished Jun 13 02:06:58 PM PDT 24
Peak memory 192320 kb
Host smart-b536bc5f-bc67-48ca-a610-940f3ee97416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225747646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.225747646
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4202217643
Short name T226
Test name
Test status
Simulation time 31168639876 ps
CPU time 48.88 seconds
Started Jun 13 02:07:32 PM PDT 24
Finished Jun 13 02:08:24 PM PDT 24
Peak memory 192432 kb
Host smart-e7a84a14-3bd1-4c60-a72a-71df618fc098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202217643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4202217643
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.951364747
Short name T199
Test name
Test status
Simulation time 596494749 ps
CPU time 0.76 seconds
Started Jun 13 02:07:30 PM PDT 24
Finished Jun 13 02:07:33 PM PDT 24
Peak memory 192256 kb
Host smart-524f836c-d977-44f5-89da-62a4fc1b0ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951364747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.951364747
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.874023601
Short name T247
Test name
Test status
Simulation time 4413918207 ps
CPU time 4.1 seconds
Started Jun 13 02:07:35 PM PDT 24
Finished Jun 13 02:07:42 PM PDT 24
Peak memory 192456 kb
Host smart-232b0ec9-bbff-4410-bb99-0ff8be7b3444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874023601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.874023601
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2997793343
Short name T245
Test name
Test status
Simulation time 637186692 ps
CPU time 0.69 seconds
Started Jun 13 02:07:34 PM PDT 24
Finished Jun 13 02:07:37 PM PDT 24
Peak memory 192352 kb
Host smart-42b033f9-9959-4315-98d7-b3eaf0ef111f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997793343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2997793343
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.611241325
Short name T222
Test name
Test status
Simulation time 39440012599 ps
CPU time 7.96 seconds
Started Jun 13 02:07:32 PM PDT 24
Finished Jun 13 02:07:43 PM PDT 24
Peak memory 192464 kb
Host smart-98d20a50-c9e6-4c06-8bca-5de23baf144d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611241325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.611241325
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1079014527
Short name T214
Test name
Test status
Simulation time 406068010 ps
CPU time 0.72 seconds
Started Jun 13 02:07:33 PM PDT 24
Finished Jun 13 02:07:36 PM PDT 24
Peak memory 192300 kb
Host smart-8d7b061d-a133-445e-ab0e-4e1858412a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079014527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1079014527
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.599868570
Short name T228
Test name
Test status
Simulation time 18671938369 ps
CPU time 12.88 seconds
Started Jun 13 02:07:35 PM PDT 24
Finished Jun 13 02:07:50 PM PDT 24
Peak memory 192408 kb
Host smart-d5bc0691-2984-44fb-8fc1-fc5ca37fc443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599868570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.599868570
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3739243882
Short name T235
Test name
Test status
Simulation time 523134566 ps
CPU time 1.06 seconds
Started Jun 13 02:07:35 PM PDT 24
Finished Jun 13 02:07:38 PM PDT 24
Peak memory 192332 kb
Host smart-dd96be67-94bf-49ed-bc7f-c6d8287ad17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739243882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3739243882
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1343186970
Short name T242
Test name
Test status
Simulation time 24419767256 ps
CPU time 3.77 seconds
Started Jun 13 02:07:35 PM PDT 24
Finished Jun 13 02:07:41 PM PDT 24
Peak memory 192432 kb
Host smart-88ad7d7f-b4dc-4116-9c87-dacad15b8447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343186970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1343186970
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1444696476
Short name T212
Test name
Test status
Simulation time 435054427 ps
CPU time 0.72 seconds
Started Jun 13 02:07:34 PM PDT 24
Finished Jun 13 02:07:37 PM PDT 24
Peak memory 197160 kb
Host smart-b0627fce-7ace-44e4-b1f4-e600c6808f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444696476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1444696476
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1340496602
Short name T28
Test name
Test status
Simulation time 10908983041 ps
CPU time 16.05 seconds
Started Jun 13 02:07:33 PM PDT 24
Finished Jun 13 02:07:52 PM PDT 24
Peak memory 192452 kb
Host smart-49ca7dd6-0ee8-44e7-a3b7-6df710be428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340496602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1340496602
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1982943251
Short name T47
Test name
Test status
Simulation time 484676631 ps
CPU time 0.81 seconds
Started Jun 13 02:07:34 PM PDT 24
Finished Jun 13 02:07:37 PM PDT 24
Peak memory 192356 kb
Host smart-ea2c1fae-c1b1-4c21-9aef-b1bce2ef97b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982943251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1982943251
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.4189041370
Short name T196
Test name
Test status
Simulation time 58661898734 ps
CPU time 17.72 seconds
Started Jun 13 02:07:42 PM PDT 24
Finished Jun 13 02:08:01 PM PDT 24
Peak memory 197440 kb
Host smart-b7fb5069-9f1b-4629-a5d5-a1b76775e50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189041370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.4189041370
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3198784103
Short name T232
Test name
Test status
Simulation time 444742414 ps
CPU time 0.77 seconds
Started Jun 13 02:07:39 PM PDT 24
Finished Jun 13 02:07:42 PM PDT 24
Peak memory 192352 kb
Host smart-be76884b-9899-4511-b0dd-7273efa3f519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198784103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3198784103
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2703823880
Short name T233
Test name
Test status
Simulation time 38999365074 ps
CPU time 17.56 seconds
Started Jun 13 02:07:41 PM PDT 24
Finished Jun 13 02:08:00 PM PDT 24
Peak memory 192436 kb
Host smart-4db0a8e0-255e-4a4a-a847-3d7784cd582e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703823880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2703823880
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3671282819
Short name T220
Test name
Test status
Simulation time 491366611 ps
CPU time 1.32 seconds
Started Jun 13 02:07:42 PM PDT 24
Finished Jun 13 02:07:45 PM PDT 24
Peak memory 197116 kb
Host smart-13128ca7-9cba-46c8-a96a-6465d96b9e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671282819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3671282819
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2832609179
Short name T172
Test name
Test status
Simulation time 388787308 ps
CPU time 1.31 seconds
Started Jun 13 02:07:53 PM PDT 24
Finished Jun 13 02:07:57 PM PDT 24
Peak memory 197100 kb
Host smart-4ad3af4f-86ff-478e-a86a-62c84db39d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832609179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2832609179
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3362913640
Short name T260
Test name
Test status
Simulation time 47425566652 ps
CPU time 33.79 seconds
Started Jun 13 02:07:41 PM PDT 24
Finished Jun 13 02:08:16 PM PDT 24
Peak memory 192476 kb
Host smart-99f2ad06-7d86-45f5-9908-b43c6f6dd598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362913640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3362913640
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.620370818
Short name T45
Test name
Test status
Simulation time 485364046 ps
CPU time 0.9 seconds
Started Jun 13 02:07:41 PM PDT 24
Finished Jun 13 02:07:44 PM PDT 24
Peak memory 197132 kb
Host smart-f749cc7f-2a0a-4422-bab5-7b49ee0b9741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620370818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.620370818
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.899097930
Short name T216
Test name
Test status
Simulation time 7886506608 ps
CPU time 5.94 seconds
Started Jun 13 02:07:53 PM PDT 24
Finished Jun 13 02:08:02 PM PDT 24
Peak memory 192452 kb
Host smart-234f2fec-a7d6-4127-8589-799b2fdd920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899097930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.899097930
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.4144840220
Short name T273
Test name
Test status
Simulation time 412110899 ps
CPU time 1.27 seconds
Started Jun 13 02:07:53 PM PDT 24
Finished Jun 13 02:07:57 PM PDT 24
Peak memory 192352 kb
Host smart-a4232397-f881-4398-b507-4c1d8960cef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144840220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.4144840220
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_jump.902195588
Short name T177
Test name
Test status
Simulation time 378681568 ps
CPU time 1.13 seconds
Started Jun 13 02:07:06 PM PDT 24
Finished Jun 13 02:07:08 PM PDT 24
Peak memory 197100 kb
Host smart-b1a3bfb8-ba5a-4898-b247-ff6670910565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902195588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.902195588
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3611992286
Short name T225
Test name
Test status
Simulation time 24532903789 ps
CPU time 10.58 seconds
Started Jun 13 02:07:06 PM PDT 24
Finished Jun 13 02:07:18 PM PDT 24
Peak memory 192424 kb
Host smart-b76ac9b3-0ab3-4731-ac4e-1913be9cb107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611992286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3611992286
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.795865068
Short name T18
Test name
Test status
Simulation time 8629217312 ps
CPU time 14.05 seconds
Started Jun 13 02:07:09 PM PDT 24
Finished Jun 13 02:07:24 PM PDT 24
Peak memory 216484 kb
Host smart-0c4d1a89-42e4-444a-abc9-92636c31eb53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795865068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.795865068
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.707615109
Short name T9
Test name
Test status
Simulation time 553090112 ps
CPU time 0.97 seconds
Started Jun 13 02:07:07 PM PDT 24
Finished Jun 13 02:07:09 PM PDT 24
Peak memory 192364 kb
Host smart-8103b394-42d0-407c-aef7-72ca7ea05a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707615109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.707615109
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3598555508
Short name T282
Test name
Test status
Simulation time 23315645156 ps
CPU time 35.39 seconds
Started Jun 13 02:07:47 PM PDT 24
Finished Jun 13 02:08:24 PM PDT 24
Peak memory 192464 kb
Host smart-fa21bdc9-d925-4203-9358-5b735b2879cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598555508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3598555508
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3444249304
Short name T223
Test name
Test status
Simulation time 594360226 ps
CPU time 1.07 seconds
Started Jun 13 02:07:51 PM PDT 24
Finished Jun 13 02:07:52 PM PDT 24
Peak memory 192368 kb
Host smart-637b4d2b-85ff-474e-88ce-e27da0554398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444249304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3444249304
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2187001323
Short name T258
Test name
Test status
Simulation time 20582822444 ps
CPU time 16.28 seconds
Started Jun 13 02:07:47 PM PDT 24
Finished Jun 13 02:08:05 PM PDT 24
Peak memory 192456 kb
Host smart-642f4e76-98c1-492c-bf89-d9cf3103ee57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187001323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2187001323
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2230078886
Short name T239
Test name
Test status
Simulation time 440001775 ps
CPU time 0.7 seconds
Started Jun 13 02:07:49 PM PDT 24
Finished Jun 13 02:07:51 PM PDT 24
Peak memory 192352 kb
Host smart-eada0110-2912-46fb-bf94-c522e3f8ee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230078886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2230078886
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.630724927
Short name T256
Test name
Test status
Simulation time 17077014485 ps
CPU time 26.59 seconds
Started Jun 13 02:07:47 PM PDT 24
Finished Jun 13 02:08:15 PM PDT 24
Peak memory 192424 kb
Host smart-7455bc5e-6034-49d4-8b19-6cff68a622e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630724927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.630724927
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.545420668
Short name T244
Test name
Test status
Simulation time 473673388 ps
CPU time 0.62 seconds
Started Jun 13 02:07:47 PM PDT 24
Finished Jun 13 02:07:49 PM PDT 24
Peak memory 192328 kb
Host smart-50360ca8-0cd8-400c-a5ed-e1beb9670367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545420668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.545420668
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.311484212
Short name T6
Test name
Test status
Simulation time 55836961892 ps
CPU time 21.77 seconds
Started Jun 13 02:07:54 PM PDT 24
Finished Jun 13 02:08:18 PM PDT 24
Peak memory 192476 kb
Host smart-42ee5a0b-3b16-4892-a904-9f063631d801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311484212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.311484212
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1164259997
Short name T281
Test name
Test status
Simulation time 369626749 ps
CPU time 1.06 seconds
Started Jun 13 02:07:53 PM PDT 24
Finished Jun 13 02:07:57 PM PDT 24
Peak memory 192348 kb
Host smart-311f76da-6045-4951-ba1f-431731e9b536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164259997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1164259997
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_jump.546831554
Short name T186
Test name
Test status
Simulation time 358456587 ps
CPU time 0.94 seconds
Started Jun 13 02:07:53 PM PDT 24
Finished Jun 13 02:07:56 PM PDT 24
Peak memory 197116 kb
Host smart-1e331970-736a-4131-890c-ccbe88b0acd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546831554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.546831554
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2007302648
Short name T213
Test name
Test status
Simulation time 33232059461 ps
CPU time 9.71 seconds
Started Jun 13 02:07:54 PM PDT 24
Finished Jun 13 02:08:06 PM PDT 24
Peak memory 192468 kb
Host smart-b0766599-d1f2-4521-9aa8-60943beb38a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007302648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2007302648
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2693339994
Short name T263
Test name
Test status
Simulation time 542734462 ps
CPU time 0.68 seconds
Started Jun 13 02:07:53 PM PDT 24
Finished Jun 13 02:07:56 PM PDT 24
Peak memory 197088 kb
Host smart-67747d65-aaf7-4a30-8158-3cc0a2dea290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693339994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2693339994
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.4259576074
Short name T221
Test name
Test status
Simulation time 4313600242 ps
CPU time 2.21 seconds
Started Jun 13 02:07:52 PM PDT 24
Finished Jun 13 02:07:55 PM PDT 24
Peak memory 192464 kb
Host smart-1a4a60ca-195e-455c-bf5e-41d1676aa9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259576074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4259576074
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1440087699
Short name T210
Test name
Test status
Simulation time 494281637 ps
CPU time 1.19 seconds
Started Jun 13 02:07:53 PM PDT 24
Finished Jun 13 02:07:56 PM PDT 24
Peak memory 192356 kb
Host smart-b01e8cc9-95a9-4c1a-a165-ee2ee711625c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440087699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1440087699
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2612586570
Short name T217
Test name
Test status
Simulation time 11336859281 ps
CPU time 13.75 seconds
Started Jun 13 02:07:59 PM PDT 24
Finished Jun 13 02:08:14 PM PDT 24
Peak memory 192456 kb
Host smart-a3f331e5-daa5-4a37-9743-69f3642607a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612586570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2612586570
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1602732528
Short name T255
Test name
Test status
Simulation time 498807861 ps
CPU time 0.75 seconds
Started Jun 13 02:07:59 PM PDT 24
Finished Jun 13 02:08:01 PM PDT 24
Peak memory 197152 kb
Host smart-89165f9d-dd9d-469f-9c17-ec718ba5ace2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602732528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1602732528
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3341868128
Short name T262
Test name
Test status
Simulation time 10786391091 ps
CPU time 18.41 seconds
Started Jun 13 02:07:58 PM PDT 24
Finished Jun 13 02:08:18 PM PDT 24
Peak memory 192436 kb
Host smart-9c5b7cfe-e52a-4afb-9bef-5c06cb3bf5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341868128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3341868128
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2335538746
Short name T264
Test name
Test status
Simulation time 544279416 ps
CPU time 0.68 seconds
Started Jun 13 02:07:59 PM PDT 24
Finished Jun 13 02:08:01 PM PDT 24
Peak memory 192368 kb
Host smart-8a46a928-eb94-46c5-b49a-b07547f5fff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335538746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2335538746
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3673448357
Short name T234
Test name
Test status
Simulation time 51065036444 ps
CPU time 62.84 seconds
Started Jun 13 02:08:07 PM PDT 24
Finished Jun 13 02:09:12 PM PDT 24
Peak memory 192476 kb
Host smart-c81b37c4-f7a4-4502-bc74-3ba2c9834157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673448357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3673448357
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.553444505
Short name T202
Test name
Test status
Simulation time 532102004 ps
CPU time 0.94 seconds
Started Jun 13 02:08:11 PM PDT 24
Finished Jun 13 02:08:13 PM PDT 24
Peak memory 196832 kb
Host smart-639827eb-fd77-4f5b-8b53-4c0195be704b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553444505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.553444505
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2715164261
Short name T230
Test name
Test status
Simulation time 6240072475 ps
CPU time 9.17 seconds
Started Jun 13 02:08:07 PM PDT 24
Finished Jun 13 02:08:18 PM PDT 24
Peak memory 192476 kb
Host smart-81534010-6473-401b-872b-12cd555e248f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715164261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2715164261
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3349688494
Short name T270
Test name
Test status
Simulation time 410139982 ps
CPU time 0.9 seconds
Started Jun 13 02:08:07 PM PDT 24
Finished Jun 13 02:08:10 PM PDT 24
Peak memory 197152 kb
Host smart-1331deef-4ac8-4062-be2a-67359cd3970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349688494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3349688494
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3563084818
Short name T285
Test name
Test status
Simulation time 17785752132 ps
CPU time 26.13 seconds
Started Jun 13 02:07:07 PM PDT 24
Finished Jun 13 02:07:33 PM PDT 24
Peak memory 192448 kb
Host smart-6647b1bf-8774-4f74-8269-ee0752b24e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563084818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3563084818
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3491167572
Short name T272
Test name
Test status
Simulation time 442287330 ps
CPU time 1.28 seconds
Started Jun 13 02:07:04 PM PDT 24
Finished Jun 13 02:07:06 PM PDT 24
Peak memory 192352 kb
Host smart-eb619f25-a95d-4829-b618-bc221f6831e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491167572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3491167572
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3662063418
Short name T280
Test name
Test status
Simulation time 35814275928 ps
CPU time 12.23 seconds
Started Jun 13 02:07:05 PM PDT 24
Finished Jun 13 02:07:18 PM PDT 24
Peak memory 192452 kb
Host smart-a4fb77f6-034e-447d-b977-0aefe588bb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662063418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3662063418
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2999065498
Short name T250
Test name
Test status
Simulation time 491040303 ps
CPU time 1.34 seconds
Started Jun 13 02:07:01 PM PDT 24
Finished Jun 13 02:07:03 PM PDT 24
Peak memory 192328 kb
Host smart-2ee558e3-5da4-4fa7-bbea-91e4d8ccfda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999065498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2999065498
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3548744054
Short name T251
Test name
Test status
Simulation time 58028478858 ps
CPU time 18.29 seconds
Started Jun 13 02:07:04 PM PDT 24
Finished Jun 13 02:07:23 PM PDT 24
Peak memory 192648 kb
Host smart-6d98b478-e147-4c53-8e3a-dba242a71d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548744054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3548744054
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1963743868
Short name T257
Test name
Test status
Simulation time 685714758 ps
CPU time 0.74 seconds
Started Jun 13 02:07:05 PM PDT 24
Finished Jun 13 02:07:07 PM PDT 24
Peak memory 197116 kb
Host smart-d7b3a2cd-0e64-42bd-b791-9a0c6e43afee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963743868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1963743868
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.791316915
Short name T8
Test name
Test status
Simulation time 37038390287 ps
CPU time 45.34 seconds
Started Jun 13 02:07:08 PM PDT 24
Finished Jun 13 02:07:54 PM PDT 24
Peak memory 192476 kb
Host smart-c43d268e-b98d-4fd9-9987-3b1346e4afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791316915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.791316915
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3887663272
Short name T271
Test name
Test status
Simulation time 412970097 ps
CPU time 0.79 seconds
Started Jun 13 02:07:04 PM PDT 24
Finished Jun 13 02:07:06 PM PDT 24
Peak memory 197148 kb
Host smart-81199e99-9536-4027-ab25-233e02e5efc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887663272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3887663272
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.323548927
Short name T4
Test name
Test status
Simulation time 23327590078 ps
CPU time 37.63 seconds
Started Jun 13 02:07:03 PM PDT 24
Finished Jun 13 02:07:41 PM PDT 24
Peak memory 192432 kb
Host smart-ff5ddc8a-bb4b-4ca2-bcc5-08e97f79c9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323548927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.323548927
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2992329027
Short name T209
Test name
Test status
Simulation time 469910672 ps
CPU time 0.95 seconds
Started Jun 13 02:07:03 PM PDT 24
Finished Jun 13 02:07:05 PM PDT 24
Peak memory 192352 kb
Host smart-e4ca2ea3-b72f-4f05-97e7-50c84b640edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992329027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2992329027
Directory /workspace/9.aon_timer_smoke/latest
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