Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	27721	1		T2	12		T3	248		T4	174
bark[1]	384	1		T3	21		T45	30		T77	60
bark[2]	544	1		T1	14		T42	70		T106	21
bark[3]	189	1		T12	21		T46	7		T106	42
bark[4]	760	1		T44	7		T47	126		T155	158
bark[5]	595	1		T12	21		T45	239		T26	63
bark[6]	98	1		T174	14		T44	21		T46	21
bark[7]	421	1		T26	224		T119	30		T168	14
bark[8]	282	1		T128	21		T156	14		T44	26
bark[9]	328	1		T8	14		T30	44		T130	21
bark[10]	128	1		T182	14		T76	21		T79	21
bark[11]	385	1		T5	14		T11	21		T164	37
bark[12]	1045	1		T42	391		T83	224		T139	21
bark[13]	342	1		T12	39		T118	21		T112	79
bark[14]	305	1		T128	67		T43	21		T45	83
bark[15]	308	1		T77	21		T30	231		T134	30
bark[16]	312	1		T25	21		T32	26		T176	53
bark[17]	401	1		T44	47		T176	21		T116	242
bark[18]	633	1		T3	39		T43	35		T155	245
bark[19]	523	1		T106	63		T140	21		T119	364
bark[20]	203	1		T4	14		T19	21		T179	63
bark[21]	476	1		T164	44		T128	51		T171	14
bark[22]	323	1		T79	21		T155	82		T104	30
bark[23]	604	1		T44	21		T27	56		T31	66
bark[24]	432	1		T4	30		T33	14		T31	21
bark[25]	189	1		T35	14		T152	14		T107	21
bark[26]	793	1		T11	21		T15	63		T43	236
bark[27]	661	1		T4	26		T6	14		T31	509
bark[28]	72	1		T155	30		T119	7		T157	14
bark[29]	512	1		T19	225		T30	70		T116	56
bark[30]	175	1		T4	42		T127	21		T133	14
bark[31]	553	1		T25	21		T32	21		T155	39
bark_0	4259	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	27069	1		T2	11		T3	247		T4	174
bite[1]	278	1		T13	13		T77	60		T25	21
bite[2]	182	1		T182	13		T77	21		T155	30
bite[3]	337	1		T8	13		T11	21		T32	26
bite[4]	268	1		T3	39		T5	13		T6	13
bite[5]	694	1		T11	21		T128	21		T117	13
bite[6]	395	1		T19	21		T128	21		T171	13
bite[7]	443	1		T43	235		T44	46		T155	6
bite[8]	350	1		T43	34		T141	21		T119	96
bite[9]	285	1		T15	62		T116	120		T130	21
bite[10]	326	1		T19	203		T43	21		T155	81
bite[11]	627	1		T164	44		T30	43		T118	42
bite[12]	865	1		T128	67		T174	13		T31	508
bite[13]	878	1		T45	21		T108	21		T112	21
bite[14]	478	1		T1	13		T27	79		T116	26
bite[15]	606	1		T4	13		T116	241		T136	13
bite[16]	231	1		T46	27		T30	69		T138	6
bite[17]	481	1		T3	21		T12	21		T44	21
bite[18]	411	1		T179	63		T44	6		T25	21
bite[19]	292	1		T4	21		T19	21		T164	36
bite[20]	94	1		T12	39		T79	21		T116	21
bite[21]	333	1		T4	21		T26	223		T118	21
bite[22]	947	1		T33	13		T18	275		T42	390
bite[23]	435	1		T45	171		T76	21		T120	21
bite[24]	386	1		T44	21		T77	21		T46	155
bite[25]	503	1		T4	30		T76	79		T46	21
bite[26]	168	1		T12	21		T35	13		T79	21
bite[27]	528	1		T42	69		T26	62		T116	65
bite[28]	216	1		T156	13		T76	21		T186	13
bite[29]	508	1		T4	26		T44	25		T120	13
bite[30]	487	1		T11	21		T155	244		T116	21
bite[31]	132	1		T155	39		T90	46		T160	13
bite_0	4723	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	44956	1		T1	21		T2	19		T3	315

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1247	1		T11	42		T42	51		T44	124
prescale[1]	1295	1		T42	58		T44	86		T79	56
prescale[2]	634	1		T11	14		T42	189		T44	40
prescale[3]	1136	1		T14	9		T18	81		T128	19
prescale[4]	922	1		T19	37		T164	19		T42	139
prescale[5]	915	1		T3	79		T18	19		T43	28
prescale[6]	763	1		T42	19		T26	19		T27	33
prescale[7]	923	1		T4	19		T9	9		T18	40
prescale[8]	785	1		T18	20		T19	61		T42	19
prescale[9]	712	1		T11	19		T15	2		T19	108
prescale[10]	891	1		T3	28		T4	37		T11	42
prescale[11]	642	1		T3	24		T11	37		T15	19
prescale[12]	579	1		T19	19		T128	19		T42	29
prescale[13]	720	1		T4	19		T18	19		T42	97
prescale[14]	637	1		T19	19		T164	23		T43	19
prescale[15]	1091	1		T12	40		T195	9		T43	100
prescale[16]	599	1		T19	19		T42	55		T43	19
prescale[17]	811	1		T19	30		T128	62		T179	19
prescale[18]	481	1		T179	19		T43	19		T32	19
prescale[19]	602	1		T2	9		T3	37		T12	9
prescale[20]	507	1		T48	9		T16	9		T18	45
prescale[21]	603	1		T42	37		T44	76		T32	9
prescale[22]	585	1		T18	127		T19	37		T164	19
prescale[23]	584	1		T15	9		T19	38		T43	58
prescale[24]	928	1		T15	19		T42	79		T44	70
prescale[25]	492	1		T19	37		T42	40		T196	9
prescale[26]	892	1		T12	58		T15	19		T179	9
prescale[27]	936	1		T11	19		T18	2		T44	2
prescale[28]	920	1		T3	40		T15	134		T19	109
prescale[29]	796	1		T15	19		T18	53		T19	40
prescale[30]	251	1		T43	38		T45	40		T46	2
prescale[31]	927	1		T19	38		T42	19		T45	19
prescale_0	20150	1		T1	21		T2	10		T3	107

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32657	1		T1	9		T2	19		T3	161
auto[1]	12299	1		T1	12		T3	154		T4	185

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	44956	1		T1	21		T2	19		T3	315

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	27529	1		T1	1		T2	14		T3	268
wkup[1]	93	1		T45	30		T27	21		T116	21
wkup[2]	171	1		T26	21		T155	21		T116	8
wkup[3]	234	1		T15	21		T18	57		T117	15
wkup[4]	316	1		T18	21		T19	15		T156	15
wkup[5]	145	1		T18	26		T45	21		T26	30
wkup[6]	147	1		T11	26		T15	35		T138	21
wkup[7]	253	1		T15	21		T106	8		T141	21
wkup[8]	213	1		T13	15		T15	21		T141	21
wkup[9]	159	1		T6	15		T18	21		T31	21
wkup[10]	269	1		T42	21		T45	21		T31	21
wkup[11]	294	1		T4	30		T44	21		T77	42
wkup[12]	66	1		T1	15		T108	30		T103	21
wkup[13]	258	1		T42	21		T26	21		T30	21
wkup[14]	243	1		T128	21		T45	30		T141	21
wkup[15]	398	1		T19	21		T42	47		T44	21
wkup[16]	245	1		T42	21		T27	21		T116	42
wkup[17]	280	1		T4	15		T12	21		T19	21
wkup[18]	284	1		T44	80		T45	21		T26	21
wkup[19]	168	1		T8	15		T19	21		T45	21
wkup[20]	190	1		T174	15		T26	21		T155	30
wkup[21]	122	1		T43	21		T79	21		T46	8
wkup[22]	252	1		T179	21		T43	21		T155	51
wkup[23]	191	1		T19	21		T46	15		T26	42
wkup[24]	265	1		T45	21		T116	42		T141	21
wkup[25]	201	1		T18	21		T27	31		T155	26
wkup[26]	287	1		T33	15		T128	21		T42	21
wkup[27]	239	1		T4	21		T42	26		T106	21
wkup[28]	150	1		T104	21		T159	15		T119	21
wkup[29]	240	1		T43	21		T45	30		T76	21
wkup[30]	196	1		T19	21		T42	15		T32	26
wkup[31]	198	1		T12	21		T79	21		T30	21
wkup[32]	296	1		T27	21		T120	21		T116	42
wkup[33]	220	1		T11	21		T128	21		T44	42
wkup[34]	209	1		T76	21		T46	21		T47	21
wkup[35]	229	1		T19	51		T116	72		T141	21
wkup[36]	299	1		T43	21		T182	15		T25	21
wkup[37]	272	1		T42	21		T45	53		T47	21
wkup[38]	233	1		T43	21		T46	21		T120	21
wkup[39]	184	1		T45	21		T138	21		T83	8
wkup[40]	188	1		T35	15		T46	30		T116	21
wkup[41]	218	1		T128	30		T45	15		T47	21
wkup[42]	150	1		T42	21		T43	30		T155	21
wkup[43]	203	1		T42	21		T27	21		T155	21
wkup[44]	159	1		T11	21		T18	42		T42	21
wkup[45]	312	1		T5	15		T11	21		T179	21
wkup[46]	156	1		T108	21		T169	30		T84	21
wkup[47]	299	1		T3	21		T46	21		T27	21
wkup[48]	214	1		T18	30		T47	38		T119	21
wkup[49]	171	1		T4	26		T18	26		T116	21
wkup[50]	126	1		T12	21		T179	21		T155	21
wkup[51]	213	1		T3	21		T46	8		T27	30
wkup[52]	302	1		T19	21		T43	21		T45	21
wkup[53]	171	1		T164	21		T155	21		T127	21
wkup[54]	284	1		T42	21		T45	42		T30	21
wkup[55]	323	1		T43	21		T44	21		T45	21
wkup[56]	201	1		T18	21		T19	21		T31	30
wkup[57]	282	1		T42	21		T45	21		T27	21
wkup[58]	193	1		T4	21		T45	30		T155	35
wkup[59]	213	1		T18	21		T19	21		T164	21
wkup[60]	187	1		T47	40		T26	21		T31	21
wkup[61]	231	1		T18	30		T42	21		T141	21
wkup[62]	298	1		T45	21		T77	21		T106	21
wkup[63]	268	1		T19	21		T164	21		T45	21
wkup_0	3356	1		T1	5		T2	5		T3	5