| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.64 | 99.33 | 93.67 | 100.00 | 98.40 | 99.51 | 46.94 |
| T286 | /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3553247231 | Jun 21 07:27:31 PM PDT 24 | Jun 21 07:27:37 PM PDT 24 | 571714924 ps | ||
| T287 | /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.196691458 | Jun 21 07:27:39 PM PDT 24 | Jun 21 07:27:46 PM PDT 24 | 501198769 ps | ||
| T41 | /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.287480862 | Jun 21 07:27:19 PM PDT 24 | Jun 21 07:27:28 PM PDT 24 | 549029060 ps | ||
| T37 | /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1362523905 | Jun 21 07:26:27 PM PDT 24 | Jun 21 07:26:49 PM PDT 24 | 8949890938 ps | ||
| T89 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1101097820 | Jun 21 07:26:47 PM PDT 24 | Jun 21 07:27:03 PM PDT 24 | 819654665 ps | ||
| T38 | /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.556698459 | Jun 21 07:27:00 PM PDT 24 | Jun 21 07:27:16 PM PDT 24 | 2279796172 ps | ||
| T288 | /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2649412779 | Jun 21 07:27:32 PM PDT 24 | Jun 21 07:27:39 PM PDT 24 | 835375925 ps | ||
| T289 | /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1971612311 | Jun 21 07:27:22 PM PDT 24 | Jun 21 07:27:30 PM PDT 24 | 372818211 ps | ||
| T52 | /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3098972510 | Jun 21 07:27:02 PM PDT 24 | Jun 21 07:27:16 PM PDT 24 | 440757857 ps | ||
| T290 | /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.921163328 | Jun 21 07:27:36 PM PDT 24 | Jun 21 07:27:43 PM PDT 24 | 483126009 ps | ||
| T197 | /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3912619782 | Jun 21 07:27:36 PM PDT 24 | Jun 21 07:27:42 PM PDT 24 | 371587086 ps | ||
| T291 | /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1799814458 | Jun 21 07:27:35 PM PDT 24 | Jun 21 07:27:41 PM PDT 24 | 559201549 ps | ||
| T70 | /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.163470015 | Jun 21 07:27:28 PM PDT 24 | Jun 21 07:27:34 PM PDT 24 | 1448964646 ps | ||
| T292 | /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2947587044 | Jun 21 07:27:20 PM PDT 24 | Jun 21 07:27:28 PM PDT 24 | 384954249 ps | ||
| T293 | /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.471383187 | Jun 21 07:27:04 PM PDT 24 | Jun 21 07:27:16 PM PDT 24 | 536776226 ps | ||
| T294 | /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.576661814 | Jun 21 07:27:37 PM PDT 24 | Jun 21 07:27:43 PM PDT 24 | 308218351 ps | ||
| T295 | /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3402772669 | Jun 21 07:27:44 PM PDT 24 | Jun 21 07:27:52 PM PDT 24 | 419761039 ps | ||
| T39 | /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3278922138 | Jun 21 07:27:05 PM PDT 24 | Jun 21 07:27:19 PM PDT 24 | 4868553654 ps | ||
| T296 | /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4179210471 | Jun 21 07:27:40 PM PDT 24 | Jun 21 07:27:46 PM PDT 24 | 541724471 ps | ||
| T297 | /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2492460526 | Jun 21 07:27:44 PM PDT 24 | Jun 21 07:27:52 PM PDT 24 | 413752308 ps | ||
| T298 | /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2412722094 | Jun 21 07:27:35 PM PDT 24 | Jun 21 07:27:41 PM PDT 24 | 388241477 ps | ||
| T71 | /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3308613771 | Jun 21 07:27:19 PM PDT 24 | Jun 21 07:27:28 PM PDT 24 | 917400010 ps | ||
| T299 | /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3216265596 | Jun 21 07:27:21 PM PDT 24 | Jun 21 07:27:28 PM PDT 24 | 440126720 ps | ||
| T300 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.414609992 | Jun 21 07:26:59 PM PDT 24 | Jun 21 07:27:13 PM PDT 24 | 546820407 ps | ||
| T301 | /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.373921442 | Jun 21 07:27:21 PM PDT 24 | Jun 21 07:27:29 PM PDT 24 | 515687414 ps | ||
| T302 | /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.844244399 | Jun 21 07:27:30 PM PDT 24 | Jun 21 07:27:37 PM PDT 24 | 365690711 ps | ||
| T303 | /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3769372883 | Jun 21 07:26:26 PM PDT 24 | Jun 21 07:26:46 PM PDT 24 | 392885174 ps | ||
| T53 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1809216166 | Jun 21 07:26:47 PM PDT 24 | Jun 21 07:27:08 PM PDT 24 | 5757479111 ps | ||
| T40 | /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1412956744 | Jun 21 07:26:38 PM PDT 24 | Jun 21 07:26:57 PM PDT 24 | 4718379350 ps | ||
| T304 | /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1027626110 | Jun 21 07:27:27 PM PDT 24 | Jun 21 07:27:33 PM PDT 24 | 425906880 ps | ||
| T305 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.901837491 | Jun 21 07:26:57 PM PDT 24 | Jun 21 07:27:12 PM PDT 24 | 575210043 ps | ||
| T306 | /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1894213768 | Jun 21 07:27:39 PM PDT 24 | Jun 21 07:27:46 PM PDT 24 | 297756796 ps | ||
| T54 | /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1365218665 | Jun 21 07:27:19 PM PDT 24 | Jun 21 07:27:26 PM PDT 24 | 503287530 ps | ||
| T307 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1791475668 | Jun 21 07:26:46 PM PDT 24 | Jun 21 07:27:02 PM PDT 24 | 524167027 ps | ||
| T72 | /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4134220229 | Jun 21 07:27:30 PM PDT 24 | Jun 21 07:27:37 PM PDT 24 | 2503133931 ps | ||
| T55 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1037635465 | Jun 21 07:26:39 PM PDT 24 | Jun 21 07:27:03 PM PDT 24 | 10099635955 ps | ||
| T308 | /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1555946260 | Jun 21 07:27:30 PM PDT 24 | Jun 21 07:27:36 PM PDT 24 | 565100560 ps | ||
| T73 | /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2384584300 | Jun 21 07:27:28 PM PDT 24 | Jun 21 07:27:35 PM PDT 24 | 1263651947 ps | ||
| T309 | /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4148837291 | Jun 21 07:27:05 PM PDT 24 | Jun 21 07:27:19 PM PDT 24 | 472600021 ps | ||
| T310 | /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3197275594 | Jun 21 07:27:39 PM PDT 24 | Jun 21 07:27:46 PM PDT 24 | 362423161 ps | ||
| T74 | /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2784373732 | Jun 21 07:26:54 PM PDT 24 | Jun 21 07:27:09 PM PDT 24 | 1694527203 ps | ||
| T311 | /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1606120504 | Jun 21 07:26:36 PM PDT 24 | Jun 21 07:26:55 PM PDT 24 | 499529079 ps | ||
| T312 | /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3571148002 | Jun 21 07:27:29 PM PDT 24 | Jun 21 07:27:35 PM PDT 24 | 486993672 ps | ||
| T313 | /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.569258571 | Jun 21 07:26:30 PM PDT 24 | Jun 21 07:26:50 PM PDT 24 | 377783303 ps | ||
| T314 | /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3597936532 | Jun 21 07:27:05 PM PDT 24 | Jun 21 07:27:18 PM PDT 24 | 439337423 ps | ||
| T315 | /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2191822320 | Jun 21 07:27:29 PM PDT 24 | Jun 21 07:27:40 PM PDT 24 | 4576544914 ps | ||
| T56 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3750858525 | Jun 21 07:26:46 PM PDT 24 | Jun 21 07:27:02 PM PDT 24 | 820652431 ps | ||
| T191 | /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1454900608 | Jun 21 07:27:30 PM PDT 24 | Jun 21 07:27:42 PM PDT 24 | 4169614668 ps | ||
| T316 | /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4066757333 | Jun 21 07:26:54 PM PDT 24 | Jun 21 07:27:08 PM PDT 24 | 314709790 ps | ||
| T317 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2186260382 | Jun 21 07:26:38 PM PDT 24 | Jun 21 07:26:55 PM PDT 24 | 586672646 ps | ||
| T318 | /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2375474647 | Jun 21 07:27:36 PM PDT 24 | Jun 21 07:27:42 PM PDT 24 | 512460371 ps | ||
| T319 | /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1600657701 | Jun 21 07:27:21 PM PDT 24 | Jun 21 07:27:29 PM PDT 24 | 357993818 ps | ||
| T320 | /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1937312233 | Jun 21 07:26:57 PM PDT 24 | Jun 21 07:27:14 PM PDT 24 | 2019304314 ps | ||
| T321 | /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1858867990 | Jun 21 07:27:02 PM PDT 24 | Jun 21 07:27:16 PM PDT 24 | 307305909 ps | ||
| T322 | /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.144442308 | Jun 21 07:27:44 PM PDT 24 | Jun 21 07:27:51 PM PDT 24 | 403130967 ps | ||
| T192 | /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1847393241 | Jun 21 07:26:55 PM PDT 24 | Jun 21 07:27:20 PM PDT 24 | 7720300499 ps | ||
| T323 | /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3432797006 | Jun 21 07:26:57 PM PDT 24 | Jun 21 07:27:17 PM PDT 24 | 3896016065 ps | ||
| T75 | /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1692619757 | Jun 21 07:27:04 PM PDT 24 | Jun 21 07:27:18 PM PDT 24 | 1097871035 ps | ||
| T324 | /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2539989374 | Jun 21 07:27:38 PM PDT 24 | Jun 21 07:27:48 PM PDT 24 | 2496513101 ps | ||
| T325 | /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3507626738 | Jun 21 07:26:39 PM PDT 24 | Jun 21 07:26:56 PM PDT 24 | 391309063 ps | ||
| T326 | /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.125285841 | Jun 21 07:27:19 PM PDT 24 | Jun 21 07:27:29 PM PDT 24 | 4053410445 ps | ||
| T327 | /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.732663461 | Jun 21 07:27:39 PM PDT 24 | Jun 21 07:27:46 PM PDT 24 | 375747280 ps | ||
| T328 | /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2711314515 | Jun 21 07:27:28 PM PDT 24 | Jun 21 07:27:33 PM PDT 24 | 296135257 ps | ||
| T329 | /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2632890506 | Jun 21 07:27:28 PM PDT 24 | Jun 21 07:27:35 PM PDT 24 | 2676242942 ps | ||
| T330 | /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1673257347 | Jun 21 07:27:31 PM PDT 24 | Jun 21 07:27:37 PM PDT 24 | 2697797339 ps | ||
| T331 | /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.459529355 | Jun 21 07:26:38 PM PDT 24 | Jun 21 07:26:58 PM PDT 24 | 4384237382 ps | ||
| T332 | /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3469901371 | Jun 21 07:26:54 PM PDT 24 | Jun 21 07:27:08 PM PDT 24 | 525146298 ps | ||
| T333 | /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.130097422 | Jun 21 07:27:29 PM PDT 24 | Jun 21 07:27:36 PM PDT 24 | 4922349613 ps | ||
| T334 | /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3787076138 | Jun 21 07:27:19 PM PDT 24 | Jun 21 07:27:38 PM PDT 24 | 8062912027 ps | ||
| T335 | /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.346138641 | Jun 21 07:26:55 PM PDT 24 | Jun 21 07:27:10 PM PDT 24 | 310495772 ps | ||
| T336 | /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3847863211 | Jun 21 07:27:39 PM PDT 24 | Jun 21 07:27:46 PM PDT 24 | 394590368 ps | ||
| T337 | /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2425166627 | Jun 21 07:26:38 PM PDT 24 | Jun 21 07:26:58 PM PDT 24 | 1086587429 ps | ||
| T57 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3546574020 | Jun 21 07:26:46 PM PDT 24 | Jun 21 07:27:02 PM PDT 24 | 446285872 ps | ||
| T338 | /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2072170170 | Jun 21 07:27:21 PM PDT 24 | Jun 21 07:27:28 PM PDT 24 | 1080601017 ps | ||
| T58 | /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3226623518 | Jun 21 07:26:55 PM PDT 24 | Jun 21 07:27:10 PM PDT 24 | 475527304 ps | ||
| T59 | /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4123468281 | Jun 21 07:27:11 PM PDT 24 | Jun 21 07:27:22 PM PDT 24 | 501531484 ps | ||
| T339 | /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2380206053 | Jun 21 07:27:29 PM PDT 24 | Jun 21 07:27:34 PM PDT 24 | 382982963 ps | ||
| T340 | /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2087261075 | Jun 21 07:27:31 PM PDT 24 | Jun 21 07:27:48 PM PDT 24 | 8518826239 ps | ||
| T341 | /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2252423894 | Jun 21 07:26:54 PM PDT 24 | Jun 21 07:27:09 PM PDT 24 | 2133009807 ps | ||
| T342 | /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2983960660 | Jun 21 07:27:38 PM PDT 24 | Jun 21 07:27:45 PM PDT 24 | 342668419 ps | ||
| T60 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4153985225 | Jun 21 07:26:38 PM PDT 24 | Jun 21 07:26:55 PM PDT 24 | 425101809 ps | ||
| T343 | /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3533165535 | Jun 21 07:26:38 PM PDT 24 | Jun 21 07:26:56 PM PDT 24 | 1641185785 ps | ||
| T61 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2300268610 | Jun 21 07:26:56 PM PDT 24 | Jun 21 07:27:12 PM PDT 24 | 387777180 ps | ||
| T344 | /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1768194636 | Jun 21 07:27:40 PM PDT 24 | Jun 21 07:27:47 PM PDT 24 | 374552152 ps | ||
| T345 | /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3055739191 | Jun 21 07:27:18 PM PDT 24 | Jun 21 07:27:26 PM PDT 24 | 321654196 ps | ||
| T346 | /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2295314685 | Jun 21 07:27:27 PM PDT 24 | Jun 21 07:27:33 PM PDT 24 | 469503832 ps | ||
| T347 | /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.930139151 | Jun 21 07:27:27 PM PDT 24 | Jun 21 07:27:36 PM PDT 24 | 4657540342 ps | ||
| T348 | /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3076258685 | Jun 21 07:27:40 PM PDT 24 | Jun 21 07:27:50 PM PDT 24 | 8105867659 ps | ||
| T349 | /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2741297510 | Jun 21 07:26:56 PM PDT 24 | Jun 21 07:27:10 PM PDT 24 | 357397511 ps | ||
| T350 | /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.992033586 | Jun 21 07:27:39 PM PDT 24 | Jun 21 07:27:47 PM PDT 24 | 446150012 ps | ||
| T351 | /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3304441496 | Jun 21 07:27:39 PM PDT 24 | Jun 21 07:27:46 PM PDT 24 | 307316439 ps | ||
| T352 | /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3435434065 | Jun 21 07:27:29 PM PDT 24 | Jun 21 07:27:34 PM PDT 24 | 383201630 ps | ||
| T353 | /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1100608516 | Jun 21 07:27:03 PM PDT 24 | Jun 21 07:27:16 PM PDT 24 | 418629498 ps | ||
| T354 | /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3029007456 | Jun 21 07:27:46 PM PDT 24 | Jun 21 07:27:53 PM PDT 24 | 271326759 ps | ||
| T355 | /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4139493829 | Jun 21 07:26:54 PM PDT 24 | Jun 21 07:27:10 PM PDT 24 | 645228669 ps | ||
| T356 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3622205292 | Jun 21 07:26:36 PM PDT 24 | Jun 21 07:26:54 PM PDT 24 | 806909144 ps | ||
| T357 | /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.912392618 | Jun 21 07:27:11 PM PDT 24 | Jun 21 07:27:22 PM PDT 24 | 551356752 ps | ||
| T358 | /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4160289966 | Jun 21 07:27:27 PM PDT 24 | Jun 21 07:27:33 PM PDT 24 | 421372268 ps | ||
| T359 | /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.515197114 | Jun 21 07:26:39 PM PDT 24 | Jun 21 07:26:56 PM PDT 24 | 416274291 ps | ||
| T360 | /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2207611010 | Jun 21 07:27:38 PM PDT 24 | Jun 21 07:27:45 PM PDT 24 | 518719869 ps | ||
| T361 | /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1977416269 | Jun 21 07:27:03 PM PDT 24 | Jun 21 07:27:16 PM PDT 24 | 392314950 ps | ||
| T362 | /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1383200045 | Jun 21 07:26:47 PM PDT 24 | Jun 21 07:27:03 PM PDT 24 | 495412690 ps | ||
| T363 | /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2074559513 | Jun 21 07:27:29 PM PDT 24 | Jun 21 07:27:35 PM PDT 24 | 560403932 ps | ||
| T364 | /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.721086504 | Jun 21 07:27:45 PM PDT 24 | Jun 21 07:27:52 PM PDT 24 | 590536635 ps | ||
| T65 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2859174196 | Jun 21 07:26:38 PM PDT 24 | Jun 21 07:27:20 PM PDT 24 | 11713834343 ps | ||
| T365 | /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.804042149 | Jun 21 07:27:32 PM PDT 24 | Jun 21 07:27:38 PM PDT 24 | 2769957401 ps | ||
| T66 | /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.756408796 | Jun 21 07:27:20 PM PDT 24 | Jun 21 07:27:27 PM PDT 24 | 488715634 ps | ||
| T366 | /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.810115628 | Jun 21 07:26:30 PM PDT 24 | Jun 21 07:26:49 PM PDT 24 | 422525571 ps | ||
| T367 | /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4024938579 | Jun 21 07:27:00 PM PDT 24 | Jun 21 07:27:14 PM PDT 24 | 581904048 ps | ||
| T368 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2048116984 | Jun 21 07:26:39 PM PDT 24 | Jun 21 07:26:56 PM PDT 24 | 579797715 ps | ||
| T62 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3483265638 | Jun 21 07:26:46 PM PDT 24 | Jun 21 07:27:02 PM PDT 24 | 493465361 ps | ||
| T369 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2028007940 | Jun 21 07:26:47 PM PDT 24 | Jun 21 07:27:03 PM PDT 24 | 388429009 ps | ||
| T370 | /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1633073375 | Jun 21 07:26:54 PM PDT 24 | Jun 21 07:27:10 PM PDT 24 | 344871712 ps | ||
| T67 | /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2576043557 | Jun 21 07:27:27 PM PDT 24 | Jun 21 07:27:33 PM PDT 24 | 432556518 ps | ||
| T371 | /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1168438419 | Jun 21 07:26:37 PM PDT 24 | Jun 21 07:26:54 PM PDT 24 | 497641503 ps | ||
| T372 | /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1066438041 | Jun 21 07:27:37 PM PDT 24 | Jun 21 07:27:43 PM PDT 24 | 455991397 ps | ||
| T373 | /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3450251457 | Jun 21 07:26:56 PM PDT 24 | Jun 21 07:27:12 PM PDT 24 | 2445446256 ps | ||
| T374 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2554568702 | Jun 21 07:26:38 PM PDT 24 | Jun 21 07:26:55 PM PDT 24 | 864041660 ps | ||
| T375 | /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3080710918 | Jun 21 07:27:28 PM PDT 24 | Jun 21 07:27:34 PM PDT 24 | 542494895 ps | ||
| T376 | /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1950370109 | Jun 21 07:27:03 PM PDT 24 | Jun 21 07:27:19 PM PDT 24 | 4053129985 ps | ||
| T194 | /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1056561768 | Jun 21 07:27:21 PM PDT 24 | Jun 21 07:27:42 PM PDT 24 | 8597519113 ps | ||
| T377 | /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.494762296 | Jun 21 07:27:21 PM PDT 24 | Jun 21 07:27:29 PM PDT 24 | 544231790 ps | ||
| T378 | /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4159194644 | Jun 21 07:26:55 PM PDT 24 | Jun 21 07:27:09 PM PDT 24 | 505930848 ps | ||
| T379 | /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2049835982 | Jun 21 07:26:55 PM PDT 24 | Jun 21 07:27:14 PM PDT 24 | 4467395683 ps | ||
| T380 | /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2138189722 | Jun 21 07:26:59 PM PDT 24 | Jun 21 07:27:13 PM PDT 24 | 329517895 ps | ||
| T381 | /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3062208049 | Jun 21 07:27:29 PM PDT 24 | Jun 21 07:27:35 PM PDT 24 | 547621706 ps | ||
| T382 | /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.87834546 | Jun 21 07:27:05 PM PDT 24 | Jun 21 07:27:18 PM PDT 24 | 1277407851 ps | ||
| T383 | /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3521832516 | Jun 21 07:26:46 PM PDT 24 | Jun 21 07:27:02 PM PDT 24 | 509836682 ps | ||
| T384 | /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2104862353 | Jun 21 07:27:22 PM PDT 24 | Jun 21 07:27:29 PM PDT 24 | 394988278 ps | ||
| T69 | /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2475521562 | Jun 21 07:27:29 PM PDT 24 | Jun 21 07:27:35 PM PDT 24 | 464416603 ps | ||
| T385 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1633900964 | Jun 21 07:27:00 PM PDT 24 | Jun 21 07:27:14 PM PDT 24 | 1426797860 ps | ||
| T386 | /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4046122932 | Jun 21 07:27:18 PM PDT 24 | Jun 21 07:27:27 PM PDT 24 | 1508577586 ps | ||
| T387 | /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2820223316 | Jun 21 07:27:43 PM PDT 24 | Jun 21 07:27:50 PM PDT 24 | 460707668 ps | ||
| T68 | /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.253348595 | Jun 21 07:27:20 PM PDT 24 | Jun 21 07:27:28 PM PDT 24 | 409585214 ps | ||
| T388 | /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1942542070 | Jun 21 07:27:38 PM PDT 24 | Jun 21 07:27:44 PM PDT 24 | 452149950 ps | ||
| T389 | /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4284067377 | Jun 21 07:27:31 PM PDT 24 | Jun 21 07:27:38 PM PDT 24 | 510962235 ps | ||
| T390 | /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2547727159 | Jun 21 07:27:12 PM PDT 24 | Jun 21 07:27:24 PM PDT 24 | 2651301671 ps | ||
| T63 | /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3261187930 | Jun 21 07:27:40 PM PDT 24 | Jun 21 07:27:47 PM PDT 24 | 523539513 ps | ||
| T391 | /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4262206765 | Jun 21 07:26:38 PM PDT 24 | Jun 21 07:26:55 PM PDT 24 | 323006078 ps | ||
| T392 | /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.510919787 | Jun 21 07:26:47 PM PDT 24 | Jun 21 07:27:03 PM PDT 24 | 548027368 ps | ||
| T393 | /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.958347970 | Jun 21 07:26:46 PM PDT 24 | Jun 21 07:27:05 PM PDT 24 | 2279496299 ps | ||
| T394 | /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3560294703 | Jun 21 07:26:46 PM PDT 24 | Jun 21 07:27:05 PM PDT 24 | 7554007186 ps | ||
| T395 | /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1522933033 | Jun 21 07:27:38 PM PDT 24 | Jun 21 07:27:44 PM PDT 24 | 493011765 ps | ||
| T396 | /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2455847188 | Jun 21 07:26:38 PM PDT 24 | Jun 21 07:26:56 PM PDT 24 | 456937554 ps | ||
| T397 | /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2286733181 | Jun 21 07:27:27 PM PDT 24 | Jun 21 07:27:32 PM PDT 24 | 333986973 ps | ||
| T398 | /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4167801059 | Jun 21 07:27:20 PM PDT 24 | Jun 21 07:27:32 PM PDT 24 | 4378458105 ps | ||
| T399 | /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1962582304 | Jun 21 07:27:05 PM PDT 24 | Jun 21 07:27:17 PM PDT 24 | 397836281 ps | ||
| T400 | /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4190330427 | Jun 21 07:27:37 PM PDT 24 | Jun 21 07:27:44 PM PDT 24 | 286538803 ps | ||
| T401 | /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3663579320 | Jun 21 07:26:45 PM PDT 24 | Jun 21 07:27:01 PM PDT 24 | 592616926 ps | ||
| T402 | /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3045705475 | Jun 21 07:27:41 PM PDT 24 | Jun 21 07:27:47 PM PDT 24 | 368207335 ps | ||
| T403 | /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.177189947 | Jun 21 07:26:36 PM PDT 24 | Jun 21 07:26:55 PM PDT 24 | 1278889337 ps | ||
| T404 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3012827785 | Jun 21 07:26:55 PM PDT 24 | Jun 21 07:27:10 PM PDT 24 | 449024793 ps | ||
| T405 | /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.678427316 | Jun 21 07:26:47 PM PDT 24 | Jun 21 07:27:03 PM PDT 24 | 5061370053 ps | ||
| T406 | /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.681112808 | Jun 21 07:27:37 PM PDT 24 | Jun 21 07:27:45 PM PDT 24 | 499240781 ps | ||
| T193 | /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.885407592 | Jun 21 07:27:06 PM PDT 24 | Jun 21 07:27:22 PM PDT 24 | 7971434603 ps | ||
| T407 | /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3254121974 | Jun 21 07:27:46 PM PDT 24 | Jun 21 07:27:53 PM PDT 24 | 396010248 ps | ||
| T408 | /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.101022083 | Jun 21 07:27:37 PM PDT 24 | Jun 21 07:27:43 PM PDT 24 | 399563931 ps | ||
| T64 | /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3744587196 | Jun 21 07:27:31 PM PDT 24 | Jun 21 07:27:37 PM PDT 24 | 314742885 ps | ||
| T409 | /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2379904748 | Jun 21 07:26:50 PM PDT 24 | Jun 21 07:27:05 PM PDT 24 | 338439582 ps | ||
| T410 | /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3649478894 | Jun 21 07:27:01 PM PDT 24 | Jun 21 07:27:15 PM PDT 24 | 730746220 ps | ||
| T411 | /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2050576740 | Jun 21 07:26:37 PM PDT 24 | Jun 21 07:26:54 PM PDT 24 | 524607639 ps | ||
| T412 | /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.935558378 | Jun 21 07:26:54 PM PDT 24 | Jun 21 07:27:10 PM PDT 24 | 7484562238 ps | ||
| T413 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.893632417 | Jun 21 07:26:36 PM PDT 24 | Jun 21 07:26:54 PM PDT 24 | 589014421 ps | ||
| T414 | /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.796914776 | Jun 21 07:26:38 PM PDT 24 | Jun 21 07:26:56 PM PDT 24 | 613498830 ps | ||
| T415 | /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3396856860 | Jun 21 07:27:44 PM PDT 24 | Jun 21 07:27:52 PM PDT 24 | 362412032 ps | ||
| T416 | /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1476331478 | Jun 21 07:27:19 PM PDT 24 | Jun 21 07:27:28 PM PDT 24 | 999851579 ps | ||
| T417 | /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.628547245 | Jun 21 07:26:49 PM PDT 24 | Jun 21 07:27:04 PM PDT 24 | 335692989 ps |
| Test location | /workspace/coverage/default/13.aon_timer_jump.1617392668 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 443728770 ps |
| CPU time | 0.97 seconds |
| Started | Jun 21 06:07:46 PM PDT 24 |
| Finished | Jun 21 06:07:48 PM PDT 24 |
| Peak memory | 197160 kb |
| Host | smart-9005b3ef-c718-4b56-89e6-9462b9c9592f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1617392668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1617392668 |
| Directory | /workspace/13.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2001510274 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 19122831330 ps |
| CPU time | 136.06 seconds |
| Started | Jun 21 06:08:05 PM PDT 24 |
| Finished | Jun 21 06:10:23 PM PDT 24 |
| Peak memory | 207296 kb |
| Host | smart-1d016a98-cba3-453f-b7e9-1c93384089d0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001510274 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2001510274 |
| Directory | /workspace/24.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.aon_timer_stress_all.2314736499 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 170401833159 ps |
| CPU time | 227.8 seconds |
| Started | Jun 21 06:07:22 PM PDT 24 |
| Finished | Jun 21 06:11:11 PM PDT 24 |
| Peak memory | 198744 kb |
| Host | smart-fc10b6e7-ab2c-46e4-b4f1-86b35ecdd9b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314736499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a ll.2314736499 |
| Directory | /workspace/3.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1362523905 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8949890938 ps |
| CPU time | 3.96 seconds |
| Started | Jun 21 07:26:27 PM PDT 24 |
| Finished | Jun 21 07:26:49 PM PDT 24 |
| Peak memory | 198320 kb |
| Host | smart-f86fd01a-629f-47d5-925d-aeeed5efcae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362523905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl _intg_err.1362523905 |
| Directory | /workspace/0.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3385424425 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 371140903361 ps |
| CPU time | 1031.81 seconds |
| Started | Jun 21 06:07:24 PM PDT 24 |
| Finished | Jun 21 06:24:37 PM PDT 24 |
| Peak memory | 211872 kb |
| Host | smart-50dcebf0-b457-4322-97d1-d7710d1dd51c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385424425 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3385424425 |
| Directory | /workspace/3.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.156147940 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 475088456430 ps |
| CPU time | 780.96 seconds |
| Started | Jun 21 06:09:07 PM PDT 24 |
| Finished | Jun 21 06:22:08 PM PDT 24 |
| Peak memory | 207716 kb |
| Host | smart-15332b53-a0ce-451e-ae3c-994db4f33235 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156147940 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.156147940 |
| Directory | /workspace/49.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1037635465 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 10099635955 ps |
| CPU time | 8.84 seconds |
| Started | Jun 21 07:26:39 PM PDT 24 |
| Finished | Jun 21 07:27:03 PM PDT 24 |
| Peak memory | 196356 kb |
| Host | smart-6e0f424b-ccdb-47b0-9b85-9460a46cc490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037635465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b it_bash.1037635465 |
| Directory | /workspace/1.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.109479194 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 257214815644 ps |
| CPU time | 738.51 seconds |
| Started | Jun 21 06:07:57 PM PDT 24 |
| Finished | Jun 21 06:20:16 PM PDT 24 |
| Peak memory | 215468 kb |
| Host | smart-ec6fa5d3-4b7d-43ba-a699-22c44741be38 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109479194 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.109479194 |
| Directory | /workspace/18.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.aon_timer_stress_all.373494996 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 36271571751 ps |
| CPU time | 37.39 seconds |
| Started | Jun 21 06:07:25 PM PDT 24 |
| Finished | Jun 21 06:08:04 PM PDT 24 |
| Peak memory | 192356 kb |
| Host | smart-7b4f683d-c8da-4651-b45e-637c10fc9b08 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373494996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al l.373494996 |
| Directory | /workspace/5.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.96775073 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 104542378347 ps |
| CPU time | 281.2 seconds |
| Started | Jun 21 06:08:21 PM PDT 24 |
| Finished | Jun 21 06:13:03 PM PDT 24 |
| Peak memory | 202000 kb |
| Host | smart-2847c8c7-9f4d-451d-b89d-a7f1ef0803a6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96775073 -assert nopo stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.96775073 |
| Directory | /workspace/29.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1999800520 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 301588378686 ps |
| CPU time | 602.85 seconds |
| Started | Jun 21 06:08:57 PM PDT 24 |
| Finished | Jun 21 06:19:00 PM PDT 24 |
| Peak memory | 214108 kb |
| Host | smart-d1c7350a-7b78-4f47-81c9-c7678b78150e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999800520 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1999800520 |
| Directory | /workspace/45.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.aon_timer_sec_cm.4202257668 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4212096943 ps |
| CPU time | 6.77 seconds |
| Started | Jun 21 06:07:17 PM PDT 24 |
| Finished | Jun 21 06:07:24 PM PDT 24 |
| Peak memory | 216088 kb |
| Host | smart-0540a6de-463c-4f5b-9379-295ab0e80543 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202257668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4202257668 |
| Directory | /workspace/0.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1389323395 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 60542980413 ps |
| CPU time | 417.09 seconds |
| Started | Jun 21 06:07:57 PM PDT 24 |
| Finished | Jun 21 06:14:55 PM PDT 24 |
| Peak memory | 201752 kb |
| Host | smart-7ecb5b12-1b29-45eb-84fd-5b6aa191d196 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389323395 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1389323395 |
| Directory | /workspace/14.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.aon_timer_stress_all.3899863173 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 83091641665 ps |
| CPU time | 118.71 seconds |
| Started | Jun 21 06:08:42 PM PDT 24 |
| Finished | Jun 21 06:10:42 PM PDT 24 |
| Peak memory | 192428 kb |
| Host | smart-d0a3241a-bd71-46e6-9b16-11f50ce6dcec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899863173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_ all.3899863173 |
| Directory | /workspace/36.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/33.aon_timer_stress_all.4123101550 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 404940606423 ps |
| CPU time | 281.9 seconds |
| Started | Jun 21 06:08:30 PM PDT 24 |
| Finished | Jun 21 06:13:13 PM PDT 24 |
| Peak memory | 198728 kb |
| Host | smart-baa02cab-f831-44ef-af47-15cc87c8a7c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123101550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_ all.4123101550 |
| Directory | /workspace/33.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.aon_timer_stress_all.2223202346 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 54541399360 ps |
| CPU time | 39.76 seconds |
| Started | Jun 21 06:08:54 PM PDT 24 |
| Finished | Jun 21 06:09:34 PM PDT 24 |
| Peak memory | 192464 kb |
| Host | smart-327b1df7-5d0e-4b16-9d72-49be5e95d261 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223202346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_ all.2223202346 |
| Directory | /workspace/45.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3207251508 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 137465412859 ps |
| CPU time | 596.85 seconds |
| Started | Jun 21 06:09:04 PM PDT 24 |
| Finished | Jun 21 06:19:02 PM PDT 24 |
| Peak memory | 205076 kb |
| Host | smart-5c4282e7-8136-41f9-8137-70aab185fab5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207251508 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3207251508 |
| Directory | /workspace/47.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1822225992 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 975056690860 ps |
| CPU time | 342.3 seconds |
| Started | Jun 21 06:07:30 PM PDT 24 |
| Finished | Jun 21 06:13:14 PM PDT 24 |
| Peak memory | 202208 kb |
| Host | smart-38c69a5d-bac1-46a6-93e3-378ce782496f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822225992 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1822225992 |
| Directory | /workspace/7.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2434097661 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 75442869772 ps |
| CPU time | 348.08 seconds |
| Started | Jun 21 06:08:30 PM PDT 24 |
| Finished | Jun 21 06:14:18 PM PDT 24 |
| Peak memory | 199116 kb |
| Host | smart-51a09966-567b-4456-8bf5-a77579181b6a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434097661 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2434097661 |
| Directory | /workspace/33.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/18.aon_timer_stress_all.3459619099 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 190834394101 ps |
| CPU time | 127.3 seconds |
| Started | Jun 21 06:07:57 PM PDT 24 |
| Finished | Jun 21 06:10:05 PM PDT 24 |
| Peak memory | 192396 kb |
| Host | smart-e23db066-3fa5-4c0e-8713-25073c353dec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459619099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_ all.3459619099 |
| Directory | /workspace/18.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3556939261 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 109028974844 ps |
| CPU time | 353.35 seconds |
| Started | Jun 21 06:08:05 PM PDT 24 |
| Finished | Jun 21 06:14:00 PM PDT 24 |
| Peak memory | 211052 kb |
| Host | smart-aebefbdc-917b-4d0d-8965-b4731a482ba0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556939261 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3556939261 |
| Directory | /workspace/23.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3816479247 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 494193988717 ps |
| CPU time | 281.93 seconds |
| Started | Jun 21 06:07:39 PM PDT 24 |
| Finished | Jun 21 06:12:21 PM PDT 24 |
| Peak memory | 210128 kb |
| Host | smart-77f12a12-f5be-4551-a753-b0f93928ae1b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816479247 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3816479247 |
| Directory | /workspace/12.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1675265569 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 83049711260 ps |
| CPU time | 264.7 seconds |
| Started | Jun 21 06:07:55 PM PDT 24 |
| Finished | Jun 21 06:12:21 PM PDT 24 |
| Peak memory | 201684 kb |
| Host | smart-9418b692-fc2a-4282-b39b-726578f36b5b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675265569 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1675265569 |
| Directory | /workspace/17.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.aon_timer_stress_all.4270549923 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 105271065209 ps |
| CPU time | 163.63 seconds |
| Started | Jun 21 06:07:23 PM PDT 24 |
| Finished | Jun 21 06:10:08 PM PDT 24 |
| Peak memory | 198792 kb |
| Host | smart-2d0dd8ab-2204-4a43-8c7b-bcfaedbdde8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270549923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a ll.4270549923 |
| Directory | /workspace/6.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/7.aon_timer_stress_all.3045660209 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 226381116855 ps |
| CPU time | 352.37 seconds |
| Started | Jun 21 06:07:24 PM PDT 24 |
| Finished | Jun 21 06:13:17 PM PDT 24 |
| Peak memory | 192428 kb |
| Host | smart-6fec9651-326c-4713-be53-4a63f7a7134a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045660209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a ll.3045660209 |
| Directory | /workspace/7.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.403882295 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 121747117201 ps |
| CPU time | 218.17 seconds |
| Started | Jun 21 06:07:16 PM PDT 24 |
| Finished | Jun 21 06:10:55 PM PDT 24 |
| Peak memory | 207304 kb |
| Host | smart-bc809ea5-48d6-4319-9f5e-ab7a0f75eb89 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403882295 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.403882295 |
| Directory | /workspace/0.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.aon_timer_stress_all.1278803912 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 40880551923 ps |
| CPU time | 14.26 seconds |
| Started | Jun 21 06:07:51 PM PDT 24 |
| Finished | Jun 21 06:08:06 PM PDT 24 |
| Peak memory | 184640 kb |
| Host | smart-217e0c79-b345-4d26-95cb-737cd378e03c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278803912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_ all.1278803912 |
| Directory | /workspace/16.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/39.aon_timer_stress_all.3963777609 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 67520597319 ps |
| CPU time | 51.97 seconds |
| Started | Jun 21 06:08:49 PM PDT 24 |
| Finished | Jun 21 06:09:41 PM PDT 24 |
| Peak memory | 198776 kb |
| Host | smart-1e71f2a9-b85b-4e03-ab25-58e8f2c51034 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963777609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_ all.3963777609 |
| Directory | /workspace/39.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.aon_timer_stress_all.2346771691 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 94033472812 ps |
| CPU time | 143.05 seconds |
| Started | Jun 21 06:07:15 PM PDT 24 |
| Finished | Jun 21 06:09:38 PM PDT 24 |
| Peak memory | 184832 kb |
| Host | smart-0b477f4e-55a0-4c74-a1df-24c3a8610354 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346771691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a ll.2346771691 |
| Directory | /workspace/0.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3651190252 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 80495210527 ps |
| CPU time | 505.83 seconds |
| Started | Jun 21 06:08:33 PM PDT 24 |
| Finished | Jun 21 06:16:59 PM PDT 24 |
| Peak memory | 202284 kb |
| Host | smart-099af035-6e8a-4ff9-8af7-893b42ff4042 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651190252 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3651190252 |
| Directory | /workspace/32.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.aon_timer_stress_all.3717757784 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 202140102946 ps |
| CPU time | 295.29 seconds |
| Started | Jun 21 06:08:12 PM PDT 24 |
| Finished | Jun 21 06:13:08 PM PDT 24 |
| Peak memory | 192984 kb |
| Host | smart-661c305c-836c-4db8-91dc-07c18c0a5115 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717757784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_ all.3717757784 |
| Directory | /workspace/26.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1934248831 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 41856407007 ps |
| CPU time | 448.28 seconds |
| Started | Jun 21 06:07:30 PM PDT 24 |
| Finished | Jun 21 06:14:59 PM PDT 24 |
| Peak memory | 214724 kb |
| Host | smart-547dcd28-d39e-40f1-bd6d-7d4f06b42c29 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934248831 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1934248831 |
| Directory | /workspace/4.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3968957007 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 48374719622 ps |
| CPU time | 403.4 seconds |
| Started | Jun 21 06:08:56 PM PDT 24 |
| Finished | Jun 21 06:15:40 PM PDT 24 |
| Peak memory | 208732 kb |
| Host | smart-3011f0d3-527e-4b4f-a4f8-45525edfddde |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968957007 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3968957007 |
| Directory | /workspace/46.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.aon_timer_stress_all.3236436486 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 557114386619 ps |
| CPU time | 519.37 seconds |
| Started | Jun 21 06:08:55 PM PDT 24 |
| Finished | Jun 21 06:17:35 PM PDT 24 |
| Peak memory | 192436 kb |
| Host | smart-7b60acda-c0a6-418c-8e65-2371ee215675 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236436486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_ all.3236436486 |
| Directory | /workspace/44.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/11.aon_timer_stress_all.3137093778 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 127095012550 ps |
| CPU time | 12.56 seconds |
| Started | Jun 21 06:07:39 PM PDT 24 |
| Finished | Jun 21 06:07:52 PM PDT 24 |
| Peak memory | 193048 kb |
| Host | smart-27118829-f6ac-4377-ab5d-a1f970fa716c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137093778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_ all.3137093778 |
| Directory | /workspace/11.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/23.aon_timer_stress_all.643049848 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 461015888278 ps |
| CPU time | 452.02 seconds |
| Started | Jun 21 06:08:05 PM PDT 24 |
| Finished | Jun 21 06:15:39 PM PDT 24 |
| Peak memory | 193020 kb |
| Host | smart-3125dd1d-0a0b-44ca-83f3-b7bf39b48720 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643049848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a ll.643049848 |
| Directory | /workspace/23.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3233126579 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 102457402406 ps |
| CPU time | 192.28 seconds |
| Started | Jun 21 06:08:31 PM PDT 24 |
| Finished | Jun 21 06:11:44 PM PDT 24 |
| Peak memory | 208932 kb |
| Host | smart-5cd66026-37b1-4b9f-8f45-2188f9910504 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233126579 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3233126579 |
| Directory | /workspace/31.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3339295741 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 82613319093 ps |
| CPU time | 456.65 seconds |
| Started | Jun 21 06:08:50 PM PDT 24 |
| Finished | Jun 21 06:16:27 PM PDT 24 |
| Peak memory | 207324 kb |
| Host | smart-8de9903d-6b5a-4c2f-9b9f-fb9c39978e5b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339295741 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3339295741 |
| Directory | /workspace/39.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1359552972 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 103991418673 ps |
| CPU time | 283.86 seconds |
| Started | Jun 21 06:07:29 PM PDT 24 |
| Finished | Jun 21 06:12:13 PM PDT 24 |
| Peak memory | 202232 kb |
| Host | smart-06a6d5c7-1e7e-45fc-9712-82d09ed40efa |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359552972 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1359552972 |
| Directory | /workspace/5.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.aon_timer_stress_all.3032894122 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 307283907262 ps |
| CPU time | 130.08 seconds |
| Started | Jun 21 06:07:55 PM PDT 24 |
| Finished | Jun 21 06:10:06 PM PDT 24 |
| Peak memory | 198740 kb |
| Host | smart-77e41f57-70fc-4e92-91a0-caeec11c4ddd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032894122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_ all.3032894122 |
| Directory | /workspace/17.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.4230724108 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 69110907869 ps |
| CPU time | 137.66 seconds |
| Started | Jun 21 06:08:03 PM PDT 24 |
| Finished | Jun 21 06:10:21 PM PDT 24 |
| Peak memory | 207276 kb |
| Host | smart-9e1f5a72-4555-4e8b-bf1c-eeb8d30b5770 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230724108 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.4230724108 |
| Directory | /workspace/22.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.aon_timer_stress_all.3707200328 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 672128129693 ps |
| CPU time | 513.09 seconds |
| Started | Jun 21 06:08:42 PM PDT 24 |
| Finished | Jun 21 06:17:16 PM PDT 24 |
| Peak memory | 193208 kb |
| Host | smart-9f8b6f6f-f634-4eee-874f-84e3cd27a36f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707200328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_ all.3707200328 |
| Directory | /workspace/37.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3693636936 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 228528155950 ps |
| CPU time | 427.38 seconds |
| Started | Jun 21 06:08:48 PM PDT 24 |
| Finished | Jun 21 06:15:56 PM PDT 24 |
| Peak memory | 203572 kb |
| Host | smart-d3035b93-e707-47d5-b6d7-524d2f702bf8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693636936 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3693636936 |
| Directory | /workspace/40.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.aon_timer_stress_all.1218549620 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 135897868626 ps |
| CPU time | 89.41 seconds |
| Started | Jun 21 06:07:30 PM PDT 24 |
| Finished | Jun 21 06:09:00 PM PDT 24 |
| Peak memory | 193688 kb |
| Host | smart-9bf1ab19-a8ee-465c-98da-12a939939b5d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218549620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a ll.1218549620 |
| Directory | /workspace/8.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2870343754 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 37680552126 ps |
| CPU time | 142.35 seconds |
| Started | Jun 21 06:08:38 PM PDT 24 |
| Finished | Jun 21 06:11:01 PM PDT 24 |
| Peak memory | 215220 kb |
| Host | smart-22733735-20aa-4cc5-92aa-a6344e02f047 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870343754 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2870343754 |
| Directory | /workspace/35.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2936527779 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 410693492823 ps |
| CPU time | 262.2 seconds |
| Started | Jun 21 06:08:41 PM PDT 24 |
| Finished | Jun 21 06:13:04 PM PDT 24 |
| Peak memory | 201428 kb |
| Host | smart-1a88a931-f4cc-4b75-b173-acf9396b291b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936527779 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2936527779 |
| Directory | /workspace/36.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.aon_timer_stress_all.3500570011 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 284590367126 ps |
| CPU time | 365.79 seconds |
| Started | Jun 21 06:08:40 PM PDT 24 |
| Finished | Jun 21 06:14:46 PM PDT 24 |
| Peak memory | 193524 kb |
| Host | smart-55c71f63-efc0-44d6-93db-a56baa6def44 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500570011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_ all.3500570011 |
| Directory | /workspace/38.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/24.aon_timer_stress_all.1462724591 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 111207641817 ps |
| CPU time | 167.31 seconds |
| Started | Jun 21 06:08:15 PM PDT 24 |
| Finished | Jun 21 06:11:03 PM PDT 24 |
| Peak memory | 193528 kb |
| Host | smart-f4cc22ec-6bde-457b-b3c9-0a6f3def835e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462724591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_ all.1462724591 |
| Directory | /workspace/24.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/29.aon_timer_stress_all.4171899352 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 101148965131 ps |
| CPU time | 61.45 seconds |
| Started | Jun 21 06:08:19 PM PDT 24 |
| Finished | Jun 21 06:09:21 PM PDT 24 |
| Peak memory | 192900 kb |
| Host | smart-5507d15a-62f3-4484-a041-c4151703f73b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171899352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_ all.4171899352 |
| Directory | /workspace/29.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/12.aon_timer_stress_all.3314870086 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 100565950219 ps |
| CPU time | 31.12 seconds |
| Started | Jun 21 06:07:41 PM PDT 24 |
| Finished | Jun 21 06:08:13 PM PDT 24 |
| Peak memory | 198760 kb |
| Host | smart-0fb9fed7-20f6-4cf0-b950-778c2e51f6c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314870086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_ all.3314870086 |
| Directory | /workspace/12.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/20.aon_timer_stress_all.2325712192 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 252732858401 ps |
| CPU time | 72.35 seconds |
| Started | Jun 21 06:08:04 PM PDT 24 |
| Finished | Jun 21 06:09:17 PM PDT 24 |
| Peak memory | 192400 kb |
| Host | smart-926c7b34-10dd-4bc3-b252-b97c32d15f98 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325712192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_ all.2325712192 |
| Directory | /workspace/20.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2922001685 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 114292415476 ps |
| CPU time | 642.62 seconds |
| Started | Jun 21 06:07:39 PM PDT 24 |
| Finished | Jun 21 06:18:22 PM PDT 24 |
| Peak memory | 214032 kb |
| Host | smart-b5495821-3710-4896-adf5-1ba7f758ece2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922001685 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2922001685 |
| Directory | /workspace/10.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.818974858 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 172296482517 ps |
| CPU time | 377.81 seconds |
| Started | Jun 21 06:08:47 PM PDT 24 |
| Finished | Jun 21 06:15:06 PM PDT 24 |
| Peak memory | 210772 kb |
| Host | smart-404e7e83-ea85-452f-b231-4a30c39922f2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818974858 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.818974858 |
| Directory | /workspace/41.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.aon_timer_stress_all.2174143219 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 367343051059 ps |
| CPU time | 473.81 seconds |
| Started | Jun 21 06:09:05 PM PDT 24 |
| Finished | Jun 21 06:17:00 PM PDT 24 |
| Peak memory | 198796 kb |
| Host | smart-a821853c-c2b8-425b-bcec-568a025326b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174143219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_ all.2174143219 |
| Directory | /workspace/49.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/2.aon_timer_stress_all.153679436 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 84723019597 ps |
| CPU time | 125.23 seconds |
| Started | Jun 21 06:07:15 PM PDT 24 |
| Finished | Jun 21 06:09:21 PM PDT 24 |
| Peak memory | 192424 kb |
| Host | smart-3c03a546-0843-44ea-83e5-d9bb4fd0c8a0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153679436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al l.153679436 |
| Directory | /workspace/2.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2007944174 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 155822835892 ps |
| CPU time | 304.65 seconds |
| Started | Jun 21 06:07:15 PM PDT 24 |
| Finished | Jun 21 06:12:21 PM PDT 24 |
| Peak memory | 209972 kb |
| Host | smart-2b09ce81-5762-48a9-b238-1af126551847 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007944174 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2007944174 |
| Directory | /workspace/2.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3308613771 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 917400010 ps |
| CPU time | 1.61 seconds |
| Started | Jun 21 07:27:19 PM PDT 24 |
| Finished | Jun 21 07:27:28 PM PDT 24 |
| Peak memory | 192944 kb |
| Host | smart-14464d36-8431-4b55-8984-3a31e15a5420 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308613771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao n_timer_same_csr_outstanding.3308613771 |
| Directory | /workspace/11.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.469044720 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 307681760057 ps |
| CPU time | 343.77 seconds |
| Started | Jun 21 06:07:45 PM PDT 24 |
| Finished | Jun 21 06:13:29 PM PDT 24 |
| Peak memory | 210840 kb |
| Host | smart-109481cc-2fa1-4fe0-a417-bfb69863db72 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469044720 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.469044720 |
| Directory | /workspace/13.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.aon_timer_stress_all.4085632291 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 107230254135 ps |
| CPU time | 148.73 seconds |
| Started | Jun 21 06:08:53 PM PDT 24 |
| Finished | Jun 21 06:11:23 PM PDT 24 |
| Peak memory | 192660 kb |
| Host | smart-8464d282-73c7-45bd-bfc0-d870435b09be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085632291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_ all.4085632291 |
| Directory | /workspace/41.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/43.aon_timer_stress_all.3216385797 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 77873810982 ps |
| CPU time | 106.33 seconds |
| Started | Jun 21 06:08:59 PM PDT 24 |
| Finished | Jun 21 06:10:46 PM PDT 24 |
| Peak memory | 192364 kb |
| Host | smart-c707afb0-72cd-4dab-abd3-f02c1510053b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216385797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_ all.3216385797 |
| Directory | /workspace/43.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/1.aon_timer_stress_all.1557356312 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 226531048991 ps |
| CPU time | 347.45 seconds |
| Started | Jun 21 06:07:15 PM PDT 24 |
| Finished | Jun 21 06:13:03 PM PDT 24 |
| Peak memory | 198720 kb |
| Host | smart-15a0490c-c353-4977-8590-f4e2d236253a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557356312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a ll.1557356312 |
| Directory | /workspace/1.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/21.aon_timer_stress_all.1922273531 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 66154408029 ps |
| CPU time | 26.11 seconds |
| Started | Jun 21 06:08:04 PM PDT 24 |
| Finished | Jun 21 06:08:31 PM PDT 24 |
| Peak memory | 193544 kb |
| Host | smart-9939c35e-6818-4187-90d6-1583600007da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922273531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_ all.1922273531 |
| Directory | /workspace/21.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/31.aon_timer_stress_all.757925289 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 108340232339 ps |
| CPU time | 162.46 seconds |
| Started | Jun 21 06:08:33 PM PDT 24 |
| Finished | Jun 21 06:11:16 PM PDT 24 |
| Peak memory | 198896 kb |
| Host | smart-3198c3e3-f65f-4901-9882-76644cddacde |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757925289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a ll.757925289 |
| Directory | /workspace/31.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3274248657 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 308510410716 ps |
| CPU time | 769.16 seconds |
| Started | Jun 21 06:08:43 PM PDT 24 |
| Finished | Jun 21 06:21:33 PM PDT 24 |
| Peak memory | 215608 kb |
| Host | smart-90e55f8a-1a54-4dd0-b2e1-d4bbd0f7ed51 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274248657 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3274248657 |
| Directory | /workspace/38.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1234457296 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 45123218848 ps |
| CPU time | 70.11 seconds |
| Started | Jun 21 06:08:02 PM PDT 24 |
| Finished | Jun 21 06:09:13 PM PDT 24 |
| Peak memory | 215372 kb |
| Host | smart-44e8ed86-e6b8-4610-99ff-6b76d528384a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234457296 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1234457296 |
| Directory | /workspace/20.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3144750449 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 72540936550 ps |
| CPU time | 155.41 seconds |
| Started | Jun 21 06:08:04 PM PDT 24 |
| Finished | Jun 21 06:10:40 PM PDT 24 |
| Peak memory | 207556 kb |
| Host | smart-02aa1fed-5c38-4851-bd1e-8a86e5740ca8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144750449 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3144750449 |
| Directory | /workspace/21.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3746126789 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 110951795749 ps |
| CPU time | 229.39 seconds |
| Started | Jun 21 06:08:13 PM PDT 24 |
| Finished | Jun 21 06:12:03 PM PDT 24 |
| Peak memory | 209256 kb |
| Host | smart-5bfc0459-9f71-46a0-98e8-3e7a72111eff |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746126789 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3746126789 |
| Directory | /workspace/25.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.aon_timer_jump.3034515587 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 396045208 ps |
| CPU time | 1.17 seconds |
| Started | Jun 21 06:08:12 PM PDT 24 |
| Finished | Jun 21 06:08:13 PM PDT 24 |
| Peak memory | 197096 kb |
| Host | smart-6559e5f9-d9ed-43ce-8f6d-858dc2434a5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3034515587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3034515587 |
| Directory | /workspace/28.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/32.aon_timer_jump.745757797 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 379499689 ps |
| CPU time | 1.11 seconds |
| Started | Jun 21 06:08:32 PM PDT 24 |
| Finished | Jun 21 06:08:33 PM PDT 24 |
| Peak memory | 197172 kb |
| Host | smart-482cd006-6c16-4e8f-a257-c9e7c51f61ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=745757797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.745757797 |
| Directory | /workspace/32.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/5.aon_timer_jump.2608888850 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 356963456 ps |
| CPU time | 0.87 seconds |
| Started | Jun 21 06:07:23 PM PDT 24 |
| Finished | Jun 21 06:07:25 PM PDT 24 |
| Peak memory | 197100 kb |
| Host | smart-57f1983e-860f-458b-9a9c-cb6caf5810dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608888850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2608888850 |
| Directory | /workspace/5.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/6.aon_timer_jump.2815053977 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 492614170 ps |
| CPU time | 1.34 seconds |
| Started | Jun 21 06:07:23 PM PDT 24 |
| Finished | Jun 21 06:07:26 PM PDT 24 |
| Peak memory | 197064 kb |
| Host | smart-3045924a-99a4-4ae8-9fc2-9fb433ad0d20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815053977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2815053977 |
| Directory | /workspace/6.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1878488035 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 16398565698 ps |
| CPU time | 173.21 seconds |
| Started | Jun 21 06:07:33 PM PDT 24 |
| Finished | Jun 21 06:10:26 PM PDT 24 |
| Peak memory | 207232 kb |
| Host | smart-66d730eb-f501-4576-928d-48b08bc054bd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878488035 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1878488035 |
| Directory | /workspace/8.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.aon_timer_jump.3142404783 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 463249364 ps |
| CPU time | 0.67 seconds |
| Started | Jun 21 06:08:21 PM PDT 24 |
| Finished | Jun 21 06:08:22 PM PDT 24 |
| Peak memory | 197176 kb |
| Host | smart-675df1dd-a899-4150-90d7-c38f4d317fbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3142404783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3142404783 |
| Directory | /workspace/30.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/34.aon_timer_stress_all.2210674075 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 210442464892 ps |
| CPU time | 276.31 seconds |
| Started | Jun 21 06:08:33 PM PDT 24 |
| Finished | Jun 21 06:13:10 PM PDT 24 |
| Peak memory | 192400 kb |
| Host | smart-60342512-c624-4228-80b3-446fa7a1895c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210674075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_ all.2210674075 |
| Directory | /workspace/34.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.aon_timer_jump.2955335139 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 467464856 ps |
| CPU time | 0.95 seconds |
| Started | Jun 21 06:07:24 PM PDT 24 |
| Finished | Jun 21 06:07:26 PM PDT 24 |
| Peak memory | 197088 kb |
| Host | smart-32bb0dca-1ffa-40b3-9102-340abf4be8ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2955335139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2955335139 |
| Directory | /workspace/4.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/4.aon_timer_stress_all.2019375003 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 183870555487 ps |
| CPU time | 67.02 seconds |
| Started | Jun 21 06:07:25 PM PDT 24 |
| Finished | Jun 21 06:08:33 PM PDT 24 |
| Peak memory | 193484 kb |
| Host | smart-1764e2f6-876f-424b-81a9-9c11e794afb1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019375003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a ll.2019375003 |
| Directory | /workspace/4.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/41.aon_timer_jump.1075876705 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 573937851 ps |
| CPU time | 0.79 seconds |
| Started | Jun 21 06:08:49 PM PDT 24 |
| Finished | Jun 21 06:08:50 PM PDT 24 |
| Peak memory | 197176 kb |
| Host | smart-5428322e-4606-41cb-93e7-2f745c16926e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075876705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1075876705 |
| Directory | /workspace/41.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3191940673 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 34385355274 ps |
| CPU time | 387.59 seconds |
| Started | Jun 21 06:08:58 PM PDT 24 |
| Finished | Jun 21 06:15:26 PM PDT 24 |
| Peak memory | 207816 kb |
| Host | smart-55db13a0-1816-408e-b700-253e6d197c5b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191940673 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3191940673 |
| Directory | /workspace/44.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.aon_timer_stress_all.2110938607 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 114224498797 ps |
| CPU time | 11.77 seconds |
| Started | Jun 21 06:09:03 PM PDT 24 |
| Finished | Jun 21 06:09:16 PM PDT 24 |
| Peak memory | 198760 kb |
| Host | smart-dd625f99-17b7-4bbb-8ddc-db74155f7532 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110938607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_ all.2110938607 |
| Directory | /workspace/47.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/11.aon_timer_jump.2463771534 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 469024838 ps |
| CPU time | 1.19 seconds |
| Started | Jun 21 06:07:40 PM PDT 24 |
| Finished | Jun 21 06:07:42 PM PDT 24 |
| Peak memory | 197188 kb |
| Host | smart-ec765fe6-3707-4860-9439-3a34c94e7acf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463771534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2463771534 |
| Directory | /workspace/11.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/16.aon_timer_jump.1768980445 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 351991843 ps |
| CPU time | 1.08 seconds |
| Started | Jun 21 06:07:47 PM PDT 24 |
| Finished | Jun 21 06:07:48 PM PDT 24 |
| Peak memory | 197092 kb |
| Host | smart-fb2221a0-1d84-4a62-a5c6-ae33bf7a3081 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768980445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1768980445 |
| Directory | /workspace/16.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1714601085 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 29908679945 ps |
| CPU time | 236.44 seconds |
| Started | Jun 21 06:08:14 PM PDT 24 |
| Finished | Jun 21 06:12:11 PM PDT 24 |
| Peak memory | 207336 kb |
| Host | smart-ba549c47-78c9-4a74-a0a3-51fa4af4fe77 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714601085 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1714601085 |
| Directory | /workspace/27.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.aon_timer_stress_all.1907440175 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 127076796986 ps |
| CPU time | 21.81 seconds |
| Started | Jun 21 06:08:13 PM PDT 24 |
| Finished | Jun 21 06:08:35 PM PDT 24 |
| Peak memory | 192400 kb |
| Host | smart-2e726c74-7849-44c9-89b2-369517fb0146 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907440175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_ all.1907440175 |
| Directory | /workspace/28.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/34.aon_timer_jump.899093985 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 444283320 ps |
| CPU time | 1.27 seconds |
| Started | Jun 21 06:08:33 PM PDT 24 |
| Finished | Jun 21 06:08:35 PM PDT 24 |
| Peak memory | 197052 kb |
| Host | smart-6e725e55-ff75-4169-a22a-311f239c2cc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=899093985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.899093985 |
| Directory | /workspace/34.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/36.aon_timer_jump.2197787551 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 587220763 ps |
| CPU time | 1.46 seconds |
| Started | Jun 21 06:08:39 PM PDT 24 |
| Finished | Jun 21 06:08:41 PM PDT 24 |
| Peak memory | 197088 kb |
| Host | smart-774334ce-cc4b-4495-8bfd-a84e171707e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2197787551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2197787551 |
| Directory | /workspace/36.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/14.aon_timer_stress_all.2141160539 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 86318867098 ps |
| CPU time | 69.31 seconds |
| Started | Jun 21 06:07:46 PM PDT 24 |
| Finished | Jun 21 06:08:56 PM PDT 24 |
| Peak memory | 198780 kb |
| Host | smart-045c287e-258c-45a1-8503-a2e161a60eff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141160539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_ all.2141160539 |
| Directory | /workspace/14.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/25.aon_timer_jump.2665257111 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 542886067 ps |
| CPU time | 0.83 seconds |
| Started | Jun 21 06:08:15 PM PDT 24 |
| Finished | Jun 21 06:08:17 PM PDT 24 |
| Peak memory | 197112 kb |
| Host | smart-328c0e8d-ed0a-441c-8bc6-ddc3dab5cf23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665257111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2665257111 |
| Directory | /workspace/25.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/3.aon_timer_jump.4187696011 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 371807047 ps |
| CPU time | 0.84 seconds |
| Started | Jun 21 06:07:23 PM PDT 24 |
| Finished | Jun 21 06:07:25 PM PDT 24 |
| Peak memory | 197096 kb |
| Host | smart-b56f7aa7-f349-4946-a5e7-1fcefd55ef73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187696011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.4187696011 |
| Directory | /workspace/3.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/37.aon_timer_jump.988997036 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 476018846 ps |
| CPU time | 1.24 seconds |
| Started | Jun 21 06:08:42 PM PDT 24 |
| Finished | Jun 21 06:08:44 PM PDT 24 |
| Peak memory | 197100 kb |
| Host | smart-31308143-1a12-47e8-85fd-6de980e1bf7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=988997036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.988997036 |
| Directory | /workspace/37.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/46.aon_timer_jump.2016214906 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 488975641 ps |
| CPU time | 1.38 seconds |
| Started | Jun 21 06:08:55 PM PDT 24 |
| Finished | Jun 21 06:08:57 PM PDT 24 |
| Peak memory | 197192 kb |
| Host | smart-74acf494-983f-4870-a212-7f4165258e1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016214906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2016214906 |
| Directory | /workspace/46.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/47.aon_timer_jump.4085797905 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 340796759 ps |
| CPU time | 1.06 seconds |
| Started | Jun 21 06:09:04 PM PDT 24 |
| Finished | Jun 21 06:09:06 PM PDT 24 |
| Peak memory | 197088 kb |
| Host | smart-bea7a13c-e643-4283-a1b9-f2a4a0927a87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4085797905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.4085797905 |
| Directory | /workspace/47.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/48.aon_timer_jump.1286538373 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 370201681 ps |
| CPU time | 0.76 seconds |
| Started | Jun 21 06:09:05 PM PDT 24 |
| Finished | Jun 21 06:09:07 PM PDT 24 |
| Peak memory | 197100 kb |
| Host | smart-269a55de-e889-4c0c-a959-d4b7ad273f0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286538373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1286538373 |
| Directory | /workspace/48.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/49.aon_timer_jump.710851230 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 565602925 ps |
| CPU time | 1.39 seconds |
| Started | Jun 21 06:09:04 PM PDT 24 |
| Finished | Jun 21 06:09:07 PM PDT 24 |
| Peak memory | 197172 kb |
| Host | smart-57ca94f5-e715-429c-9cae-739a169cb913 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710851230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.710851230 |
| Directory | /workspace/49.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/15.aon_timer_stress_all.1753077665 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 221928059215 ps |
| CPU time | 21.61 seconds |
| Started | Jun 21 06:07:47 PM PDT 24 |
| Finished | Jun 21 06:08:10 PM PDT 24 |
| Peak memory | 193368 kb |
| Host | smart-76c62588-2da2-416c-af58-818af89668be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753077665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_ all.1753077665 |
| Directory | /workspace/15.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.151346104 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 7302854222 ps |
| CPU time | 11.54 seconds |
| Started | Jun 21 06:07:49 PM PDT 24 |
| Finished | Jun 21 06:08:01 PM PDT 24 |
| Peak memory | 207272 kb |
| Host | smart-bb7765ad-82ac-4161-8d74-09101fa5a653 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151346104 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.151346104 |
| Directory | /workspace/15.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.aon_timer_jump.1547039298 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 365581472 ps |
| CPU time | 1.21 seconds |
| Started | Jun 21 06:07:16 PM PDT 24 |
| Finished | Jun 21 06:07:18 PM PDT 24 |
| Peak memory | 197192 kb |
| Host | smart-c2880c41-c455-4f6f-8411-7ebf7dc66fd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1547039298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1547039298 |
| Directory | /workspace/2.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/24.aon_timer_jump.955186690 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 409504471 ps |
| CPU time | 1.2 seconds |
| Started | Jun 21 06:08:04 PM PDT 24 |
| Finished | Jun 21 06:08:06 PM PDT 24 |
| Peak memory | 197176 kb |
| Host | smart-7db15202-2d0d-4aef-a217-c3d5c7984e68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955186690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.955186690 |
| Directory | /workspace/24.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/42.aon_timer_stress_all.21058416 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 227711291569 ps |
| CPU time | 323.24 seconds |
| Started | Jun 21 06:08:48 PM PDT 24 |
| Finished | Jun 21 06:14:12 PM PDT 24 |
| Peak memory | 192396 kb |
| Host | smart-5209a816-a4a0-4f41-a2af-a600b5076873 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21058416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_al l.21058416 |
| Directory | /workspace/42.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.aon_timer_stress_all.2222370744 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 266425597553 ps |
| CPU time | 87.63 seconds |
| Started | Jun 21 06:09:05 PM PDT 24 |
| Finished | Jun 21 06:10:34 PM PDT 24 |
| Peak memory | 198752 kb |
| Host | smart-07abb70a-6964-424c-872a-734cb1a68fb2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222370744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_ all.2222370744 |
| Directory | /workspace/48.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/7.aon_timer_jump.2893567236 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 529900430 ps |
| CPU time | 0.67 seconds |
| Started | Jun 21 06:07:31 PM PDT 24 |
| Finished | Jun 21 06:07:32 PM PDT 24 |
| Peak memory | 197084 kb |
| Host | smart-93b23f2e-3526-4126-bd41-2a15e87975ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2893567236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2893567236 |
| Directory | /workspace/7.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/0.aon_timer_jump.3647278149 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 572048062 ps |
| CPU time | 0.81 seconds |
| Started | Jun 21 06:07:05 PM PDT 24 |
| Finished | Jun 21 06:07:07 PM PDT 24 |
| Peak memory | 197104 kb |
| Host | smart-b53c6d78-a6c9-4afc-be24-1cfbf8c5f766 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3647278149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3647278149 |
| Directory | /workspace/0.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.761697640 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 27016808676 ps |
| CPU time | 198.55 seconds |
| Started | Jun 21 06:07:18 PM PDT 24 |
| Finished | Jun 21 06:10:37 PM PDT 24 |
| Peak memory | 207288 kb |
| Host | smart-716d055b-355b-46fb-9715-18fd8c6747c3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761697640 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.761697640 |
| Directory | /workspace/1.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.aon_timer_jump.3195330959 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 483849581 ps |
| CPU time | 0.69 seconds |
| Started | Jun 21 06:08:04 PM PDT 24 |
| Finished | Jun 21 06:08:06 PM PDT 24 |
| Peak memory | 197196 kb |
| Host | smart-10cdc256-9c04-4ee9-bae4-96a1d272b54e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3195330959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3195330959 |
| Directory | /workspace/20.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/22.aon_timer_stress_all.2548606429 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 154636434166 ps |
| CPU time | 121 seconds |
| Started | Jun 21 06:08:05 PM PDT 24 |
| Finished | Jun 21 06:10:07 PM PDT 24 |
| Peak memory | 192492 kb |
| Host | smart-7cb666fd-5a31-4c7c-b559-229f7283d773 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548606429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_ all.2548606429 |
| Directory | /workspace/22.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.aon_timer_jump.1665167474 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 441229374 ps |
| CPU time | 1.35 seconds |
| Started | Jun 21 06:08:13 PM PDT 24 |
| Finished | Jun 21 06:08:15 PM PDT 24 |
| Peak memory | 197144 kb |
| Host | smart-67c30536-a008-44d8-a75e-5bb4489f39d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1665167474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1665167474 |
| Directory | /workspace/26.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/42.aon_timer_jump.1088464329 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 481411285 ps |
| CPU time | 0.82 seconds |
| Started | Jun 21 06:08:48 PM PDT 24 |
| Finished | Jun 21 06:08:49 PM PDT 24 |
| Peak memory | 197068 kb |
| Host | smart-0433db96-b36a-4f3a-bc0a-0bca069d6ace |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1088464329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1088464329 |
| Directory | /workspace/42.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/9.aon_timer_jump.2549511978 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 471620951 ps |
| CPU time | 0.8 seconds |
| Started | Jun 21 06:07:30 PM PDT 24 |
| Finished | Jun 21 06:07:31 PM PDT 24 |
| Peak memory | 197184 kb |
| Host | smart-efbb9d7c-eaf1-45f9-9860-307e15f23b9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2549511978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2549511978 |
| Directory | /workspace/9.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1551355921 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 58423103892 ps |
| CPU time | 609.32 seconds |
| Started | Jun 21 06:07:36 PM PDT 24 |
| Finished | Jun 21 06:17:46 PM PDT 24 |
| Peak memory | 204332 kb |
| Host | smart-9d53a6cb-9b92-468f-b5f8-71abd830d049 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551355921 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1551355921 |
| Directory | /workspace/9.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.aon_timer_jump.237095244 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 422171207 ps |
| CPU time | 1.12 seconds |
| Started | Jun 21 06:07:57 PM PDT 24 |
| Finished | Jun 21 06:07:59 PM PDT 24 |
| Peak memory | 196968 kb |
| Host | smart-14918288-f5be-4816-9f43-93f589a9a8fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=237095244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.237095244 |
| Directory | /workspace/14.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/18.aon_timer_jump.3009974547 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 409341260 ps |
| CPU time | 1.23 seconds |
| Started | Jun 21 06:07:55 PM PDT 24 |
| Finished | Jun 21 06:07:57 PM PDT 24 |
| Peak memory | 197152 kb |
| Host | smart-4a8b10a5-2e04-4b86-9d8a-789ce009e09d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3009974547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3009974547 |
| Directory | /workspace/18.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/19.aon_timer_jump.2830295549 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 541421822 ps |
| CPU time | 1.33 seconds |
| Started | Jun 21 06:07:56 PM PDT 24 |
| Finished | Jun 21 06:07:58 PM PDT 24 |
| Peak memory | 197060 kb |
| Host | smart-d5fef501-5fe3-4b7b-8965-5ffcc8b3b41c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830295549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2830295549 |
| Directory | /workspace/19.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/21.aon_timer_jump.2996358859 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 594902176 ps |
| CPU time | 0.78 seconds |
| Started | Jun 21 06:08:03 PM PDT 24 |
| Finished | Jun 21 06:08:04 PM PDT 24 |
| Peak memory | 197144 kb |
| Host | smart-90c096be-82af-4d99-bc4b-d54a706c04f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996358859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2996358859 |
| Directory | /workspace/21.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/23.aon_timer_jump.230141808 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 582517600 ps |
| CPU time | 1.42 seconds |
| Started | Jun 21 06:08:05 PM PDT 24 |
| Finished | Jun 21 06:08:08 PM PDT 24 |
| Peak memory | 197064 kb |
| Host | smart-3864d02b-1651-4100-b3a9-c67ad57740dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=230141808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.230141808 |
| Directory | /workspace/23.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/25.aon_timer_stress_all.1501272673 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 240431470737 ps |
| CPU time | 356.71 seconds |
| Started | Jun 21 06:08:16 PM PDT 24 |
| Finished | Jun 21 06:14:13 PM PDT 24 |
| Peak memory | 192432 kb |
| Host | smart-507269dc-11e6-47b8-8789-1b94dd7c08f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501272673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_ all.1501272673 |
| Directory | /workspace/25.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.aon_timer_stress_all.969859161 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 229457294233 ps |
| CPU time | 335.55 seconds |
| Started | Jun 21 06:08:40 PM PDT 24 |
| Finished | Jun 21 06:14:16 PM PDT 24 |
| Peak memory | 198788 kb |
| Host | smart-8d89cc34-7d7d-424c-bff7-a8878eb42249 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969859161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a ll.969859161 |
| Directory | /workspace/35.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1840728608 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 14039578565 ps |
| CPU time | 120.77 seconds |
| Started | Jun 21 06:08:42 PM PDT 24 |
| Finished | Jun 21 06:10:43 PM PDT 24 |
| Peak memory | 207472 kb |
| Host | smart-c92470c8-a8d7-478c-b109-6fd460bb12fe |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840728608 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1840728608 |
| Directory | /workspace/37.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.aon_timer_jump.3325099747 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 610312930 ps |
| CPU time | 1 seconds |
| Started | Jun 21 06:08:41 PM PDT 24 |
| Finished | Jun 21 06:08:43 PM PDT 24 |
| Peak memory | 197140 kb |
| Host | smart-72ec003e-b1c8-41ba-b8eb-eab10e08c112 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325099747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3325099747 |
| Directory | /workspace/39.aon_timer_jump/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.885407592 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 7971434603 ps |
| CPU time | 4.28 seconds |
| Started | Jun 21 07:27:06 PM PDT 24 |
| Finished | Jun 21 07:27:22 PM PDT 24 |
| Peak memory | 198148 kb |
| Host | smart-be00f117-d85e-4dc4-9783-fc68608cf7bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885407592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_ intg_err.885407592 |
| Directory | /workspace/7.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/10.aon_timer_jump.2085830878 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 378850384 ps |
| CPU time | 0.74 seconds |
| Started | Jun 21 06:07:40 PM PDT 24 |
| Finished | Jun 21 06:07:42 PM PDT 24 |
| Peak memory | 197072 kb |
| Host | smart-1de9f265-137c-41b3-9d5e-388abc768228 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2085830878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2085830878 |
| Directory | /workspace/10.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1843165399 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 48703190241 ps |
| CPU time | 201.35 seconds |
| Started | Jun 21 06:07:40 PM PDT 24 |
| Finished | Jun 21 06:11:02 PM PDT 24 |
| Peak memory | 199128 kb |
| Host | smart-08613a93-a891-4e20-8ea9-8da4ebf55b97 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843165399 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1843165399 |
| Directory | /workspace/11.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.aon_timer_jump.37066406 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 600204422 ps |
| CPU time | 0.92 seconds |
| Started | Jun 21 06:07:43 PM PDT 24 |
| Finished | Jun 21 06:07:44 PM PDT 24 |
| Peak memory | 197064 kb |
| Host | smart-3e3889c2-1ac3-46fb-8f5c-a0d21ca9b464 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37066406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.37066406 |
| Directory | /workspace/12.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/29.aon_timer_jump.3821887125 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 372048798 ps |
| CPU time | 1.15 seconds |
| Started | Jun 21 06:08:21 PM PDT 24 |
| Finished | Jun 21 06:08:23 PM PDT 24 |
| Peak memory | 197052 kb |
| Host | smart-16897443-e8da-447f-8b53-aa321878e72c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3821887125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3821887125 |
| Directory | /workspace/29.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1414106727 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 53615498809 ps |
| CPU time | 103.83 seconds |
| Started | Jun 21 06:08:23 PM PDT 24 |
| Finished | Jun 21 06:10:08 PM PDT 24 |
| Peak memory | 199116 kb |
| Host | smart-8b6400c0-1450-4cdb-bb1e-8ddc4100dc2f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414106727 -assert no postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1414106727 |
| Directory | /workspace/30.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.aon_timer_jump.2466781102 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 600042430 ps |
| CPU time | 0.77 seconds |
| Started | Jun 21 06:08:30 PM PDT 24 |
| Finished | Jun 21 06:08:31 PM PDT 24 |
| Peak memory | 197064 kb |
| Host | smart-a83aa8d9-2c35-47ed-a2a8-4f7c563fafbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466781102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2466781102 |
| Directory | /workspace/31.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/35.aon_timer_jump.966895870 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 378690095 ps |
| CPU time | 0.9 seconds |
| Started | Jun 21 06:08:38 PM PDT 24 |
| Finished | Jun 21 06:08:39 PM PDT 24 |
| Peak memory | 197032 kb |
| Host | smart-027cc4d1-e142-4059-b3b8-6ba9b31de828 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966895870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.966895870 |
| Directory | /workspace/35.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/43.aon_timer_jump.3323032763 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 516668276 ps |
| CPU time | 0.99 seconds |
| Started | Jun 21 06:08:49 PM PDT 24 |
| Finished | Jun 21 06:08:51 PM PDT 24 |
| Peak memory | 197092 kb |
| Host | smart-bf39d81d-cd9d-47c7-a6d4-fa87efea517c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3323032763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3323032763 |
| Directory | /workspace/43.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/44.aon_timer_jump.1155992528 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 459609626 ps |
| CPU time | 0.82 seconds |
| Started | Jun 21 06:08:54 PM PDT 24 |
| Finished | Jun 21 06:08:56 PM PDT 24 |
| Peak memory | 197144 kb |
| Host | smart-b7273050-4923-427a-b486-237bac24c15c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155992528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1155992528 |
| Directory | /workspace/44.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/46.aon_timer_stress_all.1869593339 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 325826069696 ps |
| CPU time | 432.43 seconds |
| Started | Jun 21 06:09:00 PM PDT 24 |
| Finished | Jun 21 06:16:13 PM PDT 24 |
| Peak memory | 192912 kb |
| Host | smart-c563bf6c-def2-4e23-8a62-42f137ab4fe8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869593339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_ all.1869593339 |
| Directory | /workspace/46.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/8.aon_timer_jump.1171982945 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 386936215 ps |
| CPU time | 0.72 seconds |
| Started | Jun 21 06:07:31 PM PDT 24 |
| Finished | Jun 21 06:07:33 PM PDT 24 |
| Peak memory | 197084 kb |
| Host | smart-e9543231-1b32-4a07-a452-d8e7f0801f79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171982945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1171982945 |
| Directory | /workspace/8.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/1.aon_timer_jump.4203595597 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 495329924 ps |
| CPU time | 1.23 seconds |
| Started | Jun 21 06:07:17 PM PDT 24 |
| Finished | Jun 21 06:07:18 PM PDT 24 |
| Peak memory | 197068 kb |
| Host | smart-9b17f433-aa2e-4716-9848-1291fe421c12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4203595597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.4203595597 |
| Directory | /workspace/1.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/15.aon_timer_jump.698874642 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 563269404 ps |
| CPU time | 0.82 seconds |
| Started | Jun 21 06:07:57 PM PDT 24 |
| Finished | Jun 21 06:07:58 PM PDT 24 |
| Peak memory | 197068 kb |
| Host | smart-6d60f8dc-9f42-443c-880f-358c3538ee1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698874642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.698874642 |
| Directory | /workspace/15.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/17.aon_timer_jump.359861219 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 513997499 ps |
| CPU time | 0.96 seconds |
| Started | Jun 21 06:07:53 PM PDT 24 |
| Finished | Jun 21 06:07:55 PM PDT 24 |
| Peak memory | 197060 kb |
| Host | smart-aa2bad7c-158f-465d-a17e-22fa347a045c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359861219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.359861219 |
| Directory | /workspace/17.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/22.aon_timer_jump.1289296356 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 451447343 ps |
| CPU time | 0.78 seconds |
| Started | Jun 21 06:08:05 PM PDT 24 |
| Finished | Jun 21 06:08:08 PM PDT 24 |
| Peak memory | 197148 kb |
| Host | smart-a48fdd02-2bc1-4dc6-822d-8cff1ea145c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1289296356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1289296356 |
| Directory | /workspace/22.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/27.aon_timer_stress_all.1261752085 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 401793337975 ps |
| CPU time | 304.58 seconds |
| Started | Jun 21 06:08:12 PM PDT 24 |
| Finished | Jun 21 06:13:18 PM PDT 24 |
| Peak memory | 198728 kb |
| Host | smart-32a5bd57-20cf-466b-9dbe-a686c008d673 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261752085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_ all.1261752085 |
| Directory | /workspace/27.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/38.aon_timer_jump.287570490 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 539337753 ps |
| CPU time | 0.78 seconds |
| Started | Jun 21 06:08:39 PM PDT 24 |
| Finished | Jun 21 06:08:40 PM PDT 24 |
| Peak memory | 197144 kb |
| Host | smart-609ad366-2512-4d43-9be6-825515a03224 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=287570490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.287570490 |
| Directory | /workspace/38.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/40.aon_timer_jump.2099153306 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 341095097 ps |
| CPU time | 1.04 seconds |
| Started | Jun 21 06:08:48 PM PDT 24 |
| Finished | Jun 21 06:08:50 PM PDT 24 |
| Peak memory | 197148 kb |
| Host | smart-535f3bed-6c4a-43d3-8b24-4c1c9fafde1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099153306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2099153306 |
| Directory | /workspace/40.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/45.aon_timer_jump.2528019181 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 344585313 ps |
| CPU time | 1.19 seconds |
| Started | Jun 21 06:08:56 PM PDT 24 |
| Finished | Jun 21 06:08:58 PM PDT 24 |
| Peak memory | 197172 kb |
| Host | smart-1d3cfda6-5c5a-47d8-93ba-64b083e63e00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2528019181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2528019181 |
| Directory | /workspace/45.aon_timer_jump/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2050576740 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 524607639 ps |
| CPU time | 1.06 seconds |
| Started | Jun 21 07:26:37 PM PDT 24 |
| Finished | Jun 21 07:26:54 PM PDT 24 |
| Peak memory | 193104 kb |
| Host | smart-bc251aed-d82a-4588-ac9c-548f3fec641e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050576740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a liasing.2050576740 |
| Directory | /workspace/0.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2859174196 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 11713834343 ps |
| CPU time | 25.96 seconds |
| Started | Jun 21 07:26:38 PM PDT 24 |
| Finished | Jun 21 07:27:20 PM PDT 24 |
| Peak memory | 183944 kb |
| Host | smart-3efd4af7-369d-437e-a784-7c21b96b02e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859174196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b it_bash.2859174196 |
| Directory | /workspace/0.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2554568702 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 864041660 ps |
| CPU time | 0.97 seconds |
| Started | Jun 21 07:26:38 PM PDT 24 |
| Finished | Jun 21 07:26:55 PM PDT 24 |
| Peak memory | 193052 kb |
| Host | smart-b2895a33-b182-4327-b900-58f58244d40a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554568702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h w_reset.2554568702 |
| Directory | /workspace/0.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2186260382 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 586672646 ps |
| CPU time | 1.46 seconds |
| Started | Jun 21 07:26:38 PM PDT 24 |
| Finished | Jun 21 07:26:55 PM PDT 24 |
| Peak memory | 196280 kb |
| Host | smart-452a6836-9db5-429e-86d2-05757a1bc33b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186260382 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2186260382 |
| Directory | /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2048116984 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 579797715 ps |
| CPU time | 0.65 seconds |
| Started | Jun 21 07:26:39 PM PDT 24 |
| Finished | Jun 21 07:26:56 PM PDT 24 |
| Peak memory | 193164 kb |
| Host | smart-245c63cc-562e-49cb-8be4-671a6d4456cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048116984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2048116984 |
| Directory | /workspace/0.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3769372883 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 392885174 ps |
| CPU time | 1.1 seconds |
| Started | Jun 21 07:26:26 PM PDT 24 |
| Finished | Jun 21 07:26:46 PM PDT 24 |
| Peak memory | 183680 kb |
| Host | smart-bdf7ebda-167c-4930-b0c7-1f18991734ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769372883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3769372883 |
| Directory | /workspace/0.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.810115628 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 422525571 ps |
| CPU time | 1.06 seconds |
| Started | Jun 21 07:26:30 PM PDT 24 |
| Finished | Jun 21 07:26:49 PM PDT 24 |
| Peak memory | 183556 kb |
| Host | smart-dd4d023a-b032-458f-a862-3933e34b5c78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810115628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti mer_mem_partial_access.810115628 |
| Directory | /workspace/0.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.24590508 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 373525020 ps |
| CPU time | 1.1 seconds |
| Started | Jun 21 07:26:30 PM PDT 24 |
| Finished | Jun 21 07:26:49 PM PDT 24 |
| Peak memory | 183560 kb |
| Host | smart-05799601-abcb-410a-8d50-173103e78da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24590508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wal k.24590508 |
| Directory | /workspace/0.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.177189947 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1278889337 ps |
| CPU time | 2.41 seconds |
| Started | Jun 21 07:26:36 PM PDT 24 |
| Finished | Jun 21 07:26:55 PM PDT 24 |
| Peak memory | 193756 kb |
| Host | smart-75908e6b-fd14-4454-9afd-c8c3dd19a337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177189947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ timer_same_csr_outstanding.177189947 |
| Directory | /workspace/0.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.569258571 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 377783303 ps |
| CPU time | 2.36 seconds |
| Started | Jun 21 07:26:30 PM PDT 24 |
| Finished | Jun 21 07:26:50 PM PDT 24 |
| Peak memory | 198548 kb |
| Host | smart-0d12bd75-ad8b-40f1-b77d-14ce6f7b57e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569258571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.569258571 |
| Directory | /workspace/0.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.796914776 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 613498830 ps |
| CPU time | 1.53 seconds |
| Started | Jun 21 07:26:38 PM PDT 24 |
| Finished | Jun 21 07:26:56 PM PDT 24 |
| Peak memory | 183824 kb |
| Host | smart-6f122ba9-e9bb-4d61-ad31-869bee7b1db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796914776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al iasing.796914776 |
| Directory | /workspace/1.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3622205292 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 806909144 ps |
| CPU time | 0.8 seconds |
| Started | Jun 21 07:26:36 PM PDT 24 |
| Finished | Jun 21 07:26:54 PM PDT 24 |
| Peak memory | 183604 kb |
| Host | smart-749945b9-b7ea-4e3d-a43b-0cb0a6ee1082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622205292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h w_reset.3622205292 |
| Directory | /workspace/1.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.893632417 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 589014421 ps |
| CPU time | 1.32 seconds |
| Started | Jun 21 07:26:36 PM PDT 24 |
| Finished | Jun 21 07:26:54 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-1c8c36c3-4666-4f30-bcca-c7dabfff6653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893632417 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.893632417 |
| Directory | /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4153985225 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 425101809 ps |
| CPU time | 1.26 seconds |
| Started | Jun 21 07:26:38 PM PDT 24 |
| Finished | Jun 21 07:26:55 PM PDT 24 |
| Peak memory | 191868 kb |
| Host | smart-05d8eb20-9847-4523-b617-8cf9791af6a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153985225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.4153985225 |
| Directory | /workspace/1.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2455847188 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 456937554 ps |
| CPU time | 1.18 seconds |
| Started | Jun 21 07:26:38 PM PDT 24 |
| Finished | Jun 21 07:26:56 PM PDT 24 |
| Peak memory | 192880 kb |
| Host | smart-3e2c1a43-9516-401b-9e80-9e9f3300bc11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455847188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2455847188 |
| Directory | /workspace/1.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.515197114 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 416274291 ps |
| CPU time | 1.17 seconds |
| Started | Jun 21 07:26:39 PM PDT 24 |
| Finished | Jun 21 07:26:56 PM PDT 24 |
| Peak memory | 183668 kb |
| Host | smart-014ee5e0-9f43-4e31-81b2-73e5dfeda303 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515197114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti mer_mem_partial_access.515197114 |
| Directory | /workspace/1.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3507626738 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 391309063 ps |
| CPU time | 1.12 seconds |
| Started | Jun 21 07:26:39 PM PDT 24 |
| Finished | Jun 21 07:26:56 PM PDT 24 |
| Peak memory | 183588 kb |
| Host | smart-75ccc1ff-06b6-499f-a031-684b8b0c73f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507626738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w alk.3507626738 |
| Directory | /workspace/1.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2425166627 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1086587429 ps |
| CPU time | 3.89 seconds |
| Started | Jun 21 07:26:38 PM PDT 24 |
| Finished | Jun 21 07:26:58 PM PDT 24 |
| Peak memory | 194076 kb |
| Host | smart-38ec2996-9417-47be-9344-cdbee152d704 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425166627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon _timer_same_csr_outstanding.2425166627 |
| Directory | /workspace/1.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1606120504 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 499529079 ps |
| CPU time | 2.22 seconds |
| Started | Jun 21 07:26:36 PM PDT 24 |
| Finished | Jun 21 07:26:55 PM PDT 24 |
| Peak memory | 198428 kb |
| Host | smart-f84b1267-6f38-4acf-8dc7-f641a2e1a099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606120504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1606120504 |
| Directory | /workspace/1.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.459529355 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4384237382 ps |
| CPU time | 3.83 seconds |
| Started | Jun 21 07:26:38 PM PDT 24 |
| Finished | Jun 21 07:26:58 PM PDT 24 |
| Peak memory | 197764 kb |
| Host | smart-31866166-fdc9-46de-a1f7-0fc385cf29a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459529355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_ intg_err.459529355 |
| Directory | /workspace/1.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.494762296 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 544231790 ps |
| CPU time | 1.46 seconds |
| Started | Jun 21 07:27:21 PM PDT 24 |
| Finished | Jun 21 07:27:29 PM PDT 24 |
| Peak memory | 196152 kb |
| Host | smart-887591f9-b00c-45f3-a07e-b4ba22ee5af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494762296 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.494762296 |
| Directory | /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.253348595 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 409585214 ps |
| CPU time | 0.66 seconds |
| Started | Jun 21 07:27:20 PM PDT 24 |
| Finished | Jun 21 07:27:28 PM PDT 24 |
| Peak memory | 192968 kb |
| Host | smart-9ebcec34-e5a4-45cf-95cc-39733ed968d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253348595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.253348595 |
| Directory | /workspace/10.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2104862353 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 394988278 ps |
| CPU time | 1.04 seconds |
| Started | Jun 21 07:27:22 PM PDT 24 |
| Finished | Jun 21 07:27:29 PM PDT 24 |
| Peak memory | 192892 kb |
| Host | smart-730e9eb8-0ef4-45c7-8c04-e75d9e741091 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104862353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2104862353 |
| Directory | /workspace/10.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2072170170 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1080601017 ps |
| CPU time | 0.95 seconds |
| Started | Jun 21 07:27:21 PM PDT 24 |
| Finished | Jun 21 07:27:28 PM PDT 24 |
| Peak memory | 192948 kb |
| Host | smart-73717495-617e-4c3b-9451-4ede12f80ac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072170170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao n_timer_same_csr_outstanding.2072170170 |
| Directory | /workspace/10.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1600657701 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 357993818 ps |
| CPU time | 1.45 seconds |
| Started | Jun 21 07:27:21 PM PDT 24 |
| Finished | Jun 21 07:27:29 PM PDT 24 |
| Peak memory | 198520 kb |
| Host | smart-3505b454-8283-409b-96d0-c686e962843c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600657701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1600657701 |
| Directory | /workspace/10.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1056561768 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 8597519113 ps |
| CPU time | 14.27 seconds |
| Started | Jun 21 07:27:21 PM PDT 24 |
| Finished | Jun 21 07:27:42 PM PDT 24 |
| Peak memory | 198144 kb |
| Host | smart-e290c66c-5a08-4a54-96e8-9bff233021a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056561768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t l_intg_err.1056561768 |
| Directory | /workspace/10.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3216265596 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 440126720 ps |
| CPU time | 0.97 seconds |
| Started | Jun 21 07:27:21 PM PDT 24 |
| Finished | Jun 21 07:27:28 PM PDT 24 |
| Peak memory | 197968 kb |
| Host | smart-a9b00578-3c24-47de-b13e-8b3bdf3d2331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216265596 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3216265596 |
| Directory | /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.756408796 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 488715634 ps |
| CPU time | 0.74 seconds |
| Started | Jun 21 07:27:20 PM PDT 24 |
| Finished | Jun 21 07:27:27 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-51214cde-ed7d-403b-87ea-1a5fb35c5629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756408796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.756408796 |
| Directory | /workspace/11.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.344736200 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 433987693 ps |
| CPU time | 0.71 seconds |
| Started | Jun 21 07:27:18 PM PDT 24 |
| Finished | Jun 21 07:27:26 PM PDT 24 |
| Peak memory | 192876 kb |
| Host | smart-d11adacb-8a8f-4d0a-b50f-7f0d2a770def |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344736200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.344736200 |
| Directory | /workspace/11.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1971612311 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 372818211 ps |
| CPU time | 2.07 seconds |
| Started | Jun 21 07:27:22 PM PDT 24 |
| Finished | Jun 21 07:27:30 PM PDT 24 |
| Peak memory | 198536 kb |
| Host | smart-3f18c698-6e37-4f2f-b9c1-688757e1a118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971612311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1971612311 |
| Directory | /workspace/11.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4167801059 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4378458105 ps |
| CPU time | 5.76 seconds |
| Started | Jun 21 07:27:20 PM PDT 24 |
| Finished | Jun 21 07:27:32 PM PDT 24 |
| Peak memory | 197596 kb |
| Host | smart-cc34bffb-138c-4843-9dd4-63098f68d52d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167801059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t l_intg_err.4167801059 |
| Directory | /workspace/11.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.287480862 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 549029060 ps |
| CPU time | 1.3 seconds |
| Started | Jun 21 07:27:19 PM PDT 24 |
| Finished | Jun 21 07:27:28 PM PDT 24 |
| Peak memory | 194912 kb |
| Host | smart-868deae5-32b4-4945-b7c6-1c6623118c75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287480862 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.287480862 |
| Directory | /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1365218665 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 503287530 ps |
| CPU time | 1.27 seconds |
| Started | Jun 21 07:27:19 PM PDT 24 |
| Finished | Jun 21 07:27:26 PM PDT 24 |
| Peak memory | 192988 kb |
| Host | smart-5431e085-9081-4331-81fa-6c4eef817716 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365218665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1365218665 |
| Directory | /workspace/12.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3055739191 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 321654196 ps |
| CPU time | 0.63 seconds |
| Started | Jun 21 07:27:18 PM PDT 24 |
| Finished | Jun 21 07:27:26 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-b3a6d614-4079-4538-98b0-3c17c11b9807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055739191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3055739191 |
| Directory | /workspace/12.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4046122932 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1508577586 ps |
| CPU time | 2.34 seconds |
| Started | Jun 21 07:27:18 PM PDT 24 |
| Finished | Jun 21 07:27:27 PM PDT 24 |
| Peak memory | 193324 kb |
| Host | smart-54308770-aa34-4433-8dbc-de1921e5b34d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046122932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao n_timer_same_csr_outstanding.4046122932 |
| Directory | /workspace/12.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2947587044 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 384954249 ps |
| CPU time | 1.81 seconds |
| Started | Jun 21 07:27:20 PM PDT 24 |
| Finished | Jun 21 07:27:28 PM PDT 24 |
| Peak memory | 198516 kb |
| Host | smart-c1f945d8-163c-4058-8f51-4bde8bddb877 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947587044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2947587044 |
| Directory | /workspace/12.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3787076138 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 8062912027 ps |
| CPU time | 13.19 seconds |
| Started | Jun 21 07:27:19 PM PDT 24 |
| Finished | Jun 21 07:27:38 PM PDT 24 |
| Peak memory | 198164 kb |
| Host | smart-d5ae4d8f-a38f-44d9-89ec-5f8d41fc6679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787076138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t l_intg_err.3787076138 |
| Directory | /workspace/12.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1027626110 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 425906880 ps |
| CPU time | 1.02 seconds |
| Started | Jun 21 07:27:27 PM PDT 24 |
| Finished | Jun 21 07:27:33 PM PDT 24 |
| Peak memory | 196484 kb |
| Host | smart-bca3a48f-06c8-4af7-a546-1ef7728e3613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027626110 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1027626110 |
| Directory | /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2074559513 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 560403932 ps |
| CPU time | 0.61 seconds |
| Started | Jun 21 07:27:29 PM PDT 24 |
| Finished | Jun 21 07:27:35 PM PDT 24 |
| Peak memory | 183776 kb |
| Host | smart-cc806e71-6918-46b1-b4e8-28e6141e196c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074559513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2074559513 |
| Directory | /workspace/13.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.373921442 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 515687414 ps |
| CPU time | 1.18 seconds |
| Started | Jun 21 07:27:21 PM PDT 24 |
| Finished | Jun 21 07:27:29 PM PDT 24 |
| Peak memory | 192880 kb |
| Host | smart-9dc2d410-fe41-4681-b8cc-9e25ce027aa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373921442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.373921442 |
| Directory | /workspace/13.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4134220229 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2503133931 ps |
| CPU time | 2.64 seconds |
| Started | Jun 21 07:27:30 PM PDT 24 |
| Finished | Jun 21 07:27:37 PM PDT 24 |
| Peak memory | 194932 kb |
| Host | smart-f124b3ec-8d4d-41de-9a69-207ae37a5687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134220229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao n_timer_same_csr_outstanding.4134220229 |
| Directory | /workspace/13.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1476331478 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 999851579 ps |
| CPU time | 1.22 seconds |
| Started | Jun 21 07:27:19 PM PDT 24 |
| Finished | Jun 21 07:27:28 PM PDT 24 |
| Peak memory | 198372 kb |
| Host | smart-036f665e-2e53-4e5b-910e-365c61ffd5db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476331478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1476331478 |
| Directory | /workspace/13.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.125285841 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 4053410445 ps |
| CPU time | 3.94 seconds |
| Started | Jun 21 07:27:19 PM PDT 24 |
| Finished | Jun 21 07:27:29 PM PDT 24 |
| Peak memory | 197784 kb |
| Host | smart-a49e2f18-c271-49a7-a71b-5eb43027717c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125285841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl _intg_err.125285841 |
| Directory | /workspace/13.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3062208049 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 547621706 ps |
| CPU time | 1.52 seconds |
| Started | Jun 21 07:27:29 PM PDT 24 |
| Finished | Jun 21 07:27:35 PM PDT 24 |
| Peak memory | 196164 kb |
| Host | smart-3104de1b-cc04-4fc0-b5ae-fe31906b1dc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062208049 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3062208049 |
| Directory | /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2475521562 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 464416603 ps |
| CPU time | 0.73 seconds |
| Started | Jun 21 07:27:29 PM PDT 24 |
| Finished | Jun 21 07:27:35 PM PDT 24 |
| Peak memory | 192028 kb |
| Host | smart-3cde6f70-5a7d-4d66-b409-78a036c82a9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475521562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2475521562 |
| Directory | /workspace/14.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2713753301 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 426272285 ps |
| CPU time | 0.97 seconds |
| Started | Jun 21 07:27:32 PM PDT 24 |
| Finished | Jun 21 07:27:38 PM PDT 24 |
| Peak memory | 192848 kb |
| Host | smart-227f091c-b330-44e5-8b16-f48b6e6438e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713753301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2713753301 |
| Directory | /workspace/14.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2632890506 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2676242942 ps |
| CPU time | 2.21 seconds |
| Started | Jun 21 07:27:28 PM PDT 24 |
| Finished | Jun 21 07:27:35 PM PDT 24 |
| Peak memory | 195040 kb |
| Host | smart-366a9aa7-2e90-40bc-8023-51f5bcf52af6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632890506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao n_timer_same_csr_outstanding.2632890506 |
| Directory | /workspace/14.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3553247231 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 571714924 ps |
| CPU time | 1.56 seconds |
| Started | Jun 21 07:27:31 PM PDT 24 |
| Finished | Jun 21 07:27:37 PM PDT 24 |
| Peak memory | 198376 kb |
| Host | smart-6b81ac38-8743-4d86-a5c5-f33fc91f32e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553247231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3553247231 |
| Directory | /workspace/14.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2191822320 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4576544914 ps |
| CPU time | 6.63 seconds |
| Started | Jun 21 07:27:29 PM PDT 24 |
| Finished | Jun 21 07:27:40 PM PDT 24 |
| Peak memory | 197796 kb |
| Host | smart-e394b5d1-0bf9-4214-8d30-2cdbe7459982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191822320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t l_intg_err.2191822320 |
| Directory | /workspace/14.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2380206053 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 382982963 ps |
| CPU time | 1.25 seconds |
| Started | Jun 21 07:27:29 PM PDT 24 |
| Finished | Jun 21 07:27:34 PM PDT 24 |
| Peak memory | 195948 kb |
| Host | smart-a9ae86b8-b59d-4f2a-bab4-83efcd4ecf97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380206053 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2380206053 |
| Directory | /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2576043557 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 432556518 ps |
| CPU time | 1.17 seconds |
| Started | Jun 21 07:27:27 PM PDT 24 |
| Finished | Jun 21 07:27:33 PM PDT 24 |
| Peak memory | 192876 kb |
| Host | smart-f8049571-7535-4c6e-bdaa-5638be209d31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576043557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2576043557 |
| Directory | /workspace/15.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3435434065 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 383201630 ps |
| CPU time | 0.61 seconds |
| Started | Jun 21 07:27:29 PM PDT 24 |
| Finished | Jun 21 07:27:34 PM PDT 24 |
| Peak memory | 183652 kb |
| Host | smart-1fbf9ae5-cbf2-4bcc-ad42-fdad6dc8f240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435434065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3435434065 |
| Directory | /workspace/15.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1673257347 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2697797339 ps |
| CPU time | 1.64 seconds |
| Started | Jun 21 07:27:31 PM PDT 24 |
| Finished | Jun 21 07:27:37 PM PDT 24 |
| Peak memory | 193884 kb |
| Host | smart-ea6be4b3-a44c-4274-b371-e831a7407e73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673257347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao n_timer_same_csr_outstanding.1673257347 |
| Directory | /workspace/15.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4284067377 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 510962235 ps |
| CPU time | 2.17 seconds |
| Started | Jun 21 07:27:31 PM PDT 24 |
| Finished | Jun 21 07:27:38 PM PDT 24 |
| Peak memory | 198544 kb |
| Host | smart-f4161628-9faf-4ef1-bc4f-3f158036a2be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284067377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.4284067377 |
| Directory | /workspace/15.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.130097422 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4922349613 ps |
| CPU time | 2.6 seconds |
| Started | Jun 21 07:27:29 PM PDT 24 |
| Finished | Jun 21 07:27:36 PM PDT 24 |
| Peak memory | 196764 kb |
| Host | smart-fca5c604-6865-404a-8eb0-32d462644326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130097422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl _intg_err.130097422 |
| Directory | /workspace/15.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1555946260 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 565100560 ps |
| CPU time | 0.91 seconds |
| Started | Jun 21 07:27:30 PM PDT 24 |
| Finished | Jun 21 07:27:36 PM PDT 24 |
| Peak memory | 198412 kb |
| Host | smart-d0c1a65e-2f0d-4994-b66b-c1d591595a27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555946260 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1555946260 |
| Directory | /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3744587196 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 314742885 ps |
| CPU time | 0.71 seconds |
| Started | Jun 21 07:27:31 PM PDT 24 |
| Finished | Jun 21 07:27:37 PM PDT 24 |
| Peak memory | 193228 kb |
| Host | smart-0f38d9be-5617-4cff-8316-744184cadfac |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744587196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3744587196 |
| Directory | /workspace/16.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2711314515 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 296135257 ps |
| CPU time | 0.84 seconds |
| Started | Jun 21 07:27:28 PM PDT 24 |
| Finished | Jun 21 07:27:33 PM PDT 24 |
| Peak memory | 183652 kb |
| Host | smart-4e5aace7-4879-4e59-b71d-eee0d5605013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711314515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2711314515 |
| Directory | /workspace/16.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.163470015 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1448964646 ps |
| CPU time | 1.63 seconds |
| Started | Jun 21 07:27:28 PM PDT 24 |
| Finished | Jun 21 07:27:34 PM PDT 24 |
| Peak memory | 193220 kb |
| Host | smart-66c31f72-3a99-406d-9c7a-a5e68617793c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163470015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon _timer_same_csr_outstanding.163470015 |
| Directory | /workspace/16.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1075368590 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 429046771 ps |
| CPU time | 2.1 seconds |
| Started | Jun 21 07:27:29 PM PDT 24 |
| Finished | Jun 21 07:27:35 PM PDT 24 |
| Peak memory | 198520 kb |
| Host | smart-9542bb5f-bc48-4e08-8e09-3fb81f37cd7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075368590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1075368590 |
| Directory | /workspace/16.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2087261075 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 8518826239 ps |
| CPU time | 12.45 seconds |
| Started | Jun 21 07:27:31 PM PDT 24 |
| Finished | Jun 21 07:27:48 PM PDT 24 |
| Peak memory | 197920 kb |
| Host | smart-c9e11a9c-7793-46b7-971f-e3e60f631d86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087261075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t l_intg_err.2087261075 |
| Directory | /workspace/16.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2295314685 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 469503832 ps |
| CPU time | 1.35 seconds |
| Started | Jun 21 07:27:27 PM PDT 24 |
| Finished | Jun 21 07:27:33 PM PDT 24 |
| Peak memory | 196416 kb |
| Host | smart-0500a5fe-bb01-4dd0-9d2f-e9c60bcadfd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295314685 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2295314685 |
| Directory | /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3080710918 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 542494895 ps |
| CPU time | 1.34 seconds |
| Started | Jun 21 07:27:28 PM PDT 24 |
| Finished | Jun 21 07:27:34 PM PDT 24 |
| Peak memory | 193180 kb |
| Host | smart-693413ab-7369-426d-8ca7-4281c977e23a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080710918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3080710918 |
| Directory | /workspace/17.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2286733181 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 333986973 ps |
| CPU time | 0.65 seconds |
| Started | Jun 21 07:27:27 PM PDT 24 |
| Finished | Jun 21 07:27:32 PM PDT 24 |
| Peak memory | 183640 kb |
| Host | smart-0ce99df0-a109-44bf-95ac-b1d9b58bf879 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286733181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2286733181 |
| Directory | /workspace/17.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2384584300 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1263651947 ps |
| CPU time | 3.04 seconds |
| Started | Jun 21 07:27:28 PM PDT 24 |
| Finished | Jun 21 07:27:35 PM PDT 24 |
| Peak memory | 192948 kb |
| Host | smart-44dd55ed-c3fd-4f89-b904-caa5f1cb2645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384584300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao n_timer_same_csr_outstanding.2384584300 |
| Directory | /workspace/17.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.844244399 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 365690711 ps |
| CPU time | 2.38 seconds |
| Started | Jun 21 07:27:30 PM PDT 24 |
| Finished | Jun 21 07:27:37 PM PDT 24 |
| Peak memory | 198480 kb |
| Host | smart-b073db8c-8cf8-42cc-b7e4-66c54be31e71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844244399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.844244399 |
| Directory | /workspace/17.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1454900608 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4169614668 ps |
| CPU time | 6.82 seconds |
| Started | Jun 21 07:27:30 PM PDT 24 |
| Finished | Jun 21 07:27:42 PM PDT 24 |
| Peak memory | 197912 kb |
| Host | smart-1ce8a669-412a-46c2-997b-8ff5276636b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454900608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t l_intg_err.1454900608 |
| Directory | /workspace/17.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4160289966 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 421372268 ps |
| CPU time | 0.79 seconds |
| Started | Jun 21 07:27:27 PM PDT 24 |
| Finished | Jun 21 07:27:33 PM PDT 24 |
| Peak memory | 195784 kb |
| Host | smart-3a5e092f-0567-4f9b-a27e-dab63328b83e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160289966 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.4160289966 |
| Directory | /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1861908906 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 525932364 ps |
| CPU time | 0.65 seconds |
| Started | Jun 21 07:27:29 PM PDT 24 |
| Finished | Jun 21 07:27:35 PM PDT 24 |
| Peak memory | 192972 kb |
| Host | smart-9838aae5-8b37-4773-9fc2-1edf57c209bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861908906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1861908906 |
| Directory | /workspace/18.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3571148002 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 486993672 ps |
| CPU time | 0.94 seconds |
| Started | Jun 21 07:27:29 PM PDT 24 |
| Finished | Jun 21 07:27:35 PM PDT 24 |
| Peak memory | 183672 kb |
| Host | smart-d17416e8-c7b4-429a-a18e-aac03bdec11d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571148002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3571148002 |
| Directory | /workspace/18.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.804042149 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2769957401 ps |
| CPU time | 1.13 seconds |
| Started | Jun 21 07:27:32 PM PDT 24 |
| Finished | Jun 21 07:27:38 PM PDT 24 |
| Peak memory | 193888 kb |
| Host | smart-0306c985-b4d9-4030-8a48-f4377cefddc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804042149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon _timer_same_csr_outstanding.804042149 |
| Directory | /workspace/18.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2649412779 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 835375925 ps |
| CPU time | 2.42 seconds |
| Started | Jun 21 07:27:32 PM PDT 24 |
| Finished | Jun 21 07:27:39 PM PDT 24 |
| Peak memory | 198560 kb |
| Host | smart-7baab913-b86e-4f88-8c4c-4a9fe4aa866c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649412779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2649412779 |
| Directory | /workspace/18.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.930139151 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4657540342 ps |
| CPU time | 4.4 seconds |
| Started | Jun 21 07:27:27 PM PDT 24 |
| Finished | Jun 21 07:27:36 PM PDT 24 |
| Peak memory | 197860 kb |
| Host | smart-a77989e4-7165-469e-ad0f-abe1cd1b150d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930139151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl _intg_err.930139151 |
| Directory | /workspace/18.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3912619782 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 371587086 ps |
| CPU time | 1.02 seconds |
| Started | Jun 21 07:27:36 PM PDT 24 |
| Finished | Jun 21 07:27:42 PM PDT 24 |
| Peak memory | 196356 kb |
| Host | smart-a3535320-42c3-406d-900a-5cb6dc94ae65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912619782 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3912619782 |
| Directory | /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3261187930 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 523539513 ps |
| CPU time | 0.8 seconds |
| Started | Jun 21 07:27:40 PM PDT 24 |
| Finished | Jun 21 07:27:47 PM PDT 24 |
| Peak memory | 193076 kb |
| Host | smart-cbdf6375-5c39-4cce-b502-3067b2093a6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261187930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3261187930 |
| Directory | /workspace/19.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3847863211 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 394590368 ps |
| CPU time | 0.74 seconds |
| Started | Jun 21 07:27:39 PM PDT 24 |
| Finished | Jun 21 07:27:46 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-7745c25a-f6b1-4484-aa42-f19d1cc90297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847863211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3847863211 |
| Directory | /workspace/19.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2539989374 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 2496513101 ps |
| CPU time | 3.86 seconds |
| Started | Jun 21 07:27:38 PM PDT 24 |
| Finished | Jun 21 07:27:48 PM PDT 24 |
| Peak memory | 183900 kb |
| Host | smart-18e0e2a3-43bd-4c21-8122-e70ad6e0d574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539989374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao n_timer_same_csr_outstanding.2539989374 |
| Directory | /workspace/19.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.681112808 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 499240781 ps |
| CPU time | 2.26 seconds |
| Started | Jun 21 07:27:37 PM PDT 24 |
| Finished | Jun 21 07:27:45 PM PDT 24 |
| Peak memory | 198548 kb |
| Host | smart-90702f8d-c069-41f7-897f-d952c8dd2e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681112808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.681112808 |
| Directory | /workspace/19.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3076258685 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 8105867659 ps |
| CPU time | 4.22 seconds |
| Started | Jun 21 07:27:40 PM PDT 24 |
| Finished | Jun 21 07:27:50 PM PDT 24 |
| Peak memory | 198216 kb |
| Host | smart-78e8174b-a019-4f6c-9039-401116a6b76c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076258685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t l_intg_err.3076258685 |
| Directory | /workspace/19.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3546574020 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 446285872 ps |
| CPU time | 1.42 seconds |
| Started | Jun 21 07:26:46 PM PDT 24 |
| Finished | Jun 21 07:27:02 PM PDT 24 |
| Peak memory | 191868 kb |
| Host | smart-333d419e-868a-489c-85d9-5f0f7046ba9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546574020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a liasing.3546574020 |
| Directory | /workspace/2.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1809216166 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 5757479111 ps |
| CPU time | 6.8 seconds |
| Started | Jun 21 07:26:47 PM PDT 24 |
| Finished | Jun 21 07:27:08 PM PDT 24 |
| Peak memory | 196172 kb |
| Host | smart-3089ddd7-be57-4359-84ff-fd3d921e866b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809216166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b it_bash.1809216166 |
| Directory | /workspace/2.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3750858525 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 820652431 ps |
| CPU time | 0.81 seconds |
| Started | Jun 21 07:26:46 PM PDT 24 |
| Finished | Jun 21 07:27:02 PM PDT 24 |
| Peak memory | 191928 kb |
| Host | smart-a0dcb93d-8466-44e6-a635-9a5a607c35be |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750858525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h w_reset.3750858525 |
| Directory | /workspace/2.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3663579320 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 592616926 ps |
| CPU time | 0.89 seconds |
| Started | Jun 21 07:26:45 PM PDT 24 |
| Finished | Jun 21 07:27:01 PM PDT 24 |
| Peak memory | 196196 kb |
| Host | smart-2aac62af-2144-47a7-9417-1d43dfccd320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663579320 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3663579320 |
| Directory | /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1791475668 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 524167027 ps |
| CPU time | 1.33 seconds |
| Started | Jun 21 07:26:46 PM PDT 24 |
| Finished | Jun 21 07:27:02 PM PDT 24 |
| Peak memory | 191864 kb |
| Host | smart-73bce78f-f52e-47e6-9eb4-3ee24687bb40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791475668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1791475668 |
| Directory | /workspace/2.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1168438419 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 497641503 ps |
| CPU time | 0.64 seconds |
| Started | Jun 21 07:26:37 PM PDT 24 |
| Finished | Jun 21 07:26:54 PM PDT 24 |
| Peak memory | 192880 kb |
| Host | smart-b29dc928-768b-40d9-a6d5-e4b9950cf1b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168438419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1168438419 |
| Directory | /workspace/2.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3521832516 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 509836682 ps |
| CPU time | 1.25 seconds |
| Started | Jun 21 07:26:46 PM PDT 24 |
| Finished | Jun 21 07:27:02 PM PDT 24 |
| Peak memory | 183664 kb |
| Host | smart-a07f9acc-0697-4279-acfa-7e270c5c8ac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521832516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t imer_mem_partial_access.3521832516 |
| Directory | /workspace/2.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4262206765 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 323006078 ps |
| CPU time | 0.94 seconds |
| Started | Jun 21 07:26:38 PM PDT 24 |
| Finished | Jun 21 07:26:55 PM PDT 24 |
| Peak memory | 183588 kb |
| Host | smart-ee32552b-a75e-4fdd-b55f-df491e851275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262206765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w alk.4262206765 |
| Directory | /workspace/2.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.958347970 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2279496299 ps |
| CPU time | 3.77 seconds |
| Started | Jun 21 07:26:46 PM PDT 24 |
| Finished | Jun 21 07:27:05 PM PDT 24 |
| Peak memory | 194360 kb |
| Host | smart-a5c559b4-bb0b-4668-b18d-3ab1f960d780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958347970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ timer_same_csr_outstanding.958347970 |
| Directory | /workspace/2.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3533165535 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1641185785 ps |
| CPU time | 1.59 seconds |
| Started | Jun 21 07:26:38 PM PDT 24 |
| Finished | Jun 21 07:26:56 PM PDT 24 |
| Peak memory | 198520 kb |
| Host | smart-dcc84e24-5ce2-4337-a471-c65a591f8a45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533165535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3533165535 |
| Directory | /workspace/2.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1412956744 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4718379350 ps |
| CPU time | 2.69 seconds |
| Started | Jun 21 07:26:38 PM PDT 24 |
| Finished | Jun 21 07:26:57 PM PDT 24 |
| Peak memory | 197732 kb |
| Host | smart-4dd8b946-f0f8-4485-a77f-8bd391d447a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412956744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl _intg_err.1412956744 |
| Directory | /workspace/2.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.196691458 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 501198769 ps |
| CPU time | 0.93 seconds |
| Started | Jun 21 07:27:39 PM PDT 24 |
| Finished | Jun 21 07:27:46 PM PDT 24 |
| Peak memory | 183616 kb |
| Host | smart-5e829e99-73b1-4cdd-ba66-9f2ad6652ed4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196691458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.196691458 |
| Directory | /workspace/20.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3197275594 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 362423161 ps |
| CPU time | 1.03 seconds |
| Started | Jun 21 07:27:39 PM PDT 24 |
| Finished | Jun 21 07:27:46 PM PDT 24 |
| Peak memory | 183628 kb |
| Host | smart-a971aef8-e915-4a9b-a3ef-18ebdb28be03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197275594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3197275594 |
| Directory | /workspace/21.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1066438041 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 455991397 ps |
| CPU time | 0.72 seconds |
| Started | Jun 21 07:27:37 PM PDT 24 |
| Finished | Jun 21 07:27:43 PM PDT 24 |
| Peak memory | 183664 kb |
| Host | smart-fd6b5733-29d5-4f86-b501-33030bad3013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066438041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1066438041 |
| Directory | /workspace/22.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.992033586 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 446150012 ps |
| CPU time | 1.17 seconds |
| Started | Jun 21 07:27:39 PM PDT 24 |
| Finished | Jun 21 07:27:47 PM PDT 24 |
| Peak memory | 183660 kb |
| Host | smart-05100630-2a23-44a4-be41-9ec33f259ad3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992033586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.992033586 |
| Directory | /workspace/23.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4179210471 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 541724471 ps |
| CPU time | 0.62 seconds |
| Started | Jun 21 07:27:40 PM PDT 24 |
| Finished | Jun 21 07:27:46 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-c38d6570-a543-494e-952e-8ecca2dc0502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179210471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4179210471 |
| Directory | /workspace/24.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2983960660 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 342668419 ps |
| CPU time | 1.03 seconds |
| Started | Jun 21 07:27:38 PM PDT 24 |
| Finished | Jun 21 07:27:45 PM PDT 24 |
| Peak memory | 183676 kb |
| Host | smart-bb40978e-ec8f-4bf0-95d1-f57cfbc75feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983960660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2983960660 |
| Directory | /workspace/25.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2207611010 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 518719869 ps |
| CPU time | 0.9 seconds |
| Started | Jun 21 07:27:38 PM PDT 24 |
| Finished | Jun 21 07:27:45 PM PDT 24 |
| Peak memory | 183592 kb |
| Host | smart-4d50f61d-167c-440d-b188-24469c229ae1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207611010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2207611010 |
| Directory | /workspace/26.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1522933033 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 493011765 ps |
| CPU time | 1.17 seconds |
| Started | Jun 21 07:27:38 PM PDT 24 |
| Finished | Jun 21 07:27:44 PM PDT 24 |
| Peak memory | 183740 kb |
| Host | smart-a875ffa2-1e21-4230-b7a3-3aeae581d0c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522933033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1522933033 |
| Directory | /workspace/27.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2375474647 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 512460371 ps |
| CPU time | 0.85 seconds |
| Started | Jun 21 07:27:36 PM PDT 24 |
| Finished | Jun 21 07:27:42 PM PDT 24 |
| Peak memory | 192876 kb |
| Host | smart-383b63cf-6566-42c2-895c-da34e49c5d32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375474647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2375474647 |
| Directory | /workspace/28.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.576661814 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 308218351 ps |
| CPU time | 0.99 seconds |
| Started | Jun 21 07:27:37 PM PDT 24 |
| Finished | Jun 21 07:27:43 PM PDT 24 |
| Peak memory | 183660 kb |
| Host | smart-2b012f0f-cf06-48ee-88e9-51b69ad99745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576661814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.576661814 |
| Directory | /workspace/29.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2028007940 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 388429009 ps |
| CPU time | 1.18 seconds |
| Started | Jun 21 07:26:47 PM PDT 24 |
| Finished | Jun 21 07:27:03 PM PDT 24 |
| Peak memory | 193016 kb |
| Host | smart-df5b7c85-7ff3-40c2-bae2-90f083069d60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028007940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a liasing.2028007940 |
| Directory | /workspace/3.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3560294703 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 7554007186 ps |
| CPU time | 4.03 seconds |
| Started | Jun 21 07:26:46 PM PDT 24 |
| Finished | Jun 21 07:27:05 PM PDT 24 |
| Peak memory | 192072 kb |
| Host | smart-f2069d89-6bc4-4a7e-917f-1196992bca56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560294703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b it_bash.3560294703 |
| Directory | /workspace/3.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1101097820 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 819654665 ps |
| CPU time | 1.68 seconds |
| Started | Jun 21 07:26:47 PM PDT 24 |
| Finished | Jun 21 07:27:03 PM PDT 24 |
| Peak memory | 183668 kb |
| Host | smart-66720809-0fae-42f2-b4a4-9fed8ec158cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101097820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h w_reset.1101097820 |
| Directory | /workspace/3.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.901837491 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 575210043 ps |
| CPU time | 1.12 seconds |
| Started | Jun 21 07:26:57 PM PDT 24 |
| Finished | Jun 21 07:27:12 PM PDT 24 |
| Peak memory | 198456 kb |
| Host | smart-2bc49951-8311-47d6-bc26-3b6c0df88e88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901837491 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.901837491 |
| Directory | /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3483265638 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 493465361 ps |
| CPU time | 0.77 seconds |
| Started | Jun 21 07:26:46 PM PDT 24 |
| Finished | Jun 21 07:27:02 PM PDT 24 |
| Peak memory | 193172 kb |
| Host | smart-f31c2dac-2f04-4837-9e10-a47fe31a589b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483265638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3483265638 |
| Directory | /workspace/3.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.628547245 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 335692989 ps |
| CPU time | 0.64 seconds |
| Started | Jun 21 07:26:49 PM PDT 24 |
| Finished | Jun 21 07:27:04 PM PDT 24 |
| Peak memory | 183660 kb |
| Host | smart-c5df5de1-cc7b-45a4-8cb2-b12e1ba93ad0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628547245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.628547245 |
| Directory | /workspace/3.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1383200045 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 495412690 ps |
| CPU time | 1.14 seconds |
| Started | Jun 21 07:26:47 PM PDT 24 |
| Finished | Jun 21 07:27:03 PM PDT 24 |
| Peak memory | 183596 kb |
| Host | smart-36e39699-e215-4c73-954e-fe217f11d780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383200045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t imer_mem_partial_access.1383200045 |
| Directory | /workspace/3.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2379904748 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 338439582 ps |
| CPU time | 0.65 seconds |
| Started | Jun 21 07:26:50 PM PDT 24 |
| Finished | Jun 21 07:27:05 PM PDT 24 |
| Peak memory | 183588 kb |
| Host | smart-98150593-74d0-4ec4-aeae-3dfe8d91064a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379904748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w alk.2379904748 |
| Directory | /workspace/3.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.556698459 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2279796172 ps |
| CPU time | 3.65 seconds |
| Started | Jun 21 07:27:00 PM PDT 24 |
| Finished | Jun 21 07:27:16 PM PDT 24 |
| Peak memory | 194996 kb |
| Host | smart-c085bcfb-375a-4cad-9201-5723577e5b68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556698459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ timer_same_csr_outstanding.556698459 |
| Directory | /workspace/3.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.510919787 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 548027368 ps |
| CPU time | 1.54 seconds |
| Started | Jun 21 07:26:47 PM PDT 24 |
| Finished | Jun 21 07:27:03 PM PDT 24 |
| Peak memory | 198516 kb |
| Host | smart-fd5ce1a6-3483-42bc-9ec3-9888eb540553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510919787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.510919787 |
| Directory | /workspace/3.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.678427316 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 5061370053 ps |
| CPU time | 1.3 seconds |
| Started | Jun 21 07:26:47 PM PDT 24 |
| Finished | Jun 21 07:27:03 PM PDT 24 |
| Peak memory | 196648 kb |
| Host | smart-80b5b505-8b9e-4a3b-8722-c9a1ab0db3c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678427316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_ intg_err.678427316 |
| Directory | /workspace/3.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1768194636 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 374552152 ps |
| CPU time | 1.1 seconds |
| Started | Jun 21 07:27:40 PM PDT 24 |
| Finished | Jun 21 07:27:47 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-326d5ba4-7907-40bc-b5b5-925f2b823780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768194636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1768194636 |
| Directory | /workspace/30.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4190330427 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 286538803 ps |
| CPU time | 0.97 seconds |
| Started | Jun 21 07:27:37 PM PDT 24 |
| Finished | Jun 21 07:27:44 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-bebab332-3dbb-4d4f-87a5-877e65719557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190330427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.4190330427 |
| Directory | /workspace/31.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3304441496 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 307316439 ps |
| CPU time | 0.66 seconds |
| Started | Jun 21 07:27:39 PM PDT 24 |
| Finished | Jun 21 07:27:46 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-bdd27ae6-1965-4769-8564-6449105c6d97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304441496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3304441496 |
| Directory | /workspace/32.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1546425924 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 294549887 ps |
| CPU time | 0.72 seconds |
| Started | Jun 21 07:27:38 PM PDT 24 |
| Finished | Jun 21 07:27:44 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-751546ed-56c7-46f7-b613-d3a821aefde9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546425924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1546425924 |
| Directory | /workspace/33.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.101022083 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 399563931 ps |
| CPU time | 0.69 seconds |
| Started | Jun 21 07:27:37 PM PDT 24 |
| Finished | Jun 21 07:27:43 PM PDT 24 |
| Peak memory | 192880 kb |
| Host | smart-3a8a56ce-ce5f-4a14-be12-564b59a55f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101022083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.101022083 |
| Directory | /workspace/34.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.732663461 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 375747280 ps |
| CPU time | 0.68 seconds |
| Started | Jun 21 07:27:39 PM PDT 24 |
| Finished | Jun 21 07:27:46 PM PDT 24 |
| Peak memory | 183636 kb |
| Host | smart-0c01b405-3962-4d6b-9a1a-b023a7d1af0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732663461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.732663461 |
| Directory | /workspace/35.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.921163328 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 483126009 ps |
| CPU time | 0.72 seconds |
| Started | Jun 21 07:27:36 PM PDT 24 |
| Finished | Jun 21 07:27:43 PM PDT 24 |
| Peak memory | 192820 kb |
| Host | smart-8a1cd17d-1353-42d6-87a4-3b002462c1a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921163328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.921163328 |
| Directory | /workspace/36.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3045705475 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 368207335 ps |
| CPU time | 0.81 seconds |
| Started | Jun 21 07:27:41 PM PDT 24 |
| Finished | Jun 21 07:27:47 PM PDT 24 |
| Peak memory | 192876 kb |
| Host | smart-20cb6a24-6e9a-4203-b565-9eaef8f0fac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045705475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3045705475 |
| Directory | /workspace/37.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1894213768 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 297756796 ps |
| CPU time | 0.73 seconds |
| Started | Jun 21 07:27:39 PM PDT 24 |
| Finished | Jun 21 07:27:46 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-12b44f89-5db5-479c-9fc9-9b019c5f816b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894213768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1894213768 |
| Directory | /workspace/38.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1942542070 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 452149950 ps |
| CPU time | 1.18 seconds |
| Started | Jun 21 07:27:38 PM PDT 24 |
| Finished | Jun 21 07:27:44 PM PDT 24 |
| Peak memory | 183632 kb |
| Host | smart-d7e70286-d777-4cc1-a9da-ba67af719b0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942542070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1942542070 |
| Directory | /workspace/39.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2300268610 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 387777180 ps |
| CPU time | 1.41 seconds |
| Started | Jun 21 07:26:56 PM PDT 24 |
| Finished | Jun 21 07:27:12 PM PDT 24 |
| Peak memory | 192960 kb |
| Host | smart-9b19e540-2ddf-4626-9046-8f73b084cc5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300268610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a liasing.2300268610 |
| Directory | /workspace/4.aon_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.935558378 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 7484562238 ps |
| CPU time | 2.41 seconds |
| Started | Jun 21 07:26:54 PM PDT 24 |
| Finished | Jun 21 07:27:10 PM PDT 24 |
| Peak memory | 183888 kb |
| Host | smart-b82f01fe-05e1-4bf7-b17d-19a6358a3388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935558378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi t_bash.935558378 |
| Directory | /workspace/4.aon_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1633900964 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1426797860 ps |
| CPU time | 1.3 seconds |
| Started | Jun 21 07:27:00 PM PDT 24 |
| Finished | Jun 21 07:27:14 PM PDT 24 |
| Peak memory | 192860 kb |
| Host | smart-3230b71f-64df-4a86-8e8f-ba67960064f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633900964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h w_reset.1633900964 |
| Directory | /workspace/4.aon_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3012827785 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 449024793 ps |
| CPU time | 1.28 seconds |
| Started | Jun 21 07:26:55 PM PDT 24 |
| Finished | Jun 21 07:27:10 PM PDT 24 |
| Peak memory | 195628 kb |
| Host | smart-5edc3c1f-6fa2-4480-87a7-a2f5a3abc85d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012827785 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3012827785 |
| Directory | /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.414609992 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 546820407 ps |
| CPU time | 0.63 seconds |
| Started | Jun 21 07:26:59 PM PDT 24 |
| Finished | Jun 21 07:27:13 PM PDT 24 |
| Peak memory | 192860 kb |
| Host | smart-7487283d-90a5-41a4-8743-76abae9f0634 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414609992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.414609992 |
| Directory | /workspace/4.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2741297510 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 357397511 ps |
| CPU time | 1.03 seconds |
| Started | Jun 21 07:26:56 PM PDT 24 |
| Finished | Jun 21 07:27:10 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-1c702437-1fc5-4db8-9c3d-1c9b215f3e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741297510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2741297510 |
| Directory | /workspace/4.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4066757333 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 314709790 ps |
| CPU time | 0.95 seconds |
| Started | Jun 21 07:26:54 PM PDT 24 |
| Finished | Jun 21 07:27:08 PM PDT 24 |
| Peak memory | 183588 kb |
| Host | smart-aab1072e-9c39-4eb1-bf97-7edec94ac1c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066757333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t imer_mem_partial_access.4066757333 |
| Directory | /workspace/4.aon_timer_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1089274141 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 509543558 ps |
| CPU time | 0.88 seconds |
| Started | Jun 21 07:26:54 PM PDT 24 |
| Finished | Jun 21 07:27:08 PM PDT 24 |
| Peak memory | 183588 kb |
| Host | smart-14a982dc-9280-4ac2-a8f2-a2a414ef4544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089274141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w alk.1089274141 |
| Directory | /workspace/4.aon_timer_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3450251457 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2445446256 ps |
| CPU time | 1.47 seconds |
| Started | Jun 21 07:26:56 PM PDT 24 |
| Finished | Jun 21 07:27:12 PM PDT 24 |
| Peak memory | 195028 kb |
| Host | smart-c15b0ac0-431a-4405-961c-b184fec6977d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450251457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon _timer_same_csr_outstanding.3450251457 |
| Directory | /workspace/4.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1633073375 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 344871712 ps |
| CPU time | 2.66 seconds |
| Started | Jun 21 07:26:54 PM PDT 24 |
| Finished | Jun 21 07:27:10 PM PDT 24 |
| Peak memory | 198552 kb |
| Host | smart-44434d69-37b5-4f90-9689-2ce33158c75e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633073375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1633073375 |
| Directory | /workspace/4.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2049835982 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 4467395683 ps |
| CPU time | 7.09 seconds |
| Started | Jun 21 07:26:55 PM PDT 24 |
| Finished | Jun 21 07:27:14 PM PDT 24 |
| Peak memory | 197940 kb |
| Host | smart-d92ab542-06f4-45cd-a364-47666ca211da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049835982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl _intg_err.2049835982 |
| Directory | /workspace/4.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1799814458 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 559201549 ps |
| CPU time | 0.62 seconds |
| Started | Jun 21 07:27:35 PM PDT 24 |
| Finished | Jun 21 07:27:41 PM PDT 24 |
| Peak memory | 183560 kb |
| Host | smart-3b80f9df-f2e8-461a-9aa2-686d665b4d3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799814458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1799814458 |
| Directory | /workspace/40.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2412722094 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 388241477 ps |
| CPU time | 0.57 seconds |
| Started | Jun 21 07:27:35 PM PDT 24 |
| Finished | Jun 21 07:27:41 PM PDT 24 |
| Peak memory | 183604 kb |
| Host | smart-3e1d0b59-5045-4b86-857e-cbcbfc99695f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412722094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2412722094 |
| Directory | /workspace/41.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3402772669 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 419761039 ps |
| CPU time | 1.15 seconds |
| Started | Jun 21 07:27:44 PM PDT 24 |
| Finished | Jun 21 07:27:52 PM PDT 24 |
| Peak memory | 183740 kb |
| Host | smart-6ade6faf-c520-4898-9a34-f39f20173abd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402772669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3402772669 |
| Directory | /workspace/42.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2492460526 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 413752308 ps |
| CPU time | 0.69 seconds |
| Started | Jun 21 07:27:44 PM PDT 24 |
| Finished | Jun 21 07:27:52 PM PDT 24 |
| Peak memory | 183660 kb |
| Host | smart-349bbe87-cd22-413c-bec1-0aea2da5e5de |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492460526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2492460526 |
| Directory | /workspace/43.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.721086504 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 590536635 ps |
| CPU time | 0.61 seconds |
| Started | Jun 21 07:27:45 PM PDT 24 |
| Finished | Jun 21 07:27:52 PM PDT 24 |
| Peak memory | 183612 kb |
| Host | smart-90f244fe-6b73-4d54-8cb5-83305ec68776 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721086504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.721086504 |
| Directory | /workspace/44.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3254121974 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 396010248 ps |
| CPU time | 0.71 seconds |
| Started | Jun 21 07:27:46 PM PDT 24 |
| Finished | Jun 21 07:27:53 PM PDT 24 |
| Peak memory | 183596 kb |
| Host | smart-dbf1d093-7040-468e-bef5-047fed06b6f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254121974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3254121974 |
| Directory | /workspace/45.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.144442308 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 403130967 ps |
| CPU time | 0.66 seconds |
| Started | Jun 21 07:27:44 PM PDT 24 |
| Finished | Jun 21 07:27:51 PM PDT 24 |
| Peak memory | 183672 kb |
| Host | smart-464a91d2-3a31-4163-8f29-a9dbd612201a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144442308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.144442308 |
| Directory | /workspace/46.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3029007456 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 271326759 ps |
| CPU time | 0.73 seconds |
| Started | Jun 21 07:27:46 PM PDT 24 |
| Finished | Jun 21 07:27:53 PM PDT 24 |
| Peak memory | 183672 kb |
| Host | smart-0bae0e78-f52b-4364-867a-6f9716872e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029007456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3029007456 |
| Directory | /workspace/47.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2820223316 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 460707668 ps |
| CPU time | 0.72 seconds |
| Started | Jun 21 07:27:43 PM PDT 24 |
| Finished | Jun 21 07:27:50 PM PDT 24 |
| Peak memory | 192876 kb |
| Host | smart-94c4aaff-7b1e-4618-bd01-e5777273e026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820223316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2820223316 |
| Directory | /workspace/48.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3396856860 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 362412032 ps |
| CPU time | 1.09 seconds |
| Started | Jun 21 07:27:44 PM PDT 24 |
| Finished | Jun 21 07:27:52 PM PDT 24 |
| Peak memory | 192892 kb |
| Host | smart-6f590446-c406-4657-8483-93d04e424f9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396856860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3396856860 |
| Directory | /workspace/49.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4159194644 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 505930848 ps |
| CPU time | 1.33 seconds |
| Started | Jun 21 07:26:55 PM PDT 24 |
| Finished | Jun 21 07:27:09 PM PDT 24 |
| Peak memory | 196156 kb |
| Host | smart-84421b78-433f-498c-ac26-d8c3f3b6cde7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159194644 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.4159194644 |
| Directory | /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3226623518 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 475527304 ps |
| CPU time | 1.29 seconds |
| Started | Jun 21 07:26:55 PM PDT 24 |
| Finished | Jun 21 07:27:10 PM PDT 24 |
| Peak memory | 193968 kb |
| Host | smart-14ac8b5f-0b6d-4984-b50a-8b4e51e49d48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226623518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3226623518 |
| Directory | /workspace/5.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.346138641 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 310495772 ps |
| CPU time | 0.99 seconds |
| Started | Jun 21 07:26:55 PM PDT 24 |
| Finished | Jun 21 07:27:10 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-44b294b9-3aaf-4647-9a1b-25f0027eb515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346138641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.346138641 |
| Directory | /workspace/5.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2252423894 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2133009807 ps |
| CPU time | 1.47 seconds |
| Started | Jun 21 07:26:54 PM PDT 24 |
| Finished | Jun 21 07:27:09 PM PDT 24 |
| Peak memory | 193872 kb |
| Host | smart-bed496a8-bf3b-41b1-82af-662df4a8bc91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252423894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon _timer_same_csr_outstanding.2252423894 |
| Directory | /workspace/5.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1937312233 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2019304314 ps |
| CPU time | 2.23 seconds |
| Started | Jun 21 07:26:57 PM PDT 24 |
| Finished | Jun 21 07:27:14 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-5aa034f6-ab6e-4739-ba34-c0f2d0eab6fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937312233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1937312233 |
| Directory | /workspace/5.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3432797006 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3896016065 ps |
| CPU time | 6.19 seconds |
| Started | Jun 21 07:26:57 PM PDT 24 |
| Finished | Jun 21 07:27:17 PM PDT 24 |
| Peak memory | 198424 kb |
| Host | smart-ebb9e66b-b372-4956-b1ac-27475ec5b99e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432797006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl _intg_err.3432797006 |
| Directory | /workspace/5.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4024938579 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 581904048 ps |
| CPU time | 0.91 seconds |
| Started | Jun 21 07:27:00 PM PDT 24 |
| Finished | Jun 21 07:27:14 PM PDT 24 |
| Peak memory | 197392 kb |
| Host | smart-7624705a-1278-4f58-93c5-3111cd863b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024938579 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.4024938579 |
| Directory | /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3469901371 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 525146298 ps |
| CPU time | 1 seconds |
| Started | Jun 21 07:26:54 PM PDT 24 |
| Finished | Jun 21 07:27:08 PM PDT 24 |
| Peak memory | 183968 kb |
| Host | smart-59629d86-6b80-4dd0-8c05-93acc1213530 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469901371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3469901371 |
| Directory | /workspace/6.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2138189722 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 329517895 ps |
| CPU time | 0.99 seconds |
| Started | Jun 21 07:26:59 PM PDT 24 |
| Finished | Jun 21 07:27:13 PM PDT 24 |
| Peak memory | 183644 kb |
| Host | smart-d72c9f6f-b846-427b-8bfc-308d511bd67e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138189722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2138189722 |
| Directory | /workspace/6.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2784373732 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1694527203 ps |
| CPU time | 0.95 seconds |
| Started | Jun 21 07:26:54 PM PDT 24 |
| Finished | Jun 21 07:27:09 PM PDT 24 |
| Peak memory | 193328 kb |
| Host | smart-8d1f0107-b453-496f-ae5b-308b2eef487f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784373732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon _timer_same_csr_outstanding.2784373732 |
| Directory | /workspace/6.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4139493829 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 645228669 ps |
| CPU time | 2.44 seconds |
| Started | Jun 21 07:26:54 PM PDT 24 |
| Finished | Jun 21 07:27:10 PM PDT 24 |
| Peak memory | 198480 kb |
| Host | smart-6ff6dfa6-ca2f-4bbb-b46d-01b9619f1a40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139493829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.4139493829 |
| Directory | /workspace/6.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1847393241 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 7720300499 ps |
| CPU time | 11.81 seconds |
| Started | Jun 21 07:26:55 PM PDT 24 |
| Finished | Jun 21 07:27:20 PM PDT 24 |
| Peak memory | 198056 kb |
| Host | smart-dd966b70-3813-4037-996a-32c08a74108f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847393241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl _intg_err.1847393241 |
| Directory | /workspace/6.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3597936532 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 439337423 ps |
| CPU time | 1.32 seconds |
| Started | Jun 21 07:27:05 PM PDT 24 |
| Finished | Jun 21 07:27:18 PM PDT 24 |
| Peak memory | 196496 kb |
| Host | smart-11f9e865-0934-4c42-9463-ae23dd2c3da0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597936532 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3597936532 |
| Directory | /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1100608516 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 418629498 ps |
| CPU time | 0.87 seconds |
| Started | Jun 21 07:27:03 PM PDT 24 |
| Finished | Jun 21 07:27:16 PM PDT 24 |
| Peak memory | 193168 kb |
| Host | smart-d2b23e06-6005-4d6a-843f-c9937e7a17ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100608516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1100608516 |
| Directory | /workspace/7.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1977416269 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 392314950 ps |
| CPU time | 0.69 seconds |
| Started | Jun 21 07:27:03 PM PDT 24 |
| Finished | Jun 21 07:27:16 PM PDT 24 |
| Peak memory | 192876 kb |
| Host | smart-01875248-eb4f-483f-b807-984d107c79f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977416269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1977416269 |
| Directory | /workspace/7.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1692619757 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1097871035 ps |
| CPU time | 1.34 seconds |
| Started | Jun 21 07:27:04 PM PDT 24 |
| Finished | Jun 21 07:27:18 PM PDT 24 |
| Peak memory | 192940 kb |
| Host | smart-dd360aa4-f778-4776-a2d3-99e66d789700 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692619757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon _timer_same_csr_outstanding.1692619757 |
| Directory | /workspace/7.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3445155311 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1118432743 ps |
| CPU time | 1.64 seconds |
| Started | Jun 21 07:27:05 PM PDT 24 |
| Finished | Jun 21 07:27:19 PM PDT 24 |
| Peak memory | 198476 kb |
| Host | smart-ca87c551-f5f0-42e2-b236-b24980ee05c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445155311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3445155311 |
| Directory | /workspace/7.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.471383187 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 536776226 ps |
| CPU time | 1.09 seconds |
| Started | Jun 21 07:27:04 PM PDT 24 |
| Finished | Jun 21 07:27:16 PM PDT 24 |
| Peak memory | 197012 kb |
| Host | smart-85a0964a-8dc8-40aa-807f-2e19acc2434f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471383187 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.471383187 |
| Directory | /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3098972510 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 440757857 ps |
| CPU time | 0.67 seconds |
| Started | Jun 21 07:27:02 PM PDT 24 |
| Finished | Jun 21 07:27:16 PM PDT 24 |
| Peak memory | 193908 kb |
| Host | smart-88834624-8413-45f7-9e37-274d0ee5bec4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098972510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3098972510 |
| Directory | /workspace/8.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1962582304 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 397836281 ps |
| CPU time | 0.6 seconds |
| Started | Jun 21 07:27:05 PM PDT 24 |
| Finished | Jun 21 07:27:17 PM PDT 24 |
| Peak memory | 183656 kb |
| Host | smart-8839ac8e-21a5-442c-8318-2451495ac405 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962582304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1962582304 |
| Directory | /workspace/8.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.87834546 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1277407851 ps |
| CPU time | 1.05 seconds |
| Started | Jun 21 07:27:05 PM PDT 24 |
| Finished | Jun 21 07:27:18 PM PDT 24 |
| Peak memory | 183796 kb |
| Host | smart-d3b0359c-5889-4df1-a00d-ff8db916e390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87834546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_t imer_same_csr_outstanding.87834546 |
| Directory | /workspace/8.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3649478894 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 730746220 ps |
| CPU time | 2.35 seconds |
| Started | Jun 21 07:27:01 PM PDT 24 |
| Finished | Jun 21 07:27:15 PM PDT 24 |
| Peak memory | 198476 kb |
| Host | smart-61c2ba61-1c59-4891-9db0-ec5f96381058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649478894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3649478894 |
| Directory | /workspace/8.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3278922138 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4868553654 ps |
| CPU time | 2.38 seconds |
| Started | Jun 21 07:27:05 PM PDT 24 |
| Finished | Jun 21 07:27:19 PM PDT 24 |
| Peak memory | 196652 kb |
| Host | smart-1c530926-b2af-4af6-8d49-b428b64bab5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278922138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl _intg_err.3278922138 |
| Directory | /workspace/8.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.912392618 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 551356752 ps |
| CPU time | 1.06 seconds |
| Started | Jun 21 07:27:11 PM PDT 24 |
| Finished | Jun 21 07:27:22 PM PDT 24 |
| Peak memory | 196012 kb |
| Host | smart-ab67159d-9925-4bf0-9b7c-b481deaac96d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912392618 -assert nopostproc +UVM_TESTNAME= aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.912392618 |
| Directory | /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4123468281 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 501531484 ps |
| CPU time | 1.24 seconds |
| Started | Jun 21 07:27:11 PM PDT 24 |
| Finished | Jun 21 07:27:22 PM PDT 24 |
| Peak memory | 192884 kb |
| Host | smart-7629c0df-a4b8-4b15-811e-25330bbe65cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123468281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.4123468281 |
| Directory | /workspace/9.aon_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1858867990 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 307305909 ps |
| CPU time | 0.61 seconds |
| Started | Jun 21 07:27:02 PM PDT 24 |
| Finished | Jun 21 07:27:16 PM PDT 24 |
| Peak memory | 192828 kb |
| Host | smart-a5cae6d5-ed17-4c09-bb34-e57b28478f23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858867990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1858867990 |
| Directory | /workspace/9.aon_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2547727159 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2651301671 ps |
| CPU time | 2.22 seconds |
| Started | Jun 21 07:27:12 PM PDT 24 |
| Finished | Jun 21 07:27:24 PM PDT 24 |
| Peak memory | 194872 kb |
| Host | smart-42bce78e-4c25-4901-9db4-865d91087129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547727159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ= aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon _timer_same_csr_outstanding.2547727159 |
| Directory | /workspace/9.aon_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4148837291 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 472600021 ps |
| CPU time | 1.15 seconds |
| Started | Jun 21 07:27:05 PM PDT 24 |
| Finished | Jun 21 07:27:19 PM PDT 24 |
| Peak memory | 198388 kb |
| Host | smart-0468b90f-5b53-4b94-8c29-929417baf33c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148837291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.4148837291 |
| Directory | /workspace/9.aon_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1950370109 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4053129985 ps |
| CPU time | 3.71 seconds |
| Started | Jun 21 07:27:03 PM PDT 24 |
| Finished | Jun 21 07:27:19 PM PDT 24 |
| Peak memory | 197432 kb |
| Host | smart-92abf756-18cd-4484-a3ff-82cb2faf281d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950370109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl _intg_err.1950370109 |
| Directory | /workspace/9.aon_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.aon_timer_prescaler.1400884790 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 30614408201 ps |
| CPU time | 43.29 seconds |
| Started | Jun 21 06:07:13 PM PDT 24 |
| Finished | Jun 21 06:07:57 PM PDT 24 |
| Peak memory | 192428 kb |
| Host | smart-e1f6ee08-d583-4808-8cfc-04a7d306e975 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400884790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1400884790 |
| Directory | /workspace/0.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/0.aon_timer_smoke.3150839792 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 579708516 ps |
| CPU time | 1.38 seconds |
| Started | Jun 21 06:07:06 PM PDT 24 |
| Finished | Jun 21 06:07:08 PM PDT 24 |
| Peak memory | 192316 kb |
| Host | smart-2d41bf7d-f9a1-4be7-ae0a-90c92728c702 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150839792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3150839792 |
| Directory | /workspace/0.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/1.aon_timer_prescaler.53542255 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 25517114839 ps |
| CPU time | 39.92 seconds |
| Started | Jun 21 06:07:17 PM PDT 24 |
| Finished | Jun 21 06:07:57 PM PDT 24 |
| Peak memory | 192448 kb |
| Host | smart-0dcfd5d5-f21f-4f2f-9d42-0cb98dcc2bf6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=53542255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.53542255 |
| Directory | /workspace/1.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/1.aon_timer_sec_cm.159253342 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7853730880 ps |
| CPU time | 6.22 seconds |
| Started | Jun 21 06:07:16 PM PDT 24 |
| Finished | Jun 21 06:07:23 PM PDT 24 |
| Peak memory | 216360 kb |
| Host | smart-3a1bdfb7-9215-42f4-8384-80fa076e9b30 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159253342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.159253342 |
| Directory | /workspace/1.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/1.aon_timer_smoke.1005298715 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 557449711 ps |
| CPU time | 0.62 seconds |
| Started | Jun 21 06:07:17 PM PDT 24 |
| Finished | Jun 21 06:07:18 PM PDT 24 |
| Peak memory | 192252 kb |
| Host | smart-b8e8ea5e-a616-472d-82a2-69b6eb5a9ac9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005298715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1005298715 |
| Directory | /workspace/1.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/10.aon_timer_prescaler.3196680039 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 4620359739 ps |
| CPU time | 2.93 seconds |
| Started | Jun 21 06:07:40 PM PDT 24 |
| Finished | Jun 21 06:07:43 PM PDT 24 |
| Peak memory | 192460 kb |
| Host | smart-a09137f6-3b72-44d0-9a00-822b96038962 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196680039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3196680039 |
| Directory | /workspace/10.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/10.aon_timer_smoke.1782867231 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 622220507 ps |
| CPU time | 0.76 seconds |
| Started | Jun 21 06:07:31 PM PDT 24 |
| Finished | Jun 21 06:07:33 PM PDT 24 |
| Peak memory | 192288 kb |
| Host | smart-f7222b9a-2d42-4e04-8508-a89ff01619af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782867231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1782867231 |
| Directory | /workspace/10.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/11.aon_timer_prescaler.1405287557 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 30396883499 ps |
| CPU time | 22.25 seconds |
| Started | Jun 21 06:07:40 PM PDT 24 |
| Finished | Jun 21 06:08:04 PM PDT 24 |
| Peak memory | 192436 kb |
| Host | smart-c1d70a50-c1d1-4e62-beef-fc09eb3a4768 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405287557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1405287557 |
| Directory | /workspace/11.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/11.aon_timer_smoke.1394350541 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 403316482 ps |
| CPU time | 0.92 seconds |
| Started | Jun 21 06:07:39 PM PDT 24 |
| Finished | Jun 21 06:07:41 PM PDT 24 |
| Peak memory | 192320 kb |
| Host | smart-758e5035-4d89-41ff-9493-22d16963d7cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394350541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1394350541 |
| Directory | /workspace/11.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/12.aon_timer_prescaler.3242429379 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 31234795725 ps |
| CPU time | 47.64 seconds |
| Started | Jun 21 06:07:42 PM PDT 24 |
| Finished | Jun 21 06:08:30 PM PDT 24 |
| Peak memory | 192368 kb |
| Host | smart-26bfb6be-7637-45c1-9917-e19ecc578141 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3242429379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3242429379 |
| Directory | /workspace/12.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/12.aon_timer_smoke.2019984654 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 589303899 ps |
| CPU time | 0.64 seconds |
| Started | Jun 21 06:07:39 PM PDT 24 |
| Finished | Jun 21 06:07:41 PM PDT 24 |
| Peak memory | 197092 kb |
| Host | smart-0867ca1a-6425-49eb-9130-c5e760e748d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2019984654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2019984654 |
| Directory | /workspace/12.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/13.aon_timer_prescaler.1175757705 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 51453908213 ps |
| CPU time | 75.42 seconds |
| Started | Jun 21 06:07:46 PM PDT 24 |
| Finished | Jun 21 06:09:02 PM PDT 24 |
| Peak memory | 192380 kb |
| Host | smart-b03a128b-47f7-4a84-a8c3-019d77b4bfe9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1175757705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1175757705 |
| Directory | /workspace/13.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/13.aon_timer_smoke.1160335010 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 390753749 ps |
| CPU time | 0.88 seconds |
| Started | Jun 21 06:07:47 PM PDT 24 |
| Finished | Jun 21 06:07:49 PM PDT 24 |
| Peak memory | 192292 kb |
| Host | smart-4d16facf-c775-4786-a2ab-5f1549c2056c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160335010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1160335010 |
| Directory | /workspace/13.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/13.aon_timer_stress_all.262245375 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 196592156976 ps |
| CPU time | 303.58 seconds |
| Started | Jun 21 06:07:48 PM PDT 24 |
| Finished | Jun 21 06:12:52 PM PDT 24 |
| Peak memory | 192424 kb |
| Host | smart-1d495a31-abe2-4769-ad89-b1925e3c257c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262245375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a ll.262245375 |
| Directory | /workspace/13.aon_timer_stress_all/latest |
| Test location | /workspace/coverage/default/14.aon_timer_prescaler.3710236252 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 61075039324 ps |
| CPU time | 20.63 seconds |
| Started | Jun 21 06:07:47 PM PDT 24 |
| Finished | Jun 21 06:08:08 PM PDT 24 |
| Peak memory | 192436 kb |
| Host | smart-459b24df-9a2c-43ba-90cc-359b4cbc8f15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710236252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3710236252 |
| Directory | /workspace/14.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/14.aon_timer_smoke.4041092224 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 380935219 ps |
| CPU time | 1.07 seconds |
| Started | Jun 21 06:07:56 PM PDT 24 |
| Finished | Jun 21 06:07:58 PM PDT 24 |
| Peak memory | 192236 kb |
| Host | smart-dd64ee3b-d1d2-4d5c-81a0-b7b828e265cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4041092224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.4041092224 |
| Directory | /workspace/14.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/15.aon_timer_prescaler.1786589834 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 6004333372 ps |
| CPU time | 2.58 seconds |
| Started | Jun 21 06:07:56 PM PDT 24 |
| Finished | Jun 21 06:08:00 PM PDT 24 |
| Peak memory | 192348 kb |
| Host | smart-665740c4-05be-4d39-a23b-c079889a21b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786589834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1786589834 |
| Directory | /workspace/15.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/15.aon_timer_smoke.1206371989 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 399368399 ps |
| CPU time | 0.9 seconds |
| Started | Jun 21 06:07:56 PM PDT 24 |
| Finished | Jun 21 06:07:58 PM PDT 24 |
| Peak memory | 197004 kb |
| Host | smart-10cfb764-0594-4ac2-9645-a0008cde1c8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206371989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1206371989 |
| Directory | /workspace/15.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/16.aon_timer_prescaler.2675644350 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9740854723 ps |
| CPU time | 10.37 seconds |
| Started | Jun 21 06:07:49 PM PDT 24 |
| Finished | Jun 21 06:08:00 PM PDT 24 |
| Peak memory | 192352 kb |
| Host | smart-a4825442-1c45-4d41-960f-fdaf2a1f6bee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2675644350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2675644350 |
| Directory | /workspace/16.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/16.aon_timer_smoke.3830624468 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 521520747 ps |
| CPU time | 0.97 seconds |
| Started | Jun 21 06:07:51 PM PDT 24 |
| Finished | Jun 21 06:07:52 PM PDT 24 |
| Peak memory | 197068 kb |
| Host | smart-fb2f1516-9b3e-40d1-9a3d-fb15f82bb652 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3830624468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3830624468 |
| Directory | /workspace/16.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.187205294 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1101780150 ps |
| CPU time | 2.1 seconds |
| Started | Jun 21 06:07:48 PM PDT 24 |
| Finished | Jun 21 06:07:50 PM PDT 24 |
| Peak memory | 214356 kb |
| Host | smart-62646659-4ea5-425b-9183-83f6f56c2747 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187205294 -assert nop ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.187205294 |
| Directory | /workspace/16.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.aon_timer_prescaler.2551515171 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 57875770625 ps |
| CPU time | 24.41 seconds |
| Started | Jun 21 06:07:55 PM PDT 24 |
| Finished | Jun 21 06:08:21 PM PDT 24 |
| Peak memory | 192440 kb |
| Host | smart-16379522-2320-47e0-a315-244d66236ccc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551515171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2551515171 |
| Directory | /workspace/17.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/17.aon_timer_smoke.553327182 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 420847422 ps |
| CPU time | 0.98 seconds |
| Started | Jun 21 06:07:58 PM PDT 24 |
| Finished | Jun 21 06:08:00 PM PDT 24 |
| Peak memory | 197008 kb |
| Host | smart-5774cabb-e708-4dae-baa9-ece637c603ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553327182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.553327182 |
| Directory | /workspace/17.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/18.aon_timer_prescaler.2335896212 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6953383931 ps |
| CPU time | 10.34 seconds |
| Started | Jun 21 06:07:55 PM PDT 24 |
| Finished | Jun 21 06:08:06 PM PDT 24 |
| Peak memory | 192440 kb |
| Host | smart-35451e67-4228-4cf2-a97c-f304aed333fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335896212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2335896212 |
| Directory | /workspace/18.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/18.aon_timer_smoke.3051738188 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 356611530 ps |
| CPU time | 1.07 seconds |
| Started | Jun 21 06:07:55 PM PDT 24 |
| Finished | Jun 21 06:07:56 PM PDT 24 |
| Peak memory | 192328 kb |
| Host | smart-db235627-4e95-4cf4-b548-1495489a5ce8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051738188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3051738188 |
| Directory | /workspace/18.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/19.aon_timer_prescaler.1390320949 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 56860498114 ps |
| CPU time | 43.07 seconds |
| Started | Jun 21 06:07:56 PM PDT 24 |
| Finished | Jun 21 06:08:40 PM PDT 24 |
| Peak memory | 192432 kb |
| Host | smart-6aff68a8-8854-481f-833c-53befd612cc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1390320949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1390320949 |
| Directory | /workspace/19.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/19.aon_timer_smoke.1828640585 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 407925413 ps |
| CPU time | 0.65 seconds |
| Started | Jun 21 06:07:55 PM PDT 24 |
| Finished | Jun 21 06:07:56 PM PDT 24 |
| Peak memory | 197176 kb |
| Host | smart-6436396d-0636-417f-a1f3-f258d4fd0ae1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1828640585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1828640585 |
| Directory | /workspace/19.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/2.aon_timer_prescaler.4176997451 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 18715367260 ps |
| CPU time | 13.77 seconds |
| Started | Jun 21 06:07:16 PM PDT 24 |
| Finished | Jun 21 06:07:30 PM PDT 24 |
| Peak memory | 192412 kb |
| Host | smart-3fb20faa-70f0-4a42-ba55-0fcaee0ae0b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4176997451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.4176997451 |
| Directory | /workspace/2.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/2.aon_timer_sec_cm.3961674772 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4000184965 ps |
| CPU time | 2.02 seconds |
| Started | Jun 21 06:07:15 PM PDT 24 |
| Finished | Jun 21 06:07:18 PM PDT 24 |
| Peak memory | 216160 kb |
| Host | smart-ee2b5525-a5c4-4166-a04e-158445097ca0 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961674772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3961674772 |
| Directory | /workspace/2.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/2.aon_timer_smoke.797128001 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 388418904 ps |
| CPU time | 0.87 seconds |
| Started | Jun 21 06:07:17 PM PDT 24 |
| Finished | Jun 21 06:07:18 PM PDT 24 |
| Peak memory | 197104 kb |
| Host | smart-13a81856-bded-4232-8662-428ebecdcb8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797128001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.797128001 |
| Directory | /workspace/2.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/20.aon_timer_prescaler.1962437003 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 57217114963 ps |
| CPU time | 19.99 seconds |
| Started | Jun 21 06:08:04 PM PDT 24 |
| Finished | Jun 21 06:08:24 PM PDT 24 |
| Peak memory | 192416 kb |
| Host | smart-1b292317-11a4-463b-8165-14a9bd94049d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1962437003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1962437003 |
| Directory | /workspace/20.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/20.aon_timer_smoke.3894135830 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 575224096 ps |
| CPU time | 1.45 seconds |
| Started | Jun 21 06:08:03 PM PDT 24 |
| Finished | Jun 21 06:08:06 PM PDT 24 |
| Peak memory | 192328 kb |
| Host | smart-e5fb5bbc-f5ce-4cea-bb55-22def8af4004 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3894135830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3894135830 |
| Directory | /workspace/20.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/21.aon_timer_prescaler.89592258 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 40267370079 ps |
| CPU time | 61.46 seconds |
| Started | Jun 21 06:08:04 PM PDT 24 |
| Finished | Jun 21 06:09:07 PM PDT 24 |
| Peak memory | 192444 kb |
| Host | smart-fd83fab7-5ed3-4905-ada4-933c08a27df5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89592258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.89592258 |
| Directory | /workspace/21.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/21.aon_timer_smoke.3699959905 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 463244053 ps |
| CPU time | 0.76 seconds |
| Started | Jun 21 06:08:05 PM PDT 24 |
| Finished | Jun 21 06:08:07 PM PDT 24 |
| Peak memory | 192320 kb |
| Host | smart-d0823ffc-be1d-4841-958e-942312629906 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699959905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3699959905 |
| Directory | /workspace/21.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/22.aon_timer_prescaler.1805812813 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 7496658304 ps |
| CPU time | 3.25 seconds |
| Started | Jun 21 06:08:05 PM PDT 24 |
| Finished | Jun 21 06:08:10 PM PDT 24 |
| Peak memory | 192392 kb |
| Host | smart-e58f79e4-02b1-4a72-8df1-2616eefee493 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805812813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1805812813 |
| Directory | /workspace/22.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/22.aon_timer_smoke.868078444 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 409535540 ps |
| CPU time | 0.91 seconds |
| Started | Jun 21 06:08:05 PM PDT 24 |
| Finished | Jun 21 06:08:07 PM PDT 24 |
| Peak memory | 197068 kb |
| Host | smart-5c9fdcaf-69c7-49fd-a088-549977e98673 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868078444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.868078444 |
| Directory | /workspace/22.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/23.aon_timer_prescaler.3753277152 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 44805459404 ps |
| CPU time | 30.54 seconds |
| Started | Jun 21 06:08:04 PM PDT 24 |
| Finished | Jun 21 06:08:36 PM PDT 24 |
| Peak memory | 192396 kb |
| Host | smart-68d9d7f3-11c1-45cc-a7cf-56730c89c81e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3753277152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3753277152 |
| Directory | /workspace/23.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/23.aon_timer_smoke.2126867007 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 520936513 ps |
| CPU time | 0.8 seconds |
| Started | Jun 21 06:08:03 PM PDT 24 |
| Finished | Jun 21 06:08:04 PM PDT 24 |
| Peak memory | 192420 kb |
| Host | smart-4455d9d3-3441-4d00-90b6-efb20f302a8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126867007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2126867007 |
| Directory | /workspace/23.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/24.aon_timer_prescaler.870232543 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 55844742934 ps |
| CPU time | 79.56 seconds |
| Started | Jun 21 06:08:06 PM PDT 24 |
| Finished | Jun 21 06:09:27 PM PDT 24 |
| Peak memory | 197352 kb |
| Host | smart-63ae3faf-adb5-42c9-9662-fc3251745620 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=870232543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.870232543 |
| Directory | /workspace/24.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/24.aon_timer_smoke.1727142124 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 521699474 ps |
| CPU time | 0.85 seconds |
| Started | Jun 21 06:08:05 PM PDT 24 |
| Finished | Jun 21 06:08:07 PM PDT 24 |
| Peak memory | 192324 kb |
| Host | smart-a070e238-1273-4152-a68d-bd447aadd50b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727142124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1727142124 |
| Directory | /workspace/24.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/25.aon_timer_prescaler.2957685015 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 23637100765 ps |
| CPU time | 16.65 seconds |
| Started | Jun 21 06:08:12 PM PDT 24 |
| Finished | Jun 21 06:08:29 PM PDT 24 |
| Peak memory | 192448 kb |
| Host | smart-1324b160-27d7-44d0-b560-bec13f74cdce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2957685015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2957685015 |
| Directory | /workspace/25.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/25.aon_timer_smoke.2727271506 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 400770364 ps |
| CPU time | 1.08 seconds |
| Started | Jun 21 06:08:14 PM PDT 24 |
| Finished | Jun 21 06:08:15 PM PDT 24 |
| Peak memory | 192292 kb |
| Host | smart-ff954819-c709-4bab-ac2b-823a90a28ef3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2727271506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2727271506 |
| Directory | /workspace/25.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/26.aon_timer_prescaler.3456621836 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 19157616548 ps |
| CPU time | 29.39 seconds |
| Started | Jun 21 06:08:15 PM PDT 24 |
| Finished | Jun 21 06:08:46 PM PDT 24 |
| Peak memory | 192448 kb |
| Host | smart-9f8b2895-05d0-44cc-8617-cf4dd38fb656 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456621836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3456621836 |
| Directory | /workspace/26.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/26.aon_timer_smoke.729165133 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 522879446 ps |
| CPU time | 1.32 seconds |
| Started | Jun 21 06:08:17 PM PDT 24 |
| Finished | Jun 21 06:08:18 PM PDT 24 |
| Peak memory | 192320 kb |
| Host | smart-19b2a26c-2abe-4db2-b088-b5443329d85c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729165133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.729165133 |
| Directory | /workspace/26.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/27.aon_timer_jump.3448342846 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 376883209 ps |
| CPU time | 1.17 seconds |
| Started | Jun 21 06:08:15 PM PDT 24 |
| Finished | Jun 21 06:08:16 PM PDT 24 |
| Peak memory | 197080 kb |
| Host | smart-ac90f82b-aad5-4b70-bd0f-7b1fab7e7d91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3448342846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3448342846 |
| Directory | /workspace/27.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/27.aon_timer_prescaler.31390778 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 33697009405 ps |
| CPU time | 44 seconds |
| Started | Jun 21 06:08:17 PM PDT 24 |
| Finished | Jun 21 06:09:01 PM PDT 24 |
| Peak memory | 197428 kb |
| Host | smart-2d5fda8e-4c47-4d12-9ad1-242e4933dfb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31390778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.31390778 |
| Directory | /workspace/27.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/27.aon_timer_smoke.2823784182 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 438812515 ps |
| CPU time | 1.27 seconds |
| Started | Jun 21 06:08:12 PM PDT 24 |
| Finished | Jun 21 06:08:14 PM PDT 24 |
| Peak memory | 192272 kb |
| Host | smart-bcd1e5b2-92ee-48fe-a462-4d2e0e96c911 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823784182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2823784182 |
| Directory | /workspace/27.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/28.aon_timer_prescaler.480598165 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 17549254305 ps |
| CPU time | 9.32 seconds |
| Started | Jun 21 06:08:17 PM PDT 24 |
| Finished | Jun 21 06:08:27 PM PDT 24 |
| Peak memory | 192436 kb |
| Host | smart-102c3a6f-45e7-4a2b-9961-531c0162b48b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480598165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.480598165 |
| Directory | /workspace/28.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/28.aon_timer_smoke.2356490391 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 584379714 ps |
| CPU time | 1.39 seconds |
| Started | Jun 21 06:08:12 PM PDT 24 |
| Finished | Jun 21 06:08:14 PM PDT 24 |
| Peak memory | 192328 kb |
| Host | smart-7a441271-052a-49a6-927c-7b7aae17df7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356490391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2356490391 |
| Directory | /workspace/28.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/29.aon_timer_prescaler.3156294915 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 40084802524 ps |
| CPU time | 55.69 seconds |
| Started | Jun 21 06:08:21 PM PDT 24 |
| Finished | Jun 21 06:09:18 PM PDT 24 |
| Peak memory | 192428 kb |
| Host | smart-9e783501-72f6-419b-b100-34b3a70d488f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3156294915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3156294915 |
| Directory | /workspace/29.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/29.aon_timer_smoke.790085288 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 466578176 ps |
| CPU time | 0.89 seconds |
| Started | Jun 21 06:08:23 PM PDT 24 |
| Finished | Jun 21 06:08:24 PM PDT 24 |
| Peak memory | 192316 kb |
| Host | smart-1cd1044c-50c2-4c89-8e00-2c4535356c2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=790085288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.790085288 |
| Directory | /workspace/29.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/3.aon_timer_prescaler.754701194 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 9414832265 ps |
| CPU time | 3.6 seconds |
| Started | Jun 21 06:07:31 PM PDT 24 |
| Finished | Jun 21 06:07:35 PM PDT 24 |
| Peak memory | 192440 kb |
| Host | smart-c09f1247-d98a-4d50-92a3-ea498991d92d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754701194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.754701194 |
| Directory | /workspace/3.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/3.aon_timer_sec_cm.2461963939 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11218229940 ps |
| CPU time | 3.3 seconds |
| Started | Jun 21 06:07:24 PM PDT 24 |
| Finished | Jun 21 06:07:29 PM PDT 24 |
| Peak memory | 216492 kb |
| Host | smart-48df0dfc-bf73-4339-943d-c41aa5dc15ad |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461963939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2461963939 |
| Directory | /workspace/3.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/3.aon_timer_smoke.3846658412 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 461684108 ps |
| CPU time | 0.7 seconds |
| Started | Jun 21 06:07:29 PM PDT 24 |
| Finished | Jun 21 06:07:30 PM PDT 24 |
| Peak memory | 192308 kb |
| Host | smart-d51c1d16-fa3e-4d27-a1e1-2134cf84d06b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846658412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3846658412 |
| Directory | /workspace/3.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/30.aon_timer_prescaler.1719822366 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 32413985826 ps |
| CPU time | 14.96 seconds |
| Started | Jun 21 06:08:23 PM PDT 24 |
| Finished | Jun 21 06:08:39 PM PDT 24 |
| Peak memory | 192400 kb |
| Host | smart-17ed1824-3a6f-4f1c-b456-0bcff2973123 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719822366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1719822366 |
| Directory | /workspace/30.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/30.aon_timer_smoke.789654612 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 510477683 ps |
| CPU time | 0.71 seconds |
| Started | Jun 21 06:08:21 PM PDT 24 |
| Finished | Jun 21 06:08:23 PM PDT 24 |
| Peak memory | 192312 kb |
| Host | smart-f1ed6e06-f2c4-4c01-9f30-eddb18ff152b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789654612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.789654612 |
| Directory | /workspace/30.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/31.aon_timer_prescaler.1555737792 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 36618601939 ps |
| CPU time | 26.94 seconds |
| Started | Jun 21 06:08:21 PM PDT 24 |
| Finished | Jun 21 06:08:48 PM PDT 24 |
| Peak memory | 192396 kb |
| Host | smart-785d633a-3d4e-4c1a-b17d-0f021b1230a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1555737792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1555737792 |
| Directory | /workspace/31.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/31.aon_timer_smoke.2857173716 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 400347354 ps |
| CPU time | 1.11 seconds |
| Started | Jun 21 06:08:20 PM PDT 24 |
| Finished | Jun 21 06:08:21 PM PDT 24 |
| Peak memory | 192304 kb |
| Host | smart-dc73f18e-907c-4edc-8345-3c9080780237 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2857173716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2857173716 |
| Directory | /workspace/31.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/32.aon_timer_prescaler.2166158013 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 26871386051 ps |
| CPU time | 36.15 seconds |
| Started | Jun 21 06:08:29 PM PDT 24 |
| Finished | Jun 21 06:09:05 PM PDT 24 |
| Peak memory | 192460 kb |
| Host | smart-3538393b-5603-4e60-adea-d68e927e9294 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2166158013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2166158013 |
| Directory | /workspace/32.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/32.aon_timer_smoke.2015661003 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 583731743 ps |
| CPU time | 1.07 seconds |
| Started | Jun 21 06:08:31 PM PDT 24 |
| Finished | Jun 21 06:08:32 PM PDT 24 |
| Peak memory | 192304 kb |
| Host | smart-0ce799a9-3a53-440a-93b1-abe50b8b29fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2015661003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2015661003 |
| Directory | /workspace/32.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/33.aon_timer_jump.3039213398 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 361386103 ps |
| CPU time | 0.85 seconds |
| Started | Jun 21 06:08:33 PM PDT 24 |
| Finished | Jun 21 06:08:35 PM PDT 24 |
| Peak memory | 196984 kb |
| Host | smart-e208ca72-3a44-47a3-92c9-9d625a04b85a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3039213398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3039213398 |
| Directory | /workspace/33.aon_timer_jump/latest |
| Test location | /workspace/coverage/default/33.aon_timer_prescaler.1232227948 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 35196687474 ps |
| CPU time | 14.34 seconds |
| Started | Jun 21 06:08:31 PM PDT 24 |
| Finished | Jun 21 06:08:46 PM PDT 24 |
| Peak memory | 192436 kb |
| Host | smart-6478d002-c84c-4037-9f4c-4424da941ee4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1232227948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1232227948 |
| Directory | /workspace/33.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/33.aon_timer_smoke.1016091467 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 576844300 ps |
| CPU time | 0.79 seconds |
| Started | Jun 21 06:08:33 PM PDT 24 |
| Finished | Jun 21 06:08:34 PM PDT 24 |
| Peak memory | 197144 kb |
| Host | smart-82ccca58-7f91-4dcf-9ce5-dfd116a674a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1016091467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1016091467 |
| Directory | /workspace/33.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/34.aon_timer_prescaler.1252423189 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 32016099980 ps |
| CPU time | 46.82 seconds |
| Started | Jun 21 06:08:30 PM PDT 24 |
| Finished | Jun 21 06:09:17 PM PDT 24 |
| Peak memory | 192436 kb |
| Host | smart-78053e39-471c-42cf-a218-bc217b91dd82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252423189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1252423189 |
| Directory | /workspace/34.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/34.aon_timer_smoke.328730533 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 490096823 ps |
| CPU time | 0.77 seconds |
| Started | Jun 21 06:08:32 PM PDT 24 |
| Finished | Jun 21 06:08:33 PM PDT 24 |
| Peak memory | 192332 kb |
| Host | smart-57ae34b9-37e3-4ead-bc57-55bdc20efd28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=328730533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.328730533 |
| Directory | /workspace/34.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/35.aon_timer_prescaler.3432839390 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 21630577606 ps |
| CPU time | 8.53 seconds |
| Started | Jun 21 06:08:41 PM PDT 24 |
| Finished | Jun 21 06:08:50 PM PDT 24 |
| Peak memory | 192352 kb |
| Host | smart-ad369c1e-f4e4-4017-a8b7-21af0f1956e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3432839390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3432839390 |
| Directory | /workspace/35.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/35.aon_timer_smoke.3069216413 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 399339646 ps |
| CPU time | 1.22 seconds |
| Started | Jun 21 06:08:33 PM PDT 24 |
| Finished | Jun 21 06:08:35 PM PDT 24 |
| Peak memory | 192420 kb |
| Host | smart-b9dc1a5c-e2b3-461d-8665-5845579c7599 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069216413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3069216413 |
| Directory | /workspace/35.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/36.aon_timer_prescaler.1263918324 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 22034183647 ps |
| CPU time | 32.7 seconds |
| Started | Jun 21 06:08:40 PM PDT 24 |
| Finished | Jun 21 06:09:13 PM PDT 24 |
| Peak memory | 192428 kb |
| Host | smart-850b6ad7-8865-40bf-a528-c1df7f282e9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1263918324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1263918324 |
| Directory | /workspace/36.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/36.aon_timer_smoke.3811535447 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 505982094 ps |
| CPU time | 0.66 seconds |
| Started | Jun 21 06:08:39 PM PDT 24 |
| Finished | Jun 21 06:08:40 PM PDT 24 |
| Peak memory | 192328 kb |
| Host | smart-8fd21516-0cf2-4d49-b6cc-7af7d2001326 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3811535447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3811535447 |
| Directory | /workspace/36.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/37.aon_timer_prescaler.2908677482 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 58281596910 ps |
| CPU time | 23.31 seconds |
| Started | Jun 21 06:08:43 PM PDT 24 |
| Finished | Jun 21 06:09:07 PM PDT 24 |
| Peak memory | 192532 kb |
| Host | smart-6bb19332-f379-47dc-ab64-cb2f4a63b08f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908677482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2908677482 |
| Directory | /workspace/37.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/37.aon_timer_smoke.411002920 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 437381061 ps |
| CPU time | 1.33 seconds |
| Started | Jun 21 06:08:39 PM PDT 24 |
| Finished | Jun 21 06:08:41 PM PDT 24 |
| Peak memory | 197072 kb |
| Host | smart-72890fc6-7905-44f3-91f9-1b38c5caadd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411002920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.411002920 |
| Directory | /workspace/37.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/38.aon_timer_prescaler.3580374003 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 3093650991 ps |
| CPU time | 2.82 seconds |
| Started | Jun 21 06:08:39 PM PDT 24 |
| Finished | Jun 21 06:08:42 PM PDT 24 |
| Peak memory | 192432 kb |
| Host | smart-3d2f1fa3-0255-464b-81dc-bbbbd71a70dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580374003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3580374003 |
| Directory | /workspace/38.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/38.aon_timer_smoke.3639492215 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 462402434 ps |
| CPU time | 1.26 seconds |
| Started | Jun 21 06:08:39 PM PDT 24 |
| Finished | Jun 21 06:08:41 PM PDT 24 |
| Peak memory | 197092 kb |
| Host | smart-3dc153f6-99ce-46ae-8dd1-6691f6a6fa58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3639492215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3639492215 |
| Directory | /workspace/38.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/39.aon_timer_prescaler.370410796 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 60048986220 ps |
| CPU time | 23.56 seconds |
| Started | Jun 21 06:08:43 PM PDT 24 |
| Finished | Jun 21 06:09:07 PM PDT 24 |
| Peak memory | 192448 kb |
| Host | smart-1281c6f0-4988-4955-978f-b1e848935468 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=370410796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.370410796 |
| Directory | /workspace/39.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/39.aon_timer_smoke.4003923131 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 400785953 ps |
| CPU time | 0.73 seconds |
| Started | Jun 21 06:08:44 PM PDT 24 |
| Finished | Jun 21 06:08:45 PM PDT 24 |
| Peak memory | 192420 kb |
| Host | smart-a415c952-405b-45b5-b3ed-2283b12f5c9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003923131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.4003923131 |
| Directory | /workspace/39.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/4.aon_timer_prescaler.4007287298 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 39311999009 ps |
| CPU time | 58.02 seconds |
| Started | Jun 21 06:07:31 PM PDT 24 |
| Finished | Jun 21 06:08:30 PM PDT 24 |
| Peak memory | 192432 kb |
| Host | smart-fec181c9-8e85-4f1f-b8c6-606e6243a7c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4007287298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.4007287298 |
| Directory | /workspace/4.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/4.aon_timer_sec_cm.3844524244 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3972837174 ps |
| CPU time | 2.06 seconds |
| Started | Jun 21 06:07:30 PM PDT 24 |
| Finished | Jun 21 06:07:32 PM PDT 24 |
| Peak memory | 216024 kb |
| Host | smart-12593157-5934-4989-992a-320ac34552ec |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844524244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3844524244 |
| Directory | /workspace/4.aon_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/4.aon_timer_smoke.1564531055 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 446140896 ps |
| CPU time | 0.73 seconds |
| Started | Jun 21 06:07:24 PM PDT 24 |
| Finished | Jun 21 06:07:25 PM PDT 24 |
| Peak memory | 192424 kb |
| Host | smart-472d1463-38df-4bf1-9061-20557726512d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564531055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1564531055 |
| Directory | /workspace/4.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/40.aon_timer_prescaler.2452477533 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 44159317774 ps |
| CPU time | 29.93 seconds |
| Started | Jun 21 06:08:54 PM PDT 24 |
| Finished | Jun 21 06:09:24 PM PDT 24 |
| Peak memory | 192408 kb |
| Host | smart-ee36ad66-84a9-4b2f-96d8-3a1948da4139 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452477533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2452477533 |
| Directory | /workspace/40.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/40.aon_timer_smoke.2447251258 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 491755204 ps |
| CPU time | 0.65 seconds |
| Started | Jun 21 06:08:47 PM PDT 24 |
| Finished | Jun 21 06:08:48 PM PDT 24 |
| Peak memory | 192328 kb |
| Host | smart-4cf64b4b-3f7d-4cc3-a51d-bbf2f6f9f860 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447251258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2447251258 |
| Directory | /workspace/40.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/41.aon_timer_prescaler.691638991 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5651376445 ps |
| CPU time | 2.45 seconds |
| Started | Jun 21 06:08:49 PM PDT 24 |
| Finished | Jun 21 06:08:52 PM PDT 24 |
| Peak memory | 192408 kb |
| Host | smart-76c28119-7d0a-449d-af0d-f07290690bbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691638991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.691638991 |
| Directory | /workspace/41.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/41.aon_timer_smoke.4091185152 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 501424469 ps |
| CPU time | 0.62 seconds |
| Started | Jun 21 06:08:54 PM PDT 24 |
| Finished | Jun 21 06:08:55 PM PDT 24 |
| Peak memory | 192328 kb |
| Host | smart-3b0d2c8a-a1d2-479a-9a62-52dff1de2f48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091185152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.4091185152 |
| Directory | /workspace/41.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/42.aon_timer_prescaler.992451701 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 8093988200 ps |
| CPU time | 6.6 seconds |
| Started | Jun 21 06:08:49 PM PDT 24 |
| Finished | Jun 21 06:08:56 PM PDT 24 |
| Peak memory | 192428 kb |
| Host | smart-b7e2b2ca-bca8-4ee1-bb7c-931c7a7ee466 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=992451701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.992451701 |
| Directory | /workspace/42.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/42.aon_timer_smoke.2309430507 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 410769249 ps |
| CPU time | 0.69 seconds |
| Started | Jun 21 06:08:51 PM PDT 24 |
| Finished | Jun 21 06:08:52 PM PDT 24 |
| Peak memory | 192284 kb |
| Host | smart-16ebe65e-9480-49fd-9d2d-b02540c54ba0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2309430507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2309430507 |
| Directory | /workspace/42.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/43.aon_timer_prescaler.2334907064 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 36995988659 ps |
| CPU time | 28.45 seconds |
| Started | Jun 21 06:08:50 PM PDT 24 |
| Finished | Jun 21 06:09:20 PM PDT 24 |
| Peak memory | 192392 kb |
| Host | smart-fb2fdf65-13cc-4411-b901-aaeb47492c92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334907064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2334907064 |
| Directory | /workspace/43.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/43.aon_timer_smoke.658130184 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 408952536 ps |
| CPU time | 1.18 seconds |
| Started | Jun 21 06:08:47 PM PDT 24 |
| Finished | Jun 21 06:08:49 PM PDT 24 |
| Peak memory | 192252 kb |
| Host | smart-293cc675-1fa3-4629-bcf1-591748a6e4aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=658130184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.658130184 |
| Directory | /workspace/43.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/44.aon_timer_prescaler.1514516161 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 31966792474 ps |
| CPU time | 7.32 seconds |
| Started | Jun 21 06:08:58 PM PDT 24 |
| Finished | Jun 21 06:09:06 PM PDT 24 |
| Peak memory | 192432 kb |
| Host | smart-4c8926c5-0991-44d4-a84c-bcd0261e65a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514516161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1514516161 |
| Directory | /workspace/44.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/44.aon_timer_smoke.1968641482 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 488068215 ps |
| CPU time | 1.21 seconds |
| Started | Jun 21 06:08:55 PM PDT 24 |
| Finished | Jun 21 06:08:57 PM PDT 24 |
| Peak memory | 192268 kb |
| Host | smart-f040a499-bb02-4241-a3cd-8ca1210beb5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968641482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1968641482 |
| Directory | /workspace/44.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/45.aon_timer_prescaler.1623152728 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 991770239 ps |
| CPU time | 2.05 seconds |
| Started | Jun 21 06:08:58 PM PDT 24 |
| Finished | Jun 21 06:09:01 PM PDT 24 |
| Peak memory | 192332 kb |
| Host | smart-46b0de27-237e-4405-a31f-6fb8a085302a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623152728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1623152728 |
| Directory | /workspace/45.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/45.aon_timer_smoke.3583494682 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 396076229 ps |
| CPU time | 0.84 seconds |
| Started | Jun 21 06:08:57 PM PDT 24 |
| Finished | Jun 21 06:08:58 PM PDT 24 |
| Peak memory | 192324 kb |
| Host | smart-1c4f16f8-249d-41b9-b388-c85d92b96a3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583494682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3583494682 |
| Directory | /workspace/45.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/46.aon_timer_prescaler.4028779492 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 17820916323 ps |
| CPU time | 12.86 seconds |
| Started | Jun 21 06:08:56 PM PDT 24 |
| Finished | Jun 21 06:09:10 PM PDT 24 |
| Peak memory | 192436 kb |
| Host | smart-c289ab13-901a-4210-aa94-08c8210ea18f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028779492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.4028779492 |
| Directory | /workspace/46.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/46.aon_timer_smoke.2546732289 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 483997693 ps |
| CPU time | 1.24 seconds |
| Started | Jun 21 06:08:55 PM PDT 24 |
| Finished | Jun 21 06:08:57 PM PDT 24 |
| Peak memory | 192328 kb |
| Host | smart-692c44e4-2815-4afd-9288-069951ca728d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2546732289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2546732289 |
| Directory | /workspace/46.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/47.aon_timer_prescaler.737088078 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 37617009678 ps |
| CPU time | 22.75 seconds |
| Started | Jun 21 06:09:04 PM PDT 24 |
| Finished | Jun 21 06:09:28 PM PDT 24 |
| Peak memory | 192412 kb |
| Host | smart-fb4a9d46-befc-4d20-8aca-a1db695a2fbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=737088078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.737088078 |
| Directory | /workspace/47.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/47.aon_timer_smoke.3688342550 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 332344908 ps |
| CPU time | 0.82 seconds |
| Started | Jun 21 06:08:55 PM PDT 24 |
| Finished | Jun 21 06:08:56 PM PDT 24 |
| Peak memory | 192320 kb |
| Host | smart-21fe8cc6-a5e9-4d16-8122-0b4f25045148 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3688342550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3688342550 |
| Directory | /workspace/47.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/48.aon_timer_prescaler.1808865279 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 8775772830 ps |
| CPU time | 3.49 seconds |
| Started | Jun 21 06:09:04 PM PDT 24 |
| Finished | Jun 21 06:09:08 PM PDT 24 |
| Peak memory | 192432 kb |
| Host | smart-c511714c-85bf-47d6-9110-a1f619510baf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1808865279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1808865279 |
| Directory | /workspace/48.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/48.aon_timer_smoke.502321084 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 351266140 ps |
| CPU time | 0.71 seconds |
| Started | Jun 21 06:09:05 PM PDT 24 |
| Finished | Jun 21 06:09:06 PM PDT 24 |
| Peak memory | 192312 kb |
| Host | smart-81769c6e-a962-4f16-8071-e5ef15e25854 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502321084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.502321084 |
| Directory | /workspace/48.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/49.aon_timer_prescaler.1753909396 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 34630695264 ps |
| CPU time | 43.57 seconds |
| Started | Jun 21 06:09:03 PM PDT 24 |
| Finished | Jun 21 06:09:47 PM PDT 24 |
| Peak memory | 192436 kb |
| Host | smart-9a8aa60c-25ab-4a0e-9341-dbdebd6c6d97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753909396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1753909396 |
| Directory | /workspace/49.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/49.aon_timer_smoke.4001198413 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 603261906 ps |
| CPU time | 0.8 seconds |
| Started | Jun 21 06:09:05 PM PDT 24 |
| Finished | Jun 21 06:09:07 PM PDT 24 |
| Peak memory | 197108 kb |
| Host | smart-1ef9ea31-b826-45e4-945d-2306233a5d04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4001198413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4001198413 |
| Directory | /workspace/49.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/5.aon_timer_prescaler.3724149327 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 25567600504 ps |
| CPU time | 32.93 seconds |
| Started | Jun 21 06:07:23 PM PDT 24 |
| Finished | Jun 21 06:07:58 PM PDT 24 |
| Peak memory | 192424 kb |
| Host | smart-58f0fa03-5096-4cca-b1ff-a64122574ee7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724149327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3724149327 |
| Directory | /workspace/5.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/5.aon_timer_smoke.347132379 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 433337261 ps |
| CPU time | 0.79 seconds |
| Started | Jun 21 06:07:23 PM PDT 24 |
| Finished | Jun 21 06:07:25 PM PDT 24 |
| Peak memory | 197048 kb |
| Host | smart-9cac0849-8721-49e8-bd4b-d809ea698acd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=347132379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.347132379 |
| Directory | /workspace/5.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/6.aon_timer_prescaler.782258414 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 51485953971 ps |
| CPU time | 68.02 seconds |
| Started | Jun 21 06:07:23 PM PDT 24 |
| Finished | Jun 21 06:08:32 PM PDT 24 |
| Peak memory | 192420 kb |
| Host | smart-b988aded-5ed3-423a-acca-32875d7faeec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782258414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.782258414 |
| Directory | /workspace/6.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/6.aon_timer_smoke.3510108166 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 437219481 ps |
| CPU time | 1.2 seconds |
| Started | Jun 21 06:07:25 PM PDT 24 |
| Finished | Jun 21 06:07:27 PM PDT 24 |
| Peak memory | 192348 kb |
| Host | smart-34076b56-691f-40df-ba52-55e732b4c4d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3510108166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3510108166 |
| Directory | /workspace/6.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/7.aon_timer_prescaler.3891853047 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 59316178174 ps |
| CPU time | 82.28 seconds |
| Started | Jun 21 06:07:29 PM PDT 24 |
| Finished | Jun 21 06:08:52 PM PDT 24 |
| Peak memory | 192436 kb |
| Host | smart-64800c8e-28d8-4ae8-b69e-562555547fa1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891853047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3891853047 |
| Directory | /workspace/7.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/7.aon_timer_smoke.719567427 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 355533607 ps |
| CPU time | 1.16 seconds |
| Started | Jun 21 06:07:26 PM PDT 24 |
| Finished | Jun 21 06:07:27 PM PDT 24 |
| Peak memory | 192300 kb |
| Host | smart-5485b135-e101-4823-aeb0-16f182511454 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=719567427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.719567427 |
| Directory | /workspace/7.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/8.aon_timer_prescaler.1318327809 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 35671132313 ps |
| CPU time | 12.67 seconds |
| Started | Jun 21 06:07:32 PM PDT 24 |
| Finished | Jun 21 06:07:45 PM PDT 24 |
| Peak memory | 192408 kb |
| Host | smart-0494c75c-6aa4-4d65-b5ac-a7c92c0dc5d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1318327809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1318327809 |
| Directory | /workspace/8.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/8.aon_timer_smoke.2527429778 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 594409741 ps |
| CPU time | 1.04 seconds |
| Started | Jun 21 06:07:31 PM PDT 24 |
| Finished | Jun 21 06:07:33 PM PDT 24 |
| Peak memory | 197108 kb |
| Host | smart-4f17ca7a-6fd4-40fb-bf23-40256e566a86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527429778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2527429778 |
| Directory | /workspace/8.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/9.aon_timer_prescaler.1136447690 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 23273914960 ps |
| CPU time | 9.18 seconds |
| Started | Jun 21 06:07:29 PM PDT 24 |
| Finished | Jun 21 06:07:39 PM PDT 24 |
| Peak memory | 192436 kb |
| Host | smart-698b065e-e2ff-4e4f-96e7-5988423f7ea6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136447690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1136447690 |
| Directory | /workspace/9.aon_timer_prescaler/latest |
| Test location | /workspace/coverage/default/9.aon_timer_smoke.2836088664 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 566850811 ps |
| CPU time | 0.62 seconds |
| Started | Jun 21 06:07:30 PM PDT 24 |
| Finished | Jun 21 06:07:32 PM PDT 24 |
| Peak memory | 192304 kb |
| Host | smart-c31d09f5-95f2-4ce6-b5b7-7b89fe38ffff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836088664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2836088664 |
| Directory | /workspace/9.aon_timer_smoke/latest |
| Test location | /workspace/coverage/default/9.aon_timer_stress_all.2135009165 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 195988522620 ps |
| CPU time | 174.86 seconds |
| Started | Jun 21 06:07:31 PM PDT 24 |
| Finished | Jun 21 06:10:27 PM PDT 24 |
| Peak memory | 198752 kb |
| Host | smart-d4bb3706-d66e-42bd-8587-950e594e7757 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135009165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a ll.2135009165 |
| Directory | /workspace/9.aon_timer_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |