Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	30333	1		T1	11		T2	12		T3	503
bark[1]	310	1		T47	30		T64	21		T89	96
bark[2]	345	1		T19	40		T44	119		T82	14
bark[3]	674	1		T10	21		T18	49		T51	14
bark[4]	229	1		T47	47		T101	21		T111	30
bark[5]	519	1		T32	14		T46	7		T115	21
bark[6]	673	1		T34	47		T83	35		T64	21
bark[7]	187	1		T185	35		T22	62		T90	25
bark[8]	213	1		T6	21		T10	14		T33	21
bark[9]	644	1		T5	61		T11	14		T47	52
bark[10]	180	1		T14	14		T96	21		T56	14
bark[11]	1946	1		T33	1028		T169	68		T125	14
bark[12]	510	1		T6	21		T159	14		T106	21
bark[13]	583	1		T5	107		T53	14		T34	30
bark[14]	471	1		T10	21		T97	138		T152	21
bark[15]	252	1		T169	30		T100	30		T135	14
bark[16]	525	1		T12	14		T167	14		T82	94
bark[17]	232	1		T10	21		T113	14		T139	14
bark[18]	562	1		T121	40		T45	95		T86	185
bark[19]	527	1		T145	14		T189	14		T100	119
bark[20]	237	1		T94	21		T57	58		T188	14
bark[21]	174	1		T45	26		T149	14		T57	19
bark[22]	215	1		T10	21		T84	14		T95	21
bark[23]	770	1		T153	14		T164	76		T112	35
bark[24]	279	1		T19	21		T121	21		T46	21
bark[25]	159	1		T19	21		T127	21		T116	21
bark[26]	293	1		T121	30		T157	14		T55	21
bark[27]	308	1		T119	21		T164	21		T30	21
bark[28]	1340	1		T34	311		T45	224		T101	21
bark[29]	565	1		T3	21		T101	7		T57	21
bark[30]	135	1		T10	21		T101	5		T30	21
bark[31]	491	1		T115	21		T95	196		T96	21
bark_0	4407	1		T1	7		T2	7		T3	44

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	30085	1		T1	10		T2	11		T3	498
bite[1]	441	1		T10	21		T121	21		T169	67
bite[2]	317	1		T10	21		T46	21		T47	136
bite[3]	1174	1		T121	21		T45	94		T86	177
bite[4]	193	1		T53	13		T96	21		T55	46
bite[5]	195	1		T45	25		T58	13		T64	21
bite[6]	719	1		T10	21		T94	21		T97	123
bite[7]	181	1		T19	21		T119	21		T127	21
bite[8]	596	1		T121	30		T169	30		T152	21
bite[9]	557	1		T11	13		T34	310		T47	30
bite[10]	490	1		T6	21		T184	13		T95	21
bite[11]	399	1		T34	46		T82	73		T106	21
bite[12]	373	1		T46	6		T127	21		T150	21
bite[13]	240	1		T101	6		T97	6		T131	21
bite[14]	654	1		T100	30		T174	13		T101	21
bite[15]	189	1		T10	13		T121	40		T125	13
bite[16]	162	1		T97	21		T129	13		T105	51
bite[17]	1450	1		T33	1027		T95	21		T138	13
bite[18]	153	1		T12	13		T115	21		T105	21
bite[19]	794	1		T3	21		T10	21		T14	13
bite[20]	312	1		T5	60		T10	35		T19	21
bite[21]	223	1		T9	13		T82	21		T185	35
bite[22]	188	1		T34	30		T189	13		T82	13
bite[23]	498	1		T19	40		T44	268		T167	13
bite[24]	502	1		T5	106		T100	97		T106	21
bite[25]	442	1		T83	35		T115	21		T112	35
bite[26]	373	1		T6	21		T32	13		T33	21
bite[27]	714	1		T159	13		T47	12		T106	118
bite[28]	581	1		T45	223		T47	51		T106	21
bite[29]	240	1		T86	87		T153	13		T177	13
bite[30]	682	1		T46	25		T134	42		T168	13
bite[31]	285	1		T51	13		T145	13		T89	21
bite_0	4886	1		T1	8		T2	8		T3	49

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	49288	1		T1	18		T2	19		T3	568

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	575	1		T4	9		T5	19		T33	19
prescale[1]	931	1		T6	42		T18	54		T83	19
prescale[2]	1273	1		T10	19		T33	64		T19	40
prescale[3]	1285	1		T6	67		T34	127		T169	49
prescale[4]	598	1		T5	2		T34	19		T45	2
prescale[5]	884	1		T10	41		T13	33		T18	42
prescale[6]	533	1		T3	2		T33	2		T45	29
prescale[7]	756	1		T33	58		T47	20		T196	9
prescale[8]	939	1		T18	28		T82	23		T47	2
prescale[9]	894	1		T3	114		T10	41		T13	185
prescale[10]	897	1		T13	19		T18	19		T48	9
prescale[11]	1133	1		T33	66		T119	19		T115	23
prescale[12]	565	1		T13	2		T33	45		T45	19
prescale[13]	1038	1		T13	117		T45	116		T83	24
prescale[14]	825	1		T2	9		T33	86		T94	118
prescale[15]	764	1		T10	23		T34	125		T44	46
prescale[16]	1114	1		T33	60		T82	19		T83	41
prescale[17]	858	1		T13	88		T34	39		T169	14
prescale[18]	583	1		T3	24		T5	2		T45	40
prescale[19]	1161	1		T5	19		T13	19		T18	19
prescale[20]	672	1		T119	19		T95	70		T96	37
prescale[21]	506	1		T13	58		T45	50		T46	2
prescale[22]	766	1		T6	2		T13	2		T106	19
prescale[23]	314	1		T50	9		T44	2		T45	2
prescale[24]	804	1		T33	220		T34	153		T197	9
prescale[25]	744	1		T6	21		T49	9		T33	96
prescale[26]	605	1		T3	4		T6	37		T33	40
prescale[27]	436	1		T6	37		T198	9		T85	9
prescale[28]	370	1		T6	2		T119	29		T100	47
prescale[29]	655	1		T3	123		T18	28		T44	2
prescale[30]	762	1		T19	59		T169	28		T45	38
prescale[31]	823	1		T5	2		T6	2		T19	28
prescale_0	24225	1		T1	18		T2	10		T3	301

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	36423	1		T1	18		T2	19		T3	520
auto[1]	12865	1		T3	48		T4	10		T5	39

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	49288	1		T1	18		T2	19		T3	568

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	29230	1		T1	13		T2	14		T3	315
wkup[1]	169	1		T44	26		T94	21		T95	21
wkup[2]	265	1		T3	42		T34	21		T101	26
wkup[3]	89	1		T5	21		T28	26		T136	42
wkup[4]	261	1		T10	21		T33	21		T34	15
wkup[5]	149	1		T95	21		T96	21		T112	15
wkup[6]	180	1		T150	21		T28	8		T105	21
wkup[7]	203	1		T33	21		T44	21		T159	15
wkup[8]	288	1		T10	36		T133	21		T89	21
wkup[9]	274	1		T10	21		T47	21		T119	21
wkup[10]	165	1		T45	21		T157	15		T127	21
wkup[11]	397	1		T33	21		T34	21		T169	21
wkup[12]	256	1		T3	21		T10	35		T34	21
wkup[13]	234	1		T3	21		T46	8		T86	8
wkup[14]	275	1		T3	21		T44	45		T45	21
wkup[15]	341	1		T6	21		T9	15		T11	15
wkup[16]	286	1		T3	21		T33	21		T47	30
wkup[17]	157	1		T10	21		T33	26		T97	21
wkup[18]	315	1		T6	15		T18	15		T33	21
wkup[19]	338	1		T34	21		T189	15		T169	21
wkup[20]	198	1		T12	15		T46	21		T106	21
wkup[21]	256	1		T100	21		T95	21		T127	21
wkup[22]	284	1		T94	42		T100	30		T95	21
wkup[23]	244	1		T32	15		T33	35		T96	21
wkup[24]	172	1		T95	21		T55	31		T64	21
wkup[25]	296	1		T34	26		T169	21		T122	15
wkup[26]	168	1		T94	21		T100	42		T133	21
wkup[27]	221	1		T115	21		T135	15		T28	30
wkup[28]	449	1		T167	15		T86	21		T119	21
wkup[29]	217	1		T95	21		T183	20		T131	21
wkup[30]	292	1		T82	21		T84	15		T55	56
wkup[31]	348	1		T44	30		T45	42		T100	26
wkup[32]	261	1		T94	21		T100	21		T164	21
wkup[33]	224	1		T33	51		T44	21		T169	30
wkup[34]	300	1		T5	15		T82	26		T55	42
wkup[35]	250	1		T169	30		T45	8		T94	21
wkup[36]	308	1		T33	47		T47	6		T94	21
wkup[37]	231	1		T6	21		T33	47		T94	21
wkup[38]	376	1		T3	21		T33	42		T34	21
wkup[39]	306	1		T19	21		T86	51		T149	15
wkup[40]	306	1		T5	39		T82	15		T83	35
wkup[41]	203	1		T5	21		T14	15		T19	21
wkup[42]	196	1		T86	30		T94	21		T89	26
wkup[43]	213	1		T45	21		T101	6		T55	21
wkup[44]	330	1		T3	42		T13	21		T34	21
wkup[45]	198	1		T5	26		T86	21		T89	21
wkup[46]	320	1		T19	21		T53	15		T95	30
wkup[47]	331	1		T6	21		T51	15		T34	21
wkup[48]	376	1		T33	26		T34	30		T94	42
wkup[49]	369	1		T3	30		T13	30		T44	21
wkup[50]	225	1		T6	21		T13	21		T44	26
wkup[51]	195	1		T33	21		T125	15		T100	42
wkup[52]	173	1		T121	21		T82	21		T115	21
wkup[53]	265	1		T47	34		T94	21		T100	42
wkup[54]	259	1		T6	21		T45	30		T100	8
wkup[55]	411	1		T33	21		T47	21		T86	47
wkup[56]	219	1		T18	21		T100	21		T56	15
wkup[57]	380	1		T18	35		T33	21		T34	56
wkup[58]	251	1		T13	21		T34	8		T169	21
wkup[59]	313	1		T19	21		T46	44		T100	21
wkup[60]	278	1		T10	21		T13	44		T33	21
wkup[61]	285	1		T6	30		T13	21		T45	21
wkup[62]	294	1		T5	6		T13	21		T115	21
wkup[63]	201	1		T33	26		T121	30		T82	26
wkup_0	3424	1		T1	5		T2	5		T3	34