Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.08 99.33 93.67 100.00 98.40 99.51 49.57


Total test records in report: 420
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T281 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1607744870 Jun 22 04:43:09 PM PDT 24 Jun 22 04:43:11 PM PDT 24 369194518 ps
T41 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1322559764 Jun 22 04:43:36 PM PDT 24 Jun 22 04:43:38 PM PDT 24 453428056 ps
T35 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3188259007 Jun 22 04:43:21 PM PDT 24 Jun 22 04:43:25 PM PDT 24 2218828994 ps
T36 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1742276929 Jun 22 04:43:37 PM PDT 24 Jun 22 04:43:40 PM PDT 24 4258448106 ps
T282 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3354411290 Jun 22 04:43:36 PM PDT 24 Jun 22 04:43:38 PM PDT 24 416275214 ps
T37 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3962000166 Jun 22 04:42:38 PM PDT 24 Jun 22 04:42:39 PM PDT 24 591040237 ps
T283 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3474806805 Jun 22 04:43:53 PM PDT 24 Jun 22 04:43:54 PM PDT 24 489242435 ps
T284 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3061167905 Jun 22 04:42:30 PM PDT 24 Jun 22 04:42:34 PM PDT 24 444103148 ps
T38 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3879356533 Jun 22 04:42:39 PM PDT 24 Jun 22 04:42:42 PM PDT 24 3748632081 ps
T285 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.71174413 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:31 PM PDT 24 286816294 ps
T199 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2566902115 Jun 22 04:43:21 PM PDT 24 Jun 22 04:43:22 PM PDT 24 317643133 ps
T286 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.723193581 Jun 22 04:43:20 PM PDT 24 Jun 22 04:43:21 PM PDT 24 416915296 ps
T287 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3020923450 Jun 22 04:43:43 PM PDT 24 Jun 22 04:43:44 PM PDT 24 334762856 ps
T39 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.956271197 Jun 22 04:43:37 PM PDT 24 Jun 22 04:43:49 PM PDT 24 8097604911 ps
T288 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4042501562 Jun 22 04:43:07 PM PDT 24 Jun 22 04:43:09 PM PDT 24 505224079 ps
T289 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2536905533 Jun 22 04:43:43 PM PDT 24 Jun 22 04:43:45 PM PDT 24 369376714 ps
T194 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1395394078 Jun 22 04:43:02 PM PDT 24 Jun 22 04:43:05 PM PDT 24 4408516301 ps
T290 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.750932594 Jun 22 04:43:20 PM PDT 24 Jun 22 04:43:22 PM PDT 24 285859049 ps
T291 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2676266543 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:31 PM PDT 24 387129136 ps
T292 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2518007934 Jun 22 04:42:59 PM PDT 24 Jun 22 04:43:01 PM PDT 24 498716244 ps
T190 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3667564077 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:43 PM PDT 24 8470855375 ps
T293 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3627869546 Jun 22 04:43:14 PM PDT 24 Jun 22 04:43:28 PM PDT 24 8416606676 ps
T294 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1114439071 Jun 22 04:43:31 PM PDT 24 Jun 22 04:43:32 PM PDT 24 346548714 ps
T75 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1850866000 Jun 22 04:43:23 PM PDT 24 Jun 22 04:43:27 PM PDT 24 2365309342 ps
T295 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1253152298 Jun 22 04:43:55 PM PDT 24 Jun 22 04:43:56 PM PDT 24 510084816 ps
T296 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3723847786 Jun 22 04:43:07 PM PDT 24 Jun 22 04:43:24 PM PDT 24 13631662897 ps
T76 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.352403809 Jun 22 04:43:01 PM PDT 24 Jun 22 04:43:04 PM PDT 24 2750332657 ps
T77 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.525173389 Jun 22 04:43:26 PM PDT 24 Jun 22 04:43:27 PM PDT 24 2371976127 ps
T297 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.793334712 Jun 22 04:42:53 PM PDT 24 Jun 22 04:42:56 PM PDT 24 936323656 ps
T78 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.265066527 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:37 PM PDT 24 2596520013 ps
T298 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3818042155 Jun 22 04:43:38 PM PDT 24 Jun 22 04:43:41 PM PDT 24 468380042 ps
T299 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3530436817 Jun 22 04:43:36 PM PDT 24 Jun 22 04:43:38 PM PDT 24 748228078 ps
T300 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2317398656 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:31 PM PDT 24 556640480 ps
T301 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2973811455 Jun 22 04:43:49 PM PDT 24 Jun 22 04:43:50 PM PDT 24 336023217 ps
T195 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2569747046 Jun 22 04:43:30 PM PDT 24 Jun 22 04:43:44 PM PDT 24 8191033276 ps
T302 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3028675710 Jun 22 04:43:23 PM PDT 24 Jun 22 04:43:25 PM PDT 24 4617952784 ps
T303 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2042591491 Jun 22 04:43:00 PM PDT 24 Jun 22 04:43:02 PM PDT 24 882336073 ps
T304 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2199324038 Jun 22 04:43:44 PM PDT 24 Jun 22 04:43:46 PM PDT 24 360144153 ps
T305 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2602265390 Jun 22 04:43:43 PM PDT 24 Jun 22 04:43:46 PM PDT 24 362537519 ps
T306 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1148418753 Jun 22 04:43:22 PM PDT 24 Jun 22 04:43:23 PM PDT 24 359277848 ps
T307 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.707813712 Jun 22 04:42:51 PM PDT 24 Jun 22 04:42:58 PM PDT 24 13691411581 ps
T79 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1555581978 Jun 22 04:43:36 PM PDT 24 Jun 22 04:43:38 PM PDT 24 1561710208 ps
T308 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3389258195 Jun 22 04:43:54 PM PDT 24 Jun 22 04:43:56 PM PDT 24 399463477 ps
T65 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.463769827 Jun 22 04:43:16 PM PDT 24 Jun 22 04:43:17 PM PDT 24 502193585 ps
T309 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.250978919 Jun 22 04:42:32 PM PDT 24 Jun 22 04:42:33 PM PDT 24 494240949 ps
T310 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2384570210 Jun 22 04:43:43 PM PDT 24 Jun 22 04:43:44 PM PDT 24 507983315 ps
T311 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3289753720 Jun 22 04:43:14 PM PDT 24 Jun 22 04:43:15 PM PDT 24 375649413 ps
T80 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3280817298 Jun 22 04:43:22 PM PDT 24 Jun 22 04:43:24 PM PDT 24 328467995 ps
T81 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4197602807 Jun 22 04:42:45 PM PDT 24 Jun 22 04:42:47 PM PDT 24 2295597409 ps
T312 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.409317976 Jun 22 04:43:21 PM PDT 24 Jun 22 04:43:24 PM PDT 24 4003609519 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3096023284 Jun 22 04:43:00 PM PDT 24 Jun 22 04:43:01 PM PDT 24 317894098 ps
T313 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2347235509 Jun 22 04:42:47 PM PDT 24 Jun 22 04:42:54 PM PDT 24 8760876888 ps
T314 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1379002279 Jun 22 04:43:44 PM PDT 24 Jun 22 04:43:46 PM PDT 24 684130338 ps
T315 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1237154987 Jun 22 04:43:21 PM PDT 24 Jun 22 04:43:24 PM PDT 24 424560064 ps
T316 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1741564147 Jun 22 04:43:56 PM PDT 24 Jun 22 04:43:57 PM PDT 24 295833109 ps
T317 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3784718170 Jun 22 04:42:32 PM PDT 24 Jun 22 04:42:34 PM PDT 24 279918359 ps
T318 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1638797328 Jun 22 04:43:48 PM PDT 24 Jun 22 04:43:50 PM PDT 24 431522328 ps
T191 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3477990043 Jun 22 04:43:22 PM PDT 24 Jun 22 04:43:28 PM PDT 24 7869470274 ps
T319 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.27440041 Jun 22 04:42:37 PM PDT 24 Jun 22 04:42:39 PM PDT 24 375204421 ps
T320 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.672341830 Jun 22 04:43:21 PM PDT 24 Jun 22 04:43:23 PM PDT 24 490651598 ps
T321 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.747582149 Jun 22 04:43:45 PM PDT 24 Jun 22 04:43:48 PM PDT 24 439513289 ps
T322 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2601557942 Jun 22 04:43:35 PM PDT 24 Jun 22 04:43:38 PM PDT 24 3034655145 ps
T323 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3055095644 Jun 22 04:43:23 PM PDT 24 Jun 22 04:43:25 PM PDT 24 1904680412 ps
T324 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1187031408 Jun 22 04:43:40 PM PDT 24 Jun 22 04:43:41 PM PDT 24 400599409 ps
T325 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1137435573 Jun 22 04:43:21 PM PDT 24 Jun 22 04:43:22 PM PDT 24 411738245 ps
T326 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.253158453 Jun 22 04:43:37 PM PDT 24 Jun 22 04:43:39 PM PDT 24 294530015 ps
T327 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2255380223 Jun 22 04:43:07 PM PDT 24 Jun 22 04:43:11 PM PDT 24 7785718249 ps
T328 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3204963670 Jun 22 04:43:21 PM PDT 24 Jun 22 04:43:23 PM PDT 24 525323703 ps
T329 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1349646707 Jun 22 04:43:00 PM PDT 24 Jun 22 04:43:01 PM PDT 24 382623243 ps
T330 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3993095491 Jun 22 04:43:54 PM PDT 24 Jun 22 04:43:56 PM PDT 24 340789153 ps
T331 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3366111577 Jun 22 04:43:43 PM PDT 24 Jun 22 04:43:46 PM PDT 24 451821588 ps
T332 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3331086305 Jun 22 04:42:59 PM PDT 24 Jun 22 04:43:17 PM PDT 24 6998266354 ps
T333 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3703564987 Jun 22 04:43:43 PM PDT 24 Jun 22 04:43:44 PM PDT 24 440804851 ps
T334 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3214268369 Jun 22 04:43:54 PM PDT 24 Jun 22 04:43:55 PM PDT 24 307693976 ps
T335 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1747461573 Jun 22 04:43:54 PM PDT 24 Jun 22 04:43:56 PM PDT 24 377488897 ps
T336 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2371961975 Jun 22 04:42:38 PM PDT 24 Jun 22 04:42:40 PM PDT 24 433876203 ps
T337 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4055355378 Jun 22 04:42:32 PM PDT 24 Jun 22 04:42:34 PM PDT 24 866926202 ps
T338 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1943360256 Jun 22 04:42:59 PM PDT 24 Jun 22 04:43:00 PM PDT 24 322742821 ps
T67 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2642618590 Jun 22 04:43:08 PM PDT 24 Jun 22 04:43:09 PM PDT 24 387315549 ps
T339 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.917545982 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:31 PM PDT 24 427397417 ps
T340 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.229743017 Jun 22 04:43:55 PM PDT 24 Jun 22 04:43:57 PM PDT 24 454816000 ps
T341 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2292059537 Jun 22 04:43:07 PM PDT 24 Jun 22 04:43:08 PM PDT 24 1180585348 ps
T342 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.603345423 Jun 22 04:43:30 PM PDT 24 Jun 22 04:43:33 PM PDT 24 3843098565 ps
T343 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3177725842 Jun 22 04:43:24 PM PDT 24 Jun 22 04:43:25 PM PDT 24 430565834 ps
T68 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2422625391 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:32 PM PDT 24 376672433 ps
T344 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2452995513 Jun 22 04:42:52 PM PDT 24 Jun 22 04:42:53 PM PDT 24 324641712 ps
T345 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3210371573 Jun 22 04:43:37 PM PDT 24 Jun 22 04:43:39 PM PDT 24 413610125 ps
T346 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1243501653 Jun 22 04:43:36 PM PDT 24 Jun 22 04:43:38 PM PDT 24 597822221 ps
T347 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1031193724 Jun 22 04:43:21 PM PDT 24 Jun 22 04:43:23 PM PDT 24 525436065 ps
T348 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2483815262 Jun 22 04:43:00 PM PDT 24 Jun 22 04:43:02 PM PDT 24 392658296 ps
T349 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4007879170 Jun 22 04:43:20 PM PDT 24 Jun 22 04:43:21 PM PDT 24 408292185 ps
T350 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.889873367 Jun 22 04:43:11 PM PDT 24 Jun 22 04:43:12 PM PDT 24 437523011 ps
T351 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3919140523 Jun 22 04:43:43 PM PDT 24 Jun 22 04:43:45 PM PDT 24 363518059 ps
T352 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2544955040 Jun 22 04:43:21 PM PDT 24 Jun 22 04:43:25 PM PDT 24 570555982 ps
T353 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.643564548 Jun 22 04:42:52 PM PDT 24 Jun 22 04:42:58 PM PDT 24 4292583887 ps
T354 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.299740786 Jun 22 04:43:45 PM PDT 24 Jun 22 04:43:48 PM PDT 24 2314591437 ps
T355 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3854943980 Jun 22 04:43:22 PM PDT 24 Jun 22 04:43:26 PM PDT 24 4076120558 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1330655488 Jun 22 04:42:45 PM PDT 24 Jun 22 04:42:46 PM PDT 24 499935168 ps
T356 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2074429669 Jun 22 04:42:51 PM PDT 24 Jun 22 04:42:54 PM PDT 24 2166900917 ps
T357 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1572088903 Jun 22 04:43:37 PM PDT 24 Jun 22 04:43:39 PM PDT 24 2820984109 ps
T358 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3755759374 Jun 22 04:42:47 PM PDT 24 Jun 22 04:42:48 PM PDT 24 339948638 ps
T359 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.476848354 Jun 22 04:43:22 PM PDT 24 Jun 22 04:43:24 PM PDT 24 688300425 ps
T360 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3081410428 Jun 22 04:43:24 PM PDT 24 Jun 22 04:43:25 PM PDT 24 614312491 ps
T361 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4225456834 Jun 22 04:43:22 PM PDT 24 Jun 22 04:43:24 PM PDT 24 2758141271 ps
T362 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.851738245 Jun 22 04:43:43 PM PDT 24 Jun 22 04:43:46 PM PDT 24 564862574 ps
T363 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.888780631 Jun 22 04:43:14 PM PDT 24 Jun 22 04:43:16 PM PDT 24 1190462946 ps
T70 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.29968893 Jun 22 04:42:51 PM PDT 24 Jun 22 04:42:52 PM PDT 24 533145483 ps
T364 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3343781854 Jun 22 04:43:38 PM PDT 24 Jun 22 04:43:40 PM PDT 24 518621274 ps
T365 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1078747064 Jun 22 04:43:22 PM PDT 24 Jun 22 04:43:24 PM PDT 24 517152934 ps
T366 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3910188425 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:31 PM PDT 24 375493724 ps
T367 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2001762811 Jun 22 04:43:07 PM PDT 24 Jun 22 04:43:08 PM PDT 24 493435516 ps
T368 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.477410661 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:30 PM PDT 24 377797392 ps
T71 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1723718255 Jun 22 04:42:51 PM PDT 24 Jun 22 04:42:52 PM PDT 24 524230785 ps
T72 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1601573440 Jun 22 04:42:33 PM PDT 24 Jun 22 04:42:42 PM PDT 24 6740449929 ps
T192 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3235910414 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:42 PM PDT 24 7606787406 ps
T369 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2755747181 Jun 22 04:42:58 PM PDT 24 Jun 22 04:43:00 PM PDT 24 555928755 ps
T370 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.583741996 Jun 22 04:43:54 PM PDT 24 Jun 22 04:43:55 PM PDT 24 474594481 ps
T371 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3980116829 Jun 22 04:43:23 PM PDT 24 Jun 22 04:43:25 PM PDT 24 567003171 ps
T372 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3717829208 Jun 22 04:43:12 PM PDT 24 Jun 22 04:43:13 PM PDT 24 844303103 ps
T373 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2244870534 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:31 PM PDT 24 423608567 ps
T374 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3485496217 Jun 22 04:42:37 PM PDT 24 Jun 22 04:42:38 PM PDT 24 424043012 ps
T375 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2933810935 Jun 22 04:43:23 PM PDT 24 Jun 22 04:43:26 PM PDT 24 844839659 ps
T376 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1865203639 Jun 22 04:43:31 PM PDT 24 Jun 22 04:43:33 PM PDT 24 466843258 ps
T377 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3080197411 Jun 22 04:43:28 PM PDT 24 Jun 22 04:43:31 PM PDT 24 2945595684 ps
T378 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3518644747 Jun 22 04:43:38 PM PDT 24 Jun 22 04:43:40 PM PDT 24 402548595 ps
T379 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1203652191 Jun 22 04:43:39 PM PDT 24 Jun 22 04:43:41 PM PDT 24 687472090 ps
T380 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3107076066 Jun 22 04:43:55 PM PDT 24 Jun 22 04:43:57 PM PDT 24 369772272 ps
T381 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4262873102 Jun 22 04:42:38 PM PDT 24 Jun 22 04:42:40 PM PDT 24 682313503 ps
T382 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3189746583 Jun 22 04:43:13 PM PDT 24 Jun 22 04:43:20 PM PDT 24 7893614908 ps
T383 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1450995457 Jun 22 04:43:36 PM PDT 24 Jun 22 04:43:41 PM PDT 24 3933359079 ps
T193 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4267144311 Jun 22 04:42:32 PM PDT 24 Jun 22 04:42:45 PM PDT 24 8071526489 ps
T384 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3215283950 Jun 22 04:43:45 PM PDT 24 Jun 22 04:43:47 PM PDT 24 432829452 ps
T385 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2393262575 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:30 PM PDT 24 474075879 ps
T386 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2226539850 Jun 22 04:42:46 PM PDT 24 Jun 22 04:42:47 PM PDT 24 318632574 ps
T387 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3262674988 Jun 22 04:43:55 PM PDT 24 Jun 22 04:43:57 PM PDT 24 384314887 ps
T388 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3353918223 Jun 22 04:43:37 PM PDT 24 Jun 22 04:43:40 PM PDT 24 516642749 ps
T389 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4221312487 Jun 22 04:43:15 PM PDT 24 Jun 22 04:43:19 PM PDT 24 388438598 ps
T390 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3844009557 Jun 22 04:43:42 PM PDT 24 Jun 22 04:43:44 PM PDT 24 386910745 ps
T391 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.513477874 Jun 22 04:42:53 PM PDT 24 Jun 22 04:42:54 PM PDT 24 503537910 ps
T392 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1028777765 Jun 22 04:43:28 PM PDT 24 Jun 22 04:43:30 PM PDT 24 504501684 ps
T393 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3649019161 Jun 22 04:43:14 PM PDT 24 Jun 22 04:43:16 PM PDT 24 1721112717 ps
T394 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2081328447 Jun 22 04:43:21 PM PDT 24 Jun 22 04:43:23 PM PDT 24 473732402 ps
T73 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.33133439 Jun 22 04:42:31 PM PDT 24 Jun 22 04:42:32 PM PDT 24 527698241 ps
T395 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1582350554 Jun 22 04:42:37 PM PDT 24 Jun 22 04:42:40 PM PDT 24 1241894695 ps
T396 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.751444859 Jun 22 04:43:55 PM PDT 24 Jun 22 04:43:56 PM PDT 24 524202810 ps
T397 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2253856454 Jun 22 04:43:25 PM PDT 24 Jun 22 04:43:27 PM PDT 24 482551630 ps
T398 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1680197934 Jun 22 04:43:30 PM PDT 24 Jun 22 04:43:31 PM PDT 24 413430112 ps
T74 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1419892258 Jun 22 04:42:39 PM PDT 24 Jun 22 04:42:42 PM PDT 24 1095759913 ps
T399 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2737848884 Jun 22 04:42:50 PM PDT 24 Jun 22 04:42:51 PM PDT 24 432501139 ps
T400 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1681050259 Jun 22 04:43:21 PM PDT 24 Jun 22 04:43:35 PM PDT 24 8404164645 ps
T401 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2176219409 Jun 22 04:42:51 PM PDT 24 Jun 22 04:42:53 PM PDT 24 447803973 ps
T402 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.741776948 Jun 22 04:43:29 PM PDT 24 Jun 22 04:43:32 PM PDT 24 1059049439 ps
T403 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.449861754 Jun 22 04:43:15 PM PDT 24 Jun 22 04:43:17 PM PDT 24 502610939 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3341681648 Jun 22 04:42:59 PM PDT 24 Jun 22 04:43:00 PM PDT 24 351666396 ps
T405 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1639188603 Jun 22 04:42:40 PM PDT 24 Jun 22 04:42:42 PM PDT 24 402966009 ps
T406 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2476754682 Jun 22 04:43:13 PM PDT 24 Jun 22 04:43:15 PM PDT 24 545790215 ps
T407 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3400870621 Jun 22 04:43:13 PM PDT 24 Jun 22 04:43:15 PM PDT 24 1125464622 ps
T408 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1533378622 Jun 22 04:45:07 PM PDT 24 Jun 22 04:45:09 PM PDT 24 399941683 ps
T409 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1759154981 Jun 22 04:43:32 PM PDT 24 Jun 22 04:43:33 PM PDT 24 1202474842 ps
T410 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2469248612 Jun 22 04:42:45 PM PDT 24 Jun 22 04:43:02 PM PDT 24 7078803228 ps
T411 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3760572515 Jun 22 04:43:21 PM PDT 24 Jun 22 04:43:24 PM PDT 24 444821016 ps
T412 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.219464156 Jun 22 04:43:43 PM PDT 24 Jun 22 04:43:45 PM PDT 24 479371812 ps
T413 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.36632723 Jun 22 04:42:51 PM PDT 24 Jun 22 04:42:53 PM PDT 24 347934984 ps
T414 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4135749097 Jun 22 04:43:14 PM PDT 24 Jun 22 04:43:15 PM PDT 24 578582531 ps
T415 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2986126747 Jun 22 04:43:54 PM PDT 24 Jun 22 04:43:55 PM PDT 24 283054312 ps
T416 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1031980139 Jun 22 04:42:44 PM PDT 24 Jun 22 04:42:46 PM PDT 24 544407911 ps
T417 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3781736293 Jun 22 04:42:44 PM PDT 24 Jun 22 04:42:47 PM PDT 24 941121106 ps
T418 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1064263734 Jun 22 04:43:24 PM PDT 24 Jun 22 04:43:26 PM PDT 24 862753855 ps
T419 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4253513243 Jun 22 04:43:22 PM PDT 24 Jun 22 04:43:24 PM PDT 24 553634161 ps
T420 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4202236417 Jun 22 04:43:13 PM PDT 24 Jun 22 04:43:15 PM PDT 24 289926602 ps

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2802123421
Short name T6
Test name
Test status
Simulation time 33623736558 ps
CPU time 343.42 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:55:53 PM PDT 24
Peak memory 199520 kb
Host smart-67f3b68a-42ac-4f56-ae48-40e872243a5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802123421 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2802123421
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.27163474
Short name T95
Test name
Test status
Simulation time 66959969431 ps
CPU time 498.06 seconds
Started Jun 22 04:50:20 PM PDT 24
Finished Jun 22 04:58:39 PM PDT 24
Peak memory 202804 kb
Host smart-19ea229f-c76e-4894-b388-366343a7a2fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27163474 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.27163474
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1742276929
Short name T36
Test name
Test status
Simulation time 4258448106 ps
CPU time 2.01 seconds
Started Jun 22 04:43:37 PM PDT 24
Finished Jun 22 04:43:40 PM PDT 24
Peak memory 197800 kb
Host smart-00aefea4-c95b-48b6-b5a5-dd0ea897f1a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742276929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1742276929
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3544051719
Short name T10
Test name
Test status
Simulation time 121498770659 ps
CPU time 158.92 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:52:43 PM PDT 24
Peak memory 192432 kb
Host smart-14ff198d-bef3-43e7-842a-3da6479b15f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544051719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3544051719
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.759286733
Short name T136
Test name
Test status
Simulation time 261851966163 ps
CPU time 797.69 seconds
Started Jun 22 04:50:15 PM PDT 24
Finished Jun 22 05:03:33 PM PDT 24
Peak memory 208648 kb
Host smart-ae272f3e-19b7-45bd-a90c-9a936d630d0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759286733 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.759286733
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1526241844
Short name T104
Test name
Test status
Simulation time 385310533522 ps
CPU time 716.19 seconds
Started Jun 22 04:50:24 PM PDT 24
Finished Jun 22 05:02:20 PM PDT 24
Peak memory 215376 kb
Host smart-f34ee1db-91c4-46ee-b2df-30d9583296e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526241844 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1526241844
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3486791829
Short name T55
Test name
Test status
Simulation time 68229681690 ps
CPU time 431.01 seconds
Started Jun 22 04:50:25 PM PDT 24
Finished Jun 22 04:57:37 PM PDT 24
Peak memory 207344 kb
Host smart-dce0bd98-ae88-4c18-970f-994c3a967e52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486791829 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3486791829
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.933866890
Short name T100
Test name
Test status
Simulation time 442687093854 ps
CPU time 404.25 seconds
Started Jun 22 04:50:37 PM PDT 24
Finished Jun 22 04:57:22 PM PDT 24
Peak memory 211844 kb
Host smart-d92c80d9-d98a-4280-bb57-6f66e9977022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933866890 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.933866890
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1418110775
Short name T89
Test name
Test status
Simulation time 77372370255 ps
CPU time 592.32 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 05:00:02 PM PDT 24
Peak memory 205196 kb
Host smart-d6012322-1a92-4d10-af2b-fb034aa61e63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418110775 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1418110775
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.4068678675
Short name T120
Test name
Test status
Simulation time 116399117328 ps
CPU time 911.89 seconds
Started Jun 22 04:50:32 PM PDT 24
Finished Jun 22 05:05:46 PM PDT 24
Peak memory 215488 kb
Host smart-1c9b26ff-8982-4319-b469-4dbb00530ade
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068678675 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.4068678675
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3417652005
Short name T20
Test name
Test status
Simulation time 3985065611 ps
CPU time 3.25 seconds
Started Jun 22 04:49:52 PM PDT 24
Finished Jun 22 04:49:56 PM PDT 24
Peak memory 215996 kb
Host smart-46251b01-164e-4e3b-8cab-04c9d12d1edb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417652005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3417652005
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.4119114960
Short name T130
Test name
Test status
Simulation time 14284177270 ps
CPU time 12 seconds
Started Jun 22 04:50:20 PM PDT 24
Finished Jun 22 04:50:34 PM PDT 24
Peak memory 193492 kb
Host smart-f5f5f472-b73e-4cfc-9d87-0f6c5aea0e32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119114960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.4119114960
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1366815699
Short name T147
Test name
Test status
Simulation time 39593079282 ps
CPU time 24.58 seconds
Started Jun 22 04:50:26 PM PDT 24
Finished Jun 22 04:50:52 PM PDT 24
Peak memory 184564 kb
Host smart-3b728edd-62e9-4b57-9072-cca17dd2166d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366815699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1366815699
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.768239503
Short name T94
Test name
Test status
Simulation time 83429897058 ps
CPU time 146.88 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:52:32 PM PDT 24
Peak memory 207312 kb
Host smart-09acb071-0ea1-4c79-8d38-cf8d7d6722ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768239503 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.768239503
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3093672513
Short name T146
Test name
Test status
Simulation time 37900075416 ps
CPU time 49.91 seconds
Started Jun 22 04:50:14 PM PDT 24
Finished Jun 22 04:51:05 PM PDT 24
Peak memory 193428 kb
Host smart-5de2fa3d-aba4-45df-b613-9309673092f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093672513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3093672513
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3538568829
Short name T123
Test name
Test status
Simulation time 515830187051 ps
CPU time 672.03 seconds
Started Jun 22 04:49:55 PM PDT 24
Finished Jun 22 05:01:09 PM PDT 24
Peak memory 192952 kb
Host smart-edb959ac-3ea6-4416-84a4-45cac33b31c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538568829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3538568829
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1781170033
Short name T28
Test name
Test status
Simulation time 37703355916 ps
CPU time 383.47 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:56:57 PM PDT 24
Peak memory 200244 kb
Host smart-87f1470a-ca4b-4b1e-9e15-f65b42081294
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781170033 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1781170033
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2373380778
Short name T27
Test name
Test status
Simulation time 93814792685 ps
CPU time 372.77 seconds
Started Jun 22 04:50:22 PM PDT 24
Finished Jun 22 04:56:35 PM PDT 24
Peak memory 202808 kb
Host smart-58e4dfb5-d74d-4676-833d-101102a440c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373380778 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2373380778
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.463769827
Short name T65
Test name
Test status
Simulation time 502193585 ps
CPU time 0.79 seconds
Started Jun 22 04:43:16 PM PDT 24
Finished Jun 22 04:43:17 PM PDT 24
Peak memory 193136 kb
Host smart-40b22d64-b54e-45f1-9219-4046cbcbec1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463769827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.463769827
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3343790928
Short name T91
Test name
Test status
Simulation time 217614456933 ps
CPU time 551.43 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:59:21 PM PDT 24
Peak memory 207308 kb
Host smart-d9b5f3ec-fcda-4de5-bcfc-68cb08488ff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343790928 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3343790928
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1851993771
Short name T45
Test name
Test status
Simulation time 972695242146 ps
CPU time 351.39 seconds
Started Jun 22 04:50:04 PM PDT 24
Finished Jun 22 04:55:56 PM PDT 24
Peak memory 202048 kb
Host smart-038fc15c-4c42-4a97-ab02-fb2fcd33a84d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851993771 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1851993771
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1616262142
Short name T107
Test name
Test status
Simulation time 21529388608 ps
CPU time 10.01 seconds
Started Jun 22 04:50:32 PM PDT 24
Finished Jun 22 04:50:42 PM PDT 24
Peak memory 198764 kb
Host smart-d264f0cd-4e50-440d-afec-df807e2f881e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616262142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1616262142
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1988894141
Short name T148
Test name
Test status
Simulation time 106775602627 ps
CPU time 866.23 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 05:04:28 PM PDT 24
Peak memory 208244 kb
Host smart-4b152fad-51a4-419f-aa51-93d862209477
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988894141 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1988894141
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3696025814
Short name T106
Test name
Test status
Simulation time 122097164447 ps
CPU time 100.01 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:51:50 PM PDT 24
Peak memory 184816 kb
Host smart-a88106eb-76ca-42c0-af5a-73a64c1e2e48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696025814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3696025814
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.909334808
Short name T112
Test name
Test status
Simulation time 202376409552 ps
CPU time 576.82 seconds
Started Jun 22 04:50:26 PM PDT 24
Finished Jun 22 05:00:03 PM PDT 24
Peak memory 207304 kb
Host smart-afb63a23-9424-42e2-a035-a90367045b9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909334808 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.909334808
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1760642708
Short name T118
Test name
Test status
Simulation time 49692476584 ps
CPU time 345.95 seconds
Started Jun 22 04:50:28 PM PDT 24
Finished Jun 22 04:56:15 PM PDT 24
Peak memory 207312 kb
Host smart-601e353a-6c87-4b34-a2a1-63d4c0c950e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760642708 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1760642708
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2387516328
Short name T34
Test name
Test status
Simulation time 83645957881 ps
CPU time 218.09 seconds
Started Jun 22 04:50:20 PM PDT 24
Finished Jun 22 04:53:59 PM PDT 24
Peak memory 200584 kb
Host smart-8639dad6-c57a-4340-9336-60549496c4b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387516328 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2387516328
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1066251735
Short name T92
Test name
Test status
Simulation time 313086082514 ps
CPU time 475.26 seconds
Started Jun 22 04:50:02 PM PDT 24
Finished Jun 22 04:57:57 PM PDT 24
Peak memory 211456 kb
Host smart-c504f004-3c78-4ed2-bbc3-e9f11cec272a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066251735 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1066251735
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2839431875
Short name T141
Test name
Test status
Simulation time 68861498322 ps
CPU time 9.08 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:50:43 PM PDT 24
Peak memory 198736 kb
Host smart-311ca888-4099-4563-b232-d7c8da394493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839431875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2839431875
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2708188327
Short name T115
Test name
Test status
Simulation time 214886813854 ps
CPU time 75.22 seconds
Started Jun 22 04:50:30 PM PDT 24
Finished Jun 22 04:51:45 PM PDT 24
Peak memory 193432 kb
Host smart-7ceb3f7d-3f74-4871-834d-ac454c01bd06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708188327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2708188327
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3352082179
Short name T64
Test name
Test status
Simulation time 103640189063 ps
CPU time 147.94 seconds
Started Jun 22 04:50:11 PM PDT 24
Finished Jun 22 04:52:40 PM PDT 24
Peak memory 198784 kb
Host smart-148e6a79-175b-4d8d-9054-8b9c00c2587c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352082179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3352082179
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.285072121
Short name T3
Test name
Test status
Simulation time 46187474503 ps
CPU time 364.39 seconds
Started Jun 22 04:50:20 PM PDT 24
Finished Jun 22 04:56:26 PM PDT 24
Peak memory 200548 kb
Host smart-6f5cf669-44a9-4cd7-8bf4-06e94a32e42f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285072121 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.285072121
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3576096188
Short name T140
Test name
Test status
Simulation time 163163948333 ps
CPU time 132.22 seconds
Started Jun 22 04:50:22 PM PDT 24
Finished Jun 22 04:52:35 PM PDT 24
Peak memory 207268 kb
Host smart-0a944b0b-e7e1-4492-b65a-a07bd7d22801
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576096188 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3576096188
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3172934633
Short name T105
Test name
Test status
Simulation time 94911439807 ps
CPU time 144.69 seconds
Started Jun 22 04:49:59 PM PDT 24
Finished Jun 22 04:52:24 PM PDT 24
Peak memory 193360 kb
Host smart-99637a01-94f4-45b3-9e58-7c0d8e5349ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172934633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3172934633
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.584683592
Short name T116
Test name
Test status
Simulation time 91883365191 ps
CPU time 199.21 seconds
Started Jun 22 04:50:27 PM PDT 24
Finished Jun 22 04:53:47 PM PDT 24
Peak memory 209400 kb
Host smart-a16e42d8-65c4-47f5-8e9c-372cf0dabe14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584683592 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.584683592
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1869050103
Short name T133
Test name
Test status
Simulation time 92268752027 ps
CPU time 89.18 seconds
Started Jun 22 04:50:17 PM PDT 24
Finished Jun 22 04:51:46 PM PDT 24
Peak memory 192424 kb
Host smart-36508953-c5e3-4320-beda-ab9611898e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869050103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1869050103
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.996964153
Short name T53
Test name
Test status
Simulation time 582988909 ps
CPU time 1.01 seconds
Started Jun 22 04:50:25 PM PDT 24
Finished Jun 22 04:50:27 PM PDT 24
Peak memory 197144 kb
Host smart-5bfed24b-50e2-49c4-a00c-633c709bea7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996964153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.996964153
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1226329456
Short name T97
Test name
Test status
Simulation time 266751714660 ps
CPU time 181.81 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:53:06 PM PDT 24
Peak memory 214452 kb
Host smart-2b92a540-3cbc-4b59-9a51-ee7f7e26be4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226329456 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1226329456
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.4167457186
Short name T98
Test name
Test status
Simulation time 127522826336 ps
CPU time 449.02 seconds
Started Jun 22 04:50:12 PM PDT 24
Finished Jun 22 04:57:41 PM PDT 24
Peak memory 202448 kb
Host smart-d05ade44-381f-48a8-94e6-49701dde1521
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167457186 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.4167457186
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1803403066
Short name T132
Test name
Test status
Simulation time 88075174433 ps
CPU time 129.33 seconds
Started Jun 22 04:50:20 PM PDT 24
Finished Jun 22 04:52:30 PM PDT 24
Peak memory 198788 kb
Host smart-a9da97d6-e446-4dc4-9cc5-ff209eced080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803403066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1803403066
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1629668206
Short name T161
Test name
Test status
Simulation time 194507945948 ps
CPU time 78.92 seconds
Started Jun 22 04:50:11 PM PDT 24
Finished Jun 22 04:51:31 PM PDT 24
Peak memory 193500 kb
Host smart-a33ddd79-69aa-47e8-8069-bf093bf3981e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629668206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1629668206
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2109781153
Short name T101
Test name
Test status
Simulation time 32600178209 ps
CPU time 245.46 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:54:10 PM PDT 24
Peak memory 207304 kb
Host smart-71ee818e-e45a-4002-9ba2-95eedd4db464
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109781153 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2109781153
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1457440484
Short name T143
Test name
Test status
Simulation time 46517423259 ps
CPU time 491.45 seconds
Started Jun 22 04:50:04 PM PDT 24
Finished Jun 22 04:58:16 PM PDT 24
Peak memory 202384 kb
Host smart-686bef84-ec50-46c8-8f86-8828523e1e1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457440484 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1457440484
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1261182977
Short name T127
Test name
Test status
Simulation time 304849937395 ps
CPU time 105.35 seconds
Started Jun 22 04:50:05 PM PDT 24
Finished Jun 22 04:51:51 PM PDT 24
Peak memory 193404 kb
Host smart-dbf22dc5-938d-4cac-9c9d-09dc72e3de9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261182977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1261182977
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2693270136
Short name T121
Test name
Test status
Simulation time 259714405561 ps
CPU time 406.02 seconds
Started Jun 22 04:50:31 PM PDT 24
Finished Jun 22 04:57:18 PM PDT 24
Peak memory 192412 kb
Host smart-8ad48a3b-9845-4a5d-920d-5bc946d907cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693270136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2693270136
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.367315775
Short name T108
Test name
Test status
Simulation time 104354339419 ps
CPU time 24.88 seconds
Started Jun 22 04:50:11 PM PDT 24
Finished Jun 22 04:50:37 PM PDT 24
Peak memory 192424 kb
Host smart-0daae075-fb33-4ea8-91f9-0c275e4a7b89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367315775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.367315775
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3904403681
Short name T169
Test name
Test status
Simulation time 84866616928 ps
CPU time 79.39 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:51:30 PM PDT 24
Peak memory 193400 kb
Host smart-bed3b065-5a7f-4bc0-9726-12bb322ebdca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904403681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3904403681
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1977855238
Short name T124
Test name
Test status
Simulation time 114387229961 ps
CPU time 189.45 seconds
Started Jun 22 04:49:59 PM PDT 24
Finished Jun 22 04:53:10 PM PDT 24
Peak memory 192404 kb
Host smart-a5f28d4c-ff7d-42d2-953f-c6a5808068dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977855238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1977855238
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2351712790
Short name T131
Test name
Test status
Simulation time 306951495756 ps
CPU time 242.29 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:54:12 PM PDT 24
Peak memory 193444 kb
Host smart-bcc5411c-7f1e-416e-953e-4c2acf33797d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351712790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2351712790
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.4056638297
Short name T82
Test name
Test status
Simulation time 51297931185 ps
CPU time 19.63 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:50:29 PM PDT 24
Peak memory 192400 kb
Host smart-3fca92df-bda4-4e4a-b91f-ab60c234c720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056638297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.4056638297
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3954989612
Short name T158
Test name
Test status
Simulation time 78049206832 ps
CPU time 418.17 seconds
Started Jun 22 04:50:19 PM PDT 24
Finished Jun 22 04:57:18 PM PDT 24
Peak memory 211548 kb
Host smart-bca84669-570f-4976-acc3-907db3bf0128
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954989612 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3954989612
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.4271183338
Short name T44
Test name
Test status
Simulation time 19148306992 ps
CPU time 56.71 seconds
Started Jun 22 04:49:53 PM PDT 24
Finished Jun 22 04:50:51 PM PDT 24
Peak memory 199132 kb
Host smart-7c8dfc25-e5cd-4299-888f-2ef88a45dbf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271183338 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.4271183338
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2165711881
Short name T110
Test name
Test status
Simulation time 147749891980 ps
CPU time 41.87 seconds
Started Jun 22 04:49:55 PM PDT 24
Finished Jun 22 04:50:38 PM PDT 24
Peak memory 193040 kb
Host smart-8e93565a-8764-4145-8961-b01607087dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165711881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2165711881
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.4003546770
Short name T142
Test name
Test status
Simulation time 4823661551 ps
CPU time 8.01 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:50:18 PM PDT 24
Peak memory 192416 kb
Host smart-4c58331a-581f-4513-b603-b6078cf7d200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003546770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.4003546770
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3694187777
Short name T103
Test name
Test status
Simulation time 198653580804 ps
CPU time 300.6 seconds
Started Jun 22 04:50:16 PM PDT 24
Finished Jun 22 04:55:17 PM PDT 24
Peak memory 192412 kb
Host smart-24fc945b-41d5-4cd4-ab92-35eaaa7396b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694187777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3694187777
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2469597558
Short name T164
Test name
Test status
Simulation time 70215575613 ps
CPU time 95.17 seconds
Started Jun 22 04:50:25 PM PDT 24
Finished Jun 22 04:52:01 PM PDT 24
Peak memory 192348 kb
Host smart-fccbbffa-1b39-4716-90d2-4578bbf2f399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469597558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2469597558
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3818331366
Short name T86
Test name
Test status
Simulation time 13020598990 ps
CPU time 93.52 seconds
Started Jun 22 04:49:54 PM PDT 24
Finished Jun 22 04:51:29 PM PDT 24
Peak memory 207284 kb
Host smart-1ffdb1c6-54b2-4ff7-9129-a527db3bb58f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818331366 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3818331366
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3335666056
Short name T46
Test name
Test status
Simulation time 77469876941 ps
CPU time 322.31 seconds
Started Jun 22 04:50:02 PM PDT 24
Finished Jun 22 04:55:26 PM PDT 24
Peak memory 207252 kb
Host smart-201ffcc7-f091-4345-ace4-f8e9f3a5a100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335666056 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3335666056
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1040072133
Short name T179
Test name
Test status
Simulation time 160411771932 ps
CPU time 252.95 seconds
Started Jun 22 04:50:07 PM PDT 24
Finished Jun 22 04:54:21 PM PDT 24
Peak memory 207308 kb
Host smart-05f1d2fd-7ba5-4d2c-8f1a-945dd5b39308
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040072133 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1040072133
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3195822300
Short name T102
Test name
Test status
Simulation time 91530187210 ps
CPU time 103.66 seconds
Started Jun 22 04:50:18 PM PDT 24
Finished Jun 22 04:52:02 PM PDT 24
Peak memory 192432 kb
Host smart-911bf5af-d264-46f8-8f00-412026fa1fb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195822300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3195822300
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1633397176
Short name T163
Test name
Test status
Simulation time 33860810875 ps
CPU time 14.52 seconds
Started Jun 22 04:49:53 PM PDT 24
Finished Jun 22 04:50:09 PM PDT 24
Peak memory 192376 kb
Host smart-36318576-2979-47f8-a795-6fd8118db09f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633397176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1633397176
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2626726587
Short name T152
Test name
Test status
Simulation time 127700025602 ps
CPU time 50.07 seconds
Started Jun 22 04:50:31 PM PDT 24
Finished Jun 22 04:51:21 PM PDT 24
Peak memory 198784 kb
Host smart-aa18c130-b83e-48f3-8167-fc146c4fe1f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626726587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2626726587
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.4175244832
Short name T134
Test name
Test status
Simulation time 149014898582 ps
CPU time 60.03 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:51:01 PM PDT 24
Peak memory 192384 kb
Host smart-f2668c77-6b24-498b-9bdf-c08a15fcdf18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175244832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.4175244832
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3756081835
Short name T129
Test name
Test status
Simulation time 410641429 ps
CPU time 0.78 seconds
Started Jun 22 04:49:58 PM PDT 24
Finished Jun 22 04:49:59 PM PDT 24
Peak memory 197168 kb
Host smart-ba884750-edc0-4125-8a1f-bd80f4ee16f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756081835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3756081835
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1991904602
Short name T155
Test name
Test status
Simulation time 455198276 ps
CPU time 0.78 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:50:04 PM PDT 24
Peak memory 197132 kb
Host smart-bb270815-4fc5-4534-9026-e5f62dca6942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991904602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1991904602
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3309674927
Short name T19
Test name
Test status
Simulation time 422946171273 ps
CPU time 626.04 seconds
Started Jun 22 04:50:10 PM PDT 24
Finished Jun 22 05:00:37 PM PDT 24
Peak memory 193388 kb
Host smart-45f48251-0521-4330-9191-bb2ffdd27e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309674927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3309674927
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.4084916077
Short name T156
Test name
Test status
Simulation time 536430945 ps
CPU time 1 seconds
Started Jun 22 04:49:53 PM PDT 24
Finished Jun 22 04:49:56 PM PDT 24
Peak memory 197084 kb
Host smart-739acc8d-64f0-4011-8175-739904a74a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084916077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4084916077
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2501171179
Short name T150
Test name
Test status
Simulation time 556468612229 ps
CPU time 850.01 seconds
Started Jun 22 04:50:19 PM PDT 24
Finished Jun 22 05:04:30 PM PDT 24
Peak memory 193000 kb
Host smart-d0c20e51-4819-46e4-9fb1-e4f872c08045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501171179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2501171179
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.4277817119
Short name T57
Test name
Test status
Simulation time 292213003952 ps
CPU time 409.94 seconds
Started Jun 22 04:50:17 PM PDT 24
Finished Jun 22 04:57:08 PM PDT 24
Peak memory 193380 kb
Host smart-3f09d5fb-8f1c-472a-96bf-28484c67721c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277817119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.4277817119
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2647679593
Short name T96
Test name
Test status
Simulation time 48719950623 ps
CPU time 97.26 seconds
Started Jun 22 04:50:01 PM PDT 24
Finished Jun 22 04:51:39 PM PDT 24
Peak memory 207288 kb
Host smart-c5223510-39fa-43b8-a1f7-243e405676f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647679593 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2647679593
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2470236699
Short name T153
Test name
Test status
Simulation time 447048058 ps
CPU time 0.71 seconds
Started Jun 22 04:49:58 PM PDT 24
Finished Jun 22 04:50:00 PM PDT 24
Peak memory 197156 kb
Host smart-394f6271-fbf0-49a3-ae00-8d3f090da249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470236699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2470236699
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2044748917
Short name T126
Test name
Test status
Simulation time 55537783324 ps
CPU time 76.51 seconds
Started Jun 22 04:49:57 PM PDT 24
Finished Jun 22 04:51:14 PM PDT 24
Peak memory 192956 kb
Host smart-f1301a5f-a9a8-42b0-b6b4-5f30f39b5fe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044748917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2044748917
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2204431829
Short name T151
Test name
Test status
Simulation time 555236259 ps
CPU time 0.84 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:50:11 PM PDT 24
Peak memory 197312 kb
Host smart-daf353b7-f9cb-4c3f-af08-86891cf93421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204431829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2204431829
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1747377060
Short name T30
Test name
Test status
Simulation time 132302507409 ps
CPU time 42.61 seconds
Started Jun 22 04:50:18 PM PDT 24
Finished Jun 22 04:51:02 PM PDT 24
Peak memory 193504 kb
Host smart-8d281505-e333-430e-b5ef-eef4eb1fc48a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747377060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1747377060
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2321208406
Short name T99
Test name
Test status
Simulation time 75193810132 ps
CPU time 209.94 seconds
Started Jun 22 04:49:53 PM PDT 24
Finished Jun 22 04:53:24 PM PDT 24
Peak memory 208540 kb
Host smart-37a35e3c-cfb7-40bd-90a5-7665b8362ba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321208406 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2321208406
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2263668602
Short name T145
Test name
Test status
Simulation time 457396971 ps
CPU time 1.12 seconds
Started Jun 22 04:50:20 PM PDT 24
Finished Jun 22 04:50:22 PM PDT 24
Peak memory 197000 kb
Host smart-99d8ab80-19a2-4bad-baaf-f1d2dbe36cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263668602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2263668602
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2332321710
Short name T93
Test name
Test status
Simulation time 23601896620 ps
CPU time 223.96 seconds
Started Jun 22 04:50:17 PM PDT 24
Finished Jun 22 04:54:02 PM PDT 24
Peak memory 199524 kb
Host smart-d5d998f5-b76d-47f8-89de-05746ca7a058
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332321710 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2332321710
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.50703269
Short name T160
Test name
Test status
Simulation time 38871235360 ps
CPU time 50.76 seconds
Started Jun 22 04:50:34 PM PDT 24
Finished Jun 22 04:51:25 PM PDT 24
Peak memory 192396 kb
Host smart-46048715-174c-4b31-b7f4-1d7d2bbcaeab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50703269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_al
l.50703269
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2618551321
Short name T128
Test name
Test status
Simulation time 476102701 ps
CPU time 1.31 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:50:05 PM PDT 24
Peak memory 197116 kb
Host smart-a4523d45-582a-425c-b376-a6d0822482ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618551321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2618551321
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3048890869
Short name T171
Test name
Test status
Simulation time 281554529517 ps
CPU time 69.82 seconds
Started Jun 22 04:49:53 PM PDT 24
Finished Jun 22 04:51:05 PM PDT 24
Peak memory 193392 kb
Host smart-f57a2aa7-e16a-4bf9-bfd0-d8e07ccf7456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048890869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3048890869
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1896045409
Short name T33
Test name
Test status
Simulation time 11969024279 ps
CPU time 74.33 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:51:23 PM PDT 24
Peak memory 199036 kb
Host smart-579da350-f61f-4978-8d3a-b45561c7f0f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896045409 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1896045409
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3290652668
Short name T14
Test name
Test status
Simulation time 545349567 ps
CPU time 1.41 seconds
Started Jun 22 04:50:18 PM PDT 24
Finished Jun 22 04:50:21 PM PDT 24
Peak memory 196988 kb
Host smart-8620665a-9488-4288-88c4-087bf98e7d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290652668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3290652668
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2050879206
Short name T90
Test name
Test status
Simulation time 92971482519 ps
CPU time 784.68 seconds
Started Jun 22 04:50:17 PM PDT 24
Finished Jun 22 05:03:22 PM PDT 24
Peak memory 215524 kb
Host smart-88c2b489-800c-475c-972c-4459b104fa43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050879206 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2050879206
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3041535609
Short name T135
Test name
Test status
Simulation time 541466293 ps
CPU time 1.29 seconds
Started Jun 22 04:50:24 PM PDT 24
Finished Jun 22 04:50:26 PM PDT 24
Peak memory 197036 kb
Host smart-d72b843a-144b-4502-8722-6d160f4c5aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041535609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3041535609
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.301326203
Short name T32
Test name
Test status
Simulation time 376344049 ps
CPU time 0.72 seconds
Started Jun 22 04:50:27 PM PDT 24
Finished Jun 22 04:50:29 PM PDT 24
Peak memory 196964 kb
Host smart-703b8717-c819-42cc-90c4-1965b7f8d43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301326203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.301326203
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2254337093
Short name T109
Test name
Test status
Simulation time 570144991 ps
CPU time 1.32 seconds
Started Jun 22 04:49:59 PM PDT 24
Finished Jun 22 04:50:01 PM PDT 24
Peak memory 197008 kb
Host smart-26beeee5-605d-4951-aa1a-5a2e5f0b0f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254337093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2254337093
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3624412719
Short name T47
Test name
Test status
Simulation time 62640021445 ps
CPU time 300.76 seconds
Started Jun 22 04:50:04 PM PDT 24
Finished Jun 22 04:55:05 PM PDT 24
Peak memory 208392 kb
Host smart-9c67f54d-4181-451d-9317-0ef5b1f045b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624412719 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3624412719
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.4174140235
Short name T111
Test name
Test status
Simulation time 238759819128 ps
CPU time 241.52 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:54:03 PM PDT 24
Peak memory 192416 kb
Host smart-9407a491-6d59-4284-bbd9-8554ea4d2bdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174140235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.4174140235
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.968230342
Short name T5
Test name
Test status
Simulation time 70044127734 ps
CPU time 586.78 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:59:57 PM PDT 24
Peak memory 204220 kb
Host smart-c909af48-6457-40b6-bf94-0b118e27b05f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968230342 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.968230342
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3440881924
Short name T51
Test name
Test status
Simulation time 498128693 ps
CPU time 0.7 seconds
Started Jun 22 04:50:07 PM PDT 24
Finished Jun 22 04:50:08 PM PDT 24
Peak memory 197180 kb
Host smart-0bf991c8-8920-4c02-9ed0-e0cda6600e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440881924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3440881924
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2355630656
Short name T11
Test name
Test status
Simulation time 453854207 ps
CPU time 0.66 seconds
Started Jun 22 04:50:24 PM PDT 24
Finished Jun 22 04:50:25 PM PDT 24
Peak memory 197044 kb
Host smart-2e7bd53b-44a2-4d01-a63e-4aad2933c114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355630656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2355630656
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2670366625
Short name T56
Test name
Test status
Simulation time 571535203 ps
CPU time 0.7 seconds
Started Jun 22 04:50:26 PM PDT 24
Finished Jun 22 04:50:28 PM PDT 24
Peak memory 196940 kb
Host smart-f8f45031-7bf1-40a4-9fa1-fd7e3185ffe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670366625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2670366625
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1433241474
Short name T144
Test name
Test status
Simulation time 575702160 ps
CPU time 0.81 seconds
Started Jun 22 04:50:28 PM PDT 24
Finished Jun 22 04:50:30 PM PDT 24
Peak memory 197056 kb
Host smart-40f6683d-e244-4dbe-ab12-c1f1336f67d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433241474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1433241474
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2006052971
Short name T162
Test name
Test status
Simulation time 508039394 ps
CPU time 1.29 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:50:02 PM PDT 24
Peak memory 197012 kb
Host smart-dd0944ad-c53a-4992-b292-99e78348e71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006052971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2006052971
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3408965839
Short name T12
Test name
Test status
Simulation time 478594412 ps
CPU time 0.76 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:50:11 PM PDT 24
Peak memory 197020 kb
Host smart-cdac2bdf-2bf6-4aea-a749-be1a912ca0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408965839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3408965839
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2814973562
Short name T138
Test name
Test status
Simulation time 477172569 ps
CPU time 0.77 seconds
Started Jun 22 04:50:19 PM PDT 24
Finished Jun 22 04:50:21 PM PDT 24
Peak memory 197064 kb
Host smart-105abc64-2755-4f56-abda-13070acf5fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814973562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2814973562
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2929539076
Short name T114
Test name
Test status
Simulation time 101361390060 ps
CPU time 128.44 seconds
Started Jun 22 04:50:23 PM PDT 24
Finished Jun 22 04:52:32 PM PDT 24
Peak memory 193448 kb
Host smart-bd0f7518-c49b-43c7-850c-fe918de87fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929539076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2929539076
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.833006612
Short name T117
Test name
Test status
Simulation time 409282410 ps
CPU time 0.83 seconds
Started Jun 22 04:50:27 PM PDT 24
Finished Jun 22 04:50:29 PM PDT 24
Peak memory 197088 kb
Host smart-5ea2fa46-f5fb-4fd8-882d-b499b6d1d7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833006612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.833006612
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2862846670
Short name T23
Test name
Test status
Simulation time 407969488 ps
CPU time 0.69 seconds
Started Jun 22 04:49:52 PM PDT 24
Finished Jun 22 04:49:54 PM PDT 24
Peak memory 197108 kb
Host smart-d04cc763-6fa1-463d-b4b8-b760cc424215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862846670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2862846670
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.957886167
Short name T58
Test name
Test status
Simulation time 404206364 ps
CPU time 1.23 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:50:11 PM PDT 24
Peak memory 197172 kb
Host smart-3aaf1b9e-b37f-485d-a029-eb5edb20e390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957886167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.957886167
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3347971366
Short name T18
Test name
Test status
Simulation time 160216415802 ps
CPU time 55.14 seconds
Started Jun 22 04:50:07 PM PDT 24
Finished Jun 22 04:51:03 PM PDT 24
Peak memory 193416 kb
Host smart-6744bca4-b0c6-4b15-bc12-26f7c01a4bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347971366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3347971366
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3094417905
Short name T176
Test name
Test status
Simulation time 80588592403 ps
CPU time 24.73 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:50:35 PM PDT 24
Peak memory 193432 kb
Host smart-aa541946-3635-49dd-adca-dfdf105e1679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094417905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3094417905
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.335185215
Short name T13
Test name
Test status
Simulation time 20093273589 ps
CPU time 182.83 seconds
Started Jun 22 04:50:23 PM PDT 24
Finished Jun 22 04:53:26 PM PDT 24
Peak memory 207312 kb
Host smart-4a2e145c-08c1-4adc-a1c8-32744286253a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335185215 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.335185215
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1110459816
Short name T63
Test name
Test status
Simulation time 419113448 ps
CPU time 0.86 seconds
Started Jun 22 04:50:20 PM PDT 24
Finished Jun 22 04:50:22 PM PDT 24
Peak memory 197076 kb
Host smart-6e245428-929a-417f-8dfa-3cbcbbb69ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110459816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1110459816
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1518786250
Short name T154
Test name
Test status
Simulation time 33316538818 ps
CPU time 269.82 seconds
Started Jun 22 04:50:28 PM PDT 24
Finished Jun 22 04:54:59 PM PDT 24
Peak memory 207260 kb
Host smart-856de6c8-5bf7-4f58-9199-e5e5100ec549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518786250 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1518786250
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1409271895
Short name T113
Test name
Test status
Simulation time 546475208 ps
CPU time 1.42 seconds
Started Jun 22 04:50:26 PM PDT 24
Finished Jun 22 04:50:28 PM PDT 24
Peak memory 197080 kb
Host smart-198652a4-f0f0-46e4-a794-845f9ff2c596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409271895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1409271895
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1137422568
Short name T165
Test name
Test status
Simulation time 348616599210 ps
CPU time 501.52 seconds
Started Jun 22 04:50:30 PM PDT 24
Finished Jun 22 04:58:52 PM PDT 24
Peak memory 192388 kb
Host smart-ab1e3a5b-ebef-4327-bcc1-4837eb7c8b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137422568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1137422568
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3278242020
Short name T181
Test name
Test status
Simulation time 69919914729 ps
CPU time 197.62 seconds
Started Jun 22 04:50:31 PM PDT 24
Finished Jun 22 04:53:50 PM PDT 24
Peak memory 214796 kb
Host smart-844251d7-94f1-4cc1-b30d-8fa65502a1c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278242020 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3278242020
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2569747046
Short name T195
Test name
Test status
Simulation time 8191033276 ps
CPU time 13.34 seconds
Started Jun 22 04:43:30 PM PDT 24
Finished Jun 22 04:43:44 PM PDT 24
Peak memory 197876 kb
Host smart-3f812221-e73b-492d-a699-43772e565232
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569747046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2569747046
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1062651830
Short name T177
Test name
Test status
Simulation time 411840198 ps
CPU time 1.15 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:50:02 PM PDT 24
Peak memory 197040 kb
Host smart-d19dbf77-4b7d-4ad6-abb6-a0b49a4ebb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062651830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1062651830
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1639306235
Short name T84
Test name
Test status
Simulation time 474495578 ps
CPU time 0.88 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:50:11 PM PDT 24
Peak memory 197044 kb
Host smart-77c3a86d-9a44-4b89-a579-7951f9a78ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639306235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1639306235
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.871278692
Short name T157
Test name
Test status
Simulation time 495458707 ps
CPU time 0.76 seconds
Started Jun 22 04:50:11 PM PDT 24
Finished Jun 22 04:50:12 PM PDT 24
Peak memory 197024 kb
Host smart-b9a63fac-c877-47e4-a620-a1e2cfa9300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871278692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.871278692
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.702475124
Short name T149
Test name
Test status
Simulation time 351701120 ps
CPU time 1.13 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:50:11 PM PDT 24
Peak memory 197056 kb
Host smart-fe1ca4c0-25a6-48a7-a8ec-294015241455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702475124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.702475124
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1419905861
Short name T186
Test name
Test status
Simulation time 599006585 ps
CPU time 0.83 seconds
Started Jun 22 04:50:10 PM PDT 24
Finished Jun 22 04:50:12 PM PDT 24
Peak memory 197000 kb
Host smart-1edc96dd-03ef-409d-aefb-9f544e9ab516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419905861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1419905861
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.4117868305
Short name T172
Test name
Test status
Simulation time 391197735 ps
CPU time 1.22 seconds
Started Jun 22 04:50:18 PM PDT 24
Finished Jun 22 04:50:20 PM PDT 24
Peak memory 196960 kb
Host smart-e42f082b-64b1-46a6-8829-6250d26561f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117868305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.4117868305
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2394201548
Short name T139
Test name
Test status
Simulation time 569287026 ps
CPU time 1.36 seconds
Started Jun 22 04:50:36 PM PDT 24
Finished Jun 22 04:50:39 PM PDT 24
Peak memory 197040 kb
Host smart-d6267ff2-2c83-4f26-a6e9-09882488cd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394201548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2394201548
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1798270773
Short name T119
Test name
Test status
Simulation time 167849285464 ps
CPU time 232.19 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:53:54 PM PDT 24
Peak memory 198668 kb
Host smart-8d820e03-1fb2-4700-97e0-065ce56deb3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798270773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1798270773
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2343031135
Short name T9
Test name
Test status
Simulation time 469210145 ps
CPU time 0.79 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:50:05 PM PDT 24
Peak memory 197084 kb
Host smart-a67abdee-80fd-4b8a-b031-438b2c7c8a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343031135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2343031135
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1916572269
Short name T159
Test name
Test status
Simulation time 471677499 ps
CPU time 1.27 seconds
Started Jun 22 04:50:20 PM PDT 24
Finished Jun 22 04:50:23 PM PDT 24
Peak memory 197064 kb
Host smart-a5674a75-2492-4eff-ad91-987ac45e8b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916572269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1916572269
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2674420224
Short name T175
Test name
Test status
Simulation time 562229218 ps
CPU time 0.76 seconds
Started Jun 22 04:50:16 PM PDT 24
Finished Jun 22 04:50:18 PM PDT 24
Peak memory 197036 kb
Host smart-83244c9c-cef4-4668-a2c4-6a13e3a02eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674420224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2674420224
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1819951106
Short name T59
Test name
Test status
Simulation time 641046859 ps
CPU time 0.96 seconds
Started Jun 22 04:50:20 PM PDT 24
Finished Jun 22 04:50:22 PM PDT 24
Peak memory 197036 kb
Host smart-56c20a89-1109-49d4-ada8-450059193a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819951106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1819951106
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1291629811
Short name T187
Test name
Test status
Simulation time 625519376 ps
CPU time 0.82 seconds
Started Jun 22 04:50:23 PM PDT 24
Finished Jun 22 04:50:24 PM PDT 24
Peak memory 197384 kb
Host smart-379f3161-d665-4e90-9cd9-5fa7746f31c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291629811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1291629811
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.383828725
Short name T137
Test name
Test status
Simulation time 582529147 ps
CPU time 0.99 seconds
Started Jun 22 04:50:17 PM PDT 24
Finished Jun 22 04:50:19 PM PDT 24
Peak memory 197176 kb
Host smart-d78e4937-24d1-48e2-97a6-5f084767cb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383828725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.383828725
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2371472963
Short name T168
Test name
Test status
Simulation time 456802009 ps
CPU time 1.33 seconds
Started Jun 22 04:50:25 PM PDT 24
Finished Jun 22 04:50:28 PM PDT 24
Peak memory 197140 kb
Host smart-b6d4fbbe-5304-428c-bfa6-c19dcfdd7e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371472963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2371472963
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1789507385
Short name T180
Test name
Test status
Simulation time 484238216 ps
CPU time 0.76 seconds
Started Jun 22 04:50:27 PM PDT 24
Finished Jun 22 04:50:29 PM PDT 24
Peak memory 197388 kb
Host smart-77c454f0-79a3-4a7f-8f31-78cbda22195a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789507385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1789507385
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3271284630
Short name T60
Test name
Test status
Simulation time 524272059 ps
CPU time 0.8 seconds
Started Jun 22 04:50:04 PM PDT 24
Finished Jun 22 04:50:05 PM PDT 24
Peak memory 196984 kb
Host smart-5eabb050-abe3-4e9e-b723-278a023fd2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271284630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3271284630
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4294497969
Short name T22
Test name
Test status
Simulation time 322523679175 ps
CPU time 772.41 seconds
Started Jun 22 04:50:26 PM PDT 24
Finished Jun 22 05:03:19 PM PDT 24
Peak memory 215484 kb
Host smart-831693be-fb7d-4f2b-8d04-117d57837d4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294497969 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.4294497969
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.474145490
Short name T122
Test name
Test status
Simulation time 522174078 ps
CPU time 0.9 seconds
Started Jun 22 04:50:31 PM PDT 24
Finished Jun 22 04:50:32 PM PDT 24
Peak memory 197084 kb
Host smart-ffe367a1-0a40-4394-adf8-3fa52995d14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474145490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.474145490
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3017509467
Short name T167
Test name
Test status
Simulation time 388744353 ps
CPU time 1.06 seconds
Started Jun 22 04:50:37 PM PDT 24
Finished Jun 22 04:50:39 PM PDT 24
Peak memory 197152 kb
Host smart-8b31c4b4-ed95-4212-aef9-f70bb56c609c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017509467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3017509467
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2621016011
Short name T182
Test name
Test status
Simulation time 511066678 ps
CPU time 0.8 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:50:02 PM PDT 24
Peak memory 197052 kb
Host smart-9421f72a-847e-4032-9af1-b0b0f12f1520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621016011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2621016011
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4267144311
Short name T193
Test name
Test status
Simulation time 8071526489 ps
CPU time 12.84 seconds
Started Jun 22 04:42:32 PM PDT 24
Finished Jun 22 04:42:45 PM PDT 24
Peak memory 197960 kb
Host smart-86e17c6f-329a-4366-beb7-94da8b8820ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267144311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.4267144311
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.630055800
Short name T173
Test name
Test status
Simulation time 335237567390 ps
CPU time 248.98 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:54:10 PM PDT 24
Peak memory 193368 kb
Host smart-08134ec2-0dd1-4bcb-976c-f17526776a12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630055800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.630055800
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.692992754
Short name T125
Test name
Test status
Simulation time 399462981 ps
CPU time 0.79 seconds
Started Jun 22 04:49:59 PM PDT 24
Finished Jun 22 04:50:01 PM PDT 24
Peak memory 197092 kb
Host smart-23d4c2fa-7252-49fe-96f8-4fe0347f7523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692992754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.692992754
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1834345527
Short name T83
Test name
Test status
Simulation time 29833903780 ps
CPU time 9.46 seconds
Started Jun 22 04:50:17 PM PDT 24
Finished Jun 22 04:50:27 PM PDT 24
Peak memory 198760 kb
Host smart-77861d09-b84d-4493-a8c9-4c2b21592851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834345527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1834345527
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1601679591
Short name T188
Test name
Test status
Simulation time 588623713 ps
CPU time 1.54 seconds
Started Jun 22 04:50:37 PM PDT 24
Finished Jun 22 04:50:39 PM PDT 24
Peak memory 197140 kb
Host smart-5638cd8c-07f0-4ad1-b14a-1e137ef4d21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601679591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1601679591
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.534572753
Short name T178
Test name
Test status
Simulation time 469035119 ps
CPU time 1.32 seconds
Started Jun 22 04:49:59 PM PDT 24
Finished Jun 22 04:50:01 PM PDT 24
Peak memory 197060 kb
Host smart-4864cd35-257f-495d-a019-7b5c71b02b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534572753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.534572753
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1639188603
Short name T405
Test name
Test status
Simulation time 402966009 ps
CPU time 0.93 seconds
Started Jun 22 04:42:40 PM PDT 24
Finished Jun 22 04:42:42 PM PDT 24
Peak memory 192956 kb
Host smart-dd340f1e-86bb-428d-82a5-3477c9d4501b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639188603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1639188603
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1601573440
Short name T72
Test name
Test status
Simulation time 6740449929 ps
CPU time 8.16 seconds
Started Jun 22 04:42:33 PM PDT 24
Finished Jun 22 04:42:42 PM PDT 24
Peak memory 191992 kb
Host smart-39dd6e16-6912-404c-b02e-653975946fcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601573440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1601573440
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4055355378
Short name T337
Test name
Test status
Simulation time 866926202 ps
CPU time 1.76 seconds
Started Jun 22 04:42:32 PM PDT 24
Finished Jun 22 04:42:34 PM PDT 24
Peak memory 183488 kb
Host smart-c0a433eb-345d-4290-b1f4-8ee9c0ac8052
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055355378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.4055355378
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3962000166
Short name T37
Test name
Test status
Simulation time 591040237 ps
CPU time 0.81 seconds
Started Jun 22 04:42:38 PM PDT 24
Finished Jun 22 04:42:39 PM PDT 24
Peak memory 196372 kb
Host smart-a86cb52a-5c3f-49df-9952-901d2f5b7a9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962000166 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3962000166
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.33133439
Short name T73
Test name
Test status
Simulation time 527698241 ps
CPU time 0.78 seconds
Started Jun 22 04:42:31 PM PDT 24
Finished Jun 22 04:42:32 PM PDT 24
Peak memory 192852 kb
Host smart-71a94088-8e9b-4d2b-9da0-1dedd7875b5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33133439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.33133439
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.483759164
Short name T280
Test name
Test status
Simulation time 328812187 ps
CPU time 0.92 seconds
Started Jun 22 04:42:33 PM PDT 24
Finished Jun 22 04:42:35 PM PDT 24
Peak memory 183464 kb
Host smart-29781455-5830-4277-bccd-9dfc1c7a5d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483759164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.483759164
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3784718170
Short name T317
Test name
Test status
Simulation time 279918359 ps
CPU time 0.92 seconds
Started Jun 22 04:42:32 PM PDT 24
Finished Jun 22 04:42:34 PM PDT 24
Peak memory 183516 kb
Host smart-58b4e37a-14fb-43f4-bedf-f89fe54aaa4f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784718170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3784718170
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.250978919
Short name T309
Test name
Test status
Simulation time 494240949 ps
CPU time 0.67 seconds
Started Jun 22 04:42:32 PM PDT 24
Finished Jun 22 04:42:33 PM PDT 24
Peak memory 183476 kb
Host smart-b370b7ef-5832-4834-b987-c5fa7e544e6d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250978919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.250978919
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1582350554
Short name T395
Test name
Test status
Simulation time 1241894695 ps
CPU time 2.14 seconds
Started Jun 22 04:42:37 PM PDT 24
Finished Jun 22 04:42:40 PM PDT 24
Peak memory 193252 kb
Host smart-4b3805aa-2a80-40d9-890c-7703fa463acf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582350554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1582350554
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3061167905
Short name T284
Test name
Test status
Simulation time 444103148 ps
CPU time 2.86 seconds
Started Jun 22 04:42:30 PM PDT 24
Finished Jun 22 04:42:34 PM PDT 24
Peak memory 198452 kb
Host smart-5eb37de2-59c4-4494-a135-9f5022eba624
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061167905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3061167905
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1330655488
Short name T69
Test name
Test status
Simulation time 499935168 ps
CPU time 1.02 seconds
Started Jun 22 04:42:45 PM PDT 24
Finished Jun 22 04:42:46 PM PDT 24
Peak memory 194968 kb
Host smart-c628b556-28ea-43e2-b015-838fbf15b015
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330655488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1330655488
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2469248612
Short name T410
Test name
Test status
Simulation time 7078803228 ps
CPU time 16.12 seconds
Started Jun 22 04:42:45 PM PDT 24
Finished Jun 22 04:43:02 PM PDT 24
Peak memory 191952 kb
Host smart-b74163fd-e896-4665-9f6b-f9c2a42630d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469248612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2469248612
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1419892258
Short name T74
Test name
Test status
Simulation time 1095759913 ps
CPU time 2.03 seconds
Started Jun 22 04:42:39 PM PDT 24
Finished Jun 22 04:42:42 PM PDT 24
Peak memory 192764 kb
Host smart-65b8da3b-3b29-4a89-aa09-cef63dd85bf7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419892258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1419892258
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3755759374
Short name T358
Test name
Test status
Simulation time 339948638 ps
CPU time 0.81 seconds
Started Jun 22 04:42:47 PM PDT 24
Finished Jun 22 04:42:48 PM PDT 24
Peak memory 195140 kb
Host smart-f9b6c2a9-9e35-4bd2-96e5-7886f5840ce5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755759374 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3755759374
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1031980139
Short name T416
Test name
Test status
Simulation time 544407911 ps
CPU time 0.97 seconds
Started Jun 22 04:42:44 PM PDT 24
Finished Jun 22 04:42:46 PM PDT 24
Peak memory 193040 kb
Host smart-d2bcf8c8-5628-4c01-997e-77c07ed6ad0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031980139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1031980139
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3485496217
Short name T374
Test name
Test status
Simulation time 424043012 ps
CPU time 0.85 seconds
Started Jun 22 04:42:37 PM PDT 24
Finished Jun 22 04:42:38 PM PDT 24
Peak memory 192768 kb
Host smart-504bc576-f6fc-4fde-b985-c6ae770ab6bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485496217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3485496217
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.27440041
Short name T319
Test name
Test status
Simulation time 375204421 ps
CPU time 0.88 seconds
Started Jun 22 04:42:37 PM PDT 24
Finished Jun 22 04:42:39 PM PDT 24
Peak memory 183424 kb
Host smart-20bf5666-8090-492e-8713-c921a1286638
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27440041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim
er_mem_partial_access.27440041
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2371961975
Short name T336
Test name
Test status
Simulation time 433876203 ps
CPU time 0.66 seconds
Started Jun 22 04:42:38 PM PDT 24
Finished Jun 22 04:42:40 PM PDT 24
Peak memory 183588 kb
Host smart-6b83386b-72d2-4927-980e-e32d7b9be231
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371961975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2371961975
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4197602807
Short name T81
Test name
Test status
Simulation time 2295597409 ps
CPU time 1.34 seconds
Started Jun 22 04:42:45 PM PDT 24
Finished Jun 22 04:42:47 PM PDT 24
Peak memory 195124 kb
Host smart-c8ee5e8f-7766-4fa1-b3d6-aa1957abec52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197602807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.4197602807
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4262873102
Short name T381
Test name
Test status
Simulation time 682313503 ps
CPU time 1.26 seconds
Started Jun 22 04:42:38 PM PDT 24
Finished Jun 22 04:42:40 PM PDT 24
Peak memory 198340 kb
Host smart-1046f87b-6682-44d6-ba5b-a95db29ee82a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262873102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.4262873102
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3879356533
Short name T38
Test name
Test status
Simulation time 3748632081 ps
CPU time 2.31 seconds
Started Jun 22 04:42:39 PM PDT 24
Finished Jun 22 04:42:42 PM PDT 24
Peak memory 197784 kb
Host smart-b1408b97-d61c-4e2c-9b5a-ad466be68d84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879356533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3879356533
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1137435573
Short name T325
Test name
Test status
Simulation time 411738245 ps
CPU time 1.29 seconds
Started Jun 22 04:43:21 PM PDT 24
Finished Jun 22 04:43:22 PM PDT 24
Peak memory 196252 kb
Host smart-04a4e96a-e168-4503-82b0-46fa54986e78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137435573 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1137435573
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3177725842
Short name T343
Test name
Test status
Simulation time 430565834 ps
CPU time 0.73 seconds
Started Jun 22 04:43:24 PM PDT 24
Finished Jun 22 04:43:25 PM PDT 24
Peak memory 191944 kb
Host smart-9911dfd8-5feb-40db-889f-63bccc735e48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177725842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3177725842
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.723193581
Short name T286
Test name
Test status
Simulation time 416915296 ps
CPU time 0.83 seconds
Started Jun 22 04:43:20 PM PDT 24
Finished Jun 22 04:43:21 PM PDT 24
Peak memory 192668 kb
Host smart-66ae7236-2a28-4049-94d2-0ade6ab00818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723193581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.723193581
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3188259007
Short name T35
Test name
Test status
Simulation time 2218828994 ps
CPU time 2.54 seconds
Started Jun 22 04:43:21 PM PDT 24
Finished Jun 22 04:43:25 PM PDT 24
Peak memory 194944 kb
Host smart-feb8c0cc-9c22-4881-94c6-4a09f881a18a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188259007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3188259007
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2933810935
Short name T375
Test name
Test status
Simulation time 844839659 ps
CPU time 2.04 seconds
Started Jun 22 04:43:23 PM PDT 24
Finished Jun 22 04:43:26 PM PDT 24
Peak memory 198440 kb
Host smart-abad36ab-b64c-46d6-98ed-7f8b8878d486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933810935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2933810935
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1681050259
Short name T400
Test name
Test status
Simulation time 8404164645 ps
CPU time 13.4 seconds
Started Jun 22 04:43:21 PM PDT 24
Finished Jun 22 04:43:35 PM PDT 24
Peak memory 198288 kb
Host smart-3abe71ea-9029-4531-ae2b-d86787c6688c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681050259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1681050259
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1237154987
Short name T315
Test name
Test status
Simulation time 424560064 ps
CPU time 1.33 seconds
Started Jun 22 04:43:21 PM PDT 24
Finished Jun 22 04:43:24 PM PDT 24
Peak memory 196520 kb
Host smart-88615335-b764-422b-be60-8bacb8ec85a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237154987 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1237154987
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2253856454
Short name T397
Test name
Test status
Simulation time 482551630 ps
CPU time 0.78 seconds
Started Jun 22 04:43:25 PM PDT 24
Finished Jun 22 04:43:27 PM PDT 24
Peak memory 192776 kb
Host smart-2db49897-b5e1-4e72-b0eb-dc83f6dac19c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253856454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2253856454
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1148418753
Short name T306
Test name
Test status
Simulation time 359277848 ps
CPU time 0.68 seconds
Started Jun 22 04:43:22 PM PDT 24
Finished Jun 22 04:43:23 PM PDT 24
Peak memory 183660 kb
Host smart-4490112e-f37a-4c30-9dc6-7ef6b3f1dace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148418753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1148418753
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4225456834
Short name T361
Test name
Test status
Simulation time 2758141271 ps
CPU time 1.3 seconds
Started Jun 22 04:43:22 PM PDT 24
Finished Jun 22 04:43:24 PM PDT 24
Peak memory 194952 kb
Host smart-148a1610-2de6-4b6e-99f1-4fadd8616110
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225456834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.4225456834
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2544955040
Short name T352
Test name
Test status
Simulation time 570555982 ps
CPU time 2.55 seconds
Started Jun 22 04:43:21 PM PDT 24
Finished Jun 22 04:43:25 PM PDT 24
Peak memory 198756 kb
Host smart-9169b013-32fb-416d-99da-53a42107f2d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544955040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2544955040
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3028675710
Short name T302
Test name
Test status
Simulation time 4617952784 ps
CPU time 1.48 seconds
Started Jun 22 04:43:23 PM PDT 24
Finished Jun 22 04:43:25 PM PDT 24
Peak memory 197680 kb
Host smart-fda02723-b9bd-40f4-b211-53388b318f04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028675710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3028675710
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3081410428
Short name T360
Test name
Test status
Simulation time 614312491 ps
CPU time 0.97 seconds
Started Jun 22 04:43:24 PM PDT 24
Finished Jun 22 04:43:25 PM PDT 24
Peak memory 198256 kb
Host smart-4538212d-4ba9-44d2-89a6-0d1a11a643d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081410428 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3081410428
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1031193724
Short name T347
Test name
Test status
Simulation time 525436065 ps
CPU time 0.96 seconds
Started Jun 22 04:43:21 PM PDT 24
Finished Jun 22 04:43:23 PM PDT 24
Peak memory 192860 kb
Host smart-a8361437-5e61-4932-8fb0-d2bcc440ff0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031193724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1031193724
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2081328447
Short name T394
Test name
Test status
Simulation time 473732402 ps
CPU time 0.67 seconds
Started Jun 22 04:43:21 PM PDT 24
Finished Jun 22 04:43:23 PM PDT 24
Peak memory 183668 kb
Host smart-5fb86dcf-acb2-4d10-98cb-592c4da8c67c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081328447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2081328447
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1850866000
Short name T75
Test name
Test status
Simulation time 2365309342 ps
CPU time 3.3 seconds
Started Jun 22 04:43:23 PM PDT 24
Finished Jun 22 04:43:27 PM PDT 24
Peak memory 194044 kb
Host smart-3b02b1be-dde5-43c6-9eb2-c932eaa01fc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850866000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1850866000
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3760572515
Short name T411
Test name
Test status
Simulation time 444821016 ps
CPU time 2.07 seconds
Started Jun 22 04:43:21 PM PDT 24
Finished Jun 22 04:43:24 PM PDT 24
Peak memory 198524 kb
Host smart-757b8597-2861-40bf-bef8-ee4dbc6839a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760572515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3760572515
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3854943980
Short name T355
Test name
Test status
Simulation time 4076120558 ps
CPU time 3.51 seconds
Started Jun 22 04:43:22 PM PDT 24
Finished Jun 22 04:43:26 PM PDT 24
Peak memory 197612 kb
Host smart-2b1a3945-3a3f-484e-871a-634042087758
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854943980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3854943980
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.917545982
Short name T339
Test name
Test status
Simulation time 427397417 ps
CPU time 0.7 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:31 PM PDT 24
Peak memory 195076 kb
Host smart-5f155461-e14b-4c57-aca3-8a2c4cc883c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917545982 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.917545982
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1680197934
Short name T398
Test name
Test status
Simulation time 413430112 ps
CPU time 0.84 seconds
Started Jun 22 04:43:30 PM PDT 24
Finished Jun 22 04:43:31 PM PDT 24
Peak memory 192984 kb
Host smart-0e7d150c-de72-4a81-bdbc-f43dbcdc09bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680197934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1680197934
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2393262575
Short name T385
Test name
Test status
Simulation time 474075879 ps
CPU time 0.85 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:30 PM PDT 24
Peak memory 183592 kb
Host smart-7f74e3b1-ca6e-463a-b054-ea73927ec577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393262575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2393262575
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1759154981
Short name T409
Test name
Test status
Simulation time 1202474842 ps
CPU time 0.99 seconds
Started Jun 22 04:43:32 PM PDT 24
Finished Jun 22 04:43:33 PM PDT 24
Peak memory 193384 kb
Host smart-a67e66ee-7e1b-4364-a157-52562fce6574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759154981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1759154981
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.672341830
Short name T320
Test name
Test status
Simulation time 490651598 ps
CPU time 1.84 seconds
Started Jun 22 04:43:21 PM PDT 24
Finished Jun 22 04:43:23 PM PDT 24
Peak memory 198476 kb
Host smart-5263525f-a8b2-4e26-896c-e9a4f95200f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672341830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.672341830
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.603345423
Short name T342
Test name
Test status
Simulation time 3843098565 ps
CPU time 2.27 seconds
Started Jun 22 04:43:30 PM PDT 24
Finished Jun 22 04:43:33 PM PDT 24
Peak memory 196480 kb
Host smart-9fd2d087-36a2-4355-bde5-00ca3c5d8667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603345423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.603345423
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2676266543
Short name T291
Test name
Test status
Simulation time 387129136 ps
CPU time 1.14 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:31 PM PDT 24
Peak memory 195328 kb
Host smart-9161f0be-9b56-41f5-8682-02e288bedc9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676266543 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2676266543
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2244870534
Short name T373
Test name
Test status
Simulation time 423608567 ps
CPU time 1.13 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:31 PM PDT 24
Peak memory 191932 kb
Host smart-a318ccdf-8b4b-4058-b588-9ffa77cf5974
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244870534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2244870534
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.71174413
Short name T285
Test name
Test status
Simulation time 286816294 ps
CPU time 0.92 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:31 PM PDT 24
Peak memory 192868 kb
Host smart-924d12de-9d4b-464b-b361-96bd94c6b890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71174413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.71174413
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.265066527
Short name T78
Test name
Test status
Simulation time 2596520013 ps
CPU time 6.3 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:37 PM PDT 24
Peak memory 195028 kb
Host smart-a75a754b-5e19-4b56-a557-96fbf4ea474f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265066527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.265066527
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1028777765
Short name T392
Test name
Test status
Simulation time 504501684 ps
CPU time 1.57 seconds
Started Jun 22 04:43:28 PM PDT 24
Finished Jun 22 04:43:30 PM PDT 24
Peak memory 198516 kb
Host smart-e14d7802-c35a-4bb7-af4b-09f0365363da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028777765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1028777765
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2317398656
Short name T300
Test name
Test status
Simulation time 556640480 ps
CPU time 1.46 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:31 PM PDT 24
Peak memory 195804 kb
Host smart-8333058a-e3dc-4c32-9b69-5798357f4bec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317398656 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2317398656
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1865203639
Short name T376
Test name
Test status
Simulation time 466843258 ps
CPU time 1.35 seconds
Started Jun 22 04:43:31 PM PDT 24
Finished Jun 22 04:43:33 PM PDT 24
Peak memory 192868 kb
Host smart-76d340db-6931-4f02-9ac8-0b7eb2f35cc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865203639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1865203639
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.477410661
Short name T368
Test name
Test status
Simulation time 377797392 ps
CPU time 0.6 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:30 PM PDT 24
Peak memory 192776 kb
Host smart-b909af41-9e49-46f2-b29c-f558ff0e71ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477410661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.477410661
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3080197411
Short name T377
Test name
Test status
Simulation time 2945595684 ps
CPU time 2.81 seconds
Started Jun 22 04:43:28 PM PDT 24
Finished Jun 22 04:43:31 PM PDT 24
Peak memory 194156 kb
Host smart-23e56820-6cdf-436b-a4d7-e841e451e02e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080197411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3080197411
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3910188425
Short name T366
Test name
Test status
Simulation time 375493724 ps
CPU time 1.32 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:31 PM PDT 24
Peak memory 198312 kb
Host smart-f43e4f67-c5af-42ce-b832-52c75d517b53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910188425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3910188425
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3667564077
Short name T190
Test name
Test status
Simulation time 8470855375 ps
CPU time 12.08 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:43 PM PDT 24
Peak memory 197888 kb
Host smart-52809ee9-6e4e-49e3-89a8-e0a55365ea6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667564077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3667564077
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3343781854
Short name T364
Test name
Test status
Simulation time 518621274 ps
CPU time 1.05 seconds
Started Jun 22 04:43:38 PM PDT 24
Finished Jun 22 04:43:40 PM PDT 24
Peak memory 196900 kb
Host smart-cf866747-21db-4f06-9058-d3e3d4684bd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343781854 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3343781854
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2422625391
Short name T68
Test name
Test status
Simulation time 376672433 ps
CPU time 1.09 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:32 PM PDT 24
Peak memory 191936 kb
Host smart-5f7df508-6aea-4f7e-ab16-5f198b95d9e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422625391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2422625391
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1114439071
Short name T294
Test name
Test status
Simulation time 346548714 ps
CPU time 0.64 seconds
Started Jun 22 04:43:31 PM PDT 24
Finished Jun 22 04:43:32 PM PDT 24
Peak memory 183552 kb
Host smart-5c971010-43c7-468e-ba2b-ea244f57aa3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114439071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1114439071
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1555581978
Short name T79
Test name
Test status
Simulation time 1561710208 ps
CPU time 1.3 seconds
Started Jun 22 04:43:36 PM PDT 24
Finished Jun 22 04:43:38 PM PDT 24
Peak memory 192836 kb
Host smart-2a506815-905f-444c-b57c-44a0a480f7d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555581978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1555581978
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.741776948
Short name T402
Test name
Test status
Simulation time 1059049439 ps
CPU time 2.14 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:32 PM PDT 24
Peak memory 198524 kb
Host smart-18cb509e-c66a-489d-83a6-8f69fb3da757
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741776948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.741776948
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3235910414
Short name T192
Test name
Test status
Simulation time 7606787406 ps
CPU time 12.66 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:43:42 PM PDT 24
Peak memory 198304 kb
Host smart-2dd9c0f0-4c88-4660-93f5-0d596628352b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235910414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3235910414
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3530436817
Short name T299
Test name
Test status
Simulation time 748228078 ps
CPU time 0.85 seconds
Started Jun 22 04:43:36 PM PDT 24
Finished Jun 22 04:43:38 PM PDT 24
Peak memory 197372 kb
Host smart-796b09a7-2d44-4d18-a46b-5808792db0a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530436817 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3530436817
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1187031408
Short name T324
Test name
Test status
Simulation time 400599409 ps
CPU time 0.67 seconds
Started Jun 22 04:43:40 PM PDT 24
Finished Jun 22 04:43:41 PM PDT 24
Peak memory 192776 kb
Host smart-2dd747c5-e5da-4d2e-9566-31cded813e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187031408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1187031408
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3210371573
Short name T345
Test name
Test status
Simulation time 413610125 ps
CPU time 1.12 seconds
Started Jun 22 04:43:37 PM PDT 24
Finished Jun 22 04:43:39 PM PDT 24
Peak memory 183496 kb
Host smart-26ad6b36-6b11-48de-a12b-9e67d8d18592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210371573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3210371573
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1572088903
Short name T357
Test name
Test status
Simulation time 2820984109 ps
CPU time 2.01 seconds
Started Jun 22 04:43:37 PM PDT 24
Finished Jun 22 04:43:39 PM PDT 24
Peak memory 194340 kb
Host smart-ff7fec0d-a364-441f-807d-56c5f8464f47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572088903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1572088903
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3353918223
Short name T388
Test name
Test status
Simulation time 516642749 ps
CPU time 1.54 seconds
Started Jun 22 04:43:37 PM PDT 24
Finished Jun 22 04:43:40 PM PDT 24
Peak memory 198380 kb
Host smart-c29cc508-39aa-470d-af00-23166c53a826
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353918223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3353918223
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1450995457
Short name T383
Test name
Test status
Simulation time 3933359079 ps
CPU time 3.7 seconds
Started Jun 22 04:43:36 PM PDT 24
Finished Jun 22 04:43:41 PM PDT 24
Peak memory 197808 kb
Host smart-9c96fc92-85cd-41e3-b421-fb23f83e6078
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450995457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1450995457
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1243501653
Short name T346
Test name
Test status
Simulation time 597822221 ps
CPU time 1.56 seconds
Started Jun 22 04:43:36 PM PDT 24
Finished Jun 22 04:43:38 PM PDT 24
Peak memory 196436 kb
Host smart-0a0c17b1-ef51-419c-88f8-d2ad6f79a310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243501653 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1243501653
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3518644747
Short name T378
Test name
Test status
Simulation time 402548595 ps
CPU time 0.72 seconds
Started Jun 22 04:43:38 PM PDT 24
Finished Jun 22 04:43:40 PM PDT 24
Peak memory 193188 kb
Host smart-b43575af-cc9b-46c3-8fb6-4a9683216d4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518644747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3518644747
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.253158453
Short name T326
Test name
Test status
Simulation time 294530015 ps
CPU time 0.74 seconds
Started Jun 22 04:43:37 PM PDT 24
Finished Jun 22 04:43:39 PM PDT 24
Peak memory 192772 kb
Host smart-c5296bcc-df39-4131-bae8-d3e4904cec9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253158453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.253158453
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2601557942
Short name T322
Test name
Test status
Simulation time 3034655145 ps
CPU time 2.52 seconds
Started Jun 22 04:43:35 PM PDT 24
Finished Jun 22 04:43:38 PM PDT 24
Peak memory 194284 kb
Host smart-8d961d43-fd29-4b03-b749-0e34eea87dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601557942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2601557942
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1203652191
Short name T379
Test name
Test status
Simulation time 687472090 ps
CPU time 1.95 seconds
Started Jun 22 04:43:39 PM PDT 24
Finished Jun 22 04:43:41 PM PDT 24
Peak memory 198416 kb
Host smart-2a670739-6589-44f2-ad6e-9abc917662b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203652191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1203652191
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.851738245
Short name T362
Test name
Test status
Simulation time 564862574 ps
CPU time 1.5 seconds
Started Jun 22 04:43:43 PM PDT 24
Finished Jun 22 04:43:46 PM PDT 24
Peak memory 195404 kb
Host smart-c7034dad-c021-4066-97eb-bf93480c8462
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851738245 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.851738245
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1322559764
Short name T41
Test name
Test status
Simulation time 453428056 ps
CPU time 0.76 seconds
Started Jun 22 04:43:36 PM PDT 24
Finished Jun 22 04:43:38 PM PDT 24
Peak memory 191936 kb
Host smart-23e6f96a-45bd-42ac-be6d-2648bee1e164
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322559764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1322559764
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3354411290
Short name T282
Test name
Test status
Simulation time 416275214 ps
CPU time 0.65 seconds
Started Jun 22 04:43:36 PM PDT 24
Finished Jun 22 04:43:38 PM PDT 24
Peak memory 183556 kb
Host smart-ba5d2d9a-673c-472c-a508-1d5278b17500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354411290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3354411290
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.299740786
Short name T354
Test name
Test status
Simulation time 2314591437 ps
CPU time 1.97 seconds
Started Jun 22 04:43:45 PM PDT 24
Finished Jun 22 04:43:48 PM PDT 24
Peak memory 194496 kb
Host smart-8604efd6-5a75-4ffa-b958-cd4b88c1e405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299740786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.299740786
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3818042155
Short name T298
Test name
Test status
Simulation time 468380042 ps
CPU time 2.16 seconds
Started Jun 22 04:43:38 PM PDT 24
Finished Jun 22 04:43:41 PM PDT 24
Peak memory 198408 kb
Host smart-222ea37c-6358-44ba-9b50-5f35cc0b04f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818042155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3818042155
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.956271197
Short name T39
Test name
Test status
Simulation time 8097604911 ps
CPU time 11.1 seconds
Started Jun 22 04:43:37 PM PDT 24
Finished Jun 22 04:43:49 PM PDT 24
Peak memory 198052 kb
Host smart-339147a9-999c-4074-9f14-f86e751882d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956271197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.956271197
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1723718255
Short name T71
Test name
Test status
Simulation time 524230785 ps
CPU time 0.77 seconds
Started Jun 22 04:42:51 PM PDT 24
Finished Jun 22 04:42:52 PM PDT 24
Peak memory 183440 kb
Host smart-ad723136-26ea-4ffa-ad9e-d3a635b05ee2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723718255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1723718255
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.707813712
Short name T307
Test name
Test status
Simulation time 13691411581 ps
CPU time 5.71 seconds
Started Jun 22 04:42:51 PM PDT 24
Finished Jun 22 04:42:58 PM PDT 24
Peak memory 196092 kb
Host smart-c720286b-2697-4382-85ff-85fa23e8b014
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707813712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.707813712
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.793334712
Short name T297
Test name
Test status
Simulation time 936323656 ps
CPU time 1.96 seconds
Started Jun 22 04:42:53 PM PDT 24
Finished Jun 22 04:42:56 PM PDT 24
Peak memory 192008 kb
Host smart-23c97f25-548e-432b-826c-33f84d95fdad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793334712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.793334712
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.36632723
Short name T413
Test name
Test status
Simulation time 347934984 ps
CPU time 1.14 seconds
Started Jun 22 04:42:51 PM PDT 24
Finished Jun 22 04:42:53 PM PDT 24
Peak memory 195716 kb
Host smart-ce77087e-14ff-4a56-a642-ba07ec09ab68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36632723 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.36632723
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.29968893
Short name T70
Test name
Test status
Simulation time 533145483 ps
CPU time 0.93 seconds
Started Jun 22 04:42:51 PM PDT 24
Finished Jun 22 04:42:52 PM PDT 24
Peak memory 193888 kb
Host smart-3234c681-0eca-42a0-b0b8-2fc24fa04d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29968893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.29968893
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2226539850
Short name T386
Test name
Test status
Simulation time 318632574 ps
CPU time 0.65 seconds
Started Jun 22 04:42:46 PM PDT 24
Finished Jun 22 04:42:47 PM PDT 24
Peak memory 183640 kb
Host smart-a70f6606-5a5f-43f1-8187-061a57531f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226539850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2226539850
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2737848884
Short name T399
Test name
Test status
Simulation time 432501139 ps
CPU time 0.65 seconds
Started Jun 22 04:42:50 PM PDT 24
Finished Jun 22 04:42:51 PM PDT 24
Peak memory 183588 kb
Host smart-925fa67c-1679-454b-a711-c3c235f2bc9a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737848884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2737848884
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2452995513
Short name T344
Test name
Test status
Simulation time 324641712 ps
CPU time 0.66 seconds
Started Jun 22 04:42:52 PM PDT 24
Finished Jun 22 04:42:53 PM PDT 24
Peak memory 183576 kb
Host smart-8279556a-f4d3-41a6-8283-2f7e90939302
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452995513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2452995513
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2074429669
Short name T356
Test name
Test status
Simulation time 2166900917 ps
CPU time 1.99 seconds
Started Jun 22 04:42:51 PM PDT 24
Finished Jun 22 04:42:54 PM PDT 24
Peak memory 193616 kb
Host smart-3ee43f13-99fd-483b-8d7a-b8ca155ff2c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074429669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2074429669
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3781736293
Short name T417
Test name
Test status
Simulation time 941121106 ps
CPU time 2.36 seconds
Started Jun 22 04:42:44 PM PDT 24
Finished Jun 22 04:42:47 PM PDT 24
Peak memory 198544 kb
Host smart-5771a819-afea-4ad6-8730-56b936d6b25f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781736293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3781736293
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2347235509
Short name T313
Test name
Test status
Simulation time 8760876888 ps
CPU time 7.16 seconds
Started Jun 22 04:42:47 PM PDT 24
Finished Jun 22 04:42:54 PM PDT 24
Peak memory 198088 kb
Host smart-9109df71-06b4-47ba-841b-142c6a8698f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347235509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2347235509
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.219464156
Short name T412
Test name
Test status
Simulation time 479371812 ps
CPU time 1.21 seconds
Started Jun 22 04:43:43 PM PDT 24
Finished Jun 22 04:43:45 PM PDT 24
Peak memory 192876 kb
Host smart-8b1a2dcf-7a82-4d5b-a780-4d7f062fa212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219464156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.219464156
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1533378622
Short name T408
Test name
Test status
Simulation time 399941683 ps
CPU time 1.13 seconds
Started Jun 22 04:45:07 PM PDT 24
Finished Jun 22 04:45:09 PM PDT 24
Peak memory 183484 kb
Host smart-cc3c8598-d5b0-4274-b136-665b4931e65c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533378622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1533378622
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3919140523
Short name T351
Test name
Test status
Simulation time 363518059 ps
CPU time 0.68 seconds
Started Jun 22 04:43:43 PM PDT 24
Finished Jun 22 04:43:45 PM PDT 24
Peak memory 183664 kb
Host smart-6c1fbc3d-2b2a-492a-b043-bc6176f672b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919140523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3919140523
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2536905533
Short name T289
Test name
Test status
Simulation time 369376714 ps
CPU time 0.84 seconds
Started Jun 22 04:43:43 PM PDT 24
Finished Jun 22 04:43:45 PM PDT 24
Peak memory 192872 kb
Host smart-785c5210-c00d-412d-a3f3-39758cc29313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536905533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2536905533
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2384570210
Short name T310
Test name
Test status
Simulation time 507983315 ps
CPU time 0.69 seconds
Started Jun 22 04:43:43 PM PDT 24
Finished Jun 22 04:43:44 PM PDT 24
Peak memory 183592 kb
Host smart-b6d7a944-a498-4744-90d5-1b6126f6d145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384570210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2384570210
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.747582149
Short name T321
Test name
Test status
Simulation time 439513289 ps
CPU time 1.23 seconds
Started Jun 22 04:43:45 PM PDT 24
Finished Jun 22 04:43:48 PM PDT 24
Peak memory 183648 kb
Host smart-c19ab8b7-d61f-4629-a0e9-59e0830ce170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747582149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.747582149
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3215283950
Short name T384
Test name
Test status
Simulation time 432829452 ps
CPU time 0.72 seconds
Started Jun 22 04:43:45 PM PDT 24
Finished Jun 22 04:43:47 PM PDT 24
Peak memory 183480 kb
Host smart-f113d133-07dc-441f-8b81-b45bb8a8f6b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215283950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3215283950
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1379002279
Short name T314
Test name
Test status
Simulation time 684130338 ps
CPU time 0.63 seconds
Started Jun 22 04:43:44 PM PDT 24
Finished Jun 22 04:43:46 PM PDT 24
Peak memory 192772 kb
Host smart-4964b46f-4a94-4797-9763-45bdd6b76098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379002279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1379002279
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3020923450
Short name T287
Test name
Test status
Simulation time 334762856 ps
CPU time 0.59 seconds
Started Jun 22 04:43:43 PM PDT 24
Finished Jun 22 04:43:44 PM PDT 24
Peak memory 183664 kb
Host smart-2dfb8291-1308-4e1f-a281-2004593a6624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020923450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3020923450
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3366111577
Short name T331
Test name
Test status
Simulation time 451821588 ps
CPU time 1.21 seconds
Started Jun 22 04:43:43 PM PDT 24
Finished Jun 22 04:43:46 PM PDT 24
Peak memory 183656 kb
Host smart-73fb9fb4-3bb7-4be8-8c09-cfc9053a5e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366111577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3366111577
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3096023284
Short name T66
Test name
Test status
Simulation time 317894098 ps
CPU time 0.79 seconds
Started Jun 22 04:43:00 PM PDT 24
Finished Jun 22 04:43:01 PM PDT 24
Peak memory 183528 kb
Host smart-8e06ad71-1f52-4546-8055-d2990cb7427f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096023284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3096023284
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3331086305
Short name T332
Test name
Test status
Simulation time 6998266354 ps
CPU time 17.9 seconds
Started Jun 22 04:42:59 PM PDT 24
Finished Jun 22 04:43:17 PM PDT 24
Peak memory 191932 kb
Host smart-1c32cad0-dba5-4254-89c5-a6962aa66458
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331086305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3331086305
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2042591491
Short name T303
Test name
Test status
Simulation time 882336073 ps
CPU time 1.61 seconds
Started Jun 22 04:43:00 PM PDT 24
Finished Jun 22 04:43:02 PM PDT 24
Peak memory 191764 kb
Host smart-cd95888d-b0d6-4043-8267-13fad057f866
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042591491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2042591491
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3341681648
Short name T404
Test name
Test status
Simulation time 351666396 ps
CPU time 1.13 seconds
Started Jun 22 04:42:59 PM PDT 24
Finished Jun 22 04:43:00 PM PDT 24
Peak memory 195064 kb
Host smart-8c77816e-f85a-4b2d-922d-ee747aa86f0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341681648 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3341681648
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2755747181
Short name T369
Test name
Test status
Simulation time 555928755 ps
CPU time 1.22 seconds
Started Jun 22 04:42:58 PM PDT 24
Finished Jun 22 04:43:00 PM PDT 24
Peak memory 192964 kb
Host smart-bf6c39eb-bec2-4aea-a146-041d3f369dc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755747181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2755747181
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2176219409
Short name T401
Test name
Test status
Simulation time 447803973 ps
CPU time 0.75 seconds
Started Jun 22 04:42:51 PM PDT 24
Finished Jun 22 04:42:53 PM PDT 24
Peak memory 192872 kb
Host smart-b2c656f6-f9cd-4905-a566-fb3d0f9dd5ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176219409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2176219409
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1349646707
Short name T329
Test name
Test status
Simulation time 382623243 ps
CPU time 0.7 seconds
Started Jun 22 04:43:00 PM PDT 24
Finished Jun 22 04:43:01 PM PDT 24
Peak memory 183576 kb
Host smart-b9a331e9-2d12-4dee-a867-a836ffb38f6e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349646707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1349646707
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.513477874
Short name T391
Test name
Test status
Simulation time 503537910 ps
CPU time 0.71 seconds
Started Jun 22 04:42:53 PM PDT 24
Finished Jun 22 04:42:54 PM PDT 24
Peak memory 183580 kb
Host smart-4b358e72-b4d3-46c3-83b3-dec362bb1244
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513477874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.513477874
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.352403809
Short name T76
Test name
Test status
Simulation time 2750332657 ps
CPU time 3.05 seconds
Started Jun 22 04:43:01 PM PDT 24
Finished Jun 22 04:43:04 PM PDT 24
Peak memory 183868 kb
Host smart-7ebd5c32-09a4-49f5-ba82-7c653c557daf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352403809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.352403809
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1299585225
Short name T279
Test name
Test status
Simulation time 473528232 ps
CPU time 1.65 seconds
Started Jun 22 04:42:52 PM PDT 24
Finished Jun 22 04:42:54 PM PDT 24
Peak memory 198528 kb
Host smart-7708f7a0-841a-4d2d-91a9-fed37cda256e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299585225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1299585225
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.643564548
Short name T353
Test name
Test status
Simulation time 4292583887 ps
CPU time 5.55 seconds
Started Jun 22 04:42:52 PM PDT 24
Finished Jun 22 04:42:58 PM PDT 24
Peak memory 197744 kb
Host smart-5775956c-eec8-46ac-b654-88e522aefc5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643564548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.643564548
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3844009557
Short name T390
Test name
Test status
Simulation time 386910745 ps
CPU time 0.68 seconds
Started Jun 22 04:43:42 PM PDT 24
Finished Jun 22 04:43:44 PM PDT 24
Peak memory 183588 kb
Host smart-45b3f607-521f-4260-9073-859377ac7d93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844009557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3844009557
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2973811455
Short name T301
Test name
Test status
Simulation time 336023217 ps
CPU time 0.78 seconds
Started Jun 22 04:43:49 PM PDT 24
Finished Jun 22 04:43:50 PM PDT 24
Peak memory 183500 kb
Host smart-30daa418-2c04-4033-8cec-62652e9c5ee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973811455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2973811455
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2199324038
Short name T304
Test name
Test status
Simulation time 360144153 ps
CPU time 0.81 seconds
Started Jun 22 04:43:44 PM PDT 24
Finished Jun 22 04:43:46 PM PDT 24
Peak memory 192772 kb
Host smart-03b94e1d-4827-4eef-88b9-33616a048818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199324038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2199324038
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3703564987
Short name T333
Test name
Test status
Simulation time 440804851 ps
CPU time 0.67 seconds
Started Jun 22 04:43:43 PM PDT 24
Finished Jun 22 04:43:44 PM PDT 24
Peak memory 183556 kb
Host smart-73b56639-f907-4b1e-a9ba-5a6bd44c42ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703564987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3703564987
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1638797328
Short name T318
Test name
Test status
Simulation time 431522328 ps
CPU time 0.71 seconds
Started Jun 22 04:43:48 PM PDT 24
Finished Jun 22 04:43:50 PM PDT 24
Peak memory 183496 kb
Host smart-06226ae1-0104-4950-b570-f201b049e45e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638797328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1638797328
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2602265390
Short name T305
Test name
Test status
Simulation time 362537519 ps
CPU time 1.04 seconds
Started Jun 22 04:43:43 PM PDT 24
Finished Jun 22 04:43:46 PM PDT 24
Peak memory 183604 kb
Host smart-52472bb4-eae8-46bb-a771-a811cd8938c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602265390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2602265390
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.583741996
Short name T370
Test name
Test status
Simulation time 474594481 ps
CPU time 0.74 seconds
Started Jun 22 04:43:54 PM PDT 24
Finished Jun 22 04:43:55 PM PDT 24
Peak memory 183544 kb
Host smart-667939b5-e356-4230-abf8-dba140b4fdfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583741996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.583741996
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2986126747
Short name T415
Test name
Test status
Simulation time 283054312 ps
CPU time 0.73 seconds
Started Jun 22 04:43:54 PM PDT 24
Finished Jun 22 04:43:55 PM PDT 24
Peak memory 183672 kb
Host smart-d5d04b39-7ba0-4617-a339-6ba439e993f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986126747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2986126747
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3214268369
Short name T334
Test name
Test status
Simulation time 307693976 ps
CPU time 0.75 seconds
Started Jun 22 04:43:54 PM PDT 24
Finished Jun 22 04:43:55 PM PDT 24
Peak memory 183592 kb
Host smart-dbd5f4e8-ac79-4595-8980-abb084aa8cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214268369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3214268369
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3993095491
Short name T330
Test name
Test status
Simulation time 340789153 ps
CPU time 1.03 seconds
Started Jun 22 04:43:54 PM PDT 24
Finished Jun 22 04:43:56 PM PDT 24
Peak memory 183644 kb
Host smart-61d0560a-cb32-4a15-bc90-204b989f6a07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993095491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3993095491
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1807994608
Short name T40
Test name
Test status
Simulation time 602295359 ps
CPU time 1.45 seconds
Started Jun 22 04:43:08 PM PDT 24
Finished Jun 22 04:43:10 PM PDT 24
Peak memory 193064 kb
Host smart-d1c7b3d5-09a0-4333-bf72-c2c8397649a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807994608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1807994608
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3723847786
Short name T296
Test name
Test status
Simulation time 13631662897 ps
CPU time 16.97 seconds
Started Jun 22 04:43:07 PM PDT 24
Finished Jun 22 04:43:24 PM PDT 24
Peak memory 192016 kb
Host smart-d9633442-72b0-4a86-857f-d4c0d8a96131
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723847786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3723847786
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3717829208
Short name T372
Test name
Test status
Simulation time 844303103 ps
CPU time 1.16 seconds
Started Jun 22 04:43:12 PM PDT 24
Finished Jun 22 04:43:13 PM PDT 24
Peak memory 192872 kb
Host smart-47d3c9ec-f5cc-4490-a82a-2431a27835b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717829208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3717829208
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.889873367
Short name T350
Test name
Test status
Simulation time 437523011 ps
CPU time 1.23 seconds
Started Jun 22 04:43:11 PM PDT 24
Finished Jun 22 04:43:12 PM PDT 24
Peak memory 196148 kb
Host smart-813378ad-f3fd-43b1-a776-2e18a420b2db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889873367 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.889873367
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2642618590
Short name T67
Test name
Test status
Simulation time 387315549 ps
CPU time 0.71 seconds
Started Jun 22 04:43:08 PM PDT 24
Finished Jun 22 04:43:09 PM PDT 24
Peak memory 191960 kb
Host smart-05c85793-ec54-4167-93d2-9c8e16c1d218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642618590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2642618590
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1943360256
Short name T338
Test name
Test status
Simulation time 322742821 ps
CPU time 0.63 seconds
Started Jun 22 04:42:59 PM PDT 24
Finished Jun 22 04:43:00 PM PDT 24
Peak memory 183656 kb
Host smart-918b3feb-7a0f-4ba2-ad89-5f72e394ba85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943360256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1943360256
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4042501562
Short name T288
Test name
Test status
Simulation time 505224079 ps
CPU time 1.44 seconds
Started Jun 22 04:43:07 PM PDT 24
Finished Jun 22 04:43:09 PM PDT 24
Peak memory 183516 kb
Host smart-659c9665-4bbe-41bf-a305-b331541a3188
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042501562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.4042501562
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2518007934
Short name T292
Test name
Test status
Simulation time 498716244 ps
CPU time 0.8 seconds
Started Jun 22 04:42:59 PM PDT 24
Finished Jun 22 04:43:01 PM PDT 24
Peak memory 183480 kb
Host smart-c35a0820-eb85-44c9-8fc0-eab32ca4cee3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518007934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2518007934
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2292059537
Short name T341
Test name
Test status
Simulation time 1180585348 ps
CPU time 0.9 seconds
Started Jun 22 04:43:07 PM PDT 24
Finished Jun 22 04:43:08 PM PDT 24
Peak memory 193324 kb
Host smart-61314d9c-d98a-42a0-93a3-2ceb9fc185ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292059537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2292059537
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2483815262
Short name T348
Test name
Test status
Simulation time 392658296 ps
CPU time 2.62 seconds
Started Jun 22 04:43:00 PM PDT 24
Finished Jun 22 04:43:02 PM PDT 24
Peak memory 198404 kb
Host smart-5f49a93e-65ef-4165-9620-425cede1bcac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483815262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2483815262
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1395394078
Short name T194
Test name
Test status
Simulation time 4408516301 ps
CPU time 2.87 seconds
Started Jun 22 04:43:02 PM PDT 24
Finished Jun 22 04:43:05 PM PDT 24
Peak memory 197652 kb
Host smart-f4172943-3e25-43aa-99e8-a298b2433b61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395394078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1395394078
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.751444859
Short name T396
Test name
Test status
Simulation time 524202810 ps
CPU time 0.85 seconds
Started Jun 22 04:43:55 PM PDT 24
Finished Jun 22 04:43:56 PM PDT 24
Peak memory 192772 kb
Host smart-b1cf6c7a-b826-4604-aafa-4b3c9dd1e25d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751444859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.751444859
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3474806805
Short name T283
Test name
Test status
Simulation time 489242435 ps
CPU time 0.83 seconds
Started Jun 22 04:43:53 PM PDT 24
Finished Jun 22 04:43:54 PM PDT 24
Peak memory 192876 kb
Host smart-1cb816cf-df6f-4d0e-be9b-222f25f14b6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474806805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3474806805
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1747461573
Short name T335
Test name
Test status
Simulation time 377488897 ps
CPU time 1.06 seconds
Started Jun 22 04:43:54 PM PDT 24
Finished Jun 22 04:43:56 PM PDT 24
Peak memory 183608 kb
Host smart-f2256f51-bf24-4082-82de-d5b0c48d8fb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747461573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1747461573
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1741564147
Short name T316
Test name
Test status
Simulation time 295833109 ps
CPU time 0.65 seconds
Started Jun 22 04:43:56 PM PDT 24
Finished Jun 22 04:43:57 PM PDT 24
Peak memory 192772 kb
Host smart-927b00ab-c796-4d2e-8076-090f04253746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741564147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1741564147
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3389258195
Short name T308
Test name
Test status
Simulation time 399463477 ps
CPU time 0.7 seconds
Started Jun 22 04:43:54 PM PDT 24
Finished Jun 22 04:43:56 PM PDT 24
Peak memory 183588 kb
Host smart-b43c04f0-b7d9-45fa-89f4-148913754497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389258195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3389258195
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3107076066
Short name T380
Test name
Test status
Simulation time 369772272 ps
CPU time 1.03 seconds
Started Jun 22 04:43:55 PM PDT 24
Finished Jun 22 04:43:57 PM PDT 24
Peak memory 183496 kb
Host smart-ca922446-823d-46ac-9a93-a55577a49b4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107076066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3107076066
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3262674988
Short name T387
Test name
Test status
Simulation time 384314887 ps
CPU time 0.66 seconds
Started Jun 22 04:43:55 PM PDT 24
Finished Jun 22 04:43:57 PM PDT 24
Peak memory 183664 kb
Host smart-2878ead2-a357-4f4f-b49f-0ec1b195c560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262674988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3262674988
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.229743017
Short name T340
Test name
Test status
Simulation time 454816000 ps
CPU time 1.25 seconds
Started Jun 22 04:43:55 PM PDT 24
Finished Jun 22 04:43:57 PM PDT 24
Peak memory 183496 kb
Host smart-4e2a2ed9-025c-4779-a66d-2d8aff2a986c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229743017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.229743017
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1253152298
Short name T295
Test name
Test status
Simulation time 510084816 ps
CPU time 0.7 seconds
Started Jun 22 04:43:55 PM PDT 24
Finished Jun 22 04:43:56 PM PDT 24
Peak memory 183656 kb
Host smart-cdb4df5a-6149-4a1a-be11-32703c3a009d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253152298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1253152298
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2759047185
Short name T278
Test name
Test status
Simulation time 286243233 ps
CPU time 1.02 seconds
Started Jun 22 04:43:53 PM PDT 24
Finished Jun 22 04:43:55 PM PDT 24
Peak memory 192812 kb
Host smart-58080aa9-1c01-4ccd-bd6c-a7b5e232ef0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759047185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2759047185
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4135749097
Short name T414
Test name
Test status
Simulation time 578582531 ps
CPU time 0.86 seconds
Started Jun 22 04:43:14 PM PDT 24
Finished Jun 22 04:43:15 PM PDT 24
Peak memory 196120 kb
Host smart-3dd29eac-279a-4261-a15c-293c0a917019
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135749097 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.4135749097
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2001762811
Short name T367
Test name
Test status
Simulation time 493435516 ps
CPU time 0.91 seconds
Started Jun 22 04:43:07 PM PDT 24
Finished Jun 22 04:43:08 PM PDT 24
Peak memory 193196 kb
Host smart-29400c17-1973-40f5-972a-87d812a9ca21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001762811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2001762811
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2366203598
Short name T277
Test name
Test status
Simulation time 317574453 ps
CPU time 1.02 seconds
Started Jun 22 04:43:07 PM PDT 24
Finished Jun 22 04:43:08 PM PDT 24
Peak memory 183604 kb
Host smart-638d1145-2fc3-49ec-8348-a4e9225e2041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366203598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2366203598
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.888780631
Short name T363
Test name
Test status
Simulation time 1190462946 ps
CPU time 0.99 seconds
Started Jun 22 04:43:14 PM PDT 24
Finished Jun 22 04:43:16 PM PDT 24
Peak memory 193632 kb
Host smart-e55b3916-bc5e-4bf8-aa25-d5f8217aab50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888780631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.888780631
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1607744870
Short name T281
Test name
Test status
Simulation time 369194518 ps
CPU time 1.49 seconds
Started Jun 22 04:43:09 PM PDT 24
Finished Jun 22 04:43:11 PM PDT 24
Peak memory 198516 kb
Host smart-e2a251df-c08c-4229-93d5-91ababeb85e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607744870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1607744870
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2255380223
Short name T327
Test name
Test status
Simulation time 7785718249 ps
CPU time 3.53 seconds
Started Jun 22 04:43:07 PM PDT 24
Finished Jun 22 04:43:11 PM PDT 24
Peak memory 198036 kb
Host smart-566e051a-e033-4877-9930-6a3f2a23956f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255380223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2255380223
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2476754682
Short name T406
Test name
Test status
Simulation time 545790215 ps
CPU time 1.39 seconds
Started Jun 22 04:43:13 PM PDT 24
Finished Jun 22 04:43:15 PM PDT 24
Peak memory 197380 kb
Host smart-3504a050-c48b-4810-909f-a7d4adddda9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476754682 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2476754682
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.449861754
Short name T403
Test name
Test status
Simulation time 502610939 ps
CPU time 0.73 seconds
Started Jun 22 04:43:15 PM PDT 24
Finished Jun 22 04:43:17 PM PDT 24
Peak memory 193912 kb
Host smart-d45f8f5f-320d-48fb-89c3-b8bf3a0e0939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449861754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.449861754
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3289753720
Short name T311
Test name
Test status
Simulation time 375649413 ps
CPU time 0.62 seconds
Started Jun 22 04:43:14 PM PDT 24
Finished Jun 22 04:43:15 PM PDT 24
Peak memory 183648 kb
Host smart-85fedec9-1609-42c0-ab4c-39b91b1d2441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289753720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3289753720
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3400870621
Short name T407
Test name
Test status
Simulation time 1125464622 ps
CPU time 1.23 seconds
Started Jun 22 04:43:13 PM PDT 24
Finished Jun 22 04:43:15 PM PDT 24
Peak memory 183700 kb
Host smart-f5126f51-93b6-49b1-b43e-11af0fafe251
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400870621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3400870621
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4221312487
Short name T389
Test name
Test status
Simulation time 388438598 ps
CPU time 2.8 seconds
Started Jun 22 04:43:15 PM PDT 24
Finished Jun 22 04:43:19 PM PDT 24
Peak memory 198412 kb
Host smart-d98989c3-4d58-4739-a67f-8d4fe705d251
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221312487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.4221312487
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3189746583
Short name T382
Test name
Test status
Simulation time 7893614908 ps
CPU time 6.71 seconds
Started Jun 22 04:43:13 PM PDT 24
Finished Jun 22 04:43:20 PM PDT 24
Peak memory 198068 kb
Host smart-90793cec-e006-428b-877d-6e902fc16f7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189746583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3189746583
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4007879170
Short name T349
Test name
Test status
Simulation time 408292185 ps
CPU time 0.84 seconds
Started Jun 22 04:43:20 PM PDT 24
Finished Jun 22 04:43:21 PM PDT 24
Peak memory 196396 kb
Host smart-c0d869a5-ca4b-4686-b305-d8f321a88db2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007879170 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.4007879170
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4202236417
Short name T420
Test name
Test status
Simulation time 289926602 ps
CPU time 0.94 seconds
Started Jun 22 04:43:13 PM PDT 24
Finished Jun 22 04:43:15 PM PDT 24
Peak memory 183648 kb
Host smart-710f1b5e-304d-454f-abae-6cb9ec017ef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202236417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4202236417
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3055095644
Short name T323
Test name
Test status
Simulation time 1904680412 ps
CPU time 1.58 seconds
Started Jun 22 04:43:23 PM PDT 24
Finished Jun 22 04:43:25 PM PDT 24
Peak memory 194840 kb
Host smart-255f448a-82ca-4b15-bf91-26c00d9416ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055095644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3055095644
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3649019161
Short name T393
Test name
Test status
Simulation time 1721112717 ps
CPU time 1.6 seconds
Started Jun 22 04:43:14 PM PDT 24
Finished Jun 22 04:43:16 PM PDT 24
Peak memory 198500 kb
Host smart-aa3afaf6-f58d-4f2e-9240-dd0f383ce07b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649019161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3649019161
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3627869546
Short name T293
Test name
Test status
Simulation time 8416606676 ps
CPU time 14.34 seconds
Started Jun 22 04:43:14 PM PDT 24
Finished Jun 22 04:43:28 PM PDT 24
Peak memory 197960 kb
Host smart-7337eb72-252e-4de6-b501-06411ed07995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627869546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3627869546
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3204963670
Short name T328
Test name
Test status
Simulation time 525323703 ps
CPU time 1.37 seconds
Started Jun 22 04:43:21 PM PDT 24
Finished Jun 22 04:43:23 PM PDT 24
Peak memory 195872 kb
Host smart-31ded08e-63ab-4c12-8d60-462a85a1bac1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204963670 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3204963670
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3280817298
Short name T80
Test name
Test status
Simulation time 328467995 ps
CPU time 1.12 seconds
Started Jun 22 04:43:22 PM PDT 24
Finished Jun 22 04:43:24 PM PDT 24
Peak memory 192984 kb
Host smart-7e751d4a-3969-4f8d-a301-606666d6653b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280817298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3280817298
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3980116829
Short name T371
Test name
Test status
Simulation time 567003171 ps
CPU time 0.62 seconds
Started Jun 22 04:43:23 PM PDT 24
Finished Jun 22 04:43:25 PM PDT 24
Peak memory 192768 kb
Host smart-d9dbb91b-92b1-4ad0-82ed-3653206324fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980116829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3980116829
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.525173389
Short name T77
Test name
Test status
Simulation time 2371976127 ps
CPU time 1.39 seconds
Started Jun 22 04:43:26 PM PDT 24
Finished Jun 22 04:43:27 PM PDT 24
Peak memory 193856 kb
Host smart-c0898a4c-25f6-4379-9094-3a5bc7fdc97c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525173389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.525173389
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.476848354
Short name T359
Test name
Test status
Simulation time 688300425 ps
CPU time 1.95 seconds
Started Jun 22 04:43:22 PM PDT 24
Finished Jun 22 04:43:24 PM PDT 24
Peak memory 198676 kb
Host smart-2ef6cc2b-51ec-48c6-ae8a-222d1f2c6202
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476848354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.476848354
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3477990043
Short name T191
Test name
Test status
Simulation time 7869470274 ps
CPU time 5.36 seconds
Started Jun 22 04:43:22 PM PDT 24
Finished Jun 22 04:43:28 PM PDT 24
Peak memory 198272 kb
Host smart-0872858e-d1f1-4768-a0a0-00e8e4cdb3b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477990043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3477990043
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1078747064
Short name T365
Test name
Test status
Simulation time 517152934 ps
CPU time 1.31 seconds
Started Jun 22 04:43:22 PM PDT 24
Finished Jun 22 04:43:24 PM PDT 24
Peak memory 195436 kb
Host smart-cd093909-964f-43da-9d60-117d5efa8b86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078747064 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1078747064
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2566902115
Short name T199
Test name
Test status
Simulation time 317643133 ps
CPU time 0.64 seconds
Started Jun 22 04:43:21 PM PDT 24
Finished Jun 22 04:43:22 PM PDT 24
Peak memory 192872 kb
Host smart-ca2d6cb3-b6c0-4c06-8b29-f0f4ed07f4e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566902115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2566902115
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.750932594
Short name T290
Test name
Test status
Simulation time 285859049 ps
CPU time 0.92 seconds
Started Jun 22 04:43:20 PM PDT 24
Finished Jun 22 04:43:22 PM PDT 24
Peak memory 183660 kb
Host smart-84466bad-4835-498c-a147-0e8cd194c1d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750932594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.750932594
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1064263734
Short name T418
Test name
Test status
Simulation time 862753855 ps
CPU time 1.68 seconds
Started Jun 22 04:43:24 PM PDT 24
Finished Jun 22 04:43:26 PM PDT 24
Peak memory 193256 kb
Host smart-59391783-2fa7-48c4-af2f-ed3bc530ec39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064263734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1064263734
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4253513243
Short name T419
Test name
Test status
Simulation time 553634161 ps
CPU time 1.83 seconds
Started Jun 22 04:43:22 PM PDT 24
Finished Jun 22 04:43:24 PM PDT 24
Peak memory 198716 kb
Host smart-21a871be-86e9-46f6-94a2-51166b90d2f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253513243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.4253513243
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.409317976
Short name T312
Test name
Test status
Simulation time 4003609519 ps
CPU time 1.81 seconds
Started Jun 22 04:43:21 PM PDT 24
Finished Jun 22 04:43:24 PM PDT 24
Peak memory 196596 kb
Host smart-9c992d98-a3b9-4426-9100-b78b3b7a556d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409317976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.409317976
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2570488803
Short name T258
Test name
Test status
Simulation time 32412530061 ps
CPU time 7.06 seconds
Started Jun 22 04:49:53 PM PDT 24
Finished Jun 22 04:50:02 PM PDT 24
Peak memory 192436 kb
Host smart-f4d33b5d-6976-4498-9c87-009ffc4f04c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570488803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2570488803
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3710843555
Short name T271
Test name
Test status
Simulation time 387037385 ps
CPU time 1.16 seconds
Started Jun 22 04:49:54 PM PDT 24
Finished Jun 22 04:49:57 PM PDT 24
Peak memory 192200 kb
Host smart-1ce40a23-b767-4259-96f8-ea842cd94f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710843555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3710843555
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2328500134
Short name T219
Test name
Test status
Simulation time 54655000491 ps
CPU time 67.92 seconds
Started Jun 22 04:49:52 PM PDT 24
Finished Jun 22 04:51:01 PM PDT 24
Peak memory 192556 kb
Host smart-d8c4e727-2d6d-4cd7-bc9f-5b9617f0b574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328500134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2328500134
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3065837771
Short name T17
Test name
Test status
Simulation time 8024907953 ps
CPU time 4.1 seconds
Started Jun 22 04:49:53 PM PDT 24
Finished Jun 22 04:49:59 PM PDT 24
Peak memory 216752 kb
Host smart-1ed05389-a178-4896-8cb8-6fb13b546c69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065837771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3065837771
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.821592896
Short name T242
Test name
Test status
Simulation time 561701760 ps
CPU time 1.02 seconds
Started Jun 22 04:49:59 PM PDT 24
Finished Jun 22 04:50:01 PM PDT 24
Peak memory 192280 kb
Host smart-cfce948c-8a6c-4da6-abb5-4eec45992e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821592896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.821592896
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2971025374
Short name T247
Test name
Test status
Simulation time 37474118875 ps
CPU time 13.84 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:50:15 PM PDT 24
Peak memory 192656 kb
Host smart-fca436e0-2915-4675-bada-d957ae2c5d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971025374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2971025374
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.241968080
Short name T253
Test name
Test status
Simulation time 571907740 ps
CPU time 1.36 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:50:05 PM PDT 24
Peak memory 192240 kb
Host smart-5ab522c9-a581-4853-828e-2a925e0a8d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241968080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.241968080
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1155867904
Short name T198
Test name
Test status
Simulation time 34689818797 ps
CPU time 48.39 seconds
Started Jun 22 04:50:02 PM PDT 24
Finished Jun 22 04:50:51 PM PDT 24
Peak memory 192432 kb
Host smart-8f484828-635b-4ab6-a0b2-c43935162302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155867904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1155867904
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1214732498
Short name T203
Test name
Test status
Simulation time 604214344 ps
CPU time 0.83 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:50:05 PM PDT 24
Peak memory 197120 kb
Host smart-a19eb740-bd66-4538-851e-a32c98a50382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214732498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1214732498
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.976800472
Short name T265
Test name
Test status
Simulation time 17137398562 ps
CPU time 28.58 seconds
Started Jun 22 04:50:02 PM PDT 24
Finished Jun 22 04:50:31 PM PDT 24
Peak memory 192392 kb
Host smart-732558e4-aa0f-4792-acbb-df6d92254ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976800472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.976800472
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.83122888
Short name T241
Test name
Test status
Simulation time 446399597 ps
CPU time 0.77 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:50:04 PM PDT 24
Peak memory 192280 kb
Host smart-0a68ed53-fc86-4e45-a58a-a85f1466a936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83122888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.83122888
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3763699793
Short name T87
Test name
Test status
Simulation time 48529367235 ps
CPU time 10.29 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:50:14 PM PDT 24
Peak memory 197404 kb
Host smart-e2ab40f1-d16d-43ec-a5f1-6ba456adcf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763699793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3763699793
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3176051812
Short name T211
Test name
Test status
Simulation time 519343878 ps
CPU time 0.96 seconds
Started Jun 22 04:50:04 PM PDT 24
Finished Jun 22 04:50:06 PM PDT 24
Peak memory 192296 kb
Host smart-7b4e2d84-6195-4e2f-ba5e-2c47e01ec3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176051812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3176051812
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.910739196
Short name T233
Test name
Test status
Simulation time 37076901232 ps
CPU time 23.25 seconds
Started Jun 22 04:49:58 PM PDT 24
Finished Jun 22 04:50:22 PM PDT 24
Peak memory 192288 kb
Host smart-6ae69a0c-6a9c-4b43-abe7-92f14341f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910739196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.910739196
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3741813798
Short name T274
Test name
Test status
Simulation time 479011893 ps
CPU time 0.72 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:50:02 PM PDT 24
Peak memory 197068 kb
Host smart-ada9b859-a676-449d-b209-db0aea9df6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741813798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3741813798
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.282217550
Short name T216
Test name
Test status
Simulation time 7495060622 ps
CPU time 6.01 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:50:16 PM PDT 24
Peak memory 192308 kb
Host smart-d84d554f-2fa2-4ccb-88f3-69cbf3ae9d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282217550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.282217550
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2026373667
Short name T204
Test name
Test status
Simulation time 564900536 ps
CPU time 0.83 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:50:10 PM PDT 24
Peak memory 192232 kb
Host smart-10910751-fa89-4bc4-b3e9-7a40243aebf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026373667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2026373667
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.353803090
Short name T243
Test name
Test status
Simulation time 35019459271 ps
CPU time 12.69 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:50:22 PM PDT 24
Peak memory 192436 kb
Host smart-c567c748-1ea0-41e4-876c-6b84e5ffb8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353803090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.353803090
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1937454215
Short name T220
Test name
Test status
Simulation time 602691884 ps
CPU time 0.82 seconds
Started Jun 22 04:50:11 PM PDT 24
Finished Jun 22 04:50:13 PM PDT 24
Peak memory 192312 kb
Host smart-a9b005b6-62e5-4c9f-ac93-8c0fa98aa012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937454215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1937454215
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2744014554
Short name T166
Test name
Test status
Simulation time 39975306718 ps
CPU time 217.55 seconds
Started Jun 22 04:50:11 PM PDT 24
Finished Jun 22 04:53:49 PM PDT 24
Peak memory 207336 kb
Host smart-fb417760-b526-4150-9aa7-3f3bbc4c644e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744014554 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2744014554
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.391143072
Short name T26
Test name
Test status
Simulation time 43705477849 ps
CPU time 16.81 seconds
Started Jun 22 04:50:07 PM PDT 24
Finished Jun 22 04:50:25 PM PDT 24
Peak memory 192336 kb
Host smart-3958b952-95b9-4205-b0a5-1dbf5d0a9538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391143072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.391143072
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.4217065279
Short name T8
Test name
Test status
Simulation time 564733002 ps
CPU time 1.24 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:50:11 PM PDT 24
Peak memory 197116 kb
Host smart-531d1358-fa07-4aa7-ac26-2d30743ffee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217065279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.4217065279
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_jump.961826546
Short name T174
Test name
Test status
Simulation time 455675148 ps
CPU time 1.03 seconds
Started Jun 22 04:50:10 PM PDT 24
Finished Jun 22 04:50:12 PM PDT 24
Peak memory 197036 kb
Host smart-939d6f02-b0a5-477c-8e0d-a8dfeb89d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961826546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.961826546
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.809626326
Short name T50
Test name
Test status
Simulation time 30393583421 ps
CPU time 11.91 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:50:20 PM PDT 24
Peak memory 192352 kb
Host smart-157e37b7-80aa-46e9-9b29-58ed446fd1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809626326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.809626326
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.973918930
Short name T42
Test name
Test status
Simulation time 545081175 ps
CPU time 0.79 seconds
Started Jun 22 04:50:07 PM PDT 24
Finished Jun 22 04:50:08 PM PDT 24
Peak memory 192256 kb
Host smart-d0ba8c60-d234-4aa7-8c09-e53b22a8bb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973918930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.973918930
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_jump.910188107
Short name T170
Test name
Test status
Simulation time 454674529 ps
CPU time 0.73 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:50:09 PM PDT 24
Peak memory 197044 kb
Host smart-f60b185a-adfc-4494-9bf0-69d6c2cf201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910188107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.910188107
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3923435002
Short name T196
Test name
Test status
Simulation time 10384399365 ps
CPU time 15.3 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:50:26 PM PDT 24
Peak memory 192432 kb
Host smart-38b509e8-2cc7-4279-9d43-fd344badaba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923435002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3923435002
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1949816471
Short name T252
Test name
Test status
Simulation time 354019329 ps
CPU time 1.17 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:50:12 PM PDT 24
Peak memory 197080 kb
Host smart-2f402565-5ec3-48a1-aabd-0ea9f768faa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949816471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1949816471
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.646602387
Short name T236
Test name
Test status
Simulation time 41659520785 ps
CPU time 56.8 seconds
Started Jun 22 04:49:53 PM PDT 24
Finished Jun 22 04:50:51 PM PDT 24
Peak memory 192436 kb
Host smart-4de1aa4f-25ea-44d3-a556-ce06abdaba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646602387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.646602387
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.483031190
Short name T21
Test name
Test status
Simulation time 4511160676 ps
CPU time 4.18 seconds
Started Jun 22 04:49:52 PM PDT 24
Finished Jun 22 04:49:58 PM PDT 24
Peak memory 216356 kb
Host smart-55c98411-7eda-4524-a9ec-a31a2b27f763
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483031190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.483031190
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2627903960
Short name T240
Test name
Test status
Simulation time 542687485 ps
CPU time 0.78 seconds
Started Jun 22 04:49:56 PM PDT 24
Finished Jun 22 04:49:58 PM PDT 24
Peak memory 192264 kb
Host smart-db602ec5-c3ad-4f53-81b9-78c2d2061e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627903960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2627903960
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1869116627
Short name T263
Test name
Test status
Simulation time 3237938885 ps
CPU time 2.95 seconds
Started Jun 22 04:50:07 PM PDT 24
Finished Jun 22 04:50:10 PM PDT 24
Peak memory 192408 kb
Host smart-6bf9e9da-df90-4c9d-950a-e15ac02af7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869116627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1869116627
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2549564093
Short name T228
Test name
Test status
Simulation time 377256679 ps
CPU time 1.2 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:50:11 PM PDT 24
Peak memory 192444 kb
Host smart-c5b82d7e-e0be-4250-a88d-115a75109713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549564093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2549564093
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1841983570
Short name T2
Test name
Test status
Simulation time 29122283587 ps
CPU time 28.34 seconds
Started Jun 22 04:51:07 PM PDT 24
Finished Jun 22 04:51:35 PM PDT 24
Peak memory 192432 kb
Host smart-33bf4901-0d0a-4fc2-8de6-a2ec4159546b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841983570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1841983570
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1040338962
Short name T212
Test name
Test status
Simulation time 352060493 ps
CPU time 1.08 seconds
Started Jun 22 04:50:10 PM PDT 24
Finished Jun 22 04:50:12 PM PDT 24
Peak memory 197080 kb
Host smart-20499ea9-97bb-441f-8f13-f1577253571f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040338962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1040338962
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3772114679
Short name T269
Test name
Test status
Simulation time 22983437954 ps
CPU time 10.38 seconds
Started Jun 22 04:50:10 PM PDT 24
Finished Jun 22 04:50:21 PM PDT 24
Peak memory 192352 kb
Host smart-3e04787d-ab96-47d9-9b51-0e72323a9477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772114679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3772114679
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3065569957
Short name T222
Test name
Test status
Simulation time 516320807 ps
CPU time 0.77 seconds
Started Jun 22 04:50:07 PM PDT 24
Finished Jun 22 04:50:08 PM PDT 24
Peak memory 192204 kb
Host smart-bc414a2b-caaf-4743-a10c-a25ae159ae25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065569957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3065569957
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1447729477
Short name T213
Test name
Test status
Simulation time 34610370088 ps
CPU time 12.72 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:50:23 PM PDT 24
Peak memory 192340 kb
Host smart-e00bd8e9-e6a2-4571-8f71-01cfe69e70ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447729477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1447729477
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2205864530
Short name T7
Test name
Test status
Simulation time 519362233 ps
CPU time 1.39 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:50:10 PM PDT 24
Peak memory 197048 kb
Host smart-ce4405b5-3d55-4c58-b187-ccc9cfa867f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205864530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2205864530
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.4137165965
Short name T262
Test name
Test status
Simulation time 33994842449 ps
CPU time 12.72 seconds
Started Jun 22 04:50:07 PM PDT 24
Finished Jun 22 04:50:20 PM PDT 24
Peak memory 192432 kb
Host smart-5037de70-36e6-405a-8aa6-0d4270097faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137165965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.4137165965
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3849570908
Short name T43
Test name
Test status
Simulation time 485289186 ps
CPU time 0.76 seconds
Started Jun 22 04:50:08 PM PDT 24
Finished Jun 22 04:50:10 PM PDT 24
Peak memory 192288 kb
Host smart-03f6bfff-782b-4ff8-8c62-06604ee744ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849570908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3849570908
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2823284363
Short name T61
Test name
Test status
Simulation time 31094449144 ps
CPU time 10.42 seconds
Started Jun 22 04:50:20 PM PDT 24
Finished Jun 22 04:50:32 PM PDT 24
Peak memory 192432 kb
Host smart-ca82942c-f0c6-4b22-bb74-3fc3276af363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823284363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2823284363
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2470158852
Short name T88
Test name
Test status
Simulation time 491244645 ps
CPU time 1.32 seconds
Started Jun 22 04:50:09 PM PDT 24
Finished Jun 22 04:50:12 PM PDT 24
Peak memory 197084 kb
Host smart-e3ca1cfb-cbc0-4c21-a793-14e6ddd6961a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470158852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2470158852
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3299636961
Short name T208
Test name
Test status
Simulation time 16633112418 ps
CPU time 12.89 seconds
Started Jun 22 04:50:30 PM PDT 24
Finished Jun 22 04:50:43 PM PDT 24
Peak memory 192432 kb
Host smart-e2ddcb4a-ec9a-4d29-8a48-035653a5bb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299636961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3299636961
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3542747746
Short name T214
Test name
Test status
Simulation time 590828219 ps
CPU time 1 seconds
Started Jun 22 04:50:24 PM PDT 24
Finished Jun 22 04:50:25 PM PDT 24
Peak memory 192520 kb
Host smart-bb0e4075-ffee-4800-b125-8f36f5937835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542747746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3542747746
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3718632761
Short name T248
Test name
Test status
Simulation time 9577912406 ps
CPU time 3.98 seconds
Started Jun 22 04:50:17 PM PDT 24
Finished Jun 22 04:50:21 PM PDT 24
Peak memory 192408 kb
Host smart-6845e779-7d7e-4470-a52b-d72c8de9132f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718632761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3718632761
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1172389836
Short name T238
Test name
Test status
Simulation time 585240818 ps
CPU time 1.41 seconds
Started Jun 22 04:50:19 PM PDT 24
Finished Jun 22 04:50:21 PM PDT 24
Peak memory 192204 kb
Host smart-c5e9d285-a7c4-4f97-a482-33bcd70b2e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172389836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1172389836
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.854131579
Short name T246
Test name
Test status
Simulation time 5649682692 ps
CPU time 1.19 seconds
Started Jun 22 04:50:21 PM PDT 24
Finished Jun 22 04:50:23 PM PDT 24
Peak memory 192436 kb
Host smart-64f3d12b-ce2a-410a-924e-212a2d60d613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854131579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.854131579
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.237413079
Short name T209
Test name
Test status
Simulation time 576006208 ps
CPU time 0.8 seconds
Started Jun 22 04:50:18 PM PDT 24
Finished Jun 22 04:50:20 PM PDT 24
Peak memory 192532 kb
Host smart-205a0ff7-2eb1-4266-96c5-df5b357c3e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237413079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.237413079
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2886144560
Short name T245
Test name
Test status
Simulation time 21260051829 ps
CPU time 28.03 seconds
Started Jun 22 04:51:19 PM PDT 24
Finished Jun 22 04:51:48 PM PDT 24
Peak memory 192432 kb
Host smart-11c92602-e8c0-49db-ba71-ca7124bcd064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886144560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2886144560
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4150027603
Short name T273
Test name
Test status
Simulation time 434527857 ps
CPU time 0.74 seconds
Started Jun 22 04:50:18 PM PDT 24
Finished Jun 22 04:50:20 PM PDT 24
Peak memory 192236 kb
Host smart-7992a3d9-d516-4db2-8d9b-263b787b92cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150027603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4150027603
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3221661888
Short name T189
Test name
Test status
Simulation time 429297403 ps
CPU time 1.14 seconds
Started Jun 22 04:49:51 PM PDT 24
Finished Jun 22 04:49:53 PM PDT 24
Peak memory 196964 kb
Host smart-0dc0be7c-5dc0-412a-97bb-da7f7078f5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221661888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3221661888
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3516710265
Short name T24
Test name
Test status
Simulation time 12346948050 ps
CPU time 4.89 seconds
Started Jun 22 04:49:51 PM PDT 24
Finished Jun 22 04:49:57 PM PDT 24
Peak memory 192356 kb
Host smart-7470e80c-8e00-460c-97af-a3d5c2011d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516710265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3516710265
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2427996347
Short name T15
Test name
Test status
Simulation time 8355617392 ps
CPU time 12.6 seconds
Started Jun 22 04:49:52 PM PDT 24
Finished Jun 22 04:50:06 PM PDT 24
Peak memory 216372 kb
Host smart-02482310-5d10-429a-a8c6-ed4eed5ced14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427996347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2427996347
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1699392633
Short name T234
Test name
Test status
Simulation time 668529270 ps
CPU time 0.66 seconds
Started Jun 22 04:49:51 PM PDT 24
Finished Jun 22 04:49:53 PM PDT 24
Peak memory 197088 kb
Host smart-de9ab633-c28a-41ff-9e51-3ddf1ac5418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699392633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1699392633
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2845674738
Short name T256
Test name
Test status
Simulation time 25404587936 ps
CPU time 7.9 seconds
Started Jun 22 04:50:27 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 192432 kb
Host smart-48c10fdc-ca09-45f1-85e9-b4bd68f8ab71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845674738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2845674738
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.318696986
Short name T249
Test name
Test status
Simulation time 617866636 ps
CPU time 0.8 seconds
Started Jun 22 04:50:18 PM PDT 24
Finished Jun 22 04:50:19 PM PDT 24
Peak memory 197044 kb
Host smart-c10f9a25-f179-4eee-a9e7-31761dfad545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318696986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.318696986
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1956542790
Short name T85
Test name
Test status
Simulation time 36090530113 ps
CPU time 4.1 seconds
Started Jun 22 04:50:15 PM PDT 24
Finished Jun 22 04:50:20 PM PDT 24
Peak memory 192352 kb
Host smart-b0ef78c7-b854-4b8c-8b37-48e4977bd54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956542790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1956542790
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.284131777
Short name T223
Test name
Test status
Simulation time 532661997 ps
CPU time 1.3 seconds
Started Jun 22 04:50:20 PM PDT 24
Finished Jun 22 04:50:22 PM PDT 24
Peak memory 192196 kb
Host smart-15f85588-22f2-4c7c-bfd1-c41056a4b478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284131777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.284131777
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.662672782
Short name T257
Test name
Test status
Simulation time 22076897581 ps
CPU time 28.93 seconds
Started Jun 22 04:50:19 PM PDT 24
Finished Jun 22 04:50:48 PM PDT 24
Peak memory 192372 kb
Host smart-7ad17288-011b-4896-896f-46f11b49c259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662672782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.662672782
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1311878484
Short name T29
Test name
Test status
Simulation time 590729476 ps
CPU time 0.94 seconds
Started Jun 22 04:50:19 PM PDT 24
Finished Jun 22 04:50:21 PM PDT 24
Peak memory 197108 kb
Host smart-d67d748a-8956-41b5-a4cf-147e1d980f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311878484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1311878484
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.4109691125
Short name T230
Test name
Test status
Simulation time 28935627922 ps
CPU time 11.9 seconds
Started Jun 22 04:50:23 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 192432 kb
Host smart-46b80a40-ab72-4bf9-9b76-ba197aa31255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109691125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.4109691125
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1947892541
Short name T224
Test name
Test status
Simulation time 481906181 ps
CPU time 0.76 seconds
Started Jun 22 04:50:20 PM PDT 24
Finished Jun 22 04:50:22 PM PDT 24
Peak memory 192216 kb
Host smart-e2aa5f7f-65e0-49ad-9665-c3ff0a33129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947892541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1947892541
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3068019720
Short name T197
Test name
Test status
Simulation time 47141409855 ps
CPU time 20.05 seconds
Started Jun 22 04:50:22 PM PDT 24
Finished Jun 22 04:50:43 PM PDT 24
Peak memory 192432 kb
Host smart-8f537032-4a93-419e-b734-664a95fc79a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068019720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3068019720
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.764517044
Short name T260
Test name
Test status
Simulation time 390256518 ps
CPU time 1.15 seconds
Started Jun 22 04:50:25 PM PDT 24
Finished Jun 22 04:50:27 PM PDT 24
Peak memory 192308 kb
Host smart-5c0796d7-cc44-4ced-8e9c-21de1de582db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764517044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.764517044
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3047924930
Short name T250
Test name
Test status
Simulation time 497666739 ps
CPU time 1.31 seconds
Started Jun 22 04:50:18 PM PDT 24
Finished Jun 22 04:50:20 PM PDT 24
Peak memory 192316 kb
Host smart-e4aa2f9a-10ed-493c-aea0-6ffcae7056bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047924930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3047924930
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3913372325
Short name T266
Test name
Test status
Simulation time 503668038 ps
CPU time 0.9 seconds
Started Jun 22 04:50:24 PM PDT 24
Finished Jun 22 04:50:26 PM PDT 24
Peak memory 192268 kb
Host smart-f4012e81-d66a-45d1-8b96-94c24083d4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913372325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3913372325
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.315401063
Short name T184
Test name
Test status
Simulation time 584318313 ps
CPU time 1.41 seconds
Started Jun 22 04:50:19 PM PDT 24
Finished Jun 22 04:50:21 PM PDT 24
Peak memory 197052 kb
Host smart-b57dbdbb-fd4d-49b4-b8ab-8f20f98134dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315401063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.315401063
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1217595147
Short name T215
Test name
Test status
Simulation time 20202006970 ps
CPU time 27.25 seconds
Started Jun 22 04:50:25 PM PDT 24
Finished Jun 22 04:50:53 PM PDT 24
Peak memory 192432 kb
Host smart-9e18ee09-6fb1-4e2b-9014-2aa6a25bc038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217595147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1217595147
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3712659543
Short name T235
Test name
Test status
Simulation time 553827972 ps
CPU time 0.98 seconds
Started Jun 22 04:50:18 PM PDT 24
Finished Jun 22 04:50:19 PM PDT 24
Peak memory 197116 kb
Host smart-16dee0d7-5293-4aa5-b416-4183d596ef27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712659543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3712659543
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3354998020
Short name T275
Test name
Test status
Simulation time 9112667632 ps
CPU time 8.08 seconds
Started Jun 22 04:50:19 PM PDT 24
Finished Jun 22 04:50:28 PM PDT 24
Peak memory 192988 kb
Host smart-7def5e77-60a9-47a5-8cf5-51610290ce3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354998020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3354998020
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3527521163
Short name T218
Test name
Test status
Simulation time 30949673934 ps
CPU time 21.67 seconds
Started Jun 22 04:50:27 PM PDT 24
Finished Jun 22 04:50:50 PM PDT 24
Peak memory 192432 kb
Host smart-f0e45ef1-e018-405c-9fca-7183f8076db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527521163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3527521163
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2247108427
Short name T201
Test name
Test status
Simulation time 419030123 ps
CPU time 0.71 seconds
Started Jun 22 04:50:25 PM PDT 24
Finished Jun 22 04:50:27 PM PDT 24
Peak memory 197104 kb
Host smart-653d17b8-e7bc-457f-85d7-c0c4e295ecef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247108427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2247108427
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1230195132
Short name T226
Test name
Test status
Simulation time 44485523597 ps
CPU time 28.64 seconds
Started Jun 22 04:50:27 PM PDT 24
Finished Jun 22 04:50:56 PM PDT 24
Peak memory 192380 kb
Host smart-c756b101-ce62-4e47-8608-405848cce3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230195132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1230195132
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2330391192
Short name T231
Test name
Test status
Simulation time 379605939 ps
CPU time 1.19 seconds
Started Jun 22 04:50:30 PM PDT 24
Finished Jun 22 04:50:32 PM PDT 24
Peak memory 192296 kb
Host smart-d7288874-6044-494d-b572-9737d0132609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330391192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2330391192
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.24028511
Short name T270
Test name
Test status
Simulation time 19505530260 ps
CPU time 9.75 seconds
Started Jun 22 04:50:33 PM PDT 24
Finished Jun 22 04:50:44 PM PDT 24
Peak memory 192428 kb
Host smart-6bedddf5-96ab-46f7-bee7-12aacec355bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24028511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.24028511
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2412885808
Short name T206
Test name
Test status
Simulation time 556806696 ps
CPU time 1.49 seconds
Started Jun 22 04:50:26 PM PDT 24
Finished Jun 22 04:50:29 PM PDT 24
Peak memory 192312 kb
Host smart-d7488b05-1abc-4c9b-b5df-2dd62d6eb5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412885808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2412885808
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.4196022884
Short name T229
Test name
Test status
Simulation time 36671043528 ps
CPU time 9.7 seconds
Started Jun 22 04:49:59 PM PDT 24
Finished Jun 22 04:50:10 PM PDT 24
Peak memory 192412 kb
Host smart-4c6d89c2-406f-4990-95ed-f40f9e07b604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196022884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.4196022884
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1014227152
Short name T16
Test name
Test status
Simulation time 4408029263 ps
CPU time 6.93 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:50:11 PM PDT 24
Peak memory 216340 kb
Host smart-460cdefa-b6b6-45b9-b71d-a03cafaff069
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014227152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1014227152
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1655881428
Short name T207
Test name
Test status
Simulation time 344109095 ps
CPU time 1.11 seconds
Started Jun 22 04:50:03 PM PDT 24
Finished Jun 22 04:50:05 PM PDT 24
Peak memory 192292 kb
Host smart-a96dd998-fd37-4c78-b103-fd4ca9dce8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655881428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1655881428
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.467107086
Short name T210
Test name
Test status
Simulation time 20405035656 ps
CPU time 13.91 seconds
Started Jun 22 04:50:23 PM PDT 24
Finished Jun 22 04:50:38 PM PDT 24
Peak memory 192436 kb
Host smart-23583b90-f87b-492d-a66f-1cff46f8a657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467107086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.467107086
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2069899695
Short name T202
Test name
Test status
Simulation time 450462378 ps
CPU time 0.81 seconds
Started Jun 22 04:50:27 PM PDT 24
Finished Jun 22 04:50:29 PM PDT 24
Peak memory 192308 kb
Host smart-6101854e-ad3a-498e-9dfd-5d6369bcd077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069899695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2069899695
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1354800486
Short name T268
Test name
Test status
Simulation time 61011326734 ps
CPU time 42.9 seconds
Started Jun 22 04:50:30 PM PDT 24
Finished Jun 22 04:51:13 PM PDT 24
Peak memory 192432 kb
Host smart-96639ae6-ce30-47bf-9d5e-a75316359262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354800486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1354800486
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3739435724
Short name T221
Test name
Test status
Simulation time 375500127 ps
CPU time 1.11 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:51:36 PM PDT 24
Peak memory 197104 kb
Host smart-36c3061c-6e8c-4f71-bdc2-d9270b9c6e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739435724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3739435724
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1747108072
Short name T217
Test name
Test status
Simulation time 295887506939 ps
CPU time 29.39 seconds
Started Jun 22 04:50:28 PM PDT 24
Finished Jun 22 04:50:58 PM PDT 24
Peak memory 193016 kb
Host smart-114bdc1c-041e-468a-8d92-57e0cb12a18f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747108072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1747108072
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.960977474
Short name T272
Test name
Test status
Simulation time 16600424882 ps
CPU time 5.95 seconds
Started Jun 22 04:50:26 PM PDT 24
Finished Jun 22 04:50:33 PM PDT 24
Peak memory 192276 kb
Host smart-f6729e29-dd2f-4236-860a-ca2039ffbfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960977474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.960977474
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3473370474
Short name T232
Test name
Test status
Simulation time 383299303 ps
CPU time 0.9 seconds
Started Jun 22 04:50:30 PM PDT 24
Finished Jun 22 04:50:32 PM PDT 24
Peak memory 192288 kb
Host smart-85892102-b0fa-4399-a647-958f965239d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473370474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3473370474
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.74179669
Short name T25
Test name
Test status
Simulation time 6970520785 ps
CPU time 11.18 seconds
Started Jun 22 04:50:37 PM PDT 24
Finished Jun 22 04:50:49 PM PDT 24
Peak memory 192428 kb
Host smart-bc79eaa4-a3d7-4f42-928d-4b7cb50bde88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74179669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.74179669
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.470712123
Short name T31
Test name
Test status
Simulation time 631165417 ps
CPU time 0.67 seconds
Started Jun 22 04:50:23 PM PDT 24
Finished Jun 22 04:50:24 PM PDT 24
Peak memory 192308 kb
Host smart-394ac3fe-0e8a-4b81-99ce-9e9818ba3167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470712123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.470712123
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2210577784
Short name T4
Test name
Test status
Simulation time 1576266097 ps
CPU time 0.69 seconds
Started Jun 22 04:50:25 PM PDT 24
Finished Jun 22 04:50:27 PM PDT 24
Peak memory 192316 kb
Host smart-8113777b-d4a6-44dc-9c5e-990ef10670df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210577784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2210577784
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.4200560415
Short name T205
Test name
Test status
Simulation time 535923937 ps
CPU time 0.79 seconds
Started Jun 22 04:50:30 PM PDT 24
Finished Jun 22 04:50:32 PM PDT 24
Peak memory 192296 kb
Host smart-3b7bc69a-0d3e-4740-9d7b-826da3498dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200560415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.4200560415
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.342837794
Short name T183
Test name
Test status
Simulation time 267050459239 ps
CPU time 400.39 seconds
Started Jun 22 04:50:28 PM PDT 24
Finished Jun 22 04:57:09 PM PDT 24
Peak memory 192420 kb
Host smart-df647371-81ce-427e-ab0d-4b2a33018fab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342837794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.342837794
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2213122665
Short name T244
Test name
Test status
Simulation time 38978264575 ps
CPU time 53.84 seconds
Started Jun 22 04:50:25 PM PDT 24
Finished Jun 22 04:51:19 PM PDT 24
Peak memory 192344 kb
Host smart-4290f33e-9b7d-426d-893e-1f72eddfd8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213122665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2213122665
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1272322488
Short name T1
Test name
Test status
Simulation time 621971594 ps
CPU time 0.7 seconds
Started Jun 22 04:50:32 PM PDT 24
Finished Jun 22 04:50:34 PM PDT 24
Peak memory 197088 kb
Host smart-9f729e12-cf18-4de8-8026-3df7e0882756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272322488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1272322488
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1130596824
Short name T52
Test name
Test status
Simulation time 3131052552 ps
CPU time 3.51 seconds
Started Jun 22 04:50:36 PM PDT 24
Finished Jun 22 04:50:40 PM PDT 24
Peak memory 192424 kb
Host smart-cc738cab-ec06-4e27-8dd2-b4479dee3c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130596824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1130596824
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3321867575
Short name T200
Test name
Test status
Simulation time 568973836 ps
CPU time 0.97 seconds
Started Jun 22 04:50:26 PM PDT 24
Finished Jun 22 04:50:28 PM PDT 24
Peak memory 192232 kb
Host smart-ae8cd9e9-09ca-43c3-8087-da5a92243cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321867575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3321867575
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3073284109
Short name T225
Test name
Test status
Simulation time 17993219125 ps
CPU time 4.83 seconds
Started Jun 22 04:50:31 PM PDT 24
Finished Jun 22 04:50:37 PM PDT 24
Peak memory 191656 kb
Host smart-7b9cf1fd-eed3-4671-9f61-02b536e2749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073284109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3073284109
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3470656789
Short name T251
Test name
Test status
Simulation time 401950740 ps
CPU time 0.73 seconds
Started Jun 22 04:50:36 PM PDT 24
Finished Jun 22 04:50:38 PM PDT 24
Peak memory 192304 kb
Host smart-9636516e-9d92-4e36-858d-bb9af920e473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470656789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3470656789
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1465373093
Short name T62
Test name
Test status
Simulation time 25655591086 ps
CPU time 38.35 seconds
Started Jun 22 04:50:36 PM PDT 24
Finished Jun 22 04:51:16 PM PDT 24
Peak memory 192424 kb
Host smart-f3815964-f144-4054-a6ce-126e7208e332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465373093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1465373093
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3301582857
Short name T237
Test name
Test status
Simulation time 628935520 ps
CPU time 1.02 seconds
Started Jun 22 04:50:28 PM PDT 24
Finished Jun 22 04:50:30 PM PDT 24
Peak memory 197056 kb
Host smart-718f079b-cafb-42fa-b935-fe36730528e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301582857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3301582857
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.4160108315
Short name T48
Test name
Test status
Simulation time 13594592220 ps
CPU time 18.76 seconds
Started Jun 22 04:50:26 PM PDT 24
Finished Jun 22 04:50:46 PM PDT 24
Peak memory 192380 kb
Host smart-21bf5238-bdbc-41c1-b63e-c126d0c5091f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160108315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.4160108315
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2669974645
Short name T259
Test name
Test status
Simulation time 522535504 ps
CPU time 1.02 seconds
Started Jun 22 04:50:27 PM PDT 24
Finished Jun 22 04:50:29 PM PDT 24
Peak memory 197024 kb
Host smart-ae2cabcd-6189-4ecb-bc32-d455119d711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669974645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2669974645
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2993387153
Short name T54
Test name
Test status
Simulation time 48653586502 ps
CPU time 51.78 seconds
Started Jun 22 04:50:01 PM PDT 24
Finished Jun 22 04:50:54 PM PDT 24
Peak memory 192436 kb
Host smart-81989a89-2c89-4568-a12c-4f5bf25c0799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993387153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2993387153
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.4058956764
Short name T267
Test name
Test status
Simulation time 595233973 ps
CPU time 1.06 seconds
Started Jun 22 04:50:02 PM PDT 24
Finished Jun 22 04:50:04 PM PDT 24
Peak memory 197080 kb
Host smart-b21cbf9c-2f9b-415b-bc6e-6334b18f4b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058956764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.4058956764
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2093961439
Short name T255
Test name
Test status
Simulation time 35004661149 ps
CPU time 26.98 seconds
Started Jun 22 04:49:59 PM PDT 24
Finished Jun 22 04:50:27 PM PDT 24
Peak memory 192436 kb
Host smart-fd7ad838-71ee-489f-8ff0-477fc49f7aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093961439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2093961439
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.337896110
Short name T261
Test name
Test status
Simulation time 580749228 ps
CPU time 0.96 seconds
Started Jun 22 04:50:04 PM PDT 24
Finished Jun 22 04:50:06 PM PDT 24
Peak memory 192228 kb
Host smart-8838d20e-3f7b-45d5-bb66-5c667b7dd9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337896110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.337896110
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3053205241
Short name T254
Test name
Test status
Simulation time 46168448497 ps
CPU time 66.3 seconds
Started Jun 22 04:50:02 PM PDT 24
Finished Jun 22 04:51:10 PM PDT 24
Peak memory 192368 kb
Host smart-24f23960-1125-4a24-b1ae-e70c48ad2d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053205241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3053205241
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.131135636
Short name T264
Test name
Test status
Simulation time 527028552 ps
CPU time 0.96 seconds
Started Jun 22 04:50:01 PM PDT 24
Finished Jun 22 04:50:03 PM PDT 24
Peak memory 192296 kb
Host smart-b281f8fd-036a-41f0-a101-3401cf851281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131135636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.131135636
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1842705718
Short name T49
Test name
Test status
Simulation time 48641333179 ps
CPU time 16.65 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:50:18 PM PDT 24
Peak memory 192436 kb
Host smart-b5df3f87-e2d9-407e-b85a-56522204b6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842705718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1842705718
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2113626453
Short name T239
Test name
Test status
Simulation time 440944386 ps
CPU time 0.9 seconds
Started Jun 22 04:50:02 PM PDT 24
Finished Jun 22 04:50:04 PM PDT 24
Peak memory 192328 kb
Host smart-bb3b33b0-45f5-40e8-8331-08a7e5d8a0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113626453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2113626453
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2823431410
Short name T276
Test name
Test status
Simulation time 26592387389 ps
CPU time 34.6 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:50:36 PM PDT 24
Peak memory 192328 kb
Host smart-487f137f-4076-454b-a7e9-153054f46c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823431410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2823431410
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3625343506
Short name T227
Test name
Test status
Simulation time 653758464 ps
CPU time 0.67 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:50:02 PM PDT 24
Peak memory 197092 kb
Host smart-c18372b7-2169-4439-89e5-d5ed044f1665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625343506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3625343506
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1138277524
Short name T185
Test name
Test status
Simulation time 208046500558 ps
CPU time 146.47 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:52:27 PM PDT 24
Peak memory 192412 kb
Host smart-41fb1952-fa29-4e92-94b0-041a340ed1c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138277524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1138277524
Directory /workspace/9.aon_timer_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%