Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	33140	1		T1	11		T2	112		T4	155
bark[1]	826	1		T14	21		T15	21		T46	21
bark[2]	500	1		T13	14		T29	160		T50	14
bark[3]	336	1		T24	82		T47	21		T94	14
bark[4]	236	1		T137	21		T135	21		T111	21
bark[5]	532	1		T14	21		T113	14		T97	26
bark[6]	602	1		T12	26		T31	21		T113	21
bark[7]	1549	1		T15	21		T119	21		T84	285
bark[8]	310	1		T12	21		T22	21		T24	21
bark[9]	547	1		T14	21		T25	14		T40	133
bark[10]	1210	1		T12	35		T137	5		T54	68
bark[11]	634	1		T4	90		T23	51		T52	26
bark[12]	545	1		T22	21		T24	35		T82	26
bark[13]	591	1		T2	50		T40	89		T160	14
bark[14]	489	1		T2	30		T10	14		T119	21
bark[15]	754	1		T24	153		T29	30		T149	21
bark[16]	745	1		T12	30		T24	21		T40	164
bark[17]	529	1		T12	21		T46	31		T54	106
bark[18]	641	1		T3	14		T52	21		T151	14
bark[19]	545	1		T9	14		T12	39		T23	56
bark[20]	703	1		T4	51		T6	35		T14	220
bark[21]	369	1		T5	101		T54	21		T113	21
bark[22]	658	1		T14	237		T33	14		T47	32
bark[23]	630	1		T176	21		T95	21		T97	21
bark[24]	1203	1		T6	40		T41	229		T51	98
bark[25]	140	1		T2	39		T137	26		T155	14
bark[26]	679	1		T6	21		T183	14		T185	14
bark[27]	410	1		T29	21		T156	14		T137	183
bark[28]	524	1		T5	21		T29	21		T158	14
bark[29]	758	1		T14	241		T80	30		T111	21
bark[30]	497	1		T32	14		T14	21		T85	254
bark[31]	206	1		T4	30		T15	52		T23	21
bark_0	4796	1		T1	7		T2	12		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	32907	1		T1	10		T2	112		T4	155
bite[1]	583	1		T46	31		T40	132		T54	88
bite[2]	703	1		T14	21		T33	13		T176	21
bite[3]	888	1		T10	13		T40	184		T135	21
bite[4]	671	1		T14	21		T15	51		T29	21
bite[5]	296	1		T5	100		T29	21		T51	98
bite[6]	188	1		T94	21		T95	94		T82	31
bite[7]	362	1		T12	21		T23	50		T160	13
bite[8]	867	1		T32	13		T47	31		T114	21
bite[9]	1157	1		T4	90		T24	34		T25	13
bite[10]	394	1		T14	219		T135	21		T176	35
bite[11]	571	1		T12	21		T137	182		T54	105
bite[12]	437	1		T15	21		T166	101		T136	30
bite[13]	115	1		T3	13		T23	30		T50	13
bite[14]	270	1		T97	21		T157	13		T101	13
bite[15]	306	1		T47	21		T91	30		T86	224
bite[16]	1129	1		T14	483		T24	25		T29	159
bite[17]	1208	1		T31	21		T22	21		T24	173
bite[18]	363	1		T9	13		T13	13		T41	21
bite[19]	132	1		T6	35		T12	13		T29	21
bite[20]	1029	1		T4	30		T12	26		T23	21
bite[21]	895	1		T2	49		T95	21		T113	21
bite[22]	535	1		T2	39		T6	40		T42	113
bite[23]	494	1		T2	30		T137	26		T185	13
bite[24]	258	1		T12	39		T22	21		T29	30
bite[25]	456	1		T137	21		T81	48		T151	13
bite[26]	835	1		T14	21		T15	21		T156	13
bite[27]	783	1		T40	88		T52	21		T85	227
bite[28]	676	1		T6	21		T12	30		T41	21
bite[29]	266	1		T137	4		T94	60		T97	46
bite[30]	1422	1		T4	50		T12	21		T23	26
bite[31]	353	1		T5	21		T165	75		T149	57
bite_0	5285	1		T1	8		T2	13		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	56834	1		T1	18		T2	243		T3	21

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1503	1		T15	198		T26	58		T40	187
prescale[1]	773	1		T23	9		T24	64		T45	9
prescale[2]	1240	1		T76	9		T22	136		T23	37
prescale[3]	932	1		T22	116		T48	23		T81	28
prescale[4]	1465	1		T8	9		T15	24		T31	2
prescale[5]	1214	1		T5	2		T24	21		T46	40
prescale[6]	772	1		T23	40		T24	2		T192	9
prescale[7]	1146	1		T4	19		T15	80		T48	9
prescale[8]	813	1		T4	27		T5	2		T44	9
prescale[9]	840	1		T2	19		T14	19		T15	19
prescale[10]	1149	1		T5	66		T15	21		T40	183
prescale[11]	838	1		T14	90		T29	65		T42	28
prescale[12]	592	1		T2	19		T14	24		T193	9
prescale[13]	1045	1		T15	82		T42	120		T135	27
prescale[14]	1425	1		T22	61		T40	99		T52	33
prescale[15]	1679	1		T4	19		T5	49		T6	18
prescale[16]	931	1		T15	2		T31	197		T40	2
prescale[17]	829	1		T4	38		T40	2		T47	19
prescale[18]	753	1		T14	9		T41	9		T54	19
prescale[19]	997	1		T4	19		T5	2		T29	2
prescale[20]	583	1		T24	2		T29	2		T41	45
prescale[21]	716	1		T15	2		T31	97		T29	2
prescale[22]	611	1		T22	45		T24	2		T26	19
prescale[23]	1385	1		T11	9		T12	37		T14	115
prescale[24]	498	1		T15	38		T47	57		T41	73
prescale[25]	1057	1		T194	9		T15	2		T24	2
prescale[26]	852	1		T4	24		T24	92		T29	86
prescale[27]	1012	1		T6	19		T14	19		T31	46
prescale[28]	782	1		T12	23		T43	9		T14	87
prescale[29]	728	1		T5	2		T15	21		T31	2
prescale[30]	682	1		T31	2		T24	19		T29	4
prescale[31]	1114	1		T2	23		T5	23		T14	88
prescale_0	25878	1		T1	18		T2	182		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	43513	1		T1	18		T2	181		T3	21
auto[1]	13321	1		T2	62		T4	74		T5	106

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	56834	1		T1	18		T2	243		T3	21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	33601	1		T1	13		T2	161		T3	1
wkup[1]	375	1		T14	56		T31	21		T22	21
wkup[2]	289	1		T9	15		T40	21		T80	21
wkup[3]	219	1		T40	21		T42	15		T83	21
wkup[4]	272	1		T24	21		T29	21		T54	21
wkup[5]	445	1		T23	21		T85	15		T166	21
wkup[6]	264	1		T15	21		T42	30		T137	21
wkup[7]	197	1		T2	21		T14	21		T95	21
wkup[8]	300	1		T4	21		T6	35		T41	21
wkup[9]	292	1		T5	21		T10	15		T22	8
wkup[10]	261	1		T81	21		T97	21		T84	44
wkup[11]	134	1		T85	21		T181	15		T162	21
wkup[12]	427	1		T2	30		T22	15		T40	21
wkup[13]	467	1		T14	21		T22	42		T29	21
wkup[14]	352	1		T31	21		T40	21		T48	21
wkup[15]	439	1		T5	26		T24	21		T47	21
wkup[16]	382	1		T15	21		T31	21		T46	31
wkup[17]	360	1		T6	21		T14	21		T24	21
wkup[18]	347	1		T14	21		T24	30		T26	21
wkup[19]	188	1		T12	21		T14	21		T85	26
wkup[20]	288	1		T12	15		T165	36		T97	30
wkup[21]	229	1		T14	21		T41	31		T118	21
wkup[22]	246	1		T23	21		T24	21		T80	21
wkup[23]	224	1		T14	36		T15	21		T137	6
wkup[24]	455	1		T14	21		T22	21		T24	42
wkup[25]	418	1		T4	30		T24	30		T40	40
wkup[26]	270	1		T5	30		T15	21		T24	21
wkup[27]	394	1		T14	15		T24	26		T29	21
wkup[28]	260	1		T22	21		T40	21		T54	21
wkup[29]	251	1		T42	21		T80	21		T136	15
wkup[30]	243	1		T31	20		T50	15		T107	21
wkup[31]	292	1		T31	21		T40	51		T41	21
wkup[32]	388	1		T14	21		T15	21		T158	15
wkup[33]	272	1		T24	26		T40	21		T111	21
wkup[34]	292	1		T33	15		T15	31		T46	21
wkup[35]	282	1		T12	21		T14	42		T42	42
wkup[36]	334	1		T14	21		T26	21		T29	21
wkup[37]	508	1		T12	30		T23	26		T46	31
wkup[38]	447	1		T12	39		T15	56		T22	21
wkup[39]	312	1		T22	21		T40	21		T54	21
wkup[40]	256	1		T29	21		T80	21		T85	21
wkup[41]	238	1		T15	21		T54	42		T81	21
wkup[42]	296	1		T29	51		T40	30		T41	21
wkup[43]	121	1		T4	21		T14	21		T54	8
wkup[44]	212	1		T14	21		T15	21		T42	8
wkup[45]	339	1		T137	21		T111	21		T167	15
wkup[46]	221	1		T52	30		T164	21		T108	21
wkup[47]	310	1		T29	21		T47	21		T48	21
wkup[48]	396	1		T4	21		T6	30		T41	30
wkup[49]	272	1		T54	21		T85	21		T94	21
wkup[50]	257	1		T12	26		T119	21		T82	21
wkup[51]	351	1		T31	21		T24	30		T54	21
wkup[52]	357	1		T29	20		T40	21		T80	30
wkup[53]	221	1		T14	15		T52	21		T80	42
wkup[54]	186	1		T5	29		T6	21		T22	21
wkup[55]	358	1		T32	15		T15	21		T24	30
wkup[56]	459	1		T14	51		T15	47		T22	21
wkup[57]	277	1		T29	30		T94	21		T83	47
wkup[58]	369	1		T2	21		T3	15		T40	21
wkup[59]	281	1		T13	15		T41	21		T54	21
wkup[60]	238	1		T22	21		T24	21		T29	21
wkup[61]	415	1		T14	40		T15	21		T31	21
wkup[62]	170	1		T12	21		T40	23		T81	21
wkup[63]	417	1		T4	30		T15	21		T22	21
wkup_0	3801	1		T1	5		T2	10		T3	5