Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.49 99.33 93.67 100.00 98.40 99.51 52.07


Total test records in report: 423
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T34 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2237638131 Jun 23 06:06:32 PM PDT 24 Jun 23 06:06:34 PM PDT 24 394225581 ps
T35 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.594939430 Jun 23 06:06:09 PM PDT 24 Jun 23 06:06:22 PM PDT 24 8358393980 ps
T281 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3149854833 Jun 23 06:06:23 PM PDT 24 Jun 23 06:06:26 PM PDT 24 415282184 ps
T36 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2164575094 Jun 23 06:06:28 PM PDT 24 Jun 23 06:06:29 PM PDT 24 974624949 ps
T37 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1531886116 Jun 23 06:05:59 PM PDT 24 Jun 23 06:06:12 PM PDT 24 8652080729 ps
T282 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.864731036 Jun 23 06:06:12 PM PDT 24 Jun 23 06:06:14 PM PDT 24 607341992 ps
T55 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.500775624 Jun 23 06:06:09 PM PDT 24 Jun 23 06:06:10 PM PDT 24 574529745 ps
T68 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2444868440 Jun 23 06:06:20 PM PDT 24 Jun 23 06:06:21 PM PDT 24 451693527 ps
T69 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.729272870 Jun 23 06:06:14 PM PDT 24 Jun 23 06:06:17 PM PDT 24 1472741123 ps
T283 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1639834807 Jun 23 06:06:18 PM PDT 24 Jun 23 06:06:20 PM PDT 24 467371208 ps
T284 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3261495077 Jun 23 06:06:33 PM PDT 24 Jun 23 06:06:34 PM PDT 24 488985881 ps
T70 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2080611893 Jun 23 06:06:18 PM PDT 24 Jun 23 06:06:19 PM PDT 24 1067116338 ps
T71 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2158430790 Jun 23 06:06:27 PM PDT 24 Jun 23 06:06:28 PM PDT 24 2004554505 ps
T285 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2490484448 Jun 23 06:06:32 PM PDT 24 Jun 23 06:06:34 PM PDT 24 501402457 ps
T286 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3865054590 Jun 23 06:06:44 PM PDT 24 Jun 23 06:06:46 PM PDT 24 271707224 ps
T287 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2207349832 Jun 23 06:06:16 PM PDT 24 Jun 23 06:06:18 PM PDT 24 541996435 ps
T72 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1621628546 Jun 23 06:06:20 PM PDT 24 Jun 23 06:06:22 PM PDT 24 1087941589 ps
T288 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3345480379 Jun 23 06:06:23 PM PDT 24 Jun 23 06:06:26 PM PDT 24 461885564 ps
T73 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3880039372 Jun 23 06:06:16 PM PDT 24 Jun 23 06:06:18 PM PDT 24 1324724578 ps
T195 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.76473292 Jun 23 06:06:03 PM PDT 24 Jun 23 06:06:04 PM PDT 24 388980281 ps
T289 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1622052348 Jun 23 06:06:25 PM PDT 24 Jun 23 06:06:26 PM PDT 24 376427647 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3035240492 Jun 23 06:06:12 PM PDT 24 Jun 23 06:06:15 PM PDT 24 699239343 ps
T38 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1311843838 Jun 23 06:06:07 PM PDT 24 Jun 23 06:06:10 PM PDT 24 4359211390 ps
T290 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.285564722 Jun 23 06:06:09 PM PDT 24 Jun 23 06:06:11 PM PDT 24 332779248 ps
T74 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3693724814 Jun 23 06:06:25 PM PDT 24 Jun 23 06:06:30 PM PDT 24 2895506064 ps
T291 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.106708258 Jun 23 06:06:17 PM PDT 24 Jun 23 06:06:18 PM PDT 24 568350600 ps
T75 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.753751856 Jun 23 06:06:14 PM PDT 24 Jun 23 06:06:15 PM PDT 24 459529868 ps
T292 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1839925905 Jun 23 06:06:17 PM PDT 24 Jun 23 06:06:18 PM PDT 24 508632807 ps
T293 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.4016441463 Jun 23 06:06:11 PM PDT 24 Jun 23 06:06:13 PM PDT 24 697508240 ps
T57 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.584864368 Jun 23 06:06:25 PM PDT 24 Jun 23 06:06:26 PM PDT 24 471777215 ps
T58 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3009456173 Jun 23 06:06:01 PM PDT 24 Jun 23 06:06:09 PM PDT 24 10041017651 ps
T294 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1427957986 Jun 23 06:06:29 PM PDT 24 Jun 23 06:06:31 PM PDT 24 436155389 ps
T59 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.564108584 Jun 23 06:06:07 PM PDT 24 Jun 23 06:06:09 PM PDT 24 587403755 ps
T295 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2947013480 Jun 23 06:06:28 PM PDT 24 Jun 23 06:06:30 PM PDT 24 2217539252 ps
T296 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1681469399 Jun 23 06:06:11 PM PDT 24 Jun 23 06:06:12 PM PDT 24 277128713 ps
T297 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3899406549 Jun 23 06:06:12 PM PDT 24 Jun 23 06:06:14 PM PDT 24 1266433942 ps
T298 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3441641692 Jun 23 06:06:23 PM PDT 24 Jun 23 06:06:26 PM PDT 24 564507649 ps
T299 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.49665691 Jun 23 06:06:03 PM PDT 24 Jun 23 06:06:04 PM PDT 24 459664031 ps
T300 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1354864316 Jun 23 06:06:15 PM PDT 24 Jun 23 06:06:17 PM PDT 24 562382001 ps
T301 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2450357425 Jun 23 06:06:28 PM PDT 24 Jun 23 06:06:30 PM PDT 24 473531357 ps
T302 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.4153960634 Jun 23 06:06:23 PM PDT 24 Jun 23 06:06:26 PM PDT 24 807991282 ps
T303 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2470686791 Jun 23 06:06:04 PM PDT 24 Jun 23 06:06:06 PM PDT 24 734216085 ps
T304 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2461749551 Jun 23 06:06:12 PM PDT 24 Jun 23 06:06:13 PM PDT 24 527865778 ps
T189 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3087066357 Jun 23 06:06:25 PM PDT 24 Jun 23 06:06:33 PM PDT 24 8206421448 ps
T305 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3318719541 Jun 23 06:06:12 PM PDT 24 Jun 23 06:06:13 PM PDT 24 295949518 ps
T306 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1277244428 Jun 23 06:06:12 PM PDT 24 Jun 23 06:06:14 PM PDT 24 342937600 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2954688549 Jun 23 06:06:12 PM PDT 24 Jun 23 06:06:18 PM PDT 24 6331656389 ps
T61 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1089396557 Jun 23 06:06:12 PM PDT 24 Jun 23 06:06:15 PM PDT 24 1185588918 ps
T307 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.747266509 Jun 23 06:06:31 PM PDT 24 Jun 23 06:06:32 PM PDT 24 366648497 ps
T308 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1185531723 Jun 23 06:06:18 PM PDT 24 Jun 23 06:06:20 PM PDT 24 391771636 ps
T309 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1102029086 Jun 23 06:06:19 PM PDT 24 Jun 23 06:06:20 PM PDT 24 355468006 ps
T310 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.101023751 Jun 23 06:06:15 PM PDT 24 Jun 23 06:06:16 PM PDT 24 483450042 ps
T311 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2653849394 Jun 23 06:06:20 PM PDT 24 Jun 23 06:06:21 PM PDT 24 335422971 ps
T312 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.759299920 Jun 23 06:06:24 PM PDT 24 Jun 23 06:06:26 PM PDT 24 367482349 ps
T313 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1931840858 Jun 23 06:06:00 PM PDT 24 Jun 23 06:06:03 PM PDT 24 2532683059 ps
T314 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3923449728 Jun 23 06:06:22 PM PDT 24 Jun 23 06:06:24 PM PDT 24 353816015 ps
T315 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3550980929 Jun 23 06:06:00 PM PDT 24 Jun 23 06:06:01 PM PDT 24 303912564 ps
T316 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3622027209 Jun 23 06:06:12 PM PDT 24 Jun 23 06:06:19 PM PDT 24 7855968224 ps
T317 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2319564872 Jun 23 06:06:18 PM PDT 24 Jun 23 06:06:19 PM PDT 24 545080468 ps
T318 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3391394832 Jun 23 06:06:29 PM PDT 24 Jun 23 06:06:31 PM PDT 24 566653996 ps
T319 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3881025483 Jun 23 06:06:18 PM PDT 24 Jun 23 06:06:20 PM PDT 24 441127186 ps
T64 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3316178801 Jun 23 06:06:10 PM PDT 24 Jun 23 06:06:11 PM PDT 24 419936554 ps
T320 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2728377933 Jun 23 06:06:19 PM PDT 24 Jun 23 06:06:34 PM PDT 24 8543365643 ps
T321 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.941758164 Jun 23 06:06:33 PM PDT 24 Jun 23 06:06:36 PM PDT 24 403459103 ps
T322 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.545439069 Jun 23 06:06:30 PM PDT 24 Jun 23 06:06:31 PM PDT 24 381492384 ps
T323 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.340343231 Jun 23 06:06:29 PM PDT 24 Jun 23 06:06:31 PM PDT 24 449196652 ps
T324 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.669469425 Jun 23 06:06:36 PM PDT 24 Jun 23 06:06:38 PM PDT 24 386444892 ps
T62 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3956465128 Jun 23 06:06:01 PM PDT 24 Jun 23 06:06:05 PM PDT 24 4599085971 ps
T65 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2433417643 Jun 23 06:06:09 PM PDT 24 Jun 23 06:06:17 PM PDT 24 13138421807 ps
T325 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2190755348 Jun 23 06:06:16 PM PDT 24 Jun 23 06:06:18 PM PDT 24 632948089 ps
T326 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1069504026 Jun 23 06:06:22 PM PDT 24 Jun 23 06:06:25 PM PDT 24 545835089 ps
T327 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3208329824 Jun 23 06:06:27 PM PDT 24 Jun 23 06:06:28 PM PDT 24 548705688 ps
T328 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.563873804 Jun 23 06:06:05 PM PDT 24 Jun 23 06:06:07 PM PDT 24 462551022 ps
T66 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3944865102 Jun 23 06:06:00 PM PDT 24 Jun 23 06:06:02 PM PDT 24 629651269 ps
T329 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.536643991 Jun 23 06:06:09 PM PDT 24 Jun 23 06:06:10 PM PDT 24 1217726870 ps
T330 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.231352715 Jun 23 06:06:02 PM PDT 24 Jun 23 06:06:04 PM PDT 24 373636762 ps
T331 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3198579679 Jun 23 06:06:32 PM PDT 24 Jun 23 06:06:33 PM PDT 24 397606834 ps
T332 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.898465757 Jun 23 06:06:07 PM PDT 24 Jun 23 06:06:10 PM PDT 24 4685835200 ps
T333 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4050712759 Jun 23 06:06:03 PM PDT 24 Jun 23 06:06:08 PM PDT 24 8674070855 ps
T334 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4290134614 Jun 23 06:06:07 PM PDT 24 Jun 23 06:06:08 PM PDT 24 1306639803 ps
T335 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3036113363 Jun 23 06:06:28 PM PDT 24 Jun 23 06:06:29 PM PDT 24 498605652 ps
T336 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3819259558 Jun 23 06:06:05 PM PDT 24 Jun 23 06:06:06 PM PDT 24 338631215 ps
T337 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1277819790 Jun 23 06:06:23 PM PDT 24 Jun 23 06:06:24 PM PDT 24 365854713 ps
T338 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1764036846 Jun 23 06:06:28 PM PDT 24 Jun 23 06:06:30 PM PDT 24 455003871 ps
T339 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2719829343 Jun 23 06:06:04 PM PDT 24 Jun 23 06:06:06 PM PDT 24 1977160997 ps
T340 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1568632496 Jun 23 06:06:16 PM PDT 24 Jun 23 06:06:19 PM PDT 24 474640774 ps
T341 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3090535687 Jun 23 06:06:32 PM PDT 24 Jun 23 06:06:34 PM PDT 24 299055923 ps
T342 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1968963461 Jun 23 06:06:30 PM PDT 24 Jun 23 06:06:31 PM PDT 24 393360324 ps
T343 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2811195818 Jun 23 06:06:39 PM PDT 24 Jun 23 06:06:41 PM PDT 24 520333808 ps
T344 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.554919681 Jun 23 06:06:29 PM PDT 24 Jun 23 06:06:31 PM PDT 24 512439965 ps
T345 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1114244826 Jun 23 06:06:35 PM PDT 24 Jun 23 06:06:36 PM PDT 24 380370954 ps
T346 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2515437576 Jun 23 06:06:21 PM PDT 24 Jun 23 06:06:33 PM PDT 24 8258197712 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3612785534 Jun 23 06:06:01 PM PDT 24 Jun 23 06:06:02 PM PDT 24 276323204 ps
T348 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4247399781 Jun 23 06:06:34 PM PDT 24 Jun 23 06:06:36 PM PDT 24 523281469 ps
T349 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4290324430 Jun 23 06:06:00 PM PDT 24 Jun 23 06:06:03 PM PDT 24 4348693870 ps
T350 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3160227422 Jun 23 06:06:03 PM PDT 24 Jun 23 06:06:04 PM PDT 24 403779397 ps
T351 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2847257845 Jun 23 06:06:19 PM PDT 24 Jun 23 06:06:21 PM PDT 24 2350366530 ps
T352 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1015457441 Jun 23 06:06:13 PM PDT 24 Jun 23 06:06:15 PM PDT 24 538532102 ps
T353 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1191425458 Jun 23 06:06:11 PM PDT 24 Jun 23 06:06:12 PM PDT 24 471480457 ps
T354 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2496745668 Jun 23 06:06:02 PM PDT 24 Jun 23 06:06:04 PM PDT 24 1089989540 ps
T355 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1625256273 Jun 23 06:06:34 PM PDT 24 Jun 23 06:06:36 PM PDT 24 368562563 ps
T356 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.910462214 Jun 23 06:06:12 PM PDT 24 Jun 23 06:06:14 PM PDT 24 462731206 ps
T357 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.347246284 Jun 23 06:06:13 PM PDT 24 Jun 23 06:06:14 PM PDT 24 308306210 ps
T358 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4101847804 Jun 23 06:06:00 PM PDT 24 Jun 23 06:06:01 PM PDT 24 379721502 ps
T359 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.910423879 Jun 23 06:06:22 PM PDT 24 Jun 23 06:06:24 PM PDT 24 400823809 ps
T360 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3646021023 Jun 23 06:06:05 PM PDT 24 Jun 23 06:06:07 PM PDT 24 826825263 ps
T361 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3400019465 Jun 23 06:06:32 PM PDT 24 Jun 23 06:06:34 PM PDT 24 381231825 ps
T362 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2541044827 Jun 23 06:06:16 PM PDT 24 Jun 23 06:06:20 PM PDT 24 3089888450 ps
T363 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.902979941 Jun 23 06:06:33 PM PDT 24 Jun 23 06:06:35 PM PDT 24 351099682 ps
T364 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2261607978 Jun 23 06:06:35 PM PDT 24 Jun 23 06:06:37 PM PDT 24 410763587 ps
T365 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.319177763 Jun 23 06:06:19 PM PDT 24 Jun 23 06:06:21 PM PDT 24 427181539 ps
T366 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3261199838 Jun 23 06:06:04 PM PDT 24 Jun 23 06:06:05 PM PDT 24 384576151 ps
T367 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.354721241 Jun 23 06:06:28 PM PDT 24 Jun 23 06:06:30 PM PDT 24 410401444 ps
T368 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1664272547 Jun 23 06:06:17 PM PDT 24 Jun 23 06:06:20 PM PDT 24 537249957 ps
T369 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3114577073 Jun 23 06:06:24 PM PDT 24 Jun 23 06:06:25 PM PDT 24 430075130 ps
T370 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2850753378 Jun 23 06:06:02 PM PDT 24 Jun 23 06:06:03 PM PDT 24 489294306 ps
T371 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.882176502 Jun 23 06:06:03 PM PDT 24 Jun 23 06:06:04 PM PDT 24 561119153 ps
T372 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2002294101 Jun 23 06:06:26 PM PDT 24 Jun 23 06:06:27 PM PDT 24 563834321 ps
T67 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.880934634 Jun 23 06:06:09 PM PDT 24 Jun 23 06:06:10 PM PDT 24 425141931 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4081364855 Jun 23 06:06:00 PM PDT 24 Jun 23 06:06:03 PM PDT 24 1333837567 ps
T374 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4285900297 Jun 23 06:06:29 PM PDT 24 Jun 23 06:06:31 PM PDT 24 322454233 ps
T375 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.443368676 Jun 23 06:06:34 PM PDT 24 Jun 23 06:06:36 PM PDT 24 371029336 ps
T376 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1949899717 Jun 23 06:06:09 PM PDT 24 Jun 23 06:06:10 PM PDT 24 284588378 ps
T377 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4163736914 Jun 23 06:06:44 PM PDT 24 Jun 23 06:06:46 PM PDT 24 514912264 ps
T190 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3457494787 Jun 23 06:06:23 PM PDT 24 Jun 23 06:06:26 PM PDT 24 4858390404 ps
T378 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1758688551 Jun 23 06:06:29 PM PDT 24 Jun 23 06:06:30 PM PDT 24 281374120 ps
T379 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.352727890 Jun 23 06:06:30 PM PDT 24 Jun 23 06:06:31 PM PDT 24 573716380 ps
T380 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3102730789 Jun 23 06:06:12 PM PDT 24 Jun 23 06:06:15 PM PDT 24 8853176906 ps
T381 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2947817389 Jun 23 06:06:10 PM PDT 24 Jun 23 06:06:11 PM PDT 24 382520704 ps
T382 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3415559567 Jun 23 06:06:28 PM PDT 24 Jun 23 06:06:30 PM PDT 24 4301050830 ps
T383 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1398933820 Jun 23 06:06:20 PM PDT 24 Jun 23 06:06:28 PM PDT 24 3246928004 ps
T384 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3464480418 Jun 23 06:06:26 PM PDT 24 Jun 23 06:06:27 PM PDT 24 319567473 ps
T385 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1307524690 Jun 23 06:06:37 PM PDT 24 Jun 23 06:06:38 PM PDT 24 269757205 ps
T386 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2178656881 Jun 23 06:06:04 PM PDT 24 Jun 23 06:06:06 PM PDT 24 437797703 ps
T387 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1438603078 Jun 23 06:06:40 PM PDT 24 Jun 23 06:06:41 PM PDT 24 309221799 ps
T388 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1141670304 Jun 23 06:06:23 PM PDT 24 Jun 23 06:06:25 PM PDT 24 505157237 ps
T389 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2249869494 Jun 23 06:06:00 PM PDT 24 Jun 23 06:06:02 PM PDT 24 388978479 ps
T390 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3466847390 Jun 23 06:06:19 PM PDT 24 Jun 23 06:06:23 PM PDT 24 2522854914 ps
T391 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3824395781 Jun 23 06:06:13 PM PDT 24 Jun 23 06:06:15 PM PDT 24 4728797952 ps
T392 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4107715193 Jun 23 06:06:24 PM PDT 24 Jun 23 06:06:26 PM PDT 24 487084020 ps
T393 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3992792981 Jun 23 06:06:16 PM PDT 24 Jun 23 06:06:17 PM PDT 24 323908494 ps
T394 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2147504084 Jun 23 06:06:36 PM PDT 24 Jun 23 06:06:37 PM PDT 24 301976187 ps
T395 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.158141693 Jun 23 06:06:06 PM PDT 24 Jun 23 06:06:08 PM PDT 24 1468210956 ps
T396 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3249872847 Jun 23 06:06:15 PM PDT 24 Jun 23 06:06:22 PM PDT 24 4098536613 ps
T397 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.353199785 Jun 23 06:06:00 PM PDT 24 Jun 23 06:06:02 PM PDT 24 382190229 ps
T398 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.557435354 Jun 23 06:06:22 PM PDT 24 Jun 23 06:06:24 PM PDT 24 357540646 ps
T399 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2618449954 Jun 23 06:06:16 PM PDT 24 Jun 23 06:06:17 PM PDT 24 493509842 ps
T400 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4042177935 Jun 23 06:06:32 PM PDT 24 Jun 23 06:06:34 PM PDT 24 2456988947 ps
T401 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2931171352 Jun 23 06:06:00 PM PDT 24 Jun 23 06:06:02 PM PDT 24 359408088 ps
T402 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4160564243 Jun 23 06:06:14 PM PDT 24 Jun 23 06:06:15 PM PDT 24 362850929 ps
T403 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.291902450 Jun 23 06:06:13 PM PDT 24 Jun 23 06:06:16 PM PDT 24 4492228957 ps
T63 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3251914477 Jun 23 06:06:17 PM PDT 24 Jun 23 06:06:18 PM PDT 24 409214163 ps
T404 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.963740846 Jun 23 06:06:37 PM PDT 24 Jun 23 06:06:38 PM PDT 24 353365565 ps
T191 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2401200109 Jun 23 06:06:33 PM PDT 24 Jun 23 06:06:41 PM PDT 24 4012715068 ps
T405 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2587929454 Jun 23 06:06:14 PM PDT 24 Jun 23 06:06:15 PM PDT 24 418576908 ps
T406 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.306918771 Jun 23 06:06:24 PM PDT 24 Jun 23 06:06:37 PM PDT 24 8663457126 ps
T407 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.886240888 Jun 23 06:06:31 PM PDT 24 Jun 23 06:06:35 PM PDT 24 2132881573 ps
T408 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2180370560 Jun 23 06:06:11 PM PDT 24 Jun 23 06:06:12 PM PDT 24 456078979 ps
T409 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4287329515 Jun 23 06:06:06 PM PDT 24 Jun 23 06:06:10 PM PDT 24 545888672 ps
T410 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1113058177 Jun 23 06:06:14 PM PDT 24 Jun 23 06:06:16 PM PDT 24 429663705 ps
T411 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2388835432 Jun 23 06:06:22 PM PDT 24 Jun 23 06:06:28 PM PDT 24 7771941288 ps
T412 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.704939184 Jun 23 06:06:16 PM PDT 24 Jun 23 06:06:20 PM PDT 24 4317169636 ps
T413 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4027854644 Jun 23 06:06:34 PM PDT 24 Jun 23 06:06:35 PM PDT 24 344569654 ps
T414 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2601994995 Jun 23 06:06:24 PM PDT 24 Jun 23 06:06:36 PM PDT 24 8265356765 ps
T415 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.248135994 Jun 23 06:06:28 PM PDT 24 Jun 23 06:06:29 PM PDT 24 550426896 ps
T416 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2483616778 Jun 23 06:06:36 PM PDT 24 Jun 23 06:06:38 PM PDT 24 415929856 ps
T417 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3670025265 Jun 23 06:06:16 PM PDT 24 Jun 23 06:06:18 PM PDT 24 317059212 ps
T418 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3335304117 Jun 23 06:06:06 PM PDT 24 Jun 23 06:06:07 PM PDT 24 417260131 ps
T419 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2678000164 Jun 23 06:05:58 PM PDT 24 Jun 23 06:06:00 PM PDT 24 295205782 ps
T420 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2934939819 Jun 23 06:06:03 PM PDT 24 Jun 23 06:06:05 PM PDT 24 494811726 ps
T421 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.447693091 Jun 23 06:06:25 PM PDT 24 Jun 23 06:06:27 PM PDT 24 699121034 ps
T422 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3628741171 Jun 23 06:06:32 PM PDT 24 Jun 23 06:06:34 PM PDT 24 355204006 ps
T423 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.4201298927 Jun 23 06:06:18 PM PDT 24 Jun 23 06:06:22 PM PDT 24 2211190011 ps

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2771998424
Short name T5
Test name
Test status
Simulation time 169286527377 ps
CPU time 193.82 seconds
Started Jun 23 06:05:15 PM PDT 24
Finished Jun 23 06:08:30 PM PDT 24
Peak memory 214852 kb
Host smart-5d139ff5-dedf-4298-a5b6-cfea41bccb72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771998424 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2771998424
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.662377556
Short name T12
Test name
Test status
Simulation time 173454033596 ps
CPU time 233.74 seconds
Started Jun 23 06:05:42 PM PDT 24
Finished Jun 23 06:09:36 PM PDT 24
Peak memory 193552 kb
Host smart-bbff4b00-bea5-41ef-8e41-7f3981e8445c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662377556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.662377556
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.594939430
Short name T35
Test name
Test status
Simulation time 8358393980 ps
CPU time 12.49 seconds
Started Jun 23 06:06:09 PM PDT 24
Finished Jun 23 06:06:22 PM PDT 24
Peak memory 198076 kb
Host smart-3836d0a1-6878-420d-a075-a19cfdd7af18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594939430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.594939430
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1218061447
Short name T40
Test name
Test status
Simulation time 242033524031 ps
CPU time 670.78 seconds
Started Jun 23 06:05:50 PM PDT 24
Finished Jun 23 06:17:01 PM PDT 24
Peak memory 215504 kb
Host smart-28f38ff2-f3bd-45e1-b215-83756c274cee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218061447 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1218061447
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.697261989
Short name T115
Test name
Test status
Simulation time 449534700216 ps
CPU time 1195.66 seconds
Started Jun 23 06:05:37 PM PDT 24
Finished Jun 23 06:25:33 PM PDT 24
Peak memory 214292 kb
Host smart-14449a12-feef-4e87-8be7-d949c4f2dd5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697261989 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.697261989
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1457199506
Short name T54
Test name
Test status
Simulation time 994576440949 ps
CPU time 474.69 seconds
Started Jun 23 06:05:29 PM PDT 24
Finished Jun 23 06:13:24 PM PDT 24
Peak memory 203868 kb
Host smart-e9694a3f-1043-4ba1-a130-1878d1303502
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457199506 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1457199506
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2506713357
Short name T24
Test name
Test status
Simulation time 165584022331 ps
CPU time 448.09 seconds
Started Jun 23 06:05:41 PM PDT 24
Finished Jun 23 06:13:09 PM PDT 24
Peak memory 204300 kb
Host smart-1825d105-c645-4d61-8d84-cfef3b8e03d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506713357 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2506713357
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.425372024
Short name T129
Test name
Test status
Simulation time 264094026125 ps
CPU time 757.92 seconds
Started Jun 23 06:05:49 PM PDT 24
Finished Jun 23 06:18:27 PM PDT 24
Peak memory 208488 kb
Host smart-8a999b97-71c1-4b6c-8830-56183f0db832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425372024 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.425372024
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3848166456
Short name T79
Test name
Test status
Simulation time 406664006851 ps
CPU time 749.03 seconds
Started Jun 23 06:05:38 PM PDT 24
Finished Jun 23 06:18:08 PM PDT 24
Peak memory 215268 kb
Host smart-96ea1922-ab9c-471c-9fb5-8a251e90a3c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848166456 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3848166456
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.218202780
Short name T84
Test name
Test status
Simulation time 177799105893 ps
CPU time 328.73 seconds
Started Jun 23 06:05:45 PM PDT 24
Finished Jun 23 06:11:14 PM PDT 24
Peak memory 215528 kb
Host smart-182919d3-ea22-4b5c-8088-c593e4742f09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218202780 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.218202780
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3837084639
Short name T86
Test name
Test status
Simulation time 186641965678 ps
CPU time 535.47 seconds
Started Jun 23 06:05:49 PM PDT 24
Finished Jun 23 06:14:44 PM PDT 24
Peak memory 213804 kb
Host smart-b19ce7f5-49dc-48e3-be9d-cf2db86bd66a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837084639 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3837084639
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.4078205335
Short name T17
Test name
Test status
Simulation time 7900311221 ps
CPU time 10.97 seconds
Started Jun 23 06:05:15 PM PDT 24
Finished Jun 23 06:05:27 PM PDT 24
Peak memory 216400 kb
Host smart-e427e8fa-d0f8-48b8-ae59-f6ac9e0ae285
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078205335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4078205335
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2448752768
Short name T6
Test name
Test status
Simulation time 88654810001 ps
CPU time 12.08 seconds
Started Jun 23 06:06:04 PM PDT 24
Finished Jun 23 06:06:17 PM PDT 24
Peak memory 192344 kb
Host smart-96da9a13-4398-41b5-9d9c-d084736c25fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448752768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2448752768
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.609655333
Short name T113
Test name
Test status
Simulation time 25294156159 ps
CPU time 9.75 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:05:56 PM PDT 24
Peak memory 198748 kb
Host smart-8fcc1102-5b21-4cc8-a01f-c1182d695f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609655333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.609655333
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3491525726
Short name T14
Test name
Test status
Simulation time 205762728682 ps
CPU time 81.16 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:07:08 PM PDT 24
Peak memory 214528 kb
Host smart-1caf7672-48e8-4c20-a42c-4d34e01341be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491525726 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3491525726
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3204201613
Short name T91
Test name
Test status
Simulation time 268122925076 ps
CPU time 170.91 seconds
Started Jun 23 06:05:21 PM PDT 24
Finished Jun 23 06:08:12 PM PDT 24
Peak memory 192996 kb
Host smart-25930772-5ea4-41d1-807d-8f1f8201ab7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204201613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3204201613
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2976319418
Short name T101
Test name
Test status
Simulation time 176758745400 ps
CPU time 113.58 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:07:42 PM PDT 24
Peak memory 192436 kb
Host smart-adeb1055-c171-4e99-a864-ea18f2ed0ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976319418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2976319418
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2428233840
Short name T95
Test name
Test status
Simulation time 253992731129 ps
CPU time 385.84 seconds
Started Jun 23 06:05:54 PM PDT 24
Finished Jun 23 06:12:21 PM PDT 24
Peak memory 211536 kb
Host smart-20418d7f-055c-4661-b794-fd2e6d3de8c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428233840 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2428233840
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.775415910
Short name T119
Test name
Test status
Simulation time 131908555959 ps
CPU time 287.79 seconds
Started Jun 23 06:05:34 PM PDT 24
Finished Jun 23 06:10:22 PM PDT 24
Peak memory 210224 kb
Host smart-b867b56a-3543-444f-86d1-e08b40409150
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775415910 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.775415910
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.792738496
Short name T149
Test name
Test status
Simulation time 52981853314 ps
CPU time 443.22 seconds
Started Jun 23 06:05:45 PM PDT 24
Finished Jun 23 06:13:08 PM PDT 24
Peak memory 207352 kb
Host smart-3af9a131-5db3-424d-a5da-c2273dc27ed7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792738496 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.792738496
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2918675761
Short name T97
Test name
Test status
Simulation time 57272404534 ps
CPU time 444.55 seconds
Started Jun 23 06:05:56 PM PDT 24
Finished Jun 23 06:13:21 PM PDT 24
Peak memory 215376 kb
Host smart-8897af15-42b1-46a8-9535-2ac7b092efeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918675761 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2918675761
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2021312672
Short name T132
Test name
Test status
Simulation time 91404670550 ps
CPU time 32.43 seconds
Started Jun 23 06:05:24 PM PDT 24
Finished Jun 23 06:05:57 PM PDT 24
Peak memory 198700 kb
Host smart-852c8183-423f-4cbf-92ba-ec36848b5ede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021312672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2021312672
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3317373921
Short name T162
Test name
Test status
Simulation time 751737812034 ps
CPU time 855.8 seconds
Started Jun 23 06:05:37 PM PDT 24
Finished Jun 23 06:19:54 PM PDT 24
Peak memory 215428 kb
Host smart-c738fee0-888e-47da-bc10-9d82917e3815
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317373921 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3317373921
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.532984148
Short name T121
Test name
Test status
Simulation time 55825610039 ps
CPU time 585.19 seconds
Started Jun 23 06:05:55 PM PDT 24
Finished Jun 23 06:15:41 PM PDT 24
Peak memory 207384 kb
Host smart-ef9acf4f-a8e3-4315-826b-cf357ae0cf80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532984148 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.532984148
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.499303853
Short name T107
Test name
Test status
Simulation time 52811153063 ps
CPU time 431.67 seconds
Started Jun 23 06:05:35 PM PDT 24
Finished Jun 23 06:12:47 PM PDT 24
Peak memory 201260 kb
Host smart-ccde876b-f8db-42de-af79-30e9998b6bbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499303853 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.499303853
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2307705843
Short name T96
Test name
Test status
Simulation time 191164633938 ps
CPU time 223.98 seconds
Started Jun 23 06:05:24 PM PDT 24
Finished Jun 23 06:09:09 PM PDT 24
Peak memory 209240 kb
Host smart-7cda6a13-4351-44bb-b657-bfeafd81c5af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307705843 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2307705843
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.4168810053
Short name T46
Test name
Test status
Simulation time 208416917004 ps
CPU time 287.05 seconds
Started Jun 23 06:05:36 PM PDT 24
Finished Jun 23 06:10:23 PM PDT 24
Peak memory 198812 kb
Host smart-30892c9e-db51-4fdd-bf47-3b75de88380b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168810053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.4168810053
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1688301365
Short name T87
Test name
Test status
Simulation time 259712725610 ps
CPU time 104.65 seconds
Started Jun 23 06:05:35 PM PDT 24
Finished Jun 23 06:07:20 PM PDT 24
Peak memory 193196 kb
Host smart-b008bc48-f819-4dd7-8ba7-8c6a0d1e6f0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688301365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1688301365
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2219288922
Short name T110
Test name
Test status
Simulation time 93034122980 ps
CPU time 73.21 seconds
Started Jun 23 06:05:40 PM PDT 24
Finished Jun 23 06:06:54 PM PDT 24
Peak memory 193132 kb
Host smart-4736d430-712f-442e-81ff-8a9997f29341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219288922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2219288922
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2596499631
Short name T15
Test name
Test status
Simulation time 143461204645 ps
CPU time 494.11 seconds
Started Jun 23 06:05:28 PM PDT 24
Finished Jun 23 06:13:43 PM PDT 24
Peak memory 213856 kb
Host smart-069e6ffc-b9cb-4ea5-a230-9be9ec42aa70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596499631 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2596499631
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1856875660
Short name T29
Test name
Test status
Simulation time 231594548421 ps
CPU time 474.76 seconds
Started Jun 23 06:05:43 PM PDT 24
Finished Jun 23 06:13:38 PM PDT 24
Peak memory 211940 kb
Host smart-c0954c45-a0fb-427f-b951-f716901406ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856875660 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1856875660
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3046369877
Short name T90
Test name
Test status
Simulation time 146122104148 ps
CPU time 102.83 seconds
Started Jun 23 06:05:19 PM PDT 24
Finished Jun 23 06:07:03 PM PDT 24
Peak memory 198772 kb
Host smart-0d68fee2-6e95-4cbe-a3fb-07767b8941b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046369877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3046369877
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3021940354
Short name T22
Test name
Test status
Simulation time 47436947289 ps
CPU time 95.9 seconds
Started Jun 23 06:05:16 PM PDT 24
Finished Jun 23 06:06:52 PM PDT 24
Peak memory 215532 kb
Host smart-ddf46207-cdd4-4e65-879b-ecd6cb202cc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021940354 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3021940354
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2609985788
Short name T143
Test name
Test status
Simulation time 161460952208 ps
CPU time 588.18 seconds
Started Jun 23 06:05:41 PM PDT 24
Finished Jun 23 06:15:30 PM PDT 24
Peak memory 205596 kb
Host smart-91bc8e8d-6b89-4ab8-819c-ec7d5a586d50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609985788 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2609985788
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3009456173
Short name T58
Test name
Test status
Simulation time 10041017651 ps
CPU time 7.66 seconds
Started Jun 23 06:06:01 PM PDT 24
Finished Jun 23 06:06:09 PM PDT 24
Peak memory 192100 kb
Host smart-7a3d4f8a-15ab-4779-8271-c81be3d4899e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009456173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3009456173
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1944410123
Short name T94
Test name
Test status
Simulation time 14229867804 ps
CPU time 5.63 seconds
Started Jun 23 06:06:00 PM PDT 24
Finished Jun 23 06:06:06 PM PDT 24
Peak memory 193132 kb
Host smart-aee153d2-54d2-4785-aa06-23173ff9e4d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944410123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1944410123
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1163274668
Short name T109
Test name
Test status
Simulation time 54772765499 ps
CPU time 79.41 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:07:06 PM PDT 24
Peak memory 192992 kb
Host smart-058c36c1-74ef-44d2-a2f3-cef4e15fba3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163274668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1163274668
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4262345746
Short name T104
Test name
Test status
Simulation time 41857118603 ps
CPU time 32.21 seconds
Started Jun 23 06:05:29 PM PDT 24
Finished Jun 23 06:06:01 PM PDT 24
Peak memory 192452 kb
Host smart-f4abd608-e959-4ae6-9a22-d6a61c4ba826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262345746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4262345746
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2292721731
Short name T118
Test name
Test status
Simulation time 92065281110 ps
CPU time 72.54 seconds
Started Jun 23 06:05:19 PM PDT 24
Finished Jun 23 06:06:32 PM PDT 24
Peak memory 198776 kb
Host smart-7caf3748-fcff-443d-9295-97909cff6ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292721731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2292721731
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.327679833
Short name T108
Test name
Test status
Simulation time 101935203296 ps
CPU time 149.25 seconds
Started Jun 23 06:05:26 PM PDT 24
Finished Jun 23 06:07:56 PM PDT 24
Peak memory 198804 kb
Host smart-29128939-ad33-45de-8bff-db8ec7fd5060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327679833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.327679833
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.806162467
Short name T102
Test name
Test status
Simulation time 13725990303 ps
CPU time 20.6 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:06:07 PM PDT 24
Peak memory 184700 kb
Host smart-24891db0-a12c-4039-b856-97fae074cbb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806162467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.806162467
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1693553450
Short name T111
Test name
Test status
Simulation time 90429666575 ps
CPU time 719.47 seconds
Started Jun 23 06:05:52 PM PDT 24
Finished Jun 23 06:17:52 PM PDT 24
Peak memory 206924 kb
Host smart-6a3eacda-1b1d-4c81-8eaa-fbe3c62c36cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693553450 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1693553450
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1128267489
Short name T137
Test name
Test status
Simulation time 10790474543 ps
CPU time 54.68 seconds
Started Jun 23 06:05:34 PM PDT 24
Finished Jun 23 06:06:29 PM PDT 24
Peak memory 199132 kb
Host smart-3174aefe-f926-4afe-b7ee-4842a6fb7cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128267489 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1128267489
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1210316213
Short name T83
Test name
Test status
Simulation time 200609579079 ps
CPU time 386.7 seconds
Started Jun 23 06:05:28 PM PDT 24
Finished Jun 23 06:11:55 PM PDT 24
Peak memory 211128 kb
Host smart-cce00f0b-c9ab-4c64-ac11-2bb3c89ebd5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210316213 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1210316213
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.4139217113
Short name T134
Test name
Test status
Simulation time 168364458521 ps
CPU time 295.56 seconds
Started Jun 23 06:05:35 PM PDT 24
Finished Jun 23 06:10:31 PM PDT 24
Peak memory 202008 kb
Host smart-37b753eb-5941-4a69-84bd-55f95c577a64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139217113 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.4139217113
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.489935780
Short name T78
Test name
Test status
Simulation time 99989628598 ps
CPU time 264.3 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:10:11 PM PDT 24
Peak memory 206512 kb
Host smart-8574fc8c-c37d-493c-a523-a8eb8574ee6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489935780 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.489935780
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.47454545
Short name T159
Test name
Test status
Simulation time 132579004949 ps
CPU time 47.24 seconds
Started Jun 23 06:05:23 PM PDT 24
Finished Jun 23 06:06:11 PM PDT 24
Peak memory 192960 kb
Host smart-51e52819-7b10-42d2-aa0d-efab3e6f4af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47454545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_al
l.47454545
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3826471457
Short name T41
Test name
Test status
Simulation time 28223783224 ps
CPU time 224.03 seconds
Started Jun 23 06:05:24 PM PDT 24
Finished Jun 23 06:09:08 PM PDT 24
Peak memory 207560 kb
Host smart-dced8d13-5b8c-4dd5-a2d0-738e62b7baab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826471457 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3826471457
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1834801719
Short name T141
Test name
Test status
Simulation time 104882222895 ps
CPU time 156.91 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:08:24 PM PDT 24
Peak memory 192456 kb
Host smart-7e54d1f7-e0aa-48d8-9778-8493d75e5d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834801719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1834801719
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.389538637
Short name T140
Test name
Test status
Simulation time 34870355492 ps
CPU time 48.96 seconds
Started Jun 23 06:05:28 PM PDT 24
Finished Jun 23 06:06:17 PM PDT 24
Peak memory 192448 kb
Host smart-7aafaffe-f4b5-4941-b512-d0034c7d214f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389538637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.389538637
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.623740419
Short name T139
Test name
Test status
Simulation time 360524678036 ps
CPU time 117.79 seconds
Started Jun 23 06:05:30 PM PDT 24
Finished Jun 23 06:07:28 PM PDT 24
Peak memory 193240 kb
Host smart-dbe9c35a-10db-4d7f-919f-34e95b0ae20a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623740419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.623740419
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3372570185
Short name T99
Test name
Test status
Simulation time 177265184003 ps
CPU time 248.09 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:09:56 PM PDT 24
Peak memory 192452 kb
Host smart-0c972b7a-9e81-47a7-8fe3-208273894a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372570185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3372570185
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3446039613
Short name T89
Test name
Test status
Simulation time 53648595542 ps
CPU time 394.88 seconds
Started Jun 23 06:05:33 PM PDT 24
Finished Jun 23 06:12:09 PM PDT 24
Peak memory 209004 kb
Host smart-6d126e31-a8e5-4612-a8fc-82ca8c58442e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446039613 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3446039613
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1215594270
Short name T123
Test name
Test status
Simulation time 317478217077 ps
CPU time 488.97 seconds
Started Jun 23 06:05:38 PM PDT 24
Finished Jun 23 06:13:47 PM PDT 24
Peak memory 192452 kb
Host smart-cfbee8f7-fadf-466d-b1b7-4fdd2a5eb7cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215594270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1215594270
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.4288899561
Short name T125
Test name
Test status
Simulation time 311372477904 ps
CPU time 499.13 seconds
Started Jun 23 06:05:42 PM PDT 24
Finished Jun 23 06:14:02 PM PDT 24
Peak memory 193548 kb
Host smart-7db64e34-7feb-48a6-967a-3ebae059be40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288899561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.4288899561
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3483349807
Short name T42
Test name
Test status
Simulation time 478531525068 ps
CPU time 1159.86 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:25:08 PM PDT 24
Peak memory 215532 kb
Host smart-70fdc4a6-497d-4d8e-9b24-31979e42cbbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483349807 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3483349807
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3482720179
Short name T136
Test name
Test status
Simulation time 83119825551 ps
CPU time 47.34 seconds
Started Jun 23 06:05:45 PM PDT 24
Finished Jun 23 06:06:33 PM PDT 24
Peak memory 193012 kb
Host smart-b79080dc-91f7-4234-a8d9-1aa67024bfa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482720179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3482720179
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3021793832
Short name T150
Test name
Test status
Simulation time 262044366182 ps
CPU time 254.99 seconds
Started Jun 23 06:06:04 PM PDT 24
Finished Jun 23 06:10:19 PM PDT 24
Peak memory 193120 kb
Host smart-345b0a81-7e7c-4d06-94c3-26fb02bd4649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021793832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3021793832
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2323659569
Short name T165
Test name
Test status
Simulation time 238932052568 ps
CPU time 31.32 seconds
Started Jun 23 06:05:23 PM PDT 24
Finished Jun 23 06:05:55 PM PDT 24
Peak memory 193460 kb
Host smart-7cfcdb7a-4574-4ad5-a8ba-153c9cd18bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323659569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2323659569
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2392005099
Short name T106
Test name
Test status
Simulation time 47021765340 ps
CPU time 73.37 seconds
Started Jun 23 06:05:45 PM PDT 24
Finished Jun 23 06:06:59 PM PDT 24
Peak memory 184732 kb
Host smart-9e698592-36ff-491b-acda-aa51ae1b19fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392005099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2392005099
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2624590866
Short name T171
Test name
Test status
Simulation time 95585101885 ps
CPU time 177.81 seconds
Started Jun 23 06:05:55 PM PDT 24
Finished Jun 23 06:08:53 PM PDT 24
Peak memory 214912 kb
Host smart-c2b64ffe-1bb1-4fe8-84ac-3a7d39dcafc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624590866 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2624590866
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.753751856
Short name T75
Test name
Test status
Simulation time 459529868 ps
CPU time 0.66 seconds
Started Jun 23 06:06:14 PM PDT 24
Finished Jun 23 06:06:15 PM PDT 24
Peak memory 193900 kb
Host smart-af3075c7-3154-47d6-8628-fee57e54f260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753751856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.753751856
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1559444010
Short name T124
Test name
Test status
Simulation time 160655122071 ps
CPU time 241.2 seconds
Started Jun 23 06:05:32 PM PDT 24
Finished Jun 23 06:09:34 PM PDT 24
Peak memory 198816 kb
Host smart-3bcb08e8-9452-4139-815d-b4d277d84873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559444010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1559444010
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1349004410
Short name T85
Test name
Test status
Simulation time 86268248161 ps
CPU time 102.32 seconds
Started Jun 23 06:05:38 PM PDT 24
Finished Jun 23 06:07:21 PM PDT 24
Peak memory 207888 kb
Host smart-776daa2f-4cfe-4841-9190-c513a17e1ae8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349004410 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1349004410
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2071944773
Short name T114
Test name
Test status
Simulation time 195125111826 ps
CPU time 282.04 seconds
Started Jun 23 06:05:40 PM PDT 24
Finished Jun 23 06:10:23 PM PDT 24
Peak memory 198764 kb
Host smart-0aa88261-85aa-4172-aaa9-382a3251141b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071944773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2071944773
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3196325011
Short name T77
Test name
Test status
Simulation time 26366419046 ps
CPU time 228.14 seconds
Started Jun 23 06:05:35 PM PDT 24
Finished Jun 23 06:09:23 PM PDT 24
Peak memory 207340 kb
Host smart-85860c45-fba8-4190-ab27-10101168374c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196325011 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3196325011
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.4216459222
Short name T164
Test name
Test status
Simulation time 220416438510 ps
CPU time 390.67 seconds
Started Jun 23 06:05:39 PM PDT 24
Finished Jun 23 06:12:11 PM PDT 24
Peak memory 203024 kb
Host smart-66b3ebc4-77fb-49fd-8a5d-ae844d162e9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216459222 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.4216459222
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1349116196
Short name T103
Test name
Test status
Simulation time 137843420633 ps
CPU time 46.02 seconds
Started Jun 23 06:05:35 PM PDT 24
Finished Jun 23 06:06:21 PM PDT 24
Peak memory 192396 kb
Host smart-89ba5154-9f60-4447-94f8-ad3d93118452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349116196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1349116196
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2322316704
Short name T23
Test name
Test status
Simulation time 59758210161 ps
CPU time 40.11 seconds
Started Jun 23 06:05:49 PM PDT 24
Finished Jun 23 06:06:30 PM PDT 24
Peak memory 193484 kb
Host smart-0b4aa290-b17f-4816-90c9-330726ad8588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322316704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2322316704
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1220771897
Short name T133
Test name
Test status
Simulation time 10572352890 ps
CPU time 15 seconds
Started Jun 23 06:05:48 PM PDT 24
Finished Jun 23 06:06:04 PM PDT 24
Peak memory 198808 kb
Host smart-25267436-a386-4c1d-b1d6-6acebe8e9d3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220771897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1220771897
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3891797922
Short name T88
Test name
Test status
Simulation time 39487053670 ps
CPU time 51.27 seconds
Started Jun 23 06:05:32 PM PDT 24
Finished Jun 23 06:06:24 PM PDT 24
Peak memory 198816 kb
Host smart-1b458149-61d0-4837-9bee-ce90d660041e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891797922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3891797922
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.4159969748
Short name T146
Test name
Test status
Simulation time 483394436 ps
CPU time 0.79 seconds
Started Jun 23 06:05:25 PM PDT 24
Finished Jun 23 06:05:26 PM PDT 24
Peak memory 197376 kb
Host smart-5bf3de41-d9cb-4e43-b6e8-bddb69b8ac33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159969748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4159969748
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.80152547
Short name T48
Test name
Test status
Simulation time 299552106563 ps
CPU time 40.54 seconds
Started Jun 23 06:05:45 PM PDT 24
Finished Jun 23 06:06:26 PM PDT 24
Peak memory 198764 kb
Host smart-6a940f3d-4ecb-4033-8d19-eb47145c8c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80152547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_al
l.80152547
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1738357980
Short name T82
Test name
Test status
Simulation time 28371755941 ps
CPU time 204.66 seconds
Started Jun 23 06:05:52 PM PDT 24
Finished Jun 23 06:09:17 PM PDT 24
Peak memory 215508 kb
Host smart-db60e10f-701d-4fe3-942e-cf842df5d619
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738357980 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1738357980
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3336295191
Short name T47
Test name
Test status
Simulation time 528466647720 ps
CPU time 818.75 seconds
Started Jun 23 06:06:05 PM PDT 24
Finished Jun 23 06:19:44 PM PDT 24
Peak memory 192540 kb
Host smart-49143a73-3725-4da4-862e-5c2d61025fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336295191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3336295191
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.965054459
Short name T80
Test name
Test status
Simulation time 72012501574 ps
CPU time 265.3 seconds
Started Jun 23 06:05:58 PM PDT 24
Finished Jun 23 06:10:24 PM PDT 24
Peak memory 200604 kb
Host smart-c8413641-ebc2-4409-9d63-a6c7b71a2964
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965054459 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.965054459
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.494733647
Short name T148
Test name
Test status
Simulation time 271719938645 ps
CPU time 358.02 seconds
Started Jun 23 06:05:27 PM PDT 24
Finished Jun 23 06:11:26 PM PDT 24
Peak memory 192452 kb
Host smart-bde8d27d-c268-4849-b51c-b9e095657fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494733647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.494733647
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.333817320
Short name T52
Test name
Test status
Simulation time 54249470930 ps
CPU time 77.13 seconds
Started Jun 23 06:05:23 PM PDT 24
Finished Jun 23 06:06:40 PM PDT 24
Peak memory 198784 kb
Host smart-592883be-bec2-4b41-8ad7-e6f3000dad0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333817320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.333817320
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2743304697
Short name T93
Test name
Test status
Simulation time 109932773304 ps
CPU time 37.16 seconds
Started Jun 23 06:05:35 PM PDT 24
Finished Jun 23 06:06:12 PM PDT 24
Peak memory 198804 kb
Host smart-3ab2b7d2-fa00-43d9-affe-4e588611fbe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743304697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2743304697
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.4190156442
Short name T154
Test name
Test status
Simulation time 84041734205 ps
CPU time 122.91 seconds
Started Jun 23 06:05:41 PM PDT 24
Finished Jun 23 06:07:44 PM PDT 24
Peak memory 207644 kb
Host smart-6d6c7b15-1ef0-4e65-9c7e-18f1f9bce4c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190156442 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.4190156442
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2577841491
Short name T13
Test name
Test status
Simulation time 459411253 ps
CPU time 0.7 seconds
Started Jun 23 06:05:51 PM PDT 24
Finished Jun 23 06:05:52 PM PDT 24
Peak memory 197160 kb
Host smart-8dfd701e-000c-41a0-bd18-5a5ce3b0260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577841491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2577841491
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3582633251
Short name T151
Test name
Test status
Simulation time 417134435 ps
CPU time 0.74 seconds
Started Jun 23 06:05:18 PM PDT 24
Finished Jun 23 06:05:19 PM PDT 24
Peak memory 197136 kb
Host smart-c450ca23-576c-411a-bb80-d7e97b36845c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582633251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3582633251
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.674195858
Short name T4
Test name
Test status
Simulation time 222850867510 ps
CPU time 168.98 seconds
Started Jun 23 06:05:30 PM PDT 24
Finished Jun 23 06:08:19 PM PDT 24
Peak memory 193024 kb
Host smart-f82e726b-7b3c-4227-88cb-08cb384f33d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674195858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.674195858
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.858704780
Short name T117
Test name
Test status
Simulation time 399594305 ps
CPU time 0.91 seconds
Started Jun 23 06:05:33 PM PDT 24
Finished Jun 23 06:05:34 PM PDT 24
Peak memory 197132 kb
Host smart-5a784474-ac55-44d2-8b8f-da9005232f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858704780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.858704780
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.841507966
Short name T31
Test name
Test status
Simulation time 50195708663 ps
CPU time 178.78 seconds
Started Jun 23 06:05:38 PM PDT 24
Finished Jun 23 06:08:38 PM PDT 24
Peak memory 207368 kb
Host smart-26ee82a1-5433-463f-b1e0-42b82e15b727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841507966 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.841507966
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1575517221
Short name T112
Test name
Test status
Simulation time 97569723951 ps
CPU time 184.94 seconds
Started Jun 23 06:05:26 PM PDT 24
Finished Jun 23 06:08:31 PM PDT 24
Peak memory 215244 kb
Host smart-ad10cdd1-1452-4f29-bb5b-34200bfd20f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575517221 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1575517221
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.216880886
Short name T127
Test name
Test status
Simulation time 506700386 ps
CPU time 0.67 seconds
Started Jun 23 06:05:22 PM PDT 24
Finished Jun 23 06:05:23 PM PDT 24
Peak memory 197036 kb
Host smart-d2694109-6f72-4c3a-9040-db7274e277d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216880886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.216880886
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2539558517
Short name T92
Test name
Test status
Simulation time 511354740 ps
CPU time 1.39 seconds
Started Jun 23 06:05:22 PM PDT 24
Finished Jun 23 06:05:24 PM PDT 24
Peak memory 197000 kb
Host smart-5c6056e7-f4ff-43ff-88de-90a809403d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539558517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2539558517
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.35243670
Short name T156
Test name
Test status
Simulation time 366319701 ps
CPU time 0.67 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:05:49 PM PDT 24
Peak memory 197072 kb
Host smart-a14311bc-7c75-4f53-920f-3e2618f05e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35243670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.35243670
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.4029481592
Short name T161
Test name
Test status
Simulation time 84805015737 ps
CPU time 908.1 seconds
Started Jun 23 06:05:38 PM PDT 24
Finished Jun 23 06:20:47 PM PDT 24
Peak memory 210324 kb
Host smart-461c1718-2755-4a4d-92df-fc98e0a49cde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029481592 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.4029481592
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3542337087
Short name T122
Test name
Test status
Simulation time 348162533 ps
CPU time 0.99 seconds
Started Jun 23 06:05:35 PM PDT 24
Finished Jun 23 06:05:36 PM PDT 24
Peak memory 197212 kb
Host smart-0d6d3db9-d8e3-41e3-b34e-81894900271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542337087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3542337087
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3178261896
Short name T158
Test name
Test status
Simulation time 601826680 ps
CPU time 0.66 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:05:49 PM PDT 24
Peak memory 197088 kb
Host smart-b4f49a21-f86b-4260-b16b-d6387a5aec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178261896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3178261896
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2830619715
Short name T25
Test name
Test status
Simulation time 563832869 ps
CPU time 1.04 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:05:49 PM PDT 24
Peak memory 197116 kb
Host smart-2e3f77a5-c742-448e-9642-8ebef3c081d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830619715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2830619715
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1089250006
Short name T157
Test name
Test status
Simulation time 382888684 ps
CPU time 0.8 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:05:47 PM PDT 24
Peak memory 197104 kb
Host smart-7b4ccc3e-14f7-490a-b142-4e07c6d4f6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089250006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1089250006
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3602331376
Short name T32
Test name
Test status
Simulation time 432015037 ps
CPU time 1.27 seconds
Started Jun 23 06:06:01 PM PDT 24
Finished Jun 23 06:06:03 PM PDT 24
Peak memory 197080 kb
Host smart-e2acf6b0-f179-47c6-9741-3d4eae127618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602331376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3602331376
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1927359472
Short name T50
Test name
Test status
Simulation time 518312419 ps
CPU time 0.92 seconds
Started Jun 23 06:05:27 PM PDT 24
Finished Jun 23 06:05:28 PM PDT 24
Peak memory 197076 kb
Host smart-9df90239-6772-41a5-9223-9d08a3ebe275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927359472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1927359472
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2332962820
Short name T33
Test name
Test status
Simulation time 492444166 ps
CPU time 0.74 seconds
Started Jun 23 06:05:27 PM PDT 24
Finished Jun 23 06:05:28 PM PDT 24
Peak memory 197108 kb
Host smart-b73b4c9d-212a-420d-8016-4ecf81751308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332962820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2332962820
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1790879380
Short name T2
Test name
Test status
Simulation time 87376161048 ps
CPU time 125.88 seconds
Started Jun 23 06:05:33 PM PDT 24
Finished Jun 23 06:07:39 PM PDT 24
Peak memory 198740 kb
Host smart-0dd59dd2-49a2-4343-88df-b5c8208ef8f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790879380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1790879380
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1504835602
Short name T155
Test name
Test status
Simulation time 441222405 ps
CPU time 0.75 seconds
Started Jun 23 06:05:38 PM PDT 24
Finished Jun 23 06:05:39 PM PDT 24
Peak memory 197208 kb
Host smart-761cd9c4-4b6b-499f-a476-a658028f6db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504835602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1504835602
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.429347520
Short name T168
Test name
Test status
Simulation time 80445859485 ps
CPU time 97.78 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:07:26 PM PDT 24
Peak memory 193544 kb
Host smart-220781dc-2688-4161-9007-18c876c1a6e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429347520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.429347520
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.9828938
Short name T138
Test name
Test status
Simulation time 476275135 ps
CPU time 0.64 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:05:48 PM PDT 24
Peak memory 197228 kb
Host smart-f53c246c-d6fd-4ed0-b4be-b6bc2ad2a681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9828938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.9828938
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2180263992
Short name T105
Test name
Test status
Simulation time 520470441 ps
CPU time 1.37 seconds
Started Jun 23 06:05:24 PM PDT 24
Finished Jun 23 06:05:26 PM PDT 24
Peak memory 197128 kb
Host smart-a3b8b6cd-2a0b-4067-aba8-491068765c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180263992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2180263992
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1149840700
Short name T131
Test name
Test status
Simulation time 574649083 ps
CPU time 1.45 seconds
Started Jun 23 06:05:34 PM PDT 24
Finished Jun 23 06:05:36 PM PDT 24
Peak memory 197036 kb
Host smart-7bf56357-112d-491c-80cb-8678b01abbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149840700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1149840700
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.672403090
Short name T81
Test name
Test status
Simulation time 24747561193 ps
CPU time 190.49 seconds
Started Jun 23 06:05:36 PM PDT 24
Finished Jun 23 06:08:47 PM PDT 24
Peak memory 207420 kb
Host smart-035a2ef5-164c-41a0-b7aa-0e5b21f3aa64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672403090 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.672403090
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3961397549
Short name T135
Test name
Test status
Simulation time 243952450171 ps
CPU time 307.65 seconds
Started Jun 23 06:05:22 PM PDT 24
Finished Jun 23 06:10:30 PM PDT 24
Peak memory 193572 kb
Host smart-090b157e-9857-4114-9d97-c7eaaf39e2fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961397549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3961397549
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.562227686
Short name T152
Test name
Test status
Simulation time 486559121 ps
CPU time 1.37 seconds
Started Jun 23 06:06:01 PM PDT 24
Finished Jun 23 06:06:03 PM PDT 24
Peak memory 197000 kb
Host smart-7e609ef5-b984-4aab-8852-c3ef9087defd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562227686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.562227686
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3102382487
Short name T98
Test name
Test status
Simulation time 89755172023 ps
CPU time 120.16 seconds
Started Jun 23 06:05:49 PM PDT 24
Finished Jun 23 06:07:50 PM PDT 24
Peak memory 198804 kb
Host smart-225c3c8d-4a74-4189-b88a-cc595ccc7f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102382487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3102382487
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.595858888
Short name T126
Test name
Test status
Simulation time 580830817 ps
CPU time 1.35 seconds
Started Jun 23 06:05:51 PM PDT 24
Finished Jun 23 06:05:53 PM PDT 24
Peak memory 197208 kb
Host smart-d18b4c5f-752f-417d-be74-c22fefcc2515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595858888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.595858888
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1325290347
Short name T142
Test name
Test status
Simulation time 381586625 ps
CPU time 0.77 seconds
Started Jun 23 06:06:02 PM PDT 24
Finished Jun 23 06:06:03 PM PDT 24
Peak memory 197208 kb
Host smart-47363b16-ff87-4ea9-bfa6-151f6cd0a6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325290347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1325290347
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3757468658
Short name T128
Test name
Test status
Simulation time 52049079584 ps
CPU time 289.53 seconds
Started Jun 23 06:05:20 PM PDT 24
Finished Jun 23 06:10:10 PM PDT 24
Peak memory 199672 kb
Host smart-09e51f8b-70c5-4526-a4dd-e2daec8de702
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757468658 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3757468658
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2700226123
Short name T145
Test name
Test status
Simulation time 566990417 ps
CPU time 0.78 seconds
Started Jun 23 06:05:32 PM PDT 24
Finished Jun 23 06:05:33 PM PDT 24
Peak memory 197100 kb
Host smart-f005f6e2-8558-488c-85ce-307c0a3ecacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700226123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2700226123
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2409810471
Short name T153
Test name
Test status
Simulation time 485324466 ps
CPU time 1.32 seconds
Started Jun 23 06:05:41 PM PDT 24
Finished Jun 23 06:05:43 PM PDT 24
Peak memory 197220 kb
Host smart-4cb4690f-9813-4a91-b54a-a38652fd4178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409810471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2409810471
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.43658551
Short name T182
Test name
Test status
Simulation time 614118813 ps
CPU time 0.74 seconds
Started Jun 23 06:05:40 PM PDT 24
Finished Jun 23 06:05:41 PM PDT 24
Peak memory 197100 kb
Host smart-9655e3c7-bf54-4292-addc-c6c6c64a8f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43658551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.43658551
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1095790552
Short name T100
Test name
Test status
Simulation time 355141350 ps
CPU time 0.76 seconds
Started Jun 23 06:05:52 PM PDT 24
Finished Jun 23 06:05:54 PM PDT 24
Peak memory 197164 kb
Host smart-5fc715b1-89cc-401e-b209-9c78ce1cf662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095790552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1095790552
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2894656708
Short name T178
Test name
Test status
Simulation time 413578708 ps
CPU time 1.24 seconds
Started Jun 23 06:05:21 PM PDT 24
Finished Jun 23 06:05:23 PM PDT 24
Peak memory 197060 kb
Host smart-b74e4850-4eb7-43ed-9669-1316325536ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894656708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2894656708
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.4050165913
Short name T187
Test name
Test status
Simulation time 595064067 ps
CPU time 0.85 seconds
Started Jun 23 06:05:20 PM PDT 24
Finished Jun 23 06:05:21 PM PDT 24
Peak memory 197116 kb
Host smart-0ec89d68-5a2c-4008-aa65-c8c1489cd2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050165913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4050165913
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.165744223
Short name T169
Test name
Test status
Simulation time 533989148 ps
CPU time 1.36 seconds
Started Jun 23 06:05:32 PM PDT 24
Finished Jun 23 06:05:34 PM PDT 24
Peak memory 197052 kb
Host smart-fa51154c-6710-4923-8dfa-3f1d456e966c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165744223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.165744223
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1042208783
Short name T176
Test name
Test status
Simulation time 176356083067 ps
CPU time 265.82 seconds
Started Jun 23 06:05:31 PM PDT 24
Finished Jun 23 06:09:57 PM PDT 24
Peak memory 198720 kb
Host smart-a0569673-76a7-4e21-be23-3249b1dd36dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042208783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1042208783
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2203490515
Short name T181
Test name
Test status
Simulation time 430829970 ps
CPU time 0.71 seconds
Started Jun 23 06:05:37 PM PDT 24
Finished Jun 23 06:05:39 PM PDT 24
Peak memory 197136 kb
Host smart-ed310dc6-3f78-4edd-acdb-1674ef3747ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203490515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2203490515
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2234022888
Short name T160
Test name
Test status
Simulation time 513145909 ps
CPU time 0.94 seconds
Started Jun 23 06:05:35 PM PDT 24
Finished Jun 23 06:05:36 PM PDT 24
Peak memory 196996 kb
Host smart-d1a9e13e-a363-461d-af8f-bc0c77f446d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234022888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2234022888
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2057716743
Short name T172
Test name
Test status
Simulation time 124744861961 ps
CPU time 165.95 seconds
Started Jun 23 06:05:32 PM PDT 24
Finished Jun 23 06:08:18 PM PDT 24
Peak memory 200252 kb
Host smart-d3557deb-4eda-4844-8b40-65cd3a9de0ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057716743 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2057716743
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2605065861
Short name T147
Test name
Test status
Simulation time 536263132 ps
CPU time 1.26 seconds
Started Jun 23 06:05:37 PM PDT 24
Finished Jun 23 06:05:39 PM PDT 24
Peak memory 197220 kb
Host smart-e1b7e456-7bb9-481a-886e-58c2adbeebe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605065861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2605065861
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2054165425
Short name T116
Test name
Test status
Simulation time 494970540 ps
CPU time 0.73 seconds
Started Jun 23 06:05:42 PM PDT 24
Finished Jun 23 06:05:43 PM PDT 24
Peak memory 197144 kb
Host smart-eb7f3403-5c4e-4141-a84a-22bec1c058b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054165425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2054165425
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1306156292
Short name T170
Test name
Test status
Simulation time 581370641 ps
CPU time 1.33 seconds
Started Jun 23 06:05:45 PM PDT 24
Finished Jun 23 06:05:47 PM PDT 24
Peak memory 197084 kb
Host smart-a6519161-eca7-4e8f-8567-38b3909aeec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306156292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1306156292
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3333871597
Short name T185
Test name
Test status
Simulation time 576210205 ps
CPU time 0.8 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:05:48 PM PDT 24
Peak memory 196420 kb
Host smart-ed821906-4894-43fe-9d24-b8330d35038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333871597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3333871597
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1378936503
Short name T26
Test name
Test status
Simulation time 43762560174 ps
CPU time 63.95 seconds
Started Jun 23 06:05:55 PM PDT 24
Finished Jun 23 06:06:59 PM PDT 24
Peak memory 192400 kb
Host smart-454fffc8-92fb-4278-935f-9cc9c65d9c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378936503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1378936503
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.567217956
Short name T120
Test name
Test status
Simulation time 553659736 ps
CPU time 1.11 seconds
Started Jun 23 06:05:54 PM PDT 24
Finished Jun 23 06:05:56 PM PDT 24
Peak memory 197152 kb
Host smart-f528f73b-f3e3-4915-a2e9-96e0340ce749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567217956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.567217956
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.666131843
Short name T163
Test name
Test status
Simulation time 548365811 ps
CPU time 0.81 seconds
Started Jun 23 06:06:05 PM PDT 24
Finished Jun 23 06:06:06 PM PDT 24
Peak memory 196996 kb
Host smart-afaf0550-08c2-4061-b47c-b8d2e1810a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666131843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.666131843
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3509942444
Short name T3
Test name
Test status
Simulation time 581587448 ps
CPU time 1.52 seconds
Started Jun 23 06:05:25 PM PDT 24
Finished Jun 23 06:05:27 PM PDT 24
Peak memory 197092 kb
Host smart-83fde65a-69bc-4957-ba09-c05a4e821536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509942444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3509942444
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3457494787
Short name T190
Test name
Test status
Simulation time 4858390404 ps
CPU time 2.37 seconds
Started Jun 23 06:06:23 PM PDT 24
Finished Jun 23 06:06:26 PM PDT 24
Peak memory 197704 kb
Host smart-08480dd3-21c6-4fd4-b7b3-a7db2c068447
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457494787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3457494787
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2811283856
Short name T184
Test name
Test status
Simulation time 368118205 ps
CPU time 1.07 seconds
Started Jun 23 06:05:24 PM PDT 24
Finished Jun 23 06:05:26 PM PDT 24
Peak memory 196988 kb
Host smart-a145ee9a-4187-4d90-802a-7c1396a8a75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811283856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2811283856
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1525170161
Short name T51
Test name
Test status
Simulation time 84595719420 ps
CPU time 30.8 seconds
Started Jun 23 06:05:27 PM PDT 24
Finished Jun 23 06:05:58 PM PDT 24
Peak memory 184716 kb
Host smart-24f4e4dd-5523-461a-a72b-4a6defa00b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525170161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1525170161
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.55276395
Short name T53
Test name
Test status
Simulation time 533764114 ps
CPU time 1.43 seconds
Started Jun 23 06:05:40 PM PDT 24
Finished Jun 23 06:05:42 PM PDT 24
Peak memory 197136 kb
Host smart-74a4159b-2a0f-4c3c-8110-1ddc186d04ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55276395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.55276395
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3526421916
Short name T9
Test name
Test status
Simulation time 496318653 ps
CPU time 0.84 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:05:47 PM PDT 24
Peak memory 197072 kb
Host smart-7d3f54cb-b746-4e32-95ec-1f0307922eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526421916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3526421916
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1948267875
Short name T130
Test name
Test status
Simulation time 527775756 ps
CPU time 1.28 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:05:48 PM PDT 24
Peak memory 197104 kb
Host smart-a9dcdaa0-2192-497a-a272-84b2a416f6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948267875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1948267875
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3514345586
Short name T186
Test name
Test status
Simulation time 613645708 ps
CPU time 0.84 seconds
Started Jun 23 06:05:49 PM PDT 24
Finished Jun 23 06:05:50 PM PDT 24
Peak memory 197048 kb
Host smart-7356d942-ed39-4a0e-a491-a7f1915996f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514345586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3514345586
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2359184703
Short name T10
Test name
Test status
Simulation time 406192854 ps
CPU time 1.15 seconds
Started Jun 23 06:05:22 PM PDT 24
Finished Jun 23 06:05:24 PM PDT 24
Peak memory 197068 kb
Host smart-2b7ebe9d-a367-47d7-9649-f4edb0fa6300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359184703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2359184703
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4193350149
Short name T188
Test name
Test status
Simulation time 392582205 ps
CPU time 0.75 seconds
Started Jun 23 06:05:49 PM PDT 24
Finished Jun 23 06:05:50 PM PDT 24
Peak memory 197048 kb
Host smart-74d57c49-8d61-404e-810c-d62b0d6f2573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193350149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4193350149
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.246810004
Short name T183
Test name
Test status
Simulation time 351585964 ps
CPU time 1.05 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:05:48 PM PDT 24
Peak memory 197040 kb
Host smart-fc8096b2-26da-4ed2-83b0-1464afb2d0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246810004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.246810004
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2615153328
Short name T144
Test name
Test status
Simulation time 153821109998 ps
CPU time 226.5 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:09:34 PM PDT 24
Peak memory 198748 kb
Host smart-bb8d28fb-cee8-45a0-a14a-a187474487a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615153328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2615153328
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4152053413
Short name T174
Test name
Test status
Simulation time 563003519 ps
CPU time 1.02 seconds
Started Jun 23 06:05:55 PM PDT 24
Finished Jun 23 06:05:56 PM PDT 24
Peak memory 197164 kb
Host smart-2e7199bb-d731-4fca-858a-865acd3440bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152053413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4152053413
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1743248951
Short name T166
Test name
Test status
Simulation time 327824029499 ps
CPU time 95.44 seconds
Started Jun 23 06:05:55 PM PDT 24
Finished Jun 23 06:07:31 PM PDT 24
Peak memory 185000 kb
Host smart-fedf987d-3b54-412e-83fd-9dc7787fdfdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743248951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1743248951
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1329431279
Short name T173
Test name
Test status
Simulation time 524442915724 ps
CPU time 269.64 seconds
Started Jun 23 06:05:58 PM PDT 24
Finished Jun 23 06:10:28 PM PDT 24
Peak memory 192664 kb
Host smart-ef983d9a-a19a-45e2-b6e2-e86cf63ddff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329431279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1329431279
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1700566727
Short name T167
Test name
Test status
Simulation time 503791798 ps
CPU time 0.76 seconds
Started Jun 23 06:05:25 PM PDT 24
Finished Jun 23 06:05:26 PM PDT 24
Peak memory 197080 kb
Host smart-b7d62db5-c320-43cf-ac4a-bc684b5014c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700566727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1700566727
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3343227389
Short name T175
Test name
Test status
Simulation time 456136774 ps
CPU time 1.04 seconds
Started Jun 23 06:05:21 PM PDT 24
Finished Jun 23 06:05:23 PM PDT 24
Peak memory 197060 kb
Host smart-63897265-3858-4b23-bbad-45eea3373263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343227389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3343227389
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3944865102
Short name T66
Test name
Test status
Simulation time 629651269 ps
CPU time 1.95 seconds
Started Jun 23 06:06:00 PM PDT 24
Finished Jun 23 06:06:02 PM PDT 24
Peak memory 194484 kb
Host smart-9bab54fe-4f35-46dd-9d90-0aaf48787e1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944865102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3944865102
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4081364855
Short name T373
Test name
Test status
Simulation time 1333837567 ps
CPU time 1.97 seconds
Started Jun 23 06:06:00 PM PDT 24
Finished Jun 23 06:06:03 PM PDT 24
Peak memory 192856 kb
Host smart-d191fc2a-fbf1-47f2-a261-0c59369482a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081364855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.4081364855
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.563873804
Short name T328
Test name
Test status
Simulation time 462551022 ps
CPU time 1.3 seconds
Started Jun 23 06:06:05 PM PDT 24
Finished Jun 23 06:06:07 PM PDT 24
Peak memory 196088 kb
Host smart-faf62e92-03ec-4471-a8b7-1dca1986908e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563873804 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.563873804
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2249869494
Short name T389
Test name
Test status
Simulation time 388978479 ps
CPU time 1.12 seconds
Started Jun 23 06:06:00 PM PDT 24
Finished Jun 23 06:06:02 PM PDT 24
Peak memory 192944 kb
Host smart-7598b502-5f03-44f4-ac26-f05e1c03c1e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249869494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2249869494
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4101847804
Short name T358
Test name
Test status
Simulation time 379721502 ps
CPU time 0.61 seconds
Started Jun 23 06:06:00 PM PDT 24
Finished Jun 23 06:06:01 PM PDT 24
Peak memory 192888 kb
Host smart-60a6e52e-9e20-4b41-9007-540b897a7d6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101847804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.4101847804
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.231352715
Short name T330
Test name
Test status
Simulation time 373636762 ps
CPU time 0.66 seconds
Started Jun 23 06:06:02 PM PDT 24
Finished Jun 23 06:06:04 PM PDT 24
Peak memory 183592 kb
Host smart-08d15926-8ef7-45f2-af94-6446390b8158
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231352715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.231352715
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3819259558
Short name T336
Test name
Test status
Simulation time 338631215 ps
CPU time 0.77 seconds
Started Jun 23 06:06:05 PM PDT 24
Finished Jun 23 06:06:06 PM PDT 24
Peak memory 183432 kb
Host smart-05653653-c027-4276-a9c0-d27be23267ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819259558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3819259558
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2719829343
Short name T339
Test name
Test status
Simulation time 1977160997 ps
CPU time 2.02 seconds
Started Jun 23 06:06:04 PM PDT 24
Finished Jun 23 06:06:06 PM PDT 24
Peak memory 193884 kb
Host smart-921da38a-b14e-4c39-912c-136e032c1b8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719829343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2719829343
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2678000164
Short name T419
Test name
Test status
Simulation time 295205782 ps
CPU time 1.86 seconds
Started Jun 23 06:05:58 PM PDT 24
Finished Jun 23 06:06:00 PM PDT 24
Peak memory 198492 kb
Host smart-614a33dd-3765-4eca-a687-8e7170452299
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678000164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2678000164
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4290324430
Short name T349
Test name
Test status
Simulation time 4348693870 ps
CPU time 1.95 seconds
Started Jun 23 06:06:00 PM PDT 24
Finished Jun 23 06:06:03 PM PDT 24
Peak memory 197556 kb
Host smart-ba9dadf0-d742-4ba5-881f-787907c4d247
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290324430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.4290324430
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2470686791
Short name T303
Test name
Test status
Simulation time 734216085 ps
CPU time 1.02 seconds
Started Jun 23 06:06:04 PM PDT 24
Finished Jun 23 06:06:06 PM PDT 24
Peak memory 183728 kb
Host smart-be0ac685-65c5-452c-944b-fe710622cd2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470686791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2470686791
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4050712759
Short name T333
Test name
Test status
Simulation time 8674070855 ps
CPU time 4.37 seconds
Started Jun 23 06:06:03 PM PDT 24
Finished Jun 23 06:06:08 PM PDT 24
Peak memory 192108 kb
Host smart-fef5b55b-6558-4bb4-aef0-2d7274a0d759
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050712759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.4050712759
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.536643991
Short name T329
Test name
Test status
Simulation time 1217726870 ps
CPU time 1.05 seconds
Started Jun 23 06:06:09 PM PDT 24
Finished Jun 23 06:06:10 PM PDT 24
Peak memory 193180 kb
Host smart-66386b8b-5a18-41ea-8ada-5026feeed660
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536643991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.536643991
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.882176502
Short name T371
Test name
Test status
Simulation time 561119153 ps
CPU time 0.84 seconds
Started Jun 23 06:06:03 PM PDT 24
Finished Jun 23 06:06:04 PM PDT 24
Peak memory 195672 kb
Host smart-25ca1e55-d689-4e7e-b84c-4bf8be26780f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882176502 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.882176502
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.880934634
Short name T67
Test name
Test status
Simulation time 425141931 ps
CPU time 0.87 seconds
Started Jun 23 06:06:09 PM PDT 24
Finished Jun 23 06:06:10 PM PDT 24
Peak memory 193016 kb
Host smart-7b2a91c1-a2d6-4ee6-a2c6-dadc62370317
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880934634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.880934634
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3550980929
Short name T315
Test name
Test status
Simulation time 303912564 ps
CPU time 0.96 seconds
Started Jun 23 06:06:00 PM PDT 24
Finished Jun 23 06:06:01 PM PDT 24
Peak memory 183672 kb
Host smart-9c6c30dc-c6b9-48ea-828a-ae8cff1c7500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550980929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3550980929
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.49665691
Short name T299
Test name
Test status
Simulation time 459664031 ps
CPU time 0.7 seconds
Started Jun 23 06:06:03 PM PDT 24
Finished Jun 23 06:06:04 PM PDT 24
Peak memory 183528 kb
Host smart-dcf6ae58-41f8-40e1-9885-f0ac02e04b34
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49665691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim
er_mem_partial_access.49665691
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3612785534
Short name T347
Test name
Test status
Simulation time 276323204 ps
CPU time 0.86 seconds
Started Jun 23 06:06:01 PM PDT 24
Finished Jun 23 06:06:02 PM PDT 24
Peak memory 183560 kb
Host smart-194b36ab-494e-4335-a42e-752715ea3a67
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612785534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3612785534
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1931840858
Short name T313
Test name
Test status
Simulation time 2532683059 ps
CPU time 2.22 seconds
Started Jun 23 06:06:00 PM PDT 24
Finished Jun 23 06:06:03 PM PDT 24
Peak memory 192000 kb
Host smart-64e35940-3b57-47fe-be97-1646e954a22c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931840858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1931840858
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2931171352
Short name T401
Test name
Test status
Simulation time 359408088 ps
CPU time 1.53 seconds
Started Jun 23 06:06:00 PM PDT 24
Finished Jun 23 06:06:02 PM PDT 24
Peak memory 198360 kb
Host smart-87e4204c-8f98-4b23-afc4-6694d8102cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931171352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2931171352
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1531886116
Short name T37
Test name
Test status
Simulation time 8652080729 ps
CPU time 13.1 seconds
Started Jun 23 06:05:59 PM PDT 24
Finished Jun 23 06:06:12 PM PDT 24
Peak memory 198248 kb
Host smart-564aab24-981e-4a59-abc4-c313363998b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531886116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1531886116
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3923449728
Short name T314
Test name
Test status
Simulation time 353816015 ps
CPU time 0.75 seconds
Started Jun 23 06:06:22 PM PDT 24
Finished Jun 23 06:06:24 PM PDT 24
Peak memory 195396 kb
Host smart-65b9ae27-a6b1-499d-8ccb-4dfa2d6ec211
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923449728 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3923449728
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2618449954
Short name T399
Test name
Test status
Simulation time 493509842 ps
CPU time 0.89 seconds
Started Jun 23 06:06:16 PM PDT 24
Finished Jun 23 06:06:17 PM PDT 24
Peak memory 183672 kb
Host smart-9cb5c754-4f4b-4fac-b404-5684fa2bd6ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618449954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2618449954
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3880039372
Short name T73
Test name
Test status
Simulation time 1324724578 ps
CPU time 1.44 seconds
Started Jun 23 06:06:16 PM PDT 24
Finished Jun 23 06:06:18 PM PDT 24
Peak memory 192960 kb
Host smart-48d8fa5a-c0c7-4479-87ec-7d9b5662e751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880039372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3880039372
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1185531723
Short name T308
Test name
Test status
Simulation time 391771636 ps
CPU time 1.51 seconds
Started Jun 23 06:06:18 PM PDT 24
Finished Jun 23 06:06:20 PM PDT 24
Peak memory 198536 kb
Host smart-9f5e2b3c-7d77-49bb-ae51-30d712316e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185531723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1185531723
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3622027209
Short name T316
Test name
Test status
Simulation time 7855968224 ps
CPU time 6.31 seconds
Started Jun 23 06:06:12 PM PDT 24
Finished Jun 23 06:06:19 PM PDT 24
Peak memory 198260 kb
Host smart-3defc675-2e2f-47c5-a553-3717cc01c6fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622027209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3622027209
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3881025483
Short name T319
Test name
Test status
Simulation time 441127186 ps
CPU time 1.25 seconds
Started Jun 23 06:06:18 PM PDT 24
Finished Jun 23 06:06:20 PM PDT 24
Peak memory 196616 kb
Host smart-b9cd9ae3-90e1-4f2d-8f59-2a4b836f2192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881025483 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3881025483
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.319177763
Short name T365
Test name
Test status
Simulation time 427181539 ps
CPU time 0.87 seconds
Started Jun 23 06:06:19 PM PDT 24
Finished Jun 23 06:06:21 PM PDT 24
Peak memory 193112 kb
Host smart-6d726dea-5cf7-4dc4-b395-78592daf511d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319177763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.319177763
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1277819790
Short name T337
Test name
Test status
Simulation time 365854713 ps
CPU time 0.8 seconds
Started Jun 23 06:06:23 PM PDT 24
Finished Jun 23 06:06:24 PM PDT 24
Peak memory 183640 kb
Host smart-6455651d-7f7f-46d1-9400-ec74358570be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277819790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1277819790
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1621628546
Short name T72
Test name
Test status
Simulation time 1087941589 ps
CPU time 1.14 seconds
Started Jun 23 06:06:20 PM PDT 24
Finished Jun 23 06:06:22 PM PDT 24
Peak memory 193188 kb
Host smart-8aba2112-00cf-4193-94f4-f5bc3054e8ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621628546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1621628546
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2653849394
Short name T311
Test name
Test status
Simulation time 335422971 ps
CPU time 1.35 seconds
Started Jun 23 06:06:20 PM PDT 24
Finished Jun 23 06:06:21 PM PDT 24
Peak memory 198384 kb
Host smart-9b096f17-f8b1-40f9-8248-13c4ae337475
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653849394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2653849394
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2319564872
Short name T317
Test name
Test status
Simulation time 545080468 ps
CPU time 0.84 seconds
Started Jun 23 06:06:18 PM PDT 24
Finished Jun 23 06:06:19 PM PDT 24
Peak memory 195972 kb
Host smart-2503235e-7a71-4e8e-9d1d-6158bd082736
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319564872 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2319564872
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3251914477
Short name T63
Test name
Test status
Simulation time 409214163 ps
CPU time 1.15 seconds
Started Jun 23 06:06:17 PM PDT 24
Finished Jun 23 06:06:18 PM PDT 24
Peak memory 192872 kb
Host smart-04e1e7cf-a0e8-4350-97fe-841128af1400
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251914477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3251914477
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.106708258
Short name T291
Test name
Test status
Simulation time 568350600 ps
CPU time 0.6 seconds
Started Jun 23 06:06:17 PM PDT 24
Finished Jun 23 06:06:18 PM PDT 24
Peak memory 192928 kb
Host smart-b7920dc3-6cad-4cea-ab07-63c63ba3f1bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106708258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.106708258
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3466847390
Short name T390
Test name
Test status
Simulation time 2522854914 ps
CPU time 4.2 seconds
Started Jun 23 06:06:19 PM PDT 24
Finished Jun 23 06:06:23 PM PDT 24
Peak memory 195000 kb
Host smart-8920995f-6e83-4b3c-a91c-c77ba0fb4c91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466847390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3466847390
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1069504026
Short name T326
Test name
Test status
Simulation time 545835089 ps
CPU time 1.93 seconds
Started Jun 23 06:06:22 PM PDT 24
Finished Jun 23 06:06:25 PM PDT 24
Peak memory 198524 kb
Host smart-03048c46-b5df-4ce6-aafe-b5fb89a00259
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069504026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1069504026
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2515437576
Short name T346
Test name
Test status
Simulation time 8258197712 ps
CPU time 11.49 seconds
Started Jun 23 06:06:21 PM PDT 24
Finished Jun 23 06:06:33 PM PDT 24
Peak memory 198148 kb
Host smart-e4bf68ec-380d-40e7-a280-4842ba678c9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515437576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2515437576
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.910423879
Short name T359
Test name
Test status
Simulation time 400823809 ps
CPU time 0.79 seconds
Started Jun 23 06:06:22 PM PDT 24
Finished Jun 23 06:06:24 PM PDT 24
Peak memory 195500 kb
Host smart-2db112d2-da45-462a-ad9a-8f51d44e8510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910423879 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.910423879
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2444868440
Short name T68
Test name
Test status
Simulation time 451693527 ps
CPU time 0.91 seconds
Started Jun 23 06:06:20 PM PDT 24
Finished Jun 23 06:06:21 PM PDT 24
Peak memory 193308 kb
Host smart-0dce2209-f8f1-4964-8996-c820bd6a1dbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444868440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2444868440
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1102029086
Short name T309
Test name
Test status
Simulation time 355468006 ps
CPU time 0.67 seconds
Started Jun 23 06:06:19 PM PDT 24
Finished Jun 23 06:06:20 PM PDT 24
Peak memory 192896 kb
Host smart-5e3d7207-7efc-4576-8e9f-2b044dd48fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102029086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1102029086
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2847257845
Short name T351
Test name
Test status
Simulation time 2350366530 ps
CPU time 1.64 seconds
Started Jun 23 06:06:19 PM PDT 24
Finished Jun 23 06:06:21 PM PDT 24
Peak memory 194032 kb
Host smart-2cc62273-5e44-49ef-bcf0-f933cbc82018
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847257845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2847257845
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.4153960634
Short name T302
Test name
Test status
Simulation time 807991282 ps
CPU time 2.39 seconds
Started Jun 23 06:06:23 PM PDT 24
Finished Jun 23 06:06:26 PM PDT 24
Peak memory 198504 kb
Host smart-bfe81d91-004a-4077-b75f-10cc1d651214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153960634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.4153960634
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2388835432
Short name T411
Test name
Test status
Simulation time 7771941288 ps
CPU time 6.53 seconds
Started Jun 23 06:06:22 PM PDT 24
Finished Jun 23 06:06:28 PM PDT 24
Peak memory 198028 kb
Host smart-d77fa45f-72b1-4be5-b98b-eabc3261b802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388835432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2388835432
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.248135994
Short name T415
Test name
Test status
Simulation time 550426896 ps
CPU time 1.06 seconds
Started Jun 23 06:06:28 PM PDT 24
Finished Jun 23 06:06:29 PM PDT 24
Peak memory 196040 kb
Host smart-f4be2d91-1337-4231-8506-756272cb8bfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248135994 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.248135994
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3208329824
Short name T327
Test name
Test status
Simulation time 548705688 ps
CPU time 0.63 seconds
Started Jun 23 06:06:27 PM PDT 24
Finished Jun 23 06:06:28 PM PDT 24
Peak memory 192140 kb
Host smart-2b789baf-120e-4a4c-93b2-58a0f520c492
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208329824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3208329824
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.557435354
Short name T398
Test name
Test status
Simulation time 357540646 ps
CPU time 0.88 seconds
Started Jun 23 06:06:22 PM PDT 24
Finished Jun 23 06:06:24 PM PDT 24
Peak memory 183660 kb
Host smart-7696986e-4175-4e62-aa12-c54c2e78d90a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557435354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.557435354
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2947013480
Short name T295
Test name
Test status
Simulation time 2217539252 ps
CPU time 1.28 seconds
Started Jun 23 06:06:28 PM PDT 24
Finished Jun 23 06:06:30 PM PDT 24
Peak memory 193992 kb
Host smart-0dc44fa1-1e6a-4eb2-b4c0-6880ff10fa43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947013480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2947013480
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3149854833
Short name T281
Test name
Test status
Simulation time 415282184 ps
CPU time 2.07 seconds
Started Jun 23 06:06:23 PM PDT 24
Finished Jun 23 06:06:26 PM PDT 24
Peak memory 198504 kb
Host smart-28be34f5-6d59-4706-a16e-b4e31ff4023a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149854833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3149854833
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2728377933
Short name T320
Test name
Test status
Simulation time 8543365643 ps
CPU time 14.29 seconds
Started Jun 23 06:06:19 PM PDT 24
Finished Jun 23 06:06:34 PM PDT 24
Peak memory 198132 kb
Host smart-bd94e192-bc11-4bc5-8b96-2d3800b64f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728377933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2728377933
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4107715193
Short name T392
Test name
Test status
Simulation time 487084020 ps
CPU time 1.08 seconds
Started Jun 23 06:06:24 PM PDT 24
Finished Jun 23 06:06:26 PM PDT 24
Peak memory 195748 kb
Host smart-f975506f-e6e4-442b-a81a-485ebf865ebc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107715193 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.4107715193
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2002294101
Short name T372
Test name
Test status
Simulation time 563834321 ps
CPU time 0.73 seconds
Started Jun 23 06:06:26 PM PDT 24
Finished Jun 23 06:06:27 PM PDT 24
Peak memory 183676 kb
Host smart-3dd84ea9-1787-458a-952f-bbe5ced96728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002294101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2002294101
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3114577073
Short name T369
Test name
Test status
Simulation time 430075130 ps
CPU time 1.16 seconds
Started Jun 23 06:06:24 PM PDT 24
Finished Jun 23 06:06:25 PM PDT 24
Peak memory 192876 kb
Host smart-ccfc7117-a77e-43b8-835c-0b00037d260c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114577073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3114577073
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2158430790
Short name T71
Test name
Test status
Simulation time 2004554505 ps
CPU time 1.27 seconds
Started Jun 23 06:06:27 PM PDT 24
Finished Jun 23 06:06:28 PM PDT 24
Peak memory 183940 kb
Host smart-ea3d5195-1853-4124-a675-1b765571213b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158430790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2158430790
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1427957986
Short name T294
Test name
Test status
Simulation time 436155389 ps
CPU time 1.58 seconds
Started Jun 23 06:06:29 PM PDT 24
Finished Jun 23 06:06:31 PM PDT 24
Peak memory 198548 kb
Host smart-4507fe71-253c-4670-8a93-f17b51259550
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427957986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1427957986
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.306918771
Short name T406
Test name
Test status
Simulation time 8663457126 ps
CPU time 12.68 seconds
Started Jun 23 06:06:24 PM PDT 24
Finished Jun 23 06:06:37 PM PDT 24
Peak memory 198200 kb
Host smart-1d594d97-7e15-4053-804e-7d3f7ba64236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306918771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.306918771
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1141670304
Short name T388
Test name
Test status
Simulation time 505157237 ps
CPU time 0.87 seconds
Started Jun 23 06:06:23 PM PDT 24
Finished Jun 23 06:06:25 PM PDT 24
Peak memory 196064 kb
Host smart-ca8d1a9b-1719-4a7f-b457-d1f66d55311b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141670304 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1141670304
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.584864368
Short name T57
Test name
Test status
Simulation time 471777215 ps
CPU time 0.76 seconds
Started Jun 23 06:06:25 PM PDT 24
Finished Jun 23 06:06:26 PM PDT 24
Peak memory 193856 kb
Host smart-5d468a7f-add8-4934-904e-6a3284d10aa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584864368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.584864368
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1764036846
Short name T338
Test name
Test status
Simulation time 455003871 ps
CPU time 1.22 seconds
Started Jun 23 06:06:28 PM PDT 24
Finished Jun 23 06:06:30 PM PDT 24
Peak memory 183668 kb
Host smart-d7b5f99f-c390-4425-83d4-5b0182b29317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764036846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1764036846
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3693724814
Short name T74
Test name
Test status
Simulation time 2895506064 ps
CPU time 4.36 seconds
Started Jun 23 06:06:25 PM PDT 24
Finished Jun 23 06:06:30 PM PDT 24
Peak memory 195156 kb
Host smart-bf84930b-7c82-46e9-ad52-5e8d7fc60294
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693724814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3693724814
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.447693091
Short name T421
Test name
Test status
Simulation time 699121034 ps
CPU time 1.47 seconds
Started Jun 23 06:06:25 PM PDT 24
Finished Jun 23 06:06:27 PM PDT 24
Peak memory 198468 kb
Host smart-5cc9ec2c-3f44-4eca-b993-c7e1eef98521
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447693091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.447693091
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3415559567
Short name T382
Test name
Test status
Simulation time 4301050830 ps
CPU time 1.34 seconds
Started Jun 23 06:06:28 PM PDT 24
Finished Jun 23 06:06:30 PM PDT 24
Peak memory 196432 kb
Host smart-c965320f-e18a-47b8-a80e-503ff3426078
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415559567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3415559567
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.354721241
Short name T367
Test name
Test status
Simulation time 410401444 ps
CPU time 0.91 seconds
Started Jun 23 06:06:28 PM PDT 24
Finished Jun 23 06:06:30 PM PDT 24
Peak memory 195944 kb
Host smart-c2c3e5ef-16b2-41a2-93bc-8a1720d8b150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354721241 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.354721241
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3464480418
Short name T384
Test name
Test status
Simulation time 319567473 ps
CPU time 1.09 seconds
Started Jun 23 06:06:26 PM PDT 24
Finished Jun 23 06:06:27 PM PDT 24
Peak memory 192884 kb
Host smart-b5290bd8-fc43-4184-8c87-1c7961672b5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464480418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3464480418
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1622052348
Short name T289
Test name
Test status
Simulation time 376427647 ps
CPU time 0.69 seconds
Started Jun 23 06:06:25 PM PDT 24
Finished Jun 23 06:06:26 PM PDT 24
Peak memory 183572 kb
Host smart-32d22acc-435e-4b74-b7c3-0ec4c2653a6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622052348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1622052348
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2164575094
Short name T36
Test name
Test status
Simulation time 974624949 ps
CPU time 0.76 seconds
Started Jun 23 06:06:28 PM PDT 24
Finished Jun 23 06:06:29 PM PDT 24
Peak memory 183744 kb
Host smart-390e11ce-8e1b-4907-b9ce-1c83f2b7f928
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164575094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2164575094
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3441641692
Short name T298
Test name
Test status
Simulation time 564507649 ps
CPU time 2.23 seconds
Started Jun 23 06:06:23 PM PDT 24
Finished Jun 23 06:06:26 PM PDT 24
Peak memory 198564 kb
Host smart-a0698c77-60bb-45f7-b9d0-64d04c291920
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441641692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3441641692
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3087066357
Short name T189
Test name
Test status
Simulation time 8206421448 ps
CPU time 6.87 seconds
Started Jun 23 06:06:25 PM PDT 24
Finished Jun 23 06:06:33 PM PDT 24
Peak memory 198092 kb
Host smart-eea76a6b-2066-4949-a1cd-42667a74b61c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087066357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3087066357
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.352727890
Short name T379
Test name
Test status
Simulation time 573716380 ps
CPU time 0.88 seconds
Started Jun 23 06:06:30 PM PDT 24
Finished Jun 23 06:06:31 PM PDT 24
Peak memory 196000 kb
Host smart-697fcb1c-e85b-41fa-ab36-3b7d6bab9419
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352727890 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.352727890
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2490484448
Short name T285
Test name
Test status
Simulation time 501402457 ps
CPU time 0.74 seconds
Started Jun 23 06:06:32 PM PDT 24
Finished Jun 23 06:06:34 PM PDT 24
Peak memory 192116 kb
Host smart-01bf81ed-91f1-4863-a90d-65a7ce4c1dd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490484448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2490484448
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.759299920
Short name T312
Test name
Test status
Simulation time 367482349 ps
CPU time 1.12 seconds
Started Jun 23 06:06:24 PM PDT 24
Finished Jun 23 06:06:26 PM PDT 24
Peak memory 183668 kb
Host smart-b2aa70f7-bf25-486f-9c05-8173a7c526bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759299920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.759299920
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.886240888
Short name T407
Test name
Test status
Simulation time 2132881573 ps
CPU time 3.28 seconds
Started Jun 23 06:06:31 PM PDT 24
Finished Jun 23 06:06:35 PM PDT 24
Peak memory 194680 kb
Host smart-d6e58d4c-a463-49ed-856a-3a0a0a25e9bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886240888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.886240888
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3345480379
Short name T288
Test name
Test status
Simulation time 461885564 ps
CPU time 1.95 seconds
Started Jun 23 06:06:23 PM PDT 24
Finished Jun 23 06:06:26 PM PDT 24
Peak memory 198492 kb
Host smart-dc9f0ce3-9dc5-4d73-99b7-eed3fa158028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345480379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3345480379
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2601994995
Short name T414
Test name
Test status
Simulation time 8265356765 ps
CPU time 11.51 seconds
Started Jun 23 06:06:24 PM PDT 24
Finished Jun 23 06:06:36 PM PDT 24
Peak memory 198236 kb
Host smart-1328b575-92dd-4bb9-8bf4-9489c1ed74b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601994995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2601994995
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.554919681
Short name T344
Test name
Test status
Simulation time 512439965 ps
CPU time 0.81 seconds
Started Jun 23 06:06:29 PM PDT 24
Finished Jun 23 06:06:31 PM PDT 24
Peak memory 196148 kb
Host smart-ce2e54d8-4da7-4e07-ae98-c59872366a29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554919681 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.554919681
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2237638131
Short name T34
Test name
Test status
Simulation time 394225581 ps
CPU time 0.85 seconds
Started Jun 23 06:06:32 PM PDT 24
Finished Jun 23 06:06:34 PM PDT 24
Peak memory 193292 kb
Host smart-f5842145-8294-45bb-aaee-c2de71ad8b90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237638131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2237638131
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.747266509
Short name T307
Test name
Test status
Simulation time 366648497 ps
CPU time 0.59 seconds
Started Jun 23 06:06:31 PM PDT 24
Finished Jun 23 06:06:32 PM PDT 24
Peak memory 192888 kb
Host smart-f36a3372-1fab-4bf0-94f7-74be1ff80b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747266509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.747266509
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4042177935
Short name T400
Test name
Test status
Simulation time 2456988947 ps
CPU time 2.29 seconds
Started Jun 23 06:06:32 PM PDT 24
Finished Jun 23 06:06:34 PM PDT 24
Peak memory 183900 kb
Host smart-f2ebb2ca-082c-439b-81c0-f40cfb48404e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042177935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.4042177935
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3400019465
Short name T361
Test name
Test status
Simulation time 381231825 ps
CPU time 1.7 seconds
Started Jun 23 06:06:32 PM PDT 24
Finished Jun 23 06:06:34 PM PDT 24
Peak memory 198532 kb
Host smart-530ea02d-ae53-4e02-a3a4-c956c5e68ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400019465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3400019465
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2401200109
Short name T191
Test name
Test status
Simulation time 4012715068 ps
CPU time 7.38 seconds
Started Jun 23 06:06:33 PM PDT 24
Finished Jun 23 06:06:41 PM PDT 24
Peak memory 197652 kb
Host smart-84e97ce9-a71a-411f-9fb9-b9479c638a24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401200109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2401200109
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.500775624
Short name T55
Test name
Test status
Simulation time 574529745 ps
CPU time 0.79 seconds
Started Jun 23 06:06:09 PM PDT 24
Finished Jun 23 06:06:10 PM PDT 24
Peak memory 183664 kb
Host smart-4b114122-d765-4a83-bb10-149552676536
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500775624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.500775624
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3956465128
Short name T62
Test name
Test status
Simulation time 4599085971 ps
CPU time 2.98 seconds
Started Jun 23 06:06:01 PM PDT 24
Finished Jun 23 06:06:05 PM PDT 24
Peak memory 192072 kb
Host smart-98d88fac-bdf6-4a55-9159-d6d68c9130c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956465128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3956465128
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3646021023
Short name T360
Test name
Test status
Simulation time 826825263 ps
CPU time 1.6 seconds
Started Jun 23 06:06:05 PM PDT 24
Finished Jun 23 06:06:07 PM PDT 24
Peak memory 192888 kb
Host smart-48f1bbb2-6518-4a77-bb59-f84bdff12d6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646021023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3646021023
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.76473292
Short name T195
Test name
Test status
Simulation time 388980281 ps
CPU time 0.84 seconds
Started Jun 23 06:06:03 PM PDT 24
Finished Jun 23 06:06:04 PM PDT 24
Peak memory 195988 kb
Host smart-0c000486-dd60-4e3a-9e6d-48baf9d7998a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76473292 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.76473292
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3160227422
Short name T350
Test name
Test status
Simulation time 403779397 ps
CPU time 0.84 seconds
Started Jun 23 06:06:03 PM PDT 24
Finished Jun 23 06:06:04 PM PDT 24
Peak memory 192956 kb
Host smart-2ca0a4d5-668d-47fb-97ff-50958b5f6669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160227422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3160227422
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3335304117
Short name T418
Test name
Test status
Simulation time 417260131 ps
CPU time 0.59 seconds
Started Jun 23 06:06:06 PM PDT 24
Finished Jun 23 06:06:07 PM PDT 24
Peak memory 183672 kb
Host smart-e56d868e-a0b6-4e9c-a293-61531e4407bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335304117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3335304117
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2178656881
Short name T386
Test name
Test status
Simulation time 437797703 ps
CPU time 1.14 seconds
Started Jun 23 06:06:04 PM PDT 24
Finished Jun 23 06:06:06 PM PDT 24
Peak memory 183596 kb
Host smart-3895bcd3-b05b-4895-baab-18a1c9b17292
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178656881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2178656881
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1681469399
Short name T296
Test name
Test status
Simulation time 277128713 ps
CPU time 0.91 seconds
Started Jun 23 06:06:11 PM PDT 24
Finished Jun 23 06:06:12 PM PDT 24
Peak memory 183568 kb
Host smart-8f5dfa65-4de1-46cd-b610-b02d7db7dab5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681469399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1681469399
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2496745668
Short name T354
Test name
Test status
Simulation time 1089989540 ps
CPU time 1.43 seconds
Started Jun 23 06:06:02 PM PDT 24
Finished Jun 23 06:06:04 PM PDT 24
Peak memory 183732 kb
Host smart-98cce4df-b9a1-44a0-8925-e1e57be7a4aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496745668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2496745668
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2934939819
Short name T420
Test name
Test status
Simulation time 494811726 ps
CPU time 1.21 seconds
Started Jun 23 06:06:03 PM PDT 24
Finished Jun 23 06:06:05 PM PDT 24
Peak memory 198392 kb
Host smart-98002318-e726-44d5-bc86-e7172933613c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934939819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2934939819
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1311843838
Short name T38
Test name
Test status
Simulation time 4359211390 ps
CPU time 2.75 seconds
Started Jun 23 06:06:07 PM PDT 24
Finished Jun 23 06:06:10 PM PDT 24
Peak memory 197772 kb
Host smart-df7b4323-810a-4ae1-a3b2-d42c83d8582f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311843838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1311843838
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1758688551
Short name T378
Test name
Test status
Simulation time 281374120 ps
CPU time 0.73 seconds
Started Jun 23 06:06:29 PM PDT 24
Finished Jun 23 06:06:30 PM PDT 24
Peak memory 183668 kb
Host smart-044327df-6a0b-4b2f-a29c-2b9ef7c31693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758688551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1758688551
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.340343231
Short name T323
Test name
Test status
Simulation time 449196652 ps
CPU time 0.91 seconds
Started Jun 23 06:06:29 PM PDT 24
Finished Jun 23 06:06:31 PM PDT 24
Peak memory 183672 kb
Host smart-bbaced57-991c-4271-a93e-bbbb6cb86b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340343231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.340343231
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3613440457
Short name T280
Test name
Test status
Simulation time 269705047 ps
CPU time 0.91 seconds
Started Jun 23 06:06:32 PM PDT 24
Finished Jun 23 06:06:34 PM PDT 24
Peak memory 183672 kb
Host smart-2208c037-3ec4-496f-8a27-259bfd8a11fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613440457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3613440457
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3036113363
Short name T335
Test name
Test status
Simulation time 498605652 ps
CPU time 1.33 seconds
Started Jun 23 06:06:28 PM PDT 24
Finished Jun 23 06:06:29 PM PDT 24
Peak memory 183704 kb
Host smart-8f69439a-6754-4fa0-9efd-37c363f02c1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036113363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3036113363
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.545439069
Short name T322
Test name
Test status
Simulation time 381492384 ps
CPU time 0.72 seconds
Started Jun 23 06:06:30 PM PDT 24
Finished Jun 23 06:06:31 PM PDT 24
Peak memory 183640 kb
Host smart-be9724ac-e37d-4882-9d87-2cd84dcf961f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545439069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.545439069
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2450357425
Short name T301
Test name
Test status
Simulation time 473531357 ps
CPU time 1.15 seconds
Started Jun 23 06:06:28 PM PDT 24
Finished Jun 23 06:06:30 PM PDT 24
Peak memory 183568 kb
Host smart-e67c119a-0fc9-4b74-8eee-aa93d0060b86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450357425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2450357425
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4285900297
Short name T374
Test name
Test status
Simulation time 322454233 ps
CPU time 1 seconds
Started Jun 23 06:06:29 PM PDT 24
Finished Jun 23 06:06:31 PM PDT 24
Peak memory 192832 kb
Host smart-54182cad-dc04-4a8a-8ce1-4a4bdc94bea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285900297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4285900297
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4247399781
Short name T348
Test name
Test status
Simulation time 523281469 ps
CPU time 0.9 seconds
Started Jun 23 06:06:34 PM PDT 24
Finished Jun 23 06:06:36 PM PDT 24
Peak memory 183664 kb
Host smart-aafe9789-e503-427e-abdd-3b35597863b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247399781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.4247399781
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3090535687
Short name T341
Test name
Test status
Simulation time 299055923 ps
CPU time 0.87 seconds
Started Jun 23 06:06:32 PM PDT 24
Finished Jun 23 06:06:34 PM PDT 24
Peak memory 183624 kb
Host smart-dba28243-22b8-4fef-b4a7-f6493c731805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090535687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3090535687
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3391394832
Short name T318
Test name
Test status
Simulation time 566653996 ps
CPU time 0.66 seconds
Started Jun 23 06:06:29 PM PDT 24
Finished Jun 23 06:06:31 PM PDT 24
Peak memory 183668 kb
Host smart-70bd14ab-abb3-4daf-8f9e-b211ea9cbd4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391394832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3391394832
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.564108584
Short name T59
Test name
Test status
Simulation time 587403755 ps
CPU time 0.98 seconds
Started Jun 23 06:06:07 PM PDT 24
Finished Jun 23 06:06:09 PM PDT 24
Peak memory 193848 kb
Host smart-b5bad078-a95b-4745-9248-c9d78297f5d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564108584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.564108584
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2433417643
Short name T65
Test name
Test status
Simulation time 13138421807 ps
CPU time 7.63 seconds
Started Jun 23 06:06:09 PM PDT 24
Finished Jun 23 06:06:17 PM PDT 24
Peak memory 192072 kb
Host smart-96097f52-b345-4de8-962b-e18ae1b8922d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433417643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2433417643
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4290134614
Short name T334
Test name
Test status
Simulation time 1306639803 ps
CPU time 0.79 seconds
Started Jun 23 06:06:07 PM PDT 24
Finished Jun 23 06:06:08 PM PDT 24
Peak memory 192888 kb
Host smart-631d449a-e6de-4052-b9de-dccb68652a74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290134614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.4290134614
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2947817389
Short name T381
Test name
Test status
Simulation time 382520704 ps
CPU time 0.75 seconds
Started Jun 23 06:06:10 PM PDT 24
Finished Jun 23 06:06:11 PM PDT 24
Peak memory 195580 kb
Host smart-faecee0e-e3c3-4c6b-a057-78f4a217605f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947817389 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2947817389
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.353199785
Short name T397
Test name
Test status
Simulation time 382190229 ps
CPU time 0.69 seconds
Started Jun 23 06:06:00 PM PDT 24
Finished Jun 23 06:06:02 PM PDT 24
Peak memory 192832 kb
Host smart-89a1872b-6761-475f-be53-30b705a017cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353199785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.353199785
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2850753378
Short name T370
Test name
Test status
Simulation time 489294306 ps
CPU time 1.14 seconds
Started Jun 23 06:06:02 PM PDT 24
Finished Jun 23 06:06:03 PM PDT 24
Peak memory 183568 kb
Host smart-00d799da-92d6-4c67-ba83-eb6b2b47b9c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850753378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2850753378
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3261199838
Short name T366
Test name
Test status
Simulation time 384576151 ps
CPU time 0.66 seconds
Started Jun 23 06:06:04 PM PDT 24
Finished Jun 23 06:06:05 PM PDT 24
Peak memory 183564 kb
Host smart-76d2d2e5-2017-4ba5-b68b-ac6adb56d86c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261199838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3261199838
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1949899717
Short name T376
Test name
Test status
Simulation time 284588378 ps
CPU time 0.63 seconds
Started Jun 23 06:06:09 PM PDT 24
Finished Jun 23 06:06:10 PM PDT 24
Peak memory 183596 kb
Host smart-0044c699-b9b8-4972-a641-6a00c9ea1051
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949899717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1949899717
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.158141693
Short name T395
Test name
Test status
Simulation time 1468210956 ps
CPU time 1.06 seconds
Started Jun 23 06:06:06 PM PDT 24
Finished Jun 23 06:06:08 PM PDT 24
Peak memory 194064 kb
Host smart-55896967-1774-4eb2-bd97-0ff3c9a14423
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158141693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.158141693
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4287329515
Short name T409
Test name
Test status
Simulation time 545888672 ps
CPU time 3.12 seconds
Started Jun 23 06:06:06 PM PDT 24
Finished Jun 23 06:06:10 PM PDT 24
Peak memory 198508 kb
Host smart-071fc100-8bb7-4596-9d3b-40d46d3cdd36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287329515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4287329515
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.898465757
Short name T332
Test name
Test status
Simulation time 4685835200 ps
CPU time 2.63 seconds
Started Jun 23 06:06:07 PM PDT 24
Finished Jun 23 06:06:10 PM PDT 24
Peak memory 197836 kb
Host smart-3029e601-770d-44c7-ba1c-514abe6ebc7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898465757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.898465757
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3198579679
Short name T331
Test name
Test status
Simulation time 397606834 ps
CPU time 1.04 seconds
Started Jun 23 06:06:32 PM PDT 24
Finished Jun 23 06:06:33 PM PDT 24
Peak memory 183676 kb
Host smart-5e6af2af-c36a-4848-a78d-f2617de27663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198579679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3198579679
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3628741171
Short name T422
Test name
Test status
Simulation time 355204006 ps
CPU time 1.07 seconds
Started Jun 23 06:06:32 PM PDT 24
Finished Jun 23 06:06:34 PM PDT 24
Peak memory 192816 kb
Host smart-432ee02f-c012-41a0-8f13-5027174ed147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628741171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3628741171
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1968963461
Short name T342
Test name
Test status
Simulation time 393360324 ps
CPU time 0.68 seconds
Started Jun 23 06:06:30 PM PDT 24
Finished Jun 23 06:06:31 PM PDT 24
Peak memory 183668 kb
Host smart-feca48b0-3a1f-4729-a9a6-6c6bbe6d7a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968963461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1968963461
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.902979941
Short name T363
Test name
Test status
Simulation time 351099682 ps
CPU time 1.03 seconds
Started Jun 23 06:06:33 PM PDT 24
Finished Jun 23 06:06:35 PM PDT 24
Peak memory 192840 kb
Host smart-79ed3ec4-3a0c-4ea6-91cb-f2d732d9f3db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902979941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.902979941
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2261607978
Short name T364
Test name
Test status
Simulation time 410763587 ps
CPU time 1.06 seconds
Started Jun 23 06:06:35 PM PDT 24
Finished Jun 23 06:06:37 PM PDT 24
Peak memory 183640 kb
Host smart-e2f77f16-f13f-44c7-b6b0-8961dd89ee5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261607978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2261607978
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3865054590
Short name T286
Test name
Test status
Simulation time 271707224 ps
CPU time 0.72 seconds
Started Jun 23 06:06:44 PM PDT 24
Finished Jun 23 06:06:46 PM PDT 24
Peak memory 183632 kb
Host smart-9de84082-2389-4fa6-a5ab-32c174acfa73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865054590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3865054590
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.941758164
Short name T321
Test name
Test status
Simulation time 403459103 ps
CPU time 1.07 seconds
Started Jun 23 06:06:33 PM PDT 24
Finished Jun 23 06:06:36 PM PDT 24
Peak memory 183668 kb
Host smart-532d2eb0-1efa-4191-843d-0aeb559ca38f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941758164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.941758164
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2147504084
Short name T394
Test name
Test status
Simulation time 301976187 ps
CPU time 0.99 seconds
Started Jun 23 06:06:36 PM PDT 24
Finished Jun 23 06:06:37 PM PDT 24
Peak memory 183640 kb
Host smart-3a6b17f0-9b66-4846-a03c-d25bb5d7d4fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147504084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2147504084
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.443368676
Short name T375
Test name
Test status
Simulation time 371029336 ps
CPU time 1.07 seconds
Started Jun 23 06:06:34 PM PDT 24
Finished Jun 23 06:06:36 PM PDT 24
Peak memory 183668 kb
Host smart-ed44f702-f88b-4348-92b6-7764751923fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443368676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.443368676
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3261495077
Short name T284
Test name
Test status
Simulation time 488985881 ps
CPU time 0.68 seconds
Started Jun 23 06:06:33 PM PDT 24
Finished Jun 23 06:06:34 PM PDT 24
Peak memory 183668 kb
Host smart-c450e1d5-5b6d-4373-9210-1eb3ca3b451c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261495077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3261495077
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3035240492
Short name T56
Test name
Test status
Simulation time 699239343 ps
CPU time 1.78 seconds
Started Jun 23 06:06:12 PM PDT 24
Finished Jun 23 06:06:15 PM PDT 24
Peak memory 194284 kb
Host smart-40d5ed41-e195-4a1f-a62e-c43300ecfed3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035240492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3035240492
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2954688549
Short name T60
Test name
Test status
Simulation time 6331656389 ps
CPU time 5.21 seconds
Started Jun 23 06:06:12 PM PDT 24
Finished Jun 23 06:06:18 PM PDT 24
Peak memory 196312 kb
Host smart-1a93e077-5930-4b86-89be-bca0c574eefa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954688549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2954688549
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1089396557
Short name T61
Test name
Test status
Simulation time 1185588918 ps
CPU time 2.45 seconds
Started Jun 23 06:06:12 PM PDT 24
Finished Jun 23 06:06:15 PM PDT 24
Peak memory 193912 kb
Host smart-dc549871-32cb-4ee6-834c-2c206ecd97cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089396557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1089396557
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1015457441
Short name T352
Test name
Test status
Simulation time 538532102 ps
CPU time 1.11 seconds
Started Jun 23 06:06:13 PM PDT 24
Finished Jun 23 06:06:15 PM PDT 24
Peak memory 197624 kb
Host smart-23628c43-c27e-41b3-bde9-cbc41518422d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015457441 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1015457441
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3316178801
Short name T64
Test name
Test status
Simulation time 419936554 ps
CPU time 0.82 seconds
Started Jun 23 06:06:10 PM PDT 24
Finished Jun 23 06:06:11 PM PDT 24
Peak memory 193908 kb
Host smart-757eddd6-4eaf-4bb2-a399-f0cf490251b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316178801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3316178801
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1277244428
Short name T306
Test name
Test status
Simulation time 342937600 ps
CPU time 0.69 seconds
Started Jun 23 06:06:12 PM PDT 24
Finished Jun 23 06:06:14 PM PDT 24
Peak memory 183644 kb
Host smart-9aa9cca3-c928-44a1-a284-82079bc6550f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277244428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1277244428
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.910462214
Short name T356
Test name
Test status
Simulation time 462731206 ps
CPU time 0.73 seconds
Started Jun 23 06:06:12 PM PDT 24
Finished Jun 23 06:06:14 PM PDT 24
Peak memory 183564 kb
Host smart-42eb6fd4-5cb4-43f2-b3fa-8ef94ac6f635
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910462214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.910462214
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2180370560
Short name T408
Test name
Test status
Simulation time 456078979 ps
CPU time 0.86 seconds
Started Jun 23 06:06:11 PM PDT 24
Finished Jun 23 06:06:12 PM PDT 24
Peak memory 183596 kb
Host smart-80382ab0-dd4d-4204-a311-1c852197edaa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180370560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2180370560
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3899406549
Short name T297
Test name
Test status
Simulation time 1266433942 ps
CPU time 2.12 seconds
Started Jun 23 06:06:12 PM PDT 24
Finished Jun 23 06:06:14 PM PDT 24
Peak memory 193988 kb
Host smart-b34373b1-385a-44a2-9273-869e2dfc44d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899406549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3899406549
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.285564722
Short name T290
Test name
Test status
Simulation time 332779248 ps
CPU time 1.88 seconds
Started Jun 23 06:06:09 PM PDT 24
Finished Jun 23 06:06:11 PM PDT 24
Peak memory 198532 kb
Host smart-a48036fc-e76c-4514-85fc-6c0e30d3b10c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285564722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.285564722
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.669469425
Short name T324
Test name
Test status
Simulation time 386444892 ps
CPU time 0.9 seconds
Started Jun 23 06:06:36 PM PDT 24
Finished Jun 23 06:06:38 PM PDT 24
Peak memory 192892 kb
Host smart-9b8ce054-617e-445b-8f65-ccc726847b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669469425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.669469425
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4163736914
Short name T377
Test name
Test status
Simulation time 514912264 ps
CPU time 0.73 seconds
Started Jun 23 06:06:44 PM PDT 24
Finished Jun 23 06:06:46 PM PDT 24
Peak memory 183628 kb
Host smart-7dfd2f56-41e4-4729-a321-b23b1ee6283b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163736914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.4163736914
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1114244826
Short name T345
Test name
Test status
Simulation time 380370954 ps
CPU time 0.67 seconds
Started Jun 23 06:06:35 PM PDT 24
Finished Jun 23 06:06:36 PM PDT 24
Peak memory 183664 kb
Host smart-124a77d3-85a4-4573-9ec0-9acb9037d3fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114244826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1114244826
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2811195818
Short name T343
Test name
Test status
Simulation time 520333808 ps
CPU time 1.16 seconds
Started Jun 23 06:06:39 PM PDT 24
Finished Jun 23 06:06:41 PM PDT 24
Peak memory 183664 kb
Host smart-959f6cf0-69ce-482b-be22-4240df7fdb5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811195818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2811195818
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1625256273
Short name T355
Test name
Test status
Simulation time 368562563 ps
CPU time 0.99 seconds
Started Jun 23 06:06:34 PM PDT 24
Finished Jun 23 06:06:36 PM PDT 24
Peak memory 192836 kb
Host smart-6e9f6f35-b431-4be3-ab1e-86ee8879c864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625256273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1625256273
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1307524690
Short name T385
Test name
Test status
Simulation time 269757205 ps
CPU time 0.69 seconds
Started Jun 23 06:06:37 PM PDT 24
Finished Jun 23 06:06:38 PM PDT 24
Peak memory 183664 kb
Host smart-767e9197-bf5e-43af-9f64-b2b473c34608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307524690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1307524690
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2483616778
Short name T416
Test name
Test status
Simulation time 415929856 ps
CPU time 1.1 seconds
Started Jun 23 06:06:36 PM PDT 24
Finished Jun 23 06:06:38 PM PDT 24
Peak memory 183668 kb
Host smart-16aa838f-fcb3-4745-8585-78d621e4d65e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483616778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2483616778
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4027854644
Short name T413
Test name
Test status
Simulation time 344569654 ps
CPU time 0.61 seconds
Started Jun 23 06:06:34 PM PDT 24
Finished Jun 23 06:06:35 PM PDT 24
Peak memory 192880 kb
Host smart-f156edca-52e8-49b0-9b86-ff1448f8295d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027854644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.4027854644
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1438603078
Short name T387
Test name
Test status
Simulation time 309221799 ps
CPU time 0.64 seconds
Started Jun 23 06:06:40 PM PDT 24
Finished Jun 23 06:06:41 PM PDT 24
Peak memory 183632 kb
Host smart-d658ab51-296e-4add-912e-96c1f60e0f2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438603078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1438603078
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.963740846
Short name T404
Test name
Test status
Simulation time 353365565 ps
CPU time 1.02 seconds
Started Jun 23 06:06:37 PM PDT 24
Finished Jun 23 06:06:38 PM PDT 24
Peak memory 183672 kb
Host smart-2632a6bd-a46c-4b82-9d0f-439c66e0b643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963740846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.963740846
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.101023751
Short name T310
Test name
Test status
Simulation time 483450042 ps
CPU time 0.93 seconds
Started Jun 23 06:06:15 PM PDT 24
Finished Jun 23 06:06:16 PM PDT 24
Peak memory 197000 kb
Host smart-83879913-94f3-41ee-a43b-bbb8e5b18fc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101023751 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.101023751
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.347246284
Short name T357
Test name
Test status
Simulation time 308306210 ps
CPU time 0.74 seconds
Started Jun 23 06:06:13 PM PDT 24
Finished Jun 23 06:06:14 PM PDT 24
Peak memory 192884 kb
Host smart-6e8091e0-564a-4cac-9f8d-f1581b2dbe05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347246284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.347246284
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2587929454
Short name T405
Test name
Test status
Simulation time 418576908 ps
CPU time 0.72 seconds
Started Jun 23 06:06:14 PM PDT 24
Finished Jun 23 06:06:15 PM PDT 24
Peak memory 183664 kb
Host smart-689b399a-115e-442a-8272-ec9fb09eeefa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587929454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2587929454
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2541044827
Short name T362
Test name
Test status
Simulation time 3089888450 ps
CPU time 3.07 seconds
Started Jun 23 06:06:16 PM PDT 24
Finished Jun 23 06:06:20 PM PDT 24
Peak memory 195464 kb
Host smart-2d6473ac-5a95-41a5-9a28-70ee2f686640
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541044827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2541044827
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.4016441463
Short name T293
Test name
Test status
Simulation time 697508240 ps
CPU time 1.51 seconds
Started Jun 23 06:06:11 PM PDT 24
Finished Jun 23 06:06:13 PM PDT 24
Peak memory 198532 kb
Host smart-5ce9be02-62ca-4300-9432-2a5525f4c003
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016441463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.4016441463
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.704939184
Short name T412
Test name
Test status
Simulation time 4317169636 ps
CPU time 3.86 seconds
Started Jun 23 06:06:16 PM PDT 24
Finished Jun 23 06:06:20 PM PDT 24
Peak memory 197944 kb
Host smart-3b555a64-9c43-4352-ab3e-d89213362cb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704939184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.704939184
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1354864316
Short name T300
Test name
Test status
Simulation time 562382001 ps
CPU time 1.03 seconds
Started Jun 23 06:06:15 PM PDT 24
Finished Jun 23 06:06:17 PM PDT 24
Peak memory 195672 kb
Host smart-b0f12a09-89cc-4845-8f15-90ff72d0258e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354864316 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1354864316
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1839925905
Short name T292
Test name
Test status
Simulation time 508632807 ps
CPU time 0.76 seconds
Started Jun 23 06:06:17 PM PDT 24
Finished Jun 23 06:06:18 PM PDT 24
Peak memory 193080 kb
Host smart-d578810d-5bd3-464e-88d3-1cb025ce6b97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839925905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1839925905
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1113058177
Short name T410
Test name
Test status
Simulation time 429663705 ps
CPU time 0.69 seconds
Started Jun 23 06:06:14 PM PDT 24
Finished Jun 23 06:06:16 PM PDT 24
Peak memory 192812 kb
Host smart-ee03ed9f-8629-4871-8992-7a26eb659921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113058177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1113058177
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.4201298927
Short name T423
Test name
Test status
Simulation time 2211190011 ps
CPU time 2.66 seconds
Started Jun 23 06:06:18 PM PDT 24
Finished Jun 23 06:06:22 PM PDT 24
Peak memory 193848 kb
Host smart-b7d4103a-c10e-4572-981a-2e38d9c09021
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201298927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.4201298927
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1664272547
Short name T368
Test name
Test status
Simulation time 537249957 ps
CPU time 2.61 seconds
Started Jun 23 06:06:17 PM PDT 24
Finished Jun 23 06:06:20 PM PDT 24
Peak memory 198540 kb
Host smart-9c6726c2-8b4c-49a9-a3d9-714905d22993
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664272547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1664272547
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.291902450
Short name T403
Test name
Test status
Simulation time 4492228957 ps
CPU time 2.54 seconds
Started Jun 23 06:06:13 PM PDT 24
Finished Jun 23 06:06:16 PM PDT 24
Peak memory 197552 kb
Host smart-57ea403b-dbb7-451c-811b-6025594691e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291902450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.291902450
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2461749551
Short name T304
Test name
Test status
Simulation time 527865778 ps
CPU time 0.81 seconds
Started Jun 23 06:06:12 PM PDT 24
Finished Jun 23 06:06:13 PM PDT 24
Peak memory 197448 kb
Host smart-1542af6f-a745-415a-beda-1858ed1ac8d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461749551 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2461749551
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2106744984
Short name T39
Test name
Test status
Simulation time 528937515 ps
CPU time 0.91 seconds
Started Jun 23 06:06:18 PM PDT 24
Finished Jun 23 06:06:20 PM PDT 24
Peak memory 183628 kb
Host smart-20059c87-fcc7-47ab-87cd-b7025d04b41b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106744984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2106744984
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1639834807
Short name T283
Test name
Test status
Simulation time 467371208 ps
CPU time 0.7 seconds
Started Jun 23 06:06:18 PM PDT 24
Finished Jun 23 06:06:20 PM PDT 24
Peak memory 183528 kb
Host smart-67f803d6-64be-4f6a-a924-db9720bef886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639834807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1639834807
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.729272870
Short name T69
Test name
Test status
Simulation time 1472741123 ps
CPU time 2.67 seconds
Started Jun 23 06:06:14 PM PDT 24
Finished Jun 23 06:06:17 PM PDT 24
Peak memory 193308 kb
Host smart-1bcf52dd-10f4-4ce8-94fe-9b65ca684001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729272870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.729272870
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2190755348
Short name T325
Test name
Test status
Simulation time 632948089 ps
CPU time 1.7 seconds
Started Jun 23 06:06:16 PM PDT 24
Finished Jun 23 06:06:18 PM PDT 24
Peak memory 198560 kb
Host smart-57f97f5d-01f0-4a6b-9452-caf45851880d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190755348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2190755348
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3249872847
Short name T396
Test name
Test status
Simulation time 4098536613 ps
CPU time 6.92 seconds
Started Jun 23 06:06:15 PM PDT 24
Finished Jun 23 06:06:22 PM PDT 24
Peak memory 197800 kb
Host smart-9da06a9d-6e6d-49e9-8a52-f492284b6abd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249872847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3249872847
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1191425458
Short name T353
Test name
Test status
Simulation time 471480457 ps
CPU time 0.97 seconds
Started Jun 23 06:06:11 PM PDT 24
Finished Jun 23 06:06:12 PM PDT 24
Peak memory 196044 kb
Host smart-f825a714-5d66-4764-a8b1-4d31eabaa4a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191425458 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1191425458
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3670025265
Short name T417
Test name
Test status
Simulation time 317059212 ps
CPU time 1.03 seconds
Started Jun 23 06:06:16 PM PDT 24
Finished Jun 23 06:06:18 PM PDT 24
Peak memory 191944 kb
Host smart-9e1f5513-086a-4645-aa75-aaaaa9a0e410
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670025265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3670025265
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3992792981
Short name T393
Test name
Test status
Simulation time 323908494 ps
CPU time 0.65 seconds
Started Jun 23 06:06:16 PM PDT 24
Finished Jun 23 06:06:17 PM PDT 24
Peak memory 192888 kb
Host smart-ce569498-f739-4349-b6e8-930a2e047387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992792981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3992792981
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2080611893
Short name T70
Test name
Test status
Simulation time 1067116338 ps
CPU time 1.14 seconds
Started Jun 23 06:06:18 PM PDT 24
Finished Jun 23 06:06:19 PM PDT 24
Peak memory 192832 kb
Host smart-63ac8a2a-4bda-45f6-a18e-7ee1bcddd3bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080611893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2080611893
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1568632496
Short name T340
Test name
Test status
Simulation time 474640774 ps
CPU time 2.04 seconds
Started Jun 23 06:06:16 PM PDT 24
Finished Jun 23 06:06:19 PM PDT 24
Peak memory 198536 kb
Host smart-d5a5ad3a-976c-41ac-b30e-047cc1756e2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568632496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1568632496
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3102730789
Short name T380
Test name
Test status
Simulation time 8853176906 ps
CPU time 2.66 seconds
Started Jun 23 06:06:12 PM PDT 24
Finished Jun 23 06:06:15 PM PDT 24
Peak memory 198236 kb
Host smart-08b5273d-f7b9-4484-bb43-9ed60d6a7776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102730789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3102730789
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2207349832
Short name T287
Test name
Test status
Simulation time 541996435 ps
CPU time 1.03 seconds
Started Jun 23 06:06:16 PM PDT 24
Finished Jun 23 06:06:18 PM PDT 24
Peak memory 195584 kb
Host smart-da58a537-8632-4e47-88b6-8555aa7000ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207349832 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2207349832
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4160564243
Short name T402
Test name
Test status
Simulation time 362850929 ps
CPU time 1.06 seconds
Started Jun 23 06:06:14 PM PDT 24
Finished Jun 23 06:06:15 PM PDT 24
Peak memory 192992 kb
Host smart-6c6e3299-488d-4866-b28d-3f30e359deff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160564243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.4160564243
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3318719541
Short name T305
Test name
Test status
Simulation time 295949518 ps
CPU time 0.61 seconds
Started Jun 23 06:06:12 PM PDT 24
Finished Jun 23 06:06:13 PM PDT 24
Peak memory 183680 kb
Host smart-c18de86e-efb8-43f3-aa3a-92f5018ec7a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318719541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3318719541
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1398933820
Short name T383
Test name
Test status
Simulation time 3246928004 ps
CPU time 7.72 seconds
Started Jun 23 06:06:20 PM PDT 24
Finished Jun 23 06:06:28 PM PDT 24
Peak memory 195144 kb
Host smart-3c45a1eb-99b7-4208-a86f-a3980949aeed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398933820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1398933820
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.864731036
Short name T282
Test name
Test status
Simulation time 607341992 ps
CPU time 1.42 seconds
Started Jun 23 06:06:12 PM PDT 24
Finished Jun 23 06:06:14 PM PDT 24
Peak memory 198496 kb
Host smart-cbde4ae7-a474-4ff2-b9f1-93ece94ce211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864731036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.864731036
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3824395781
Short name T391
Test name
Test status
Simulation time 4728797952 ps
CPU time 1.53 seconds
Started Jun 23 06:06:13 PM PDT 24
Finished Jun 23 06:06:15 PM PDT 24
Peak memory 196328 kb
Host smart-f8f60be0-717d-4d3c-a8c8-5060055c00c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824395781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3824395781
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3613780601
Short name T209
Test name
Test status
Simulation time 25436529276 ps
CPU time 17.93 seconds
Started Jun 23 06:05:18 PM PDT 24
Finished Jun 23 06:05:36 PM PDT 24
Peak memory 192468 kb
Host smart-714e52a3-3d04-49ff-b903-246ab14081ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613780601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3613780601
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1570199138
Short name T200
Test name
Test status
Simulation time 598019447 ps
CPU time 0.97 seconds
Started Jun 23 06:05:15 PM PDT 24
Finished Jun 23 06:05:17 PM PDT 24
Peak memory 192348 kb
Host smart-92cbf8e1-6ab0-446f-ad2d-80b5c8978f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570199138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1570199138
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.4154387562
Short name T223
Test name
Test status
Simulation time 40597497678 ps
CPU time 55.83 seconds
Started Jun 23 06:05:14 PM PDT 24
Finished Jun 23 06:06:11 PM PDT 24
Peak memory 192464 kb
Host smart-307c3e98-b341-4ea5-929d-cdb0d57a3fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154387562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.4154387562
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3992915549
Short name T16
Test name
Test status
Simulation time 8433889010 ps
CPU time 14.17 seconds
Started Jun 23 06:05:15 PM PDT 24
Finished Jun 23 06:05:30 PM PDT 24
Peak memory 216448 kb
Host smart-2bd3ce21-978a-4b90-96a5-555d3415a4fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992915549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3992915549
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2277119228
Short name T229
Test name
Test status
Simulation time 475552690 ps
CPU time 0.94 seconds
Started Jun 23 06:05:18 PM PDT 24
Finished Jun 23 06:05:19 PM PDT 24
Peak memory 192344 kb
Host smart-d7f721bd-e208-4a5f-83aa-d728060f3bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277119228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2277119228
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.62966522
Short name T193
Test name
Test status
Simulation time 16472286056 ps
CPU time 22.57 seconds
Started Jun 23 06:05:31 PM PDT 24
Finished Jun 23 06:05:54 PM PDT 24
Peak memory 192472 kb
Host smart-1ceebf3b-f24e-4f70-89ae-023f1b8b2916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62966522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.62966522
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3038449532
Short name T28
Test name
Test status
Simulation time 517622487 ps
CPU time 0.7 seconds
Started Jun 23 06:05:27 PM PDT 24
Finished Jun 23 06:05:28 PM PDT 24
Peak memory 192280 kb
Host smart-c4fb2141-78b6-4608-8bcc-6a492499646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038449532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3038449532
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.410525668
Short name T273
Test name
Test status
Simulation time 6640405302 ps
CPU time 10.57 seconds
Started Jun 23 06:05:26 PM PDT 24
Finished Jun 23 06:05:37 PM PDT 24
Peak memory 192404 kb
Host smart-2d7e7d84-1602-4ffb-bc29-e3e21944230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410525668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.410525668
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3419861524
Short name T27
Test name
Test status
Simulation time 494801388 ps
CPU time 0.8 seconds
Started Jun 23 06:05:28 PM PDT 24
Finished Jun 23 06:05:29 PM PDT 24
Peak memory 192344 kb
Host smart-d5aa4f08-ac7c-4d9b-8061-03123696ae07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419861524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3419861524
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.4132481045
Short name T227
Test name
Test status
Simulation time 38851198634 ps
CPU time 59.14 seconds
Started Jun 23 06:05:27 PM PDT 24
Finished Jun 23 06:06:27 PM PDT 24
Peak memory 192472 kb
Host smart-ef7b2a65-7f33-4a5d-b0e4-36af16420eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132481045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.4132481045
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3748062377
Short name T239
Test name
Test status
Simulation time 521548642 ps
CPU time 1.35 seconds
Started Jun 23 06:05:29 PM PDT 24
Finished Jun 23 06:05:30 PM PDT 24
Peak memory 192344 kb
Host smart-086a48c7-24cf-4b74-960b-c98f34cee4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748062377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3748062377
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3669708659
Short name T194
Test name
Test status
Simulation time 48664875977 ps
CPU time 70.24 seconds
Started Jun 23 06:05:28 PM PDT 24
Finished Jun 23 06:06:39 PM PDT 24
Peak memory 192412 kb
Host smart-e6ab259e-5c4b-4b42-9e61-a4a57471bc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669708659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3669708659
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1132443954
Short name T241
Test name
Test status
Simulation time 522345554 ps
CPU time 0.74 seconds
Started Jun 23 06:05:27 PM PDT 24
Finished Jun 23 06:05:29 PM PDT 24
Peak memory 197152 kb
Host smart-bf33af6b-292e-4a97-a0ed-79f5c784938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132443954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1132443954
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1787864553
Short name T259
Test name
Test status
Simulation time 38675684215 ps
CPU time 49.18 seconds
Started Jun 23 06:05:27 PM PDT 24
Finished Jun 23 06:06:17 PM PDT 24
Peak memory 192384 kb
Host smart-747c774a-e42b-4af2-97ac-19621f2e98b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787864553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1787864553
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3087112488
Short name T233
Test name
Test status
Simulation time 457066907 ps
CPU time 1.31 seconds
Started Jun 23 06:05:27 PM PDT 24
Finished Jun 23 06:05:29 PM PDT 24
Peak memory 192292 kb
Host smart-5c4400cf-5e70-4543-87ac-ee6f9ab923d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087112488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3087112488
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3619906006
Short name T228
Test name
Test status
Simulation time 8164349302 ps
CPU time 4.42 seconds
Started Jun 23 06:05:30 PM PDT 24
Finished Jun 23 06:05:34 PM PDT 24
Peak memory 192452 kb
Host smart-66b6ede5-4a0f-4a7f-9092-eac1fa81b355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619906006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3619906006
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2114666019
Short name T249
Test name
Test status
Simulation time 381415431 ps
CPU time 1.12 seconds
Started Jun 23 06:05:29 PM PDT 24
Finished Jun 23 06:05:31 PM PDT 24
Peak memory 192348 kb
Host smart-b5605c2a-2631-4e17-a3fa-3a2071dd6698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114666019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2114666019
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.4244457735
Short name T270
Test name
Test status
Simulation time 54831337008 ps
CPU time 16.64 seconds
Started Jun 23 06:05:31 PM PDT 24
Finished Jun 23 06:05:48 PM PDT 24
Peak memory 192460 kb
Host smart-8c65f546-9fae-4484-bf6f-144193c07805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244457735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.4244457735
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.206976459
Short name T205
Test name
Test status
Simulation time 482290665 ps
CPU time 1.04 seconds
Started Jun 23 06:05:28 PM PDT 24
Finished Jun 23 06:05:30 PM PDT 24
Peak memory 197152 kb
Host smart-12ae612e-0ed5-4661-8f39-51f42dfd4438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206976459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.206976459
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.969210587
Short name T245
Test name
Test status
Simulation time 28560323544 ps
CPU time 38.04 seconds
Started Jun 23 06:05:34 PM PDT 24
Finished Jun 23 06:06:13 PM PDT 24
Peak memory 192436 kb
Host smart-2671f4d9-0d05-4034-b107-bc23af3ac968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969210587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.969210587
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.81935599
Short name T279
Test name
Test status
Simulation time 523411480 ps
CPU time 1.12 seconds
Started Jun 23 06:05:32 PM PDT 24
Finished Jun 23 06:05:33 PM PDT 24
Peak memory 192496 kb
Host smart-9167725a-baad-44f8-9211-9af693d793f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81935599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.81935599
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3551214013
Short name T201
Test name
Test status
Simulation time 24988988929 ps
CPU time 10.08 seconds
Started Jun 23 06:05:31 PM PDT 24
Finished Jun 23 06:05:42 PM PDT 24
Peak memory 192444 kb
Host smart-26c388d9-db23-4bf1-a6bd-d3f1edf527e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551214013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3551214013
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1374261312
Short name T276
Test name
Test status
Simulation time 482463916 ps
CPU time 1.3 seconds
Started Jun 23 06:05:35 PM PDT 24
Finished Jun 23 06:05:37 PM PDT 24
Peak memory 197132 kb
Host smart-ebffc7ab-84eb-4432-94b9-2ca0e30b714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374261312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1374261312
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2233955284
Short name T256
Test name
Test status
Simulation time 39276384694 ps
CPU time 15.25 seconds
Started Jun 23 06:05:36 PM PDT 24
Finished Jun 23 06:05:51 PM PDT 24
Peak memory 192416 kb
Host smart-84d0d037-8c0c-4a6c-85fd-28faee1fd60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233955284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2233955284
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2257499289
Short name T217
Test name
Test status
Simulation time 510320627 ps
CPU time 1.36 seconds
Started Jun 23 06:05:36 PM PDT 24
Finished Jun 23 06:05:37 PM PDT 24
Peak memory 192308 kb
Host smart-d2c2c966-f586-41a2-b96f-9e8ccecaa141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257499289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2257499289
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2245420564
Short name T213
Test name
Test status
Simulation time 28066513591 ps
CPU time 38.18 seconds
Started Jun 23 06:05:35 PM PDT 24
Finished Jun 23 06:06:14 PM PDT 24
Peak memory 192464 kb
Host smart-28cae09f-f859-41c7-8a5d-b385b704fb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245420564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2245420564
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2781277584
Short name T20
Test name
Test status
Simulation time 4184399440 ps
CPU time 2.2 seconds
Started Jun 23 06:05:27 PM PDT 24
Finished Jun 23 06:05:30 PM PDT 24
Peak memory 216060 kb
Host smart-38a99f87-be17-499c-af02-36ec650920ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781277584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2781277584
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2233056993
Short name T253
Test name
Test status
Simulation time 571019584 ps
CPU time 1.03 seconds
Started Jun 23 06:05:23 PM PDT 24
Finished Jun 23 06:05:25 PM PDT 24
Peak memory 192344 kb
Host smart-5b8181fe-08cf-434e-8c74-81eb502dadfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233056993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2233056993
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.448794894
Short name T198
Test name
Test status
Simulation time 13372527035 ps
CPU time 4.35 seconds
Started Jun 23 06:05:34 PM PDT 24
Finished Jun 23 06:05:39 PM PDT 24
Peak memory 192472 kb
Host smart-7d27a5ea-9abc-42c1-ae15-f8675b8975e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448794894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.448794894
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3431581272
Short name T243
Test name
Test status
Simulation time 446079215 ps
CPU time 1.17 seconds
Started Jun 23 06:05:32 PM PDT 24
Finished Jun 23 06:05:33 PM PDT 24
Peak memory 192492 kb
Host smart-216e14bc-91ad-4ffc-98b0-e901a14b76bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431581272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3431581272
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3084248927
Short name T255
Test name
Test status
Simulation time 15773387951 ps
CPU time 25.54 seconds
Started Jun 23 06:05:32 PM PDT 24
Finished Jun 23 06:05:58 PM PDT 24
Peak memory 192464 kb
Host smart-674bb978-654e-4936-96bc-319d59dd817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084248927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3084248927
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2132037606
Short name T49
Test name
Test status
Simulation time 565148794 ps
CPU time 0.82 seconds
Started Jun 23 06:05:35 PM PDT 24
Finished Jun 23 06:05:36 PM PDT 24
Peak memory 192316 kb
Host smart-2cd03ba2-073f-48b2-8f93-441b45cc5f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132037606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2132037606
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2340451406
Short name T262
Test name
Test status
Simulation time 19746290678 ps
CPU time 30.36 seconds
Started Jun 23 06:05:42 PM PDT 24
Finished Jun 23 06:06:13 PM PDT 24
Peak memory 192452 kb
Host smart-c08657fa-cf4f-4d9e-8b80-697958f90568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340451406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2340451406
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.861380992
Short name T268
Test name
Test status
Simulation time 468530339 ps
CPU time 1.16 seconds
Started Jun 23 06:05:38 PM PDT 24
Finished Jun 23 06:05:40 PM PDT 24
Peak memory 197128 kb
Host smart-f7251578-a069-4b80-aeb8-8e4167b5d6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861380992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.861380992
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1491039321
Short name T202
Test name
Test status
Simulation time 9465613417 ps
CPU time 14.63 seconds
Started Jun 23 06:05:39 PM PDT 24
Finished Jun 23 06:05:54 PM PDT 24
Peak memory 192460 kb
Host smart-85b47cfa-995e-4027-af7d-2d71efdbbe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491039321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1491039321
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3952491152
Short name T197
Test name
Test status
Simulation time 557361656 ps
CPU time 0.77 seconds
Started Jun 23 06:05:38 PM PDT 24
Finished Jun 23 06:05:39 PM PDT 24
Peak memory 192352 kb
Host smart-9315b8e3-b744-4151-8776-332957db55a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952491152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3952491152
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1815926095
Short name T179
Test name
Test status
Simulation time 740976780 ps
CPU time 0.67 seconds
Started Jun 23 06:05:39 PM PDT 24
Finished Jun 23 06:05:40 PM PDT 24
Peak memory 197188 kb
Host smart-b91b84f9-f783-4156-a029-fecf36e6a111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815926095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1815926095
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3637974497
Short name T45
Test name
Test status
Simulation time 4210551277 ps
CPU time 2.05 seconds
Started Jun 23 06:05:37 PM PDT 24
Finished Jun 23 06:05:40 PM PDT 24
Peak memory 192432 kb
Host smart-0585a46f-e44b-4b03-a8ba-0a6eb3960921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637974497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3637974497
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1927313623
Short name T224
Test name
Test status
Simulation time 453660627 ps
CPU time 0.76 seconds
Started Jun 23 06:05:37 PM PDT 24
Finished Jun 23 06:05:38 PM PDT 24
Peak memory 197156 kb
Host smart-2cc69b2d-0d11-47d4-9d79-17f675f218e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927313623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1927313623
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3856029997
Short name T8
Test name
Test status
Simulation time 6304300085 ps
CPU time 10.63 seconds
Started Jun 23 06:05:37 PM PDT 24
Finished Jun 23 06:05:48 PM PDT 24
Peak memory 192460 kb
Host smart-59489f42-b330-4684-baca-1d59fc60c919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856029997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3856029997
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1202863223
Short name T218
Test name
Test status
Simulation time 426741903 ps
CPU time 0.94 seconds
Started Jun 23 06:05:37 PM PDT 24
Finished Jun 23 06:05:38 PM PDT 24
Peak memory 192352 kb
Host smart-6e235f05-1d2e-4140-8c4b-72dba6ac7aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202863223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1202863223
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2501002528
Short name T221
Test name
Test status
Simulation time 14663637610 ps
CPU time 1.93 seconds
Started Jun 23 06:05:40 PM PDT 24
Finished Jun 23 06:05:42 PM PDT 24
Peak memory 192460 kb
Host smart-e16d7894-5e61-4533-bec9-3682571fd5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501002528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2501002528
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3514603205
Short name T226
Test name
Test status
Simulation time 417634648 ps
CPU time 1.08 seconds
Started Jun 23 06:05:37 PM PDT 24
Finished Jun 23 06:05:39 PM PDT 24
Peak memory 192292 kb
Host smart-52f750ad-7265-4280-be16-2dc2fca1a9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514603205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3514603205
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.743181970
Short name T225
Test name
Test status
Simulation time 24790213495 ps
CPU time 33.44 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:06:21 PM PDT 24
Peak memory 192420 kb
Host smart-16585061-c78a-48d2-8f3c-d41dec2c21d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743181970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.743181970
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.119353128
Short name T196
Test name
Test status
Simulation time 531646910 ps
CPU time 1.02 seconds
Started Jun 23 06:05:38 PM PDT 24
Finished Jun 23 06:05:39 PM PDT 24
Peak memory 197152 kb
Host smart-1a2472b0-068b-4e21-9dde-051715ba82d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119353128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.119353128
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3055070675
Short name T211
Test name
Test status
Simulation time 7613079668 ps
CPU time 12.45 seconds
Started Jun 23 06:05:41 PM PDT 24
Finished Jun 23 06:05:54 PM PDT 24
Peak memory 192452 kb
Host smart-35218f15-46a8-4f6a-87c8-a4cb96c55f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055070675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3055070675
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.450158726
Short name T265
Test name
Test status
Simulation time 373842655 ps
CPU time 1.21 seconds
Started Jun 23 06:05:36 PM PDT 24
Finished Jun 23 06:05:38 PM PDT 24
Peak memory 197104 kb
Host smart-543e3ab2-bf43-4050-baf2-1ed959e90e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450158726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.450158726
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1972385798
Short name T43
Test name
Test status
Simulation time 54702862293 ps
CPU time 57.32 seconds
Started Jun 23 06:05:38 PM PDT 24
Finished Jun 23 06:06:36 PM PDT 24
Peak memory 192428 kb
Host smart-c84ac578-604d-4ddf-ae6d-8bcf04a64be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972385798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1972385798
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3810180325
Short name T7
Test name
Test status
Simulation time 457509770 ps
CPU time 0.75 seconds
Started Jun 23 06:05:37 PM PDT 24
Finished Jun 23 06:05:38 PM PDT 24
Peak memory 192356 kb
Host smart-e6fae5aa-d526-481d-b0a7-c04ae980740d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810180325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3810180325
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3401107174
Short name T251
Test name
Test status
Simulation time 24280537306 ps
CPU time 8.5 seconds
Started Jun 23 06:05:19 PM PDT 24
Finished Jun 23 06:05:28 PM PDT 24
Peak memory 192456 kb
Host smart-c29aa5bc-19d0-4a2d-9dce-a2e45cf18b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401107174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3401107174
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1622486666
Short name T19
Test name
Test status
Simulation time 8048808571 ps
CPU time 11.11 seconds
Started Jun 23 06:05:21 PM PDT 24
Finished Jun 23 06:05:33 PM PDT 24
Peak memory 216480 kb
Host smart-f014abe1-2361-4d41-a4b5-000007cc3785
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622486666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1622486666
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3142091796
Short name T30
Test name
Test status
Simulation time 579625930 ps
CPU time 1.3 seconds
Started Jun 23 06:05:24 PM PDT 24
Finished Jun 23 06:05:26 PM PDT 24
Peak memory 197152 kb
Host smart-a1f1f527-e1b8-4945-ab98-2d31160b00a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142091796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3142091796
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2091820359
Short name T232
Test name
Test status
Simulation time 33533367550 ps
CPU time 45.92 seconds
Started Jun 23 06:05:42 PM PDT 24
Finished Jun 23 06:06:28 PM PDT 24
Peak memory 192404 kb
Host smart-c67219c1-d5ec-4080-b90f-f71191828e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091820359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2091820359
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2249805894
Short name T252
Test name
Test status
Simulation time 613564464 ps
CPU time 0.81 seconds
Started Jun 23 06:05:41 PM PDT 24
Finished Jun 23 06:05:43 PM PDT 24
Peak memory 192344 kb
Host smart-2b735c6e-ff02-4dae-92c4-2d26b988cfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249805894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2249805894
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2150272544
Short name T177
Test name
Test status
Simulation time 482351740 ps
CPU time 0.91 seconds
Started Jun 23 06:05:45 PM PDT 24
Finished Jun 23 06:05:46 PM PDT 24
Peak memory 197188 kb
Host smart-d705a530-c190-401d-ae16-83ea8f8f159e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150272544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2150272544
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1210624898
Short name T219
Test name
Test status
Simulation time 27505376822 ps
CPU time 15.49 seconds
Started Jun 23 06:05:45 PM PDT 24
Finished Jun 23 06:06:00 PM PDT 24
Peak memory 197436 kb
Host smart-cca1f1b5-3b5a-4b27-8c69-6ec824c99545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210624898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1210624898
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2420687689
Short name T264
Test name
Test status
Simulation time 499871598 ps
CPU time 0.78 seconds
Started Jun 23 06:05:40 PM PDT 24
Finished Jun 23 06:05:41 PM PDT 24
Peak memory 192288 kb
Host smart-da1ccbc9-6871-4a21-bd20-5290a891d74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420687689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2420687689
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2029943931
Short name T247
Test name
Test status
Simulation time 25133721580 ps
CPU time 18.78 seconds
Started Jun 23 06:05:40 PM PDT 24
Finished Jun 23 06:05:59 PM PDT 24
Peak memory 192460 kb
Host smart-a00617b7-7436-4bcf-84b9-e77c8d9dfc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029943931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2029943931
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2897329225
Short name T199
Test name
Test status
Simulation time 417032837 ps
CPU time 1.23 seconds
Started Jun 23 06:05:44 PM PDT 24
Finished Jun 23 06:05:45 PM PDT 24
Peak memory 192344 kb
Host smart-ed1e2121-d289-489c-b366-f04f446f4057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897329225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2897329225
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.399581041
Short name T204
Test name
Test status
Simulation time 4641902077 ps
CPU time 6.47 seconds
Started Jun 23 06:05:41 PM PDT 24
Finished Jun 23 06:05:48 PM PDT 24
Peak memory 192464 kb
Host smart-c54aaed5-5547-4707-87e2-b486a6f30b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399581041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.399581041
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.788982323
Short name T231
Test name
Test status
Simulation time 476635477 ps
CPU time 0.76 seconds
Started Jun 23 06:05:43 PM PDT 24
Finished Jun 23 06:05:44 PM PDT 24
Peak memory 192336 kb
Host smart-aa6bc22c-51e3-4c0f-b047-fd7c026f5f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788982323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.788982323
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2534104260
Short name T76
Test name
Test status
Simulation time 6021125990 ps
CPU time 8.16 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:05:56 PM PDT 24
Peak memory 197428 kb
Host smart-df7cb7e1-d2bd-47ed-94a3-19eafe3d627a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534104260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2534104260
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3648673603
Short name T234
Test name
Test status
Simulation time 429541956 ps
CPU time 0.64 seconds
Started Jun 23 06:05:43 PM PDT 24
Finished Jun 23 06:05:44 PM PDT 24
Peak memory 197160 kb
Host smart-6405e1eb-485e-40f2-b19b-003ac37be775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648673603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3648673603
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1870737643
Short name T222
Test name
Test status
Simulation time 6360161883 ps
CPU time 10.94 seconds
Started Jun 23 06:05:44 PM PDT 24
Finished Jun 23 06:05:55 PM PDT 24
Peak memory 192460 kb
Host smart-5b9a96d4-3441-4bcd-a58b-883089776f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870737643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1870737643
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2374387229
Short name T208
Test name
Test status
Simulation time 373347225 ps
CPU time 1.03 seconds
Started Jun 23 06:05:45 PM PDT 24
Finished Jun 23 06:05:46 PM PDT 24
Peak memory 192356 kb
Host smart-d2d45367-41ef-4021-b922-d7b6134d0022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374387229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2374387229
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2707136033
Short name T258
Test name
Test status
Simulation time 21911171380 ps
CPU time 17.3 seconds
Started Jun 23 06:05:41 PM PDT 24
Finished Jun 23 06:05:59 PM PDT 24
Peak memory 192452 kb
Host smart-bd8ae629-df30-4c80-ab89-10aae22e1e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707136033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2707136033
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1592431040
Short name T212
Test name
Test status
Simulation time 431559357 ps
CPU time 0.72 seconds
Started Jun 23 06:05:44 PM PDT 24
Finished Jun 23 06:05:45 PM PDT 24
Peak memory 192364 kb
Host smart-c22b59b1-73d7-4be0-8cc4-b3d945a4b2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592431040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1592431040
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3007657940
Short name T240
Test name
Test status
Simulation time 48638224168 ps
CPU time 17.64 seconds
Started Jun 23 06:05:49 PM PDT 24
Finished Jun 23 06:06:07 PM PDT 24
Peak memory 192464 kb
Host smart-d0d2f9f1-9750-470b-9054-7325ba3a8d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007657940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3007657940
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2105551337
Short name T237
Test name
Test status
Simulation time 457952923 ps
CPU time 0.94 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:05:49 PM PDT 24
Peak memory 192364 kb
Host smart-6b1588e7-d0c5-4044-8a0d-68fca794cf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105551337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2105551337
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3331539086
Short name T180
Test name
Test status
Simulation time 210604750335 ps
CPU time 58.58 seconds
Started Jun 23 06:05:48 PM PDT 24
Finished Jun 23 06:06:47 PM PDT 24
Peak memory 198784 kb
Host smart-ac16f33b-19be-4a84-91ad-0019da1daf46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331539086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3331539086
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3517744667
Short name T257
Test name
Test status
Simulation time 29389061601 ps
CPU time 16.54 seconds
Started Jun 23 06:05:51 PM PDT 24
Finished Jun 23 06:06:08 PM PDT 24
Peak memory 192460 kb
Host smart-d7a8f807-d96b-4eff-96b5-ab6b2af75c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517744667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3517744667
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.961387760
Short name T1
Test name
Test status
Simulation time 459011992 ps
CPU time 0.74 seconds
Started Jun 23 06:05:48 PM PDT 24
Finished Jun 23 06:05:49 PM PDT 24
Peak memory 192316 kb
Host smart-a02bd819-c41a-4a05-8fe7-328eb819583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961387760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.961387760
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3272028013
Short name T207
Test name
Test status
Simulation time 37238967485 ps
CPU time 53.22 seconds
Started Jun 23 06:05:56 PM PDT 24
Finished Jun 23 06:06:50 PM PDT 24
Peak memory 192404 kb
Host smart-d170ae06-4c0c-4fad-9d26-a038397d98e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272028013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3272028013
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.489934360
Short name T271
Test name
Test status
Simulation time 535917291 ps
CPU time 1.41 seconds
Started Jun 23 06:05:56 PM PDT 24
Finished Jun 23 06:05:58 PM PDT 24
Peak memory 192288 kb
Host smart-00bff87f-f496-4f88-9475-36e6ee70ef37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489934360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.489934360
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1478191623
Short name T242
Test name
Test status
Simulation time 31635186651 ps
CPU time 24.92 seconds
Started Jun 23 06:05:34 PM PDT 24
Finished Jun 23 06:06:00 PM PDT 24
Peak memory 192464 kb
Host smart-5d82674f-e61e-4a5f-9dfc-fae80023b3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478191623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1478191623
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3369736688
Short name T18
Test name
Test status
Simulation time 7816144724 ps
CPU time 3.78 seconds
Started Jun 23 06:05:19 PM PDT 24
Finished Jun 23 06:05:23 PM PDT 24
Peak memory 216432 kb
Host smart-0cf4ade0-c9ec-4e6c-9b49-681ec271e069
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369736688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3369736688
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.392799546
Short name T203
Test name
Test status
Simulation time 389390179 ps
CPU time 0.91 seconds
Started Jun 23 06:05:25 PM PDT 24
Finished Jun 23 06:05:26 PM PDT 24
Peak memory 197300 kb
Host smart-6825b022-185f-4ca6-9ffd-a67e4894d518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392799546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.392799546
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3890897494
Short name T216
Test name
Test status
Simulation time 56954198814 ps
CPU time 85.93 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:07:12 PM PDT 24
Peak memory 192628 kb
Host smart-d6eec498-4534-4b20-8afd-fe9a524bba79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890897494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3890897494
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3568625571
Short name T21
Test name
Test status
Simulation time 575695018 ps
CPU time 1.47 seconds
Started Jun 23 06:05:49 PM PDT 24
Finished Jun 23 06:05:51 PM PDT 24
Peak memory 197128 kb
Host smart-0bed5b89-2723-423c-ac70-9309837c9d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568625571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3568625571
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2204428882
Short name T192
Test name
Test status
Simulation time 12502613486 ps
CPU time 18.24 seconds
Started Jun 23 06:05:46 PM PDT 24
Finished Jun 23 06:06:05 PM PDT 24
Peak memory 192420 kb
Host smart-a8e2fb03-bdff-427a-acf8-c7d9c4ea7c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204428882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2204428882
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.4105004285
Short name T230
Test name
Test status
Simulation time 566823677 ps
CPU time 0.72 seconds
Started Jun 23 06:05:56 PM PDT 24
Finished Jun 23 06:05:57 PM PDT 24
Peak memory 196928 kb
Host smart-e2fe6a59-971b-4dcb-8a27-8e93deb02644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105004285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.4105004285
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2174838427
Short name T263
Test name
Test status
Simulation time 24077762543 ps
CPU time 34.54 seconds
Started Jun 23 06:05:56 PM PDT 24
Finished Jun 23 06:06:31 PM PDT 24
Peak memory 192404 kb
Host smart-a1d47ca4-7c4c-4ed7-9dca-eb4aa826eacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174838427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2174838427
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.134055054
Short name T248
Test name
Test status
Simulation time 384324507 ps
CPU time 1.11 seconds
Started Jun 23 06:05:47 PM PDT 24
Finished Jun 23 06:05:49 PM PDT 24
Peak memory 192344 kb
Host smart-9d87f22b-70a5-4693-8140-380d70e86711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134055054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.134055054
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3092391237
Short name T11
Test name
Test status
Simulation time 46069247707 ps
CPU time 68.32 seconds
Started Jun 23 06:05:50 PM PDT 24
Finished Jun 23 06:06:59 PM PDT 24
Peak memory 192460 kb
Host smart-9f232fd0-1b68-4a07-a772-2da983bb5601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092391237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3092391237
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.609494514
Short name T210
Test name
Test status
Simulation time 582967781 ps
CPU time 0.77 seconds
Started Jun 23 06:05:49 PM PDT 24
Finished Jun 23 06:05:50 PM PDT 24
Peak memory 192344 kb
Host smart-f13d3226-4b5b-4271-90fc-e7d7db7b76e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609494514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.609494514
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1842191307
Short name T235
Test name
Test status
Simulation time 4538200272 ps
CPU time 5.18 seconds
Started Jun 23 06:05:52 PM PDT 24
Finished Jun 23 06:05:57 PM PDT 24
Peak memory 192400 kb
Host smart-702e53fa-7640-436a-8465-7389dcb35054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842191307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1842191307
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1684552276
Short name T236
Test name
Test status
Simulation time 565735913 ps
CPU time 1 seconds
Started Jun 23 06:05:55 PM PDT 24
Finished Jun 23 06:05:57 PM PDT 24
Peak memory 197172 kb
Host smart-36a00c23-4dc8-4e42-b076-3e9a199daf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684552276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1684552276
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1743468907
Short name T44
Test name
Test status
Simulation time 11775928060 ps
CPU time 4.14 seconds
Started Jun 23 06:05:57 PM PDT 24
Finished Jun 23 06:06:01 PM PDT 24
Peak memory 197388 kb
Host smart-b0e0cd1b-1bac-48e9-b540-295e37af74a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743468907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1743468907
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.4261626720
Short name T214
Test name
Test status
Simulation time 532639407 ps
CPU time 0.68 seconds
Started Jun 23 06:06:05 PM PDT 24
Finished Jun 23 06:06:06 PM PDT 24
Peak memory 197044 kb
Host smart-cee0ee69-5ff3-4aa3-b1cc-7b761a70939c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261626720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.4261626720
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2088090491
Short name T246
Test name
Test status
Simulation time 58367863179 ps
CPU time 18.7 seconds
Started Jun 23 06:05:53 PM PDT 24
Finished Jun 23 06:06:12 PM PDT 24
Peak memory 192404 kb
Host smart-33b5709c-54fb-4ad4-89b4-d9e0fe45a926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088090491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2088090491
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2756193794
Short name T244
Test name
Test status
Simulation time 638872349 ps
CPU time 0.74 seconds
Started Jun 23 06:06:02 PM PDT 24
Finished Jun 23 06:06:03 PM PDT 24
Peak memory 192364 kb
Host smart-f9cac11c-0342-4a97-9eb8-13754e662873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756193794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2756193794
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3584897479
Short name T278
Test name
Test status
Simulation time 39456916250 ps
CPU time 56.47 seconds
Started Jun 23 06:05:52 PM PDT 24
Finished Jun 23 06:06:49 PM PDT 24
Peak memory 192484 kb
Host smart-8d4e87af-eeec-4a89-9597-c852ba825b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584897479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3584897479
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.82607434
Short name T277
Test name
Test status
Simulation time 575124192 ps
CPU time 1.46 seconds
Started Jun 23 06:05:53 PM PDT 24
Finished Jun 23 06:05:55 PM PDT 24
Peak memory 192336 kb
Host smart-e8ecfd2c-5805-478c-a782-ae16ca3bb385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82607434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.82607434
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.243132560
Short name T250
Test name
Test status
Simulation time 1599350746 ps
CPU time 1.77 seconds
Started Jun 23 06:05:59 PM PDT 24
Finished Jun 23 06:06:01 PM PDT 24
Peak memory 192320 kb
Host smart-30aa4dfb-9e66-4566-8e26-6e283d79092a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243132560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.243132560
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1323312170
Short name T261
Test name
Test status
Simulation time 484786420 ps
CPU time 1.06 seconds
Started Jun 23 06:05:54 PM PDT 24
Finished Jun 23 06:05:56 PM PDT 24
Peak memory 192344 kb
Host smart-4a73523b-f9d8-48ae-851a-11eccd4cf1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323312170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1323312170
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2289563615
Short name T272
Test name
Test status
Simulation time 55223623522 ps
CPU time 88.72 seconds
Started Jun 23 06:06:05 PM PDT 24
Finished Jun 23 06:07:34 PM PDT 24
Peak memory 192352 kb
Host smart-1da457be-025c-4d32-9684-9d4b90a62da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289563615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2289563615
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2995581588
Short name T220
Test name
Test status
Simulation time 361330666 ps
CPU time 0.69 seconds
Started Jun 23 06:05:51 PM PDT 24
Finished Jun 23 06:05:52 PM PDT 24
Peak memory 192256 kb
Host smart-aa804c43-d608-4b5f-b8ce-803c3e1ac30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995581588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2995581588
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1760886579
Short name T215
Test name
Test status
Simulation time 29649726213 ps
CPU time 37.95 seconds
Started Jun 23 06:05:21 PM PDT 24
Finished Jun 23 06:06:00 PM PDT 24
Peak memory 192444 kb
Host smart-4e3edb98-c8ca-42ac-87cf-2712f44c49fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760886579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1760886579
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2092991796
Short name T254
Test name
Test status
Simulation time 418968523 ps
CPU time 1.16 seconds
Started Jun 23 06:05:25 PM PDT 24
Finished Jun 23 06:05:27 PM PDT 24
Peak memory 192344 kb
Host smart-72deddd9-ecd0-43ef-b88b-1303a03105a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092991796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2092991796
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1273390446
Short name T238
Test name
Test status
Simulation time 15866066798 ps
CPU time 5.84 seconds
Started Jun 23 06:05:23 PM PDT 24
Finished Jun 23 06:05:30 PM PDT 24
Peak memory 192404 kb
Host smart-b00c7d14-3cad-4cfe-9f5b-0e5f67a24860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273390446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1273390446
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.4284491019
Short name T260
Test name
Test status
Simulation time 477918332 ps
CPU time 1.27 seconds
Started Jun 23 06:05:27 PM PDT 24
Finished Jun 23 06:05:29 PM PDT 24
Peak memory 197136 kb
Host smart-d5ec0947-463a-4d84-850f-3b9fa632b8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284491019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.4284491019
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.97874352
Short name T267
Test name
Test status
Simulation time 35169990656 ps
CPU time 13.05 seconds
Started Jun 23 06:05:28 PM PDT 24
Finished Jun 23 06:05:41 PM PDT 24
Peak memory 192472 kb
Host smart-96df84ba-020b-4237-9485-0a9d3b39785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97874352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.97874352
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3271295351
Short name T206
Test name
Test status
Simulation time 386108799 ps
CPU time 1.19 seconds
Started Jun 23 06:05:25 PM PDT 24
Finished Jun 23 06:05:27 PM PDT 24
Peak memory 197292 kb
Host smart-be6906f3-7833-4d53-8863-54a374f7bf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271295351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3271295351
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2859451927
Short name T275
Test name
Test status
Simulation time 41209701540 ps
CPU time 16.39 seconds
Started Jun 23 06:05:22 PM PDT 24
Finished Jun 23 06:05:39 PM PDT 24
Peak memory 192432 kb
Host smart-edea70fd-f5dc-4b96-84d4-d34ac24cf545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859451927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2859451927
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2838368486
Short name T269
Test name
Test status
Simulation time 612625789 ps
CPU time 0.67 seconds
Started Jun 23 06:05:36 PM PDT 24
Finished Jun 23 06:05:37 PM PDT 24
Peak memory 197128 kb
Host smart-cdc50353-6cc0-4c91-9cb0-f13c1d808a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838368486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2838368486
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1453946098
Short name T266
Test name
Test status
Simulation time 25528029842 ps
CPU time 12.33 seconds
Started Jun 23 06:05:29 PM PDT 24
Finished Jun 23 06:05:42 PM PDT 24
Peak memory 192460 kb
Host smart-af6ea347-5a23-4637-b7dd-76371c13c295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453946098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1453946098
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2498010130
Short name T274
Test name
Test status
Simulation time 354422347 ps
CPU time 1.05 seconds
Started Jun 23 06:05:27 PM PDT 24
Finished Jun 23 06:05:28 PM PDT 24
Peak memory 197144 kb
Host smart-350847f7-0da8-4c6e-98eb-1ce9c199dfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498010130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2498010130
Directory /workspace/9.aon_timer_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%