Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	30249	1		T1	11		T2	207		T3	11
bark[1]	814	1		T65	14		T102	143		T91	23
bark[2]	424	1		T9	21		T36	21		T62	26
bark[3]	815	1		T4	218		T11	14		T32	150
bark[4]	1136	1		T12	62		T22	108		T182	14
bark[5]	660	1		T32	31		T184	14		T62	199
bark[6]	730	1		T11	21		T23	14		T36	26
bark[7]	715	1		T33	26		T37	14		T44	21
bark[8]	1435	1		T9	224		T13	62		T65	263
bark[9]	414	1		T17	21		T115	14		T114	309
bark[10]	319	1		T18	42		T125	14		T117	21
bark[11]	517	1		T17	21		T32	7		T34	26
bark[12]	397	1		T117	14		T36	173		T113	58
bark[13]	254	1		T17	21		T122	14		T126	14
bark[14]	962	1		T2	21		T18	21		T117	31
bark[15]	361	1		T34	21		T36	125		T154	63
bark[16]	698	1		T9	26		T34	21		T35	49
bark[17]	362	1		T156	56		T36	21		T131	21
bark[18]	486	1		T13	47		T137	14		T33	126
bark[19]	1196	1		T4	120		T18	42		T102	21
bark[20]	540	1		T12	232		T33	21		T94	21
bark[21]	594	1		T2	76		T9	31		T11	26
bark[22]	382	1		T12	171		T17	30		T88	21
bark[23]	583	1		T147	14		T183	14		T117	77
bark[24]	1145	1		T17	26		T166	14		T65	65
bark[25]	392	1		T12	146		T26	14		T156	63
bark[26]	525	1		T18	14		T117	21		T62	26
bark[27]	163	1		T18	21		T102	21		T110	14
bark[28]	397	1		T13	21		T166	21		T62	79
bark[29]	328	1		T24	14		T166	21		T154	59
bark[30]	781	1		T2	21		T11	21		T39	14
bark[31]	197	1		T180	26		T69	40		T154	21
bark_0	4826	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	29261	1		T1	10		T2	206		T3	10
bite[1]	588	1		T11	26		T33	21		T156	63
bite[2]	708	1		T18	42		T180	26		T94	21
bite[3]	581	1		T65	26		T173	114		T108	55
bite[4]	220	1		T11	13		T102	26		T91	30
bite[5]	453	1		T156	21		T34	26		T180	21
bite[6]	599	1		T32	149		T117	87		T39	13
bite[7]	1119	1		T17	21		T18	13		T166	21
bite[8]	536	1		T36	236		T140	13		T115	13
bite[9]	438	1		T4	217		T183	13		T117	13
bite[10]	1457	1		T17	21		T18	21		T34	180
bite[11]	770	1		T137	13		T18	21		T117	21
bite[12]	171	1		T122	13		T65	13		T92	21
bite[13]	303	1		T2	21		T18	21		T125	13
bite[14]	494	1		T13	46		T18	21		T36	76
bite[15]	434	1		T34	21		T62	78		T94	21
bite[16]	441	1		T9	26		T13	61		T65	21
bite[17]	706	1		T62	212		T154	30		T131	21
bite[18]	747	1		T182	13		T62	188		T102	21
bite[19]	828	1		T9	52		T12	62		T22	107
bite[20]	267	1		T17	21		T63	13		T66	65
bite[21]	526	1		T32	31		T166	21		T66	39
bite[22]	269	1		T24	13		T62	30		T132	39
bite[23]	1364	1		T12	21		T13	21		T18	21
bite[24]	861	1		T2	76		T4	119		T26	13
bite[25]	950	1		T2	21		T11	21		T33	25
bite[26]	640	1		T12	145		T184	13		T36	21
bite[27]	598	1		T35	48		T36	25		T94	21
bite[28]	476	1		T9	223		T12	149		T91	22
bite[29]	282	1		T156	55		T36	67		T154	21
bite[30]	685	1		T34	21		T108	21		T101	31
bite[31]	581	1		T12	231		T34	21		T44	21
bite_0	5444	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	53797	1		T1	18		T2	332		T3	18

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	775	1		T12	56		T13	78		T17	19
prescale[1]	1003	1		T7	9		T12	49		T13	24
prescale[2]	712	1		T13	18		T17	9		T36	35
prescale[3]	917	1		T12	180		T22	58		T34	45
prescale[4]	627	1		T9	19		T13	2		T36	74
prescale[5]	473	1		T23	178		T34	40		T199	9
prescale[6]	1045	1		T4	37		T12	54		T200	9
prescale[7]	1133	1		T9	100		T13	28		T32	19
prescale[8]	1051	1		T12	79		T13	19		T32	2
prescale[9]	811	1		T4	19		T9	19		T13	150
prescale[10]	868	1		T2	23		T9	37		T12	137
prescale[11]	468	1		T9	27		T12	39		T23	2
prescale[12]	818	1		T11	28		T13	196		T22	100
prescale[13]	619	1		T12	55		T13	19		T17	68
prescale[14]	503	1		T4	20		T33	19		T34	37
prescale[15]	975	1		T2	46		T4	55		T22	19
prescale[16]	691	1		T13	171		T22	58		T33	66
prescale[17]	546	1		T9	109		T12	43		T27	9
prescale[18]	1676	1		T12	128		T22	19		T32	150
prescale[19]	711	1		T4	20		T12	40		T32	60
prescale[20]	1191	1		T2	9		T180	35		T35	23
prescale[21]	819	1		T9	146		T12	19		T22	20
prescale[22]	685	1		T13	114		T32	86		T117	23
prescale[23]	1008	1		T2	76		T21	9		T201	9
prescale[24]	856	1		T5	9		T9	2		T12	28
prescale[25]	469	1		T4	2		T12	2		T33	45
prescale[26]	860	1		T2	37		T12	34		T13	2
prescale[27]	882	1		T4	40		T9	2		T11	46
prescale[28]	610	1		T13	4		T202	9		T157	19
prescale[29]	631	1		T12	2		T32	23		T18	24
prescale[30]	875	1		T6	9		T9	2		T12	58
prescale[31]	915	1		T4	75		T13	101		T32	2
prescale_0	27574	1		T1	18		T2	141		T3	18

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40810	1		T1	9		T2	155		T3	9
auto[1]	12987	1		T1	9		T2	177		T3	9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	53797	1		T1	18		T2	332		T3	18

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	31002	1		T1	13		T2	225		T3	13
wkup[1]	265	1		T9	30		T12	35		T34	21
wkup[2]	303	1		T12	21		T34	21		T183	15
wkup[3]	244	1		T22	21		T62	21		T150	21
wkup[4]	336	1		T9	21		T12	26		T18	21
wkup[5]	273	1		T33	30		T36	21		T62	15
wkup[6]	222	1		T23	21		T34	49		T65	21
wkup[7]	292	1		T4	21		T13	21		T23	21
wkup[8]	318	1		T12	21		T156	21		T34	21
wkup[9]	322	1		T2	21		T166	21		T36	21
wkup[10]	533	1		T4	21		T9	21		T11	26
wkup[11]	464	1		T13	42		T34	21		T184	15
wkup[12]	240	1		T12	21		T23	21		T17	42
wkup[13]	156	1		T13	21		T33	30		T117	21
wkup[14]	249	1		T23	21		T147	15		T34	26
wkup[15]	353	1		T9	26		T23	21		T34	21
wkup[16]	215	1		T37	15		T102	21		T163	35
wkup[17]	507	1		T23	15		T34	26		T180	21
wkup[18]	221	1		T65	26		T102	30		T162	21
wkup[19]	179	1		T4	21		T9	21		T18	21
wkup[20]	337	1		T9	70		T12	21		T32	8
wkup[21]	366	1		T13	21		T33	42		T34	15
wkup[22]	366	1		T9	21		T125	15		T166	21
wkup[23]	281	1		T13	42		T117	21		T36	56
wkup[24]	353	1		T12	21		T23	15		T44	21
wkup[25]	165	1		T11	21		T18	21		T44	30
wkup[26]	307	1		T12	15		T13	21		T34	21
wkup[27]	279	1		T9	21		T32	8		T33	21
wkup[28]	335	1		T22	21		T33	42		T166	39
wkup[29]	312	1		T33	47		T34	42		T36	21
wkup[30]	240	1		T166	21		T36	42		T62	58
wkup[31]	209	1		T12	42		T22	21		T17	26
wkup[32]	269	1		T13	21		T18	15		T33	21
wkup[33]	233	1		T36	21		T62	26		T81	8
wkup[34]	281	1		T4	30		T13	24		T32	21
wkup[35]	269	1		T11	21		T22	21		T156	21
wkup[36]	335	1		T156	21		T102	51		T131	30
wkup[37]	353	1		T12	21		T180	15		T44	47
wkup[38]	341	1		T12	21		T22	21		T157	26
wkup[39]	311	1		T23	21		T157	42		T41	15
wkup[40]	361	1		T4	21		T9	21		T22	30
wkup[41]	580	1		T9	21		T17	21		T33	26
wkup[42]	213	1		T13	21		T34	21		T44	21
wkup[43]	220	1		T13	21		T22	21		T34	47
wkup[44]	312	1		T12	83		T23	21		T32	31
wkup[45]	392	1		T4	21		T18	42		T34	15
wkup[46]	260	1		T13	21		T36	60		T102	15
wkup[47]	232	1		T22	30		T33	15		T34	21
wkup[48]	238	1		T4	21		T9	21		T182	15
wkup[49]	250	1		T4	21		T13	26		T44	21
wkup[50]	353	1		T22	21		T32	21		T34	26
wkup[51]	323	1		T2	39		T156	21		T39	15
wkup[52]	363	1		T9	73		T12	35		T44	31
wkup[53]	307	1		T13	21		T17	30		T34	21
wkup[54]	281	1		T2	21		T9	31		T32	21
wkup[55]	310	1		T4	21		T13	21		T166	15
wkup[56]	250	1		T102	52		T159	21		T148	36
wkup[57]	299	1		T2	21		T9	21		T11	15
wkup[58]	253	1		T13	30		T32	21		T66	26
wkup[59]	446	1		T12	21		T13	21		T22	26
wkup[60]	317	1		T32	41		T65	21		T165	21
wkup[61]	209	1		T137	15		T67	15		T87	21
wkup[62]	278	1		T9	63		T12	21		T13	21
wkup[63]	276	1		T4	21		T13	21		T32	21
wkup_0	3838	1		T1	5		T2	5		T3	5