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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.37 99.33 93.67 100.00 98.40 99.51 51.29


Total test records in report: 425
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T284 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2559606564 Jun 24 05:50:39 PM PDT 24 Jun 24 05:50:42 PM PDT 24 430925551 ps
T285 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1701704345 Jun 24 05:51:07 PM PDT 24 Jun 24 05:51:10 PM PDT 24 503881312 ps
T31 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2987911387 Jun 24 05:50:47 PM PDT 24 Jun 24 05:50:50 PM PDT 24 622073812 ps
T286 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.652684869 Jun 24 05:50:37 PM PDT 24 Jun 24 05:50:41 PM PDT 24 545782497 ps
T28 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1842598588 Jun 24 05:50:47 PM PDT 24 Jun 24 05:50:50 PM PDT 24 8681239013 ps
T29 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2391858420 Jun 24 05:50:36 PM PDT 24 Jun 24 05:50:44 PM PDT 24 4554606108 ps
T287 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2342438343 Jun 24 05:50:08 PM PDT 24 Jun 24 05:50:09 PM PDT 24 520816880 ps
T288 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1102852511 Jun 24 05:50:29 PM PDT 24 Jun 24 05:50:32 PM PDT 24 514865506 ps
T30 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1422192976 Jun 24 05:50:44 PM PDT 24 Jun 24 05:50:59 PM PDT 24 8129254927 ps
T289 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1365658042 Jun 24 05:50:09 PM PDT 24 Jun 24 05:50:12 PM PDT 24 449580511 ps
T71 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3861581107 Jun 24 05:50:47 PM PDT 24 Jun 24 05:50:54 PM PDT 24 2072773810 ps
T290 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3413330118 Jun 24 05:50:44 PM PDT 24 Jun 24 05:50:47 PM PDT 24 431347591 ps
T49 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2020906197 Jun 24 05:50:26 PM PDT 24 Jun 24 05:50:28 PM PDT 24 1087855840 ps
T72 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.322160885 Jun 24 05:50:46 PM PDT 24 Jun 24 05:50:48 PM PDT 24 851363237 ps
T291 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3040140240 Jun 24 05:51:05 PM PDT 24 Jun 24 05:51:07 PM PDT 24 483762630 ps
T292 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3013967255 Jun 24 05:51:15 PM PDT 24 Jun 24 05:51:18 PM PDT 24 462221600 ps
T293 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2319795926 Jun 24 05:50:36 PM PDT 24 Jun 24 05:50:38 PM PDT 24 356788627 ps
T73 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1293735937 Jun 24 05:50:27 PM PDT 24 Jun 24 05:50:29 PM PDT 24 1411389606 ps
T294 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.230592576 Jun 24 05:50:53 PM PDT 24 Jun 24 05:50:55 PM PDT 24 290157805 ps
T50 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1413999181 Jun 24 05:50:37 PM PDT 24 Jun 24 05:50:39 PM PDT 24 357269760 ps
T295 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3061094235 Jun 24 05:51:05 PM PDT 24 Jun 24 05:51:07 PM PDT 24 494465726 ps
T296 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1934908914 Jun 24 05:50:27 PM PDT 24 Jun 24 05:50:30 PM PDT 24 348638104 ps
T192 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3338738090 Jun 24 05:50:36 PM PDT 24 Jun 24 05:50:41 PM PDT 24 8722068170 ps
T297 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3481219576 Jun 24 05:50:27 PM PDT 24 Jun 24 05:50:28 PM PDT 24 409160147 ps
T51 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3102519108 Jun 24 05:50:27 PM PDT 24 Jun 24 05:50:28 PM PDT 24 1333325387 ps
T52 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2842270583 Jun 24 05:50:28 PM PDT 24 Jun 24 05:50:42 PM PDT 24 10425690789 ps
T193 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.422848184 Jun 24 05:50:38 PM PDT 24 Jun 24 05:50:41 PM PDT 24 4669870913 ps
T298 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.851812305 Jun 24 05:51:07 PM PDT 24 Jun 24 05:51:10 PM PDT 24 490392498 ps
T299 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2348277643 Jun 24 05:50:54 PM PDT 24 Jun 24 05:50:55 PM PDT 24 347653694 ps
T300 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3893056082 Jun 24 05:51:05 PM PDT 24 Jun 24 05:51:07 PM PDT 24 517717353 ps
T301 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2966774713 Jun 24 05:51:06 PM PDT 24 Jun 24 05:51:08 PM PDT 24 437355776 ps
T74 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2453321107 Jun 24 05:50:55 PM PDT 24 Jun 24 05:50:56 PM PDT 24 476897721 ps
T302 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.317753163 Jun 24 05:50:16 PM PDT 24 Jun 24 05:50:19 PM PDT 24 327070601 ps
T303 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1919799757 Jun 24 05:50:17 PM PDT 24 Jun 24 05:50:21 PM PDT 24 4422929852 ps
T304 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2025834887 Jun 24 05:50:46 PM PDT 24 Jun 24 05:50:49 PM PDT 24 515721298 ps
T305 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.312705068 Jun 24 05:50:28 PM PDT 24 Jun 24 05:50:32 PM PDT 24 7533113972 ps
T306 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3200584431 Jun 24 05:51:04 PM PDT 24 Jun 24 05:51:07 PM PDT 24 509239783 ps
T307 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3130361745 Jun 24 05:50:56 PM PDT 24 Jun 24 05:50:58 PM PDT 24 446198372 ps
T308 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3155878234 Jun 24 05:51:06 PM PDT 24 Jun 24 05:51:10 PM PDT 24 719024253 ps
T309 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1855352221 Jun 24 05:50:27 PM PDT 24 Jun 24 05:50:29 PM PDT 24 504883936 ps
T53 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.827791713 Jun 24 05:50:44 PM PDT 24 Jun 24 05:50:46 PM PDT 24 532912139 ps
T75 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2191984514 Jun 24 05:50:46 PM PDT 24 Jun 24 05:50:49 PM PDT 24 1831306138 ps
T197 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4172977689 Jun 24 05:50:44 PM PDT 24 Jun 24 05:50:51 PM PDT 24 7761278083 ps
T310 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1970690634 Jun 24 05:50:17 PM PDT 24 Jun 24 05:50:20 PM PDT 24 530801735 ps
T311 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3909544428 Jun 24 05:50:31 PM PDT 24 Jun 24 05:50:33 PM PDT 24 427506307 ps
T312 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.151121768 Jun 24 05:51:14 PM PDT 24 Jun 24 05:51:23 PM PDT 24 4286575216 ps
T313 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2797800002 Jun 24 05:50:38 PM PDT 24 Jun 24 05:50:40 PM PDT 24 515848523 ps
T314 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2591557894 Jun 24 05:50:07 PM PDT 24 Jun 24 05:50:10 PM PDT 24 515008791 ps
T315 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1716398335 Jun 24 05:50:32 PM PDT 24 Jun 24 05:50:35 PM PDT 24 394946641 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2904178228 Jun 24 05:50:17 PM PDT 24 Jun 24 05:50:19 PM PDT 24 641071326 ps
T316 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.616046210 Jun 24 05:50:48 PM PDT 24 Jun 24 05:50:50 PM PDT 24 389291628 ps
T317 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.56743678 Jun 24 05:50:29 PM PDT 24 Jun 24 05:50:31 PM PDT 24 467671224 ps
T318 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3380308286 Jun 24 05:51:15 PM PDT 24 Jun 24 05:51:18 PM PDT 24 527572036 ps
T319 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.910992794 Jun 24 05:51:06 PM PDT 24 Jun 24 05:51:08 PM PDT 24 455470871 ps
T76 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.393352466 Jun 24 05:50:47 PM PDT 24 Jun 24 05:50:49 PM PDT 24 1320465953 ps
T320 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2349843160 Jun 24 05:51:06 PM PDT 24 Jun 24 05:51:08 PM PDT 24 337418440 ps
T321 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.615376376 Jun 24 05:50:39 PM PDT 24 Jun 24 05:50:41 PM PDT 24 380164301 ps
T322 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3390136853 Jun 24 05:51:07 PM PDT 24 Jun 24 05:51:10 PM PDT 24 352051253 ps
T323 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.80267897 Jun 24 05:50:57 PM PDT 24 Jun 24 05:50:59 PM PDT 24 298183538 ps
T324 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4100955991 Jun 24 05:51:07 PM PDT 24 Jun 24 05:51:10 PM PDT 24 354041809 ps
T58 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3767251186 Jun 24 05:50:37 PM PDT 24 Jun 24 05:50:40 PM PDT 24 317459865 ps
T325 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2151363600 Jun 24 05:51:06 PM PDT 24 Jun 24 05:51:09 PM PDT 24 393272541 ps
T77 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.699735575 Jun 24 05:50:54 PM PDT 24 Jun 24 05:50:56 PM PDT 24 1313779319 ps
T326 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3620373070 Jun 24 05:50:16 PM PDT 24 Jun 24 05:50:17 PM PDT 24 446596041 ps
T327 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.317486999 Jun 24 05:50:38 PM PDT 24 Jun 24 05:50:41 PM PDT 24 343720288 ps
T328 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1505846521 Jun 24 05:50:19 PM PDT 24 Jun 24 05:50:21 PM PDT 24 444737655 ps
T198 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2415935909 Jun 24 05:50:47 PM PDT 24 Jun 24 05:50:53 PM PDT 24 8297100614 ps
T78 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2348219770 Jun 24 05:50:54 PM PDT 24 Jun 24 05:50:59 PM PDT 24 2527483854 ps
T329 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.613350149 Jun 24 05:50:27 PM PDT 24 Jun 24 05:50:32 PM PDT 24 2309759559 ps
T330 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.185351798 Jun 24 05:50:46 PM PDT 24 Jun 24 05:50:47 PM PDT 24 446325979 ps
T331 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3487927526 Jun 24 05:50:35 PM PDT 24 Jun 24 05:50:37 PM PDT 24 366336133 ps
T332 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1802898430 Jun 24 05:50:49 PM PDT 24 Jun 24 05:50:51 PM PDT 24 568852046 ps
T333 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1734800238 Jun 24 05:50:37 PM PDT 24 Jun 24 05:50:42 PM PDT 24 1486887431 ps
T334 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1473161321 Jun 24 05:50:17 PM PDT 24 Jun 24 05:50:21 PM PDT 24 1305410272 ps
T335 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3173496313 Jun 24 05:50:26 PM PDT 24 Jun 24 05:50:28 PM PDT 24 441122225 ps
T336 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1172206557 Jun 24 05:51:14 PM PDT 24 Jun 24 05:51:17 PM PDT 24 284913671 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3604905425 Jun 24 05:50:08 PM PDT 24 Jun 24 05:50:32 PM PDT 24 8924536966 ps
T337 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3379359090 Jun 24 05:51:05 PM PDT 24 Jun 24 05:51:08 PM PDT 24 424236884 ps
T338 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1669987391 Jun 24 05:51:03 PM PDT 24 Jun 24 05:51:05 PM PDT 24 325187575 ps
T339 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2351493099 Jun 24 05:50:39 PM PDT 24 Jun 24 05:50:42 PM PDT 24 773083353 ps
T194 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3734495675 Jun 24 05:50:46 PM PDT 24 Jun 24 05:50:53 PM PDT 24 8915521246 ps
T340 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1405521757 Jun 24 05:51:03 PM PDT 24 Jun 24 05:51:06 PM PDT 24 2670421760 ps
T341 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1269779159 Jun 24 05:51:02 PM PDT 24 Jun 24 05:51:03 PM PDT 24 424147769 ps
T342 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.776395595 Jun 24 05:50:55 PM PDT 24 Jun 24 05:50:58 PM PDT 24 617404170 ps
T343 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2802750810 Jun 24 05:50:30 PM PDT 24 Jun 24 05:50:32 PM PDT 24 315427355 ps
T344 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1723847060 Jun 24 05:51:06 PM PDT 24 Jun 24 05:51:09 PM PDT 24 473793169 ps
T345 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4138735790 Jun 24 05:50:19 PM PDT 24 Jun 24 05:50:21 PM PDT 24 939115071 ps
T346 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2007593647 Jun 24 05:50:46 PM PDT 24 Jun 24 05:50:50 PM PDT 24 512110923 ps
T195 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3760360465 Jun 24 05:50:27 PM PDT 24 Jun 24 05:50:34 PM PDT 24 4299181600 ps
T347 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.854226928 Jun 24 05:50:37 PM PDT 24 Jun 24 05:50:41 PM PDT 24 2034189409 ps
T348 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1451970666 Jun 24 05:50:08 PM PDT 24 Jun 24 05:50:10 PM PDT 24 479923682 ps
T349 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4129177389 Jun 24 05:50:46 PM PDT 24 Jun 24 05:50:49 PM PDT 24 488516188 ps
T350 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2589056544 Jun 24 05:50:37 PM PDT 24 Jun 24 05:50:39 PM PDT 24 945836068 ps
T60 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1221912653 Jun 24 05:50:37 PM PDT 24 Jun 24 05:50:40 PM PDT 24 445872885 ps
T351 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1117928063 Jun 24 05:50:54 PM PDT 24 Jun 24 05:50:56 PM PDT 24 2285581420 ps
T352 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3131799935 Jun 24 05:51:05 PM PDT 24 Jun 24 05:51:07 PM PDT 24 427674648 ps
T353 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.947432543 Jun 24 05:50:45 PM PDT 24 Jun 24 05:50:47 PM PDT 24 611300704 ps
T354 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2706569799 Jun 24 05:51:08 PM PDT 24 Jun 24 05:51:10 PM PDT 24 442292173 ps
T61 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1785612507 Jun 24 05:50:46 PM PDT 24 Jun 24 05:50:49 PM PDT 24 558234958 ps
T355 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4253466148 Jun 24 05:50:05 PM PDT 24 Jun 24 05:50:07 PM PDT 24 284522603 ps
T356 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1129304689 Jun 24 05:50:16 PM PDT 24 Jun 24 05:50:18 PM PDT 24 288742389 ps
T357 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2969975821 Jun 24 05:50:09 PM PDT 24 Jun 24 05:50:18 PM PDT 24 4264149434 ps
T358 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2573420310 Jun 24 05:50:27 PM PDT 24 Jun 24 05:50:29 PM PDT 24 322610431 ps
T359 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4148228191 Jun 24 05:50:30 PM PDT 24 Jun 24 05:50:32 PM PDT 24 502245161 ps
T360 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2865957437 Jun 24 05:50:56 PM PDT 24 Jun 24 05:51:05 PM PDT 24 4183242217 ps
T361 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.36859263 Jun 24 05:50:29 PM PDT 24 Jun 24 05:50:31 PM PDT 24 4373340299 ps
T54 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1077094015 Jun 24 05:50:29 PM PDT 24 Jun 24 05:50:31 PM PDT 24 638086572 ps
T362 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3218642842 Jun 24 05:50:45 PM PDT 24 Jun 24 05:50:48 PM PDT 24 891298852 ps
T363 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2890641397 Jun 24 05:50:36 PM PDT 24 Jun 24 05:50:39 PM PDT 24 578516849 ps
T55 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2855814113 Jun 24 05:50:30 PM PDT 24 Jun 24 05:50:32 PM PDT 24 469397507 ps
T364 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3219255929 Jun 24 05:50:06 PM PDT 24 Jun 24 05:50:08 PM PDT 24 840618839 ps
T70 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.554381468 Jun 24 05:50:26 PM PDT 24 Jun 24 05:50:27 PM PDT 24 391899522 ps
T365 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2160890033 Jun 24 05:50:56 PM PDT 24 Jun 24 05:51:02 PM PDT 24 9062817693 ps
T366 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2542731714 Jun 24 05:51:04 PM PDT 24 Jun 24 05:51:06 PM PDT 24 469546497 ps
T367 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1102075124 Jun 24 05:50:29 PM PDT 24 Jun 24 05:50:31 PM PDT 24 502520969 ps
T368 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1066771881 Jun 24 05:50:47 PM PDT 24 Jun 24 05:50:49 PM PDT 24 560427650 ps
T369 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2965269986 Jun 24 05:50:56 PM PDT 24 Jun 24 05:51:00 PM PDT 24 563017571 ps
T370 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3852915267 Jun 24 05:50:17 PM PDT 24 Jun 24 05:50:20 PM PDT 24 581306510 ps
T371 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4138621111 Jun 24 05:50:16 PM PDT 24 Jun 24 05:50:21 PM PDT 24 7200467471 ps
T372 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2301816424 Jun 24 05:50:18 PM PDT 24 Jun 24 05:50:23 PM PDT 24 7435439762 ps
T373 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2852979 Jun 24 05:50:32 PM PDT 24 Jun 24 05:50:34 PM PDT 24 402977904 ps
T374 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.948724853 Jun 24 05:50:49 PM PDT 24 Jun 24 05:50:50 PM PDT 24 313674031 ps
T375 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.28575273 Jun 24 05:51:06 PM PDT 24 Jun 24 05:51:13 PM PDT 24 7781270490 ps
T376 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1892437158 Jun 24 05:51:07 PM PDT 24 Jun 24 05:51:10 PM PDT 24 1273355618 ps
T377 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2108691282 Jun 24 05:50:56 PM PDT 24 Jun 24 05:50:59 PM PDT 24 2591851699 ps
T378 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.358723851 Jun 24 05:50:31 PM PDT 24 Jun 24 05:50:40 PM PDT 24 8949486113 ps
T379 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3541597659 Jun 24 05:51:08 PM PDT 24 Jun 24 05:51:10 PM PDT 24 418030613 ps
T380 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3467857990 Jun 24 05:50:46 PM PDT 24 Jun 24 05:50:49 PM PDT 24 1909513482 ps
T381 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2452707862 Jun 24 05:50:57 PM PDT 24 Jun 24 05:50:59 PM PDT 24 464999204 ps
T382 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3678778244 Jun 24 05:51:05 PM PDT 24 Jun 24 05:51:07 PM PDT 24 589113209 ps
T383 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.675442491 Jun 24 05:51:04 PM PDT 24 Jun 24 05:51:06 PM PDT 24 303552294 ps
T384 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3349075337 Jun 24 05:50:19 PM PDT 24 Jun 24 05:50:22 PM PDT 24 492209039 ps
T385 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.510516690 Jun 24 05:50:56 PM PDT 24 Jun 24 05:50:59 PM PDT 24 556016650 ps
T386 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3437245459 Jun 24 05:50:26 PM PDT 24 Jun 24 05:50:31 PM PDT 24 1629954287 ps
T387 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2823831575 Jun 24 05:51:04 PM PDT 24 Jun 24 05:51:06 PM PDT 24 415833425 ps
T388 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1241069121 Jun 24 05:51:03 PM PDT 24 Jun 24 05:51:05 PM PDT 24 532518054 ps
T389 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.361615567 Jun 24 05:50:45 PM PDT 24 Jun 24 05:50:47 PM PDT 24 508454791 ps
T390 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3539682988 Jun 24 05:51:04 PM PDT 24 Jun 24 05:51:06 PM PDT 24 335574097 ps
T391 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2511783008 Jun 24 05:50:47 PM PDT 24 Jun 24 05:50:50 PM PDT 24 399471065 ps
T392 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1745215105 Jun 24 05:50:29 PM PDT 24 Jun 24 05:50:32 PM PDT 24 539113790 ps
T196 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2180852561 Jun 24 05:50:08 PM PDT 24 Jun 24 05:50:11 PM PDT 24 4297193860 ps
T393 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.75648527 Jun 24 05:51:04 PM PDT 24 Jun 24 05:51:07 PM PDT 24 450745745 ps
T394 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4294017783 Jun 24 05:50:56 PM PDT 24 Jun 24 05:50:59 PM PDT 24 406009527 ps
T395 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1141654941 Jun 24 05:50:28 PM PDT 24 Jun 24 05:50:30 PM PDT 24 537286200 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3200174259 Jun 24 05:50:16 PM PDT 24 Jun 24 05:50:20 PM PDT 24 425541284 ps
T397 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1740372827 Jun 24 05:50:39 PM PDT 24 Jun 24 05:50:43 PM PDT 24 4316049548 ps
T398 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1276406110 Jun 24 05:50:08 PM PDT 24 Jun 24 05:50:10 PM PDT 24 470738929 ps
T399 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1407095496 Jun 24 05:51:15 PM PDT 24 Jun 24 05:51:17 PM PDT 24 418196245 ps
T400 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.576766974 Jun 24 05:50:17 PM PDT 24 Jun 24 05:50:19 PM PDT 24 420161018 ps
T401 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.983355996 Jun 24 05:51:14 PM PDT 24 Jun 24 05:51:17 PM PDT 24 412552675 ps
T56 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4018633879 Jun 24 05:50:08 PM PDT 24 Jun 24 05:50:09 PM PDT 24 333241139 ps
T402 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1013540539 Jun 24 05:50:48 PM PDT 24 Jun 24 05:50:51 PM PDT 24 708161690 ps
T403 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.651446094 Jun 24 05:50:56 PM PDT 24 Jun 24 05:51:02 PM PDT 24 4368840296 ps
T404 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1344895279 Jun 24 05:50:06 PM PDT 24 Jun 24 05:50:10 PM PDT 24 2398401838 ps
T405 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.441406882 Jun 24 05:51:06 PM PDT 24 Jun 24 05:51:09 PM PDT 24 427877636 ps
T406 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1939715683 Jun 24 05:50:17 PM PDT 24 Jun 24 05:50:19 PM PDT 24 431486450 ps
T407 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1688748890 Jun 24 05:50:37 PM PDT 24 Jun 24 05:50:40 PM PDT 24 534052901 ps
T408 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2902875483 Jun 24 05:51:04 PM PDT 24 Jun 24 05:51:06 PM PDT 24 446250319 ps
T409 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3923734461 Jun 24 05:50:48 PM PDT 24 Jun 24 05:50:49 PM PDT 24 343250008 ps
T410 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3824889680 Jun 24 05:51:06 PM PDT 24 Jun 24 05:51:08 PM PDT 24 405237159 ps
T411 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.522483344 Jun 24 05:50:36 PM PDT 24 Jun 24 05:50:38 PM PDT 24 604216480 ps
T412 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2811899288 Jun 24 05:50:44 PM PDT 24 Jun 24 05:50:45 PM PDT 24 391807028 ps
T413 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.818196449 Jun 24 05:50:18 PM PDT 24 Jun 24 05:50:20 PM PDT 24 544205368 ps
T414 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2479496212 Jun 24 05:50:56 PM PDT 24 Jun 24 05:51:00 PM PDT 24 899552275 ps
T415 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.967929866 Jun 24 05:51:06 PM PDT 24 Jun 24 05:51:09 PM PDT 24 434506660 ps
T416 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1009363953 Jun 24 05:50:56 PM PDT 24 Jun 24 05:50:58 PM PDT 24 317757117 ps
T417 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3352866845 Jun 24 05:50:56 PM PDT 24 Jun 24 05:50:58 PM PDT 24 406232834 ps
T418 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1356646871 Jun 24 05:50:16 PM PDT 24 Jun 24 05:50:19 PM PDT 24 2142867845 ps
T419 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3096208392 Jun 24 05:51:06 PM PDT 24 Jun 24 05:51:09 PM PDT 24 311818254 ps
T420 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1792236875 Jun 24 05:50:56 PM PDT 24 Jun 24 05:50:58 PM PDT 24 350414693 ps
T421 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4057513066 Jun 24 05:51:06 PM PDT 24 Jun 24 05:51:08 PM PDT 24 474478544 ps
T422 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3357757659 Jun 24 05:50:46 PM PDT 24 Jun 24 05:50:48 PM PDT 24 398843990 ps
T423 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3527695862 Jun 24 05:51:07 PM PDT 24 Jun 24 05:51:10 PM PDT 24 389766348 ps
T424 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3335634567 Jun 24 05:50:16 PM PDT 24 Jun 24 05:50:20 PM PDT 24 2067563673 ps
T425 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2736448899 Jun 24 05:50:06 PM PDT 24 Jun 24 05:50:08 PM PDT 24 547418001 ps

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3642686368
Short name T4
Test name
Test status
Simulation time 170541780681 ps
CPU time 216.28 seconds
Started Jun 24 05:49:11 PM PDT 24
Finished Jun 24 05:52:49 PM PDT 24
Peak memory 207272 kb
Host smart-8e0fbd34-d8a5-4711-908b-2b8e857f3738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642686368 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3642686368
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3307136868
Short name T17
Test name
Test status
Simulation time 173336210093 ps
CPU time 68.71 seconds
Started Jun 24 05:49:01 PM PDT 24
Finished Jun 24 05:50:11 PM PDT 24
Peak memory 198972 kb
Host smart-7405ce0e-bbbc-4798-8755-63ef033a3767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307136868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3307136868
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.195458419
Short name T36
Test name
Test status
Simulation time 235977548549 ps
CPU time 694.48 seconds
Started Jun 24 05:49:48 PM PDT 24
Finished Jun 24 06:01:24 PM PDT 24
Peak memory 213928 kb
Host smart-b3ddd127-d625-42f9-abe3-74d180a77a90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195458419 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.195458419
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1842598588
Short name T28
Test name
Test status
Simulation time 8681239013 ps
CPU time 2.54 seconds
Started Jun 24 05:50:47 PM PDT 24
Finished Jun 24 05:50:50 PM PDT 24
Peak memory 198052 kb
Host smart-917360ff-6209-4c3d-b79e-821d1177d44c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842598588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1842598588
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.198727361
Short name T11
Test name
Test status
Simulation time 55398267070 ps
CPU time 33.9 seconds
Started Jun 24 05:49:49 PM PDT 24
Finished Jun 24 05:50:24 PM PDT 24
Peak memory 184652 kb
Host smart-01c6b849-3962-4d41-a345-436ebff05a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198727361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.198727361
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.4268603371
Short name T34
Test name
Test status
Simulation time 314769368885 ps
CPU time 367.79 seconds
Started Jun 24 05:49:58 PM PDT 24
Finished Jun 24 05:56:08 PM PDT 24
Peak memory 207272 kb
Host smart-355aad4d-cdf9-45b5-9a43-0ed779612f6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268603371 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.4268603371
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2745445944
Short name T84
Test name
Test status
Simulation time 496600474619 ps
CPU time 830.3 seconds
Started Jun 24 05:49:30 PM PDT 24
Finished Jun 24 06:03:21 PM PDT 24
Peak memory 215452 kb
Host smart-9d33e9d9-9a21-4b72-a687-1bc7422953f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745445944 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2745445944
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2893715545
Short name T102
Test name
Test status
Simulation time 85415359011 ps
CPU time 929.2 seconds
Started Jun 24 05:48:35 PM PDT 24
Finished Jun 24 06:04:06 PM PDT 24
Peak memory 215712 kb
Host smart-7c7dbbbd-8a2b-4c8b-a7f6-4de2dd6d3087
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893715545 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2893715545
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1320646419
Short name T93
Test name
Test status
Simulation time 69007942225 ps
CPU time 517.93 seconds
Started Jun 24 05:48:45 PM PDT 24
Finished Jun 24 05:57:24 PM PDT 24
Peak memory 214756 kb
Host smart-eb856556-5b3b-4e2f-9509-3833bcb099a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320646419 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1320646419
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1415670872
Short name T96
Test name
Test status
Simulation time 323313923167 ps
CPU time 1103.21 seconds
Started Jun 24 05:48:52 PM PDT 24
Finished Jun 24 06:07:17 PM PDT 24
Peak memory 215448 kb
Host smart-b90f1a25-8c20-41af-a0c0-c72b1e394464
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415670872 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1415670872
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2863375280
Short name T62
Test name
Test status
Simulation time 122282410632 ps
CPU time 686.97 seconds
Started Jun 24 05:49:47 PM PDT 24
Finished Jun 24 06:01:14 PM PDT 24
Peak memory 215496 kb
Host smart-37a50b55-55a1-443d-9c4e-82277b42be73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863375280 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2863375280
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3840890756
Short name T111
Test name
Test status
Simulation time 54904580870 ps
CPU time 409.83 seconds
Started Jun 24 05:50:00 PM PDT 24
Finished Jun 24 05:56:52 PM PDT 24
Peak memory 201224 kb
Host smart-78b79e82-cce6-4163-9b49-197162aaeec6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840890756 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3840890756
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3285595725
Short name T19
Test name
Test status
Simulation time 3847592304 ps
CPU time 2.09 seconds
Started Jun 24 05:48:28 PM PDT 24
Finished Jun 24 05:48:31 PM PDT 24
Peak memory 216220 kb
Host smart-b4eb0666-f8e0-4e5f-bd1a-8b0d1afa0820
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285595725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3285595725
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2476081948
Short name T130
Test name
Test status
Simulation time 403191870569 ps
CPU time 321.09 seconds
Started Jun 24 05:49:12 PM PDT 24
Finished Jun 24 05:54:34 PM PDT 24
Peak memory 202448 kb
Host smart-d6caf8dc-2c3d-4d79-91e5-98b179459008
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476081948 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2476081948
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1113403903
Short name T44
Test name
Test status
Simulation time 99976985843 ps
CPU time 831.95 seconds
Started Jun 24 05:48:34 PM PDT 24
Finished Jun 24 06:02:28 PM PDT 24
Peak memory 207956 kb
Host smart-477d1976-4d6b-484a-8168-604668bf197c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113403903 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1113403903
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.517807604
Short name T47
Test name
Test status
Simulation time 342557744284 ps
CPU time 896.77 seconds
Started Jun 24 05:49:00 PM PDT 24
Finished Jun 24 06:03:58 PM PDT 24
Peak memory 215496 kb
Host smart-5ae9c742-9bae-4a2a-bbb7-d03282eb1ce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517807604 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.517807604
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3630829239
Short name T94
Test name
Test status
Simulation time 29424406761 ps
CPU time 44.18 seconds
Started Jun 24 05:48:42 PM PDT 24
Finished Jun 24 05:49:27 PM PDT 24
Peak memory 193472 kb
Host smart-bab43813-c3ac-4730-a744-fb590487ff35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630829239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3630829239
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.870705096
Short name T83
Test name
Test status
Simulation time 192779967090 ps
CPU time 369.32 seconds
Started Jun 24 05:49:57 PM PDT 24
Finished Jun 24 05:56:09 PM PDT 24
Peak memory 202636 kb
Host smart-6477d355-3a2e-47b5-a0f4-bce93ab77725
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870705096 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.870705096
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2655673765
Short name T116
Test name
Test status
Simulation time 23114307048 ps
CPU time 179.43 seconds
Started Jun 24 05:48:36 PM PDT 24
Finished Jun 24 05:51:37 PM PDT 24
Peak memory 207268 kb
Host smart-8166f83f-de05-4c93-a892-b1a4376248e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655673765 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2655673765
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1590978990
Short name T65
Test name
Test status
Simulation time 65430792557 ps
CPU time 486.01 seconds
Started Jun 24 05:50:01 PM PDT 24
Finished Jun 24 05:58:09 PM PDT 24
Peak memory 202716 kb
Host smart-8d12d8c7-a2c3-4ead-9f84-d790bd8c71c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590978990 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1590978990
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2500869869
Short name T95
Test name
Test status
Simulation time 210453824830 ps
CPU time 317.2 seconds
Started Jun 24 05:48:25 PM PDT 24
Finished Jun 24 05:53:43 PM PDT 24
Peak memory 193428 kb
Host smart-0ae83152-9af0-4d13-873c-2f2c5fc2eab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500869869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2500869869
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2632994155
Short name T114
Test name
Test status
Simulation time 59672716098 ps
CPU time 648.24 seconds
Started Jun 24 05:49:37 PM PDT 24
Finished Jun 24 06:00:26 PM PDT 24
Peak memory 212740 kb
Host smart-1c3f0a21-4abb-4b43-9cc0-ec3aaa3246bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632994155 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2632994155
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3796687937
Short name T87
Test name
Test status
Simulation time 243758243132 ps
CPU time 173.36 seconds
Started Jun 24 05:49:21 PM PDT 24
Finished Jun 24 05:52:16 PM PDT 24
Peak memory 192964 kb
Host smart-caafe25d-0cab-4327-a429-c4ee7a4ce06b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796687937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3796687937
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.281309938
Short name T18
Test name
Test status
Simulation time 104816722375 ps
CPU time 17.47 seconds
Started Jun 24 05:49:58 PM PDT 24
Finished Jun 24 05:50:18 PM PDT 24
Peak memory 193436 kb
Host smart-44cae308-992e-4fb7-a8bd-02c4ea8c0e39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281309938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.281309938
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.638404339
Short name T107
Test name
Test status
Simulation time 21451614440 ps
CPU time 4.51 seconds
Started Jun 24 05:48:54 PM PDT 24
Finished Jun 24 05:49:00 PM PDT 24
Peak memory 198784 kb
Host smart-e50480e0-b445-4e48-b101-6241c558cd54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638404339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.638404339
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3798389157
Short name T148
Test name
Test status
Simulation time 181904889776 ps
CPU time 407.17 seconds
Started Jun 24 05:49:01 PM PDT 24
Finished Jun 24 05:55:49 PM PDT 24
Peak memory 211396 kb
Host smart-b7031403-fe21-431c-a158-f6db4770ac99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798389157 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3798389157
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3767251186
Short name T58
Test name
Test status
Simulation time 317459865 ps
CPU time 1.03 seconds
Started Jun 24 05:50:37 PM PDT 24
Finished Jun 24 05:50:40 PM PDT 24
Peak memory 183672 kb
Host smart-7f8da3d0-65ad-4172-8e4a-8d9049dc964c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767251186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3767251186
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2849883650
Short name T108
Test name
Test status
Simulation time 246619620749 ps
CPU time 350.29 seconds
Started Jun 24 05:49:01 PM PDT 24
Finished Jun 24 05:54:52 PM PDT 24
Peak memory 193000 kb
Host smart-1e463852-f077-446f-8430-0e5a79baae42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849883650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2849883650
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.538695720
Short name T151
Test name
Test status
Simulation time 155886103723 ps
CPU time 517.74 seconds
Started Jun 24 05:49:23 PM PDT 24
Finished Jun 24 05:58:02 PM PDT 24
Peak memory 204716 kb
Host smart-df886fff-591a-496b-87cf-e7d011dc9f86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538695720 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.538695720
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2311842743
Short name T9
Test name
Test status
Simulation time 90011626972 ps
CPU time 309.94 seconds
Started Jun 24 05:49:31 PM PDT 24
Finished Jun 24 05:54:42 PM PDT 24
Peak memory 201768 kb
Host smart-f196cdb7-23a2-470b-87b7-062f70988108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311842743 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2311842743
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.4040383858
Short name T100
Test name
Test status
Simulation time 213903963766 ps
CPU time 153.13 seconds
Started Jun 24 05:50:10 PM PDT 24
Finished Jun 24 05:52:44 PM PDT 24
Peak memory 198660 kb
Host smart-c41b4184-095e-4bb4-bb4a-3eef802579a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040383858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.4040383858
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2457735461
Short name T32
Test name
Test status
Simulation time 528566314310 ps
CPU time 661.62 seconds
Started Jun 24 05:48:43 PM PDT 24
Finished Jun 24 05:59:45 PM PDT 24
Peak memory 207276 kb
Host smart-15002fca-4102-430c-8afc-84698a19c9b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457735461 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2457735461
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2065759890
Short name T117
Test name
Test status
Simulation time 53213937742 ps
CPU time 38.22 seconds
Started Jun 24 05:48:35 PM PDT 24
Finished Jun 24 05:49:15 PM PDT 24
Peak memory 193444 kb
Host smart-d45ede42-9554-4c8b-90ce-7010ca90786a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065759890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2065759890
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.352876095
Short name T97
Test name
Test status
Simulation time 69260866065 ps
CPU time 90.94 seconds
Started Jun 24 05:48:28 PM PDT 24
Finished Jun 24 05:50:00 PM PDT 24
Peak memory 193520 kb
Host smart-b3e9be9a-928b-467c-9ec5-641e2e1b55db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352876095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.352876095
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.484535782
Short name T171
Test name
Test status
Simulation time 400277907453 ps
CPU time 646.77 seconds
Started Jun 24 05:48:25 PM PDT 24
Finished Jun 24 05:59:13 PM PDT 24
Peak memory 206724 kb
Host smart-2804d657-4cde-4c2d-9f5d-54e9389a881b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484535782 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.484535782
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2664946187
Short name T13
Test name
Test status
Simulation time 182093839099 ps
CPU time 845.88 seconds
Started Jun 24 05:49:30 PM PDT 24
Finished Jun 24 06:03:37 PM PDT 24
Peak memory 208924 kb
Host smart-c26c85e9-e22b-459a-ad04-c613cac917fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664946187 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2664946187
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2399190057
Short name T129
Test name
Test status
Simulation time 51864295886 ps
CPU time 234.22 seconds
Started Jun 24 05:48:51 PM PDT 24
Finished Jun 24 05:52:46 PM PDT 24
Peak memory 199060 kb
Host smart-35414067-adac-40bd-ada9-fd668581c801
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399190057 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2399190057
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3811855917
Short name T170
Test name
Test status
Simulation time 137204441539 ps
CPU time 372.62 seconds
Started Jun 24 05:49:21 PM PDT 24
Finished Jun 24 05:55:35 PM PDT 24
Peak memory 211312 kb
Host smart-fef4cfe9-84aa-4be7-a2c4-4d9d3defec46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811855917 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3811855917
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3291295300
Short name T156
Test name
Test status
Simulation time 28219689867 ps
CPU time 28.27 seconds
Started Jun 24 05:49:30 PM PDT 24
Finished Jun 24 05:49:59 PM PDT 24
Peak memory 192332 kb
Host smart-b3dcbd1a-6256-40cc-8fb7-ed991e939195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291295300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3291295300
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1170006392
Short name T124
Test name
Test status
Simulation time 109161425348 ps
CPU time 42.16 seconds
Started Jun 24 05:49:39 PM PDT 24
Finished Jun 24 05:50:22 PM PDT 24
Peak memory 193476 kb
Host smart-ca818923-e6d3-4de8-8d47-f69e7309e421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170006392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1170006392
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1580503828
Short name T99
Test name
Test status
Simulation time 88841749576 ps
CPU time 471.02 seconds
Started Jun 24 05:49:48 PM PDT 24
Finished Jun 24 05:57:40 PM PDT 24
Peak memory 207292 kb
Host smart-af4d898f-7f4c-4986-a64c-ed1fac525e7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580503828 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1580503828
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3446530524
Short name T33
Test name
Test status
Simulation time 50131554491 ps
CPU time 333.82 seconds
Started Jun 24 05:48:46 PM PDT 24
Finished Jun 24 05:54:21 PM PDT 24
Peak memory 207316 kb
Host smart-181b9164-1f8e-41f6-823a-d2d212fe0fa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446530524 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3446530524
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3305300347
Short name T155
Test name
Test status
Simulation time 166160250294 ps
CPU time 231.43 seconds
Started Jun 24 05:48:53 PM PDT 24
Finished Jun 24 05:52:45 PM PDT 24
Peak memory 192964 kb
Host smart-773c36f0-1f52-4824-8353-b573bf911c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305300347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3305300347
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3748249785
Short name T142
Test name
Test status
Simulation time 239202369683 ps
CPU time 86.51 seconds
Started Jun 24 05:49:49 PM PDT 24
Finished Jun 24 05:51:17 PM PDT 24
Peak memory 198760 kb
Host smart-a830724e-45bf-4f3e-baa8-258f140fd1bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748249785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3748249785
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.4105041001
Short name T163
Test name
Test status
Simulation time 99989123813 ps
CPU time 215.62 seconds
Started Jun 24 05:50:00 PM PDT 24
Finished Jun 24 05:53:38 PM PDT 24
Peak memory 200916 kb
Host smart-5e82951d-466b-482a-a05b-e9c2090f1030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105041001 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.4105041001
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.444256383
Short name T12
Test name
Test status
Simulation time 260700850919 ps
CPU time 519.88 seconds
Started Jun 24 05:48:42 PM PDT 24
Finished Jun 24 05:57:23 PM PDT 24
Peak memory 212996 kb
Host smart-e678d5c2-f85b-47c4-8771-935b753386ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444256383 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.444256383
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2701861754
Short name T22
Test name
Test status
Simulation time 189860006749 ps
CPU time 409.7 seconds
Started Jun 24 05:49:13 PM PDT 24
Finished Jun 24 05:56:04 PM PDT 24
Peak memory 203012 kb
Host smart-aaaee80c-d22f-4692-b431-83182bb51255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701861754 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2701861754
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1360904757
Short name T146
Test name
Test status
Simulation time 97112230910 ps
CPU time 39.4 seconds
Started Jun 24 05:49:57 PM PDT 24
Finished Jun 24 05:50:39 PM PDT 24
Peak memory 192404 kb
Host smart-d5922a25-8d36-4931-9531-1169f3f261d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360904757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1360904757
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3931458077
Short name T89
Test name
Test status
Simulation time 274683292441 ps
CPU time 752.12 seconds
Started Jun 24 05:48:44 PM PDT 24
Finished Jun 24 06:01:17 PM PDT 24
Peak memory 207636 kb
Host smart-4101a74e-0995-488e-946e-5523c09de2ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931458077 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3931458077
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3093117013
Short name T113
Test name
Test status
Simulation time 67136077606 ps
CPU time 487.21 seconds
Started Jun 24 05:49:23 PM PDT 24
Finished Jun 24 05:57:31 PM PDT 24
Peak memory 201032 kb
Host smart-9e2fcd1f-d6e0-4857-a9a8-3b56935d22c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093117013 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3093117013
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.4066711499
Short name T109
Test name
Test status
Simulation time 185170831377 ps
CPU time 245.47 seconds
Started Jun 24 05:49:19 PM PDT 24
Finished Jun 24 05:53:26 PM PDT 24
Peak memory 192376 kb
Host smart-5ae21925-57c9-416e-9dcc-57b98b74a569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066711499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.4066711499
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1989752635
Short name T154
Test name
Test status
Simulation time 141957357239 ps
CPU time 221.99 seconds
Started Jun 24 05:50:00 PM PDT 24
Finished Jun 24 05:53:44 PM PDT 24
Peak memory 198788 kb
Host smart-1d1be49d-5b18-434d-bb83-fdbf3f41f2a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989752635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1989752635
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3728031284
Short name T46
Test name
Test status
Simulation time 41315742750 ps
CPU time 269.77 seconds
Started Jun 24 05:49:22 PM PDT 24
Finished Jun 24 05:53:53 PM PDT 24
Peak memory 215332 kb
Host smart-6ed54eab-b2bf-4fb9-a303-3a65d62ff630
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728031284 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3728031284
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1390801826
Short name T2
Test name
Test status
Simulation time 310200146205 ps
CPU time 422.18 seconds
Started Jun 24 05:49:20 PM PDT 24
Finished Jun 24 05:56:23 PM PDT 24
Peak memory 192972 kb
Host smart-7f843903-95c4-4bb4-893f-88ec4d478e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390801826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1390801826
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3411064886
Short name T101
Test name
Test status
Simulation time 151809753845 ps
CPU time 201.15 seconds
Started Jun 24 05:49:23 PM PDT 24
Finished Jun 24 05:52:45 PM PDT 24
Peak memory 192428 kb
Host smart-9221f196-a416-4fb1-b9bc-0ce2e21e689c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411064886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3411064886
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.4065507542
Short name T98
Test name
Test status
Simulation time 260854938411 ps
CPU time 81.61 seconds
Started Jun 24 05:49:02 PM PDT 24
Finished Jun 24 05:50:25 PM PDT 24
Peak memory 192420 kb
Host smart-28aa18cf-bf6c-416f-bef4-45c209e48d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065507542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.4065507542
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1712388043
Short name T82
Test name
Test status
Simulation time 59539770405 ps
CPU time 91.83 seconds
Started Jun 24 05:49:28 PM PDT 24
Finished Jun 24 05:51:01 PM PDT 24
Peak memory 207320 kb
Host smart-4af96509-0a7d-43dd-b597-cee1e52963c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712388043 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1712388043
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3151127137
Short name T80
Test name
Test status
Simulation time 108308977320 ps
CPU time 545.58 seconds
Started Jun 24 05:49:38 PM PDT 24
Finished Jun 24 05:58:44 PM PDT 24
Peak memory 208968 kb
Host smart-16154586-0ae4-4b2d-b831-005921ff286d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151127137 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3151127137
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3244407187
Short name T85
Test name
Test status
Simulation time 141038125617 ps
CPU time 538.65 seconds
Started Jun 24 05:49:00 PM PDT 24
Finished Jun 24 05:58:00 PM PDT 24
Peak memory 212600 kb
Host smart-4181328b-c1c6-4cb6-8a4f-602e1466aa91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244407187 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3244407187
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.356393539
Short name T132
Test name
Test status
Simulation time 182739542216 ps
CPU time 233.33 seconds
Started Jun 24 05:49:29 PM PDT 24
Finished Jun 24 05:53:23 PM PDT 24
Peak memory 198688 kb
Host smart-c0dfe571-9dc9-4a0e-9627-a6b761550a5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356393539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.356393539
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2982245444
Short name T88
Test name
Test status
Simulation time 105880190898 ps
CPU time 166.11 seconds
Started Jun 24 05:49:50 PM PDT 24
Finished Jun 24 05:52:37 PM PDT 24
Peak memory 192380 kb
Host smart-71aa762b-3349-433e-b9f8-5115e0efbea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982245444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2982245444
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.113745863
Short name T92
Test name
Test status
Simulation time 216855208474 ps
CPU time 83.41 seconds
Started Jun 24 05:49:47 PM PDT 24
Finished Jun 24 05:51:11 PM PDT 24
Peak memory 193684 kb
Host smart-2beff650-d388-47cb-88c0-dbfbcb0f07fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113745863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.113745863
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3954897387
Short name T119
Test name
Test status
Simulation time 137592106777 ps
CPU time 92.07 seconds
Started Jun 24 05:49:19 PM PDT 24
Finished Jun 24 05:50:52 PM PDT 24
Peak memory 193476 kb
Host smart-bd23e0bc-407d-48a2-a248-cc054f99170b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954897387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3954897387
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2570799580
Short name T141
Test name
Test status
Simulation time 68755694963 ps
CPU time 284.86 seconds
Started Jun 24 05:49:20 PM PDT 24
Finished Jun 24 05:54:06 PM PDT 24
Peak memory 208916 kb
Host smart-0d0d4bb3-6922-4305-9c25-60c8688006e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570799580 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2570799580
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1201897585
Short name T134
Test name
Test status
Simulation time 25245650732 ps
CPU time 191.08 seconds
Started Jun 24 05:49:41 PM PDT 24
Finished Jun 24 05:52:53 PM PDT 24
Peak memory 199168 kb
Host smart-4c3a0a09-4397-4ae6-92bc-53c599741c72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201897585 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1201897585
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2057959321
Short name T91
Test name
Test status
Simulation time 184007319277 ps
CPU time 259.77 seconds
Started Jun 24 05:48:34 PM PDT 24
Finished Jun 24 05:52:55 PM PDT 24
Peak memory 198692 kb
Host smart-62816ab3-eeb6-4915-8292-a59b95aef218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057959321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2057959321
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1974406714
Short name T164
Test name
Test status
Simulation time 141350196890 ps
CPU time 240.12 seconds
Started Jun 24 05:48:36 PM PDT 24
Finished Jun 24 05:52:38 PM PDT 24
Peak memory 201116 kb
Host smart-e5b6bc65-a431-486f-8e51-520b2d76fc95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974406714 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1974406714
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.723397165
Short name T136
Test name
Test status
Simulation time 116579790412 ps
CPU time 82.3 seconds
Started Jun 24 05:49:31 PM PDT 24
Finished Jun 24 05:50:54 PM PDT 24
Peak memory 192664 kb
Host smart-776219e4-3469-467b-9032-0336a2e27a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723397165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.723397165
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1058431328
Short name T112
Test name
Test status
Simulation time 399262734 ps
CPU time 1.1 seconds
Started Jun 24 05:49:39 PM PDT 24
Finished Jun 24 05:49:41 PM PDT 24
Peak memory 197108 kb
Host smart-7885044d-51c8-479e-a371-6c4507fa4098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058431328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1058431328
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1524249069
Short name T35
Test name
Test status
Simulation time 322938396679 ps
CPU time 917.31 seconds
Started Jun 24 05:50:00 PM PDT 24
Finished Jun 24 06:05:20 PM PDT 24
Peak memory 215460 kb
Host smart-8523bb42-3232-46c4-9949-9369baa108e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524249069 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1524249069
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.981743316
Short name T165
Test name
Test status
Simulation time 233249938370 ps
CPU time 161.75 seconds
Started Jun 24 05:48:43 PM PDT 24
Finished Jun 24 05:51:26 PM PDT 24
Peak memory 198768 kb
Host smart-c983c152-9b2d-4dc9-b1a6-0430faa7fbbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981743316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.981743316
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.388434663
Short name T37
Test name
Test status
Simulation time 492016236 ps
CPU time 1.31 seconds
Started Jun 24 05:48:28 PM PDT 24
Finished Jun 24 05:48:31 PM PDT 24
Peak memory 197064 kb
Host smart-07b874fc-43a7-436b-811e-54773b5cbd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388434663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.388434663
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3525967055
Short name T118
Test name
Test status
Simulation time 55021705695 ps
CPU time 21.8 seconds
Started Jun 24 05:49:10 PM PDT 24
Finished Jun 24 05:49:34 PM PDT 24
Peak memory 192408 kb
Host smart-a08ce56f-1a61-4d89-a6fd-61ffe5b78aff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525967055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3525967055
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.822617714
Short name T121
Test name
Test status
Simulation time 578441540 ps
CPU time 0.83 seconds
Started Jun 24 05:49:31 PM PDT 24
Finished Jun 24 05:49:33 PM PDT 24
Peak memory 197104 kb
Host smart-553549d1-5ef6-4b01-a8e9-724a62827359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822617714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.822617714
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3456233932
Short name T24
Test name
Test status
Simulation time 625599846 ps
CPU time 0.8 seconds
Started Jun 24 05:48:35 PM PDT 24
Finished Jun 24 05:48:37 PM PDT 24
Peak memory 197080 kb
Host smart-de7323f0-c1e3-4ec6-8223-9c51c736bf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456233932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3456233932
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2858964775
Short name T150
Test name
Test status
Simulation time 70131980282 ps
CPU time 15.63 seconds
Started Jun 24 05:48:34 PM PDT 24
Finished Jun 24 05:48:51 PM PDT 24
Peak memory 193496 kb
Host smart-87f784f9-0220-4a58-bdde-b64c0d509c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858964775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2858964775
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2883400202
Short name T67
Test name
Test status
Simulation time 509946320 ps
CPU time 0.81 seconds
Started Jun 24 05:50:00 PM PDT 24
Finished Jun 24 05:50:03 PM PDT 24
Peak memory 197176 kb
Host smart-a55fff41-0f77-4665-87a3-7872b08d9836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883400202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2883400202
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.214356803
Short name T167
Test name
Test status
Simulation time 224403132743 ps
CPU time 171.62 seconds
Started Jun 24 05:49:58 PM PDT 24
Finished Jun 24 05:52:52 PM PDT 24
Peak memory 193092 kb
Host smart-818d375c-326d-40af-9abf-d0acbf936b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214356803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.214356803
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1123865477
Short name T135
Test name
Test status
Simulation time 521021011 ps
CPU time 1.4 seconds
Started Jun 24 05:50:09 PM PDT 24
Finished Jun 24 05:50:11 PM PDT 24
Peak memory 197176 kb
Host smart-7c6bbedc-8d11-4476-bc08-98693f663891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123865477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1123865477
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.225934682
Short name T137
Test name
Test status
Simulation time 481673568 ps
CPU time 0.8 seconds
Started Jun 24 05:48:45 PM PDT 24
Finished Jun 24 05:48:47 PM PDT 24
Peak memory 197092 kb
Host smart-9e3ca222-0bc5-497f-a5ac-92325dedc8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225934682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.225934682
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3963053580
Short name T104
Test name
Test status
Simulation time 495897338 ps
CPU time 1.29 seconds
Started Jun 24 05:49:10 PM PDT 24
Finished Jun 24 05:49:13 PM PDT 24
Peak memory 197080 kb
Host smart-f345ab8a-c3eb-4c6f-b4b7-760a3ba638dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963053580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3963053580
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.402081221
Short name T127
Test name
Test status
Simulation time 435653942 ps
CPU time 1.09 seconds
Started Jun 24 05:49:37 PM PDT 24
Finished Jun 24 05:49:39 PM PDT 24
Peak memory 197060 kb
Host smart-b125e02b-c5d0-4781-b1b1-d26c542a3bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402081221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.402081221
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3977143047
Short name T131
Test name
Test status
Simulation time 65430935295 ps
CPU time 720.65 seconds
Started Jun 24 05:49:42 PM PDT 24
Finished Jun 24 06:01:43 PM PDT 24
Peak memory 205880 kb
Host smart-c5f77413-8c99-4b2c-8e18-d787a32345fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977143047 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3977143047
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.165340202
Short name T149
Test name
Test status
Simulation time 483964250 ps
CPU time 1.29 seconds
Started Jun 24 05:49:47 PM PDT 24
Finished Jun 24 05:49:50 PM PDT 24
Peak memory 197076 kb
Host smart-d06afa62-cdb1-4f78-9ea7-9a902a0f91d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165340202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.165340202
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.16497952
Short name T120
Test name
Test status
Simulation time 154176473493 ps
CPU time 102.09 seconds
Started Jun 24 05:50:05 PM PDT 24
Finished Jun 24 05:51:47 PM PDT 24
Peak memory 198760 kb
Host smart-fdfca3ab-6f4a-4d88-a6b2-3f3b6b8a8309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16497952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_al
l.16497952
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.4134888052
Short name T103
Test name
Test status
Simulation time 79691800306 ps
CPU time 230.77 seconds
Started Jun 24 05:49:00 PM PDT 24
Finished Jun 24 05:52:52 PM PDT 24
Peak memory 209012 kb
Host smart-31d44ee0-243d-4ba9-92e9-4bc191f0a56c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134888052 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.4134888052
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3670747532
Short name T123
Test name
Test status
Simulation time 548186523 ps
CPU time 1.05 seconds
Started Jun 24 05:49:02 PM PDT 24
Finished Jun 24 05:49:04 PM PDT 24
Peak memory 197184 kb
Host smart-11135aa2-00d9-49c0-98ec-88fbaa53e1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670747532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3670747532
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3156857613
Short name T153
Test name
Test status
Simulation time 563089206 ps
CPU time 0.64 seconds
Started Jun 24 05:49:20 PM PDT 24
Finished Jun 24 05:49:22 PM PDT 24
Peak memory 197112 kb
Host smart-d22509d2-cf71-4f93-a3b7-3895259791f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156857613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3156857613
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.788217962
Short name T69
Test name
Test status
Simulation time 237651452053 ps
CPU time 85.25 seconds
Started Jun 24 05:49:19 PM PDT 24
Finished Jun 24 05:50:45 PM PDT 24
Peak memory 193496 kb
Host smart-e55d24bf-3b41-4be3-912c-bcd1f1d78a86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788217962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.788217962
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2596642247
Short name T138
Test name
Test status
Simulation time 550331838 ps
CPU time 1.39 seconds
Started Jun 24 05:49:56 PM PDT 24
Finished Jun 24 05:49:59 PM PDT 24
Peak memory 197172 kb
Host smart-1fb36750-6d8e-45b9-b673-d4d62b2377f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596642247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2596642247
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1267269850
Short name T81
Test name
Test status
Simulation time 141327746544 ps
CPU time 253.87 seconds
Started Jun 24 05:50:07 PM PDT 24
Finished Jun 24 05:54:22 PM PDT 24
Peak memory 199076 kb
Host smart-fcf9e21c-78e4-4dd8-b51d-dfd3a4127e07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267269850 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1267269850
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1592650284
Short name T139
Test name
Test status
Simulation time 416427039 ps
CPU time 0.75 seconds
Started Jun 24 05:48:55 PM PDT 24
Finished Jun 24 05:48:57 PM PDT 24
Peak memory 197092 kb
Host smart-b2f34b0c-7303-4e49-977f-c7fabc0a46d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592650284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1592650284
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2127301022
Short name T152
Test name
Test status
Simulation time 371775066 ps
CPU time 0.72 seconds
Started Jun 24 05:48:53 PM PDT 24
Finished Jun 24 05:48:54 PM PDT 24
Peak memory 197072 kb
Host smart-de0dff78-24c9-4fe0-b30a-c790528558b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127301022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2127301022
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3145370328
Short name T23
Test name
Test status
Simulation time 28635253766 ps
CPU time 112.29 seconds
Started Jun 24 05:48:52 PM PDT 24
Finished Jun 24 05:50:46 PM PDT 24
Peak memory 207312 kb
Host smart-adc5de61-6c0d-411a-9d3f-cfc8a000e193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145370328 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3145370328
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3419941020
Short name T169
Test name
Test status
Simulation time 86832643467 ps
CPU time 60.72 seconds
Started Jun 24 05:48:54 PM PDT 24
Finished Jun 24 05:49:56 PM PDT 24
Peak memory 192984 kb
Host smart-dfab10a2-1419-4b71-a2a9-dac59746fc31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419941020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3419941020
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2970175072
Short name T145
Test name
Test status
Simulation time 570550119 ps
CPU time 0.69 seconds
Started Jun 24 05:49:20 PM PDT 24
Finished Jun 24 05:49:22 PM PDT 24
Peak memory 197052 kb
Host smart-3d841638-ada2-4809-947e-220a4af6dba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970175072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2970175072
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.504735982
Short name T173
Test name
Test status
Simulation time 518384548838 ps
CPU time 417.53 seconds
Started Jun 24 05:49:31 PM PDT 24
Finished Jun 24 05:56:30 PM PDT 24
Peak memory 192400 kb
Host smart-87c70a68-5610-4955-8cfb-033a88c5c3aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504735982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.504735982
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2758009445
Short name T133
Test name
Test status
Simulation time 650404657259 ps
CPU time 233.47 seconds
Started Jun 24 05:49:42 PM PDT 24
Finished Jun 24 05:53:37 PM PDT 24
Peak memory 193108 kb
Host smart-41218a1e-44b5-4262-8d2a-db954945c907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758009445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2758009445
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2062124489
Short name T90
Test name
Test status
Simulation time 347651424 ps
CPU time 1.17 seconds
Started Jun 24 05:49:39 PM PDT 24
Finished Jun 24 05:49:41 PM PDT 24
Peak memory 197156 kb
Host smart-cdd8397f-505f-4377-af90-82b7c3accb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062124489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2062124489
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1902267185
Short name T106
Test name
Test status
Simulation time 523110201 ps
CPU time 0.92 seconds
Started Jun 24 05:49:59 PM PDT 24
Finished Jun 24 05:50:02 PM PDT 24
Peak memory 197024 kb
Host smart-b20aa721-2365-41c6-af71-0089d4db2560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902267185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1902267185
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1017845058
Short name T66
Test name
Test status
Simulation time 285049676983 ps
CPU time 45.59 seconds
Started Jun 24 05:49:57 PM PDT 24
Finished Jun 24 05:50:45 PM PDT 24
Peak memory 192404 kb
Host smart-69b7b1c1-8349-4522-aec3-1045b773cf1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017845058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1017845058
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3132661187
Short name T105
Test name
Test status
Simulation time 448369119 ps
CPU time 0.75 seconds
Started Jun 24 05:48:34 PM PDT 24
Finished Jun 24 05:48:37 PM PDT 24
Peak memory 197136 kb
Host smart-cf00aaf9-58c9-4701-a88a-94bc27078f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132661187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3132661187
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.4281917763
Short name T125
Test name
Test status
Simulation time 496889406 ps
CPU time 1.39 seconds
Started Jun 24 05:48:44 PM PDT 24
Finished Jun 24 05:48:47 PM PDT 24
Peak memory 197036 kb
Host smart-b38ceaab-ccb0-4e06-bc91-80faeeae94a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281917763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.4281917763
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2219284736
Short name T162
Test name
Test status
Simulation time 129787493739 ps
CPU time 95.4 seconds
Started Jun 24 05:48:44 PM PDT 24
Finished Jun 24 05:50:20 PM PDT 24
Peak memory 198752 kb
Host smart-139b744b-e486-4b5b-9a01-ebad76825d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219284736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2219284736
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3274750563
Short name T166
Test name
Test status
Simulation time 173655435345 ps
CPU time 247.28 seconds
Started Jun 24 05:49:01 PM PDT 24
Finished Jun 24 05:53:09 PM PDT 24
Peak memory 193500 kb
Host smart-4730b602-2568-4852-a9af-b17ef4a70561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274750563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3274750563
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3924104020
Short name T158
Test name
Test status
Simulation time 354541035150 ps
CPU time 245.69 seconds
Started Jun 24 05:49:11 PM PDT 24
Finished Jun 24 05:53:18 PM PDT 24
Peak memory 198776 kb
Host smart-77b69e6e-3f5e-4804-b4a8-62cc9967b840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924104020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3924104020
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2910428633
Short name T140
Test name
Test status
Simulation time 563433003 ps
CPU time 0.75 seconds
Started Jun 24 05:49:11 PM PDT 24
Finished Jun 24 05:49:13 PM PDT 24
Peak memory 197100 kb
Host smart-0afa0e4b-67c4-48c9-b31b-ad8cb9a49be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910428633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2910428633
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.425399726
Short name T110
Test name
Test status
Simulation time 537536779 ps
CPU time 0.8 seconds
Started Jun 24 05:49:21 PM PDT 24
Finished Jun 24 05:49:23 PM PDT 24
Peak memory 197084 kb
Host smart-0d7f6a0b-060b-4c23-9b50-bffd49447df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425399726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.425399726
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.575948735
Short name T86
Test name
Test status
Simulation time 388688174 ps
CPU time 0.72 seconds
Started Jun 24 05:49:59 PM PDT 24
Finished Jun 24 05:50:02 PM PDT 24
Peak memory 197008 kb
Host smart-f1c55b0f-7b6b-4f58-a595-825389b49912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575948735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.575948735
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3324267258
Short name T177
Test name
Test status
Simulation time 581635670 ps
CPU time 0.65 seconds
Started Jun 24 05:49:19 PM PDT 24
Finished Jun 24 05:49:21 PM PDT 24
Peak memory 197160 kb
Host smart-bfb17541-25fa-4320-9104-937e2d29eb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324267258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3324267258
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1644396865
Short name T147
Test name
Test status
Simulation time 545192609 ps
CPU time 1.33 seconds
Started Jun 24 05:49:19 PM PDT 24
Finished Jun 24 05:49:21 PM PDT 24
Peak memory 197180 kb
Host smart-9135a6a5-b6d0-4963-bfb0-7ce5ddef68bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644396865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1644396865
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.4026933940
Short name T181
Test name
Test status
Simulation time 365013238 ps
CPU time 0.72 seconds
Started Jun 24 05:49:41 PM PDT 24
Finished Jun 24 05:49:42 PM PDT 24
Peak memory 197068 kb
Host smart-963397de-29b8-45fb-ab2d-83b9445590e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026933940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.4026933940
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3061130669
Short name T68
Test name
Test status
Simulation time 382962721 ps
CPU time 0.86 seconds
Started Jun 24 05:48:33 PM PDT 24
Finished Jun 24 05:48:35 PM PDT 24
Peak memory 197044 kb
Host smart-46cd59d2-ac53-44fb-b971-e70c8b48bc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061130669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3061130669
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.145945406
Short name T122
Test name
Test status
Simulation time 559913861 ps
CPU time 0.76 seconds
Started Jun 24 05:49:47 PM PDT 24
Finished Jun 24 05:49:49 PM PDT 24
Peak memory 196992 kb
Host smart-46865ac8-13c0-4acc-b497-c98c2edbaa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145945406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.145945406
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3449362002
Short name T143
Test name
Test status
Simulation time 59682877581 ps
CPU time 171.45 seconds
Started Jun 24 05:49:59 PM PDT 24
Finished Jun 24 05:52:53 PM PDT 24
Peak memory 199164 kb
Host smart-e252ba18-c083-46dd-b6c7-85711c2aa493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449362002 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3449362002
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2549255145
Short name T159
Test name
Test status
Simulation time 152032754519 ps
CPU time 195.88 seconds
Started Jun 24 05:50:00 PM PDT 24
Finished Jun 24 05:53:18 PM PDT 24
Peak memory 193400 kb
Host smart-b6e4a944-f797-4012-81c6-eb9935c3900b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549255145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2549255145
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3734495675
Short name T194
Test name
Test status
Simulation time 8915521246 ps
CPU time 4.66 seconds
Started Jun 24 05:50:46 PM PDT 24
Finished Jun 24 05:50:53 PM PDT 24
Peak memory 198204 kb
Host smart-cc3c4d70-bc78-4ce1-af35-4b3900b323ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734495675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3734495675
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2023798220
Short name T179
Test name
Test status
Simulation time 121823078304 ps
CPU time 28.81 seconds
Started Jun 24 05:48:51 PM PDT 24
Finished Jun 24 05:49:21 PM PDT 24
Peak memory 192408 kb
Host smart-548c413f-b056-42db-93c0-cac82357048c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023798220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2023798220
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3260311807
Short name T128
Test name
Test status
Simulation time 435278280 ps
CPU time 1.27 seconds
Started Jun 24 05:48:54 PM PDT 24
Finished Jun 24 05:48:57 PM PDT 24
Peak memory 197116 kb
Host smart-e18c6c87-c7e6-4eaa-a8ed-7dbd7559d5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260311807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3260311807
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3723137831
Short name T63
Test name
Test status
Simulation time 447522674 ps
CPU time 1.27 seconds
Started Jun 24 05:49:01 PM PDT 24
Finished Jun 24 05:49:04 PM PDT 24
Peak memory 197040 kb
Host smart-235bfee8-f610-4c9a-a3e3-474144a3aeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723137831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3723137831
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2927480143
Short name T144
Test name
Test status
Simulation time 346506400 ps
CPU time 1.1 seconds
Started Jun 24 05:49:09 PM PDT 24
Finished Jun 24 05:49:11 PM PDT 24
Peak memory 197180 kb
Host smart-dba0304f-6a0b-4941-bf53-848909f8c268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927480143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2927480143
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3065908956
Short name T157
Test name
Test status
Simulation time 178457270931 ps
CPU time 241.88 seconds
Started Jun 24 05:49:10 PM PDT 24
Finished Jun 24 05:53:14 PM PDT 24
Peak memory 184684 kb
Host smart-152cc82e-71d2-4b96-8fec-968b22fc3951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065908956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3065908956
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.611267666
Short name T188
Test name
Test status
Simulation time 651709032 ps
CPU time 0.8 seconds
Started Jun 24 05:49:30 PM PDT 24
Finished Jun 24 05:49:32 PM PDT 24
Peak memory 197056 kb
Host smart-864cd826-7b1a-4510-814c-f997079a2881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611267666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.611267666
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2419147775
Short name T172
Test name
Test status
Simulation time 137934587057 ps
CPU time 52.44 seconds
Started Jun 24 05:49:30 PM PDT 24
Finished Jun 24 05:50:24 PM PDT 24
Peak memory 193424 kb
Host smart-2d52b8bd-e9f4-4893-a30f-a3602afaa50c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419147775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2419147775
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2472924427
Short name T115
Test name
Test status
Simulation time 585804568 ps
CPU time 1.46 seconds
Started Jun 24 05:49:28 PM PDT 24
Finished Jun 24 05:49:30 PM PDT 24
Peak memory 197076 kb
Host smart-16a12b80-b147-4b5a-bb65-6ae9babd9626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472924427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2472924427
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2035980902
Short name T180
Test name
Test status
Simulation time 172398977790 ps
CPU time 39.23 seconds
Started Jun 24 05:49:39 PM PDT 24
Finished Jun 24 05:50:19 PM PDT 24
Peak memory 198764 kb
Host smart-611c1d5d-79da-40d1-b4e3-8368e212d48a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035980902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2035980902
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3001815389
Short name T176
Test name
Test status
Simulation time 95895173600 ps
CPU time 408.54 seconds
Started Jun 24 05:49:49 PM PDT 24
Finished Jun 24 05:56:39 PM PDT 24
Peak memory 203504 kb
Host smart-67cfde40-3adf-47b3-aec0-fd2ab61f12e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001815389 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3001815389
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.531342050
Short name T183
Test name
Test status
Simulation time 384143140 ps
CPU time 0.73 seconds
Started Jun 24 05:49:58 PM PDT 24
Finished Jun 24 05:50:00 PM PDT 24
Peak memory 197040 kb
Host smart-5574672f-3506-4cd8-acf1-b69ed33c2de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531342050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.531342050
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.808249303
Short name T187
Test name
Test status
Simulation time 383365493 ps
CPU time 0.9 seconds
Started Jun 24 05:49:02 PM PDT 24
Finished Jun 24 05:49:05 PM PDT 24
Peak memory 197024 kb
Host smart-d8ff818a-d3df-4b45-b108-73f65e74cda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808249303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.808249303
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.201747020
Short name T39
Test name
Test status
Simulation time 406543130 ps
CPU time 1.12 seconds
Started Jun 24 05:49:21 PM PDT 24
Finished Jun 24 05:49:23 PM PDT 24
Peak memory 197084 kb
Host smart-1d98be86-6d31-4639-856e-dd88caee9e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201747020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.201747020
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1535692492
Short name T190
Test name
Test status
Simulation time 427120002 ps
CPU time 0.89 seconds
Started Jun 24 05:49:29 PM PDT 24
Finished Jun 24 05:49:30 PM PDT 24
Peak memory 197156 kb
Host smart-7fb77efb-70df-4ce5-81e7-ff9ee3a6df82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535692492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1535692492
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2425698699
Short name T189
Test name
Test status
Simulation time 505183765 ps
CPU time 0.7 seconds
Started Jun 24 05:49:30 PM PDT 24
Finished Jun 24 05:49:32 PM PDT 24
Peak memory 197060 kb
Host smart-79475756-d741-48df-a213-8a26637e5a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425698699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2425698699
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3172623354
Short name T41
Test name
Test status
Simulation time 389083647 ps
CPU time 0.73 seconds
Started Jun 24 05:49:56 PM PDT 24
Finished Jun 24 05:49:58 PM PDT 24
Peak memory 197056 kb
Host smart-0e119103-4684-4b0a-8091-09a43a603ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172623354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3172623354
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1876225678
Short name T185
Test name
Test status
Simulation time 511338846 ps
CPU time 0.77 seconds
Started Jun 24 05:49:56 PM PDT 24
Finished Jun 24 05:49:58 PM PDT 24
Peak memory 197068 kb
Host smart-3c419cd6-3569-4086-afc5-df6ce3a5ea58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876225678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1876225678
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.597714494
Short name T191
Test name
Test status
Simulation time 43509071472 ps
CPU time 83.27 seconds
Started Jun 24 05:49:57 PM PDT 24
Finished Jun 24 05:51:22 PM PDT 24
Peak memory 207320 kb
Host smart-49a5ddee-1d24-4bd3-9eb3-020c39fee018
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597714494 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.597714494
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.783304782
Short name T186
Test name
Test status
Simulation time 379845372 ps
CPU time 1 seconds
Started Jun 24 05:49:59 PM PDT 24
Finished Jun 24 05:50:02 PM PDT 24
Peak memory 197124 kb
Host smart-66e9dcdf-ea03-4063-b009-d7f2dbe9d990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783304782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.783304782
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3880843861
Short name T184
Test name
Test status
Simulation time 552963102 ps
CPU time 1.21 seconds
Started Jun 24 05:48:44 PM PDT 24
Finished Jun 24 05:48:46 PM PDT 24
Peak memory 197136 kb
Host smart-51dfc0f7-a8f5-47c4-9215-33aed294dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880843861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3880843861
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.991832889
Short name T126
Test name
Test status
Simulation time 343534486 ps
CPU time 1.18 seconds
Started Jun 24 05:48:43 PM PDT 24
Finished Jun 24 05:48:44 PM PDT 24
Peak memory 197172 kb
Host smart-e85e2580-1f70-4b40-a4d7-629aaeb79ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991832889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.991832889
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3067211404
Short name T161
Test name
Test status
Simulation time 265350569243 ps
CPU time 206.11 seconds
Started Jun 24 05:48:42 PM PDT 24
Finished Jun 24 05:52:09 PM PDT 24
Peak memory 192392 kb
Host smart-c89e8322-92e2-47ba-be9b-fbab69c4b589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067211404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3067211404
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4018633879
Short name T56
Test name
Test status
Simulation time 333241139 ps
CPU time 1.09 seconds
Started Jun 24 05:50:08 PM PDT 24
Finished Jun 24 05:50:09 PM PDT 24
Peak memory 192912 kb
Host smart-b29c3b33-3d8a-47a3-add6-2924fc7a9157
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018633879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4018633879
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3604905425
Short name T59
Test name
Test status
Simulation time 8924536966 ps
CPU time 23.26 seconds
Started Jun 24 05:50:08 PM PDT 24
Finished Jun 24 05:50:32 PM PDT 24
Peak memory 191956 kb
Host smart-ddb9055b-6cb8-4f19-b83b-98821422030d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604905425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3604905425
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3219255929
Short name T364
Test name
Test status
Simulation time 840618839 ps
CPU time 0.82 seconds
Started Jun 24 05:50:06 PM PDT 24
Finished Jun 24 05:50:08 PM PDT 24
Peak memory 183600 kb
Host smart-dc5c2662-e7ea-454f-8b6a-9faa51ed6e42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219255929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3219255929
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2736448899
Short name T425
Test name
Test status
Simulation time 547418001 ps
CPU time 1.49 seconds
Started Jun 24 05:50:06 PM PDT 24
Finished Jun 24 05:50:08 PM PDT 24
Peak memory 196396 kb
Host smart-e3811cdd-8a17-4083-b418-ca2f2923b1a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736448899 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2736448899
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1276406110
Short name T398
Test name
Test status
Simulation time 470738929 ps
CPU time 1.25 seconds
Started Jun 24 05:50:08 PM PDT 24
Finished Jun 24 05:50:10 PM PDT 24
Peak memory 192828 kb
Host smart-9bc5ac9a-096f-4584-b727-0f26c7f595db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276406110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1276406110
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4253466148
Short name T355
Test name
Test status
Simulation time 284522603 ps
CPU time 0.91 seconds
Started Jun 24 05:50:05 PM PDT 24
Finished Jun 24 05:50:07 PM PDT 24
Peak memory 192836 kb
Host smart-a0357cda-f328-4812-9642-ef9b93db9a6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253466148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.4253466148
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1451970666
Short name T348
Test name
Test status
Simulation time 479923682 ps
CPU time 0.69 seconds
Started Jun 24 05:50:08 PM PDT 24
Finished Jun 24 05:50:10 PM PDT 24
Peak memory 183532 kb
Host smart-4309bc55-359e-43a0-9ccc-2829cecc9119
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451970666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1451970666
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2342438343
Short name T287
Test name
Test status
Simulation time 520816880 ps
CPU time 0.71 seconds
Started Jun 24 05:50:08 PM PDT 24
Finished Jun 24 05:50:09 PM PDT 24
Peak memory 183532 kb
Host smart-b4abf80f-8f99-4e63-ad20-0638f87206df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342438343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2342438343
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1344895279
Short name T404
Test name
Test status
Simulation time 2398401838 ps
CPU time 3.35 seconds
Started Jun 24 05:50:06 PM PDT 24
Finished Jun 24 05:50:10 PM PDT 24
Peak memory 183892 kb
Host smart-b18788b2-56e8-4a10-997c-8b1df05908b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344895279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1344895279
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1365658042
Short name T289
Test name
Test status
Simulation time 449580511 ps
CPU time 2.05 seconds
Started Jun 24 05:50:09 PM PDT 24
Finished Jun 24 05:50:12 PM PDT 24
Peak memory 198476 kb
Host smart-60228995-5411-488b-8706-4c271fefee8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365658042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1365658042
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2969975821
Short name T357
Test name
Test status
Simulation time 4264149434 ps
CPU time 7.85 seconds
Started Jun 24 05:50:09 PM PDT 24
Finished Jun 24 05:50:18 PM PDT 24
Peak memory 197968 kb
Host smart-17b9a969-3202-4793-9a82-85f8690f2084
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969975821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2969975821
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3349075337
Short name T384
Test name
Test status
Simulation time 492209039 ps
CPU time 1.35 seconds
Started Jun 24 05:50:19 PM PDT 24
Finished Jun 24 05:50:22 PM PDT 24
Peak memory 193344 kb
Host smart-d9afa5b7-455e-4832-b6fd-78c9754279bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349075337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3349075337
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4138621111
Short name T371
Test name
Test status
Simulation time 7200467471 ps
CPU time 3.5 seconds
Started Jun 24 05:50:16 PM PDT 24
Finished Jun 24 05:50:21 PM PDT 24
Peak memory 196072 kb
Host smart-9d52adcc-f792-4339-9604-7b99651fd5bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138621111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.4138621111
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1473161321
Short name T334
Test name
Test status
Simulation time 1305410272 ps
CPU time 2.13 seconds
Started Jun 24 05:50:17 PM PDT 24
Finished Jun 24 05:50:21 PM PDT 24
Peak memory 192812 kb
Host smart-729c23cc-d8cf-40fc-a6a8-15826bc818b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473161321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1473161321
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1939715683
Short name T406
Test name
Test status
Simulation time 431486450 ps
CPU time 0.83 seconds
Started Jun 24 05:50:17 PM PDT 24
Finished Jun 24 05:50:19 PM PDT 24
Peak memory 195828 kb
Host smart-108cc669-fd67-429d-9cdb-3dfc19d48b4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939715683 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1939715683
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3852915267
Short name T370
Test name
Test status
Simulation time 581306510 ps
CPU time 0.78 seconds
Started Jun 24 05:50:17 PM PDT 24
Finished Jun 24 05:50:20 PM PDT 24
Peak memory 193312 kb
Host smart-a89c386c-b5cf-461c-bc16-9455e7446c6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852915267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3852915267
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1970690634
Short name T310
Test name
Test status
Simulation time 530801735 ps
CPU time 0.76 seconds
Started Jun 24 05:50:17 PM PDT 24
Finished Jun 24 05:50:20 PM PDT 24
Peak memory 183604 kb
Host smart-badc8d6f-ed75-485e-af2d-bf0c5912f7e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970690634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1970690634
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1129304689
Short name T356
Test name
Test status
Simulation time 288742389 ps
CPU time 0.86 seconds
Started Jun 24 05:50:16 PM PDT 24
Finished Jun 24 05:50:18 PM PDT 24
Peak memory 183524 kb
Host smart-292fc82e-64d7-4a58-ae7d-cc46fc6c22d8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129304689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1129304689
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3620373070
Short name T326
Test name
Test status
Simulation time 446596041 ps
CPU time 0.63 seconds
Started Jun 24 05:50:16 PM PDT 24
Finished Jun 24 05:50:17 PM PDT 24
Peak memory 183512 kb
Host smart-052fa96b-0158-4143-b045-93a28b02015c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620373070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3620373070
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3335634567
Short name T424
Test name
Test status
Simulation time 2067563673 ps
CPU time 1.85 seconds
Started Jun 24 05:50:16 PM PDT 24
Finished Jun 24 05:50:20 PM PDT 24
Peak memory 191868 kb
Host smart-6308a1cc-ce99-4611-8cf8-8ee9726c0e50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335634567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3335634567
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2591557894
Short name T314
Test name
Test status
Simulation time 515008791 ps
CPU time 3.09 seconds
Started Jun 24 05:50:07 PM PDT 24
Finished Jun 24 05:50:10 PM PDT 24
Peak memory 198464 kb
Host smart-e4881196-fb83-4216-a643-3dd50bdedf18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591557894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2591557894
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2180852561
Short name T196
Test name
Test status
Simulation time 4297193860 ps
CPU time 2.32 seconds
Started Jun 24 05:50:08 PM PDT 24
Finished Jun 24 05:50:11 PM PDT 24
Peak memory 197664 kb
Host smart-764f9cfc-f75f-4424-9fe4-1f3e8bc464df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180852561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2180852561
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2987911387
Short name T31
Test name
Test status
Simulation time 622073812 ps
CPU time 1.66 seconds
Started Jun 24 05:50:47 PM PDT 24
Finished Jun 24 05:50:50 PM PDT 24
Peak memory 196640 kb
Host smart-c32aec91-3cbd-4bc7-a34d-298a027353bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987911387 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2987911387
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.948724853
Short name T374
Test name
Test status
Simulation time 313674031 ps
CPU time 0.8 seconds
Started Jun 24 05:50:49 PM PDT 24
Finished Jun 24 05:50:50 PM PDT 24
Peak memory 192936 kb
Host smart-cfd20e90-e718-442b-8c25-5abfbaef2e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948724853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.948724853
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2811899288
Short name T412
Test name
Test status
Simulation time 391807028 ps
CPU time 0.82 seconds
Started Jun 24 05:50:44 PM PDT 24
Finished Jun 24 05:50:45 PM PDT 24
Peak memory 183600 kb
Host smart-b24f36d8-a900-400b-b8d7-1d803019585b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811899288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2811899288
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3861581107
Short name T71
Test name
Test status
Simulation time 2072773810 ps
CPU time 5.51 seconds
Started Jun 24 05:50:47 PM PDT 24
Finished Jun 24 05:50:54 PM PDT 24
Peak memory 193892 kb
Host smart-d78845da-3cf9-45ff-b414-95eec0287d89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861581107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3861581107
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2007593647
Short name T346
Test name
Test status
Simulation time 512110923 ps
CPU time 1.87 seconds
Started Jun 24 05:50:46 PM PDT 24
Finished Jun 24 05:50:50 PM PDT 24
Peak memory 198448 kb
Host smart-ddf9f968-2d65-4890-98ea-6988614bd4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007593647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2007593647
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1802898430
Short name T332
Test name
Test status
Simulation time 568852046 ps
CPU time 1.03 seconds
Started Jun 24 05:50:49 PM PDT 24
Finished Jun 24 05:50:51 PM PDT 24
Peak memory 197060 kb
Host smart-14699f7b-1ec1-4044-b027-db263f8ee709
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802898430 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1802898430
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1785612507
Short name T61
Test name
Test status
Simulation time 558234958 ps
CPU time 1.44 seconds
Started Jun 24 05:50:46 PM PDT 24
Finished Jun 24 05:50:49 PM PDT 24
Peak memory 193840 kb
Host smart-8671e915-97b9-4901-80f7-8570fd8cdeb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785612507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1785612507
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1066771881
Short name T368
Test name
Test status
Simulation time 560427650 ps
CPU time 0.69 seconds
Started Jun 24 05:50:47 PM PDT 24
Finished Jun 24 05:50:49 PM PDT 24
Peak memory 183584 kb
Host smart-c9b998af-167b-4bae-b51f-47478b45ea4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066771881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1066771881
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3467857990
Short name T380
Test name
Test status
Simulation time 1909513482 ps
CPU time 1.59 seconds
Started Jun 24 05:50:46 PM PDT 24
Finished Jun 24 05:50:49 PM PDT 24
Peak memory 193920 kb
Host smart-00a326ae-90ef-4a10-a2d1-abb8bca77431
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467857990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3467857990
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3413330118
Short name T290
Test name
Test status
Simulation time 431347591 ps
CPU time 1.71 seconds
Started Jun 24 05:50:44 PM PDT 24
Finished Jun 24 05:50:47 PM PDT 24
Peak memory 198468 kb
Host smart-782c812b-65f8-4522-9ead-97d76af634ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413330118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3413330118
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1422192976
Short name T30
Test name
Test status
Simulation time 8129254927 ps
CPU time 13.46 seconds
Started Jun 24 05:50:44 PM PDT 24
Finished Jun 24 05:50:59 PM PDT 24
Peak memory 197984 kb
Host smart-99bd4deb-2bbf-4362-9f5d-604f75787801
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422192976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1422192976
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.616046210
Short name T316
Test name
Test status
Simulation time 389291628 ps
CPU time 1.23 seconds
Started Jun 24 05:50:48 PM PDT 24
Finished Jun 24 05:50:50 PM PDT 24
Peak memory 195996 kb
Host smart-1ad5ba91-c847-4c21-bf6e-9e5e7d84a5ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616046210 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.616046210
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2025834887
Short name T304
Test name
Test status
Simulation time 515721298 ps
CPU time 0.68 seconds
Started Jun 24 05:50:46 PM PDT 24
Finished Jun 24 05:50:49 PM PDT 24
Peak memory 191872 kb
Host smart-4c4cfc2e-10f2-420a-a022-d34cbd8629f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025834887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2025834887
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4129177389
Short name T349
Test name
Test status
Simulation time 488516188 ps
CPU time 1.3 seconds
Started Jun 24 05:50:46 PM PDT 24
Finished Jun 24 05:50:49 PM PDT 24
Peak memory 192808 kb
Host smart-dc95e7a9-8eb4-4bcf-a314-460f251be00b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129177389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.4129177389
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.322160885
Short name T72
Test name
Test status
Simulation time 851363237 ps
CPU time 0.99 seconds
Started Jun 24 05:50:46 PM PDT 24
Finished Jun 24 05:50:48 PM PDT 24
Peak memory 193408 kb
Host smart-cd3dbb82-449b-4c04-987c-827c3e6ba192
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322160885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.322160885
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1013540539
Short name T402
Test name
Test status
Simulation time 708161690 ps
CPU time 2.62 seconds
Started Jun 24 05:50:48 PM PDT 24
Finished Jun 24 05:50:51 PM PDT 24
Peak memory 198468 kb
Host smart-2e1e43e5-99aa-4207-bac3-762e6c2951ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013540539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1013540539
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.361615567
Short name T389
Test name
Test status
Simulation time 508454791 ps
CPU time 0.94 seconds
Started Jun 24 05:50:45 PM PDT 24
Finished Jun 24 05:50:47 PM PDT 24
Peak memory 195852 kb
Host smart-1fc3f620-3341-4e6b-bade-1246670dc284
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361615567 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.361615567
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.827791713
Short name T53
Test name
Test status
Simulation time 532912139 ps
CPU time 0.77 seconds
Started Jun 24 05:50:44 PM PDT 24
Finished Jun 24 05:50:46 PM PDT 24
Peak memory 193224 kb
Host smart-807eb3ca-4948-4489-81f1-9a2fa3e169b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827791713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.827791713
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3357757659
Short name T422
Test name
Test status
Simulation time 398843990 ps
CPU time 1.15 seconds
Started Jun 24 05:50:46 PM PDT 24
Finished Jun 24 05:50:48 PM PDT 24
Peak memory 183604 kb
Host smart-077e0e11-cc94-4f7d-9c11-4285f40789f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357757659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3357757659
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2191984514
Short name T75
Test name
Test status
Simulation time 1831306138 ps
CPU time 1.51 seconds
Started Jun 24 05:50:46 PM PDT 24
Finished Jun 24 05:50:49 PM PDT 24
Peak memory 194468 kb
Host smart-d462ce14-1975-47f3-b28f-f450e787dcfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191984514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2191984514
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2511783008
Short name T391
Test name
Test status
Simulation time 399471065 ps
CPU time 1.72 seconds
Started Jun 24 05:50:47 PM PDT 24
Finished Jun 24 05:50:50 PM PDT 24
Peak memory 198304 kb
Host smart-c24ee2db-28de-4e6b-8c1c-775dd3ee0c84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511783008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2511783008
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2415935909
Short name T198
Test name
Test status
Simulation time 8297100614 ps
CPU time 4.73 seconds
Started Jun 24 05:50:47 PM PDT 24
Finished Jun 24 05:50:53 PM PDT 24
Peak memory 198112 kb
Host smart-5230a43c-bd9d-4377-9aa7-d36357559b82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415935909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2415935909
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2348277643
Short name T299
Test name
Test status
Simulation time 347653694 ps
CPU time 0.8 seconds
Started Jun 24 05:50:54 PM PDT 24
Finished Jun 24 05:50:55 PM PDT 24
Peak memory 195704 kb
Host smart-2b01c83d-5b0c-4680-8273-0072e6f5a91d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348277643 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2348277643
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2453321107
Short name T74
Test name
Test status
Simulation time 476897721 ps
CPU time 0.78 seconds
Started Jun 24 05:50:55 PM PDT 24
Finished Jun 24 05:50:56 PM PDT 24
Peak memory 192816 kb
Host smart-db2fb5a0-9d21-481d-bcdb-72dd9c936a1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453321107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2453321107
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.510516690
Short name T385
Test name
Test status
Simulation time 556016650 ps
CPU time 0.67 seconds
Started Jun 24 05:50:56 PM PDT 24
Finished Jun 24 05:50:59 PM PDT 24
Peak memory 183608 kb
Host smart-741cac94-93d2-46f2-9a74-d54864b07e34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510516690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.510516690
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2348219770
Short name T78
Test name
Test status
Simulation time 2527483854 ps
CPU time 3.87 seconds
Started Jun 24 05:50:54 PM PDT 24
Finished Jun 24 05:50:59 PM PDT 24
Peak memory 193856 kb
Host smart-1f0cb473-a890-40fc-83ca-643d12336daa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348219770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2348219770
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3218642842
Short name T362
Test name
Test status
Simulation time 891298852 ps
CPU time 2.43 seconds
Started Jun 24 05:50:45 PM PDT 24
Finished Jun 24 05:50:48 PM PDT 24
Peak memory 198412 kb
Host smart-9cb8aa64-bffd-496d-ad14-6303edd3b7fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218642842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3218642842
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4172977689
Short name T197
Test name
Test status
Simulation time 7761278083 ps
CPU time 5.63 seconds
Started Jun 24 05:50:44 PM PDT 24
Finished Jun 24 05:50:51 PM PDT 24
Peak memory 197996 kb
Host smart-36dc9003-7cc7-42eb-8812-863f11bf008b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172977689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.4172977689
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2452707862
Short name T381
Test name
Test status
Simulation time 464999204 ps
CPU time 1.02 seconds
Started Jun 24 05:50:57 PM PDT 24
Finished Jun 24 05:50:59 PM PDT 24
Peak memory 197976 kb
Host smart-971544f8-ed17-4675-9769-250469ae96e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452707862 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2452707862
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1792236875
Short name T420
Test name
Test status
Simulation time 350414693 ps
CPU time 0.7 seconds
Started Jun 24 05:50:56 PM PDT 24
Finished Jun 24 05:50:58 PM PDT 24
Peak memory 192964 kb
Host smart-0e38622f-8002-4766-908c-337ff8c17f04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792236875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1792236875
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4294017783
Short name T394
Test name
Test status
Simulation time 406009527 ps
CPU time 0.7 seconds
Started Jun 24 05:50:56 PM PDT 24
Finished Jun 24 05:50:59 PM PDT 24
Peak memory 183608 kb
Host smart-10dd6c63-df55-40ff-9048-f35c17f9d55d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294017783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.4294017783
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1117928063
Short name T351
Test name
Test status
Simulation time 2285581420 ps
CPU time 1.43 seconds
Started Jun 24 05:50:54 PM PDT 24
Finished Jun 24 05:50:56 PM PDT 24
Peak memory 194644 kb
Host smart-70e5b796-44d7-4a58-9b6e-42ebe1738f74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117928063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1117928063
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2479496212
Short name T414
Test name
Test status
Simulation time 899552275 ps
CPU time 2.57 seconds
Started Jun 24 05:50:56 PM PDT 24
Finished Jun 24 05:51:00 PM PDT 24
Peak memory 198436 kb
Host smart-60fe3870-eb49-4db9-a96e-8bed07d5d413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479496212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2479496212
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.651446094
Short name T403
Test name
Test status
Simulation time 4368840296 ps
CPU time 4.25 seconds
Started Jun 24 05:50:56 PM PDT 24
Finished Jun 24 05:51:02 PM PDT 24
Peak memory 197660 kb
Host smart-9a1bce43-f641-4e7d-ba28-e978413ad499
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651446094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.651446094
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3130361745
Short name T307
Test name
Test status
Simulation time 446198372 ps
CPU time 0.93 seconds
Started Jun 24 05:50:56 PM PDT 24
Finished Jun 24 05:50:58 PM PDT 24
Peak memory 195876 kb
Host smart-730cd50f-ba8b-4d81-ad88-2867591b5eac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130361745 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3130361745
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.230592576
Short name T294
Test name
Test status
Simulation time 290157805 ps
CPU time 0.76 seconds
Started Jun 24 05:50:53 PM PDT 24
Finished Jun 24 05:50:55 PM PDT 24
Peak memory 192932 kb
Host smart-d048fb74-462c-4e38-ac42-0a9c080586d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230592576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.230592576
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3352866845
Short name T417
Test name
Test status
Simulation time 406232834 ps
CPU time 0.66 seconds
Started Jun 24 05:50:56 PM PDT 24
Finished Jun 24 05:50:58 PM PDT 24
Peak memory 183572 kb
Host smart-c78c77d3-3dc1-4d72-8b7f-d534132c9e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352866845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3352866845
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2108691282
Short name T377
Test name
Test status
Simulation time 2591851699 ps
CPU time 1.67 seconds
Started Jun 24 05:50:56 PM PDT 24
Finished Jun 24 05:50:59 PM PDT 24
Peak memory 193884 kb
Host smart-4a8649f1-1648-4485-b36f-f8f41eb254d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108691282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2108691282
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2965269986
Short name T369
Test name
Test status
Simulation time 563017571 ps
CPU time 2.21 seconds
Started Jun 24 05:50:56 PM PDT 24
Finished Jun 24 05:51:00 PM PDT 24
Peak memory 198464 kb
Host smart-d0032249-391b-4441-8f06-39b5576b071b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965269986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2965269986
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2865957437
Short name T360
Test name
Test status
Simulation time 4183242217 ps
CPU time 7.09 seconds
Started Jun 24 05:50:56 PM PDT 24
Finished Jun 24 05:51:05 PM PDT 24
Peak memory 197772 kb
Host smart-3a4b24e3-8494-4087-844b-d34d03806628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865957437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2865957437
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3678778244
Short name T382
Test name
Test status
Simulation time 589113209 ps
CPU time 1.06 seconds
Started Jun 24 05:51:05 PM PDT 24
Finished Jun 24 05:51:07 PM PDT 24
Peak memory 196392 kb
Host smart-7b7fa01a-4b60-48b6-85eb-71646a0c106c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678778244 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3678778244
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1009363953
Short name T416
Test name
Test status
Simulation time 317757117 ps
CPU time 0.81 seconds
Started Jun 24 05:50:56 PM PDT 24
Finished Jun 24 05:50:58 PM PDT 24
Peak memory 192824 kb
Host smart-a6cd8552-43a1-4e3a-82fa-d1885c5b0eb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009363953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1009363953
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.80267897
Short name T323
Test name
Test status
Simulation time 298183538 ps
CPU time 0.74 seconds
Started Jun 24 05:50:57 PM PDT 24
Finished Jun 24 05:50:59 PM PDT 24
Peak memory 192768 kb
Host smart-41c9ef22-35b3-4364-8bf4-cb9a33fb32c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80267897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.80267897
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.699735575
Short name T77
Test name
Test status
Simulation time 1313779319 ps
CPU time 1.33 seconds
Started Jun 24 05:50:54 PM PDT 24
Finished Jun 24 05:50:56 PM PDT 24
Peak memory 183844 kb
Host smart-62f773d0-d224-433d-8b84-93f2e1d26786
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699735575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.699735575
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.776395595
Short name T342
Test name
Test status
Simulation time 617404170 ps
CPU time 1.75 seconds
Started Jun 24 05:50:55 PM PDT 24
Finished Jun 24 05:50:58 PM PDT 24
Peak memory 198488 kb
Host smart-401d85c4-0969-4255-91e2-042030a53c08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776395595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.776395595
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2160890033
Short name T365
Test name
Test status
Simulation time 9062817693 ps
CPU time 3.78 seconds
Started Jun 24 05:50:56 PM PDT 24
Finished Jun 24 05:51:02 PM PDT 24
Peak memory 198136 kb
Host smart-844f710e-4804-4f46-81b8-1030674941b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160890033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2160890033
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3061094235
Short name T295
Test name
Test status
Simulation time 494465726 ps
CPU time 0.9 seconds
Started Jun 24 05:51:05 PM PDT 24
Finished Jun 24 05:51:07 PM PDT 24
Peak memory 197160 kb
Host smart-022f22cb-73de-4ad9-9bc4-a07e949cf2ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061094235 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3061094235
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2902875483
Short name T408
Test name
Test status
Simulation time 446250319 ps
CPU time 0.95 seconds
Started Jun 24 05:51:04 PM PDT 24
Finished Jun 24 05:51:06 PM PDT 24
Peak memory 193028 kb
Host smart-a0244593-8c53-4d8e-a2b4-dc6e8c55fa6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902875483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2902875483
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2542731714
Short name T366
Test name
Test status
Simulation time 469546497 ps
CPU time 1.02 seconds
Started Jun 24 05:51:04 PM PDT 24
Finished Jun 24 05:51:06 PM PDT 24
Peak memory 183492 kb
Host smart-3e8e541a-5061-4f07-a4b2-157c2c1c691f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542731714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2542731714
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1892437158
Short name T376
Test name
Test status
Simulation time 1273355618 ps
CPU time 1.12 seconds
Started Jun 24 05:51:07 PM PDT 24
Finished Jun 24 05:51:10 PM PDT 24
Peak memory 193388 kb
Host smart-cac87e89-e62b-46f2-b799-147a0b1e7f7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892437158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1892437158
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3380308286
Short name T318
Test name
Test status
Simulation time 527572036 ps
CPU time 1.12 seconds
Started Jun 24 05:51:15 PM PDT 24
Finished Jun 24 05:51:18 PM PDT 24
Peak memory 197128 kb
Host smart-798f31d6-8a1c-4071-8677-58a24c246e59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380308286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3380308286
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.151121768
Short name T312
Test name
Test status
Simulation time 4286575216 ps
CPU time 7.45 seconds
Started Jun 24 05:51:14 PM PDT 24
Finished Jun 24 05:51:23 PM PDT 24
Peak memory 197500 kb
Host smart-251f23ab-b916-4e0c-92a7-8a6a917411d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151121768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.151121768
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3131799935
Short name T352
Test name
Test status
Simulation time 427674648 ps
CPU time 0.77 seconds
Started Jun 24 05:51:05 PM PDT 24
Finished Jun 24 05:51:07 PM PDT 24
Peak memory 195128 kb
Host smart-1acb8d84-5230-49f6-ac71-e650ed9348c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131799935 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3131799935
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4100955991
Short name T324
Test name
Test status
Simulation time 354041809 ps
CPU time 1.01 seconds
Started Jun 24 05:51:07 PM PDT 24
Finished Jun 24 05:51:10 PM PDT 24
Peak memory 191860 kb
Host smart-cb3a88f2-81e1-4e26-8afc-796e56129740
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100955991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.4100955991
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1269779159
Short name T341
Test name
Test status
Simulation time 424147769 ps
CPU time 0.6 seconds
Started Jun 24 05:51:02 PM PDT 24
Finished Jun 24 05:51:03 PM PDT 24
Peak memory 192792 kb
Host smart-b07bafdb-73d2-4c0f-a362-0463e176d151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269779159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1269779159
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1405521757
Short name T340
Test name
Test status
Simulation time 2670421760 ps
CPU time 1.6 seconds
Started Jun 24 05:51:03 PM PDT 24
Finished Jun 24 05:51:06 PM PDT 24
Peak memory 195052 kb
Host smart-7359a7ad-083f-41fa-a458-47138cbb84f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405521757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1405521757
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3155878234
Short name T308
Test name
Test status
Simulation time 719024253 ps
CPU time 2.89 seconds
Started Jun 24 05:51:06 PM PDT 24
Finished Jun 24 05:51:10 PM PDT 24
Peak memory 198464 kb
Host smart-55f2f0bd-f2fa-43b9-8ff1-01ccd476710b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155878234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3155878234
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.28575273
Short name T375
Test name
Test status
Simulation time 7781270490 ps
CPU time 4.38 seconds
Started Jun 24 05:51:06 PM PDT 24
Finished Jun 24 05:51:13 PM PDT 24
Peak memory 198264 kb
Host smart-61090693-7362-45e5-aceb-a259db7066b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28575273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_
intg_err.28575273
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2904178228
Short name T57
Test name
Test status
Simulation time 641071326 ps
CPU time 0.98 seconds
Started Jun 24 05:50:17 PM PDT 24
Finished Jun 24 05:50:19 PM PDT 24
Peak memory 194408 kb
Host smart-227a9174-c9be-4e0f-8aee-82010a38f5c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904178228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2904178228
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2301816424
Short name T372
Test name
Test status
Simulation time 7435439762 ps
CPU time 3.61 seconds
Started Jun 24 05:50:18 PM PDT 24
Finished Jun 24 05:50:23 PM PDT 24
Peak memory 192032 kb
Host smart-777a96a3-6a8c-4000-acd0-2fc3d94b412a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301816424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2301816424
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4138735790
Short name T345
Test name
Test status
Simulation time 939115071 ps
CPU time 0.76 seconds
Started Jun 24 05:50:19 PM PDT 24
Finished Jun 24 05:50:21 PM PDT 24
Peak memory 183604 kb
Host smart-9874cd39-cffc-4e75-9d88-eee21f0eb02e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138735790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.4138735790
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1141654941
Short name T395
Test name
Test status
Simulation time 537286200 ps
CPU time 1.02 seconds
Started Jun 24 05:50:28 PM PDT 24
Finished Jun 24 05:50:30 PM PDT 24
Peak memory 195576 kb
Host smart-8bc2abe7-091d-4494-bc8d-aedfeecee545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141654941 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1141654941
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1505846521
Short name T328
Test name
Test status
Simulation time 444737655 ps
CPU time 0.86 seconds
Started Jun 24 05:50:19 PM PDT 24
Finished Jun 24 05:50:21 PM PDT 24
Peak memory 193072 kb
Host smart-b1bf8c24-adb1-4f41-aa99-25328cfb89ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505846521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1505846521
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.576766974
Short name T400
Test name
Test status
Simulation time 420161018 ps
CPU time 0.68 seconds
Started Jun 24 05:50:17 PM PDT 24
Finished Jun 24 05:50:19 PM PDT 24
Peak memory 183576 kb
Host smart-295a3df3-3c2d-40cf-a545-23ec5e2175ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576766974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.576766974
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.818196449
Short name T413
Test name
Test status
Simulation time 544205368 ps
CPU time 0.57 seconds
Started Jun 24 05:50:18 PM PDT 24
Finished Jun 24 05:50:20 PM PDT 24
Peak memory 183536 kb
Host smart-02b27795-6cb2-45ab-8a06-3912ec9aac42
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818196449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.818196449
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.317753163
Short name T302
Test name
Test status
Simulation time 327070601 ps
CPU time 0.93 seconds
Started Jun 24 05:50:16 PM PDT 24
Finished Jun 24 05:50:19 PM PDT 24
Peak memory 183540 kb
Host smart-9be029d8-2292-4db0-bfc7-64e0cb918664
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317753163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.317753163
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1356646871
Short name T418
Test name
Test status
Simulation time 2142867845 ps
CPU time 1.61 seconds
Started Jun 24 05:50:16 PM PDT 24
Finished Jun 24 05:50:19 PM PDT 24
Peak memory 193860 kb
Host smart-19470402-6571-4ee9-8193-5a7377f9a188
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356646871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1356646871
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3200174259
Short name T396
Test name
Test status
Simulation time 425541284 ps
CPU time 2.66 seconds
Started Jun 24 05:50:16 PM PDT 24
Finished Jun 24 05:50:20 PM PDT 24
Peak memory 198416 kb
Host smart-6c20d558-b2cf-46d6-afa2-cb32ed88ec94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200174259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3200174259
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1919799757
Short name T303
Test name
Test status
Simulation time 4422929852 ps
CPU time 3.23 seconds
Started Jun 24 05:50:17 PM PDT 24
Finished Jun 24 05:50:21 PM PDT 24
Peak memory 197708 kb
Host smart-23df0661-4085-433b-9e95-b03f251351cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919799757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1919799757
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.910992794
Short name T319
Test name
Test status
Simulation time 455470871 ps
CPU time 0.68 seconds
Started Jun 24 05:51:06 PM PDT 24
Finished Jun 24 05:51:08 PM PDT 24
Peak memory 183600 kb
Host smart-352af4d4-e6d6-4fed-a8e3-b43bc0e593c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910992794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.910992794
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3893056082
Short name T300
Test name
Test status
Simulation time 517717353 ps
CPU time 1.34 seconds
Started Jun 24 05:51:05 PM PDT 24
Finished Jun 24 05:51:07 PM PDT 24
Peak memory 183604 kb
Host smart-4508b039-7fde-425c-9f70-d291cee42716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893056082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3893056082
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1241069121
Short name T388
Test name
Test status
Simulation time 532518054 ps
CPU time 0.75 seconds
Started Jun 24 05:51:03 PM PDT 24
Finished Jun 24 05:51:05 PM PDT 24
Peak memory 183608 kb
Host smart-6fbd6173-3d3d-446e-b965-d59f032f0973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241069121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1241069121
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.851812305
Short name T298
Test name
Test status
Simulation time 490392498 ps
CPU time 1.17 seconds
Started Jun 24 05:51:07 PM PDT 24
Finished Jun 24 05:51:10 PM PDT 24
Peak memory 192828 kb
Host smart-96147d3a-09fb-4364-8335-810b72224f3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851812305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.851812305
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3013967255
Short name T292
Test name
Test status
Simulation time 462221600 ps
CPU time 0.92 seconds
Started Jun 24 05:51:15 PM PDT 24
Finished Jun 24 05:51:18 PM PDT 24
Peak memory 191912 kb
Host smart-23aa1b9c-476b-47e5-a5b3-2c1388db9c87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013967255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3013967255
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.967929866
Short name T415
Test name
Test status
Simulation time 434506660 ps
CPU time 1.22 seconds
Started Jun 24 05:51:06 PM PDT 24
Finished Jun 24 05:51:09 PM PDT 24
Peak memory 183604 kb
Host smart-ad8ac9d2-543c-4450-b56d-077e87b499d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967929866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.967929866
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4057513066
Short name T421
Test name
Test status
Simulation time 474478544 ps
CPU time 1.2 seconds
Started Jun 24 05:51:06 PM PDT 24
Finished Jun 24 05:51:08 PM PDT 24
Peak memory 192820 kb
Host smart-eef3ad34-81c2-4e4e-94c7-77a09344a960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057513066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4057513066
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.675442491
Short name T383
Test name
Test status
Simulation time 303552294 ps
CPU time 0.8 seconds
Started Jun 24 05:51:04 PM PDT 24
Finished Jun 24 05:51:06 PM PDT 24
Peak memory 183604 kb
Host smart-d5273662-d340-4750-b36f-28953b45beab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675442491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.675442491
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3539682988
Short name T390
Test name
Test status
Simulation time 335574097 ps
CPU time 0.79 seconds
Started Jun 24 05:51:04 PM PDT 24
Finished Jun 24 05:51:06 PM PDT 24
Peak memory 183580 kb
Host smart-1f22daca-d72e-478f-bc5b-37603d41d1ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539682988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3539682988
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1701704345
Short name T285
Test name
Test status
Simulation time 503881312 ps
CPU time 0.87 seconds
Started Jun 24 05:51:07 PM PDT 24
Finished Jun 24 05:51:10 PM PDT 24
Peak memory 183804 kb
Host smart-7f44bdd8-efbd-46a3-b765-e4fbc462ad3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701704345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1701704345
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1077094015
Short name T54
Test name
Test status
Simulation time 638086572 ps
CPU time 1.02 seconds
Started Jun 24 05:50:29 PM PDT 24
Finished Jun 24 05:50:31 PM PDT 24
Peak memory 193820 kb
Host smart-c42830c9-025b-4403-be79-ef1bcadbc5dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077094015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1077094015
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2842270583
Short name T52
Test name
Test status
Simulation time 10425690789 ps
CPU time 13.64 seconds
Started Jun 24 05:50:28 PM PDT 24
Finished Jun 24 05:50:42 PM PDT 24
Peak memory 195164 kb
Host smart-8344dc94-3c29-4204-a64f-6918c3b06841
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842270583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2842270583
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3102519108
Short name T51
Test name
Test status
Simulation time 1333325387 ps
CPU time 0.83 seconds
Started Jun 24 05:50:27 PM PDT 24
Finished Jun 24 05:50:28 PM PDT 24
Peak memory 192952 kb
Host smart-11398a9d-9d60-4bd1-b0f9-1af27aa0ce7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102519108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3102519108
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1745215105
Short name T392
Test name
Test status
Simulation time 539113790 ps
CPU time 1.45 seconds
Started Jun 24 05:50:29 PM PDT 24
Finished Jun 24 05:50:32 PM PDT 24
Peak memory 196128 kb
Host smart-220548ca-a055-407d-9eee-9897701cde44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745215105 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1745215105
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2855814113
Short name T55
Test name
Test status
Simulation time 469397507 ps
CPU time 1.19 seconds
Started Jun 24 05:50:30 PM PDT 24
Finished Jun 24 05:50:32 PM PDT 24
Peak memory 192804 kb
Host smart-f00075fa-78fe-43f9-be35-3f64331336e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855814113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2855814113
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1855352221
Short name T309
Test name
Test status
Simulation time 504883936 ps
CPU time 0.86 seconds
Started Jun 24 05:50:27 PM PDT 24
Finished Jun 24 05:50:29 PM PDT 24
Peak memory 192808 kb
Host smart-4c212851-3846-42bb-965f-18ca659b3183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855352221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1855352221
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2802750810
Short name T343
Test name
Test status
Simulation time 315427355 ps
CPU time 0.78 seconds
Started Jun 24 05:50:30 PM PDT 24
Finished Jun 24 05:50:32 PM PDT 24
Peak memory 183528 kb
Host smart-5b096140-6207-4661-8c3a-d16edd7fce2f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802750810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2802750810
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1102075124
Short name T367
Test name
Test status
Simulation time 502520969 ps
CPU time 0.71 seconds
Started Jun 24 05:50:29 PM PDT 24
Finished Jun 24 05:50:31 PM PDT 24
Peak memory 183532 kb
Host smart-b177cb9a-2e8b-4a78-b334-15a9a08b703f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102075124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1102075124
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1293735937
Short name T73
Test name
Test status
Simulation time 1411389606 ps
CPU time 1 seconds
Started Jun 24 05:50:27 PM PDT 24
Finished Jun 24 05:50:29 PM PDT 24
Peak memory 192888 kb
Host smart-dbb63f88-461d-4e2d-bf87-1601845794b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293735937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1293735937
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1934908914
Short name T296
Test name
Test status
Simulation time 348638104 ps
CPU time 1.51 seconds
Started Jun 24 05:50:27 PM PDT 24
Finished Jun 24 05:50:30 PM PDT 24
Peak memory 198328 kb
Host smart-2e31fd93-c8cc-4575-82f2-c2ec9301b117
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934908914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1934908914
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.358723851
Short name T378
Test name
Test status
Simulation time 8949486113 ps
CPU time 8.05 seconds
Started Jun 24 05:50:31 PM PDT 24
Finished Jun 24 05:50:40 PM PDT 24
Peak memory 198120 kb
Host smart-1a153108-be17-441d-8fee-b067f6fa8270
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358723851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.358723851
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.75648527
Short name T393
Test name
Test status
Simulation time 450745745 ps
CPU time 1.22 seconds
Started Jun 24 05:51:04 PM PDT 24
Finished Jun 24 05:51:07 PM PDT 24
Peak memory 183604 kb
Host smart-afc49783-5395-4ad9-b3ea-fb60fc188abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75648527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.75648527
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1172206557
Short name T336
Test name
Test status
Simulation time 284913671 ps
CPU time 0.94 seconds
Started Jun 24 05:51:14 PM PDT 24
Finished Jun 24 05:51:17 PM PDT 24
Peak memory 183600 kb
Host smart-760a3aac-5fd3-4fdc-890e-83306555f32a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172206557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1172206557
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3096208392
Short name T419
Test name
Test status
Simulation time 311818254 ps
CPU time 1 seconds
Started Jun 24 05:51:06 PM PDT 24
Finished Jun 24 05:51:09 PM PDT 24
Peak memory 192824 kb
Host smart-ad11f26f-d451-4cea-8b7a-1615fa1b5673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096208392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3096208392
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.983355996
Short name T401
Test name
Test status
Simulation time 412552675 ps
CPU time 1.04 seconds
Started Jun 24 05:51:14 PM PDT 24
Finished Jun 24 05:51:17 PM PDT 24
Peak memory 183552 kb
Host smart-2d4c01fb-677d-4767-9829-a707b786caf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983355996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.983355996
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3824889680
Short name T410
Test name
Test status
Simulation time 405237159 ps
CPU time 0.65 seconds
Started Jun 24 05:51:06 PM PDT 24
Finished Jun 24 05:51:08 PM PDT 24
Peak memory 192824 kb
Host smart-162e682c-494d-4cde-9ada-0b11abb1f404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824889680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3824889680
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1723847060
Short name T344
Test name
Test status
Simulation time 473793169 ps
CPU time 0.71 seconds
Started Jun 24 05:51:06 PM PDT 24
Finished Jun 24 05:51:09 PM PDT 24
Peak memory 183600 kb
Host smart-182228a4-cfc5-4765-a0bf-35085c219e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723847060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1723847060
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3200584431
Short name T306
Test name
Test status
Simulation time 509239783 ps
CPU time 1.32 seconds
Started Jun 24 05:51:04 PM PDT 24
Finished Jun 24 05:51:07 PM PDT 24
Peak memory 183600 kb
Host smart-8701ac7a-fc70-4437-ab9a-e21c029c176d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200584431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3200584431
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1669987391
Short name T338
Test name
Test status
Simulation time 325187575 ps
CPU time 0.58 seconds
Started Jun 24 05:51:03 PM PDT 24
Finished Jun 24 05:51:05 PM PDT 24
Peak memory 183584 kb
Host smart-3651d661-16b6-4403-9ed1-291e8dbe6f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669987391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1669987391
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3379359090
Short name T337
Test name
Test status
Simulation time 424236884 ps
CPU time 1.16 seconds
Started Jun 24 05:51:05 PM PDT 24
Finished Jun 24 05:51:08 PM PDT 24
Peak memory 183600 kb
Host smart-9b22301d-f4c6-42c9-8218-7fce9dd915d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379359090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3379359090
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2966774713
Short name T301
Test name
Test status
Simulation time 437355776 ps
CPU time 0.71 seconds
Started Jun 24 05:51:06 PM PDT 24
Finished Jun 24 05:51:08 PM PDT 24
Peak memory 183600 kb
Host smart-0ca8b4b0-78ba-4815-878e-a297a9a496ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966774713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2966774713
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.554381468
Short name T70
Test name
Test status
Simulation time 391899522 ps
CPU time 0.97 seconds
Started Jun 24 05:50:26 PM PDT 24
Finished Jun 24 05:50:27 PM PDT 24
Peak memory 193824 kb
Host smart-743d1c58-acdd-4077-9ed5-5cdd1a87c47c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554381468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.554381468
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.312705068
Short name T305
Test name
Test status
Simulation time 7533113972 ps
CPU time 2.61 seconds
Started Jun 24 05:50:28 PM PDT 24
Finished Jun 24 05:50:32 PM PDT 24
Peak memory 192008 kb
Host smart-3a9c6300-ce5c-41aa-ad0c-68bf1c7fd8c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312705068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.312705068
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2020906197
Short name T49
Test name
Test status
Simulation time 1087855840 ps
CPU time 0.7 seconds
Started Jun 24 05:50:26 PM PDT 24
Finished Jun 24 05:50:28 PM PDT 24
Peak memory 193112 kb
Host smart-aebbf89b-207e-488d-a6dc-b17a4dc82cc8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020906197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2020906197
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.56743678
Short name T317
Test name
Test status
Simulation time 467671224 ps
CPU time 1.06 seconds
Started Jun 24 05:50:29 PM PDT 24
Finished Jun 24 05:50:31 PM PDT 24
Peak memory 195948 kb
Host smart-c6692606-205c-4c60-a208-ae042712065e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56743678 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.56743678
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2852979
Short name T373
Test name
Test status
Simulation time 402977904 ps
CPU time 0.88 seconds
Started Jun 24 05:50:32 PM PDT 24
Finished Jun 24 05:50:34 PM PDT 24
Peak memory 192772 kb
Host smart-aa8266f4-b834-4d22-af96-2b951e8a4a77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2852979
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3481219576
Short name T297
Test name
Test status
Simulation time 409160147 ps
CPU time 0.83 seconds
Started Jun 24 05:50:27 PM PDT 24
Finished Jun 24 05:50:28 PM PDT 24
Peak memory 183600 kb
Host smart-78a3b31c-5afd-4424-b220-ce51427c2966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481219576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3481219576
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4148228191
Short name T359
Test name
Test status
Simulation time 502245161 ps
CPU time 1.21 seconds
Started Jun 24 05:50:30 PM PDT 24
Finished Jun 24 05:50:32 PM PDT 24
Peak memory 183528 kb
Host smart-1b4a67e0-27a1-4df4-a997-9d6d538effac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148228191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.4148228191
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3173496313
Short name T335
Test name
Test status
Simulation time 441122225 ps
CPU time 1.14 seconds
Started Jun 24 05:50:26 PM PDT 24
Finished Jun 24 05:50:28 PM PDT 24
Peak memory 183540 kb
Host smart-9a785f5f-41a7-4ea1-9c4a-f33e841c6bd7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173496313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3173496313
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.613350149
Short name T329
Test name
Test status
Simulation time 2309759559 ps
CPU time 3.91 seconds
Started Jun 24 05:50:27 PM PDT 24
Finished Jun 24 05:50:32 PM PDT 24
Peak memory 192200 kb
Host smart-f05b72e6-d046-441c-b22b-d5abefb3119c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613350149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.613350149
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1716398335
Short name T315
Test name
Test status
Simulation time 394946641 ps
CPU time 1.99 seconds
Started Jun 24 05:50:32 PM PDT 24
Finished Jun 24 05:50:35 PM PDT 24
Peak memory 198476 kb
Host smart-62e7bc9a-9378-48cf-8012-94ec53abfe6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716398335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1716398335
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3760360465
Short name T195
Test name
Test status
Simulation time 4299181600 ps
CPU time 6.7 seconds
Started Jun 24 05:50:27 PM PDT 24
Finished Jun 24 05:50:34 PM PDT 24
Peak memory 197472 kb
Host smart-f1924bc9-eaf8-407f-aa09-765a8a93da8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760360465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3760360465
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2823831575
Short name T387
Test name
Test status
Simulation time 415833425 ps
CPU time 1.14 seconds
Started Jun 24 05:51:04 PM PDT 24
Finished Jun 24 05:51:06 PM PDT 24
Peak memory 193080 kb
Host smart-8a0859f0-b827-49d8-97bd-990d6357d767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823831575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2823831575
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3390136853
Short name T322
Test name
Test status
Simulation time 352051253 ps
CPU time 0.97 seconds
Started Jun 24 05:51:07 PM PDT 24
Finished Jun 24 05:51:10 PM PDT 24
Peak memory 183612 kb
Host smart-5973e441-6083-409d-8a67-8676d94b6fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390136853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3390136853
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2349843160
Short name T320
Test name
Test status
Simulation time 337418440 ps
CPU time 0.8 seconds
Started Jun 24 05:51:06 PM PDT 24
Finished Jun 24 05:51:08 PM PDT 24
Peak memory 192820 kb
Host smart-b9e55355-124b-491c-8647-e0c22cfe06d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349843160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2349843160
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3040140240
Short name T291
Test name
Test status
Simulation time 483762630 ps
CPU time 1.15 seconds
Started Jun 24 05:51:05 PM PDT 24
Finished Jun 24 05:51:07 PM PDT 24
Peak memory 183600 kb
Host smart-98d9d855-a34b-4610-b1de-93685096d8e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040140240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3040140240
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2706569799
Short name T354
Test name
Test status
Simulation time 442292173 ps
CPU time 0.69 seconds
Started Jun 24 05:51:08 PM PDT 24
Finished Jun 24 05:51:10 PM PDT 24
Peak memory 193068 kb
Host smart-d5117bd7-2d2c-45f0-8e49-667aeb7fc18e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706569799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2706569799
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3527695862
Short name T423
Test name
Test status
Simulation time 389766348 ps
CPU time 0.64 seconds
Started Jun 24 05:51:07 PM PDT 24
Finished Jun 24 05:51:10 PM PDT 24
Peak memory 183600 kb
Host smart-f4e3201f-9b46-46e0-a081-9447c5531441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527695862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3527695862
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1407095496
Short name T399
Test name
Test status
Simulation time 418196245 ps
CPU time 0.72 seconds
Started Jun 24 05:51:15 PM PDT 24
Finished Jun 24 05:51:17 PM PDT 24
Peak memory 192824 kb
Host smart-b19697b3-1af5-46b2-bc8f-e9fe5f763698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407095496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1407095496
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2151363600
Short name T325
Test name
Test status
Simulation time 393272541 ps
CPU time 1.19 seconds
Started Jun 24 05:51:06 PM PDT 24
Finished Jun 24 05:51:09 PM PDT 24
Peak memory 192816 kb
Host smart-918da880-97f1-4deb-b1ee-c4397832fbdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151363600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2151363600
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3541597659
Short name T379
Test name
Test status
Simulation time 418030613 ps
CPU time 0.68 seconds
Started Jun 24 05:51:08 PM PDT 24
Finished Jun 24 05:51:10 PM PDT 24
Peak memory 183840 kb
Host smart-1ec2f7da-aee6-4efd-97b9-61e176645dbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541597659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3541597659
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.441406882
Short name T405
Test name
Test status
Simulation time 427877636 ps
CPU time 0.92 seconds
Started Jun 24 05:51:06 PM PDT 24
Finished Jun 24 05:51:09 PM PDT 24
Peak memory 192820 kb
Host smart-6bc03d80-879b-4dbd-b632-98b1aba0db73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441406882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.441406882
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2351493099
Short name T339
Test name
Test status
Simulation time 773083353 ps
CPU time 1.14 seconds
Started Jun 24 05:50:39 PM PDT 24
Finished Jun 24 05:50:42 PM PDT 24
Peak memory 198308 kb
Host smart-f3c97f7a-5ff7-4915-8705-b5d6cfcc8a54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351493099 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2351493099
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2573420310
Short name T358
Test name
Test status
Simulation time 322610431 ps
CPU time 0.83 seconds
Started Jun 24 05:50:27 PM PDT 24
Finished Jun 24 05:50:29 PM PDT 24
Peak memory 193012 kb
Host smart-f6a87001-3bad-41ba-8cd9-b37815211102
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573420310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2573420310
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3909544428
Short name T311
Test name
Test status
Simulation time 427506307 ps
CPU time 0.71 seconds
Started Jun 24 05:50:31 PM PDT 24
Finished Jun 24 05:50:33 PM PDT 24
Peak memory 192836 kb
Host smart-7b586f5e-30d6-46b7-8bba-89a8ffcf057f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909544428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3909544428
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3437245459
Short name T386
Test name
Test status
Simulation time 1629954287 ps
CPU time 4.03 seconds
Started Jun 24 05:50:26 PM PDT 24
Finished Jun 24 05:50:31 PM PDT 24
Peak memory 193224 kb
Host smart-5198e308-16b3-4cff-825b-fcce8fb678dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437245459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3437245459
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1102852511
Short name T288
Test name
Test status
Simulation time 514865506 ps
CPU time 1.92 seconds
Started Jun 24 05:50:29 PM PDT 24
Finished Jun 24 05:50:32 PM PDT 24
Peak memory 198436 kb
Host smart-cf6942ee-e2a4-458d-9910-f0422aed8c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102852511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1102852511
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.36859263
Short name T361
Test name
Test status
Simulation time 4373340299 ps
CPU time 1.4 seconds
Started Jun 24 05:50:29 PM PDT 24
Finished Jun 24 05:50:31 PM PDT 24
Peak memory 196296 kb
Host smart-4cc9fb35-195b-4348-83be-45a9825dde5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_i
ntg_err.36859263
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3487927526
Short name T331
Test name
Test status
Simulation time 366336133 ps
CPU time 0.85 seconds
Started Jun 24 05:50:35 PM PDT 24
Finished Jun 24 05:50:37 PM PDT 24
Peak memory 195516 kb
Host smart-fba0deb6-4c94-47b9-9789-39158a8664a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487927526 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3487927526
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2319795926
Short name T293
Test name
Test status
Simulation time 356788627 ps
CPU time 0.96 seconds
Started Jun 24 05:50:36 PM PDT 24
Finished Jun 24 05:50:38 PM PDT 24
Peak memory 192816 kb
Host smart-0785eb82-3fdf-46af-988c-0182a185810d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319795926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2319795926
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1734800238
Short name T333
Test name
Test status
Simulation time 1486887431 ps
CPU time 2.6 seconds
Started Jun 24 05:50:37 PM PDT 24
Finished Jun 24 05:50:42 PM PDT 24
Peak memory 192916 kb
Host smart-23f8173d-2cb2-4614-a8f2-4507418bcaae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734800238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1734800238
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.317486999
Short name T327
Test name
Test status
Simulation time 343720288 ps
CPU time 1.56 seconds
Started Jun 24 05:50:38 PM PDT 24
Finished Jun 24 05:50:41 PM PDT 24
Peak memory 198444 kb
Host smart-4f4eb560-33c7-440f-9499-a2fe884a8e85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317486999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.317486999
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3338738090
Short name T192
Test name
Test status
Simulation time 8722068170 ps
CPU time 3.92 seconds
Started Jun 24 05:50:36 PM PDT 24
Finished Jun 24 05:50:41 PM PDT 24
Peak memory 198144 kb
Host smart-c1ab9c84-9b53-45bb-b410-82da762bf41d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338738090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3338738090
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.522483344
Short name T411
Test name
Test status
Simulation time 604216480 ps
CPU time 1.17 seconds
Started Jun 24 05:50:36 PM PDT 24
Finished Jun 24 05:50:38 PM PDT 24
Peak memory 198300 kb
Host smart-598d1ec0-6643-4e38-bb22-02dfb3acb68a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522483344 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.522483344
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1413999181
Short name T50
Test name
Test status
Simulation time 357269760 ps
CPU time 0.7 seconds
Started Jun 24 05:50:37 PM PDT 24
Finished Jun 24 05:50:39 PM PDT 24
Peak memory 193236 kb
Host smart-a43b6caa-2247-4d92-b901-3da28d2287e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413999181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1413999181
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.615376376
Short name T321
Test name
Test status
Simulation time 380164301 ps
CPU time 0.66 seconds
Started Jun 24 05:50:39 PM PDT 24
Finished Jun 24 05:50:41 PM PDT 24
Peak memory 183592 kb
Host smart-362d7e87-0946-4afe-b8b2-4460b938eb55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615376376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.615376376
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2589056544
Short name T350
Test name
Test status
Simulation time 945836068 ps
CPU time 0.81 seconds
Started Jun 24 05:50:37 PM PDT 24
Finished Jun 24 05:50:39 PM PDT 24
Peak memory 193516 kb
Host smart-6d4511a0-8e10-415f-a05c-a9de9fc0a2e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589056544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2589056544
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2559606564
Short name T284
Test name
Test status
Simulation time 430925551 ps
CPU time 2.04 seconds
Started Jun 24 05:50:39 PM PDT 24
Finished Jun 24 05:50:42 PM PDT 24
Peak memory 198448 kb
Host smart-a68eeb1f-b2ed-4c22-9723-d6a618ec1c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559606564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2559606564
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1740372827
Short name T397
Test name
Test status
Simulation time 4316049548 ps
CPU time 2.37 seconds
Started Jun 24 05:50:39 PM PDT 24
Finished Jun 24 05:50:43 PM PDT 24
Peak memory 197708 kb
Host smart-2403c715-3093-4350-99ac-9501f6ed047e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740372827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1740372827
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1688748890
Short name T407
Test name
Test status
Simulation time 534052901 ps
CPU time 1.39 seconds
Started Jun 24 05:50:37 PM PDT 24
Finished Jun 24 05:50:40 PM PDT 24
Peak memory 195904 kb
Host smart-045188be-ce2a-43d4-b8f5-3e900719f295
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688748890 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1688748890
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1221912653
Short name T60
Test name
Test status
Simulation time 445872885 ps
CPU time 1.25 seconds
Started Jun 24 05:50:37 PM PDT 24
Finished Jun 24 05:50:40 PM PDT 24
Peak memory 193084 kb
Host smart-d98617c4-dccd-4f1a-92b3-5637306db100
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221912653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1221912653
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2797800002
Short name T313
Test name
Test status
Simulation time 515848523 ps
CPU time 0.74 seconds
Started Jun 24 05:50:38 PM PDT 24
Finished Jun 24 05:50:40 PM PDT 24
Peak memory 192800 kb
Host smart-b21b9697-5f78-4559-b298-45e16d22d230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797800002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2797800002
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.854226928
Short name T347
Test name
Test status
Simulation time 2034189409 ps
CPU time 3.36 seconds
Started Jun 24 05:50:37 PM PDT 24
Finished Jun 24 05:50:41 PM PDT 24
Peak memory 194792 kb
Host smart-8dda0725-b136-4381-bfd7-63e02da3a122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854226928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.854226928
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2890641397
Short name T363
Test name
Test status
Simulation time 578516849 ps
CPU time 1.33 seconds
Started Jun 24 05:50:36 PM PDT 24
Finished Jun 24 05:50:39 PM PDT 24
Peak memory 198440 kb
Host smart-d2afd119-7c1c-463c-8c6b-34ae9f08b4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890641397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2890641397
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.422848184
Short name T193
Test name
Test status
Simulation time 4669870913 ps
CPU time 2.28 seconds
Started Jun 24 05:50:38 PM PDT 24
Finished Jun 24 05:50:41 PM PDT 24
Peak memory 196356 kb
Host smart-62468172-7a07-476b-91a4-9467d93ca2bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422848184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.422848184
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.947432543
Short name T353
Test name
Test status
Simulation time 611300704 ps
CPU time 0.94 seconds
Started Jun 24 05:50:45 PM PDT 24
Finished Jun 24 05:50:47 PM PDT 24
Peak memory 197060 kb
Host smart-37587d04-65d7-4932-939e-257d46b2b01f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947432543 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.947432543
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3923734461
Short name T409
Test name
Test status
Simulation time 343250008 ps
CPU time 0.73 seconds
Started Jun 24 05:50:48 PM PDT 24
Finished Jun 24 05:50:49 PM PDT 24
Peak memory 193144 kb
Host smart-c766eeb3-b3d6-4a1b-bc25-ed6d5c51d544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923734461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3923734461
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.185351798
Short name T330
Test name
Test status
Simulation time 446325979 ps
CPU time 0.66 seconds
Started Jun 24 05:50:46 PM PDT 24
Finished Jun 24 05:50:47 PM PDT 24
Peak memory 192820 kb
Host smart-c4485195-61cc-4e45-9fb4-da02c936e5fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185351798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.185351798
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.393352466
Short name T76
Test name
Test status
Simulation time 1320465953 ps
CPU time 1.04 seconds
Started Jun 24 05:50:47 PM PDT 24
Finished Jun 24 05:50:49 PM PDT 24
Peak memory 193900 kb
Host smart-3aec5cb5-2149-4309-b967-8a426a2388c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393352466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.393352466
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.652684869
Short name T286
Test name
Test status
Simulation time 545782497 ps
CPU time 1.98 seconds
Started Jun 24 05:50:37 PM PDT 24
Finished Jun 24 05:50:41 PM PDT 24
Peak memory 198464 kb
Host smart-46a7a2e0-edde-4c05-b084-8a0ad436e1d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652684869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.652684869
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2391858420
Short name T29
Test name
Test status
Simulation time 4554606108 ps
CPU time 6.79 seconds
Started Jun 24 05:50:36 PM PDT 24
Finished Jun 24 05:50:44 PM PDT 24
Peak memory 197844 kb
Host smart-6109b54f-dc5e-49f1-9649-36c8c6eb41f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391858420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2391858420
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2328562219
Short name T160
Test name
Test status
Simulation time 349577678 ps
CPU time 1.11 seconds
Started Jun 24 05:48:24 PM PDT 24
Finished Jun 24 05:48:27 PM PDT 24
Peak memory 197040 kb
Host smart-2284fcfb-b60a-4c47-b709-81eb9361720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328562219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2328562219
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1865129269
Short name T220
Test name
Test status
Simulation time 27211814376 ps
CPU time 42.33 seconds
Started Jun 24 05:48:23 PM PDT 24
Finished Jun 24 05:49:07 PM PDT 24
Peak memory 192428 kb
Host smart-efef0a01-799d-4aca-97fe-51ac8c17278d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865129269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1865129269
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3286651741
Short name T234
Test name
Test status
Simulation time 531245704 ps
CPU time 1.29 seconds
Started Jun 24 05:48:25 PM PDT 24
Finished Jun 24 05:48:28 PM PDT 24
Peak memory 192300 kb
Host smart-24768779-a920-4505-8f15-0146806cc023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286651741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3286651741
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3960097
Short name T265
Test name
Test status
Simulation time 43563092676 ps
CPU time 65.9 seconds
Started Jun 24 05:48:24 PM PDT 24
Finished Jun 24 05:49:31 PM PDT 24
Peak memory 192424 kb
Host smart-c7cd4704-3d2a-4831-9760-59afb6aa28d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3960097
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.413303429
Short name T15
Test name
Test status
Simulation time 7615464675 ps
CPU time 12.05 seconds
Started Jun 24 05:48:24 PM PDT 24
Finished Jun 24 05:48:37 PM PDT 24
Peak memory 216364 kb
Host smart-a11928bd-6f1f-4962-bc94-1de5a4917713
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413303429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.413303429
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2245685615
Short name T252
Test name
Test status
Simulation time 528314768 ps
CPU time 1.38 seconds
Started Jun 24 05:48:24 PM PDT 24
Finished Jun 24 05:48:27 PM PDT 24
Peak memory 192312 kb
Host smart-9289c7c5-e2df-4e25-8d66-5138029f150d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245685615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2245685615
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2327140759
Short name T278
Test name
Test status
Simulation time 23766415797 ps
CPU time 35.74 seconds
Started Jun 24 05:48:46 PM PDT 24
Finished Jun 24 05:49:22 PM PDT 24
Peak memory 192436 kb
Host smart-53d080f5-a73c-4485-989a-44197d66f588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327140759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2327140759
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3175413621
Short name T211
Test name
Test status
Simulation time 457740114 ps
CPU time 0.72 seconds
Started Jun 24 05:48:43 PM PDT 24
Finished Jun 24 05:48:45 PM PDT 24
Peak memory 192296 kb
Host smart-a3c44264-c760-4fce-afe4-058c7b704979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175413621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3175413621
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3179316236
Short name T223
Test name
Test status
Simulation time 46837653492 ps
CPU time 68.27 seconds
Started Jun 24 05:48:52 PM PDT 24
Finished Jun 24 05:50:02 PM PDT 24
Peak memory 192412 kb
Host smart-4d29711b-f635-4aba-913d-e96ae8873c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179316236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3179316236
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.4264790824
Short name T40
Test name
Test status
Simulation time 399114729 ps
CPU time 1.15 seconds
Started Jun 24 05:48:52 PM PDT 24
Finished Jun 24 05:48:54 PM PDT 24
Peak memory 192304 kb
Host smart-1dd93cd7-0ec9-4d46-8e02-38b7393f45aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264790824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.4264790824
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.519260273
Short name T229
Test name
Test status
Simulation time 16057253531 ps
CPU time 2.63 seconds
Started Jun 24 05:48:53 PM PDT 24
Finished Jun 24 05:48:56 PM PDT 24
Peak memory 192412 kb
Host smart-390bfa12-1a8b-4474-a325-c9e50656d84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519260273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.519260273
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2104415565
Short name T261
Test name
Test status
Simulation time 584988998 ps
CPU time 0.8 seconds
Started Jun 24 05:48:51 PM PDT 24
Finished Jun 24 05:48:53 PM PDT 24
Peak memory 192288 kb
Host smart-46c2ed4e-c9d7-4d9c-a544-ef668b574895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104415565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2104415565
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2157508054
Short name T228
Test name
Test status
Simulation time 7453408763 ps
CPU time 10 seconds
Started Jun 24 05:48:52 PM PDT 24
Finished Jun 24 05:49:03 PM PDT 24
Peak memory 192412 kb
Host smart-aec601a4-f6a4-4902-b5fa-4c464726aedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157508054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2157508054
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1209242197
Short name T232
Test name
Test status
Simulation time 475726216 ps
CPU time 0.93 seconds
Started Jun 24 05:48:54 PM PDT 24
Finished Jun 24 05:48:56 PM PDT 24
Peak memory 192532 kb
Host smart-d8faf0de-73c9-4db1-a851-62846478f67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209242197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1209242197
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1414202961
Short name T26
Test name
Test status
Simulation time 598082269 ps
CPU time 1.46 seconds
Started Jun 24 05:48:53 PM PDT 24
Finished Jun 24 05:48:55 PM PDT 24
Peak memory 197076 kb
Host smart-6889985e-4476-4188-8aa0-ac1276198e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414202961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1414202961
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.537651147
Short name T214
Test name
Test status
Simulation time 28044438994 ps
CPU time 21.36 seconds
Started Jun 24 05:48:51 PM PDT 24
Finished Jun 24 05:49:14 PM PDT 24
Peak memory 192416 kb
Host smart-26f80f36-2564-4051-b722-6ec4e65d24b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537651147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.537651147
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2852182297
Short name T225
Test name
Test status
Simulation time 444405631 ps
CPU time 1.26 seconds
Started Jun 24 05:48:54 PM PDT 24
Finished Jun 24 05:48:56 PM PDT 24
Peak memory 197120 kb
Host smart-5134dcae-49a2-46a7-9301-ed8473068f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852182297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2852182297
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2668408693
Short name T227
Test name
Test status
Simulation time 34187241110 ps
CPU time 46.84 seconds
Started Jun 24 05:49:02 PM PDT 24
Finished Jun 24 05:49:50 PM PDT 24
Peak memory 192408 kb
Host smart-e5798fa5-daa4-4ef5-b1b6-737049c44160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668408693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2668408693
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2346265315
Short name T250
Test name
Test status
Simulation time 467361092 ps
CPU time 0.76 seconds
Started Jun 24 05:49:01 PM PDT 24
Finished Jun 24 05:49:03 PM PDT 24
Peak memory 197080 kb
Host smart-58605b49-548a-48d3-82d3-6128f03b0f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346265315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2346265315
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3926879833
Short name T201
Test name
Test status
Simulation time 30469950600 ps
CPU time 7.38 seconds
Started Jun 24 05:49:04 PM PDT 24
Finished Jun 24 05:49:12 PM PDT 24
Peak memory 192420 kb
Host smart-954514f1-287e-4712-a444-1ede75ebbec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926879833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3926879833
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1399613639
Short name T270
Test name
Test status
Simulation time 442726114 ps
CPU time 0.93 seconds
Started Jun 24 05:49:03 PM PDT 24
Finished Jun 24 05:49:05 PM PDT 24
Peak memory 197104 kb
Host smart-3929d29e-cc91-4c72-ba71-3cbe11ab2ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399613639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1399613639
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3133947420
Short name T272
Test name
Test status
Simulation time 26896674637 ps
CPU time 10.84 seconds
Started Jun 24 05:49:02 PM PDT 24
Finished Jun 24 05:49:14 PM PDT 24
Peak memory 192432 kb
Host smart-222234d6-23b1-4cd1-9938-e2b60818ddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133947420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3133947420
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2638041157
Short name T43
Test name
Test status
Simulation time 419800151 ps
CPU time 1.27 seconds
Started Jun 24 05:49:02 PM PDT 24
Finished Jun 24 05:49:05 PM PDT 24
Peak memory 197076 kb
Host smart-d605d0c0-a9aa-4dc0-86c2-cae2adb7f8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638041157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2638041157
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.478124205
Short name T7
Test name
Test status
Simulation time 3716651304 ps
CPU time 1.29 seconds
Started Jun 24 05:49:02 PM PDT 24
Finished Jun 24 05:49:05 PM PDT 24
Peak memory 192432 kb
Host smart-d158d37f-ebac-4207-8cca-5d904e3c36ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478124205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.478124205
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.546788499
Short name T207
Test name
Test status
Simulation time 514411414 ps
CPU time 0.75 seconds
Started Jun 24 05:49:03 PM PDT 24
Finished Jun 24 05:49:05 PM PDT 24
Peak memory 197052 kb
Host smart-8dc1a39a-1e32-4217-ba45-d6f5bc46b41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546788499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.546788499
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.4110734238
Short name T283
Test name
Test status
Simulation time 18146823650 ps
CPU time 6.44 seconds
Started Jun 24 05:49:10 PM PDT 24
Finished Jun 24 05:49:18 PM PDT 24
Peak memory 192404 kb
Host smart-c4eed331-0a89-4796-a3cc-30a4eaca6ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110734238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.4110734238
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.4277061893
Short name T279
Test name
Test status
Simulation time 561849023 ps
CPU time 1.39 seconds
Started Jun 24 05:49:11 PM PDT 24
Finished Jun 24 05:49:13 PM PDT 24
Peak memory 197048 kb
Host smart-8f2275f1-f882-4ef8-a5b1-8bcc61da88b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277061893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.4277061893
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3473104560
Short name T168
Test name
Test status
Simulation time 395605837 ps
CPU time 1.12 seconds
Started Jun 24 05:48:34 PM PDT 24
Finished Jun 24 05:48:36 PM PDT 24
Peak memory 197060 kb
Host smart-4c29a85d-259d-4f8f-b9e2-bcf9144b35cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473104560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3473104560
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1419326442
Short name T236
Test name
Test status
Simulation time 10472158153 ps
CPU time 4.71 seconds
Started Jun 24 05:48:33 PM PDT 24
Finished Jun 24 05:48:38 PM PDT 24
Peak memory 192388 kb
Host smart-894cd1be-a12b-4306-848f-6ffbde5500af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419326442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1419326442
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2824467199
Short name T14
Test name
Test status
Simulation time 8006167291 ps
CPU time 6.36 seconds
Started Jun 24 05:48:34 PM PDT 24
Finished Jun 24 05:48:43 PM PDT 24
Peak memory 216436 kb
Host smart-6fb92414-592e-46b9-934d-8f49e61db35a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824467199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2824467199
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3910108070
Short name T8
Test name
Test status
Simulation time 554713507 ps
CPU time 0.95 seconds
Started Jun 24 05:48:26 PM PDT 24
Finished Jun 24 05:48:28 PM PDT 24
Peak memory 192296 kb
Host smart-52dc1e2e-92b2-4d03-929e-0fd096e3173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910108070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3910108070
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3425661061
Short name T64
Test name
Test status
Simulation time 61926693526 ps
CPU time 9.97 seconds
Started Jun 24 05:48:34 PM PDT 24
Finished Jun 24 05:48:46 PM PDT 24
Peak memory 192380 kb
Host smart-c98e097d-7747-410e-ba48-d968ed4f1d27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425661061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3425661061
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1829866765
Short name T226
Test name
Test status
Simulation time 24715712346 ps
CPU time 38.05 seconds
Started Jun 24 05:49:13 PM PDT 24
Finished Jun 24 05:49:52 PM PDT 24
Peak memory 192644 kb
Host smart-ee3eb3b3-ece7-4746-90fd-f2111749f0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829866765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1829866765
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2132690630
Short name T253
Test name
Test status
Simulation time 446382331 ps
CPU time 0.76 seconds
Started Jun 24 05:49:11 PM PDT 24
Finished Jun 24 05:49:13 PM PDT 24
Peak memory 192304 kb
Host smart-67f21e09-196e-4569-8c36-3fe4e684ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132690630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2132690630
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2381162407
Short name T266
Test name
Test status
Simulation time 41744895153 ps
CPU time 12.73 seconds
Started Jun 24 05:49:12 PM PDT 24
Finished Jun 24 05:49:26 PM PDT 24
Peak memory 192412 kb
Host smart-4616489b-8036-463c-a13d-59bf496d8de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381162407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2381162407
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.876123833
Short name T224
Test name
Test status
Simulation time 567518968 ps
CPU time 1.28 seconds
Started Jun 24 05:49:12 PM PDT 24
Finished Jun 24 05:49:14 PM PDT 24
Peak memory 192296 kb
Host smart-52f1c20d-adf0-417d-b58d-624c918940d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876123833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.876123833
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.673464739
Short name T248
Test name
Test status
Simulation time 14264651430 ps
CPU time 8.21 seconds
Started Jun 24 05:49:18 PM PDT 24
Finished Jun 24 05:49:27 PM PDT 24
Peak memory 192420 kb
Host smart-a388191f-01f2-4212-8819-1763c58cf19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673464739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.673464739
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2126218295
Short name T260
Test name
Test status
Simulation time 503975104 ps
CPU time 1.32 seconds
Started Jun 24 05:49:21 PM PDT 24
Finished Jun 24 05:49:24 PM PDT 24
Peak memory 192324 kb
Host smart-f986858b-54f4-4c0d-88c2-6e789634e206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126218295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2126218295
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.977717782
Short name T200
Test name
Test status
Simulation time 12684597083 ps
CPU time 4.91 seconds
Started Jun 24 05:49:20 PM PDT 24
Finished Jun 24 05:49:26 PM PDT 24
Peak memory 192396 kb
Host smart-6a8f4a81-2ab1-4ea9-ad32-9271871308e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977717782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.977717782
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.4177298642
Short name T251
Test name
Test status
Simulation time 492006639 ps
CPU time 1.26 seconds
Started Jun 24 05:49:22 PM PDT 24
Finished Jun 24 05:49:25 PM PDT 24
Peak memory 197084 kb
Host smart-c29007ea-5abc-46b4-9b6d-ade75d2bca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177298642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.4177298642
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1676373885
Short name T244
Test name
Test status
Simulation time 52886906032 ps
CPU time 15.42 seconds
Started Jun 24 05:49:23 PM PDT 24
Finished Jun 24 05:49:39 PM PDT 24
Peak memory 192344 kb
Host smart-131e1352-349d-43e6-ae3a-bf6b84051592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676373885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1676373885
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3133687296
Short name T257
Test name
Test status
Simulation time 529190799 ps
CPU time 1.43 seconds
Started Jun 24 05:49:19 PM PDT 24
Finished Jun 24 05:49:21 PM PDT 24
Peak memory 192304 kb
Host smart-c272d7f1-d3e9-4b56-a4a9-6c3feaf9f4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133687296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3133687296
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3112557621
Short name T182
Test name
Test status
Simulation time 614197806 ps
CPU time 1.03 seconds
Started Jun 24 05:49:19 PM PDT 24
Finished Jun 24 05:49:22 PM PDT 24
Peak memory 196980 kb
Host smart-3f223884-2147-4164-9c14-c670c992d2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112557621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3112557621
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3705948795
Short name T6
Test name
Test status
Simulation time 58884016830 ps
CPU time 24.57 seconds
Started Jun 24 05:49:20 PM PDT 24
Finished Jun 24 05:49:46 PM PDT 24
Peak memory 192424 kb
Host smart-244d838d-7087-4690-8149-5de76c5d3c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705948795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3705948795
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3632328844
Short name T206
Test name
Test status
Simulation time 416447146 ps
CPU time 1.17 seconds
Started Jun 24 05:49:18 PM PDT 24
Finished Jun 24 05:49:20 PM PDT 24
Peak memory 197080 kb
Host smart-1375ffb8-8dcb-40d1-bc8e-5edffbd4b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632328844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3632328844
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.863901744
Short name T259
Test name
Test status
Simulation time 4546305553 ps
CPU time 6.54 seconds
Started Jun 24 05:49:22 PM PDT 24
Finished Jun 24 05:49:30 PM PDT 24
Peak memory 192344 kb
Host smart-bb990592-0696-42ae-baf2-79cbb86bc0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863901744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.863901744
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1333993677
Short name T246
Test name
Test status
Simulation time 497513906 ps
CPU time 1.21 seconds
Started Jun 24 05:49:20 PM PDT 24
Finished Jun 24 05:49:23 PM PDT 24
Peak memory 192324 kb
Host smart-d753f025-3150-4541-ae5f-2b4e014c8ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333993677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1333993677
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3563992875
Short name T268
Test name
Test status
Simulation time 24965665510 ps
CPU time 25.71 seconds
Started Jun 24 05:49:21 PM PDT 24
Finished Jun 24 05:49:48 PM PDT 24
Peak memory 192412 kb
Host smart-6b6f60d9-6a73-4ec2-a348-1d8a77e827a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563992875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3563992875
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.4113761672
Short name T281
Test name
Test status
Simulation time 607038193 ps
CPU time 1.35 seconds
Started Jun 24 05:49:22 PM PDT 24
Finished Jun 24 05:49:25 PM PDT 24
Peak memory 192236 kb
Host smart-391c537e-a819-4f21-8e98-8f3f526acf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113761672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.4113761672
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1305886044
Short name T79
Test name
Test status
Simulation time 19587425460 ps
CPU time 87.16 seconds
Started Jun 24 05:49:19 PM PDT 24
Finished Jun 24 05:50:47 PM PDT 24
Peak memory 214868 kb
Host smart-79b1907b-a847-46e2-b6d8-39b2833bf45d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305886044 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1305886044
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.984844008
Short name T243
Test name
Test status
Simulation time 37805952623 ps
CPU time 15.46 seconds
Started Jun 24 05:49:29 PM PDT 24
Finished Jun 24 05:49:46 PM PDT 24
Peak memory 192400 kb
Host smart-08a16de0-79ee-4d93-8472-fab05b44abae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984844008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.984844008
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.529937439
Short name T42
Test name
Test status
Simulation time 499059256 ps
CPU time 0.77 seconds
Started Jun 24 05:49:21 PM PDT 24
Finished Jun 24 05:49:23 PM PDT 24
Peak memory 192308 kb
Host smart-7ca80651-3418-4533-a202-6f5f5b4f777f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529937439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.529937439
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1514634893
Short name T282
Test name
Test status
Simulation time 37591658913 ps
CPU time 13.64 seconds
Started Jun 24 05:49:28 PM PDT 24
Finished Jun 24 05:49:42 PM PDT 24
Peak memory 197396 kb
Host smart-99487197-f13f-45ad-a903-4c50bdc9fbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514634893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1514634893
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.390552395
Short name T274
Test name
Test status
Simulation time 555867388 ps
CPU time 0.94 seconds
Started Jun 24 05:49:30 PM PDT 24
Finished Jun 24 05:49:32 PM PDT 24
Peak memory 192292 kb
Host smart-e94d3861-ca53-4d4c-be31-0c9459a43029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390552395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.390552395
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1992313439
Short name T267
Test name
Test status
Simulation time 712142795 ps
CPU time 1.56 seconds
Started Jun 24 05:48:34 PM PDT 24
Finished Jun 24 05:48:37 PM PDT 24
Peak memory 192324 kb
Host smart-ab716df1-14eb-4264-8eca-f693cdecd61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992313439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1992313439
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.471952646
Short name T16
Test name
Test status
Simulation time 5100404299 ps
CPU time 1.18 seconds
Started Jun 24 05:48:35 PM PDT 24
Finished Jun 24 05:48:38 PM PDT 24
Peak memory 216256 kb
Host smart-de566fa1-e2c2-40c3-bc37-b3aceff3252f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471952646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.471952646
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3906224250
Short name T203
Test name
Test status
Simulation time 429752538 ps
CPU time 0.89 seconds
Started Jun 24 05:48:35 PM PDT 24
Finished Jun 24 05:48:37 PM PDT 24
Peak memory 197052 kb
Host smart-d4aa97ad-cfd1-45d9-a16a-074d9e1dabe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906224250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3906224250
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3562034399
Short name T199
Test name
Test status
Simulation time 11480075114 ps
CPU time 14.83 seconds
Started Jun 24 05:49:30 PM PDT 24
Finished Jun 24 05:49:46 PM PDT 24
Peak memory 192412 kb
Host smart-874ea7fc-13bd-46e7-8a4e-5c939ff06a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562034399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3562034399
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2275519816
Short name T204
Test name
Test status
Simulation time 452361188 ps
CPU time 0.76 seconds
Started Jun 24 05:49:31 PM PDT 24
Finished Jun 24 05:49:33 PM PDT 24
Peak memory 197072 kb
Host smart-7652a3b7-5aa0-4b8e-a8c1-6ee219596af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275519816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2275519816
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3275091351
Short name T48
Test name
Test status
Simulation time 253710738591 ps
CPU time 494.96 seconds
Started Jun 24 05:49:30 PM PDT 24
Finished Jun 24 05:57:46 PM PDT 24
Peak memory 204388 kb
Host smart-e41f99db-42a1-4803-ba16-fcffa8bc635e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275091351 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3275091351
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1475345651
Short name T27
Test name
Test status
Simulation time 23230447752 ps
CPU time 34.82 seconds
Started Jun 24 05:49:30 PM PDT 24
Finished Jun 24 05:50:06 PM PDT 24
Peak memory 192384 kb
Host smart-49e84092-8386-47f5-9ba3-9baa90af8556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475345651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1475345651
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3049125645
Short name T215
Test name
Test status
Simulation time 534470879 ps
CPU time 0.69 seconds
Started Jun 24 05:49:32 PM PDT 24
Finished Jun 24 05:49:34 PM PDT 24
Peak memory 192340 kb
Host smart-2a4ee452-886f-4887-9995-90a9d5a61976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049125645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3049125645
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3894682536
Short name T213
Test name
Test status
Simulation time 4627815858 ps
CPU time 1.62 seconds
Started Jun 24 05:49:31 PM PDT 24
Finished Jun 24 05:49:34 PM PDT 24
Peak memory 192424 kb
Host smart-82e5d64a-ac37-4df7-b19c-9923f2a8a8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894682536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3894682536
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2897776025
Short name T277
Test name
Test status
Simulation time 542713017 ps
CPU time 1.32 seconds
Started Jun 24 05:49:30 PM PDT 24
Finished Jun 24 05:49:33 PM PDT 24
Peak memory 192296 kb
Host smart-f4b2bb07-996b-4c37-aa21-784af5b2dba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897776025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2897776025
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1113378229
Short name T238
Test name
Test status
Simulation time 15447778931 ps
CPU time 22.21 seconds
Started Jun 24 05:49:42 PM PDT 24
Finished Jun 24 05:50:05 PM PDT 24
Peak memory 192412 kb
Host smart-475e0bcb-795e-4eab-9b02-d2a05bacc1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113378229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1113378229
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.197519289
Short name T242
Test name
Test status
Simulation time 523484816 ps
CPU time 0.8 seconds
Started Jun 24 05:49:39 PM PDT 24
Finished Jun 24 05:49:41 PM PDT 24
Peak memory 197096 kb
Host smart-ef2758a3-e023-4598-bda1-64938373fe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197519289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.197519289
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3319839626
Short name T38
Test name
Test status
Simulation time 9235450789 ps
CPU time 7.1 seconds
Started Jun 24 05:49:38 PM PDT 24
Finished Jun 24 05:49:46 PM PDT 24
Peak memory 192408 kb
Host smart-c7e12a85-7590-4e9d-8314-b1911e3ec179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319839626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3319839626
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1065592860
Short name T208
Test name
Test status
Simulation time 360636308 ps
CPU time 0.75 seconds
Started Jun 24 05:49:38 PM PDT 24
Finished Jun 24 05:49:39 PM PDT 24
Peak memory 192232 kb
Host smart-6ead85f5-90a7-4491-8b38-a93de28f66d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065592860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1065592860
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.227866733
Short name T241
Test name
Test status
Simulation time 30450381332 ps
CPU time 31.77 seconds
Started Jun 24 05:49:39 PM PDT 24
Finished Jun 24 05:50:11 PM PDT 24
Peak memory 192396 kb
Host smart-a13bbe44-d865-4320-8c79-85baed5c5e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227866733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.227866733
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.971906995
Short name T221
Test name
Test status
Simulation time 348756192 ps
CPU time 1.07 seconds
Started Jun 24 05:49:38 PM PDT 24
Finished Jun 24 05:49:40 PM PDT 24
Peak memory 197064 kb
Host smart-7bfffa1b-9052-4d45-af2f-612799b5a355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971906995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.971906995
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3846835583
Short name T209
Test name
Test status
Simulation time 36612275471 ps
CPU time 28.62 seconds
Started Jun 24 05:49:37 PM PDT 24
Finished Jun 24 05:50:07 PM PDT 24
Peak memory 192412 kb
Host smart-3c197a7d-732f-4d4e-953b-2f4af1796dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846835583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3846835583
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1706058760
Short name T258
Test name
Test status
Simulation time 445731590 ps
CPU time 1.19 seconds
Started Jun 24 05:49:39 PM PDT 24
Finished Jun 24 05:49:41 PM PDT 24
Peak memory 192468 kb
Host smart-ccc3edc7-66f1-4134-a084-f779fbb2e494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706058760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1706058760
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1442791458
Short name T175
Test name
Test status
Simulation time 395869531 ps
CPU time 0.85 seconds
Started Jun 24 05:49:49 PM PDT 24
Finished Jun 24 05:49:51 PM PDT 24
Peak memory 197056 kb
Host smart-f00078f5-13de-44e4-a8b5-d5245e32c075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442791458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1442791458
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3565063205
Short name T276
Test name
Test status
Simulation time 43457111613 ps
CPU time 61.9 seconds
Started Jun 24 05:49:50 PM PDT 24
Finished Jun 24 05:50:53 PM PDT 24
Peak memory 192420 kb
Host smart-e879fb6d-c00e-4066-a2ec-4cfe17c41f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565063205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3565063205
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2496040841
Short name T239
Test name
Test status
Simulation time 548511483 ps
CPU time 1.29 seconds
Started Jun 24 05:49:39 PM PDT 24
Finished Jun 24 05:49:41 PM PDT 24
Peak memory 192312 kb
Host smart-050aff65-0322-4439-adfd-a016256f7594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496040841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2496040841
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.528862939
Short name T178
Test name
Test status
Simulation time 483761980 ps
CPU time 0.64 seconds
Started Jun 24 05:49:48 PM PDT 24
Finished Jun 24 05:49:49 PM PDT 24
Peak memory 197100 kb
Host smart-943ab195-cfa8-45fc-8aac-9adeefca3a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528862939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.528862939
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2212458828
Short name T269
Test name
Test status
Simulation time 6262932507 ps
CPU time 10.52 seconds
Started Jun 24 05:49:49 PM PDT 24
Finished Jun 24 05:50:00 PM PDT 24
Peak memory 192412 kb
Host smart-b17aa48d-9da0-41d9-b365-f4ad15922016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212458828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2212458828
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2159469832
Short name T217
Test name
Test status
Simulation time 498936728 ps
CPU time 1.36 seconds
Started Jun 24 05:49:49 PM PDT 24
Finished Jun 24 05:49:52 PM PDT 24
Peak memory 192304 kb
Host smart-f52c5610-6f1e-4bd3-b185-9304805d5d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159469832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2159469832
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1641836560
Short name T222
Test name
Test status
Simulation time 25337316368 ps
CPU time 4.85 seconds
Started Jun 24 05:49:48 PM PDT 24
Finished Jun 24 05:49:53 PM PDT 24
Peak memory 192412 kb
Host smart-c3fa8787-93f3-47e3-88ec-748941a04a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641836560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1641836560
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2855265132
Short name T249
Test name
Test status
Simulation time 360297176 ps
CPU time 0.69 seconds
Started Jun 24 05:49:48 PM PDT 24
Finished Jun 24 05:49:49 PM PDT 24
Peak memory 192304 kb
Host smart-dd23a34a-ae89-469c-9002-bb2e37c59087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855265132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2855265132
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2679723625
Short name T262
Test name
Test status
Simulation time 30258264704 ps
CPU time 44.09 seconds
Started Jun 24 05:48:34 PM PDT 24
Finished Jun 24 05:49:20 PM PDT 24
Peak memory 192408 kb
Host smart-9f66da50-8c6b-4d62-a14a-96bfee24f6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679723625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2679723625
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.60597965
Short name T20
Test name
Test status
Simulation time 4332510775 ps
CPU time 2.25 seconds
Started Jun 24 05:48:34 PM PDT 24
Finished Jun 24 05:48:37 PM PDT 24
Peak memory 216256 kb
Host smart-336b55b3-e85c-4bcd-a827-6ede447c269b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60597965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.60597965
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2372235368
Short name T216
Test name
Test status
Simulation time 478553389 ps
CPU time 0.8 seconds
Started Jun 24 05:48:37 PM PDT 24
Finished Jun 24 05:48:39 PM PDT 24
Peak memory 192300 kb
Host smart-7c076099-ecd6-4358-a413-67103075cfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372235368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2372235368
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3256484061
Short name T202
Test name
Test status
Simulation time 54116846885 ps
CPU time 47.22 seconds
Started Jun 24 05:49:50 PM PDT 24
Finished Jun 24 05:50:38 PM PDT 24
Peak memory 192388 kb
Host smart-9139ee79-73c4-41b3-8b7f-5b55f04fdd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256484061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3256484061
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3587023213
Short name T256
Test name
Test status
Simulation time 470665019 ps
CPU time 0.73 seconds
Started Jun 24 05:49:48 PM PDT 24
Finished Jun 24 05:49:50 PM PDT 24
Peak memory 192304 kb
Host smart-9a8c7d10-4386-4d8d-ac0f-4bd71a1eec83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587023213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3587023213
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2256413253
Short name T25
Test name
Test status
Simulation time 19653973709 ps
CPU time 8.17 seconds
Started Jun 24 05:49:57 PM PDT 24
Finished Jun 24 05:50:08 PM PDT 24
Peak memory 192392 kb
Host smart-c8843b5b-c62d-4d58-b3c2-d3c5086c435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256413253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2256413253
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3051404406
Short name T10
Test name
Test status
Simulation time 421392790 ps
CPU time 0.69 seconds
Started Jun 24 05:49:48 PM PDT 24
Finished Jun 24 05:49:50 PM PDT 24
Peak memory 192316 kb
Host smart-d0b4ae38-1aaf-4b09-af6a-a4d9468b9ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051404406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3051404406
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3030023933
Short name T275
Test name
Test status
Simulation time 39783271871 ps
CPU time 55.26 seconds
Started Jun 24 05:49:58 PM PDT 24
Finished Jun 24 05:50:56 PM PDT 24
Peak memory 192428 kb
Host smart-bfde7262-b069-47a2-8f06-49fec8a78fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030023933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3030023933
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.746508258
Short name T3
Test name
Test status
Simulation time 458514908 ps
CPU time 1.16 seconds
Started Jun 24 05:49:57 PM PDT 24
Finished Jun 24 05:50:00 PM PDT 24
Peak memory 192296 kb
Host smart-de109002-f73e-49a1-bf8d-9666b1b35545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746508258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.746508258
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2979093975
Short name T247
Test name
Test status
Simulation time 23829277842 ps
CPU time 11.15 seconds
Started Jun 24 05:49:58 PM PDT 24
Finished Jun 24 05:50:12 PM PDT 24
Peak memory 192644 kb
Host smart-b0c40f69-b8de-4d0f-b2b7-7907efd1315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979093975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2979093975
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1413283052
Short name T255
Test name
Test status
Simulation time 492991600 ps
CPU time 0.8 seconds
Started Jun 24 05:49:59 PM PDT 24
Finished Jun 24 05:50:02 PM PDT 24
Peak memory 197100 kb
Host smart-a8a88cd1-f68f-4e2f-b6e9-59653b24e5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413283052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1413283052
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3432147845
Short name T233
Test name
Test status
Simulation time 15542848120 ps
CPU time 20.17 seconds
Started Jun 24 05:49:59 PM PDT 24
Finished Jun 24 05:50:22 PM PDT 24
Peak memory 192424 kb
Host smart-37141a16-5786-4ddb-8b56-64bc227e5cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432147845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3432147845
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2915477529
Short name T235
Test name
Test status
Simulation time 529070019 ps
CPU time 1.42 seconds
Started Jun 24 05:49:56 PM PDT 24
Finished Jun 24 05:49:59 PM PDT 24
Peak memory 197104 kb
Host smart-53c490ae-3705-4477-859b-8340bf319758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915477529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2915477529
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2332157009
Short name T218
Test name
Test status
Simulation time 1136020943 ps
CPU time 1.74 seconds
Started Jun 24 05:49:58 PM PDT 24
Finished Jun 24 05:50:02 PM PDT 24
Peak memory 192296 kb
Host smart-f2e31119-c3cd-4f1e-ba88-311124f79e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332157009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2332157009
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2356885678
Short name T263
Test name
Test status
Simulation time 536983739 ps
CPU time 1.29 seconds
Started Jun 24 05:50:00 PM PDT 24
Finished Jun 24 05:50:03 PM PDT 24
Peak memory 192304 kb
Host smart-3d6802df-175e-468a-aa50-a1b36048917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356885678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2356885678
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1818688391
Short name T271
Test name
Test status
Simulation time 2628236497 ps
CPU time 4.31 seconds
Started Jun 24 05:49:57 PM PDT 24
Finished Jun 24 05:50:02 PM PDT 24
Peak memory 192412 kb
Host smart-675c986e-cbe3-4c92-a495-684660cfaba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818688391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1818688391
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1515970429
Short name T245
Test name
Test status
Simulation time 524176726 ps
CPU time 0.81 seconds
Started Jun 24 05:50:01 PM PDT 24
Finished Jun 24 05:50:04 PM PDT 24
Peak memory 197008 kb
Host smart-15fcedeb-aa8d-438c-beb4-490779cde1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515970429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1515970429
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2447569976
Short name T5
Test name
Test status
Simulation time 46723649906 ps
CPU time 68.47 seconds
Started Jun 24 05:50:00 PM PDT 24
Finished Jun 24 05:51:11 PM PDT 24
Peak memory 192392 kb
Host smart-a511cac8-77c2-4082-98be-e203334bd603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447569976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2447569976
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2988258843
Short name T273
Test name
Test status
Simulation time 402369028 ps
CPU time 0.74 seconds
Started Jun 24 05:49:57 PM PDT 24
Finished Jun 24 05:49:59 PM PDT 24
Peak memory 192308 kb
Host smart-241870bb-e548-4167-b51c-0b30025da1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988258843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2988258843
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3065270064
Short name T230
Test name
Test status
Simulation time 53562163956 ps
CPU time 41.9 seconds
Started Jun 24 05:50:01 PM PDT 24
Finished Jun 24 05:50:45 PM PDT 24
Peak memory 192424 kb
Host smart-c00b2cb3-e904-442d-a179-d9cae6531339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065270064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3065270064
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.248390256
Short name T264
Test name
Test status
Simulation time 468163616 ps
CPU time 0.72 seconds
Started Jun 24 05:49:58 PM PDT 24
Finished Jun 24 05:50:01 PM PDT 24
Peak memory 192308 kb
Host smart-a5d31e49-95bf-45c9-bfe0-c9fd513c22b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248390256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.248390256
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.4220323187
Short name T254
Test name
Test status
Simulation time 19523592030 ps
CPU time 26.14 seconds
Started Jun 24 05:50:07 PM PDT 24
Finished Jun 24 05:50:34 PM PDT 24
Peak memory 192412 kb
Host smart-957a9aed-c0f6-488a-a5fe-7a5177a705cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220323187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.4220323187
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2827445216
Short name T210
Test name
Test status
Simulation time 570955700 ps
CPU time 0.68 seconds
Started Jun 24 05:50:06 PM PDT 24
Finished Jun 24 05:50:08 PM PDT 24
Peak memory 192304 kb
Host smart-800f115f-058c-4c13-8bd2-e665e9278035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827445216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2827445216
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1053257608
Short name T174
Test name
Test status
Simulation time 522129578 ps
CPU time 0.97 seconds
Started Jun 24 05:48:34 PM PDT 24
Finished Jun 24 05:48:36 PM PDT 24
Peak memory 197040 kb
Host smart-a74f7841-b81d-43d8-bcd6-19f6ec4fe541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053257608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1053257608
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.529224221
Short name T21
Test name
Test status
Simulation time 29636834511 ps
CPU time 36.91 seconds
Started Jun 24 05:48:36 PM PDT 24
Finished Jun 24 05:49:14 PM PDT 24
Peak memory 192440 kb
Host smart-da56d162-f0bc-45db-97c6-4f6b1580264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529224221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.529224221
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1828271890
Short name T231
Test name
Test status
Simulation time 555016874 ps
CPU time 0.93 seconds
Started Jun 24 05:48:34 PM PDT 24
Finished Jun 24 05:48:37 PM PDT 24
Peak memory 192280 kb
Host smart-745a212d-d23c-4f3f-b167-1e969481a742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828271890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1828271890
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.4163998325
Short name T205
Test name
Test status
Simulation time 26028826819 ps
CPU time 18.91 seconds
Started Jun 24 05:48:35 PM PDT 24
Finished Jun 24 05:48:55 PM PDT 24
Peak memory 192424 kb
Host smart-8e0f4a52-eccc-4bd0-9d82-668b379f4d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163998325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4163998325
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.41965961
Short name T212
Test name
Test status
Simulation time 431820423 ps
CPU time 0.87 seconds
Started Jun 24 05:48:33 PM PDT 24
Finished Jun 24 05:48:36 PM PDT 24
Peak memory 192280 kb
Host smart-560fbd98-16a6-40d6-ac59-a31b0eb0e53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41965961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.41965961
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1816505685
Short name T280
Test name
Test status
Simulation time 21240077800 ps
CPU time 28.4 seconds
Started Jun 24 05:48:43 PM PDT 24
Finished Jun 24 05:49:12 PM PDT 24
Peak memory 192428 kb
Host smart-bc782768-3c01-4e77-98ef-b34195209165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816505685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1816505685
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2361004579
Short name T237
Test name
Test status
Simulation time 607492785 ps
CPU time 1.42 seconds
Started Jun 24 05:48:44 PM PDT 24
Finished Jun 24 05:48:46 PM PDT 24
Peak memory 197068 kb
Host smart-5f29be11-b6a2-44ba-9a94-c69e886568e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361004579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2361004579
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2657339027
Short name T219
Test name
Test status
Simulation time 18014260627 ps
CPU time 26.31 seconds
Started Jun 24 05:48:42 PM PDT 24
Finished Jun 24 05:49:09 PM PDT 24
Peak memory 192348 kb
Host smart-e5a1c6a4-e9a9-4fe8-8d27-464ff4f08b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657339027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2657339027
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2550557738
Short name T1
Test name
Test status
Simulation time 561963826 ps
CPU time 0.81 seconds
Started Jun 24 05:48:46 PM PDT 24
Finished Jun 24 05:48:48 PM PDT 24
Peak memory 192324 kb
Host smart-1fdb1988-eade-4519-a5a8-28e19d02809e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550557738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2550557738
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3643692430
Short name T45
Test name
Test status
Simulation time 14670669174 ps
CPU time 2.87 seconds
Started Jun 24 05:48:43 PM PDT 24
Finished Jun 24 05:48:47 PM PDT 24
Peak memory 192416 kb
Host smart-babfbbdf-fe08-4b78-8375-6848e83d7f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643692430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3643692430
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2785723195
Short name T240
Test name
Test status
Simulation time 623041181 ps
CPU time 0.79 seconds
Started Jun 24 05:48:44 PM PDT 24
Finished Jun 24 05:48:46 PM PDT 24
Peak memory 192228 kb
Host smart-e821ac22-ff4a-48c8-a70d-41109ce14eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785723195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2785723195
Directory /workspace/9.aon_timer_smoke/latest
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