Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	29289	1		T1	11		T2	109		T3	187
bark[1]	234	1		T16	7		T52	21		T35	49
bark[2]	795	1		T47	21		T192	14		T120	21
bark[3]	1139	1		T106	21		T108	47		T90	174
bark[4]	876	1		T20	21		T113	42		T188	14
bark[5]	910	1		T16	7		T35	21		T43	253
bark[6]	807	1		T15	30		T162	21		T148	14
bark[7]	653	1		T44	31		T137	265		T128	21
bark[8]	459	1		T35	239		T47	56		T89	5
bark[9]	695	1		T14	14		T20	111		T46	26
bark[10]	934	1		T7	14		T19	7		T43	26
bark[11]	184	1		T48	35		T120	7		T181	14
bark[12]	1083	1		T52	21		T35	327		T180	30
bark[13]	474	1		T10	70		T189	74		T46	109
bark[14]	563	1		T11	14		T130	21		T47	21
bark[15]	571	1		T2	66		T4	14		T15	30
bark[16]	964	1		T10	76		T52	23		T44	21
bark[17]	459	1		T17	21		T137	21		T77	44
bark[18]	271	1		T19	21		T47	45		T167	30
bark[19]	324	1		T8	14		T94	105		T167	21
bark[20]	443	1		T2	52		T43	28		T32	14
bark[21]	446	1		T13	14		T15	48		T46	21
bark[22]	605	1		T3	21		T12	14		T193	14
bark[23]	224	1		T45	21		T130	21		T106	21
bark[24]	859	1		T2	51		T43	263		T48	21
bark[25]	708	1		T19	7		T44	86		T45	221
bark[26]	1287	1		T35	35		T48	7		T154	14
bark[27]	642	1		T15	21		T17	40		T43	21
bark[28]	602	1		T158	14		T45	53		T31	39
bark[29]	500	1		T162	21		T45	153		T94	21
bark[30]	582	1		T52	21		T31	21		T108	30
bark[31]	399	1		T52	21		T20	26		T43	21
bark_0	4739	1		T1	7		T2	16		T3	16

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	29080	1		T1	10		T2	108		T3	186
bite[1]	1006	1		T47	44		T106	21		T133	58
bite[2]	879	1		T15	78		T19	6		T44	159
bite[3]	623	1		T8	13		T15	30		T113	21
bite[4]	254	1		T3	21		T17	21		T130	30
bite[5]	877	1		T45	53		T55	21		T117	258
bite[6]	782	1		T52	21		T35	35		T46	21
bite[7]	289	1		T11	13		T20	21		T130	21
bite[8]	478	1		T13	13		T19	21		T52	21
bite[9]	532	1		T20	110		T109	57		T167	21
bite[10]	751	1		T189	74		T130	21		T108	21
bite[11]	569	1		T162	21		T46	268		T47	55
bite[12]	108	1		T43	26		T48	6		T154	13
bite[13]	137	1		T10	76		T106	21		T117	6
bite[14]	242	1		T15	56		T35	21		T32	13
bite[15]	573	1		T14	13		T35	30		T120	21
bite[16]	367	1		T17	21		T106	40		T120	43
bite[17]	336	1		T2	66		T10	70		T16	6
bite[18]	1312	1		T16	14		T130	39		T31	21
bite[19]	384	1		T7	13		T52	42		T43	6
bite[20]	855	1		T35	238		T43	273		T45	21
bite[21]	726	1		T20	61		T113	21		T46	129
bite[22]	1072	1		T43	21		T94	64		T167	21
bite[23]	657	1		T52	21		T31	39		T111	21
bite[24]	1408	1		T17	40		T35	296		T43	262
bite[25]	913	1		T4	13		T52	22		T47	21
bite[26]	333	1		T2	52		T20	26		T44	33
bite[27]	345	1		T94	21		T89	6		T133	30
bite[28]	656	1		T35	48		T144	21		T191	13
bite[29]	711	1		T19	43		T20	21		T43	21
bite[30]	238	1		T44	21		T180	30		T90	21
bite[31]	1009	1		T2	51		T19	6		T48	21
bite_0	5218	1		T1	8		T2	17		T3	17

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	53720	1		T1	18		T2	294		T3	224

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1131	1		T35	82		T43	82		T44	64
prescale[1]	988	1		T2	19		T10	19		T19	19
prescale[2]	864	1		T3	19		T35	50		T113	38
prescale[3]	902	1		T16	28		T44	19		T162	9
prescale[4]	811	1		T3	40		T16	23		T35	40
prescale[5]	791	1		T20	40		T35	124		T130	32
prescale[6]	1051	1		T35	19		T45	113		T46	123
prescale[7]	704	1		T2	9		T17	97		T35	19
prescale[8]	695	1		T35	2		T44	21		T89	2
prescale[9]	871	1		T20	38		T35	2		T113	19
prescale[10]	1333	1		T19	105		T52	41		T44	56
prescale[11]	1019	1		T20	2		T35	46		T44	46
prescale[12]	731	1		T2	23		T20	27		T35	65
prescale[13]	568	1		T16	2		T17	33		T45	20
prescale[14]	910	1		T3	19		T43	59		T45	42
prescale[15]	218	1		T46	2		T130	19		T128	27
prescale[16]	1169	1		T43	84		T44	2		T46	35
prescale[17]	639	1		T16	48		T209	9		T43	35
prescale[18]	441	1		T10	23		T43	76		T46	2
prescale[19]	451	1		T19	2		T113	19		T44	19
prescale[20]	665	1		T19	28		T43	147		T137	197
prescale[21]	772	1		T3	24		T10	19		T43	134
prescale[22]	1029	1		T15	32		T19	2		T43	72
prescale[23]	899	1		T6	9		T9	9		T19	24
prescale[24]	600	1		T113	19		T45	14		T46	88
prescale[25]	756	1		T53	9		T44	2		T46	128
prescale[26]	725	1		T15	19		T44	19		T162	40
prescale[27]	873	1		T19	23		T20	2		T113	19
prescale[28]	1061	1		T16	2		T20	2		T35	61
prescale[29]	892	1		T17	14		T35	138		T44	11
prescale[30]	804	1		T19	127		T20	9		T113	19
prescale[31]	800	1		T10	27		T113	19		T44	80
prescale_0	27557	1		T1	18		T2	243		T3	122

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	39447	1		T1	18		T2	234		T3	107
auto[1]	14273	1		T2	60		T3	117		T4	12

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	53720	1		T1	18		T2	294		T3	224

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30949	1		T1	13		T2	138		T3	189
wkup[1]	220	1		T113	21		T180	30		T47	47
wkup[2]	344	1		T15	30		T16	35		T148	15
wkup[3]	328	1		T14	15		T44	21		T46	21
wkup[4]	303	1		T44	21		T47	56		T109	21
wkup[5]	279	1		T13	15		T35	21		T185	15
wkup[6]	420	1		T43	42		T46	21		T47	21
wkup[7]	114	1		T48	21		T170	21		T147	21
wkup[8]	249	1		T17	21		T19	21		T20	26
wkup[9]	480	1		T20	21		T44	21		T188	15
wkup[10]	362	1		T43	15		T45	21		T163	39
wkup[11]	441	1		T2	26		T16	49		T52	21
wkup[12]	348	1		T10	49		T43	21		T44	8
wkup[13]	382	1		T17	40		T19	21		T44	26
wkup[14]	378	1		T52	26		T189	29		T46	21
wkup[15]	202	1		T46	52		T31	21		T137	21
wkup[16]	173	1		T46	21		T144	65		T55	21
wkup[17]	249	1		T2	30		T19	30		T35	21
wkup[18]	320	1		T113	21		T44	21		T47	26
wkup[19]	424	1		T2	26		T44	26		T47	42
wkup[20]	298	1		T15	35		T20	60		T43	21
wkup[21]	238	1		T43	21		T47	21		T94	6
wkup[22]	378	1		T19	21		T46	21		T48	35
wkup[23]	371	1		T20	21		T43	26		T46	21
wkup[24]	362	1		T43	8		T46	44		T111	21
wkup[25]	350	1		T35	21		T43	21		T46	42
wkup[26]	463	1		T16	21		T43	21		T180	21
wkup[27]	283	1		T8	15		T43	21		T189	21
wkup[28]	252	1		T52	45		T43	21		T46	21
wkup[29]	278	1		T2	39		T11	15		T20	35
wkup[30]	358	1		T3	21		T35	59		T43	36
wkup[31]	351	1		T15	30		T46	21		T90	21
wkup[32]	380	1		T2	21		T15	21		T16	8
wkup[33]	113	1		T46	15		T173	21		T91	26
wkup[34]	271	1		T7	15		T35	26		T44	21
wkup[35]	458	1		T10	21		T167	30		T89	25
wkup[36]	363	1		T20	31		T44	21		T46	21
wkup[37]	251	1		T44	21		T108	53		T120	21
wkup[38]	199	1		T43	26		T181	15		T116	15
wkup[39]	310	1		T35	21		T43	26		T130	21
wkup[40]	320	1		T19	8		T52	21		T47	21
wkup[41]	377	1		T19	8		T162	21		T45	30
wkup[42]	309	1		T43	84		T44	21		T46	21
wkup[43]	251	1		T106	21		T133	30		T90	21
wkup[44]	439	1		T17	21		T20	21		T47	42
wkup[45]	254	1		T16	8		T94	21		T154	15
wkup[46]	209	1		T52	21		T35	21		T44	6
wkup[47]	234	1		T15	21		T47	15		T94	21
wkup[48]	168	1		T130	24		T146	15		T55	21
wkup[49]	157	1		T35	21		T90	21		T142	21
wkup[50]	331	1		T19	21		T52	21		T44	39
wkup[51]	207	1		T20	21		T89	8		T128	21
wkup[52]	246	1		T12	15		T19	21		T43	42
wkup[53]	267	1		T35	21		T44	21		T162	21
wkup[54]	281	1		T17	21		T52	21		T35	51
wkup[55]	191	1		T180	21		T137	21		T120	30
wkup[56]	267	1		T35	21		T193	15		T89	6
wkup[57]	358	1		T44	30		T162	21		T47	21
wkup[58]	392	1		T10	21		T19	21		T20	21
wkup[59]	287	1		T32	15		T94	6		T167	21
wkup[60]	386	1		T43	42		T46	21		T106	21
wkup[61]	212	1		T4	15		T43	15		T130	21
wkup[62]	245	1		T17	21		T43	21		T109	21
wkup[63]	372	1		T35	21		T113	21		T46	21
wkup_0	3668	1		T1	5		T2	14		T3	14