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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.53 99.33 93.67 100.00 98.40 99.51 52.31


Total test records in report: 426
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T160 /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3095234298 Jun 25 05:45:59 PM PDT 24 Jun 25 05:50:03 PM PDT 24 33537992197 ps
T41 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4212413107 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:58 PM PDT 24 558218460 ps
T289 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.222528115 Jun 25 05:47:48 PM PDT 24 Jun 25 05:47:51 PM PDT 24 624870906 ps
T290 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.822590575 Jun 25 05:48:02 PM PDT 24 Jun 25 05:48:03 PM PDT 24 519355736 ps
T291 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2307984315 Jun 25 05:48:04 PM PDT 24 Jun 25 05:48:07 PM PDT 24 425546803 ps
T36 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.957525553 Jun 25 05:47:30 PM PDT 24 Jun 25 05:47:32 PM PDT 24 2877083253 ps
T292 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3446058811 Jun 25 05:47:49 PM PDT 24 Jun 25 05:47:52 PM PDT 24 406428765 ps
T293 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4293221183 Jun 25 05:47:04 PM PDT 24 Jun 25 05:47:06 PM PDT 24 448052071 ps
T294 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.528983180 Jun 25 05:47:39 PM PDT 24 Jun 25 05:47:41 PM PDT 24 363184466 ps
T295 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1633165837 Jun 25 05:47:38 PM PDT 24 Jun 25 05:47:41 PM PDT 24 500821184 ps
T296 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.984730642 Jun 25 05:48:07 PM PDT 24 Jun 25 05:48:08 PM PDT 24 459327234 ps
T42 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.251797795 Jun 25 05:47:23 PM PDT 24 Jun 25 05:47:26 PM PDT 24 1425925703 ps
T297 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3205120374 Jun 25 05:47:31 PM PDT 24 Jun 25 05:47:34 PM PDT 24 513020767 ps
T298 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.679357257 Jun 25 05:47:04 PM PDT 24 Jun 25 05:47:06 PM PDT 24 490811793 ps
T299 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1628355262 Jun 25 05:47:22 PM PDT 24 Jun 25 05:47:24 PM PDT 24 527426064 ps
T37 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1379714665 Jun 25 05:47:23 PM PDT 24 Jun 25 05:47:28 PM PDT 24 8254950686 ps
T300 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1667249721 Jun 25 05:48:03 PM PDT 24 Jun 25 05:48:05 PM PDT 24 282725347 ps
T38 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3167639200 Jun 25 05:47:24 PM PDT 24 Jun 25 05:47:26 PM PDT 24 542139618 ps
T301 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2456935308 Jun 25 05:47:56 PM PDT 24 Jun 25 05:47:58 PM PDT 24 539546904 ps
T57 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2989620562 Jun 25 05:47:21 PM PDT 24 Jun 25 05:47:28 PM PDT 24 11979624008 ps
T302 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.4264795300 Jun 25 05:47:22 PM PDT 24 Jun 25 05:47:25 PM PDT 24 330286699 ps
T210 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4153211923 Jun 25 05:47:14 PM PDT 24 Jun 25 05:47:50 PM PDT 24 13809264514 ps
T58 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.63074817 Jun 25 05:47:23 PM PDT 24 Jun 25 05:47:26 PM PDT 24 467585664 ps
T303 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3614130642 Jun 25 05:47:47 PM PDT 24 Jun 25 05:47:49 PM PDT 24 473752314 ps
T304 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3343577949 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:57 PM PDT 24 386587452 ps
T59 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1941483798 Jun 25 05:47:22 PM PDT 24 Jun 25 05:47:24 PM PDT 24 366696607 ps
T39 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1716493108 Jun 25 05:47:25 PM PDT 24 Jun 25 05:47:28 PM PDT 24 4139771773 ps
T81 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3272617949 Jun 25 05:47:56 PM PDT 24 Jun 25 05:48:01 PM PDT 24 1248859061 ps
T305 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1801133144 Jun 25 05:47:33 PM PDT 24 Jun 25 05:47:35 PM PDT 24 310964015 ps
T40 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3530619934 Jun 25 05:47:29 PM PDT 24 Jun 25 05:47:37 PM PDT 24 7959363684 ps
T306 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2662527963 Jun 25 05:47:29 PM PDT 24 Jun 25 05:47:31 PM PDT 24 493297251 ps
T307 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3122740401 Jun 25 05:48:02 PM PDT 24 Jun 25 05:48:04 PM PDT 24 442700710 ps
T308 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.459606258 Jun 25 05:47:54 PM PDT 24 Jun 25 05:47:56 PM PDT 24 332115060 ps
T309 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1743889825 Jun 25 05:47:24 PM PDT 24 Jun 25 05:47:27 PM PDT 24 366844459 ps
T310 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2383678250 Jun 25 05:47:57 PM PDT 24 Jun 25 05:47:59 PM PDT 24 367132395 ps
T204 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1901202926 Jun 25 05:47:23 PM PDT 24 Jun 25 05:47:28 PM PDT 24 7687391179 ps
T311 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1748101678 Jun 25 05:48:03 PM PDT 24 Jun 25 05:48:05 PM PDT 24 288871526 ps
T82 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2783693624 Jun 25 05:47:26 PM PDT 24 Jun 25 05:47:29 PM PDT 24 2808914246 ps
T312 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2837243532 Jun 25 05:47:45 PM PDT 24 Jun 25 05:47:47 PM PDT 24 420910869 ps
T313 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.203665979 Jun 25 05:48:05 PM PDT 24 Jun 25 05:48:07 PM PDT 24 381117264 ps
T314 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2585848309 Jun 25 05:47:07 PM PDT 24 Jun 25 05:47:10 PM PDT 24 659996496 ps
T315 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2329366223 Jun 25 05:47:15 PM PDT 24 Jun 25 05:47:17 PM PDT 24 348551640 ps
T316 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2129320414 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:58 PM PDT 24 579882864 ps
T317 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1088743287 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:57 PM PDT 24 623286058 ps
T60 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1540403323 Jun 25 05:47:32 PM PDT 24 Jun 25 05:47:34 PM PDT 24 614584285 ps
T203 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.904314002 Jun 25 05:47:48 PM PDT 24 Jun 25 05:47:54 PM PDT 24 3687445748 ps
T318 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1375887917 Jun 25 05:48:06 PM PDT 24 Jun 25 05:48:08 PM PDT 24 389004443 ps
T83 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.770778176 Jun 25 05:47:21 PM PDT 24 Jun 25 05:47:24 PM PDT 24 2631581668 ps
T319 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1222531181 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:57 PM PDT 24 298125049 ps
T84 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2347299014 Jun 25 05:47:24 PM PDT 24 Jun 25 05:47:27 PM PDT 24 1142695723 ps
T320 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1794734879 Jun 25 05:48:03 PM PDT 24 Jun 25 05:48:05 PM PDT 24 441223270 ps
T321 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.701995344 Jun 25 05:47:13 PM PDT 24 Jun 25 05:47:15 PM PDT 24 379496445 ps
T85 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.684540324 Jun 25 05:47:52 PM PDT 24 Jun 25 05:47:54 PM PDT 24 502693725 ps
T86 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3888290656 Jun 25 05:47:31 PM PDT 24 Jun 25 05:47:35 PM PDT 24 924191931 ps
T322 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3438515496 Jun 25 05:47:22 PM PDT 24 Jun 25 05:47:25 PM PDT 24 314884922 ps
T61 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4128488445 Jun 25 05:47:24 PM PDT 24 Jun 25 05:47:28 PM PDT 24 1338037246 ps
T323 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.484754709 Jun 25 05:47:21 PM PDT 24 Jun 25 05:47:25 PM PDT 24 574206203 ps
T62 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1865761200 Jun 25 05:47:57 PM PDT 24 Jun 25 05:47:59 PM PDT 24 498646116 ps
T324 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2662045374 Jun 25 05:47:45 PM PDT 24 Jun 25 05:47:46 PM PDT 24 292673039 ps
T325 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3064757672 Jun 25 05:47:57 PM PDT 24 Jun 25 05:47:59 PM PDT 24 286780894 ps
T326 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2795012118 Jun 25 05:47:30 PM PDT 24 Jun 25 05:47:32 PM PDT 24 471654316 ps
T327 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.152075554 Jun 25 05:47:24 PM PDT 24 Jun 25 05:47:30 PM PDT 24 7894376253 ps
T328 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.638172444 Jun 25 05:47:24 PM PDT 24 Jun 25 05:47:27 PM PDT 24 381584638 ps
T329 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2809059351 Jun 25 05:47:45 PM PDT 24 Jun 25 05:47:47 PM PDT 24 710923723 ps
T330 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2818391233 Jun 25 05:47:15 PM PDT 24 Jun 25 05:47:17 PM PDT 24 442457144 ps
T331 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.101733807 Jun 25 05:47:06 PM PDT 24 Jun 25 05:47:10 PM PDT 24 470992452 ps
T332 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4092741925 Jun 25 05:47:04 PM PDT 24 Jun 25 05:47:15 PM PDT 24 14240465409 ps
T333 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4055473827 Jun 25 05:48:05 PM PDT 24 Jun 25 05:48:07 PM PDT 24 326465070 ps
T334 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.893297982 Jun 25 05:47:56 PM PDT 24 Jun 25 05:47:58 PM PDT 24 411256496 ps
T87 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2378206319 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:58 PM PDT 24 1706862801 ps
T335 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1205421161 Jun 25 05:47:31 PM PDT 24 Jun 25 05:47:33 PM PDT 24 520168678 ps
T336 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3049768152 Jun 25 05:47:46 PM PDT 24 Jun 25 05:47:48 PM PDT 24 555837710 ps
T337 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.532856771 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:57 PM PDT 24 431474441 ps
T67 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.225842703 Jun 25 05:47:16 PM PDT 24 Jun 25 05:47:19 PM PDT 24 304743296 ps
T338 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2167857366 Jun 25 05:48:04 PM PDT 24 Jun 25 05:48:06 PM PDT 24 375340429 ps
T339 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3055766050 Jun 25 05:47:24 PM PDT 24 Jun 25 05:47:26 PM PDT 24 623457700 ps
T205 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.134432656 Jun 25 05:47:36 PM PDT 24 Jun 25 05:47:50 PM PDT 24 9044393576 ps
T340 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.719410794 Jun 25 05:47:23 PM PDT 24 Jun 25 05:47:25 PM PDT 24 340411723 ps
T341 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3892209421 Jun 25 05:47:16 PM PDT 24 Jun 25 05:47:19 PM PDT 24 584272160 ps
T342 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.375251952 Jun 25 05:47:24 PM PDT 24 Jun 25 05:47:26 PM PDT 24 380975933 ps
T207 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2832061940 Jun 25 05:47:54 PM PDT 24 Jun 25 05:47:58 PM PDT 24 4502932765 ps
T343 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2326041436 Jun 25 05:47:22 PM PDT 24 Jun 25 05:47:25 PM PDT 24 564212757 ps
T88 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1940498318 Jun 25 05:47:40 PM PDT 24 Jun 25 05:47:44 PM PDT 24 1170776803 ps
T344 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2748738499 Jun 25 05:47:44 PM PDT 24 Jun 25 05:47:48 PM PDT 24 1990040270 ps
T345 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.242412676 Jun 25 05:47:23 PM PDT 24 Jun 25 05:47:25 PM PDT 24 292901765 ps
T346 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.90979418 Jun 25 05:47:21 PM PDT 24 Jun 25 05:47:22 PM PDT 24 457170953 ps
T347 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3056488430 Jun 25 05:48:04 PM PDT 24 Jun 25 05:48:06 PM PDT 24 490115601 ps
T348 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.829702339 Jun 25 05:47:14 PM PDT 24 Jun 25 05:47:17 PM PDT 24 331990307 ps
T349 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4186721160 Jun 25 05:47:29 PM PDT 24 Jun 25 05:47:31 PM PDT 24 534311059 ps
T350 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1055830214 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:57 PM PDT 24 303334532 ps
T351 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4033647113 Jun 25 05:47:23 PM PDT 24 Jun 25 05:47:26 PM PDT 24 547886113 ps
T352 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3696916332 Jun 25 05:47:53 PM PDT 24 Jun 25 05:47:56 PM PDT 24 2828370597 ps
T353 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.478734812 Jun 25 05:47:15 PM PDT 24 Jun 25 05:47:17 PM PDT 24 384606454 ps
T354 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3562316390 Jun 25 05:47:54 PM PDT 24 Jun 25 05:48:05 PM PDT 24 7975986682 ps
T355 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3849404191 Jun 25 05:47:24 PM PDT 24 Jun 25 05:47:27 PM PDT 24 459926185 ps
T356 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.278133710 Jun 25 05:47:32 PM PDT 24 Jun 25 05:47:34 PM PDT 24 406219262 ps
T357 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2428499892 Jun 25 05:47:54 PM PDT 24 Jun 25 05:47:56 PM PDT 24 413650287 ps
T358 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2722053384 Jun 25 05:48:04 PM PDT 24 Jun 25 05:48:07 PM PDT 24 490312887 ps
T359 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2520989517 Jun 25 05:47:46 PM PDT 24 Jun 25 05:47:47 PM PDT 24 375873300 ps
T360 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4034082475 Jun 25 05:47:06 PM PDT 24 Jun 25 05:47:16 PM PDT 24 2950336293 ps
T361 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.765023910 Jun 25 05:47:54 PM PDT 24 Jun 25 05:47:55 PM PDT 24 443249100 ps
T362 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.366267145 Jun 25 05:47:44 PM PDT 24 Jun 25 05:47:46 PM PDT 24 562684478 ps
T363 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2570789885 Jun 25 05:47:30 PM PDT 24 Jun 25 05:47:32 PM PDT 24 421478996 ps
T364 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3762596022 Jun 25 05:47:47 PM PDT 24 Jun 25 05:47:50 PM PDT 24 2300214239 ps
T365 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1655312481 Jun 25 05:47:26 PM PDT 24 Jun 25 05:47:28 PM PDT 24 446041804 ps
T366 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2100231259 Jun 25 05:48:03 PM PDT 24 Jun 25 05:48:04 PM PDT 24 295431005 ps
T367 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.966023691 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:58 PM PDT 24 350222474 ps
T368 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1453789350 Jun 25 05:47:30 PM PDT 24 Jun 25 05:47:32 PM PDT 24 297574184 ps
T369 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2616123864 Jun 25 05:47:54 PM PDT 24 Jun 25 05:47:59 PM PDT 24 2550840085 ps
T68 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2634572893 Jun 25 05:47:15 PM PDT 24 Jun 25 05:47:17 PM PDT 24 495329171 ps
T63 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2566015238 Jun 25 05:47:56 PM PDT 24 Jun 25 05:47:58 PM PDT 24 428229776 ps
T370 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1452941486 Jun 25 05:47:14 PM PDT 24 Jun 25 05:47:16 PM PDT 24 463051306 ps
T371 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3521410265 Jun 25 05:47:44 PM PDT 24 Jun 25 05:47:45 PM PDT 24 288373366 ps
T69 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1131572198 Jun 25 05:47:24 PM PDT 24 Jun 25 05:47:32 PM PDT 24 5204527044 ps
T64 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.511161792 Jun 25 05:47:46 PM PDT 24 Jun 25 05:47:47 PM PDT 24 478775042 ps
T372 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.602408815 Jun 25 05:47:14 PM PDT 24 Jun 25 05:47:16 PM PDT 24 400431556 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1955941960 Jun 25 05:47:04 PM PDT 24 Jun 25 05:47:06 PM PDT 24 297665358 ps
T374 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3172543474 Jun 25 05:47:22 PM PDT 24 Jun 25 05:47:24 PM PDT 24 1157983976 ps
T375 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.987508583 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:57 PM PDT 24 415616518 ps
T376 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3175982096 Jun 25 05:47:05 PM PDT 24 Jun 25 05:47:07 PM PDT 24 455288751 ps
T377 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3190950813 Jun 25 05:47:47 PM PDT 24 Jun 25 05:47:54 PM PDT 24 4374504587 ps
T378 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2185639533 Jun 25 05:47:15 PM PDT 24 Jun 25 05:47:18 PM PDT 24 551593470 ps
T379 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4145921062 Jun 25 05:47:46 PM PDT 24 Jun 25 05:47:49 PM PDT 24 657405360 ps
T380 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3457084952 Jun 25 05:48:03 PM PDT 24 Jun 25 05:48:04 PM PDT 24 378537356 ps
T381 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3126974570 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:58 PM PDT 24 580849139 ps
T382 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.910140260 Jun 25 05:47:40 PM PDT 24 Jun 25 05:47:44 PM PDT 24 502852612 ps
T383 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1781838843 Jun 25 05:47:13 PM PDT 24 Jun 25 05:47:18 PM PDT 24 2303566864 ps
T70 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3494941081 Jun 25 05:47:41 PM PDT 24 Jun 25 05:47:42 PM PDT 24 498043703 ps
T384 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1180929029 Jun 25 05:47:39 PM PDT 24 Jun 25 05:47:41 PM PDT 24 469387498 ps
T385 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.334719309 Jun 25 05:47:45 PM PDT 24 Jun 25 05:47:51 PM PDT 24 5122047510 ps
T386 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2610598086 Jun 25 05:47:30 PM PDT 24 Jun 25 05:47:32 PM PDT 24 492944384 ps
T387 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1644362757 Jun 25 05:47:33 PM PDT 24 Jun 25 05:47:37 PM PDT 24 476668324 ps
T71 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.320151764 Jun 25 05:47:26 PM PDT 24 Jun 25 05:47:28 PM PDT 24 664729061 ps
T388 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1831690152 Jun 25 05:47:46 PM PDT 24 Jun 25 05:47:51 PM PDT 24 1565390165 ps
T389 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.787894433 Jun 25 05:47:44 PM PDT 24 Jun 25 05:47:47 PM PDT 24 388391389 ps
T390 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1919424906 Jun 25 05:47:23 PM PDT 24 Jun 25 05:47:27 PM PDT 24 1509918266 ps
T391 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4164878442 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:57 PM PDT 24 344613667 ps
T392 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3270631236 Jun 25 05:48:06 PM PDT 24 Jun 25 05:48:08 PM PDT 24 412392511 ps
T393 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2325293473 Jun 25 05:47:38 PM PDT 24 Jun 25 05:47:40 PM PDT 24 404840658 ps
T394 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3471976111 Jun 25 05:47:14 PM PDT 24 Jun 25 05:47:16 PM PDT 24 783485896 ps
T395 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1407043923 Jun 25 05:47:54 PM PDT 24 Jun 25 05:47:56 PM PDT 24 382825352 ps
T396 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.505787477 Jun 25 05:48:04 PM PDT 24 Jun 25 05:48:06 PM PDT 24 489170017 ps
T397 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3172293202 Jun 25 05:47:24 PM PDT 24 Jun 25 05:47:27 PM PDT 24 472437631 ps
T398 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2025847472 Jun 25 05:47:48 PM PDT 24 Jun 25 05:47:49 PM PDT 24 511257775 ps
T399 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.404414502 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:59 PM PDT 24 499021655 ps
T400 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.237846945 Jun 25 05:47:43 PM PDT 24 Jun 25 05:47:45 PM PDT 24 528820250 ps
T401 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3444363543 Jun 25 05:47:53 PM PDT 24 Jun 25 05:47:55 PM PDT 24 5045572205 ps
T402 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1181498972 Jun 25 05:47:08 PM PDT 24 Jun 25 05:47:09 PM PDT 24 1000053333 ps
T403 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1559551738 Jun 25 05:47:50 PM PDT 24 Jun 25 05:47:52 PM PDT 24 1963345673 ps
T208 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4124954337 Jun 25 05:47:03 PM PDT 24 Jun 25 05:47:11 PM PDT 24 4556587690 ps
T206 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.414080041 Jun 25 05:47:45 PM PDT 24 Jun 25 05:47:58 PM PDT 24 8602523102 ps
T404 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1037130387 Jun 25 05:47:15 PM PDT 24 Jun 25 05:47:20 PM PDT 24 4591300509 ps
T405 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2679825607 Jun 25 05:47:13 PM PDT 24 Jun 25 05:47:16 PM PDT 24 4608469180 ps
T406 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1419650820 Jun 25 05:47:31 PM PDT 24 Jun 25 05:47:33 PM PDT 24 326509672 ps
T407 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4084890680 Jun 25 05:47:23 PM PDT 24 Jun 25 05:47:26 PM PDT 24 357071429 ps
T408 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4093586973 Jun 25 05:47:29 PM PDT 24 Jun 25 05:47:32 PM PDT 24 4180846617 ps
T409 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3615757610 Jun 25 05:47:39 PM PDT 24 Jun 25 05:47:40 PM PDT 24 536531475 ps
T410 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3914984775 Jun 25 05:47:15 PM PDT 24 Jun 25 05:47:22 PM PDT 24 7169245068 ps
T411 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4281673181 Jun 25 05:48:04 PM PDT 24 Jun 25 05:48:06 PM PDT 24 310692966 ps
T412 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4141510391 Jun 25 05:47:49 PM PDT 24 Jun 25 05:47:51 PM PDT 24 528990235 ps
T413 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2499011032 Jun 25 05:47:55 PM PDT 24 Jun 25 05:47:57 PM PDT 24 462798037 ps
T414 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.394778583 Jun 25 05:48:06 PM PDT 24 Jun 25 05:48:08 PM PDT 24 450949086 ps
T415 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1811881669 Jun 25 05:47:47 PM PDT 24 Jun 25 05:48:01 PM PDT 24 8008030891 ps
T416 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.213012926 Jun 25 05:47:37 PM PDT 24 Jun 25 05:47:50 PM PDT 24 8746617868 ps
T417 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3936648130 Jun 25 05:47:16 PM PDT 24 Jun 25 05:47:20 PM PDT 24 1094367673 ps
T418 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1068764405 Jun 25 05:47:22 PM PDT 24 Jun 25 05:47:25 PM PDT 24 2247383636 ps
T419 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1666026018 Jun 25 05:47:30 PM PDT 24 Jun 25 05:47:34 PM PDT 24 1258224247 ps
T420 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.794822832 Jun 25 05:47:29 PM PDT 24 Jun 25 05:47:33 PM PDT 24 4028171657 ps
T421 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4183385188 Jun 25 05:47:46 PM PDT 24 Jun 25 05:47:48 PM PDT 24 404143614 ps
T422 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2898035235 Jun 25 05:47:12 PM PDT 24 Jun 25 05:47:14 PM PDT 24 430912993 ps
T65 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.162574173 Jun 25 05:47:47 PM PDT 24 Jun 25 05:47:49 PM PDT 24 461660159 ps
T423 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.958001011 Jun 25 05:47:23 PM PDT 24 Jun 25 05:47:25 PM PDT 24 318834502 ps
T424 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3563816629 Jun 25 05:47:38 PM PDT 24 Jun 25 05:47:43 PM PDT 24 2037851596 ps
T425 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.686805578 Jun 25 05:47:54 PM PDT 24 Jun 25 05:47:56 PM PDT 24 370910607 ps
T426 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2540291726 Jun 25 05:47:45 PM PDT 24 Jun 25 05:47:48 PM PDT 24 490479039 ps
T66 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.11511628 Jun 25 05:47:17 PM PDT 24 Jun 25 05:47:19 PM PDT 24 500008782 ps

Test location /workspace/coverage/default/9.aon_timer_jump.3478246742
Short name T7
Test name
Test status
Simulation time 573555087 ps
CPU time 1.06 seconds
Started Jun 25 05:46:09 PM PDT 24
Finished Jun 25 05:46:12 PM PDT 24
Peak memory 196332 kb
Host smart-595b5424-7d80-4f42-9ce9-09a30af94e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478246742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3478246742
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2465686377
Short name T20
Test name
Test status
Simulation time 36540363423 ps
CPU time 285.5 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:51:46 PM PDT 24
Peak memory 206648 kb
Host smart-245b84a4-ca76-4f3e-913c-ae344a8ca3e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465686377 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2465686377
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.745901915
Short name T2
Test name
Test status
Simulation time 41442746816 ps
CPU time 12.59 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:46:12 PM PDT 24
Peak memory 192744 kb
Host smart-e8c5124b-65d3-4436-986d-1c3f9530ec7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745901915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.745901915
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1379714665
Short name T37
Test name
Test status
Simulation time 8254950686 ps
CPU time 2.99 seconds
Started Jun 25 05:47:23 PM PDT 24
Finished Jun 25 05:47:28 PM PDT 24
Peak memory 198288 kb
Host smart-d7f753c4-2334-4ec5-9b25-ba173d651a68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379714665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1379714665
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.469809465
Short name T55
Test name
Test status
Simulation time 339873994718 ps
CPU time 911.17 seconds
Started Jun 25 05:46:47 PM PDT 24
Finished Jun 25 06:01:59 PM PDT 24
Peak memory 214840 kb
Host smart-6a981175-a265-44be-b009-b781e734afe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469809465 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.469809465
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.917228341
Short name T47
Test name
Test status
Simulation time 137420997939 ps
CPU time 578.02 seconds
Started Jun 25 05:46:28 PM PDT 24
Finished Jun 25 05:56:07 PM PDT 24
Peak memory 214324 kb
Host smart-d5c3c250-9a04-471b-96a4-1ed10a81f3c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917228341 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.917228341
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3973335328
Short name T92
Test name
Test status
Simulation time 66017372405 ps
CPU time 673.73 seconds
Started Jun 25 05:46:40 PM PDT 24
Finished Jun 25 05:57:55 PM PDT 24
Peak memory 212852 kb
Host smart-47a2d172-ff8e-44cb-8e59-06a54f5ffcf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973335328 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3973335328
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.702898876
Short name T46
Test name
Test status
Simulation time 84463982107 ps
CPU time 886.34 seconds
Started Jun 25 05:46:58 PM PDT 24
Finished Jun 25 06:01:45 PM PDT 24
Peak memory 214824 kb
Host smart-ce56134a-84d9-4cdb-aca2-2b46fd5e7236
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702898876 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.702898876
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3301360489
Short name T127
Test name
Test status
Simulation time 38270333753 ps
CPU time 431.76 seconds
Started Jun 25 05:46:00 PM PDT 24
Finished Jun 25 05:53:13 PM PDT 24
Peak memory 208008 kb
Host smart-7b45ecda-05c7-42e2-8ebf-b049c235cc45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301360489 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3301360489
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1375262599
Short name T101
Test name
Test status
Simulation time 131268236936 ps
CPU time 41.71 seconds
Started Jun 25 05:46:02 PM PDT 24
Finished Jun 25 05:46:45 PM PDT 24
Peak memory 192316 kb
Host smart-47e38523-762c-4d32-81f3-e99020471075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375262599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1375262599
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3095234298
Short name T160
Test name
Test status
Simulation time 33537992197 ps
CPU time 243.26 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:50:03 PM PDT 24
Peak memory 213796 kb
Host smart-9f27f918-2c62-480a-be4d-064c61f6b625
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095234298 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3095234298
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2820435297
Short name T22
Test name
Test status
Simulation time 8275466422 ps
CPU time 1.7 seconds
Started Jun 25 05:46:02 PM PDT 24
Finished Jun 25 05:46:04 PM PDT 24
Peak memory 215796 kb
Host smart-f4f47181-be1c-4a95-811e-d6de01246d18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820435297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2820435297
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.679877502
Short name T111
Test name
Test status
Simulation time 130134607093 ps
CPU time 48.56 seconds
Started Jun 25 05:46:23 PM PDT 24
Finished Jun 25 05:47:13 PM PDT 24
Peak memory 191792 kb
Host smart-2a686376-4dc9-4c36-8669-1756b69fb895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679877502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.679877502
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1908604467
Short name T43
Test name
Test status
Simulation time 79115543737 ps
CPU time 322.36 seconds
Started Jun 25 05:46:52 PM PDT 24
Finished Jun 25 05:52:15 PM PDT 24
Peak memory 209224 kb
Host smart-f8167e53-7836-4c2d-ab63-5f840951423f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908604467 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1908604467
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.4018544850
Short name T117
Test name
Test status
Simulation time 50797929951 ps
CPU time 327.82 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:51:38 PM PDT 24
Peak memory 214024 kb
Host smart-dc70d14d-4cb6-453c-8f6e-14475230bc8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018544850 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.4018544850
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3670955856
Short name T52
Test name
Test status
Simulation time 4372389220 ps
CPU time 6.8 seconds
Started Jun 25 05:46:37 PM PDT 24
Finished Jun 25 05:46:44 PM PDT 24
Peak memory 192816 kb
Host smart-3ed65cca-886e-4d21-af0e-3abfc734d1d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670955856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3670955856
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.836567616
Short name T142
Test name
Test status
Simulation time 26003575174 ps
CPU time 10.9 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:21 PM PDT 24
Peak memory 198260 kb
Host smart-d80f6810-3008-4fd0-b04e-c30349688299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836567616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.836567616
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1223621657
Short name T15
Test name
Test status
Simulation time 38583226816 ps
CPU time 26.06 seconds
Started Jun 25 05:46:38 PM PDT 24
Finished Jun 25 05:47:05 PM PDT 24
Peak memory 192344 kb
Host smart-5ae1cbad-b2af-4378-9ba8-a13db08b7164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223621657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1223621657
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1907144267
Short name T44
Test name
Test status
Simulation time 223179006099 ps
CPU time 494.11 seconds
Started Jun 25 05:47:04 PM PDT 24
Finished Jun 25 05:55:19 PM PDT 24
Peak memory 204008 kb
Host smart-db6ad1e2-870f-49b0-92f1-c9ee7b156d2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907144267 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1907144267
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3342815838
Short name T99
Test name
Test status
Simulation time 19454080692 ps
CPU time 84.1 seconds
Started Jun 25 05:46:06 PM PDT 24
Finished Jun 25 05:47:31 PM PDT 24
Peak memory 198716 kb
Host smart-60c82b16-60c1-480d-a2f6-82ca71a7dd8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342815838 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3342815838
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2465808793
Short name T120
Test name
Test status
Simulation time 45963411786 ps
CPU time 490.74 seconds
Started Jun 25 05:46:14 PM PDT 24
Finished Jun 25 05:54:25 PM PDT 24
Peak memory 214144 kb
Host smart-0b4f2319-9d3c-423b-8913-0277f42e6923
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465808793 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2465808793
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.4099171230
Short name T106
Test name
Test status
Simulation time 113018822317 ps
CPU time 151.5 seconds
Started Jun 25 05:46:58 PM PDT 24
Finished Jun 25 05:49:31 PM PDT 24
Peak memory 198052 kb
Host smart-05b90942-344c-4ea6-b9fb-1806ae0233e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099171230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.4099171230
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3096260772
Short name T91
Test name
Test status
Simulation time 175119333179 ps
CPU time 408.5 seconds
Started Jun 25 05:46:14 PM PDT 24
Finished Jun 25 05:53:05 PM PDT 24
Peak memory 211048 kb
Host smart-75d012e7-9775-49bc-95d7-364a4d324f0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096260772 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3096260772
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1901385635
Short name T93
Test name
Test status
Simulation time 85305322171 ps
CPU time 491.08 seconds
Started Jun 25 05:46:39 PM PDT 24
Finished Jun 25 05:54:51 PM PDT 24
Peak memory 211920 kb
Host smart-77368f52-5fa5-49e6-b979-92e96096b196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901385635 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1901385635
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.4202744146
Short name T119
Test name
Test status
Simulation time 81617918787 ps
CPU time 9.49 seconds
Started Jun 25 05:46:33 PM PDT 24
Finished Jun 25 05:46:44 PM PDT 24
Peak memory 192724 kb
Host smart-9c237dbf-75c0-44ae-ad57-b15e6c672867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202744146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.4202744146
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.543233808
Short name T130
Test name
Test status
Simulation time 91466221171 ps
CPU time 122.59 seconds
Started Jun 25 05:46:09 PM PDT 24
Finished Jun 25 05:48:13 PM PDT 24
Peak memory 192304 kb
Host smart-511fffb1-0d51-4bad-9d7b-35a7e88048ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543233808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.543233808
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.307021766
Short name T90
Test name
Test status
Simulation time 528021503711 ps
CPU time 441.9 seconds
Started Jun 25 05:46:31 PM PDT 24
Finished Jun 25 05:53:53 PM PDT 24
Peak memory 202912 kb
Host smart-11186846-c5d7-4811-af46-ef90c8c5d446
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307021766 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.307021766
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3605363116
Short name T110
Test name
Test status
Simulation time 141803706676 ps
CPU time 141.34 seconds
Started Jun 25 05:46:58 PM PDT 24
Finished Jun 25 05:49:20 PM PDT 24
Peak memory 192424 kb
Host smart-f93bedb5-7783-45dc-a0a8-b280e7ee87d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605363116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3605363116
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2804668018
Short name T35
Test name
Test status
Simulation time 24750805025 ps
CPU time 192.4 seconds
Started Jun 25 05:45:57 PM PDT 24
Finished Jun 25 05:49:10 PM PDT 24
Peak memory 206620 kb
Host smart-8a045a43-54bc-4dfd-84f1-3cf6ea1ae07e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804668018 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2804668018
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1951662593
Short name T124
Test name
Test status
Simulation time 25479422109 ps
CPU time 292.77 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:51:54 PM PDT 24
Peak memory 198456 kb
Host smart-9a187b0a-833a-4fbd-85c1-508fa805a90c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951662593 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1951662593
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3953481351
Short name T108
Test name
Test status
Simulation time 5894331658 ps
CPU time 3.11 seconds
Started Jun 25 05:46:22 PM PDT 24
Finished Jun 25 05:46:26 PM PDT 24
Peak memory 184036 kb
Host smart-a01840a5-e43f-4a5c-99fb-93c7c4080753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953481351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3953481351
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2991197858
Short name T48
Test name
Test status
Simulation time 98523226262 ps
CPU time 159.61 seconds
Started Jun 25 05:46:15 PM PDT 24
Finished Jun 25 05:48:56 PM PDT 24
Peak memory 199756 kb
Host smart-23f532f3-2287-478f-9326-22beaf102a04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991197858 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2991197858
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1713729449
Short name T156
Test name
Test status
Simulation time 170442358660 ps
CPU time 363 seconds
Started Jun 25 05:46:30 PM PDT 24
Finished Jun 25 05:52:34 PM PDT 24
Peak memory 202308 kb
Host smart-4007dc15-2ec5-4c2f-93bc-ec05400270b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713729449 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1713729449
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2388918204
Short name T122
Test name
Test status
Simulation time 303021850247 ps
CPU time 208.47 seconds
Started Jun 25 05:46:06 PM PDT 24
Finished Jun 25 05:49:36 PM PDT 24
Peak memory 198092 kb
Host smart-6ba83091-72f5-4e95-8311-18913fc1ebdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388918204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2388918204
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3279301464
Short name T128
Test name
Test status
Simulation time 114856393141 ps
CPU time 248.34 seconds
Started Jun 25 05:47:08 PM PDT 24
Finished Jun 25 05:51:17 PM PDT 24
Peak memory 200616 kb
Host smart-d4e3f9a5-409d-4662-aef2-0e47ece84cf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279301464 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3279301464
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1540403323
Short name T60
Test name
Test status
Simulation time 614584285 ps
CPU time 0.69 seconds
Started Jun 25 05:47:32 PM PDT 24
Finished Jun 25 05:47:34 PM PDT 24
Peak memory 193352 kb
Host smart-69dbbe06-0338-4a44-9cfe-189e08f9ecf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540403323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1540403323
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2502699231
Short name T17
Test name
Test status
Simulation time 237578114225 ps
CPU time 160.02 seconds
Started Jun 25 05:46:17 PM PDT 24
Finished Jun 25 05:48:59 PM PDT 24
Peak memory 191712 kb
Host smart-27dace44-6eea-40dd-bf09-8ccbcd57c351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502699231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2502699231
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2844085765
Short name T118
Test name
Test status
Simulation time 101930175164 ps
CPU time 30.87 seconds
Started Jun 25 05:47:05 PM PDT 24
Finished Jun 25 05:47:37 PM PDT 24
Peak memory 192828 kb
Host smart-fc51581d-1a79-4d16-854c-cf9f1c8d97f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844085765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2844085765
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1008001235
Short name T166
Test name
Test status
Simulation time 325919216865 ps
CPU time 308.35 seconds
Started Jun 25 05:46:01 PM PDT 24
Finished Jun 25 05:51:11 PM PDT 24
Peak memory 201560 kb
Host smart-86bf8ff8-07e5-438f-be18-bf010001a270
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008001235 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1008001235
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3320786213
Short name T147
Test name
Test status
Simulation time 124116027092 ps
CPU time 259.12 seconds
Started Jun 25 05:46:07 PM PDT 24
Finished Jun 25 05:50:28 PM PDT 24
Peak memory 206644 kb
Host smart-33034507-fa79-4f8f-b589-f582462e9d80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320786213 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3320786213
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.305995696
Short name T172
Test name
Test status
Simulation time 90747584681 ps
CPU time 956.08 seconds
Started Jun 25 05:46:33 PM PDT 24
Finished Jun 25 06:02:30 PM PDT 24
Peak memory 214780 kb
Host smart-ba819368-67fc-43bd-a5ff-b5972ab0c337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305995696 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.305995696
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1871654294
Short name T107
Test name
Test status
Simulation time 156649916333 ps
CPU time 625.52 seconds
Started Jun 25 05:47:07 PM PDT 24
Finished Jun 25 05:57:34 PM PDT 24
Peak memory 213552 kb
Host smart-a7605001-16b9-4746-ac12-73aaf0cb2801
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871654294 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1871654294
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1050412223
Short name T105
Test name
Test status
Simulation time 164894982961 ps
CPU time 62.74 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:47:13 PM PDT 24
Peak memory 198084 kb
Host smart-2f00b638-b63f-4817-8821-4e745f13b8fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050412223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1050412223
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.794465524
Short name T133
Test name
Test status
Simulation time 3937947845 ps
CPU time 2.56 seconds
Started Jun 25 05:46:34 PM PDT 24
Finished Jun 25 05:46:38 PM PDT 24
Peak memory 198020 kb
Host smart-9f85f71b-c18f-4d3e-b813-9b69e300b94a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794465524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.794465524
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1724614689
Short name T153
Test name
Test status
Simulation time 199590055000 ps
CPU time 424.55 seconds
Started Jun 25 05:46:51 PM PDT 24
Finished Jun 25 05:53:56 PM PDT 24
Peak memory 211080 kb
Host smart-dd83bb81-9df8-43fd-aa2a-f858f9a1baaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724614689 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1724614689
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.374357007
Short name T94
Test name
Test status
Simulation time 23858562443 ps
CPU time 81.47 seconds
Started Jun 25 05:46:35 PM PDT 24
Finished Jun 25 05:47:58 PM PDT 24
Peak memory 206656 kb
Host smart-e915283b-6dab-4304-8395-016a83302f74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374357007 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.374357007
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1155629963
Short name T115
Test name
Test status
Simulation time 158206296855 ps
CPU time 61 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:47:11 PM PDT 24
Peak memory 192808 kb
Host smart-d1ce1f28-fd0f-4694-b1fc-2a9153b1a744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155629963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1155629963
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2293464370
Short name T104
Test name
Test status
Simulation time 376322942508 ps
CPU time 169.49 seconds
Started Jun 25 05:46:14 PM PDT 24
Finished Jun 25 05:49:05 PM PDT 24
Peak memory 192336 kb
Host smart-6f25b095-5c8d-468d-9d53-9dc8b91ce13d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293464370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2293464370
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1761523982
Short name T102
Test name
Test status
Simulation time 63886519846 ps
CPU time 184.68 seconds
Started Jun 25 05:46:57 PM PDT 24
Finished Jun 25 05:50:03 PM PDT 24
Peak memory 198756 kb
Host smart-7ba28627-ec3d-4dd5-94c2-8c5a6327930a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761523982 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1761523982
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.777895149
Short name T138
Test name
Test status
Simulation time 69893677835 ps
CPU time 27.19 seconds
Started Jun 25 05:47:05 PM PDT 24
Finished Jun 25 05:47:34 PM PDT 24
Peak memory 191712 kb
Host smart-b5f9c230-e475-438b-8d3e-9d467cc89db1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777895149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.777895149
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2787742375
Short name T145
Test name
Test status
Simulation time 119811904953 ps
CPU time 96.2 seconds
Started Jun 25 05:46:31 PM PDT 24
Finished Jun 25 05:48:08 PM PDT 24
Peak memory 191700 kb
Host smart-8fbf148d-eee2-4cbf-87b4-b317077eb788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787742375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2787742375
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2817661578
Short name T131
Test name
Test status
Simulation time 175559639052 ps
CPU time 66.3 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:47:16 PM PDT 24
Peak memory 191940 kb
Host smart-80dc4da0-ea32-4167-9651-269805d8e058
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817661578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2817661578
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3408453091
Short name T126
Test name
Test status
Simulation time 443598261929 ps
CPU time 154.73 seconds
Started Jun 25 05:46:17 PM PDT 24
Finished Jun 25 05:48:53 PM PDT 24
Peak memory 192808 kb
Host smart-ea10e988-7497-4c62-9bb0-900c99d0f549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408453091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3408453091
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3633855142
Short name T109
Test name
Test status
Simulation time 308459670065 ps
CPU time 110.63 seconds
Started Jun 25 05:46:51 PM PDT 24
Finished Jun 25 05:48:42 PM PDT 24
Peak memory 198080 kb
Host smart-67df3f49-704d-4acc-b324-8f065775ecbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633855142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3633855142
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2021847255
Short name T149
Test name
Test status
Simulation time 31395633471 ps
CPU time 23.11 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:47:23 PM PDT 24
Peak memory 198076 kb
Host smart-0cd315db-d90e-4214-8572-9aae29cd5eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021847255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2021847255
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3561172925
Short name T96
Test name
Test status
Simulation time 119947010929 ps
CPU time 481.01 seconds
Started Jun 25 05:47:05 PM PDT 24
Finished Jun 25 05:55:07 PM PDT 24
Peak memory 211964 kb
Host smart-2bd07842-ce06-4083-8f5f-f43fcb7fbef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561172925 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3561172925
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.110061131
Short name T121
Test name
Test status
Simulation time 206993688155 ps
CPU time 305.44 seconds
Started Jun 25 05:46:06 PM PDT 24
Finished Jun 25 05:51:13 PM PDT 24
Peak memory 198044 kb
Host smart-492be7fa-1ddb-4857-a09b-2610bf3f3f5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110061131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.110061131
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1663226475
Short name T144
Test name
Test status
Simulation time 296578839316 ps
CPU time 375.59 seconds
Started Jun 25 05:46:04 PM PDT 24
Finished Jun 25 05:52:21 PM PDT 24
Peak memory 191704 kb
Host smart-2a09f2eb-c0a0-4929-a105-009361c642d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663226475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1663226475
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.429939090
Short name T113
Test name
Test status
Simulation time 240782280620 ps
CPU time 83.48 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:47:23 PM PDT 24
Peak memory 198088 kb
Host smart-68d8a083-7cfb-4648-a874-79cc0711f6e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429939090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.429939090
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.4203860274
Short name T179
Test name
Test status
Simulation time 152238866479 ps
CPU time 47.36 seconds
Started Jun 25 05:47:00 PM PDT 24
Finished Jun 25 05:47:49 PM PDT 24
Peak memory 198084 kb
Host smart-d307314a-fce2-4767-b100-ae93b13268f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203860274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.4203860274
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.4235133822
Short name T175
Test name
Test status
Simulation time 85151486926 ps
CPU time 699.35 seconds
Started Jun 25 05:46:07 PM PDT 24
Finished Jun 25 05:57:48 PM PDT 24
Peak memory 214552 kb
Host smart-43a967ee-5257-45c5-98d7-d0b6a52988d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235133822 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.4235133822
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2451396912
Short name T89
Test name
Test status
Simulation time 166502765617 ps
CPU time 898.81 seconds
Started Jun 25 05:46:29 PM PDT 24
Finished Jun 25 06:01:29 PM PDT 24
Peak memory 207228 kb
Host smart-4d29be25-cd3d-4c6b-a2e1-b16b910efe7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451396912 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2451396912
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3351322360
Short name T163
Test name
Test status
Simulation time 110309041937 ps
CPU time 47.89 seconds
Started Jun 25 05:46:36 PM PDT 24
Finished Jun 25 05:47:25 PM PDT 24
Peak memory 184420 kb
Host smart-94b7676e-d4a6-4310-a60e-67c01368ffe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351322360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3351322360
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.383993356
Short name T162
Test name
Test status
Simulation time 8638481396 ps
CPU time 12.33 seconds
Started Jun 25 05:46:15 PM PDT 24
Finished Jun 25 05:46:29 PM PDT 24
Peak memory 183964 kb
Host smart-b6553fd4-3a4b-4502-b227-b2ec2568fd93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383993356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.383993356
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.4272454723
Short name T112
Test name
Test status
Simulation time 188666445259 ps
CPU time 125.12 seconds
Started Jun 25 05:46:16 PM PDT 24
Finished Jun 25 05:48:23 PM PDT 24
Peak memory 191700 kb
Host smart-26433ef2-784e-4430-9cd8-872ec536ca60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272454723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.4272454723
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1847156893
Short name T19
Test name
Test status
Simulation time 112776778820 ps
CPU time 146.12 seconds
Started Jun 25 05:46:34 PM PDT 24
Finished Jun 25 05:49:01 PM PDT 24
Peak memory 206712 kb
Host smart-9e77c0e1-d50c-4148-9a38-5defab16ba1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847156893 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1847156893
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1655620869
Short name T135
Test name
Test status
Simulation time 29578633383 ps
CPU time 9.79 seconds
Started Jun 25 05:46:29 PM PDT 24
Finished Jun 25 05:46:40 PM PDT 24
Peak memory 198076 kb
Host smart-0f1117a7-f2f5-48e1-94d8-08b23c418b66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655620869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1655620869
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1919765088
Short name T167
Test name
Test status
Simulation time 134566308028 ps
CPU time 54.48 seconds
Started Jun 25 05:46:47 PM PDT 24
Finished Jun 25 05:47:42 PM PDT 24
Peak memory 183988 kb
Host smart-de31ffd2-bef3-47c6-b86c-aa134f955438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919765088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1919765088
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1337833778
Short name T56
Test name
Test status
Simulation time 117190753427 ps
CPU time 404.34 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:53:46 PM PDT 24
Peak memory 210052 kb
Host smart-cbb1041c-236b-4820-926f-b40967ead55d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337833778 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1337833778
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.4224227674
Short name T76
Test name
Test status
Simulation time 64158524449 ps
CPU time 21.87 seconds
Started Jun 25 05:46:01 PM PDT 24
Finished Jun 25 05:46:24 PM PDT 24
Peak memory 192736 kb
Host smart-c286a76e-2523-4a60-9dca-72ec234a0bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224227674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.4224227674
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2664233710
Short name T137
Test name
Test status
Simulation time 13453418676 ps
CPU time 135.47 seconds
Started Jun 25 05:46:15 PM PDT 24
Finished Jun 25 05:48:32 PM PDT 24
Peak memory 214136 kb
Host smart-52011ceb-1c01-489f-8497-093f0c167ad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664233710 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2664233710
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3974965264
Short name T100
Test name
Test status
Simulation time 299603301801 ps
CPU time 91.35 seconds
Started Jun 25 05:46:47 PM PDT 24
Finished Jun 25 05:48:20 PM PDT 24
Peak memory 192728 kb
Host smart-7ae938a3-0898-4dbb-bbb8-3709db51b132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974965264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3974965264
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2139674765
Short name T95
Test name
Test status
Simulation time 103753312821 ps
CPU time 198.2 seconds
Started Jun 25 05:47:04 PM PDT 24
Finished Jun 25 05:50:24 PM PDT 24
Peak memory 199924 kb
Host smart-399615f8-6c3e-4785-ae41-6b660c606a9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139674765 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2139674765
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2918083285
Short name T97
Test name
Test status
Simulation time 125272087690 ps
CPU time 177.44 seconds
Started Jun 25 05:46:07 PM PDT 24
Finished Jun 25 05:49:05 PM PDT 24
Peak memory 206776 kb
Host smart-bfe4116c-b58c-4ec7-b445-c8f2a66f0fa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918083285 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2918083285
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2037077227
Short name T129
Test name
Test status
Simulation time 500646705 ps
CPU time 0.91 seconds
Started Jun 25 05:46:15 PM PDT 24
Finished Jun 25 05:46:18 PM PDT 24
Peak memory 196384 kb
Host smart-c694d1c7-716e-48df-9bfe-3b7c98b3305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037077227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2037077227
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2012737873
Short name T139
Test name
Test status
Simulation time 231637626052 ps
CPU time 83.68 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:48:24 PM PDT 24
Peak memory 192808 kb
Host smart-c357d0ae-611e-4b22-b647-ed6cef4577fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012737873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2012737873
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.4119008345
Short name T134
Test name
Test status
Simulation time 63775441946 ps
CPU time 44.89 seconds
Started Jun 25 05:47:05 PM PDT 24
Finished Jun 25 05:47:52 PM PDT 24
Peak memory 191484 kb
Host smart-9cecc1d9-ede7-4231-b5ab-de5349bf1bb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119008345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.4119008345
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3643991861
Short name T169
Test name
Test status
Simulation time 37965273239 ps
CPU time 235.35 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:49:55 PM PDT 24
Peak memory 198448 kb
Host smart-373a19b7-2799-4464-bb9c-091975516da4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643991861 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3643991861
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2861982449
Short name T150
Test name
Test status
Simulation time 121214545253 ps
CPU time 1272.65 seconds
Started Jun 25 05:46:42 PM PDT 24
Finished Jun 25 06:07:55 PM PDT 24
Peak memory 214168 kb
Host smart-42ac9524-c28f-4467-820c-3bf7380c958e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861982449 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2861982449
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.4052319793
Short name T161
Test name
Test status
Simulation time 58116343474 ps
CPU time 12.38 seconds
Started Jun 25 05:46:48 PM PDT 24
Finished Jun 25 05:47:02 PM PDT 24
Peak memory 191700 kb
Host smart-52d1b341-4a32-4e43-943e-b2022eceecd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052319793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.4052319793
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.119897353
Short name T125
Test name
Test status
Simulation time 130938707263 ps
CPU time 174.21 seconds
Started Jun 25 05:47:05 PM PDT 24
Finished Jun 25 05:50:00 PM PDT 24
Peak memory 198048 kb
Host smart-99dd5687-6281-42df-a57f-96e9950d1658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119897353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.119897353
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1139756671
Short name T132
Test name
Test status
Simulation time 103115077672 ps
CPU time 16.9 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:27 PM PDT 24
Peak memory 191708 kb
Host smart-2bfb0dd5-53de-4b04-986b-be569b9e9fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139756671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1139756671
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2990947629
Short name T98
Test name
Test status
Simulation time 21160795131 ps
CPU time 79.74 seconds
Started Jun 25 05:46:06 PM PDT 24
Finished Jun 25 05:47:27 PM PDT 24
Peak memory 206648 kb
Host smart-cd677659-3d40-47d6-8b21-d3b48c26cd35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990947629 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2990947629
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2997235581
Short name T4
Test name
Test status
Simulation time 371277930 ps
CPU time 0.7 seconds
Started Jun 25 05:46:06 PM PDT 24
Finished Jun 25 05:46:08 PM PDT 24
Peak memory 196512 kb
Host smart-f3d3b449-993b-4cdf-a544-6aaba9e865c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997235581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2997235581
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.759300141
Short name T148
Test name
Test status
Simulation time 458057185 ps
CPU time 0.8 seconds
Started Jun 25 05:46:07 PM PDT 24
Finished Jun 25 05:46:09 PM PDT 24
Peak memory 196472 kb
Host smart-538f6b54-7c75-428f-8539-f4f46f60a702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759300141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.759300141
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1064215245
Short name T155
Test name
Test status
Simulation time 542946094 ps
CPU time 1.31 seconds
Started Jun 25 05:46:17 PM PDT 24
Finished Jun 25 05:46:20 PM PDT 24
Peak memory 196552 kb
Host smart-3a0dda71-70bd-42c5-bedd-f6e52ffcbd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064215245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1064215245
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3934881454
Short name T183
Test name
Test status
Simulation time 271461904173 ps
CPU time 195.69 seconds
Started Jun 25 05:46:16 PM PDT 24
Finished Jun 25 05:49:33 PM PDT 24
Peak memory 191536 kb
Host smart-8ceab029-c70b-4a24-a5c2-cc671ac8d6bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934881454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3934881454
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2692557413
Short name T180
Test name
Test status
Simulation time 287089663789 ps
CPU time 64.51 seconds
Started Jun 25 05:46:29 PM PDT 24
Finished Jun 25 05:47:34 PM PDT 24
Peak memory 192200 kb
Host smart-101bbee3-cb8d-44ca-806a-fd66d51759c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692557413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2692557413
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1265396748
Short name T159
Test name
Test status
Simulation time 95018910471 ps
CPU time 31.52 seconds
Started Jun 25 05:46:38 PM PDT 24
Finished Jun 25 05:47:10 PM PDT 24
Peak memory 191736 kb
Host smart-55f00510-4cdc-491c-95e1-645443b5d46e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265396748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1265396748
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3146848176
Short name T158
Test name
Test status
Simulation time 531670764 ps
CPU time 0.75 seconds
Started Jun 25 05:47:01 PM PDT 24
Finished Jun 25 05:47:03 PM PDT 24
Peak memory 196412 kb
Host smart-9c280cdc-1d9f-4e2e-a397-2ff3bad2c673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146848176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3146848176
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1268862742
Short name T140
Test name
Test status
Simulation time 350992361 ps
CPU time 0.74 seconds
Started Jun 25 05:46:16 PM PDT 24
Finished Jun 25 05:46:18 PM PDT 24
Peak memory 196448 kb
Host smart-1bb2a8a3-c251-4a7a-b359-2dd1348fe135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268862742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1268862742
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2730829431
Short name T165
Test name
Test status
Simulation time 65178789161 ps
CPU time 694.03 seconds
Started Jun 25 05:46:16 PM PDT 24
Finished Jun 25 05:57:52 PM PDT 24
Peak memory 204988 kb
Host smart-bf4f5bf4-9463-478a-95fb-e45bd5b583f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730829431 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2730829431
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2750573086
Short name T187
Test name
Test status
Simulation time 29364582252 ps
CPU time 204.1 seconds
Started Jun 25 05:46:21 PM PDT 24
Finished Jun 25 05:49:46 PM PDT 24
Peak memory 206652 kb
Host smart-54e8edd1-8b10-4994-9d3d-b3e5fbdd7e3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750573086 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2750573086
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1866097263
Short name T198
Test name
Test status
Simulation time 106117835116 ps
CPU time 146.73 seconds
Started Jun 25 05:46:48 PM PDT 24
Finished Jun 25 05:49:16 PM PDT 24
Peak memory 198028 kb
Host smart-e090b365-dfe9-4c4a-82de-3e32337efdfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866097263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1866097263
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.341657202
Short name T170
Test name
Test status
Simulation time 343479322543 ps
CPU time 279.48 seconds
Started Jun 25 05:47:00 PM PDT 24
Finished Jun 25 05:51:41 PM PDT 24
Peak memory 209328 kb
Host smart-bed80303-f2a3-4c53-b48b-1c8be4e13229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341657202 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.341657202
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.746277643
Short name T173
Test name
Test status
Simulation time 314732099749 ps
CPU time 340.37 seconds
Started Jun 25 05:46:07 PM PDT 24
Finished Jun 25 05:51:48 PM PDT 24
Peak memory 213820 kb
Host smart-5a528fb3-9d52-497a-ada7-5e20eb75e7cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746277643 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.746277643
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2519527762
Short name T116
Test name
Test status
Simulation time 456900533 ps
CPU time 0.72 seconds
Started Jun 25 05:46:14 PM PDT 24
Finished Jun 25 05:46:15 PM PDT 24
Peak memory 196804 kb
Host smart-236881a6-33e7-43a9-8297-0a8401036b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519527762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2519527762
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2762598280
Short name T189
Test name
Test status
Simulation time 102598440281 ps
CPU time 129.82 seconds
Started Jun 25 05:46:21 PM PDT 24
Finished Jun 25 05:48:32 PM PDT 24
Peak memory 198084 kb
Host smart-c00f5156-b92e-4721-b496-bdc3f7a30027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762598280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2762598280
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.957653916
Short name T146
Test name
Test status
Simulation time 517418274 ps
CPU time 1.28 seconds
Started Jun 25 05:46:29 PM PDT 24
Finished Jun 25 05:46:31 PM PDT 24
Peak memory 196380 kb
Host smart-23b138bc-30e4-48dc-b4e6-a266c73ad64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957653916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.957653916
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1364485
Short name T8
Test name
Test status
Simulation time 612115614 ps
CPU time 1.15 seconds
Started Jun 25 05:46:47 PM PDT 24
Finished Jun 25 05:46:50 PM PDT 24
Peak memory 196496 kb
Host smart-813f19c5-be70-47ea-9654-711a2a1d6fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1364485
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2951861540
Short name T77
Test name
Test status
Simulation time 74542939902 ps
CPU time 14.55 seconds
Started Jun 25 05:47:05 PM PDT 24
Finished Jun 25 05:47:21 PM PDT 24
Peak memory 192736 kb
Host smart-fa79697e-b9c1-48c8-b2ff-283a50758572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951861540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2951861540
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_jump.488226256
Short name T103
Test name
Test status
Simulation time 461576058 ps
CPU time 0.86 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:46:01 PM PDT 24
Peak memory 196684 kb
Host smart-fe93f52e-713e-4137-8194-5a5ae47a98bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488226256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.488226256
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2614627067
Short name T152
Test name
Test status
Simulation time 433648242 ps
CPU time 1.24 seconds
Started Jun 25 05:46:47 PM PDT 24
Finished Jun 25 05:46:50 PM PDT 24
Peak memory 196536 kb
Host smart-d611c69e-95e7-4b7e-9020-c0f9f8745d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614627067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2614627067
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.649570401
Short name T75
Test name
Test status
Simulation time 75470252399 ps
CPU time 45.45 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:47:46 PM PDT 24
Peak memory 192820 kb
Host smart-f12ef57f-a9c4-4ad8-9713-df922757738f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649570401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.649570401
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.762543553
Short name T136
Test name
Test status
Simulation time 17889077198 ps
CPU time 156.89 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:49:38 PM PDT 24
Peak memory 214008 kb
Host smart-4ca734c6-8894-4fe1-9964-60f6157dcfef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762543553 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.762543553
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1405174323
Short name T190
Test name
Test status
Simulation time 11406268498 ps
CPU time 47.99 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:58 PM PDT 24
Peak memory 206612 kb
Host smart-67b9944a-61b2-4b33-b2da-157f3bd50bcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405174323 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1405174323
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3630494715
Short name T31
Test name
Test status
Simulation time 165044951975 ps
CPU time 60.03 seconds
Started Jun 25 05:46:14 PM PDT 24
Finished Jun 25 05:47:15 PM PDT 24
Peak memory 191732 kb
Host smart-40ee4141-ef34-4c95-b8ba-2ca83be07ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630494715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3630494715
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.779718136
Short name T143
Test name
Test status
Simulation time 533352747 ps
CPU time 0.78 seconds
Started Jun 25 05:46:00 PM PDT 24
Finished Jun 25 05:46:01 PM PDT 24
Peak memory 196476 kb
Host smart-6b62cb41-aaa9-415e-ad52-6db4cfa4060d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779718136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.779718136
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2322031572
Short name T10
Test name
Test status
Simulation time 91728013433 ps
CPU time 65.11 seconds
Started Jun 25 05:46:34 PM PDT 24
Finished Jun 25 05:47:41 PM PDT 24
Peak memory 191776 kb
Host smart-bd7c1e81-46b9-437c-9e0f-d5c564aacf2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322031572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2322031572
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2766446752
Short name T164
Test name
Test status
Simulation time 514996547 ps
CPU time 0.82 seconds
Started Jun 25 05:46:00 PM PDT 24
Finished Jun 25 05:46:02 PM PDT 24
Peak memory 196484 kb
Host smart-1c64fafc-2cfb-40a4-a51b-a7e9b4b4f3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766446752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2766446752
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1304524098
Short name T16
Test name
Test status
Simulation time 59237936759 ps
CPU time 446.4 seconds
Started Jun 25 05:46:47 PM PDT 24
Finished Jun 25 05:54:15 PM PDT 24
Peak memory 209100 kb
Host smart-0fc79b2c-c5cf-4983-aa11-26ab03ea31af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304524098 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1304524098
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3794042876
Short name T154
Test name
Test status
Simulation time 527192579 ps
CPU time 1.25 seconds
Started Jun 25 05:47:03 PM PDT 24
Finished Jun 25 05:47:05 PM PDT 24
Peak memory 196452 kb
Host smart-266c6c64-4bf4-4297-a65e-8701dd64b7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794042876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3794042876
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.753477797
Short name T181
Test name
Test status
Simulation time 473918783 ps
CPU time 0.66 seconds
Started Jun 25 05:47:04 PM PDT 24
Finished Jun 25 05:47:06 PM PDT 24
Peak memory 196448 kb
Host smart-68e3762b-886b-4b00-8732-ced2c74c3bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753477797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.753477797
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.134432656
Short name T205
Test name
Test status
Simulation time 9044393576 ps
CPU time 13.63 seconds
Started Jun 25 05:47:36 PM PDT 24
Finished Jun 25 05:47:50 PM PDT 24
Peak memory 198284 kb
Host smart-5812471a-0cee-4298-afba-975fe77da60a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134432656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.134432656
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_jump.912382111
Short name T194
Test name
Test status
Simulation time 400569163 ps
CPU time 1.07 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:11 PM PDT 24
Peak memory 196464 kb
Host smart-47f0bac6-4774-4d3c-a1c3-0522780c8271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912382111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.912382111
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3231331531
Short name T32
Test name
Test status
Simulation time 490337998 ps
CPU time 1.05 seconds
Started Jun 25 05:46:16 PM PDT 24
Finished Jun 25 05:46:19 PM PDT 24
Peak memory 196536 kb
Host smart-b462aa7b-7f38-4c3f-a9b9-d568b60afaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231331531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3231331531
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2885285721
Short name T176
Test name
Test status
Simulation time 534307140 ps
CPU time 1.38 seconds
Started Jun 25 05:46:15 PM PDT 24
Finished Jun 25 05:46:19 PM PDT 24
Peak memory 196452 kb
Host smart-3de15c8b-3df0-49a9-a77b-6d0ef927da62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885285721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2885285721
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2611595676
Short name T184
Test name
Test status
Simulation time 453654674 ps
CPU time 1.21 seconds
Started Jun 25 05:46:22 PM PDT 24
Finished Jun 25 05:46:24 PM PDT 24
Peak memory 196508 kb
Host smart-6c8001bd-441c-4a32-9b9a-d74c4d7bb0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611595676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2611595676
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.279220488
Short name T195
Test name
Test status
Simulation time 409428673 ps
CPU time 0.76 seconds
Started Jun 25 05:46:30 PM PDT 24
Finished Jun 25 05:46:31 PM PDT 24
Peak memory 196440 kb
Host smart-ea9ab09a-5c3e-4a83-9baf-eb18c5687d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279220488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.279220488
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1221012648
Short name T200
Test name
Test status
Simulation time 592828680 ps
CPU time 1 seconds
Started Jun 25 05:46:38 PM PDT 24
Finished Jun 25 05:46:39 PM PDT 24
Peak memory 196432 kb
Host smart-0815e31a-2556-4a51-8f5b-e3173af5b50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221012648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1221012648
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.166198779
Short name T72
Test name
Test status
Simulation time 559553880 ps
CPU time 1.24 seconds
Started Jun 25 05:46:47 PM PDT 24
Finished Jun 25 05:46:50 PM PDT 24
Peak memory 196452 kb
Host smart-1a1e7160-b42d-46f1-ad10-d2be4e17ff5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166198779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.166198779
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.367716201
Short name T123
Test name
Test status
Simulation time 523174289 ps
CPU time 0.81 seconds
Started Jun 25 05:46:00 PM PDT 24
Finished Jun 25 05:46:02 PM PDT 24
Peak memory 196532 kb
Host smart-60513163-e1a0-4f68-937f-e26481ba3001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367716201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.367716201
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3019665676
Short name T151
Test name
Test status
Simulation time 523514897 ps
CPU time 0.81 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:47:01 PM PDT 24
Peak memory 196432 kb
Host smart-69c60c39-40f6-4ce3-8a58-6ceec5e6222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019665676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3019665676
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1761982691
Short name T186
Test name
Test status
Simulation time 521299427 ps
CPU time 1.43 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:47:03 PM PDT 24
Peak memory 196508 kb
Host smart-d4820d80-39c2-4dcd-be52-637f0bc0a4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761982691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1761982691
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1366748307
Short name T157
Test name
Test status
Simulation time 423959770 ps
CPU time 0.81 seconds
Started Jun 25 05:47:03 PM PDT 24
Finished Jun 25 05:47:04 PM PDT 24
Peak memory 196468 kb
Host smart-43a8f496-6d2d-4453-8763-8947b0bbd1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366748307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1366748307
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1970490168
Short name T202
Test name
Test status
Simulation time 624459428 ps
CPU time 0.9 seconds
Started Jun 25 05:47:06 PM PDT 24
Finished Jun 25 05:47:08 PM PDT 24
Peak memory 196424 kb
Host smart-e401d23a-34c7-4d7c-b363-1592075483c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970490168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1970490168
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1366746079
Short name T11
Test name
Test status
Simulation time 347653117 ps
CPU time 1.11 seconds
Started Jun 25 05:46:07 PM PDT 24
Finished Jun 25 05:46:10 PM PDT 24
Peak memory 196388 kb
Host smart-0c4614e5-fe4d-457b-a158-34f74fb322c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366746079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1366746079
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1387001019
Short name T45
Test name
Test status
Simulation time 175790619124 ps
CPU time 291.32 seconds
Started Jun 25 05:46:07 PM PDT 24
Finished Jun 25 05:51:00 PM PDT 24
Peak memory 201144 kb
Host smart-af729087-4d6f-41d2-84d6-54dc7aec7278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387001019 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1387001019
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1037130387
Short name T404
Test name
Test status
Simulation time 4591300509 ps
CPU time 2.61 seconds
Started Jun 25 05:47:15 PM PDT 24
Finished Jun 25 05:47:20 PM PDT 24
Peak memory 197808 kb
Host smart-e94d070c-8f33-47ec-a73a-741fa9a73fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037130387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1037130387
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1729128355
Short name T193
Test name
Test status
Simulation time 602211856 ps
CPU time 0.61 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:10 PM PDT 24
Peak memory 196500 kb
Host smart-7df924c5-3793-4ab9-9ee6-27084650cdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729128355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1729128355
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1036015984
Short name T13
Test name
Test status
Simulation time 338792383 ps
CPU time 1.04 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:11 PM PDT 24
Peak memory 196436 kb
Host smart-f52c55f8-6fa4-4bea-aca1-987dea63459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036015984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1036015984
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1219233417
Short name T196
Test name
Test status
Simulation time 563015105 ps
CPU time 0.85 seconds
Started Jun 25 05:46:16 PM PDT 24
Finished Jun 25 05:46:19 PM PDT 24
Peak memory 196444 kb
Host smart-71959924-98aa-4204-ad3c-d1cb7fb4bb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219233417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1219233417
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.242644311
Short name T141
Test name
Test status
Simulation time 362058435 ps
CPU time 1.06 seconds
Started Jun 25 05:46:34 PM PDT 24
Finished Jun 25 05:46:36 PM PDT 24
Peak memory 196528 kb
Host smart-2e56bfc4-6fd3-472d-b684-6dfd6f64cafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242644311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.242644311
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3797299622
Short name T199
Test name
Test status
Simulation time 479583650 ps
CPU time 1.28 seconds
Started Jun 25 05:46:32 PM PDT 24
Finished Jun 25 05:46:34 PM PDT 24
Peak memory 196364 kb
Host smart-1fc925bc-ab2b-4347-9e78-18c2d9a66dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797299622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3797299622
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1838850932
Short name T168
Test name
Test status
Simulation time 492742057 ps
CPU time 0.96 seconds
Started Jun 25 05:46:40 PM PDT 24
Finished Jun 25 05:46:42 PM PDT 24
Peak memory 196468 kb
Host smart-fca9b7bc-6d78-4542-9588-cab589deb4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838850932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1838850932
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1062598308
Short name T178
Test name
Test status
Simulation time 487938425 ps
CPU time 0.78 seconds
Started Jun 25 05:46:39 PM PDT 24
Finished Jun 25 05:46:41 PM PDT 24
Peak memory 196436 kb
Host smart-d980e6b4-cd35-44a3-92f6-cffb2903fa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062598308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1062598308
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3699747056
Short name T174
Test name
Test status
Simulation time 377295342 ps
CPU time 0.85 seconds
Started Jun 25 05:46:46 PM PDT 24
Finished Jun 25 05:46:48 PM PDT 24
Peak memory 196516 kb
Host smart-113f96eb-9d7d-4bda-98d7-07693a7c0037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699747056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3699747056
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2719985132
Short name T114
Test name
Test status
Simulation time 432275082 ps
CPU time 0.75 seconds
Started Jun 25 05:46:58 PM PDT 24
Finished Jun 25 05:47:00 PM PDT 24
Peak memory 196788 kb
Host smart-d47fffb5-a354-4c8c-af05-087ed6a28fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719985132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2719985132
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3986813237
Short name T14
Test name
Test status
Simulation time 544541219 ps
CPU time 0.68 seconds
Started Jun 25 05:46:07 PM PDT 24
Finished Jun 25 05:46:09 PM PDT 24
Peak memory 196544 kb
Host smart-0bd98357-09fe-4a76-9039-d5c832bba270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986813237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3986813237
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1162720498
Short name T12
Test name
Test status
Simulation time 556164228 ps
CPU time 1.07 seconds
Started Jun 25 05:46:06 PM PDT 24
Finished Jun 25 05:46:07 PM PDT 24
Peak memory 196552 kb
Host smart-26412a4f-355a-4d9a-b080-7e7bdedeb1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162720498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1162720498
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2585848309
Short name T314
Test name
Test status
Simulation time 659996496 ps
CPU time 1.7 seconds
Started Jun 25 05:47:07 PM PDT 24
Finished Jun 25 05:47:10 PM PDT 24
Peak memory 183980 kb
Host smart-6372c5b3-6a38-4819-9d28-0356bc5ce2c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585848309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2585848309
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4092741925
Short name T332
Test name
Test status
Simulation time 14240465409 ps
CPU time 9.21 seconds
Started Jun 25 05:47:04 PM PDT 24
Finished Jun 25 05:47:15 PM PDT 24
Peak memory 192276 kb
Host smart-9349d400-e870-4f2d-b698-ecbd44aa9008
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092741925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.4092741925
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1181498972
Short name T402
Test name
Test status
Simulation time 1000053333 ps
CPU time 1.03 seconds
Started Jun 25 05:47:08 PM PDT 24
Finished Jun 25 05:47:09 PM PDT 24
Peak memory 193208 kb
Host smart-a947c646-9ee8-4f78-8be3-10c70c4637e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181498972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1181498972
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.478734812
Short name T353
Test name
Test status
Simulation time 384606454 ps
CPU time 0.78 seconds
Started Jun 25 05:47:15 PM PDT 24
Finished Jun 25 05:47:17 PM PDT 24
Peak memory 195804 kb
Host smart-2624c34a-a1d5-44eb-8d5b-6972ed3a4045
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478734812 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.478734812
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1955941960
Short name T373
Test name
Test status
Simulation time 297665358 ps
CPU time 1.08 seconds
Started Jun 25 05:47:04 PM PDT 24
Finished Jun 25 05:47:06 PM PDT 24
Peak memory 193052 kb
Host smart-918a91cc-35d1-4316-8d6e-b63f181ac022
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955941960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1955941960
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4293221183
Short name T293
Test name
Test status
Simulation time 448052071 ps
CPU time 1.11 seconds
Started Jun 25 05:47:04 PM PDT 24
Finished Jun 25 05:47:06 PM PDT 24
Peak memory 183828 kb
Host smart-971ac783-00ab-47de-84a0-6c0ef8792219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293221183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.4293221183
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.679357257
Short name T298
Test name
Test status
Simulation time 490811793 ps
CPU time 1.18 seconds
Started Jun 25 05:47:04 PM PDT 24
Finished Jun 25 05:47:06 PM PDT 24
Peak memory 183752 kb
Host smart-655ecdb6-573d-492a-9665-05923170298c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679357257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.679357257
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3175982096
Short name T376
Test name
Test status
Simulation time 455288751 ps
CPU time 1.09 seconds
Started Jun 25 05:47:05 PM PDT 24
Finished Jun 25 05:47:07 PM PDT 24
Peak memory 183744 kb
Host smart-5547de4f-3bc0-43df-8e89-3dbb52a6eb3b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175982096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3175982096
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4034082475
Short name T360
Test name
Test status
Simulation time 2950336293 ps
CPU time 8.99 seconds
Started Jun 25 05:47:06 PM PDT 24
Finished Jun 25 05:47:16 PM PDT 24
Peak memory 195148 kb
Host smart-8b7d2d25-e9ee-4ddb-944d-925784c90169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034082475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.4034082475
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.101733807
Short name T331
Test name
Test status
Simulation time 470992452 ps
CPU time 2.55 seconds
Started Jun 25 05:47:06 PM PDT 24
Finished Jun 25 05:47:10 PM PDT 24
Peak memory 198672 kb
Host smart-bf68cc45-334c-4154-92a2-c5b9ec8f701e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101733807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.101733807
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4124954337
Short name T208
Test name
Test status
Simulation time 4556587690 ps
CPU time 7.29 seconds
Started Jun 25 05:47:03 PM PDT 24
Finished Jun 25 05:47:11 PM PDT 24
Peak memory 197620 kb
Host smart-d6c518f6-e1fa-4218-b563-1217a834ae78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124954337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.4124954337
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2634572893
Short name T68
Test name
Test status
Simulation time 495329171 ps
CPU time 1 seconds
Started Jun 25 05:47:15 PM PDT 24
Finished Jun 25 05:47:17 PM PDT 24
Peak memory 183988 kb
Host smart-f63c8a86-507e-45e4-8538-9c83615d9634
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634572893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2634572893
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4153211923
Short name T210
Test name
Test status
Simulation time 13809264514 ps
CPU time 35.88 seconds
Started Jun 25 05:47:14 PM PDT 24
Finished Jun 25 05:47:50 PM PDT 24
Peak memory 196264 kb
Host smart-06552d69-2f61-4083-9d70-54c4556b0ae8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153211923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.4153211923
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3471976111
Short name T394
Test name
Test status
Simulation time 783485896 ps
CPU time 0.9 seconds
Started Jun 25 05:47:14 PM PDT 24
Finished Jun 25 05:47:16 PM PDT 24
Peak memory 192200 kb
Host smart-c393fce0-80c4-45f6-8047-75c9611d248f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471976111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3471976111
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2898035235
Short name T422
Test name
Test status
Simulation time 430912993 ps
CPU time 1.27 seconds
Started Jun 25 05:47:12 PM PDT 24
Finished Jun 25 05:47:14 PM PDT 24
Peak memory 196440 kb
Host smart-f5cd5a77-4948-471d-8630-97c1dad63dac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898035235 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2898035235
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.225842703
Short name T67
Test name
Test status
Simulation time 304743296 ps
CPU time 1.12 seconds
Started Jun 25 05:47:16 PM PDT 24
Finished Jun 25 05:47:19 PM PDT 24
Peak memory 194072 kb
Host smart-e837b1ef-7a5d-450d-8cc9-7db8f27dedee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225842703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.225842703
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.602408815
Short name T372
Test name
Test status
Simulation time 400431556 ps
CPU time 0.79 seconds
Started Jun 25 05:47:14 PM PDT 24
Finished Jun 25 05:47:16 PM PDT 24
Peak memory 183832 kb
Host smart-05fd1272-524d-4bc9-b891-29f2d88674ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602408815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.602408815
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2818391233
Short name T330
Test name
Test status
Simulation time 442457144 ps
CPU time 1.01 seconds
Started Jun 25 05:47:15 PM PDT 24
Finished Jun 25 05:47:17 PM PDT 24
Peak memory 183752 kb
Host smart-b4c9fcca-cc4c-4291-9713-6f64fd3f5a00
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818391233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2818391233
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.701995344
Short name T321
Test name
Test status
Simulation time 379496445 ps
CPU time 1.01 seconds
Started Jun 25 05:47:13 PM PDT 24
Finished Jun 25 05:47:15 PM PDT 24
Peak memory 183668 kb
Host smart-6f24275d-78ff-4e4a-adb6-be99a6435928
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701995344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.701995344
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1781838843
Short name T383
Test name
Test status
Simulation time 2303566864 ps
CPU time 3.54 seconds
Started Jun 25 05:47:13 PM PDT 24
Finished Jun 25 05:47:18 PM PDT 24
Peak memory 192080 kb
Host smart-c924f45d-8a03-4983-9cbb-e6fdd88fa4b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781838843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1781838843
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3892209421
Short name T341
Test name
Test status
Simulation time 584272160 ps
CPU time 1.46 seconds
Started Jun 25 05:47:16 PM PDT 24
Finished Jun 25 05:47:19 PM PDT 24
Peak memory 198656 kb
Host smart-f43c2e5a-5b6c-48e8-9e15-81718dbbeddd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892209421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3892209421
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1180929029
Short name T384
Test name
Test status
Simulation time 469387498 ps
CPU time 1 seconds
Started Jun 25 05:47:39 PM PDT 24
Finished Jun 25 05:47:41 PM PDT 24
Peak memory 195848 kb
Host smart-20882cab-af42-4160-ab12-7409ad4503c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180929029 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1180929029
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3615757610
Short name T409
Test name
Test status
Simulation time 536531475 ps
CPU time 0.84 seconds
Started Jun 25 05:47:39 PM PDT 24
Finished Jun 25 05:47:40 PM PDT 24
Peak memory 193680 kb
Host smart-f6e13ced-8603-422c-a087-9229d4942dc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615757610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3615757610
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.528983180
Short name T294
Test name
Test status
Simulation time 363184466 ps
CPU time 1.02 seconds
Started Jun 25 05:47:39 PM PDT 24
Finished Jun 25 05:47:41 PM PDT 24
Peak memory 192856 kb
Host smart-d56297d4-cc60-404c-b324-8c4dea65442d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528983180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.528983180
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3563816629
Short name T424
Test name
Test status
Simulation time 2037851596 ps
CPU time 4.83 seconds
Started Jun 25 05:47:38 PM PDT 24
Finished Jun 25 05:47:43 PM PDT 24
Peak memory 193848 kb
Host smart-5b3f8c17-4df3-4b6d-950c-b978337734c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563816629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3563816629
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1633165837
Short name T295
Test name
Test status
Simulation time 500821184 ps
CPU time 2.28 seconds
Started Jun 25 05:47:38 PM PDT 24
Finished Jun 25 05:47:41 PM PDT 24
Peak memory 198704 kb
Host smart-bd6e3803-f708-4d7f-a85d-fee346e5847b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633165837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1633165837
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3049768152
Short name T336
Test name
Test status
Simulation time 555837710 ps
CPU time 1.49 seconds
Started Jun 25 05:47:46 PM PDT 24
Finished Jun 25 05:47:48 PM PDT 24
Peak memory 197180 kb
Host smart-2e8d21c3-e3cc-4b0f-af56-9b2262a2f86d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049768152 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3049768152
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3494941081
Short name T70
Test name
Test status
Simulation time 498043703 ps
CPU time 1.25 seconds
Started Jun 25 05:47:41 PM PDT 24
Finished Jun 25 05:47:42 PM PDT 24
Peak memory 192028 kb
Host smart-72439ee3-76cb-4f4b-989b-7bd91404afad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494941081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3494941081
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2325293473
Short name T393
Test name
Test status
Simulation time 404840658 ps
CPU time 0.86 seconds
Started Jun 25 05:47:38 PM PDT 24
Finished Jun 25 05:47:40 PM PDT 24
Peak memory 183832 kb
Host smart-14a6c10f-81af-4fad-97f1-ec6c3ca1f229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325293473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2325293473
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1940498318
Short name T88
Test name
Test status
Simulation time 1170776803 ps
CPU time 2.75 seconds
Started Jun 25 05:47:40 PM PDT 24
Finished Jun 25 05:47:44 PM PDT 24
Peak memory 193660 kb
Host smart-6c56bdf1-b97f-4194-a881-6f5d14b33b1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940498318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1940498318
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.910140260
Short name T382
Test name
Test status
Simulation time 502852612 ps
CPU time 2.69 seconds
Started Jun 25 05:47:40 PM PDT 24
Finished Jun 25 05:47:44 PM PDT 24
Peak memory 198672 kb
Host smart-c8348419-8db4-49d9-8bed-32feb2659473
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910140260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.910140260
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.213012926
Short name T416
Test name
Test status
Simulation time 8746617868 ps
CPU time 12.99 seconds
Started Jun 25 05:47:37 PM PDT 24
Finished Jun 25 05:47:50 PM PDT 24
Peak memory 198320 kb
Host smart-6e516115-7b9b-4241-98b0-a8d43a0d089e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213012926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.213012926
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2520989517
Short name T359
Test name
Test status
Simulation time 375873300 ps
CPU time 0.76 seconds
Started Jun 25 05:47:46 PM PDT 24
Finished Jun 25 05:47:47 PM PDT 24
Peak memory 195660 kb
Host smart-804e5430-7bdf-4e41-aaff-93554345db21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520989517 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2520989517
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.162574173
Short name T65
Test name
Test status
Simulation time 461660159 ps
CPU time 1.29 seconds
Started Jun 25 05:47:47 PM PDT 24
Finished Jun 25 05:47:49 PM PDT 24
Peak memory 193364 kb
Host smart-ee861262-e330-4dce-a582-282dfb8e5fef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162574173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.162574173
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3521410265
Short name T371
Test name
Test status
Simulation time 288373366 ps
CPU time 0.71 seconds
Started Jun 25 05:47:44 PM PDT 24
Finished Jun 25 05:47:45 PM PDT 24
Peak memory 183832 kb
Host smart-d53111d4-978f-4915-aa28-e50442b1b05d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521410265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3521410265
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1559551738
Short name T403
Test name
Test status
Simulation time 1963345673 ps
CPU time 1.88 seconds
Started Jun 25 05:47:50 PM PDT 24
Finished Jun 25 05:47:52 PM PDT 24
Peak memory 193968 kb
Host smart-e18a5589-f167-4331-9f58-be519fbce051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559551738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1559551738
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.222528115
Short name T289
Test name
Test status
Simulation time 624870906 ps
CPU time 2.44 seconds
Started Jun 25 05:47:48 PM PDT 24
Finished Jun 25 05:47:51 PM PDT 24
Peak memory 198696 kb
Host smart-979db12d-5333-44bc-bf6e-635f434ce67e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222528115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.222528115
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.414080041
Short name T206
Test name
Test status
Simulation time 8602523102 ps
CPU time 11.91 seconds
Started Jun 25 05:47:45 PM PDT 24
Finished Jun 25 05:47:58 PM PDT 24
Peak memory 198256 kb
Host smart-4a386bdd-affe-4182-830e-219dd52d5115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414080041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.414080041
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.366267145
Short name T362
Test name
Test status
Simulation time 562684478 ps
CPU time 0.85 seconds
Started Jun 25 05:47:44 PM PDT 24
Finished Jun 25 05:47:46 PM PDT 24
Peak memory 196568 kb
Host smart-fcd0a130-629d-4ade-9e7d-cb3d34a44a88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366267145 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.366267145
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4141510391
Short name T412
Test name
Test status
Simulation time 528990235 ps
CPU time 1.46 seconds
Started Jun 25 05:47:49 PM PDT 24
Finished Jun 25 05:47:51 PM PDT 24
Peak memory 193028 kb
Host smart-a7e4be94-a4dc-4100-99ae-5fe2750af4d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141510391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.4141510391
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2540291726
Short name T426
Test name
Test status
Simulation time 490479039 ps
CPU time 1.31 seconds
Started Jun 25 05:47:45 PM PDT 24
Finished Jun 25 05:47:48 PM PDT 24
Peak memory 192972 kb
Host smart-68f8e5e4-6d17-46b0-b171-42d619fbab9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540291726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2540291726
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3762596022
Short name T364
Test name
Test status
Simulation time 2300214239 ps
CPU time 2.04 seconds
Started Jun 25 05:47:47 PM PDT 24
Finished Jun 25 05:47:50 PM PDT 24
Peak memory 184048 kb
Host smart-50b751ba-4b18-4fdc-9769-67d1a88e44b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762596022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3762596022
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.787894433
Short name T389
Test name
Test status
Simulation time 388391389 ps
CPU time 2.05 seconds
Started Jun 25 05:47:44 PM PDT 24
Finished Jun 25 05:47:47 PM PDT 24
Peak memory 198688 kb
Host smart-1ae5aeff-dbee-41e0-af6a-93fe4b52a514
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787894433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.787894433
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1811881669
Short name T415
Test name
Test status
Simulation time 8008030891 ps
CPU time 13.14 seconds
Started Jun 25 05:47:47 PM PDT 24
Finished Jun 25 05:48:01 PM PDT 24
Peak memory 198072 kb
Host smart-594894df-614e-48b4-8a16-303bebcffe50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811881669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1811881669
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3614130642
Short name T303
Test name
Test status
Simulation time 473752314 ps
CPU time 1.34 seconds
Started Jun 25 05:47:47 PM PDT 24
Finished Jun 25 05:47:49 PM PDT 24
Peak memory 195812 kb
Host smart-8b6b9cf5-130e-4534-aeea-ad3cf16fdabb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614130642 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3614130642
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.511161792
Short name T64
Test name
Test status
Simulation time 478775042 ps
CPU time 0.83 seconds
Started Jun 25 05:47:46 PM PDT 24
Finished Jun 25 05:47:47 PM PDT 24
Peak memory 192080 kb
Host smart-8585d05b-05f5-4b59-88c6-2dac9f2c60e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511161792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.511161792
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2662045374
Short name T324
Test name
Test status
Simulation time 292673039 ps
CPU time 1 seconds
Started Jun 25 05:47:45 PM PDT 24
Finished Jun 25 05:47:46 PM PDT 24
Peak memory 183832 kb
Host smart-a3618794-155c-4eb7-b480-7af1df296576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662045374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2662045374
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1831690152
Short name T388
Test name
Test status
Simulation time 1565390165 ps
CPU time 4.16 seconds
Started Jun 25 05:47:46 PM PDT 24
Finished Jun 25 05:47:51 PM PDT 24
Peak memory 194228 kb
Host smart-22c669f3-9252-404d-a177-24132a9a4e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831690152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1831690152
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2809059351
Short name T329
Test name
Test status
Simulation time 710923723 ps
CPU time 1.79 seconds
Started Jun 25 05:47:45 PM PDT 24
Finished Jun 25 05:47:47 PM PDT 24
Peak memory 198672 kb
Host smart-cb420c86-c6ce-436c-8b28-053f4dbb3b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809059351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2809059351
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.904314002
Short name T203
Test name
Test status
Simulation time 3687445748 ps
CPU time 5.59 seconds
Started Jun 25 05:47:48 PM PDT 24
Finished Jun 25 05:47:54 PM PDT 24
Peak memory 197844 kb
Host smart-eb55f888-ff24-41f8-ba1e-2f4091ac257b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904314002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.904314002
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.237846945
Short name T400
Test name
Test status
Simulation time 528820250 ps
CPU time 1.32 seconds
Started Jun 25 05:47:43 PM PDT 24
Finished Jun 25 05:47:45 PM PDT 24
Peak memory 195936 kb
Host smart-b1244934-affa-46f0-a1c0-b3778179331e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237846945 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.237846945
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2025847472
Short name T398
Test name
Test status
Simulation time 511257775 ps
CPU time 0.91 seconds
Started Jun 25 05:47:48 PM PDT 24
Finished Jun 25 05:47:49 PM PDT 24
Peak memory 193032 kb
Host smart-8b168b2b-e46b-4484-8c2f-a11025c325aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025847472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2025847472
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2837243532
Short name T312
Test name
Test status
Simulation time 420910869 ps
CPU time 0.85 seconds
Started Jun 25 05:47:45 PM PDT 24
Finished Jun 25 05:47:47 PM PDT 24
Peak memory 183796 kb
Host smart-c4006a36-b049-4896-8fc5-07222c0b8fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837243532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2837243532
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2748738499
Short name T344
Test name
Test status
Simulation time 1990040270 ps
CPU time 2.96 seconds
Started Jun 25 05:47:44 PM PDT 24
Finished Jun 25 05:47:48 PM PDT 24
Peak memory 195120 kb
Host smart-0447dfb5-573d-45b0-9241-ae0f62f6f21e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748738499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2748738499
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4145921062
Short name T379
Test name
Test status
Simulation time 657405360 ps
CPU time 2.25 seconds
Started Jun 25 05:47:46 PM PDT 24
Finished Jun 25 05:47:49 PM PDT 24
Peak memory 198648 kb
Host smart-2004afe6-29ad-4316-a9b6-2d9aaea6cfa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145921062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.4145921062
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.334719309
Short name T385
Test name
Test status
Simulation time 5122047510 ps
CPU time 4.94 seconds
Started Jun 25 05:47:45 PM PDT 24
Finished Jun 25 05:47:51 PM PDT 24
Peak memory 197804 kb
Host smart-4ddf8294-7325-4c00-bc72-c452cd75b2d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334719309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.334719309
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4212413107
Short name T41
Test name
Test status
Simulation time 558218460 ps
CPU time 1.54 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:58 PM PDT 24
Peak memory 196252 kb
Host smart-e6761043-d24d-4448-a5d3-80fd8c67facf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212413107 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.4212413107
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2566015238
Short name T63
Test name
Test status
Simulation time 428229776 ps
CPU time 1.14 seconds
Started Jun 25 05:47:56 PM PDT 24
Finished Jun 25 05:47:58 PM PDT 24
Peak memory 193036 kb
Host smart-6642e8fc-e5f8-4c97-9723-a2555a703a7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566015238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2566015238
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4183385188
Short name T421
Test name
Test status
Simulation time 404143614 ps
CPU time 1.05 seconds
Started Jun 25 05:47:46 PM PDT 24
Finished Jun 25 05:47:48 PM PDT 24
Peak memory 183828 kb
Host smart-50b55bc6-0564-4ac3-97c4-1a0cc4b3be22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183385188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.4183385188
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3272617949
Short name T81
Test name
Test status
Simulation time 1248859061 ps
CPU time 4.07 seconds
Started Jun 25 05:47:56 PM PDT 24
Finished Jun 25 05:48:01 PM PDT 24
Peak memory 193820 kb
Host smart-6f06316e-f476-456b-a7e1-a0505d754a9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272617949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3272617949
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3446058811
Short name T292
Test name
Test status
Simulation time 406428765 ps
CPU time 1.96 seconds
Started Jun 25 05:47:49 PM PDT 24
Finished Jun 25 05:47:52 PM PDT 24
Peak memory 198680 kb
Host smart-ae8d64ac-2f25-4ef1-b2e0-e8c86ec1ed43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446058811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3446058811
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3190950813
Short name T377
Test name
Test status
Simulation time 4374504587 ps
CPU time 6.86 seconds
Started Jun 25 05:47:47 PM PDT 24
Finished Jun 25 05:47:54 PM PDT 24
Peak memory 196712 kb
Host smart-2720cf18-9cdc-4816-b7f2-883eac7e6cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190950813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3190950813
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3126974570
Short name T381
Test name
Test status
Simulation time 580849139 ps
CPU time 1.2 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:58 PM PDT 24
Peak memory 198476 kb
Host smart-2e530912-e5a5-452b-9bfa-5cfe40096b82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126974570 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3126974570
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.684540324
Short name T85
Test name
Test status
Simulation time 502693725 ps
CPU time 1.2 seconds
Started Jun 25 05:47:52 PM PDT 24
Finished Jun 25 05:47:54 PM PDT 24
Peak memory 193192 kb
Host smart-30ec72a3-52ce-4142-bf6e-fd668ce56be4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684540324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.684540324
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1055830214
Short name T350
Test name
Test status
Simulation time 303334532 ps
CPU time 0.67 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:57 PM PDT 24
Peak memory 193052 kb
Host smart-735879ce-46f9-4805-b814-1cf006cd8b82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055830214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1055830214
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2616123864
Short name T369
Test name
Test status
Simulation time 2550840085 ps
CPU time 3.96 seconds
Started Jun 25 05:47:54 PM PDT 24
Finished Jun 25 05:47:59 PM PDT 24
Peak memory 194080 kb
Host smart-5b829030-6c49-46d3-b407-1b8fec183597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616123864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2616123864
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2129320414
Short name T316
Test name
Test status
Simulation time 579882864 ps
CPU time 2.36 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:58 PM PDT 24
Peak memory 198664 kb
Host smart-cbe00871-49e8-4374-9b92-51a07c9f46a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129320414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2129320414
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2832061940
Short name T207
Test name
Test status
Simulation time 4502932765 ps
CPU time 3.65 seconds
Started Jun 25 05:47:54 PM PDT 24
Finished Jun 25 05:47:58 PM PDT 24
Peak memory 196904 kb
Host smart-cf05334e-3fa8-49f1-940b-4600894a5820
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832061940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2832061940
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.893297982
Short name T334
Test name
Test status
Simulation time 411256496 ps
CPU time 0.79 seconds
Started Jun 25 05:47:56 PM PDT 24
Finished Jun 25 05:47:58 PM PDT 24
Peak memory 196132 kb
Host smart-fa86bef6-f4d9-4408-9cf3-aa8e75a9db16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893297982 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.893297982
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1865761200
Short name T62
Test name
Test status
Simulation time 498646116 ps
CPU time 0.81 seconds
Started Jun 25 05:47:57 PM PDT 24
Finished Jun 25 05:47:59 PM PDT 24
Peak memory 193172 kb
Host smart-6b99badd-70f5-44c1-952a-f1d3cb05376b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865761200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1865761200
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.459606258
Short name T308
Test name
Test status
Simulation time 332115060 ps
CPU time 0.66 seconds
Started Jun 25 05:47:54 PM PDT 24
Finished Jun 25 05:47:56 PM PDT 24
Peak memory 183848 kb
Host smart-3b03ed73-0888-4692-858e-6ef0785e000f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459606258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.459606258
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2378206319
Short name T87
Test name
Test status
Simulation time 1706862801 ps
CPU time 1.49 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:58 PM PDT 24
Peak memory 193980 kb
Host smart-d85d4cc5-6e04-48f5-b627-a1d2c1fb0f56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378206319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2378206319
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.404414502
Short name T399
Test name
Test status
Simulation time 499021655 ps
CPU time 1.88 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:59 PM PDT 24
Peak memory 198700 kb
Host smart-ede7d3a7-451f-4c91-9330-696f03649a39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404414502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.404414502
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3562316390
Short name T354
Test name
Test status
Simulation time 7975986682 ps
CPU time 10.53 seconds
Started Jun 25 05:47:54 PM PDT 24
Finished Jun 25 05:48:05 PM PDT 24
Peak memory 198296 kb
Host smart-5a457a78-0152-4c19-bcdd-ae51ea6e0883
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562316390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3562316390
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1088743287
Short name T317
Test name
Test status
Simulation time 623286058 ps
CPU time 1.49 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:57 PM PDT 24
Peak memory 196724 kb
Host smart-321bf7d6-ab3a-4549-a0a9-f2329662851f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088743287 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1088743287
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2383678250
Short name T310
Test name
Test status
Simulation time 367132395 ps
CPU time 0.84 seconds
Started Jun 25 05:47:57 PM PDT 24
Finished Jun 25 05:47:59 PM PDT 24
Peak memory 192904 kb
Host smart-de3595ac-bc04-4d66-b60b-f333b6724d10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383678250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2383678250
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.987508583
Short name T375
Test name
Test status
Simulation time 415616518 ps
CPU time 0.71 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:57 PM PDT 24
Peak memory 183792 kb
Host smart-ede1d5c3-7058-4130-91a4-4fab0908f5e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987508583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.987508583
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3696916332
Short name T352
Test name
Test status
Simulation time 2828370597 ps
CPU time 2.38 seconds
Started Jun 25 05:47:53 PM PDT 24
Finished Jun 25 05:47:56 PM PDT 24
Peak memory 195084 kb
Host smart-46ee6143-9849-4c35-adf3-7f13145ffeaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696916332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3696916332
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.966023691
Short name T367
Test name
Test status
Simulation time 350222474 ps
CPU time 1.32 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:58 PM PDT 24
Peak memory 198488 kb
Host smart-9c2e8d94-ef30-4b20-9632-a0f11633ebe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966023691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.966023691
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3444363543
Short name T401
Test name
Test status
Simulation time 5045572205 ps
CPU time 1.26 seconds
Started Jun 25 05:47:53 PM PDT 24
Finished Jun 25 05:47:55 PM PDT 24
Peak memory 196600 kb
Host smart-f702e722-b5b2-4382-b9b8-805e6a0a5d86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444363543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3444363543
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.320151764
Short name T71
Test name
Test status
Simulation time 664729061 ps
CPU time 1.08 seconds
Started Jun 25 05:47:26 PM PDT 24
Finished Jun 25 05:47:28 PM PDT 24
Peak memory 183916 kb
Host smart-d1743b2d-018f-4420-a1fd-a054b0aab88a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320151764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.320151764
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3914984775
Short name T410
Test name
Test status
Simulation time 7169245068 ps
CPU time 4.81 seconds
Started Jun 25 05:47:15 PM PDT 24
Finished Jun 25 05:47:22 PM PDT 24
Peak memory 192288 kb
Host smart-2af66c75-83c2-416e-92e7-b16f1b5bde40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914984775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3914984775
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3936648130
Short name T417
Test name
Test status
Simulation time 1094367673 ps
CPU time 2 seconds
Started Jun 25 05:47:16 PM PDT 24
Finished Jun 25 05:47:20 PM PDT 24
Peak memory 193348 kb
Host smart-aa8d89ac-1986-44d0-904a-a6bff1811bea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936648130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3936648130
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3055766050
Short name T339
Test name
Test status
Simulation time 623457700 ps
CPU time 0.87 seconds
Started Jun 25 05:47:24 PM PDT 24
Finished Jun 25 05:47:26 PM PDT 24
Peak memory 198056 kb
Host smart-0c6780ff-60f5-4d18-968e-484fa9a49f9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055766050 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3055766050
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.11511628
Short name T66
Test name
Test status
Simulation time 500008782 ps
CPU time 0.78 seconds
Started Jun 25 05:47:17 PM PDT 24
Finished Jun 25 05:47:19 PM PDT 24
Peak memory 192104 kb
Host smart-31049972-4bc2-44b5-9462-8a0b8c273224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11511628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.11511628
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2185639533
Short name T378
Test name
Test status
Simulation time 551593470 ps
CPU time 0.66 seconds
Started Jun 25 05:47:15 PM PDT 24
Finished Jun 25 05:47:18 PM PDT 24
Peak memory 183824 kb
Host smart-c68386aa-3665-4a38-9c87-d929ec677b15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185639533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2185639533
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2329366223
Short name T315
Test name
Test status
Simulation time 348551640 ps
CPU time 0.75 seconds
Started Jun 25 05:47:15 PM PDT 24
Finished Jun 25 05:47:17 PM PDT 24
Peak memory 183712 kb
Host smart-a54ae6ad-7239-4202-9384-0460f04b5f01
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329366223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2329366223
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.829702339
Short name T348
Test name
Test status
Simulation time 331990307 ps
CPU time 0.94 seconds
Started Jun 25 05:47:14 PM PDT 24
Finished Jun 25 05:47:17 PM PDT 24
Peak memory 183760 kb
Host smart-51dacf19-a05e-4710-81e2-abeba51e3e6e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829702339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.829702339
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2783693624
Short name T82
Test name
Test status
Simulation time 2808914246 ps
CPU time 2.09 seconds
Started Jun 25 05:47:26 PM PDT 24
Finished Jun 25 05:47:29 PM PDT 24
Peak memory 194796 kb
Host smart-c771ae11-db6e-4011-8f86-dc505d23d668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783693624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2783693624
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1452941486
Short name T370
Test name
Test status
Simulation time 463051306 ps
CPU time 1.71 seconds
Started Jun 25 05:47:14 PM PDT 24
Finished Jun 25 05:47:16 PM PDT 24
Peak memory 198432 kb
Host smart-76e54ea6-77b3-40e8-aba2-d3a0d5446215
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452941486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1452941486
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2679825607
Short name T405
Test name
Test status
Simulation time 4608469180 ps
CPU time 2.23 seconds
Started Jun 25 05:47:13 PM PDT 24
Finished Jun 25 05:47:16 PM PDT 24
Peak memory 196864 kb
Host smart-47fb688c-7139-4ba8-b1b5-06f4de4f71e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679825607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2679825607
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3343577949
Short name T304
Test name
Test status
Simulation time 386587452 ps
CPU time 0.62 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:57 PM PDT 24
Peak memory 183844 kb
Host smart-1fe704ec-b9ac-4036-9736-d3f26ec4b575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343577949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3343577949
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2428499892
Short name T357
Test name
Test status
Simulation time 413650287 ps
CPU time 0.84 seconds
Started Jun 25 05:47:54 PM PDT 24
Finished Jun 25 05:47:56 PM PDT 24
Peak memory 183832 kb
Host smart-5ecaa598-fef5-46d5-abeb-69ab83ed4ba7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428499892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2428499892
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2499011032
Short name T413
Test name
Test status
Simulation time 462798037 ps
CPU time 0.59 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:57 PM PDT 24
Peak memory 193040 kb
Host smart-f9c3bf3d-d020-4ec3-bd5a-75082e63d7fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499011032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2499011032
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1407043923
Short name T395
Test name
Test status
Simulation time 382825352 ps
CPU time 0.85 seconds
Started Jun 25 05:47:54 PM PDT 24
Finished Jun 25 05:47:56 PM PDT 24
Peak memory 193044 kb
Host smart-4d749b90-dbff-4a84-947d-b8cd38fbbb1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407043923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1407043923
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4164878442
Short name T391
Test name
Test status
Simulation time 344613667 ps
CPU time 1.03 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:57 PM PDT 24
Peak memory 183788 kb
Host smart-9154a4fb-dcf6-42c2-9b51-216c1d45c01e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164878442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4164878442
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3064757672
Short name T325
Test name
Test status
Simulation time 286780894 ps
CPU time 1.05 seconds
Started Jun 25 05:47:57 PM PDT 24
Finished Jun 25 05:47:59 PM PDT 24
Peak memory 193048 kb
Host smart-5ee77793-f611-4c44-a7be-63a4716b7787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064757672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3064757672
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1222531181
Short name T319
Test name
Test status
Simulation time 298125049 ps
CPU time 0.62 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:57 PM PDT 24
Peak memory 183828 kb
Host smart-d586acb4-56ac-4c1e-b52f-72b38e6b58d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222531181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1222531181
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.686805578
Short name T425
Test name
Test status
Simulation time 370910607 ps
CPU time 0.84 seconds
Started Jun 25 05:47:54 PM PDT 24
Finished Jun 25 05:47:56 PM PDT 24
Peak memory 193052 kb
Host smart-65ca9d79-12bc-494e-889e-cf38cd9649a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686805578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.686805578
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.532856771
Short name T337
Test name
Test status
Simulation time 431474441 ps
CPU time 0.87 seconds
Started Jun 25 05:47:55 PM PDT 24
Finished Jun 25 05:47:57 PM PDT 24
Peak memory 183756 kb
Host smart-a12e83a1-57ca-4833-b27e-7e63568cf785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532856771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.532856771
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2456935308
Short name T301
Test name
Test status
Simulation time 539546904 ps
CPU time 0.64 seconds
Started Jun 25 05:47:56 PM PDT 24
Finished Jun 25 05:47:58 PM PDT 24
Peak memory 183828 kb
Host smart-6b49ef72-8b72-44fd-a83b-d26350d870a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456935308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2456935308
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4033647113
Short name T351
Test name
Test status
Simulation time 547886113 ps
CPU time 1.51 seconds
Started Jun 25 05:47:23 PM PDT 24
Finished Jun 25 05:47:26 PM PDT 24
Peak memory 194760 kb
Host smart-20319fc3-30b4-4535-ac0a-2df6ad288187
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033647113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4033647113
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2989620562
Short name T57
Test name
Test status
Simulation time 11979624008 ps
CPU time 5.39 seconds
Started Jun 25 05:47:21 PM PDT 24
Finished Jun 25 05:47:28 PM PDT 24
Peak memory 196392 kb
Host smart-ad3b21e1-b5ea-43a0-a6d3-529ee5bba78d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989620562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2989620562
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.251797795
Short name T42
Test name
Test status
Simulation time 1425925703 ps
CPU time 1.56 seconds
Started Jun 25 05:47:23 PM PDT 24
Finished Jun 25 05:47:26 PM PDT 24
Peak memory 193304 kb
Host smart-9cbfaff3-c28f-4f81-81bd-c33c52ecd9dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251797795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.251797795
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3849404191
Short name T355
Test name
Test status
Simulation time 459926185 ps
CPU time 1.26 seconds
Started Jun 25 05:47:24 PM PDT 24
Finished Jun 25 05:47:27 PM PDT 24
Peak memory 195412 kb
Host smart-cc792ecc-36b5-456f-ae96-25fd06f8cded
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849404191 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3849404191
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.958001011
Short name T423
Test name
Test status
Simulation time 318834502 ps
CPU time 0.64 seconds
Started Jun 25 05:47:23 PM PDT 24
Finished Jun 25 05:47:25 PM PDT 24
Peak memory 192088 kb
Host smart-fcf6412d-b7d1-492c-a99a-bb3985e37d31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958001011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.958001011
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1628355262
Short name T299
Test name
Test status
Simulation time 527426064 ps
CPU time 0.91 seconds
Started Jun 25 05:47:22 PM PDT 24
Finished Jun 25 05:47:24 PM PDT 24
Peak memory 183840 kb
Host smart-9fd0c2a9-377b-4716-8764-7be4a3364b3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628355262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1628355262
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.375251952
Short name T342
Test name
Test status
Simulation time 380975933 ps
CPU time 0.58 seconds
Started Jun 25 05:47:24 PM PDT 24
Finished Jun 25 05:47:26 PM PDT 24
Peak memory 183752 kb
Host smart-98d522ff-e53b-4666-a639-5154e773e852
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375251952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.375251952
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.242412676
Short name T345
Test name
Test status
Simulation time 292901765 ps
CPU time 0.96 seconds
Started Jun 25 05:47:23 PM PDT 24
Finished Jun 25 05:47:25 PM PDT 24
Peak memory 183752 kb
Host smart-83859230-eb67-4dc0-b31f-c3446380aebf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242412676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.242412676
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1068764405
Short name T418
Test name
Test status
Simulation time 2247383636 ps
CPU time 1.44 seconds
Started Jun 25 05:47:22 PM PDT 24
Finished Jun 25 05:47:25 PM PDT 24
Peak memory 194156 kb
Host smart-17ac7553-564d-47a4-97b2-a40b70adb8f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068764405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1068764405
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3438515496
Short name T322
Test name
Test status
Simulation time 314884922 ps
CPU time 2.2 seconds
Started Jun 25 05:47:22 PM PDT 24
Finished Jun 25 05:47:25 PM PDT 24
Peak memory 198580 kb
Host smart-b63e3349-9caa-4d7f-ab4e-4f3bc9022903
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438515496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3438515496
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1901202926
Short name T204
Test name
Test status
Simulation time 7687391179 ps
CPU time 3.96 seconds
Started Jun 25 05:47:23 PM PDT 24
Finished Jun 25 05:47:28 PM PDT 24
Peak memory 198296 kb
Host smart-4cc59cb9-9095-4de0-94fd-076fae160837
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901202926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1901202926
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.765023910
Short name T361
Test name
Test status
Simulation time 443249100 ps
CPU time 0.75 seconds
Started Jun 25 05:47:54 PM PDT 24
Finished Jun 25 05:47:55 PM PDT 24
Peak memory 183788 kb
Host smart-6355a12b-254b-4d9a-9f89-d78bf3a84c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765023910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.765023910
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3457084952
Short name T380
Test name
Test status
Simulation time 378537356 ps
CPU time 0.68 seconds
Started Jun 25 05:48:03 PM PDT 24
Finished Jun 25 05:48:04 PM PDT 24
Peak memory 183836 kb
Host smart-bd324be9-2f02-4167-a26a-63e59002c914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457084952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3457084952
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.394778583
Short name T414
Test name
Test status
Simulation time 450949086 ps
CPU time 0.7 seconds
Started Jun 25 05:48:06 PM PDT 24
Finished Jun 25 05:48:08 PM PDT 24
Peak memory 183452 kb
Host smart-c5e8d767-21bf-403a-b3a4-c39cd6541060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394778583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.394778583
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.984730642
Short name T296
Test name
Test status
Simulation time 459327234 ps
CPU time 0.75 seconds
Started Jun 25 05:48:07 PM PDT 24
Finished Jun 25 05:48:08 PM PDT 24
Peak memory 183844 kb
Host smart-e8aafd5b-8d51-44ab-97e9-7cba1a5d8ad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984730642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.984730642
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1375887917
Short name T318
Test name
Test status
Simulation time 389004443 ps
CPU time 0.83 seconds
Started Jun 25 05:48:06 PM PDT 24
Finished Jun 25 05:48:08 PM PDT 24
Peak memory 183468 kb
Host smart-087d685f-5ac1-4dca-a026-6cbd1390df0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375887917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1375887917
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1794734879
Short name T320
Test name
Test status
Simulation time 441223270 ps
CPU time 0.56 seconds
Started Jun 25 05:48:03 PM PDT 24
Finished Jun 25 05:48:05 PM PDT 24
Peak memory 183832 kb
Host smart-56c4dd90-5196-4507-a0a7-44902721d94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794734879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1794734879
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3056488430
Short name T347
Test name
Test status
Simulation time 490115601 ps
CPU time 0.78 seconds
Started Jun 25 05:48:04 PM PDT 24
Finished Jun 25 05:48:06 PM PDT 24
Peak memory 183828 kb
Host smart-8dc71cda-6a17-4164-b105-410a46e80be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056488430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3056488430
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1667249721
Short name T300
Test name
Test status
Simulation time 282725347 ps
CPU time 0.98 seconds
Started Jun 25 05:48:03 PM PDT 24
Finished Jun 25 05:48:05 PM PDT 24
Peak memory 183836 kb
Host smart-f92ac3fd-2b68-4172-8e1c-9911142ff506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667249721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1667249721
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4281673181
Short name T411
Test name
Test status
Simulation time 310692966 ps
CPU time 1.02 seconds
Started Jun 25 05:48:04 PM PDT 24
Finished Jun 25 05:48:06 PM PDT 24
Peak memory 183828 kb
Host smart-b9774210-a039-4e4c-a91b-99ee972643cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281673181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4281673181
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2100231259
Short name T366
Test name
Test status
Simulation time 295431005 ps
CPU time 0.64 seconds
Started Jun 25 05:48:03 PM PDT 24
Finished Jun 25 05:48:04 PM PDT 24
Peak memory 183824 kb
Host smart-654c5f37-047d-4f18-a85f-cde4a5280661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100231259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2100231259
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3167639200
Short name T38
Test name
Test status
Simulation time 542139618 ps
CPU time 0.86 seconds
Started Jun 25 05:47:24 PM PDT 24
Finished Jun 25 05:47:26 PM PDT 24
Peak memory 183812 kb
Host smart-b1eab691-fa9f-4d1f-bfdf-cff407c10e5b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167639200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3167639200
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1131572198
Short name T69
Test name
Test status
Simulation time 5204527044 ps
CPU time 7.14 seconds
Started Jun 25 05:47:24 PM PDT 24
Finished Jun 25 05:47:32 PM PDT 24
Peak memory 192244 kb
Host smart-e32256d8-260c-491d-bda1-da5e0779587e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131572198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1131572198
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4128488445
Short name T61
Test name
Test status
Simulation time 1338037246 ps
CPU time 2.46 seconds
Started Jun 25 05:47:24 PM PDT 24
Finished Jun 25 05:47:28 PM PDT 24
Peak memory 183788 kb
Host smart-10f444a5-131e-4401-bf9c-857a1b972968
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128488445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.4128488445
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3172293202
Short name T397
Test name
Test status
Simulation time 472437631 ps
CPU time 1.21 seconds
Started Jun 25 05:47:24 PM PDT 24
Finished Jun 25 05:47:27 PM PDT 24
Peak memory 196808 kb
Host smart-cedbf2be-519d-487e-af7b-dfedb2a8c7cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172293202 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3172293202
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1743889825
Short name T309
Test name
Test status
Simulation time 366844459 ps
CPU time 0.72 seconds
Started Jun 25 05:47:24 PM PDT 24
Finished Jun 25 05:47:27 PM PDT 24
Peak memory 193184 kb
Host smart-5fcf369d-1aa8-4cd1-b56f-cde9c4086a2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743889825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1743889825
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.719410794
Short name T340
Test name
Test status
Simulation time 340411723 ps
CPU time 0.77 seconds
Started Jun 25 05:47:23 PM PDT 24
Finished Jun 25 05:47:25 PM PDT 24
Peak memory 183848 kb
Host smart-e2646760-3a33-4b94-918f-8b229cb41e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719410794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.719410794
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1655312481
Short name T365
Test name
Test status
Simulation time 446041804 ps
CPU time 1.21 seconds
Started Jun 25 05:47:26 PM PDT 24
Finished Jun 25 05:47:28 PM PDT 24
Peak memory 183692 kb
Host smart-62fb901a-5a32-4944-b645-be123c799461
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655312481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1655312481
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.90979418
Short name T346
Test name
Test status
Simulation time 457170953 ps
CPU time 0.85 seconds
Started Jun 25 05:47:21 PM PDT 24
Finished Jun 25 05:47:22 PM PDT 24
Peak memory 183736 kb
Host smart-e76d4e9c-4837-4a84-9038-a9dc00cf3291
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90979418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wal
k.90979418
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2347299014
Short name T84
Test name
Test status
Simulation time 1142695723 ps
CPU time 1.49 seconds
Started Jun 25 05:47:24 PM PDT 24
Finished Jun 25 05:47:27 PM PDT 24
Peak memory 191824 kb
Host smart-5418f0aa-72f4-4cad-b75f-e6835c14695c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347299014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2347299014
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1919424906
Short name T390
Test name
Test status
Simulation time 1509918266 ps
CPU time 1.91 seconds
Started Jun 25 05:47:23 PM PDT 24
Finished Jun 25 05:47:27 PM PDT 24
Peak memory 198680 kb
Host smart-c18d77f5-a256-47c7-8159-fb66f3e1eb98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919424906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1919424906
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1716493108
Short name T39
Test name
Test status
Simulation time 4139771773 ps
CPU time 2.26 seconds
Started Jun 25 05:47:25 PM PDT 24
Finished Jun 25 05:47:28 PM PDT 24
Peak memory 197780 kb
Host smart-bb4acbcd-3d4e-4491-97ca-e49c393adcaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716493108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1716493108
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4055473827
Short name T333
Test name
Test status
Simulation time 326465070 ps
CPU time 0.78 seconds
Started Jun 25 05:48:05 PM PDT 24
Finished Jun 25 05:48:07 PM PDT 24
Peak memory 184052 kb
Host smart-28d49064-6a69-4ea1-b257-de15cd9707a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055473827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4055473827
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2722053384
Short name T358
Test name
Test status
Simulation time 490312887 ps
CPU time 0.9 seconds
Started Jun 25 05:48:04 PM PDT 24
Finished Jun 25 05:48:07 PM PDT 24
Peak memory 193060 kb
Host smart-c5122906-686b-4503-9c91-ba95a5c19a4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722053384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2722053384
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2307984315
Short name T291
Test name
Test status
Simulation time 425546803 ps
CPU time 1.23 seconds
Started Jun 25 05:48:04 PM PDT 24
Finished Jun 25 05:48:07 PM PDT 24
Peak memory 193064 kb
Host smart-51699959-d319-4b80-8aba-17e7609a30da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307984315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2307984315
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.505787477
Short name T396
Test name
Test status
Simulation time 489170017 ps
CPU time 0.64 seconds
Started Jun 25 05:48:04 PM PDT 24
Finished Jun 25 05:48:06 PM PDT 24
Peak memory 183824 kb
Host smart-3c6b8166-b9f9-4ecd-a31b-d8859786c4ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505787477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.505787477
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.822590575
Short name T290
Test name
Test status
Simulation time 519355736 ps
CPU time 0.68 seconds
Started Jun 25 05:48:02 PM PDT 24
Finished Jun 25 05:48:03 PM PDT 24
Peak memory 193048 kb
Host smart-44fd4ea7-9014-4551-9e5b-d4a606344d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822590575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.822590575
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3270631236
Short name T392
Test name
Test status
Simulation time 412392511 ps
CPU time 1.05 seconds
Started Jun 25 05:48:06 PM PDT 24
Finished Jun 25 05:48:08 PM PDT 24
Peak memory 193048 kb
Host smart-c673f6a0-df2a-48c5-9970-87bcde05b96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270631236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3270631236
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2167857366
Short name T338
Test name
Test status
Simulation time 375340429 ps
CPU time 0.68 seconds
Started Jun 25 05:48:04 PM PDT 24
Finished Jun 25 05:48:06 PM PDT 24
Peak memory 183636 kb
Host smart-e392dfbf-bcf9-4bb0-ad5a-dd8cbd95d134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167857366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2167857366
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3122740401
Short name T307
Test name
Test status
Simulation time 442700710 ps
CPU time 0.61 seconds
Started Jun 25 05:48:02 PM PDT 24
Finished Jun 25 05:48:04 PM PDT 24
Peak memory 193072 kb
Host smart-55323f60-42d6-48a2-9799-7d1318d671ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122740401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3122740401
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1748101678
Short name T311
Test name
Test status
Simulation time 288871526 ps
CPU time 0.94 seconds
Started Jun 25 05:48:03 PM PDT 24
Finished Jun 25 05:48:05 PM PDT 24
Peak memory 193044 kb
Host smart-1ca921e1-3076-46bd-89da-18f133fe27c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748101678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1748101678
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.203665979
Short name T313
Test name
Test status
Simulation time 381117264 ps
CPU time 0.68 seconds
Started Jun 25 05:48:05 PM PDT 24
Finished Jun 25 05:48:07 PM PDT 24
Peak memory 183828 kb
Host smart-7eece90a-0a36-4dca-a219-f4b336390253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203665979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.203665979
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4084890680
Short name T407
Test name
Test status
Simulation time 357071429 ps
CPU time 1.17 seconds
Started Jun 25 05:47:23 PM PDT 24
Finished Jun 25 05:47:26 PM PDT 24
Peak memory 195888 kb
Host smart-e8de95d7-d4b0-4200-816c-2bb6d3050679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084890680 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.4084890680
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.63074817
Short name T58
Test name
Test status
Simulation time 467585664 ps
CPU time 1.31 seconds
Started Jun 25 05:47:23 PM PDT 24
Finished Jun 25 05:47:26 PM PDT 24
Peak memory 193472 kb
Host smart-5e0e4cff-4ed1-4f5c-b3c9-9c83ebf40ce8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63074817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.63074817
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.4264795300
Short name T302
Test name
Test status
Simulation time 330286699 ps
CPU time 1.02 seconds
Started Jun 25 05:47:22 PM PDT 24
Finished Jun 25 05:47:25 PM PDT 24
Peak memory 183832 kb
Host smart-6524d277-4fb1-40f6-bfde-31fb96083408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264795300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.4264795300
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.770778176
Short name T83
Test name
Test status
Simulation time 2631581668 ps
CPU time 1.51 seconds
Started Jun 25 05:47:21 PM PDT 24
Finished Jun 25 05:47:24 PM PDT 24
Peak memory 194104 kb
Host smart-2061ad25-c3f5-4025-8075-263a545ee516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770778176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.770778176
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.484754709
Short name T323
Test name
Test status
Simulation time 574206203 ps
CPU time 2.88 seconds
Started Jun 25 05:47:21 PM PDT 24
Finished Jun 25 05:47:25 PM PDT 24
Peak memory 198704 kb
Host smart-12f2e6c2-43ea-436d-88af-8cd62f27fe3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484754709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.484754709
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.152075554
Short name T327
Test name
Test status
Simulation time 7894376253 ps
CPU time 3.82 seconds
Started Jun 25 05:47:24 PM PDT 24
Finished Jun 25 05:47:30 PM PDT 24
Peak memory 198200 kb
Host smart-efe497ae-ccd4-4354-b131-defc4a39bcf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152075554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.152075554
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4186721160
Short name T349
Test name
Test status
Simulation time 534311059 ps
CPU time 1.07 seconds
Started Jun 25 05:47:29 PM PDT 24
Finished Jun 25 05:47:31 PM PDT 24
Peak memory 196900 kb
Host smart-64b33e98-9c98-4c97-ba27-614b013a323d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186721160 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.4186721160
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1941483798
Short name T59
Test name
Test status
Simulation time 366696607 ps
CPU time 1.19 seconds
Started Jun 25 05:47:22 PM PDT 24
Finished Jun 25 05:47:24 PM PDT 24
Peak memory 193028 kb
Host smart-70898093-5ee4-40f1-aeec-849856169d58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941483798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1941483798
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.638172444
Short name T328
Test name
Test status
Simulation time 381584638 ps
CPU time 0.92 seconds
Started Jun 25 05:47:24 PM PDT 24
Finished Jun 25 05:47:27 PM PDT 24
Peak memory 193044 kb
Host smart-11191a6c-808b-4850-944a-bb2c39dde6c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638172444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.638172444
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3172543474
Short name T374
Test name
Test status
Simulation time 1157983976 ps
CPU time 0.91 seconds
Started Jun 25 05:47:22 PM PDT 24
Finished Jun 25 05:47:24 PM PDT 24
Peak memory 193044 kb
Host smart-d4f46d42-6537-4dfb-b356-26a00e0e827d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172543474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3172543474
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2326041436
Short name T343
Test name
Test status
Simulation time 564212757 ps
CPU time 1.5 seconds
Started Jun 25 05:47:22 PM PDT 24
Finished Jun 25 05:47:25 PM PDT 24
Peak memory 198904 kb
Host smart-9ee134a2-ef49-4d2e-a15f-ea23651ca33a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326041436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2326041436
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.278133710
Short name T356
Test name
Test status
Simulation time 406219262 ps
CPU time 0.96 seconds
Started Jun 25 05:47:32 PM PDT 24
Finished Jun 25 05:47:34 PM PDT 24
Peak memory 197244 kb
Host smart-0b580135-2832-4422-be77-e645e2255508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278133710 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.278133710
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1419650820
Short name T406
Test name
Test status
Simulation time 326509672 ps
CPU time 0.68 seconds
Started Jun 25 05:47:31 PM PDT 24
Finished Jun 25 05:47:33 PM PDT 24
Peak memory 192316 kb
Host smart-355f63f7-a6fc-42f5-bb08-30657caf1136
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419650820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1419650820
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2610598086
Short name T386
Test name
Test status
Simulation time 492944384 ps
CPU time 0.73 seconds
Started Jun 25 05:47:30 PM PDT 24
Finished Jun 25 05:47:32 PM PDT 24
Peak memory 193076 kb
Host smart-eaa43ce1-9759-49f5-9c8f-ebd4cbf3e4ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610598086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2610598086
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.957525553
Short name T36
Test name
Test status
Simulation time 2877083253 ps
CPU time 1.22 seconds
Started Jun 25 05:47:30 PM PDT 24
Finished Jun 25 05:47:32 PM PDT 24
Peak memory 184012 kb
Host smart-f18a75c8-9b24-4c6e-8e31-6f0873ab43af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957525553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.957525553
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1644362757
Short name T387
Test name
Test status
Simulation time 476668324 ps
CPU time 2.99 seconds
Started Jun 25 05:47:33 PM PDT 24
Finished Jun 25 05:47:37 PM PDT 24
Peak memory 198656 kb
Host smart-9811c5a5-3d72-4b6e-bb15-f6ee93330bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644362757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1644362757
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.794822832
Short name T420
Test name
Test status
Simulation time 4028171657 ps
CPU time 3.36 seconds
Started Jun 25 05:47:29 PM PDT 24
Finished Jun 25 05:47:33 PM PDT 24
Peak memory 197620 kb
Host smart-2063dde8-1bf9-4974-8143-a5df9d4732c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794822832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.794822832
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2570789885
Short name T363
Test name
Test status
Simulation time 421478996 ps
CPU time 1.27 seconds
Started Jun 25 05:47:30 PM PDT 24
Finished Jun 25 05:47:32 PM PDT 24
Peak memory 196256 kb
Host smart-5b44a2f8-016d-4f46-a5ff-922192a08fa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570789885 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2570789885
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1453789350
Short name T368
Test name
Test status
Simulation time 297574184 ps
CPU time 0.93 seconds
Started Jun 25 05:47:30 PM PDT 24
Finished Jun 25 05:47:32 PM PDT 24
Peak memory 193056 kb
Host smart-e5334e87-896f-4945-9c66-f65876a7bbb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453789350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1453789350
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1666026018
Short name T419
Test name
Test status
Simulation time 1258224247 ps
CPU time 3.68 seconds
Started Jun 25 05:47:30 PM PDT 24
Finished Jun 25 05:47:34 PM PDT 24
Peak memory 193032 kb
Host smart-b65d974f-0ec7-4eb5-a500-08a22a7da29a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666026018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1666026018
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2662527963
Short name T306
Test name
Test status
Simulation time 493297251 ps
CPU time 1.59 seconds
Started Jun 25 05:47:29 PM PDT 24
Finished Jun 25 05:47:31 PM PDT 24
Peak memory 198684 kb
Host smart-d2d12816-75c3-43a7-bd9f-2b4676e32c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662527963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2662527963
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3530619934
Short name T40
Test name
Test status
Simulation time 7959363684 ps
CPU time 7.32 seconds
Started Jun 25 05:47:29 PM PDT 24
Finished Jun 25 05:47:37 PM PDT 24
Peak memory 198304 kb
Host smart-191148b3-6a39-444d-bc35-e3ceca11a696
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530619934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3530619934
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2795012118
Short name T326
Test name
Test status
Simulation time 471654316 ps
CPU time 0.8 seconds
Started Jun 25 05:47:30 PM PDT 24
Finished Jun 25 05:47:32 PM PDT 24
Peak memory 196080 kb
Host smart-5d8adfe3-2da1-4d5a-9665-3ffec813c3ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795012118 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2795012118
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1205421161
Short name T335
Test name
Test status
Simulation time 520168678 ps
CPU time 0.76 seconds
Started Jun 25 05:47:31 PM PDT 24
Finished Jun 25 05:47:33 PM PDT 24
Peak memory 193048 kb
Host smart-e80d4c3c-1596-4cd2-9307-000b402e75ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205421161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1205421161
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1801133144
Short name T305
Test name
Test status
Simulation time 310964015 ps
CPU time 0.63 seconds
Started Jun 25 05:47:33 PM PDT 24
Finished Jun 25 05:47:35 PM PDT 24
Peak memory 183832 kb
Host smart-3f66d0b4-6ea6-473b-9e23-1d425d3d4c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801133144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1801133144
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3888290656
Short name T86
Test name
Test status
Simulation time 924191931 ps
CPU time 2.78 seconds
Started Jun 25 05:47:31 PM PDT 24
Finished Jun 25 05:47:35 PM PDT 24
Peak memory 194064 kb
Host smart-56766ee2-5460-4d85-b93a-49b2ce796449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888290656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3888290656
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3205120374
Short name T297
Test name
Test status
Simulation time 513020767 ps
CPU time 2.21 seconds
Started Jun 25 05:47:31 PM PDT 24
Finished Jun 25 05:47:34 PM PDT 24
Peak memory 198700 kb
Host smart-ac9ebd36-fd5d-402f-a6ff-c373425ccd1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205120374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3205120374
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4093586973
Short name T408
Test name
Test status
Simulation time 4180846617 ps
CPU time 1.99 seconds
Started Jun 25 05:47:29 PM PDT 24
Finished Jun 25 05:47:32 PM PDT 24
Peak memory 197864 kb
Host smart-24683ca2-2084-4cdb-bd70-47488a9faed1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093586973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.4093586973
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.478304823
Short name T219
Test name
Test status
Simulation time 34318105865 ps
CPU time 13.04 seconds
Started Jun 25 05:45:51 PM PDT 24
Finished Jun 25 05:46:05 PM PDT 24
Peak memory 196756 kb
Host smart-6c0b2fe1-508b-497e-9eb6-b27b6dcca04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478304823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.478304823
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.641663464
Short name T73
Test name
Test status
Simulation time 543636196 ps
CPU time 0.94 seconds
Started Jun 25 05:45:51 PM PDT 24
Finished Jun 25 05:45:53 PM PDT 24
Peak memory 196472 kb
Host smart-21245e5a-ce5f-4f9e-a4b6-1834b3c8d383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641663464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.641663464
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3484082285
Short name T197
Test name
Test status
Simulation time 517567526 ps
CPU time 1.22 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:46:01 PM PDT 24
Peak memory 196484 kb
Host smart-2dcbbbe5-c228-40ae-8e5d-c04652037d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484082285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3484082285
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2905160497
Short name T26
Test name
Test status
Simulation time 20907973320 ps
CPU time 14.78 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:46:14 PM PDT 24
Peak memory 191716 kb
Host smart-8483d34a-f9cb-439f-a3e9-54052a61f486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905160497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2905160497
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.42357795
Short name T24
Test name
Test status
Simulation time 7757765778 ps
CPU time 12.05 seconds
Started Jun 25 05:45:58 PM PDT 24
Finished Jun 25 05:46:11 PM PDT 24
Peak memory 215808 kb
Host smart-a9583203-96fc-4f08-8171-23659f0f3dbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42357795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.42357795
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3529385149
Short name T279
Test name
Test status
Simulation time 505979222 ps
CPU time 1.32 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:46:01 PM PDT 24
Peak memory 190920 kb
Host smart-88556309-879e-4a8b-9af6-9059297425f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529385149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3529385149
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2233151749
Short name T232
Test name
Test status
Simulation time 20109227223 ps
CPU time 29.83 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:40 PM PDT 24
Peak memory 196732 kb
Host smart-4e4eded8-b655-41c7-ace7-87e7034279d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233151749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2233151749
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.371226824
Short name T1
Test name
Test status
Simulation time 454507290 ps
CPU time 0.91 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:11 PM PDT 24
Peak memory 196480 kb
Host smart-f7820ca9-c15d-484d-a61a-a5720ba81a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371226824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.371226824
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2333374703
Short name T30
Test name
Test status
Simulation time 7049695784 ps
CPU time 1.83 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:12 PM PDT 24
Peak memory 191728 kb
Host smart-d23c087c-72bc-49b5-af21-39df5bb31b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333374703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2333374703
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3175432070
Short name T282
Test name
Test status
Simulation time 529802860 ps
CPU time 1.25 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:11 PM PDT 24
Peak memory 191664 kb
Host smart-135ea120-fff5-4df0-a455-730d7dd60c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175432070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3175432070
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.4098343079
Short name T250
Test name
Test status
Simulation time 32955969855 ps
CPU time 26.16 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:37 PM PDT 24
Peak memory 196732 kb
Host smart-3dafe556-3336-44b7-989a-5a301d3f1d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098343079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.4098343079
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.48850928
Short name T28
Test name
Test status
Simulation time 579137018 ps
CPU time 1.36 seconds
Started Jun 25 05:46:07 PM PDT 24
Finished Jun 25 05:46:10 PM PDT 24
Peak memory 191632 kb
Host smart-74306ede-fa59-43bb-bbd6-3bd8dd51dffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48850928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.48850928
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.682358320
Short name T54
Test name
Test status
Simulation time 45606059685 ps
CPU time 32.34 seconds
Started Jun 25 05:46:09 PM PDT 24
Finished Jun 25 05:46:43 PM PDT 24
Peak memory 191724 kb
Host smart-4e0f785c-82e4-47e8-bc45-63ee6f7c7692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682358320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.682358320
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3946378479
Short name T252
Test name
Test status
Simulation time 467717437 ps
CPU time 1.07 seconds
Started Jun 25 05:46:07 PM PDT 24
Finished Jun 25 05:46:10 PM PDT 24
Peak memory 191664 kb
Host smart-da820b86-8643-42d2-8a5d-26ab8ef7f3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946378479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3946378479
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1585687040
Short name T285
Test name
Test status
Simulation time 26762019437 ps
CPU time 17.14 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:27 PM PDT 24
Peak memory 191708 kb
Host smart-4bf81c2d-ead5-4e99-84a4-8867eac0b5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585687040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1585687040
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1059595669
Short name T79
Test name
Test status
Simulation time 580828700 ps
CPU time 0.79 seconds
Started Jun 25 05:46:07 PM PDT 24
Finished Jun 25 05:46:10 PM PDT 24
Peak memory 191664 kb
Host smart-29199949-7a23-4835-8854-62ee17ba384e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059595669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1059595669
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.542784320
Short name T258
Test name
Test status
Simulation time 4668051218 ps
CPU time 7.52 seconds
Started Jun 25 05:46:16 PM PDT 24
Finished Jun 25 05:46:26 PM PDT 24
Peak memory 191736 kb
Host smart-c05fbaed-1555-4dc6-a473-180bff4279e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542784320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.542784320
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2918423016
Short name T251
Test name
Test status
Simulation time 580896072 ps
CPU time 1.03 seconds
Started Jun 25 05:46:16 PM PDT 24
Finished Jun 25 05:46:19 PM PDT 24
Peak memory 191680 kb
Host smart-d6ca882a-4c15-42dc-a3b2-31465b301e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918423016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2918423016
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1577457128
Short name T286
Test name
Test status
Simulation time 22435901459 ps
CPU time 6.32 seconds
Started Jun 25 05:46:16 PM PDT 24
Finished Jun 25 05:46:25 PM PDT 24
Peak memory 191724 kb
Host smart-81018aab-5358-462e-86ea-a2314b6e623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577457128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1577457128
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3907963499
Short name T224
Test name
Test status
Simulation time 596202745 ps
CPU time 1.41 seconds
Started Jun 25 05:46:15 PM PDT 24
Finished Jun 25 05:46:17 PM PDT 24
Peak memory 191588 kb
Host smart-8ce91660-016d-4e96-8438-e8b84609aac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907963499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3907963499
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1830095583
Short name T209
Test name
Test status
Simulation time 22543980923 ps
CPU time 9.23 seconds
Started Jun 25 05:46:15 PM PDT 24
Finished Jun 25 05:46:26 PM PDT 24
Peak memory 196720 kb
Host smart-7968e23b-020c-4549-a823-7645838cf840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830095583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1830095583
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1991362913
Short name T254
Test name
Test status
Simulation time 371148442 ps
CPU time 0.85 seconds
Started Jun 25 05:46:15 PM PDT 24
Finished Jun 25 05:46:18 PM PDT 24
Peak memory 191648 kb
Host smart-9aa78348-a68b-4ee3-8d44-a5a08daf23c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991362913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1991362913
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1554024500
Short name T244
Test name
Test status
Simulation time 21747678809 ps
CPU time 7.2 seconds
Started Jun 25 05:46:18 PM PDT 24
Finished Jun 25 05:46:26 PM PDT 24
Peak memory 191720 kb
Host smart-ae22ad5f-2720-4d57-9fea-91bb731a2cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554024500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1554024500
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1415427948
Short name T261
Test name
Test status
Simulation time 433726816 ps
CPU time 0.73 seconds
Started Jun 25 05:46:16 PM PDT 24
Finished Jun 25 05:46:19 PM PDT 24
Peak memory 191656 kb
Host smart-14e98089-33b7-46f2-9ca7-84eef3a15b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415427948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1415427948
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2173745272
Short name T262
Test name
Test status
Simulation time 32287983523 ps
CPU time 3.01 seconds
Started Jun 25 05:46:17 PM PDT 24
Finished Jun 25 05:46:22 PM PDT 24
Peak memory 191712 kb
Host smart-07990dff-83cb-460a-b268-ca0f80f9337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173745272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2173745272
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1621137730
Short name T272
Test name
Test status
Simulation time 365983377 ps
CPU time 1.1 seconds
Started Jun 25 05:46:15 PM PDT 24
Finished Jun 25 05:46:17 PM PDT 24
Peak memory 191652 kb
Host smart-c155ded4-b1e5-4952-85c6-6b6fbc088d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621137730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1621137730
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.604239032
Short name T253
Test name
Test status
Simulation time 20912253733 ps
CPU time 14.69 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:46:15 PM PDT 24
Peak memory 191740 kb
Host smart-799fb3a7-871d-4b0d-a2f4-f0b0ad6e5f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604239032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.604239032
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.474994486
Short name T21
Test name
Test status
Simulation time 8266122581 ps
CPU time 3.46 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:46:03 PM PDT 24
Peak memory 215736 kb
Host smart-f1db4ab1-9bb0-48d0-a762-30f03f374c16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474994486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.474994486
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3332758869
Short name T263
Test name
Test status
Simulation time 483950883 ps
CPU time 1.25 seconds
Started Jun 25 05:45:58 PM PDT 24
Finished Jun 25 05:46:00 PM PDT 24
Peak memory 191648 kb
Host smart-86afeb65-5734-44ab-b0dd-50a359b981b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332758869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3332758869
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1348665953
Short name T74
Test name
Test status
Simulation time 43779175034 ps
CPU time 15.08 seconds
Started Jun 25 05:46:17 PM PDT 24
Finished Jun 25 05:46:34 PM PDT 24
Peak memory 191488 kb
Host smart-8bbf2428-9bcb-4a1d-8084-16ea3d1b061f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348665953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1348665953
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3364454088
Short name T220
Test name
Test status
Simulation time 488172045 ps
CPU time 1.28 seconds
Started Jun 25 05:46:14 PM PDT 24
Finished Jun 25 05:46:16 PM PDT 24
Peak memory 191656 kb
Host smart-cd598a6d-bf9a-418c-b54c-6780a6269edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364454088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3364454088
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.634872118
Short name T33
Test name
Test status
Simulation time 36494805475 ps
CPU time 27.52 seconds
Started Jun 25 05:46:18 PM PDT 24
Finished Jun 25 05:46:47 PM PDT 24
Peak memory 196608 kb
Host smart-b96a00e4-a6df-4c8c-9d0e-4abe1ff06a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634872118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.634872118
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2569254201
Short name T214
Test name
Test status
Simulation time 437053837 ps
CPU time 1.18 seconds
Started Jun 25 05:46:15 PM PDT 24
Finished Jun 25 05:46:19 PM PDT 24
Peak memory 191584 kb
Host smart-9d89bc5b-57ff-4ce7-8e03-7704ac5c9025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569254201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2569254201
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_jump.513974431
Short name T171
Test name
Test status
Simulation time 382000452 ps
CPU time 0.83 seconds
Started Jun 25 05:46:34 PM PDT 24
Finished Jun 25 05:46:36 PM PDT 24
Peak memory 196412 kb
Host smart-68cb239a-a80f-4444-ab0c-720af651db05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513974431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.513974431
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1072792340
Short name T283
Test name
Test status
Simulation time 10902565019 ps
CPU time 15.7 seconds
Started Jun 25 05:46:23 PM PDT 24
Finished Jun 25 05:46:40 PM PDT 24
Peak memory 191712 kb
Host smart-5762062f-fee5-450b-b5a0-93c7c5d477e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072792340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1072792340
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.606230438
Short name T211
Test name
Test status
Simulation time 355726737 ps
CPU time 0.85 seconds
Started Jun 25 05:46:34 PM PDT 24
Finished Jun 25 05:46:36 PM PDT 24
Peak memory 191640 kb
Host smart-e9365113-d3bd-4169-8076-22e73a27f452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606230438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.606230438
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.33333420
Short name T288
Test name
Test status
Simulation time 55460671473 ps
CPU time 22.75 seconds
Started Jun 25 05:46:22 PM PDT 24
Finished Jun 25 05:46:46 PM PDT 24
Peak memory 191720 kb
Host smart-a90815a6-6b34-4414-952e-46ffeb3ac968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33333420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.33333420
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2582866461
Short name T51
Test name
Test status
Simulation time 576525257 ps
CPU time 1.29 seconds
Started Jun 25 05:46:24 PM PDT 24
Finished Jun 25 05:46:26 PM PDT 24
Peak memory 191432 kb
Host smart-70490dbd-43c7-44bd-b1a4-5d408f6cbe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582866461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2582866461
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1241308343
Short name T227
Test name
Test status
Simulation time 10599084562 ps
CPU time 7.16 seconds
Started Jun 25 05:46:24 PM PDT 24
Finished Jun 25 05:46:32 PM PDT 24
Peak memory 196508 kb
Host smart-53ca404b-44b6-4800-9912-680fc5cb5b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241308343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1241308343
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2547319881
Short name T34
Test name
Test status
Simulation time 591725382 ps
CPU time 0.67 seconds
Started Jun 25 05:46:35 PM PDT 24
Finished Jun 25 05:46:37 PM PDT 24
Peak memory 196484 kb
Host smart-303e506e-c9a3-49fe-bfb8-11e2efc96702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547319881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2547319881
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2431440436
Short name T182
Test name
Test status
Simulation time 632233372 ps
CPU time 1.1 seconds
Started Jun 25 05:46:33 PM PDT 24
Finished Jun 25 05:46:34 PM PDT 24
Peak memory 196456 kb
Host smart-0f6caefc-df08-46f2-8816-d1777c0cad72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431440436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2431440436
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1589185310
Short name T249
Test name
Test status
Simulation time 2917143720 ps
CPU time 2.58 seconds
Started Jun 25 05:46:31 PM PDT 24
Finished Jun 25 05:46:34 PM PDT 24
Peak memory 191648 kb
Host smart-68651f81-f535-45fe-874e-e3b783a6f217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589185310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1589185310
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2801195439
Short name T266
Test name
Test status
Simulation time 407217847 ps
CPU time 1.21 seconds
Started Jun 25 05:46:34 PM PDT 24
Finished Jun 25 05:46:36 PM PDT 24
Peak memory 196512 kb
Host smart-99b39c85-eec4-4ac1-b8b9-308a1387ad07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801195439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2801195439
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2651386537
Short name T9
Test name
Test status
Simulation time 30386241844 ps
CPU time 11.24 seconds
Started Jun 25 05:46:32 PM PDT 24
Finished Jun 25 05:46:44 PM PDT 24
Peak memory 196712 kb
Host smart-4cf1434e-7790-4667-a81a-b3f5899ff8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651386537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2651386537
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2858685670
Short name T27
Test name
Test status
Simulation time 414911473 ps
CPU time 1.14 seconds
Started Jun 25 05:46:34 PM PDT 24
Finished Jun 25 05:46:37 PM PDT 24
Peak memory 191664 kb
Host smart-04591440-1ab3-4fa3-b89d-d9a12796ed04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858685670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2858685670
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3875805838
Short name T278
Test name
Test status
Simulation time 13132449344 ps
CPU time 5.15 seconds
Started Jun 25 05:46:35 PM PDT 24
Finished Jun 25 05:46:42 PM PDT 24
Peak memory 191708 kb
Host smart-6c9857f3-1c93-45a2-80dc-fd5a68dff5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875805838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3875805838
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.711274606
Short name T276
Test name
Test status
Simulation time 445642311 ps
CPU time 1.25 seconds
Started Jun 25 05:46:30 PM PDT 24
Finished Jun 25 05:46:32 PM PDT 24
Peak memory 196492 kb
Host smart-8493c26f-da1c-4142-a5af-f38e4781a925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711274606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.711274606
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.102001697
Short name T53
Test name
Test status
Simulation time 49154702660 ps
CPU time 67.64 seconds
Started Jun 25 05:46:28 PM PDT 24
Finished Jun 25 05:47:37 PM PDT 24
Peak memory 191724 kb
Host smart-8ac84e0d-2574-49be-bfbf-fbbf13b7e734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102001697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.102001697
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2747157044
Short name T274
Test name
Test status
Simulation time 408711680 ps
CPU time 0.65 seconds
Started Jun 25 05:46:30 PM PDT 24
Finished Jun 25 05:46:31 PM PDT 24
Peak memory 191668 kb
Host smart-7891f445-c1ba-4dc9-9225-9cd2540d03a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747157044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2747157044
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3908952429
Short name T201
Test name
Test status
Simulation time 511168848 ps
CPU time 0.92 seconds
Started Jun 25 05:46:32 PM PDT 24
Finished Jun 25 05:46:34 PM PDT 24
Peak memory 196532 kb
Host smart-7c4515b4-68c6-4910-bab9-a18167e0bca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908952429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3908952429
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.844839022
Short name T277
Test name
Test status
Simulation time 11217235734 ps
CPU time 8.91 seconds
Started Jun 25 05:46:30 PM PDT 24
Finished Jun 25 05:46:39 PM PDT 24
Peak memory 191700 kb
Host smart-a72b779a-7e3e-44c9-98c2-de2e25b970a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844839022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.844839022
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.614212826
Short name T212
Test name
Test status
Simulation time 502357990 ps
CPU time 0.76 seconds
Started Jun 25 05:46:31 PM PDT 24
Finished Jun 25 05:46:32 PM PDT 24
Peak memory 191636 kb
Host smart-8c9336d4-e619-4b63-9edb-7646ce0ec41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614212826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.614212826
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2334361820
Short name T273
Test name
Test status
Simulation time 12988965704 ps
CPU time 10.51 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:46:10 PM PDT 24
Peak memory 196736 kb
Host smart-37d2f737-c350-4781-8bc1-4ad396800f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334361820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2334361820
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3911164901
Short name T23
Test name
Test status
Simulation time 4158644913 ps
CPU time 6.41 seconds
Started Jun 25 05:46:01 PM PDT 24
Finished Jun 25 05:46:09 PM PDT 24
Peak memory 215444 kb
Host smart-6609d4eb-4e5e-42d7-b394-c6c672807673
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911164901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3911164901
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3432387744
Short name T226
Test name
Test status
Simulation time 487240338 ps
CPU time 0.76 seconds
Started Jun 25 05:45:57 PM PDT 24
Finished Jun 25 05:45:58 PM PDT 24
Peak memory 191584 kb
Host smart-8f6493a4-d783-475e-a984-2d7aa8041a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432387744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3432387744
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4206889758
Short name T280
Test name
Test status
Simulation time 39998900952 ps
CPU time 53.96 seconds
Started Jun 25 05:46:32 PM PDT 24
Finished Jun 25 05:47:26 PM PDT 24
Peak memory 191716 kb
Host smart-56100550-4f1b-4226-b6f2-003aaf83e576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206889758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4206889758
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.417553968
Short name T256
Test name
Test status
Simulation time 481281960 ps
CPU time 1.24 seconds
Started Jun 25 05:46:29 PM PDT 24
Finished Jun 25 05:46:31 PM PDT 24
Peak memory 191656 kb
Host smart-45e1a17f-2357-4746-a2e9-962d86dfb261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417553968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.417553968
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1793366862
Short name T229
Test name
Test status
Simulation time 57079453852 ps
CPU time 73.86 seconds
Started Jun 25 05:46:38 PM PDT 24
Finished Jun 25 05:47:53 PM PDT 24
Peak memory 196728 kb
Host smart-7757026d-5fca-4828-b5d6-fce7459f6980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793366862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1793366862
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1718233999
Short name T240
Test name
Test status
Simulation time 581036243 ps
CPU time 0.67 seconds
Started Jun 25 05:46:42 PM PDT 24
Finished Jun 25 05:46:44 PM PDT 24
Peak memory 191588 kb
Host smart-a8e4f955-3d31-4cf8-afc6-5759bf9cdd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718233999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1718233999
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1007111722
Short name T257
Test name
Test status
Simulation time 31036030846 ps
CPU time 21.34 seconds
Started Jun 25 05:46:38 PM PDT 24
Finished Jun 25 05:46:59 PM PDT 24
Peak memory 191716 kb
Host smart-9bb3ee32-2d2d-4428-a357-8499bcf7a308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007111722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1007111722
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.714811355
Short name T269
Test name
Test status
Simulation time 553919172 ps
CPU time 0.8 seconds
Started Jun 25 05:46:38 PM PDT 24
Finished Jun 25 05:46:39 PM PDT 24
Peak memory 191632 kb
Host smart-d39d8dc9-f05d-4b09-868b-2f5f608c3837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714811355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.714811355
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2687030808
Short name T188
Test name
Test status
Simulation time 386086101 ps
CPU time 0.74 seconds
Started Jun 25 05:46:39 PM PDT 24
Finished Jun 25 05:46:41 PM PDT 24
Peak memory 196444 kb
Host smart-1f1d3289-101c-43e0-a083-fd23185718d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687030808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2687030808
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.32159629
Short name T242
Test name
Test status
Simulation time 3374626916 ps
CPU time 2.12 seconds
Started Jun 25 05:46:39 PM PDT 24
Finished Jun 25 05:46:42 PM PDT 24
Peak memory 191716 kb
Host smart-9612c043-cf84-4c0c-b1e7-b0f6dee118fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32159629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.32159629
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3774255008
Short name T80
Test name
Test status
Simulation time 340045173 ps
CPU time 1.05 seconds
Started Jun 25 05:46:39 PM PDT 24
Finished Jun 25 05:46:41 PM PDT 24
Peak memory 191660 kb
Host smart-2e2e3363-30dd-4ece-bd4e-78556f9844e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774255008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3774255008
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3701668496
Short name T243
Test name
Test status
Simulation time 19085865214 ps
CPU time 12.58 seconds
Started Jun 25 05:46:57 PM PDT 24
Finished Jun 25 05:47:11 PM PDT 24
Peak memory 196712 kb
Host smart-4ff7eed7-1d2f-4755-8871-9957663e830a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701668496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3701668496
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.4005887405
Short name T247
Test name
Test status
Simulation time 485319742 ps
CPU time 1.29 seconds
Started Jun 25 05:46:45 PM PDT 24
Finished Jun 25 05:46:47 PM PDT 24
Peak memory 196480 kb
Host smart-79e87f2c-a384-4064-aee3-d7d869bdbf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005887405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4005887405
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2530318158
Short name T231
Test name
Test status
Simulation time 50570044825 ps
CPU time 78.29 seconds
Started Jun 25 05:46:47 PM PDT 24
Finished Jun 25 05:48:06 PM PDT 24
Peak memory 196736 kb
Host smart-dbdd66ca-03c4-400c-ac1b-c21ef194a918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530318158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2530318158
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1834631628
Short name T222
Test name
Test status
Simulation time 414242137 ps
CPU time 0.81 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:47:01 PM PDT 24
Peak memory 191680 kb
Host smart-578b7190-8cf7-45c8-9cae-dfcb1bd23c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834631628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1834631628
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.782613316
Short name T246
Test name
Test status
Simulation time 8944754433 ps
CPU time 3.87 seconds
Started Jun 25 05:46:46 PM PDT 24
Finished Jun 25 05:46:51 PM PDT 24
Peak memory 191736 kb
Host smart-b1b2eaed-dcec-4a03-a5c5-c29f03fd92e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782613316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.782613316
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2974219704
Short name T245
Test name
Test status
Simulation time 384774400 ps
CPU time 1.11 seconds
Started Jun 25 05:46:46 PM PDT 24
Finished Jun 25 05:46:48 PM PDT 24
Peak memory 191624 kb
Host smart-337bbb2f-b0a0-4e54-aada-1583af9c2abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974219704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2974219704
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1009744454
Short name T177
Test name
Test status
Simulation time 540723890 ps
CPU time 0.79 seconds
Started Jun 25 05:46:46 PM PDT 24
Finished Jun 25 05:46:47 PM PDT 24
Peak memory 196448 kb
Host smart-72990747-fd14-4620-b3b3-29816717995f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009744454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1009744454
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.960808472
Short name T268
Test name
Test status
Simulation time 25436298947 ps
CPU time 37.88 seconds
Started Jun 25 05:46:58 PM PDT 24
Finished Jun 25 05:47:36 PM PDT 24
Peak memory 196720 kb
Host smart-e70186a3-f293-4d24-b3fb-feb0c6f0ce95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960808472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.960808472
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1728545681
Short name T233
Test name
Test status
Simulation time 476982890 ps
CPU time 0.76 seconds
Started Jun 25 05:46:47 PM PDT 24
Finished Jun 25 05:46:49 PM PDT 24
Peak memory 196696 kb
Host smart-f19a9622-66f9-4262-9023-e3ace7639ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728545681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1728545681
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3901405359
Short name T221
Test name
Test status
Simulation time 13356391107 ps
CPU time 2.55 seconds
Started Jun 25 05:46:57 PM PDT 24
Finished Jun 25 05:47:01 PM PDT 24
Peak memory 191492 kb
Host smart-5d5fef90-ab1e-4edd-87fb-a68813ad8dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901405359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3901405359
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.4202208783
Short name T225
Test name
Test status
Simulation time 462112445 ps
CPU time 0.8 seconds
Started Jun 25 05:46:45 PM PDT 24
Finished Jun 25 05:46:46 PM PDT 24
Peak memory 196448 kb
Host smart-6112a6c4-5d20-417b-8032-60984882cd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202208783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4202208783
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2119876319
Short name T192
Test name
Test status
Simulation time 373712488 ps
CPU time 1.12 seconds
Started Jun 25 05:46:47 PM PDT 24
Finished Jun 25 05:46:49 PM PDT 24
Peak memory 196516 kb
Host smart-aef615c9-8c8b-49c3-b86d-d94f50b2c661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119876319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2119876319
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.4244075110
Short name T216
Test name
Test status
Simulation time 15785766254 ps
CPU time 20.77 seconds
Started Jun 25 05:46:48 PM PDT 24
Finished Jun 25 05:47:10 PM PDT 24
Peak memory 191640 kb
Host smart-8c91f71c-a509-4054-9909-b1ccd40324c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244075110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.4244075110
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3503889425
Short name T255
Test name
Test status
Simulation time 592433021 ps
CPU time 0.81 seconds
Started Jun 25 05:46:46 PM PDT 24
Finished Jun 25 05:46:49 PM PDT 24
Peak memory 196512 kb
Host smart-cb360f5b-925d-42d9-86c0-a30a33cd0320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503889425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3503889425
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3872030050
Short name T228
Test name
Test status
Simulation time 8299482108 ps
CPU time 3.34 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:46:03 PM PDT 24
Peak memory 190900 kb
Host smart-0ba3442f-e921-44ce-9679-a42a027ce60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872030050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3872030050
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2911039068
Short name T25
Test name
Test status
Simulation time 3967738420 ps
CPU time 2.16 seconds
Started Jun 25 05:46:04 PM PDT 24
Finished Jun 25 05:46:07 PM PDT 24
Peak memory 215376 kb
Host smart-ec481bb5-f8ff-44a3-9d3a-2414ba11cb80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911039068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2911039068
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3619372355
Short name T50
Test name
Test status
Simulation time 471083445 ps
CPU time 1.24 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:46:01 PM PDT 24
Peak memory 191676 kb
Host smart-e64061d3-3e47-4865-9981-b56c75b5be5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619372355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3619372355
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.4230152534
Short name T3
Test name
Test status
Simulation time 67989044067 ps
CPU time 43.85 seconds
Started Jun 25 05:45:59 PM PDT 24
Finished Jun 25 05:46:44 PM PDT 24
Peak memory 191720 kb
Host smart-93bf829d-f261-496c-ab39-52c44838129a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230152534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.4230152534
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2654167843
Short name T271
Test name
Test status
Simulation time 11686731416 ps
CPU time 18.88 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:47:19 PM PDT 24
Peak memory 191712 kb
Host smart-86dcb0f1-c8df-41b1-975e-8b89f5dec1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654167843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2654167843
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1702749284
Short name T264
Test name
Test status
Simulation time 554032423 ps
CPU time 1.49 seconds
Started Jun 25 05:46:48 PM PDT 24
Finished Jun 25 05:46:51 PM PDT 24
Peak memory 191676 kb
Host smart-56278999-b6c8-494c-80b3-f73c22353263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702749284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1702749284
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.236335681
Short name T275
Test name
Test status
Simulation time 9740480199 ps
CPU time 14.65 seconds
Started Jun 25 05:47:00 PM PDT 24
Finished Jun 25 05:47:16 PM PDT 24
Peak memory 196756 kb
Host smart-acbb835b-e50e-4962-a848-89b5b2c77949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236335681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.236335681
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2539100104
Short name T49
Test name
Test status
Simulation time 481605599 ps
CPU time 0.78 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:47:01 PM PDT 24
Peak memory 191660 kb
Host smart-9d2669c6-f6cf-4e9c-a092-2268ead594a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539100104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2539100104
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2077623928
Short name T267
Test name
Test status
Simulation time 12364805206 ps
CPU time 16.6 seconds
Started Jun 25 05:46:57 PM PDT 24
Finished Jun 25 05:47:15 PM PDT 24
Peak memory 196724 kb
Host smart-40365474-99c6-4793-a39d-565ce48de445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077623928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2077623928
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2996655527
Short name T248
Test name
Test status
Simulation time 552953715 ps
CPU time 1.47 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:47:02 PM PDT 24
Peak memory 191592 kb
Host smart-91441e23-66ad-4e27-a0b3-7681cdd7f056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996655527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2996655527
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.4286180778
Short name T239
Test name
Test status
Simulation time 36137413555 ps
CPU time 9.65 seconds
Started Jun 25 05:47:01 PM PDT 24
Finished Jun 25 05:47:12 PM PDT 24
Peak memory 196716 kb
Host smart-06c1f075-6c1b-4428-80a8-a15c522b0300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286180778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.4286180778
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.197363782
Short name T29
Test name
Test status
Simulation time 442818984 ps
CPU time 0.92 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:47:01 PM PDT 24
Peak memory 196484 kb
Host smart-f5eb4df6-1f2f-4223-ae32-4f6044fd1290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197363782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.197363782
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2065378682
Short name T191
Test name
Test status
Simulation time 572294681 ps
CPU time 1.37 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:47:01 PM PDT 24
Peak memory 196456 kb
Host smart-17a0a4e4-9949-4c8c-8d5e-f856f837eb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065378682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2065378682
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1127607074
Short name T241
Test name
Test status
Simulation time 24950085623 ps
CPU time 3.19 seconds
Started Jun 25 05:47:01 PM PDT 24
Finished Jun 25 05:47:05 PM PDT 24
Peak memory 191712 kb
Host smart-07a26d38-3106-4184-889c-7d867e2c05fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127607074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1127607074
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3172275100
Short name T238
Test name
Test status
Simulation time 387135347 ps
CPU time 1.17 seconds
Started Jun 25 05:47:02 PM PDT 24
Finished Jun 25 05:47:04 PM PDT 24
Peak memory 196432 kb
Host smart-270aaed0-91b3-4d12-8a73-03aabe59cd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172275100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3172275100
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1583656940
Short name T236
Test name
Test status
Simulation time 20623240463 ps
CPU time 26.5 seconds
Started Jun 25 05:47:04 PM PDT 24
Finished Jun 25 05:47:31 PM PDT 24
Peak memory 191716 kb
Host smart-7ff4f9b2-6de9-4d5b-890c-64c03d3fe3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583656940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1583656940
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2580780278
Short name T218
Test name
Test status
Simulation time 334821808 ps
CPU time 1.01 seconds
Started Jun 25 05:46:59 PM PDT 24
Finished Jun 25 05:47:02 PM PDT 24
Peak memory 191656 kb
Host smart-9c028e53-6be3-4cbd-bc1f-f3705383baee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580780278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2580780278
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2971632984
Short name T260
Test name
Test status
Simulation time 44113282093 ps
CPU time 13.47 seconds
Started Jun 25 05:47:04 PM PDT 24
Finished Jun 25 05:47:18 PM PDT 24
Peak memory 191696 kb
Host smart-ddbef400-9b99-4f69-a49b-0b7d4ac30192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971632984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2971632984
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2227170208
Short name T217
Test name
Test status
Simulation time 385948818 ps
CPU time 0.7 seconds
Started Jun 25 05:47:03 PM PDT 24
Finished Jun 25 05:47:04 PM PDT 24
Peak memory 191652 kb
Host smart-16cff721-25ba-4e40-a51b-939cd7191d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227170208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2227170208
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1626236682
Short name T78
Test name
Test status
Simulation time 351653272 ps
CPU time 0.86 seconds
Started Jun 25 05:47:05 PM PDT 24
Finished Jun 25 05:47:07 PM PDT 24
Peak memory 196468 kb
Host smart-ff4f6b8b-257a-47a4-bda4-a7a7f8541fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626236682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1626236682
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2701626142
Short name T230
Test name
Test status
Simulation time 61545092023 ps
CPU time 45.37 seconds
Started Jun 25 05:47:05 PM PDT 24
Finished Jun 25 05:47:52 PM PDT 24
Peak memory 191720 kb
Host smart-70a98b53-8226-4b14-b77c-99aace3edfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701626142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2701626142
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1340612727
Short name T237
Test name
Test status
Simulation time 659473203 ps
CPU time 0.63 seconds
Started Jun 25 05:47:05 PM PDT 24
Finished Jun 25 05:47:07 PM PDT 24
Peak memory 196508 kb
Host smart-395a0968-8c9b-4fab-b5cf-ca3bd62f501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340612727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1340612727
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.4104818487
Short name T223
Test name
Test status
Simulation time 43723397812 ps
CPU time 15.45 seconds
Started Jun 25 05:47:07 PM PDT 24
Finished Jun 25 05:47:23 PM PDT 24
Peak memory 191724 kb
Host smart-eade0b20-7fbb-462f-90ba-33e2177e0e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104818487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4104818487
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.4217001260
Short name T234
Test name
Test status
Simulation time 460101668 ps
CPU time 1.16 seconds
Started Jun 25 05:47:04 PM PDT 24
Finished Jun 25 05:47:06 PM PDT 24
Peak memory 191644 kb
Host smart-dbbb1e44-f9ef-410f-b974-89cd7b4eb876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217001260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.4217001260
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2646912640
Short name T281
Test name
Test status
Simulation time 15314252808 ps
CPU time 10.37 seconds
Started Jun 25 05:47:05 PM PDT 24
Finished Jun 25 05:47:17 PM PDT 24
Peak memory 191708 kb
Host smart-bd6b42af-947e-41ca-a3f2-7bd10b0b7cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646912640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2646912640
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3682093157
Short name T18
Test name
Test status
Simulation time 355432086 ps
CPU time 1.04 seconds
Started Jun 25 05:47:06 PM PDT 24
Finished Jun 25 05:47:08 PM PDT 24
Peak memory 196536 kb
Host smart-88e59db5-38e7-45ef-a90e-2f4edfcbad9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682093157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3682093157
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.75528561
Short name T259
Test name
Test status
Simulation time 10609852679 ps
CPU time 4.23 seconds
Started Jun 25 05:46:08 PM PDT 24
Finished Jun 25 05:46:14 PM PDT 24
Peak memory 191724 kb
Host smart-0e59dbca-c9be-49d9-a8ed-18db400d4281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75528561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.75528561
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2296543187
Short name T5
Test name
Test status
Simulation time 433002815 ps
CPU time 0.72 seconds
Started Jun 25 05:45:57 PM PDT 24
Finished Jun 25 05:45:59 PM PDT 24
Peak memory 191652 kb
Host smart-e0531d6d-f4d0-4b09-832e-171262ed476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296543187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2296543187
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3825001197
Short name T185
Test name
Test status
Simulation time 431572331 ps
CPU time 0.74 seconds
Started Jun 25 05:46:06 PM PDT 24
Finished Jun 25 05:46:08 PM PDT 24
Peak memory 196548 kb
Host smart-acf8e066-6de8-4fff-bbd1-bdaaf152c962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825001197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3825001197
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3587243117
Short name T6
Test name
Test status
Simulation time 45834915685 ps
CPU time 15.53 seconds
Started Jun 25 05:46:06 PM PDT 24
Finished Jun 25 05:46:22 PM PDT 24
Peak memory 191716 kb
Host smart-0d463656-fe73-40ab-a99d-cd9815e17884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587243117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3587243117
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3707737257
Short name T215
Test name
Test status
Simulation time 497501921 ps
CPU time 0.77 seconds
Started Jun 25 05:46:09 PM PDT 24
Finished Jun 25 05:46:12 PM PDT 24
Peak memory 191660 kb
Host smart-e8d9770b-c38b-4145-ac74-1e61371d8187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707737257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3707737257
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1148562939
Short name T270
Test name
Test status
Simulation time 1108652655 ps
CPU time 1.01 seconds
Started Jun 25 05:46:06 PM PDT 24
Finished Jun 25 05:46:07 PM PDT 24
Peak memory 196300 kb
Host smart-4b2d54d7-d2de-42e5-b06e-499c3b2ce1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148562939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1148562939
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.337801532
Short name T213
Test name
Test status
Simulation time 567346626 ps
CPU time 1.33 seconds
Started Jun 25 05:46:05 PM PDT 24
Finished Jun 25 05:46:07 PM PDT 24
Peak memory 196428 kb
Host smart-89e28f6a-4751-4668-90e0-6304b1b94e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337801532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.337801532
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2465627194
Short name T287
Test name
Test status
Simulation time 14991666798 ps
CPU time 5.41 seconds
Started Jun 25 05:46:07 PM PDT 24
Finished Jun 25 05:46:13 PM PDT 24
Peak memory 191720 kb
Host smart-bf820e90-3ed4-4202-a638-f3e9f4555e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465627194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2465627194
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2649174896
Short name T265
Test name
Test status
Simulation time 474499150 ps
CPU time 0.96 seconds
Started Jun 25 05:46:06 PM PDT 24
Finished Jun 25 05:46:08 PM PDT 24
Peak memory 196512 kb
Host smart-9257ef52-337e-4e8f-9fab-fd0013397241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649174896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2649174896
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3271982839
Short name T235
Test name
Test status
Simulation time 11477992745 ps
CPU time 16.36 seconds
Started Jun 25 05:46:06 PM PDT 24
Finished Jun 25 05:46:24 PM PDT 24
Peak memory 191700 kb
Host smart-f996c73c-9cd1-49ba-9a2d-9dffafdd6104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271982839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3271982839
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3819082011
Short name T284
Test name
Test status
Simulation time 496521920 ps
CPU time 0.94 seconds
Started Jun 25 05:46:09 PM PDT 24
Finished Jun 25 05:46:12 PM PDT 24
Peak memory 191648 kb
Host smart-cbbf254d-bad7-4d99-a4f7-fc210e18b7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819082011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3819082011
Directory /workspace/9.aon_timer_smoke/latest
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