Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	34767	1		T1	216		T2	12		T7	11
bark[1]	262	1		T10	21		T146	21		T135	21
bark[2]	323	1		T43	14		T26	26		T81	21
bark[3]	1302	1		T34	1002		T119	49		T159	26
bark[4]	225	1		T128	21		T133	26		T73	21
bark[5]	171	1		T119	61		T73	26		T98	14
bark[6]	332	1		T1	42		T16	26		T103	14
bark[7]	142	1		T138	26		T33	7		T79	44
bark[8]	833	1		T107	14		T36	7		T108	14
bark[9]	1042	1		T80	73		T109	21		T88	200
bark[10]	326	1		T80	48		T146	21		T143	14
bark[11]	235	1		T34	30		T147	21		T87	42
bark[12]	419	1		T6	14		T81	21		T99	21
bark[13]	281	1		T146	59		T82	14		T114	21
bark[14]	358	1		T174	14		T119	21		T159	26
bark[15]	1435	1		T25	14		T81	21		T82	21
bark[16]	539	1		T35	44		T135	30		T99	51
bark[17]	251	1		T126	14		T84	30		T141	23
bark[18]	552	1		T40	14		T33	21		T37	26
bark[19]	906	1		T1	21		T20	30		T42	21
bark[20]	459	1		T13	68		T138	21		T102	23
bark[21]	940	1		T16	250		T138	49		T33	62
bark[22]	612	1		T155	21		T33	30		T142	14
bark[23]	556	1		T24	14		T138	40		T128	21
bark[24]	476	1		T146	21		T81	21		T76	26
bark[25]	824	1		T13	30		T184	14		T155	21
bark[26]	491	1		T3	14		T10	21		T80	23
bark[27]	605	1		T13	53		T16	21		T112	217
bark[28]	267	1		T4	14		T146	21		T135	14
bark[29]	1014	1		T138	35		T92	14		T135	40
bark[30]	616	1		T1	42		T5	14		T10	21
bark[31]	823	1		T23	14		T34	21		T35	7
bark_0	4848	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	34103	1		T1	215		T2	11		T7	10
bite[1]	1090	1		T1	21		T88	21		T112	314
bite[2]	645	1		T92	13		T159	26		T87	51
bite[3]	670	1		T138	34		T35	43		T119	61
bite[4]	1311	1		T13	219		T80	73		T178	30
bite[5]	425	1		T119	49		T124	21		T125	48
bite[6]	334	1		T16	21		T35	21		T99	21
bite[7]	105	1		T135	21		T106	21		T89	21
bite[8]	180	1		T5	13		T138	40		T142	13
bite[9]	817	1		T10	21		T34	21		T81	21
bite[10]	320	1		T10	21		T174	13		T100	161
bite[11]	328	1		T135	40		T84	25		T180	13
bite[12]	452	1		T16	26		T81	21		T108	13
bite[13]	288	1		T162	21		T115	13		T148	25
bite[14]	628	1		T1	42		T146	21		T128	21
bite[15]	116	1		T137	13		T83	21		T73	21
bite[16]	394	1		T10	80		T80	48		T159	73
bite[17]	572	1		T128	21		T144	30		T147	21
bite[18]	505	1		T13	67		T24	13		T34	30
bite[19]	255	1		T3	13		T33	21		T128	21
bite[20]	1592	1		T13	82		T26	26		T81	42
bite[21]	670	1		T43	13		T35	6		T96	26
bite[22]	574	1		T33	61		T103	13		T143	13
bite[23]	446	1		T190	13		T146	21		T151	21
bite[24]	513	1		T20	30		T138	21		T150	13
bite[25]	205	1		T23	13		T25	13		T33	30
bite[26]	272	1		T138	26		T33	6		T36	6
bite[27]	226	1		T42	21		T107	13		T84	21
bite[28]	807	1		T6	13		T16	249		T138	49
bite[29]	701	1		T1	21		T4	13		T40	13
bite[30]	1464	1		T10	21		T184	13		T155	21
bite[31]	850	1		T1	21		T146	80		T82	21
bite_0	5374	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	57232	1		T1	328		T2	19		T3	21

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	925	1		T13	19		T155	19		T34	103
prescale[1]	1036	1		T15	19		T42	28		T26	45
prescale[2]	1591	1		T14	9		T15	79		T16	48
prescale[3]	1137	1		T13	2		T26	19		T196	9
prescale[4]	1532	1		T12	9		T13	39		T33	60
prescale[5]	937	1		T15	9		T34	91		T178	9
prescale[6]	794	1		T10	44		T13	4		T15	9
prescale[7]	1099	1		T39	9		T42	23		T138	23
prescale[8]	1030	1		T13	41		T197	9		T138	19
prescale[9]	1048	1		T26	2		T102	56		T109	103
prescale[10]	597	1		T198	9		T34	2		T199	9
prescale[11]	1685	1		T10	32		T13	50		T15	161
prescale[12]	723	1		T26	19		T33	189		T200	9
prescale[13]	687	1		T10	9		T138	37		T33	2
prescale[14]	879	1		T20	19		T33	27		T35	2
prescale[15]	1007	1		T80	19		T34	12		T35	147
prescale[16]	1446	1		T1	19		T10	19		T41	9
prescale[17]	930	1		T2	9		T13	40		T15	19
prescale[18]	1182	1		T16	133		T201	9		T119	19
prescale[19]	831	1		T20	47		T26	2		T155	24
prescale[20]	692	1		T1	19		T33	2		T130	78
prescale[21]	639	1		T36	34		T151	9		T88	2
prescale[22]	608	1		T15	2		T42	19		T33	94
prescale[23]	1016	1		T1	28		T16	4		T42	19
prescale[24]	660	1		T20	58		T33	64		T80	24
prescale[25]	596	1		T1	24		T42	9		T119	77
prescale[26]	708	1		T13	26		T35	19		T147	19
prescale[27]	783	1		T16	42		T26	2		T34	60
prescale[28]	932	1		T16	2		T33	2		T34	19
prescale[29]	812	1		T15	33		T33	106		T35	19
prescale[30]	277	1		T13	2		T20	19		T112	2
prescale[31]	791	1		T1	79		T15	48		T42	19
prescale_0	27622	1		T1	159		T2	10		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	43911	1		T1	286		T2	19		T3	9
auto[1]	13321	1		T1	42		T3	12		T4	12

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	57232	1		T1	328		T2	19		T3	21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	33877	1		T1	176		T2	14		T3	1
wkup[1]	317	1		T15	21		T119	21		T146	21
wkup[2]	218	1		T10	21		T112	21		T164	15
wkup[3]	373	1		T33	29		T146	21		T36	8
wkup[4]	120	1		T81	21		T38	21		T88	21
wkup[5]	333	1		T1	21		T13	30		T15	21
wkup[6]	320	1		T184	15		T33	21		T103	15
wkup[7]	574	1		T13	21		T15	26		T138	21
wkup[8]	204	1		T161	21		T78	21		T72	21
wkup[9]	251	1		T13	42		T34	30		T146	30
wkup[10]	231	1		T81	21		T128	21		T112	8
wkup[11]	337	1		T16	26		T34	56		T178	30
wkup[12]	434	1		T35	29		T109	21		T87	21
wkup[13]	156	1		T13	30		T35	21		T37	21
wkup[14]	229	1		T25	15		T174	15		T168	30
wkup[15]	284	1		T34	30		T146	21		T147	21
wkup[16]	387	1		T1	21		T13	21		T80	24
wkup[17]	373	1		T33	21		T128	47		T99	21
wkup[18]	203	1		T6	15		T37	26		T127	21
wkup[19]	204	1		T133	21		T160	15		T83	15
wkup[20]	452	1		T10	21		T138	21		T119	21
wkup[21]	304	1		T26	21		T178	21		T144	30
wkup[22]	397	1		T24	15		T34	21		T35	21
wkup[23]	457	1		T1	21		T15	66		T16	21
wkup[24]	182	1		T33	21		T151	21		T38	21
wkup[25]	403	1		T138	15		T75	21		T76	21
wkup[26]	243	1		T126	15		T162	21		T130	29
wkup[27]	269	1		T23	15		T33	21		T188	15
wkup[28]	311	1		T26	15		T92	15		T34	47
wkup[29]	279	1		T13	21		T15	21		T34	21
wkup[30]	276	1		T1	21		T96	21		T148	21
wkup[31]	383	1		T42	21		T33	30		T34	21
wkup[32]	267	1		T26	21		T81	21		T173	21
wkup[33]	488	1		T138	21		T33	30		T34	21
wkup[34]	414	1		T15	42		T26	21		T33	21
wkup[35]	275	1		T162	21		T151	21		T112	30
wkup[36]	341	1		T1	21		T10	21		T26	21
wkup[37]	242	1		T13	21		T16	21		T147	21
wkup[38]	295	1		T4	15		T13	30		T33	21
wkup[39]	259	1		T1	21		T37	30		T76	51
wkup[40]	390	1		T87	21		T76	21		T177	21
wkup[41]	283	1		T15	21		T190	15		T109	21
wkup[42]	312	1		T10	21		T40	15		T26	21
wkup[43]	449	1		T34	21		T35	21		T81	21
wkup[44]	274	1		T3	15		T26	26		T135	21
wkup[45]	239	1		T33	21		T34	21		T35	8
wkup[46]	275	1		T13	21		T119	21		T112	21
wkup[47]	171	1		T5	15		T15	30		T155	21
wkup[48]	261	1		T33	39		T34	42		T162	21
wkup[49]	345	1		T15	30		T135	21		T108	15
wkup[50]	326	1		T13	15		T15	21		T43	15
wkup[51]	213	1		T16	21		T34	21		T38	21
wkup[52]	392	1		T1	21		T138	21		T155	21
wkup[53]	391	1		T33	21		T34	21		T119	26
wkup[54]	329	1		T16	26		T42	21		T178	21
wkup[55]	354	1		T16	39		T138	26		T33	42
wkup[56]	251	1		T13	42		T142	15		T119	30
wkup[57]	345	1		T20	21		T34	30		T81	21
wkup[58]	138	1		T13	21		T37	26		T118	26
wkup[59]	347	1		T16	21		T109	21		T37	21
wkup[60]	333	1		T34	21		T81	21		T159	26
wkup[61]	524	1		T155	21		T80	30		T34	21
wkup[62]	293	1		T13	26		T16	21		T146	21
wkup[63]	244	1		T15	30		T138	21		T143	15
wkup_0	3791	1		T1	5		T2	5		T3	5