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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.43 99.33 93.67 100.00 98.40 99.51 51.67


Total test records in report: 426
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T46 /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2226194137 Jun 26 06:50:04 PM PDT 24 Jun 26 06:58:16 PM PDT 24 86228329890 ps
T286 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3953833138 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:14 PM PDT 24 528131208 ps
T28 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3579907935 Jun 26 06:22:49 PM PDT 24 Jun 26 06:22:55 PM PDT 24 4689920935 ps
T29 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1215618339 Jun 26 06:23:04 PM PDT 24 Jun 26 06:23:07 PM PDT 24 516257945 ps
T287 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3640102529 Jun 26 06:22:59 PM PDT 24 Jun 26 06:23:04 PM PDT 24 370464976 ps
T288 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1251258167 Jun 26 06:23:11 PM PDT 24 Jun 26 06:23:12 PM PDT 24 390127210 ps
T289 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.503225838 Jun 26 06:23:06 PM PDT 24 Jun 26 06:23:11 PM PDT 24 364304452 ps
T30 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3022253136 Jun 26 06:23:09 PM PDT 24 Jun 26 06:23:11 PM PDT 24 552296882 ps
T290 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.290033843 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:15 PM PDT 24 607071157 ps
T31 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1498505459 Jun 26 06:22:59 PM PDT 24 Jun 26 06:23:05 PM PDT 24 4487552539 ps
T291 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.460370394 Jun 26 06:22:56 PM PDT 24 Jun 26 06:23:00 PM PDT 24 531696490 ps
T292 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.306996566 Jun 26 06:23:14 PM PDT 24 Jun 26 06:23:17 PM PDT 24 374044287 ps
T32 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4057345140 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:21 PM PDT 24 4439643358 ps
T293 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.899704020 Jun 26 06:23:02 PM PDT 24 Jun 26 06:23:06 PM PDT 24 539069287 ps
T294 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.589034467 Jun 26 06:23:11 PM PDT 24 Jun 26 06:23:12 PM PDT 24 417871216 ps
T202 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3087622157 Jun 26 06:22:56 PM PDT 24 Jun 26 06:23:00 PM PDT 24 505229607 ps
T295 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2771842414 Jun 26 06:23:13 PM PDT 24 Jun 26 06:23:16 PM PDT 24 271062583 ps
T296 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.415272300 Jun 26 06:23:15 PM PDT 24 Jun 26 06:23:18 PM PDT 24 473535728 ps
T297 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3631257584 Jun 26 06:22:56 PM PDT 24 Jun 26 06:23:00 PM PDT 24 488762389 ps
T47 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1130159385 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:02 PM PDT 24 518703158 ps
T298 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.521985666 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:15 PM PDT 24 410061494 ps
T299 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1471784694 Jun 26 06:22:55 PM PDT 24 Jun 26 06:22:59 PM PDT 24 359070792 ps
T191 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.819229961 Jun 26 06:23:01 PM PDT 24 Jun 26 06:23:05 PM PDT 24 5046406746 ps
T300 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1000682780 Jun 26 06:22:54 PM PDT 24 Jun 26 06:22:58 PM PDT 24 825560868 ps
T62 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3305792424 Jun 26 06:23:02 PM PDT 24 Jun 26 06:23:07 PM PDT 24 2783348716 ps
T301 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.328606482 Jun 26 06:23:00 PM PDT 24 Jun 26 06:23:03 PM PDT 24 338149740 ps
T48 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1971302767 Jun 26 06:23:01 PM PDT 24 Jun 26 06:23:04 PM PDT 24 559237302 ps
T49 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3174315995 Jun 26 06:23:03 PM PDT 24 Jun 26 06:23:07 PM PDT 24 427227661 ps
T302 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.117949637 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:09 PM PDT 24 498694944 ps
T63 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3473349400 Jun 26 06:23:15 PM PDT 24 Jun 26 06:23:21 PM PDT 24 2709379051 ps
T303 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.342613365 Jun 26 06:23:20 PM PDT 24 Jun 26 06:23:21 PM PDT 24 349401386 ps
T304 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1346516787 Jun 26 06:22:56 PM PDT 24 Jun 26 06:23:02 PM PDT 24 410597630 ps
T305 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3042581898 Jun 26 06:23:01 PM PDT 24 Jun 26 06:23:04 PM PDT 24 343703323 ps
T306 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1395396263 Jun 26 06:23:13 PM PDT 24 Jun 26 06:23:16 PM PDT 24 469167858 ps
T307 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2404237749 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:14 PM PDT 24 384966678 ps
T64 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2444172391 Jun 26 06:23:00 PM PDT 24 Jun 26 06:23:05 PM PDT 24 996884121 ps
T192 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.602065533 Jun 26 06:22:59 PM PDT 24 Jun 26 06:23:04 PM PDT 24 4575833982 ps
T308 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.842870147 Jun 26 06:22:54 PM PDT 24 Jun 26 06:22:58 PM PDT 24 1474679649 ps
T309 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2915831027 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:14 PM PDT 24 500721474 ps
T310 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2600621516 Jun 26 06:22:59 PM PDT 24 Jun 26 06:23:03 PM PDT 24 326230428 ps
T311 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1183086282 Jun 26 06:23:13 PM PDT 24 Jun 26 06:23:17 PM PDT 24 267170131 ps
T312 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1149085540 Jun 26 06:22:51 PM PDT 24 Jun 26 06:22:55 PM PDT 24 524224018 ps
T65 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1114677322 Jun 26 06:23:04 PM PDT 24 Jun 26 06:23:09 PM PDT 24 1393137428 ps
T313 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3874954529 Jun 26 06:22:55 PM PDT 24 Jun 26 06:22:59 PM PDT 24 293652761 ps
T314 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.719206411 Jun 26 06:23:10 PM PDT 24 Jun 26 06:23:12 PM PDT 24 375902570 ps
T315 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.807710235 Jun 26 06:22:55 PM PDT 24 Jun 26 06:22:59 PM PDT 24 465269526 ps
T316 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.522471698 Jun 26 06:23:00 PM PDT 24 Jun 26 06:23:07 PM PDT 24 7329234735 ps
T317 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2024741498 Jun 26 06:22:59 PM PDT 24 Jun 26 06:23:03 PM PDT 24 484441639 ps
T318 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2927178109 Jun 26 06:23:21 PM PDT 24 Jun 26 06:23:23 PM PDT 24 313500817 ps
T66 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3698364505 Jun 26 06:23:02 PM PDT 24 Jun 26 06:23:09 PM PDT 24 2547598851 ps
T319 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.326804284 Jun 26 06:23:04 PM PDT 24 Jun 26 06:23:08 PM PDT 24 338411197 ps
T320 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3834772356 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:15 PM PDT 24 461528765 ps
T321 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.810798812 Jun 26 06:22:55 PM PDT 24 Jun 26 06:23:10 PM PDT 24 8294594550 ps
T322 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4208284362 Jun 26 06:23:11 PM PDT 24 Jun 26 06:23:13 PM PDT 24 471563920 ps
T323 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3976950780 Jun 26 06:23:14 PM PDT 24 Jun 26 06:23:17 PM PDT 24 499443236 ps
T324 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3870106213 Jun 26 06:23:06 PM PDT 24 Jun 26 06:23:09 PM PDT 24 561140493 ps
T50 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.798974708 Jun 26 06:23:14 PM PDT 24 Jun 26 06:23:17 PM PDT 24 394155071 ps
T325 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1524806204 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:16 PM PDT 24 4648674196 ps
T326 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1951966857 Jun 26 06:23:10 PM PDT 24 Jun 26 06:23:13 PM PDT 24 1001401727 ps
T327 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.802856846 Jun 26 06:22:58 PM PDT 24 Jun 26 06:23:06 PM PDT 24 4129236263 ps
T328 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2483290683 Jun 26 06:23:14 PM PDT 24 Jun 26 06:23:17 PM PDT 24 343815134 ps
T329 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1789551456 Jun 26 06:22:49 PM PDT 24 Jun 26 06:22:52 PM PDT 24 610154793 ps
T51 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1745823009 Jun 26 06:22:53 PM PDT 24 Jun 26 06:23:04 PM PDT 24 10621154794 ps
T330 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.625177156 Jun 26 06:23:02 PM PDT 24 Jun 26 06:23:08 PM PDT 24 8718689796 ps
T331 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1183914548 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:02 PM PDT 24 434495214 ps
T332 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2489273654 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:09 PM PDT 24 359372192 ps
T333 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3647324013 Jun 26 06:23:13 PM PDT 24 Jun 26 06:23:15 PM PDT 24 315763058 ps
T67 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3312730544 Jun 26 06:22:49 PM PDT 24 Jun 26 06:22:53 PM PDT 24 1508935596 ps
T52 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3695069072 Jun 26 06:22:48 PM PDT 24 Jun 26 06:22:51 PM PDT 24 466501885 ps
T334 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.4169584940 Jun 26 06:23:08 PM PDT 24 Jun 26 06:23:17 PM PDT 24 4126005330 ps
T68 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3192217480 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:09 PM PDT 24 434678768 ps
T69 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2933923309 Jun 26 06:22:55 PM PDT 24 Jun 26 06:22:59 PM PDT 24 400369023 ps
T335 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3489083450 Jun 26 06:22:55 PM PDT 24 Jun 26 06:22:59 PM PDT 24 350548812 ps
T336 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1634019783 Jun 26 06:22:51 PM PDT 24 Jun 26 06:22:56 PM PDT 24 552458657 ps
T337 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1311713602 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:14 PM PDT 24 269158840 ps
T338 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.56447273 Jun 26 06:23:03 PM PDT 24 Jun 26 06:23:08 PM PDT 24 421814785 ps
T339 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4087003628 Jun 26 06:23:14 PM PDT 24 Jun 26 06:23:17 PM PDT 24 576832634 ps
T55 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.700237287 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:09 PM PDT 24 482457062 ps
T340 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.577952555 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:10 PM PDT 24 2417412422 ps
T341 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2952127983 Jun 26 06:23:13 PM PDT 24 Jun 26 06:23:16 PM PDT 24 559596937 ps
T342 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2148618787 Jun 26 06:23:22 PM PDT 24 Jun 26 06:23:23 PM PDT 24 412734821 ps
T343 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.11056921 Jun 26 06:23:18 PM PDT 24 Jun 26 06:23:20 PM PDT 24 498280016 ps
T344 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3659548179 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:09 PM PDT 24 1814192009 ps
T345 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3365181749 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:02 PM PDT 24 381127409 ps
T346 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2345145635 Jun 26 06:23:03 PM PDT 24 Jun 26 06:23:07 PM PDT 24 528988634 ps
T347 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3816992784 Jun 26 06:23:17 PM PDT 24 Jun 26 06:23:19 PM PDT 24 391870849 ps
T348 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1006077105 Jun 26 06:22:56 PM PDT 24 Jun 26 06:23:00 PM PDT 24 1315732015 ps
T349 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2757323160 Jun 26 06:22:56 PM PDT 24 Jun 26 06:23:01 PM PDT 24 1038029562 ps
T350 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.778248396 Jun 26 06:23:01 PM PDT 24 Jun 26 06:23:17 PM PDT 24 8630754604 ps
T351 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1342044286 Jun 26 06:22:55 PM PDT 24 Jun 26 06:23:00 PM PDT 24 511832463 ps
T352 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4171971977 Jun 26 06:23:06 PM PDT 24 Jun 26 06:23:09 PM PDT 24 287221301 ps
T353 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.970184361 Jun 26 06:23:04 PM PDT 24 Jun 26 06:23:08 PM PDT 24 1495089108 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1236338944 Jun 26 06:22:56 PM PDT 24 Jun 26 06:23:01 PM PDT 24 1161977447 ps
T355 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4070351192 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:01 PM PDT 24 330842354 ps
T53 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1630977286 Jun 26 06:22:56 PM PDT 24 Jun 26 06:23:00 PM PDT 24 433767482 ps
T356 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.439550127 Jun 26 06:23:02 PM PDT 24 Jun 26 06:23:05 PM PDT 24 367499778 ps
T357 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2690395494 Jun 26 06:23:04 PM PDT 24 Jun 26 06:23:08 PM PDT 24 358369443 ps
T358 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3716753869 Jun 26 06:23:15 PM PDT 24 Jun 26 06:23:18 PM PDT 24 277253579 ps
T359 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2385407394 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:16 PM PDT 24 437439191 ps
T360 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.40468201 Jun 26 06:23:19 PM PDT 24 Jun 26 06:23:21 PM PDT 24 357249015 ps
T361 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3197946745 Jun 26 06:23:09 PM PDT 24 Jun 26 06:23:11 PM PDT 24 388716913 ps
T362 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1474680951 Jun 26 06:22:51 PM PDT 24 Jun 26 06:22:54 PM PDT 24 450675788 ps
T363 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.29592891 Jun 26 06:23:00 PM PDT 24 Jun 26 06:23:11 PM PDT 24 2883510185 ps
T56 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.313984799 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:01 PM PDT 24 448881851 ps
T364 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2675949913 Jun 26 06:22:49 PM PDT 24 Jun 26 06:22:53 PM PDT 24 410209795 ps
T365 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3073943843 Jun 26 06:23:02 PM PDT 24 Jun 26 06:23:06 PM PDT 24 863100963 ps
T366 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1598504773 Jun 26 06:22:55 PM PDT 24 Jun 26 06:23:00 PM PDT 24 2848423189 ps
T193 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1410471575 Jun 26 06:23:11 PM PDT 24 Jun 26 06:23:14 PM PDT 24 4723265854 ps
T367 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2270345577 Jun 26 06:23:13 PM PDT 24 Jun 26 06:23:18 PM PDT 24 1864927645 ps
T368 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2379846851 Jun 26 06:23:07 PM PDT 24 Jun 26 06:23:11 PM PDT 24 4790239639 ps
T369 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3750351711 Jun 26 06:23:06 PM PDT 24 Jun 26 06:23:10 PM PDT 24 342856434 ps
T370 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.240949129 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:09 PM PDT 24 928888232 ps
T57 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.444215154 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:08 PM PDT 24 7475507410 ps
T194 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.69592501 Jun 26 06:23:04 PM PDT 24 Jun 26 06:23:21 PM PDT 24 8853397642 ps
T371 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.843405148 Jun 26 06:23:01 PM PDT 24 Jun 26 06:23:04 PM PDT 24 453503741 ps
T372 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1134874896 Jun 26 06:23:03 PM PDT 24 Jun 26 06:23:07 PM PDT 24 573766702 ps
T373 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3736709250 Jun 26 06:22:58 PM PDT 24 Jun 26 06:23:04 PM PDT 24 492939780 ps
T374 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1239072640 Jun 26 06:22:51 PM PDT 24 Jun 26 06:22:55 PM PDT 24 337006129 ps
T375 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1853787654 Jun 26 06:22:58 PM PDT 24 Jun 26 06:23:02 PM PDT 24 417229072 ps
T376 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2294381396 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:02 PM PDT 24 7747413551 ps
T58 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1391142788 Jun 26 06:23:00 PM PDT 24 Jun 26 06:23:03 PM PDT 24 539823103 ps
T377 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2063580836 Jun 26 06:23:01 PM PDT 24 Jun 26 06:23:06 PM PDT 24 2062905946 ps
T378 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2424461127 Jun 26 06:22:50 PM PDT 24 Jun 26 06:22:54 PM PDT 24 1439996746 ps
T379 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1457617336 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:03 PM PDT 24 471349040 ps
T380 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.706193772 Jun 26 06:23:21 PM PDT 24 Jun 26 06:23:23 PM PDT 24 461842271 ps
T381 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.322830959 Jun 26 06:23:11 PM PDT 24 Jun 26 06:23:14 PM PDT 24 708225870 ps
T382 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2846449996 Jun 26 06:23:11 PM PDT 24 Jun 26 06:23:15 PM PDT 24 2050466499 ps
T59 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2050959369 Jun 26 06:22:59 PM PDT 24 Jun 26 06:23:16 PM PDT 24 6212741450 ps
T383 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3432803880 Jun 26 06:23:20 PM PDT 24 Jun 26 06:23:22 PM PDT 24 510543040 ps
T384 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3679957106 Jun 26 06:23:03 PM PDT 24 Jun 26 06:23:09 PM PDT 24 2831288793 ps
T385 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.426789723 Jun 26 06:22:54 PM PDT 24 Jun 26 06:22:58 PM PDT 24 393478188 ps
T386 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1405563103 Jun 26 06:23:15 PM PDT 24 Jun 26 06:23:17 PM PDT 24 520044857 ps
T387 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.904699474 Jun 26 06:23:04 PM PDT 24 Jun 26 06:23:08 PM PDT 24 616783626 ps
T60 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.302527752 Jun 26 06:23:15 PM PDT 24 Jun 26 06:23:17 PM PDT 24 530122829 ps
T388 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3453655290 Jun 26 06:23:07 PM PDT 24 Jun 26 06:23:17 PM PDT 24 8412090323 ps
T389 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4209743004 Jun 26 06:23:03 PM PDT 24 Jun 26 06:23:07 PM PDT 24 801988860 ps
T390 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3705909653 Jun 26 06:23:13 PM PDT 24 Jun 26 06:23:18 PM PDT 24 1462012049 ps
T391 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3828931712 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:08 PM PDT 24 390228303 ps
T392 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1125137145 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:10 PM PDT 24 719581557 ps
T61 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.764145556 Jun 26 06:23:14 PM PDT 24 Jun 26 06:23:17 PM PDT 24 462371315 ps
T393 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.950724872 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:10 PM PDT 24 434836031 ps
T394 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2296876904 Jun 26 06:22:54 PM PDT 24 Jun 26 06:22:58 PM PDT 24 331342859 ps
T395 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1821376997 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:02 PM PDT 24 509924966 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.420466772 Jun 26 06:22:56 PM PDT 24 Jun 26 06:23:00 PM PDT 24 568277265 ps
T396 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2460188348 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:14 PM PDT 24 325531932 ps
T397 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2760959563 Jun 26 06:23:00 PM PDT 24 Jun 26 06:23:04 PM PDT 24 668117885 ps
T398 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2620600187 Jun 26 06:22:56 PM PDT 24 Jun 26 06:23:00 PM PDT 24 427713630 ps
T399 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2486191069 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:01 PM PDT 24 526364763 ps
T400 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.305346074 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:15 PM PDT 24 458558551 ps
T401 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2381698574 Jun 26 06:22:56 PM PDT 24 Jun 26 06:23:01 PM PDT 24 457250254 ps
T402 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1240804547 Jun 26 06:23:03 PM PDT 24 Jun 26 06:23:07 PM PDT 24 614282772 ps
T403 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.842943175 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:14 PM PDT 24 578784549 ps
T404 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3063043098 Jun 26 06:23:13 PM PDT 24 Jun 26 06:23:16 PM PDT 24 464495623 ps
T405 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1568017934 Jun 26 06:22:48 PM PDT 24 Jun 26 06:22:52 PM PDT 24 908251663 ps
T406 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2038092517 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:02 PM PDT 24 857227256 ps
T407 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1939478611 Jun 26 06:22:54 PM PDT 24 Jun 26 06:22:58 PM PDT 24 379641906 ps
T408 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3623896672 Jun 26 06:23:11 PM PDT 24 Jun 26 06:23:19 PM PDT 24 8191408669 ps
T195 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3162693774 Jun 26 06:22:55 PM PDT 24 Jun 26 06:23:11 PM PDT 24 8235179501 ps
T409 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3725380227 Jun 26 06:22:54 PM PDT 24 Jun 26 06:23:06 PM PDT 24 4898353666 ps
T410 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.385548013 Jun 26 06:23:13 PM PDT 24 Jun 26 06:23:16 PM PDT 24 300750708 ps
T411 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1693162888 Jun 26 06:22:54 PM PDT 24 Jun 26 06:22:59 PM PDT 24 2363513818 ps
T412 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2852108603 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:15 PM PDT 24 454683046 ps
T413 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1732683606 Jun 26 06:22:51 PM PDT 24 Jun 26 06:22:54 PM PDT 24 520763080 ps
T414 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.179347124 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:01 PM PDT 24 5255127372 ps
T415 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.686432084 Jun 26 06:23:12 PM PDT 24 Jun 26 06:23:15 PM PDT 24 521191343 ps
T416 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.325042504 Jun 26 06:23:07 PM PDT 24 Jun 26 06:23:10 PM PDT 24 416231599 ps
T417 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3489709403 Jun 26 06:22:51 PM PDT 24 Jun 26 06:22:55 PM PDT 24 486982154 ps
T418 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1011489817 Jun 26 06:22:48 PM PDT 24 Jun 26 06:22:52 PM PDT 24 665707995 ps
T419 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3047791692 Jun 26 06:22:56 PM PDT 24 Jun 26 06:23:01 PM PDT 24 2706639013 ps
T420 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3897126659 Jun 26 06:22:54 PM PDT 24 Jun 26 06:22:58 PM PDT 24 377997780 ps
T421 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.578751534 Jun 26 06:22:57 PM PDT 24 Jun 26 06:23:02 PM PDT 24 585045150 ps
T422 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.676508304 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:09 PM PDT 24 499447292 ps
T423 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4012971234 Jun 26 06:23:03 PM PDT 24 Jun 26 06:23:18 PM PDT 24 8736211217 ps
T424 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.652479409 Jun 26 06:23:00 PM PDT 24 Jun 26 06:23:04 PM PDT 24 386983988 ps
T425 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2623278880 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:09 PM PDT 24 583155281 ps
T426 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2035035348 Jun 26 06:23:05 PM PDT 24 Jun 26 06:23:11 PM PDT 24 609169561 ps

Test location /workspace/coverage/default/21.aon_timer_stress_all.3562686782
Short name T10
Test name
Test status
Simulation time 77091746821 ps
CPU time 61.51 seconds
Started Jun 26 06:50:04 PM PDT 24
Finished Jun 26 06:51:07 PM PDT 24
Peak memory 198088 kb
Host smart-0cdab603-871e-45e3-910f-0b490a57ce3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562686782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3562686782
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1266322763
Short name T15
Test name
Test status
Simulation time 70506304807 ps
CPU time 87.22 seconds
Started Jun 26 06:49:42 PM PDT 24
Finished Jun 26 06:51:11 PM PDT 24
Peak memory 214040 kb
Host smart-e86016eb-79b1-403f-9b6e-bedd695383c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266322763 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1266322763
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4057345140
Short name T32
Test name
Test status
Simulation time 4439643358 ps
CPU time 7.27 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:21 PM PDT 24
Peak memory 196472 kb
Host smart-82a0deed-bb6b-4710-b986-4dbd2daa9666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057345140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.4057345140
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.48696124
Short name T34
Test name
Test status
Simulation time 69622792287 ps
CPU time 426.9 seconds
Started Jun 26 06:51:01 PM PDT 24
Finished Jun 26 06:58:09 PM PDT 24
Peak memory 200692 kb
Host smart-01ebc38d-c5ba-4d8f-add8-c30e2d29698e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48696124 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.48696124
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1463526510
Short name T100
Test name
Test status
Simulation time 108604738832 ps
CPU time 412.92 seconds
Started Jun 26 06:49:41 PM PDT 24
Finished Jun 26 06:56:35 PM PDT 24
Peak memory 214812 kb
Host smart-bee43d33-e267-4d84-bcd0-ed07507c4390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463526510 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1463526510
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.799823413
Short name T167
Test name
Test status
Simulation time 93511716378 ps
CPU time 187.14 seconds
Started Jun 26 06:50:15 PM PDT 24
Finished Jun 26 06:53:23 PM PDT 24
Peak memory 199860 kb
Host smart-1e5fe9d6-f32d-4846-87d2-0f28063ce21f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799823413 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.799823413
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1440472622
Short name T93
Test name
Test status
Simulation time 423689385327 ps
CPU time 559.18 seconds
Started Jun 26 06:49:27 PM PDT 24
Finished Jun 26 06:58:48 PM PDT 24
Peak memory 204456 kb
Host smart-b273c957-30ad-42a5-b953-ad80b3286c19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440472622 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1440472622
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.4089707742
Short name T76
Test name
Test status
Simulation time 301543120218 ps
CPU time 1122.48 seconds
Started Jun 26 06:50:44 PM PDT 24
Finished Jun 26 07:09:29 PM PDT 24
Peak memory 212492 kb
Host smart-421d8225-7d12-4329-ae93-22f9c4f98e9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089707742 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.4089707742
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3900762222
Short name T122
Test name
Test status
Simulation time 400624495950 ps
CPU time 1068 seconds
Started Jun 26 06:49:30 PM PDT 24
Finished Jun 26 07:07:19 PM PDT 24
Peak memory 211700 kb
Host smart-c11feed1-7b0c-41c7-b4cd-df8c6d4ac1f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900762222 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3900762222
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3625586866
Short name T117
Test name
Test status
Simulation time 16415733636 ps
CPU time 134.31 seconds
Started Jun 26 06:48:49 PM PDT 24
Finished Jun 26 06:51:05 PM PDT 24
Peak memory 198440 kb
Host smart-6a7ad3e8-684a-4a50-9bde-b2738b072543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625586866 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3625586866
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1489407918
Short name T83
Test name
Test status
Simulation time 157679640515 ps
CPU time 223.75 seconds
Started Jun 26 06:49:32 PM PDT 24
Finished Jun 26 06:53:17 PM PDT 24
Peak memory 192844 kb
Host smart-43c0d03c-4cb4-4d37-a431-b3113399b9c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489407918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1489407918
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1807389086
Short name T79
Test name
Test status
Simulation time 157252214588 ps
CPU time 573.13 seconds
Started Jun 26 06:48:34 PM PDT 24
Finished Jun 26 06:58:08 PM PDT 24
Peak memory 212552 kb
Host smart-da4c2703-ff28-432e-83df-5b82027cbb17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807389086 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1807389086
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2521065379
Short name T73
Test name
Test status
Simulation time 270418043458 ps
CPU time 349.1 seconds
Started Jun 26 06:49:16 PM PDT 24
Finished Jun 26 06:55:07 PM PDT 24
Peak memory 209788 kb
Host smart-2ead6047-150a-4e48-b813-70cbd0678ae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521065379 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2521065379
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2226194137
Short name T46
Test name
Test status
Simulation time 86228329890 ps
CPU time 490.08 seconds
Started Jun 26 06:50:04 PM PDT 24
Finished Jun 26 06:58:16 PM PDT 24
Peak memory 212152 kb
Host smart-f07e9193-6188-47f8-9dd3-b2756756907b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226194137 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2226194137
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.653088493
Short name T91
Test name
Test status
Simulation time 159500405220 ps
CPU time 340.19 seconds
Started Jun 26 06:50:31 PM PDT 24
Finished Jun 26 06:56:14 PM PDT 24
Peak memory 201736 kb
Host smart-6e7fe61b-edf9-4c6c-9c39-616810482fc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653088493 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.653088493
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1002411287
Short name T21
Test name
Test status
Simulation time 8355131532 ps
CPU time 2.51 seconds
Started Jun 26 06:48:34 PM PDT 24
Finished Jun 26 06:48:38 PM PDT 24
Peak memory 215860 kb
Host smart-b99125e3-aa9d-4892-b6ab-0d2f1cf52446
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002411287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1002411287
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3684634765
Short name T95
Test name
Test status
Simulation time 315232425612 ps
CPU time 741.66 seconds
Started Jun 26 06:50:29 PM PDT 24
Finished Jun 26 07:02:52 PM PDT 24
Peak memory 214772 kb
Host smart-ed65bd95-65c6-4c8b-b9f3-33918618013c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684634765 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3684634765
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1137192018
Short name T1
Test name
Test status
Simulation time 93526626381 ps
CPU time 22.42 seconds
Started Jun 26 06:49:04 PM PDT 24
Finished Jun 26 06:49:28 PM PDT 24
Peak memory 192340 kb
Host smart-154d92d1-f851-4766-84e7-aa723070dab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137192018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1137192018
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.71510877
Short name T84
Test name
Test status
Simulation time 32398470812 ps
CPU time 349 seconds
Started Jun 26 06:51:02 PM PDT 24
Finished Jun 26 06:56:53 PM PDT 24
Peak memory 198772 kb
Host smart-f43a010a-e2ca-4577-a10b-e462b01c127b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71510877 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.71510877
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1138782993
Short name T112
Test name
Test status
Simulation time 112506131150 ps
CPU time 337.12 seconds
Started Jun 26 06:51:24 PM PDT 24
Finished Jun 26 06:57:03 PM PDT 24
Peak memory 206636 kb
Host smart-55510ddd-61f6-4cef-9803-fdaaf7811d41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138782993 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1138782993
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1404996961
Short name T110
Test name
Test status
Simulation time 130618440378 ps
CPU time 36 seconds
Started Jun 26 06:51:25 PM PDT 24
Finished Jun 26 06:52:03 PM PDT 24
Peak memory 191720 kb
Host smart-a442f5de-3d52-4872-9b4c-10ebc585c704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404996961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1404996961
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.4157945834
Short name T90
Test name
Test status
Simulation time 658475509141 ps
CPU time 862.89 seconds
Started Jun 26 06:50:02 PM PDT 24
Finished Jun 26 07:04:26 PM PDT 24
Peak memory 208176 kb
Host smart-e6fcbd88-4286-404c-9600-fd5b7d73a822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157945834 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.4157945834
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1719825300
Short name T105
Test name
Test status
Simulation time 82567332617 ps
CPU time 668.64 seconds
Started Jun 26 06:51:26 PM PDT 24
Finished Jun 26 07:02:37 PM PDT 24
Peak memory 213636 kb
Host smart-2aa05563-be23-4c86-8df0-91f343bc4db6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719825300 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1719825300
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2823553993
Short name T99
Test name
Test status
Simulation time 63176291081 ps
CPU time 90.65 seconds
Started Jun 26 06:50:43 PM PDT 24
Finished Jun 26 06:52:16 PM PDT 24
Peak memory 191712 kb
Host smart-daf7deb7-d9e8-4379-bc8b-fb4552bda660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823553993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2823553993
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2011097360
Short name T33
Test name
Test status
Simulation time 197060516013 ps
CPU time 535.87 seconds
Started Jun 26 06:50:04 PM PDT 24
Finished Jun 26 06:59:01 PM PDT 24
Peak memory 213072 kb
Host smart-1a9ce1b3-032b-4d9c-aa42-44309720eb86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011097360 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2011097360
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.4255609235
Short name T82
Test name
Test status
Simulation time 229414200002 ps
CPU time 81.42 seconds
Started Jun 26 06:50:19 PM PDT 24
Finished Jun 26 06:51:42 PM PDT 24
Peak memory 198108 kb
Host smart-604560fd-e6f8-4ed7-911e-9d4ca81a089b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255609235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.4255609235
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2476019011
Short name T134
Test name
Test status
Simulation time 271143497327 ps
CPU time 168.47 seconds
Started Jun 26 06:50:03 PM PDT 24
Finished Jun 26 06:52:53 PM PDT 24
Peak memory 198104 kb
Host smart-3cbc838f-5c4c-4179-905e-c1b8a657dbc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476019011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2476019011
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3723055226
Short name T87
Test name
Test status
Simulation time 137841076537 ps
CPU time 87.05 seconds
Started Jun 26 06:50:17 PM PDT 24
Finished Jun 26 06:51:46 PM PDT 24
Peak memory 198284 kb
Host smart-6448a4bd-9d0f-42e1-8ce7-b1eb74c13753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723055226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3723055226
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.4119455355
Short name T123
Test name
Test status
Simulation time 432644014039 ps
CPU time 533.18 seconds
Started Jun 26 06:49:59 PM PDT 24
Finished Jun 26 06:58:53 PM PDT 24
Peak memory 204156 kb
Host smart-85e6e028-ff80-4542-8ab5-5de3a46e55e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119455355 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.4119455355
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.4162430543
Short name T125
Test name
Test status
Simulation time 18009572673 ps
CPU time 6.36 seconds
Started Jun 26 06:48:34 PM PDT 24
Finished Jun 26 06:48:42 PM PDT 24
Peak memory 192752 kb
Host smart-e726ffd5-532f-4bad-b6cb-71ac5322fdfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162430543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.4162430543
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3342707083
Short name T128
Test name
Test status
Simulation time 110886294858 ps
CPU time 174.72 seconds
Started Jun 26 06:49:41 PM PDT 24
Finished Jun 26 06:52:36 PM PDT 24
Peak memory 191716 kb
Host smart-761ed9bf-d094-4af8-8a37-53ee99e3de91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342707083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3342707083
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1545887043
Short name T72
Test name
Test status
Simulation time 41598094292 ps
CPU time 319.7 seconds
Started Jun 26 06:51:24 PM PDT 24
Finished Jun 26 06:56:46 PM PDT 24
Peak memory 198668 kb
Host smart-faa54f2a-82b5-47b1-9f48-d00d77ef15ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545887043 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1545887043
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.218831358
Short name T109
Test name
Test status
Simulation time 166502705870 ps
CPU time 109.22 seconds
Started Jun 26 06:51:25 PM PDT 24
Finished Jun 26 06:53:16 PM PDT 24
Peak memory 192812 kb
Host smart-a2c03958-36cf-41a1-bded-07eabc9b4bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218831358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.218831358
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.253815074
Short name T104
Test name
Test status
Simulation time 233365511786 ps
CPU time 52.68 seconds
Started Jun 26 06:49:31 PM PDT 24
Finished Jun 26 06:50:25 PM PDT 24
Peak memory 192328 kb
Host smart-06992c5e-17f2-4744-9fb3-77f7bb6d65dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253815074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.253815074
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1770657568
Short name T85
Test name
Test status
Simulation time 64639335207 ps
CPU time 26.73 seconds
Started Jun 26 06:50:03 PM PDT 24
Finished Jun 26 06:50:31 PM PDT 24
Peak memory 192812 kb
Host smart-026eff70-0916-4e6d-b81b-eace02fadb34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770657568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1770657568
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.259954849
Short name T120
Test name
Test status
Simulation time 120965095923 ps
CPU time 98.76 seconds
Started Jun 26 06:50:17 PM PDT 24
Finished Jun 26 06:51:58 PM PDT 24
Peak memory 191712 kb
Host smart-67f935d5-235f-490f-b783-c69513e24710
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259954849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.259954849
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3974648255
Short name T138
Test name
Test status
Simulation time 45066904713 ps
CPU time 7.4 seconds
Started Jun 26 06:49:40 PM PDT 24
Finished Jun 26 06:49:48 PM PDT 24
Peak memory 191700 kb
Host smart-4a125b02-877f-47f9-b2e6-2c7b5a6aee34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974648255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3974648255
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2847552212
Short name T13
Test name
Test status
Simulation time 78635047779 ps
CPU time 569.43 seconds
Started Jun 26 06:50:05 PM PDT 24
Finished Jun 26 06:59:36 PM PDT 24
Peak memory 213844 kb
Host smart-f7fc698c-0279-45f9-baba-652b6f147d33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847552212 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2847552212
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2131129969
Short name T26
Test name
Test status
Simulation time 50861061923 ps
CPU time 271.52 seconds
Started Jun 26 06:49:53 PM PDT 24
Finished Jun 26 06:54:26 PM PDT 24
Peak memory 206628 kb
Host smart-3373a4a0-15f5-4303-b76e-09c6784ea996
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131129969 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2131129969
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.735291817
Short name T81
Test name
Test status
Simulation time 106649757232 ps
CPU time 165.35 seconds
Started Jun 26 06:51:03 PM PDT 24
Finished Jun 26 06:53:50 PM PDT 24
Peak memory 184188 kb
Host smart-c7404586-81ac-43d9-be51-efecb768ed5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735291817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.735291817
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.782674990
Short name T148
Test name
Test status
Simulation time 56111993510 ps
CPU time 321.87 seconds
Started Jun 26 06:50:32 PM PDT 24
Finished Jun 26 06:55:57 PM PDT 24
Peak memory 213772 kb
Host smart-0c714e80-a1ee-4678-b634-caeba54fa365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782674990 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.782674990
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3053870896
Short name T101
Test name
Test status
Simulation time 81425336343 ps
CPU time 627.5 seconds
Started Jun 26 06:49:16 PM PDT 24
Finished Jun 26 06:59:44 PM PDT 24
Peak memory 214840 kb
Host smart-700356bf-d5d7-4f51-8765-9c76d42cd42d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053870896 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3053870896
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3277432279
Short name T119
Test name
Test status
Simulation time 257049656820 ps
CPU time 163.26 seconds
Started Jun 26 06:50:30 PM PDT 24
Finished Jun 26 06:53:15 PM PDT 24
Peak memory 192248 kb
Host smart-85460cf8-736f-4d3f-ab57-d71676f3d9f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277432279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3277432279
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1324754902
Short name T35
Test name
Test status
Simulation time 78179326730 ps
CPU time 549.02 seconds
Started Jun 26 06:51:03 PM PDT 24
Finished Jun 26 07:00:14 PM PDT 24
Peak memory 211828 kb
Host smart-e33510dc-eab8-4dab-a599-bedc0708ce65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324754902 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1324754902
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2398892957
Short name T118
Test name
Test status
Simulation time 209565183914 ps
CPU time 294.89 seconds
Started Jun 26 06:51:01 PM PDT 24
Finished Jun 26 06:55:58 PM PDT 24
Peak memory 191992 kb
Host smart-c3010746-a36b-4b6b-ac45-4d4570be2d99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398892957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2398892957
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.4202680403
Short name T106
Test name
Test status
Simulation time 60160788516 ps
CPU time 28.06 seconds
Started Jun 26 06:49:17 PM PDT 24
Finished Jun 26 06:49:46 PM PDT 24
Peak memory 192784 kb
Host smart-6b918ece-a0ab-4a01-a556-b6a4b4cb03ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202680403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.4202680403
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.476590963
Short name T140
Test name
Test status
Simulation time 103031106181 ps
CPU time 157.36 seconds
Started Jun 26 06:49:54 PM PDT 24
Finished Jun 26 06:52:33 PM PDT 24
Peak memory 198076 kb
Host smart-ead52e9e-88db-4e53-8d62-285869132670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476590963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.476590963
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3237460467
Short name T75
Test name
Test status
Simulation time 122973852242 ps
CPU time 234.69 seconds
Started Jun 26 06:50:17 PM PDT 24
Finished Jun 26 06:54:14 PM PDT 24
Peak memory 206660 kb
Host smart-d7effe0c-83b1-437d-870a-4fc2c166baf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237460467 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3237460467
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3649801789
Short name T151
Test name
Test status
Simulation time 221470001402 ps
CPU time 286.56 seconds
Started Jun 26 06:48:51 PM PDT 24
Finished Jun 26 06:53:39 PM PDT 24
Peak memory 198080 kb
Host smart-6ea65be7-29c1-4800-9b94-5949bec79721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649801789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3649801789
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.702142757
Short name T38
Test name
Test status
Simulation time 22888689708 ps
CPU time 233.16 seconds
Started Jun 26 06:49:05 PM PDT 24
Finished Jun 26 06:52:59 PM PDT 24
Peak memory 206664 kb
Host smart-658781af-5812-46b4-925e-9088caae1f83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702142757 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.702142757
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1745823009
Short name T51
Test name
Test status
Simulation time 10621154794 ps
CPU time 7.94 seconds
Started Jun 26 06:22:53 PM PDT 24
Finished Jun 26 06:23:04 PM PDT 24
Peak memory 192224 kb
Host smart-72181fec-9b68-4d9e-9dd5-6912b64c9867
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745823009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1745823009
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2194816405
Short name T127
Test name
Test status
Simulation time 50723065485 ps
CPU time 164.88 seconds
Started Jun 26 06:49:42 PM PDT 24
Finished Jun 26 06:52:28 PM PDT 24
Peak memory 206692 kb
Host smart-ed3005dc-b138-408c-8c41-62e33d3650e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194816405 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2194816405
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2903064090
Short name T137
Test name
Test status
Simulation time 128418962038 ps
CPU time 48.23 seconds
Started Jun 26 06:50:05 PM PDT 24
Finished Jun 26 06:50:54 PM PDT 24
Peak memory 191740 kb
Host smart-2b80767e-9333-467c-97f9-b87e41ae4ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903064090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2903064090
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3312730544
Short name T67
Test name
Test status
Simulation time 1508935596 ps
CPU time 1.42 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:53 PM PDT 24
Peak memory 183808 kb
Host smart-dadded78-c43d-44be-af1f-64cc45601e8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312730544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3312730544
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3418413106
Short name T141
Test name
Test status
Simulation time 180999352480 ps
CPU time 54.37 seconds
Started Jun 26 06:49:28 PM PDT 24
Finished Jun 26 06:50:23 PM PDT 24
Peak memory 198052 kb
Host smart-ca71f25d-b4e0-4e07-9fae-1d7d40663cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418413106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3418413106
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.291111255
Short name T94
Test name
Test status
Simulation time 33888209143 ps
CPU time 47.87 seconds
Started Jun 26 06:48:51 PM PDT 24
Finished Jun 26 06:49:41 PM PDT 24
Peak memory 198048 kb
Host smart-fc11975c-d666-40cd-886f-7e153383b9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291111255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.291111255
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1803108744
Short name T161
Test name
Test status
Simulation time 16277202129 ps
CPU time 175.35 seconds
Started Jun 26 06:50:04 PM PDT 24
Finished Jun 26 06:53:01 PM PDT 24
Peak memory 206864 kb
Host smart-1cfcc1f6-c0be-4ba1-a01b-2399eeac4b88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803108744 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1803108744
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2613540309
Short name T159
Test name
Test status
Simulation time 10281552403 ps
CPU time 4.23 seconds
Started Jun 26 06:50:15 PM PDT 24
Finished Jun 26 06:50:20 PM PDT 24
Peak memory 198092 kb
Host smart-e0552a4e-9218-4daf-8a52-083bac2f29b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613540309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2613540309
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2404807355
Short name T133
Test name
Test status
Simulation time 52161359208 ps
CPU time 17.79 seconds
Started Jun 26 06:49:04 PM PDT 24
Finished Jun 26 06:49:23 PM PDT 24
Peak memory 191720 kb
Host smart-8205538d-67a8-4b2c-aa03-ae2fc28f9255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404807355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2404807355
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1740910126
Short name T124
Test name
Test status
Simulation time 228341945653 ps
CPU time 466.4 seconds
Started Jun 26 06:50:46 PM PDT 24
Finished Jun 26 06:58:34 PM PDT 24
Peak memory 211848 kb
Host smart-4a127034-41bd-4310-b6ed-a683fcd65960
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740910126 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1740910126
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2645742997
Short name T111
Test name
Test status
Simulation time 28968205240 ps
CPU time 134.73 seconds
Started Jun 26 06:51:24 PM PDT 24
Finished Jun 26 06:53:41 PM PDT 24
Peak memory 206844 kb
Host smart-b645cb48-740e-4cc0-b98c-1f999ba37a4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645742997 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2645742997
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.792241094
Short name T89
Test name
Test status
Simulation time 84856445189 ps
CPU time 125.94 seconds
Started Jun 26 06:50:44 PM PDT 24
Finished Jun 26 06:52:52 PM PDT 24
Peak memory 184392 kb
Host smart-4929a721-d9b2-4192-8ef5-935579bbb0b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792241094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.792241094
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.306761619
Short name T37
Test name
Test status
Simulation time 226483525261 ps
CPU time 417.23 seconds
Started Jun 26 06:50:47 PM PDT 24
Finished Jun 26 06:57:45 PM PDT 24
Peak memory 213932 kb
Host smart-4397e604-3642-4fd7-8b17-4a0bf719849c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306761619 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.306761619
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.747673954
Short name T80
Test name
Test status
Simulation time 73664277338 ps
CPU time 29.52 seconds
Started Jun 26 06:51:05 PM PDT 24
Finished Jun 26 06:51:36 PM PDT 24
Peak memory 184248 kb
Host smart-eade3a0c-2dc6-4e49-ad15-ca13424d9b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747673954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.747673954
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.4159228393
Short name T107
Test name
Test status
Simulation time 390945474 ps
CPU time 0.74 seconds
Started Jun 26 06:49:29 PM PDT 24
Finished Jun 26 06:49:31 PM PDT 24
Peak memory 196468 kb
Host smart-e7989679-d704-4d73-aa2e-75651db7db1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159228393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4159228393
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.167841272
Short name T155
Test name
Test status
Simulation time 196956765136 ps
CPU time 24.51 seconds
Started Jun 26 06:51:02 PM PDT 24
Finished Jun 26 06:51:28 PM PDT 24
Peak memory 191732 kb
Host smart-478b766c-0921-4e35-b248-231ff35bbbc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167841272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.167841272
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3408388295
Short name T135
Test name
Test status
Simulation time 186556903905 ps
CPU time 227.33 seconds
Started Jun 26 06:48:35 PM PDT 24
Finished Jun 26 06:52:24 PM PDT 24
Peak memory 192812 kb
Host smart-c58879b0-e2a3-4423-8a1b-41d4c23dd28e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408388295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3408388295
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.4063497381
Short name T45
Test name
Test status
Simulation time 114455127409 ps
CPU time 406.46 seconds
Started Jun 26 06:49:50 PM PDT 24
Finished Jun 26 06:56:37 PM PDT 24
Peak memory 209084 kb
Host smart-f334a5a3-bb8a-4e71-ac7f-e0e22d95a444
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063497381 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.4063497381
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1143633216
Short name T97
Test name
Test status
Simulation time 437549355 ps
CPU time 0.78 seconds
Started Jun 26 06:50:05 PM PDT 24
Finished Jun 26 06:50:07 PM PDT 24
Peak memory 196476 kb
Host smart-f8908b2e-c062-46a8-8836-c91a09e22ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143633216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1143633216
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3164255886
Short name T98
Test name
Test status
Simulation time 358594812 ps
CPU time 0.88 seconds
Started Jun 26 06:48:50 PM PDT 24
Finished Jun 26 06:48:52 PM PDT 24
Peak memory 196532 kb
Host smart-f94684bd-8d34-4953-b39b-6d26f685beb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164255886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3164255886
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3130681601
Short name T74
Test name
Test status
Simulation time 64075307218 ps
CPU time 367.86 seconds
Started Jun 26 06:49:03 PM PDT 24
Finished Jun 26 06:55:12 PM PDT 24
Peak memory 207020 kb
Host smart-e876fe56-95d5-4ad9-a993-2e2f7eb217a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130681601 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3130681601
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2900774464
Short name T88
Test name
Test status
Simulation time 53633138918 ps
CPU time 133.98 seconds
Started Jun 26 06:48:36 PM PDT 24
Finished Jun 26 06:50:51 PM PDT 24
Peak memory 206644 kb
Host smart-508ed5c5-6e8a-4d80-81b1-afd3edb4a55e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900774464 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2900774464
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3148438573
Short name T162
Test name
Test status
Simulation time 6679807963 ps
CPU time 4.24 seconds
Started Jun 26 06:49:28 PM PDT 24
Finished Jun 26 06:49:34 PM PDT 24
Peak memory 183980 kb
Host smart-9d2bcc1e-221d-407c-b083-4e89d714d80d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148438573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3148438573
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1115802694
Short name T121
Test name
Test status
Simulation time 108282249589 ps
CPU time 590.07 seconds
Started Jun 26 06:49:32 PM PDT 24
Finished Jun 26 06:59:23 PM PDT 24
Peak memory 205516 kb
Host smart-3c8f947d-12e6-4ae0-a933-f0c80b3f14d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115802694 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1115802694
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.4142404939
Short name T114
Test name
Test status
Simulation time 91102518843 ps
CPU time 128.24 seconds
Started Jun 26 06:49:40 PM PDT 24
Finished Jun 26 06:51:49 PM PDT 24
Peak memory 198056 kb
Host smart-e19c60cd-d055-4855-b017-e400c0a01d3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142404939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.4142404939
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3331361581
Short name T157
Test name
Test status
Simulation time 192846886601 ps
CPU time 254.26 seconds
Started Jun 26 06:49:52 PM PDT 24
Finished Jun 26 06:54:07 PM PDT 24
Peak memory 198032 kb
Host smart-d7f22324-a34c-4676-ae1b-8f1d7b06f851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331361581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3331361581
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2161293824
Short name T142
Test name
Test status
Simulation time 509319460 ps
CPU time 1.39 seconds
Started Jun 26 06:50:05 PM PDT 24
Finished Jun 26 06:50:08 PM PDT 24
Peak memory 196556 kb
Host smart-3ab2c1cd-5751-4f3f-bef2-9fb5a41ddd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161293824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2161293824
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1628919572
Short name T144
Test name
Test status
Simulation time 22727945211 ps
CPU time 3.15 seconds
Started Jun 26 06:50:30 PM PDT 24
Finished Jun 26 06:50:34 PM PDT 24
Peak memory 191924 kb
Host smart-bc925669-c053-43fd-8a4a-52bbfd5ffac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628919572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1628919572
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1950878197
Short name T96
Test name
Test status
Simulation time 221664878377 ps
CPU time 46.91 seconds
Started Jun 26 06:50:43 PM PDT 24
Finished Jun 26 06:51:31 PM PDT 24
Peak memory 192752 kb
Host smart-7ed36c86-0a5d-44d8-b579-61c172a634b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950878197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1950878197
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.967755379
Short name T78
Test name
Test status
Simulation time 24958057495 ps
CPU time 189.31 seconds
Started Jun 26 06:49:04 PM PDT 24
Finished Jun 26 06:52:15 PM PDT 24
Peak memory 206612 kb
Host smart-9e419192-875e-4e80-aa26-efac1a404d26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967755379 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.967755379
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3884698749
Short name T156
Test name
Test status
Simulation time 464512601 ps
CPU time 1.19 seconds
Started Jun 26 06:51:02 PM PDT 24
Finished Jun 26 06:51:05 PM PDT 24
Peak memory 196496 kb
Host smart-605ae145-840d-4c74-8631-726f6a05a237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884698749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3884698749
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1625686293
Short name T130
Test name
Test status
Simulation time 197689087560 ps
CPU time 62.59 seconds
Started Jun 26 06:49:18 PM PDT 24
Finished Jun 26 06:50:22 PM PDT 24
Peak memory 198016 kb
Host smart-d3b1c6be-66d7-4566-9135-60df47bb40e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625686293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1625686293
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2511038722
Short name T86
Test name
Test status
Simulation time 496668991 ps
CPU time 0.72 seconds
Started Jun 26 06:49:29 PM PDT 24
Finished Jun 26 06:49:32 PM PDT 24
Peak memory 196132 kb
Host smart-f3ea224b-0c0e-4439-a2a5-6c9c84f37757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511038722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2511038722
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.511859309
Short name T145
Test name
Test status
Simulation time 540044835 ps
CPU time 1.6 seconds
Started Jun 26 06:49:39 PM PDT 24
Finished Jun 26 06:49:42 PM PDT 24
Peak memory 196576 kb
Host smart-ecd81d80-94b9-4c34-bbde-86124441f049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511859309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.511859309
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3765846342
Short name T126
Test name
Test status
Simulation time 364647941 ps
CPU time 1.09 seconds
Started Jun 26 06:49:51 PM PDT 24
Finished Jun 26 06:49:53 PM PDT 24
Peak memory 196448 kb
Host smart-d2209052-c7ed-40cf-8b78-860e49b5cc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765846342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3765846342
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3576120739
Short name T136
Test name
Test status
Simulation time 346317875 ps
CPU time 0.83 seconds
Started Jun 26 06:48:51 PM PDT 24
Finished Jun 26 06:48:54 PM PDT 24
Peak memory 196440 kb
Host smart-bd55ded3-e3e1-4350-b986-8bee0acef9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576120739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3576120739
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1404819936
Short name T70
Test name
Test status
Simulation time 45882617125 ps
CPU time 443.97 seconds
Started Jun 26 06:50:16 PM PDT 24
Finished Jun 26 06:57:42 PM PDT 24
Peak memory 200432 kb
Host smart-0446935d-6cd8-49db-9c0d-b35d83f190bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404819936 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1404819936
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2541765596
Short name T43
Test name
Test status
Simulation time 549604366 ps
CPU time 0.64 seconds
Started Jun 26 06:50:27 PM PDT 24
Finished Jun 26 06:50:29 PM PDT 24
Peak memory 196580 kb
Host smart-1e04638b-87c1-4290-aa70-b318ea8e1b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541765596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2541765596
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3093469097
Short name T129
Test name
Test status
Simulation time 106617991069 ps
CPU time 399.82 seconds
Started Jun 26 06:50:43 PM PDT 24
Finished Jun 26 06:57:24 PM PDT 24
Peak memory 214856 kb
Host smart-49ba3373-7abb-4f7e-9899-689821fc413c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093469097 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3093469097
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.231887066
Short name T139
Test name
Test status
Simulation time 120138140983 ps
CPU time 181.85 seconds
Started Jun 26 06:51:24 PM PDT 24
Finished Jun 26 06:54:28 PM PDT 24
Peak memory 198040 kb
Host smart-778fe869-10f3-4fe3-bb6e-b2dd2784c797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231887066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.231887066
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3894623157
Short name T154
Test name
Test status
Simulation time 445833071 ps
CPU time 0.88 seconds
Started Jun 26 06:49:18 PM PDT 24
Finished Jun 26 06:49:20 PM PDT 24
Peak memory 196448 kb
Host smart-1540a707-3f9b-489b-b4bf-ea28b3032730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894623157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3894623157
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.814756701
Short name T3
Test name
Test status
Simulation time 360593536 ps
CPU time 0.77 seconds
Started Jun 26 06:48:36 PM PDT 24
Finished Jun 26 06:48:38 PM PDT 24
Peak memory 196444 kb
Host smart-4cf937ab-e06d-4111-8ff2-cbfcb8721977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814756701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.814756701
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3551924856
Short name T108
Test name
Test status
Simulation time 426606365 ps
CPU time 0.63 seconds
Started Jun 26 06:50:45 PM PDT 24
Finished Jun 26 06:50:47 PM PDT 24
Peak memory 196504 kb
Host smart-f22dc696-92ac-454d-80d5-b97b667058f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551924856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3551924856
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2859285265
Short name T92
Test name
Test status
Simulation time 583518824 ps
CPU time 1.4 seconds
Started Jun 26 06:51:24 PM PDT 24
Finished Jun 26 06:51:27 PM PDT 24
Peak memory 196608 kb
Host smart-0d246dc9-9cd3-4d8f-b8b9-e234d415e101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859285265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2859285265
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1532423412
Short name T163
Test name
Test status
Simulation time 155626396385 ps
CPU time 103.16 seconds
Started Jun 26 06:49:54 PM PDT 24
Finished Jun 26 06:51:39 PM PDT 24
Peak memory 198104 kb
Host smart-27ae7794-4f97-4fff-a371-09f057b55bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532423412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1532423412
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1637170270
Short name T4
Test name
Test status
Simulation time 430112437 ps
CPU time 0.78 seconds
Started Jun 26 06:50:08 PM PDT 24
Finished Jun 26 06:50:09 PM PDT 24
Peak memory 196572 kb
Host smart-ef48416b-9fa7-442a-b99e-f24d90780679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637170270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1637170270
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1662816052
Short name T147
Test name
Test status
Simulation time 148133993323 ps
CPU time 22.04 seconds
Started Jun 26 06:50:30 PM PDT 24
Finished Jun 26 06:50:54 PM PDT 24
Peak memory 191704 kb
Host smart-7e6eca95-d02f-47e9-855c-796d86aaeb7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662816052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1662816052
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3578696813
Short name T152
Test name
Test status
Simulation time 349335059 ps
CPU time 1.05 seconds
Started Jun 26 06:50:42 PM PDT 24
Finished Jun 26 06:50:45 PM PDT 24
Peak memory 196776 kb
Host smart-20e73610-2825-472c-b4f1-b32f89010e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578696813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3578696813
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2810962123
Short name T42
Test name
Test status
Simulation time 178617056468 ps
CPU time 50.65 seconds
Started Jun 26 06:51:03 PM PDT 24
Finished Jun 26 06:51:56 PM PDT 24
Peak memory 191736 kb
Host smart-752e449c-d934-4bd9-9f34-3a1afbab4616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810962123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2810962123
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1820100824
Short name T165
Test name
Test status
Simulation time 44817195622 ps
CPU time 143.1 seconds
Started Jun 26 06:51:31 PM PDT 24
Finished Jun 26 06:53:55 PM PDT 24
Peak memory 213876 kb
Host smart-2a2a7a35-8c42-49f6-83f7-2d5d6f2d4fcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820100824 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1820100824
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.195435090
Short name T23
Test name
Test status
Simulation time 387124744 ps
CPU time 1.15 seconds
Started Jun 26 06:49:02 PM PDT 24
Finished Jun 26 06:49:04 PM PDT 24
Peak memory 196680 kb
Host smart-c7c0d62e-273f-4d1c-8c37-1301150e1738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195435090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.195435090
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1087003237
Short name T143
Test name
Test status
Simulation time 564141529 ps
CPU time 1.33 seconds
Started Jun 26 06:49:08 PM PDT 24
Finished Jun 26 06:49:10 PM PDT 24
Peak memory 196532 kb
Host smart-5452afdd-2239-478e-91fb-1adb05e1ec90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087003237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1087003237
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1126126668
Short name T102
Test name
Test status
Simulation time 371737311845 ps
CPU time 568.53 seconds
Started Jun 26 06:49:17 PM PDT 24
Finished Jun 26 06:58:47 PM PDT 24
Peak memory 192808 kb
Host smart-6ceb54f0-ad30-44d1-be3c-971c9e00b0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126126668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1126126668
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2499066880
Short name T16
Test name
Test status
Simulation time 68928797646 ps
CPU time 576.05 seconds
Started Jun 26 06:49:16 PM PDT 24
Finished Jun 26 06:58:53 PM PDT 24
Peak memory 210736 kb
Host smart-c743ea11-3eb6-4c7b-acef-bd50bbd7713f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499066880 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2499066880
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3717461050
Short name T132
Test name
Test status
Simulation time 382204178 ps
CPU time 0.72 seconds
Started Jun 26 06:50:17 PM PDT 24
Finished Jun 26 06:50:20 PM PDT 24
Peak memory 196544 kb
Host smart-7ddca9eb-6705-4394-97b9-4af963300538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717461050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3717461050
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.108233884
Short name T168
Test name
Test status
Simulation time 56526047476 ps
CPU time 149.49 seconds
Started Jun 26 06:48:50 PM PDT 24
Finished Jun 26 06:51:21 PM PDT 24
Peak memory 206724 kb
Host smart-a6f9be38-6b33-4efe-9ccc-e1aaade9ec86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108233884 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.108233884
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.4287339037
Short name T24
Test name
Test status
Simulation time 587201754 ps
CPU time 1.27 seconds
Started Jun 26 06:50:41 PM PDT 24
Finished Jun 26 06:50:43 PM PDT 24
Peak memory 196484 kb
Host smart-c58981a3-0fe7-4603-8b35-78fc84bd0226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287339037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.4287339037
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2197642585
Short name T169
Test name
Test status
Simulation time 10084466059 ps
CPU time 104.52 seconds
Started Jun 26 06:50:43 PM PDT 24
Finished Jun 26 06:52:29 PM PDT 24
Peak memory 206668 kb
Host smart-c1f84496-4ad7-4e43-95fe-e45abebc38d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197642585 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2197642585
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.92921726
Short name T164
Test name
Test status
Simulation time 492957308 ps
CPU time 0.97 seconds
Started Jun 26 06:49:08 PM PDT 24
Finished Jun 26 06:49:10 PM PDT 24
Peak memory 196472 kb
Host smart-5c026dec-6349-49b3-b801-546cb246c470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92921726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.92921726
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.987781131
Short name T131
Test name
Test status
Simulation time 545859559 ps
CPU time 0.83 seconds
Started Jun 26 06:51:04 PM PDT 24
Finished Jun 26 06:51:06 PM PDT 24
Peak memory 196556 kb
Host smart-160a6866-03a2-4b3a-b6d1-064ceca50ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987781131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.987781131
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.710981783
Short name T20
Test name
Test status
Simulation time 307873833184 ps
CPU time 127.2 seconds
Started Jun 26 06:51:24 PM PDT 24
Finished Jun 26 06:53:34 PM PDT 24
Peak memory 184012 kb
Host smart-5819f0fc-97bf-431c-8820-19009cafc054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710981783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.710981783
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1806666856
Short name T103
Test name
Test status
Simulation time 431804034 ps
CPU time 1.16 seconds
Started Jun 26 06:51:25 PM PDT 24
Finished Jun 26 06:51:28 PM PDT 24
Peak memory 196692 kb
Host smart-2e0ea375-f7d9-4aa0-afdf-86236dccad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806666856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1806666856
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3591599903
Short name T153
Test name
Test status
Simulation time 541335735 ps
CPU time 0.77 seconds
Started Jun 26 06:51:25 PM PDT 24
Finished Jun 26 06:51:28 PM PDT 24
Peak memory 196508 kb
Host smart-369b8a44-12af-4524-a9b1-f80187e70f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591599903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3591599903
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2880548950
Short name T178
Test name
Test status
Simulation time 57014035881 ps
CPU time 12.53 seconds
Started Jun 26 06:49:01 PM PDT 24
Finished Jun 26 06:49:15 PM PDT 24
Peak memory 192816 kb
Host smart-ce3bcbaf-919a-4186-b90c-6d5872574d1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880548950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2880548950
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1851647151
Short name T116
Test name
Test status
Simulation time 358468180 ps
CPU time 0.8 seconds
Started Jun 26 06:49:18 PM PDT 24
Finished Jun 26 06:49:19 PM PDT 24
Peak memory 196460 kb
Host smart-1dd50e8c-5afa-49bc-ae28-208d64d0598f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851647151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1851647151
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.991861377
Short name T160
Test name
Test status
Simulation time 458285545 ps
CPU time 0.75 seconds
Started Jun 26 06:49:17 PM PDT 24
Finished Jun 26 06:49:19 PM PDT 24
Peak memory 196428 kb
Host smart-b5637624-dcfa-47f0-9ba4-ec2b97e331a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991861377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.991861377
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.69592501
Short name T194
Test name
Test status
Simulation time 8853397642 ps
CPU time 14.29 seconds
Started Jun 26 06:23:04 PM PDT 24
Finished Jun 26 06:23:21 PM PDT 24
Peak memory 198340 kb
Host smart-ba456c97-bd2c-4c6c-8b25-09386aac1f09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69592501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_
intg_err.69592501
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3450246569
Short name T176
Test name
Test status
Simulation time 525959059 ps
CPU time 1.36 seconds
Started Jun 26 06:49:51 PM PDT 24
Finished Jun 26 06:49:54 PM PDT 24
Peak memory 196476 kb
Host smart-a53e83d8-8611-4499-b4be-0ea094cc5b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450246569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3450246569
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.675000892
Short name T25
Test name
Test status
Simulation time 395537994 ps
CPU time 0.91 seconds
Started Jun 26 06:49:52 PM PDT 24
Finished Jun 26 06:49:54 PM PDT 24
Peak memory 196460 kb
Host smart-91d4d24d-6530-45ba-b6bf-7160d83fc9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675000892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.675000892
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2565725070
Short name T181
Test name
Test status
Simulation time 510371266 ps
CPU time 0.7 seconds
Started Jun 26 06:50:06 PM PDT 24
Finished Jun 26 06:50:08 PM PDT 24
Peak memory 196436 kb
Host smart-859cddb3-32b3-42b3-995e-2d6cc9e3d666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565725070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2565725070
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3730543168
Short name T149
Test name
Test status
Simulation time 283087205594 ps
CPU time 214.45 seconds
Started Jun 26 06:50:17 PM PDT 24
Finished Jun 26 06:53:54 PM PDT 24
Peak memory 191732 kb
Host smart-4b3895e2-ac1f-42ad-9bf6-fa19c030e85c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730543168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3730543168
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3958846432
Short name T113
Test name
Test status
Simulation time 457582224 ps
CPU time 1.39 seconds
Started Jun 26 06:50:17 PM PDT 24
Finished Jun 26 06:50:21 PM PDT 24
Peak memory 196532 kb
Host smart-9b8699f6-04f8-4236-88a7-59567f96643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958846432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3958846432
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3928834074
Short name T71
Test name
Test status
Simulation time 45801277921 ps
CPU time 304.64 seconds
Started Jun 26 06:50:21 PM PDT 24
Finished Jun 26 06:55:27 PM PDT 24
Peak memory 206916 kb
Host smart-68eabcd4-841c-4a63-a0ef-195aaa02524c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928834074 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3928834074
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3333199114
Short name T180
Test name
Test status
Simulation time 414266633 ps
CPU time 1.23 seconds
Started Jun 26 06:50:16 PM PDT 24
Finished Jun 26 06:50:19 PM PDT 24
Peak memory 196440 kb
Host smart-8672f3f8-6197-428a-b9dc-8cbbe6303bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333199114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3333199114
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.873280223
Short name T6
Test name
Test status
Simulation time 407385025 ps
CPU time 0.75 seconds
Started Jun 26 06:50:29 PM PDT 24
Finished Jun 26 06:50:32 PM PDT 24
Peak memory 196428 kb
Host smart-5f88eebd-e8f3-4a90-a6cc-fc713e53665a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873280223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.873280223
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1557618315
Short name T183
Test name
Test status
Simulation time 346900484864 ps
CPU time 549.79 seconds
Started Jun 26 06:50:30 PM PDT 24
Finished Jun 26 06:59:42 PM PDT 24
Peak memory 191724 kb
Host smart-02edf142-b42c-43d6-8404-4a9380b25f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557618315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1557618315
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1408349858
Short name T36
Test name
Test status
Simulation time 47676192932 ps
CPU time 88.37 seconds
Started Jun 26 06:50:30 PM PDT 24
Finished Jun 26 06:52:00 PM PDT 24
Peak memory 214060 kb
Host smart-dccbc1e8-dbc4-4be7-bb91-b41566ddcd4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408349858 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1408349858
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.4068291074
Short name T187
Test name
Test status
Simulation time 547606077 ps
CPU time 0.69 seconds
Started Jun 26 06:50:28 PM PDT 24
Finished Jun 26 06:50:30 PM PDT 24
Peak memory 196452 kb
Host smart-c7cc9a59-b400-4ae4-8192-2b38cf9b12ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068291074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.4068291074
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.628762535
Short name T115
Test name
Test status
Simulation time 394599066 ps
CPU time 1.24 seconds
Started Jun 26 06:50:42 PM PDT 24
Finished Jun 26 06:50:45 PM PDT 24
Peak memory 196532 kb
Host smart-7870dc4c-3eab-4236-8188-1dd7165d6f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628762535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.628762535
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2611095624
Short name T146
Test name
Test status
Simulation time 104384039585 ps
CPU time 165.49 seconds
Started Jun 26 06:50:44 PM PDT 24
Finished Jun 26 06:53:31 PM PDT 24
Peak memory 184340 kb
Host smart-b3130418-2a0d-4b99-a516-2021c53ef78e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611095624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2611095624
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2709000707
Short name T175
Test name
Test status
Simulation time 529774340 ps
CPU time 1.48 seconds
Started Jun 26 06:51:04 PM PDT 24
Finished Jun 26 06:51:07 PM PDT 24
Peak memory 196448 kb
Host smart-27fa76c5-a4da-4a8a-852b-fc4f75dbabc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709000707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2709000707
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2023776207
Short name T188
Test name
Test status
Simulation time 399149856 ps
CPU time 1.24 seconds
Started Jun 26 06:48:35 PM PDT 24
Finished Jun 26 06:48:37 PM PDT 24
Peak memory 196656 kb
Host smart-a4ec1e90-951c-4354-82ef-55e870d3de5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023776207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2023776207
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.4089850807
Short name T40
Test name
Test status
Simulation time 428991883 ps
CPU time 1.26 seconds
Started Jun 26 06:49:29 PM PDT 24
Finished Jun 26 06:49:32 PM PDT 24
Peak memory 196592 kb
Host smart-7fcac0b2-7105-4909-9e43-484b51a7b090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089850807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.4089850807
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2502137749
Short name T190
Test name
Test status
Simulation time 603825634 ps
CPU time 0.98 seconds
Started Jun 26 06:49:30 PM PDT 24
Finished Jun 26 06:49:32 PM PDT 24
Peak memory 196540 kb
Host smart-d87ad437-e0c9-4ce9-bf56-637d79d83c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502137749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2502137749
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1806791017
Short name T189
Test name
Test status
Simulation time 91714488371 ps
CPU time 33.71 seconds
Started Jun 26 06:49:50 PM PDT 24
Finished Jun 26 06:50:25 PM PDT 24
Peak memory 191788 kb
Host smart-042284d8-3ddb-4e12-969b-a94bea6968a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806791017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1806791017
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1168913956
Short name T179
Test name
Test status
Simulation time 480802692 ps
CPU time 1.25 seconds
Started Jun 26 06:50:17 PM PDT 24
Finished Jun 26 06:50:20 PM PDT 24
Peak memory 196552 kb
Host smart-a5305ab9-4039-4d51-b16f-b830c6349332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168913956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1168913956
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.364487963
Short name T171
Test name
Test status
Simulation time 513607349 ps
CPU time 0.8 seconds
Started Jun 26 06:50:28 PM PDT 24
Finished Jun 26 06:50:31 PM PDT 24
Peak memory 196420 kb
Host smart-b87daa19-aa36-4135-94bb-2a6b9457e34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364487963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.364487963
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1738204161
Short name T177
Test name
Test status
Simulation time 181762732096 ps
CPU time 61.53 seconds
Started Jun 26 06:50:30 PM PDT 24
Finished Jun 26 06:51:33 PM PDT 24
Peak memory 191712 kb
Host smart-2f5fd047-d787-4933-bc31-921fcf98d5bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738204161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1738204161
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3342990817
Short name T5
Test name
Test status
Simulation time 602818768 ps
CPU time 0.69 seconds
Started Jun 26 06:51:02 PM PDT 24
Finished Jun 26 06:51:05 PM PDT 24
Peak memory 196468 kb
Host smart-d267347c-2f87-4fc9-ab7e-4bf6394915e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342990817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3342990817
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2002693815
Short name T172
Test name
Test status
Simulation time 514643580 ps
CPU time 0.66 seconds
Started Jun 26 06:51:30 PM PDT 24
Finished Jun 26 06:51:31 PM PDT 24
Peak memory 196476 kb
Host smart-9d17bd52-22b7-4cd5-ba2b-9aa095b92e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002693815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2002693815
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1795394136
Short name T173
Test name
Test status
Simulation time 704721343359 ps
CPU time 221.75 seconds
Started Jun 26 06:51:26 PM PDT 24
Finished Jun 26 06:55:10 PM PDT 24
Peak memory 192168 kb
Host smart-ecedd9a0-2ae9-40bd-83e7-b5133cce9617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795394136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1795394136
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2651887646
Short name T174
Test name
Test status
Simulation time 378693432 ps
CPU time 1.06 seconds
Started Jun 26 06:51:28 PM PDT 24
Finished Jun 26 06:51:31 PM PDT 24
Peak memory 196436 kb
Host smart-44faae75-e230-4e56-b528-5085956a7165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651887646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2651887646
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3695069072
Short name T52
Test name
Test status
Simulation time 466501885 ps
CPU time 1.31 seconds
Started Jun 26 06:22:48 PM PDT 24
Finished Jun 26 06:22:51 PM PDT 24
Peak memory 194044 kb
Host smart-81d72622-3e02-4b3c-b754-0fd7f5460165
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695069072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3695069072
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2424461127
Short name T378
Test name
Test status
Simulation time 1439996746 ps
CPU time 0.76 seconds
Started Jun 26 06:22:50 PM PDT 24
Finished Jun 26 06:22:54 PM PDT 24
Peak memory 193336 kb
Host smart-ddbca8a0-4dfa-4ef2-9554-1eb175ebd655
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424461127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2424461127
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1789551456
Short name T329
Test name
Test status
Simulation time 610154793 ps
CPU time 1.08 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:52 PM PDT 24
Peak memory 196656 kb
Host smart-887994f6-7adb-49cc-92c2-abe7b169ec7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789551456 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1789551456
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3897126659
Short name T420
Test name
Test status
Simulation time 377997780 ps
CPU time 1.14 seconds
Started Jun 26 06:22:54 PM PDT 24
Finished Jun 26 06:22:58 PM PDT 24
Peak memory 193036 kb
Host smart-d1ed5807-1fe5-4344-add6-79d4d1faec64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897126659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3897126659
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1474680951
Short name T362
Test name
Test status
Simulation time 450675788 ps
CPU time 0.6 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:54 PM PDT 24
Peak memory 183764 kb
Host smart-4bbdad68-5281-4927-9186-1be453114bd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474680951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1474680951
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3489709403
Short name T417
Test name
Test status
Simulation time 486982154 ps
CPU time 0.9 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:55 PM PDT 24
Peak memory 183776 kb
Host smart-dac5de91-4e6b-4929-967c-14122033ee38
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489709403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3489709403
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2296876904
Short name T394
Test name
Test status
Simulation time 331342859 ps
CPU time 0.92 seconds
Started Jun 26 06:22:54 PM PDT 24
Finished Jun 26 06:22:58 PM PDT 24
Peak memory 183748 kb
Host smart-17d4d35d-fc5c-4c3a-9899-ac6996b6b2bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296876904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2296876904
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1011489817
Short name T418
Test name
Test status
Simulation time 665707995 ps
CPU time 2.05 seconds
Started Jun 26 06:22:48 PM PDT 24
Finished Jun 26 06:22:52 PM PDT 24
Peak memory 198608 kb
Host smart-33b39fb5-4188-48bc-9511-a79cc8e49e4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011489817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1011489817
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3579907935
Short name T28
Test name
Test status
Simulation time 4689920935 ps
CPU time 2.61 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:55 PM PDT 24
Peak memory 197664 kb
Host smart-05ae9a7f-7d0f-45f4-a7e1-044aea447c05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579907935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3579907935
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.420466772
Short name T54
Test name
Test status
Simulation time 568277265 ps
CPU time 0.74 seconds
Started Jun 26 06:22:56 PM PDT 24
Finished Jun 26 06:23:00 PM PDT 24
Peak memory 193236 kb
Host smart-39b76a4f-5b6b-4868-83c7-e96660b34463
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420466772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.420466772
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.444215154
Short name T57
Test name
Test status
Simulation time 7475507410 ps
CPU time 6.67 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:08 PM PDT 24
Peak memory 192244 kb
Host smart-449eec01-d18f-4a90-9740-2489bdaefbfc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444215154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.444215154
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1568017934
Short name T405
Test name
Test status
Simulation time 908251663 ps
CPU time 1.74 seconds
Started Jun 26 06:22:48 PM PDT 24
Finished Jun 26 06:22:52 PM PDT 24
Peak memory 192204 kb
Host smart-b5a3edf9-2daa-4dea-a3e3-9153e38d61b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568017934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1568017934
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1853787654
Short name T375
Test name
Test status
Simulation time 417229072 ps
CPU time 1.05 seconds
Started Jun 26 06:22:58 PM PDT 24
Finished Jun 26 06:23:02 PM PDT 24
Peak memory 197520 kb
Host smart-e408d52e-0cf1-413a-8721-65e6874bde69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853787654 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1853787654
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1634019783
Short name T336
Test name
Test status
Simulation time 552458657 ps
CPU time 0.8 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:56 PM PDT 24
Peak memory 193056 kb
Host smart-ad6c9fd6-5904-42a9-bf9a-b28ad971475c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634019783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1634019783
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2675949913
Short name T364
Test name
Test status
Simulation time 410209795 ps
CPU time 1.19 seconds
Started Jun 26 06:22:49 PM PDT 24
Finished Jun 26 06:22:53 PM PDT 24
Peak memory 183824 kb
Host smart-5b59beb9-0822-423d-870f-d771cce4567a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675949913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2675949913
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1732683606
Short name T413
Test name
Test status
Simulation time 520763080 ps
CPU time 0.68 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:54 PM PDT 24
Peak memory 183776 kb
Host smart-b688236c-bd28-4e1c-9d47-67b226788142
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732683606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1732683606
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1239072640
Short name T374
Test name
Test status
Simulation time 337006129 ps
CPU time 0.6 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:55 PM PDT 24
Peak memory 183768 kb
Host smart-99a84398-f39b-43c1-91bc-d9a6ac4e63e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239072640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1239072640
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1693162888
Short name T411
Test name
Test status
Simulation time 2363513818 ps
CPU time 2.19 seconds
Started Jun 26 06:22:54 PM PDT 24
Finished Jun 26 06:22:59 PM PDT 24
Peak memory 194096 kb
Host smart-cc4b75f9-c700-4cbd-b3b0-99611eecb87b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693162888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1693162888
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1149085540
Short name T312
Test name
Test status
Simulation time 524224018 ps
CPU time 1.2 seconds
Started Jun 26 06:22:51 PM PDT 24
Finished Jun 26 06:22:55 PM PDT 24
Peak memory 197896 kb
Host smart-1f5f84fd-46fe-4a7e-8ab0-2209e6e046f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149085540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1149085540
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3725380227
Short name T409
Test name
Test status
Simulation time 4898353666 ps
CPU time 8.27 seconds
Started Jun 26 06:22:54 PM PDT 24
Finished Jun 26 06:23:06 PM PDT 24
Peak memory 198144 kb
Host smart-11694d42-c14d-4995-853c-2cd9660dd08d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725380227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3725380227
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1134874896
Short name T372
Test name
Test status
Simulation time 573766702 ps
CPU time 0.8 seconds
Started Jun 26 06:23:03 PM PDT 24
Finished Jun 26 06:23:07 PM PDT 24
Peak memory 196304 kb
Host smart-e3175ea8-772d-48b4-93e0-1b2e6a8cb069
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134874896 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1134874896
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.700237287
Short name T55
Test name
Test status
Simulation time 482457062 ps
CPU time 0.95 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 192072 kb
Host smart-40a78fc0-d662-4494-af0a-ffb71412aef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700237287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.700237287
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.676508304
Short name T422
Test name
Test status
Simulation time 499447292 ps
CPU time 1.24 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 183844 kb
Host smart-7654ae58-a5d8-4f6f-aedf-ebed354e096e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676508304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.676508304
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3698364505
Short name T66
Test name
Test status
Simulation time 2547598851 ps
CPU time 3.93 seconds
Started Jun 26 06:23:02 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 192096 kb
Host smart-7814588c-d679-4fe4-8b64-099a4973aa4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698364505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3698364505
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1125137145
Short name T392
Test name
Test status
Simulation time 719581557 ps
CPU time 1.83 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:10 PM PDT 24
Peak memory 198656 kb
Host smart-967e1a79-4ea3-4a83-9420-f4a95dfeb8e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125137145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1125137145
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.4169584940
Short name T334
Test name
Test status
Simulation time 4126005330 ps
CPU time 7.09 seconds
Started Jun 26 06:23:08 PM PDT 24
Finished Jun 26 06:23:17 PM PDT 24
Peak memory 197896 kb
Host smart-af4fc011-5e50-4b45-8f31-d52f2a0b954f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169584940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.4169584940
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1240804547
Short name T402
Test name
Test status
Simulation time 614282772 ps
CPU time 1.14 seconds
Started Jun 26 06:23:03 PM PDT 24
Finished Jun 26 06:23:07 PM PDT 24
Peak memory 198480 kb
Host smart-2ab967b7-bc0d-404f-830e-55133d3dcfa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240804547 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1240804547
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1215618339
Short name T29
Test name
Test status
Simulation time 516257945 ps
CPU time 0.64 seconds
Started Jun 26 06:23:04 PM PDT 24
Finished Jun 26 06:23:07 PM PDT 24
Peak memory 193016 kb
Host smart-e436bd5e-d890-4194-853e-ae57ba40879c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215618339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1215618339
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.326804284
Short name T319
Test name
Test status
Simulation time 338411197 ps
CPU time 1 seconds
Started Jun 26 06:23:04 PM PDT 24
Finished Jun 26 06:23:08 PM PDT 24
Peak memory 183840 kb
Host smart-fbb7bc5e-a91b-4dda-bd05-c27b045b1342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326804284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.326804284
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3659548179
Short name T344
Test name
Test status
Simulation time 1814192009 ps
CPU time 0.85 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 183848 kb
Host smart-cb8c7371-ca8c-47d9-92d9-8ff49f221f9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659548179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3659548179
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.503225838
Short name T289
Test name
Test status
Simulation time 364304452 ps
CPU time 2.52 seconds
Started Jun 26 06:23:06 PM PDT 24
Finished Jun 26 06:23:11 PM PDT 24
Peak memory 198680 kb
Host smart-f9dd6e47-3388-481d-b7f5-ab974edc0c2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503225838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.503225838
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3022253136
Short name T30
Test name
Test status
Simulation time 552296882 ps
CPU time 1.13 seconds
Started Jun 26 06:23:09 PM PDT 24
Finished Jun 26 06:23:11 PM PDT 24
Peak memory 195856 kb
Host smart-1f98edda-6410-482a-9a1e-8e010d1c5c20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022253136 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3022253136
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.843405148
Short name T371
Test name
Test status
Simulation time 453503741 ps
CPU time 0.7 seconds
Started Jun 26 06:23:01 PM PDT 24
Finished Jun 26 06:23:04 PM PDT 24
Peak memory 192084 kb
Host smart-bf23010c-6858-478e-96ff-f949a977357c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843405148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.843405148
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2489273654
Short name T332
Test name
Test status
Simulation time 359372192 ps
CPU time 1.13 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 183812 kb
Host smart-a2e3ea46-b3c8-4ffd-a690-e2d82e009b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489273654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2489273654
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3679957106
Short name T384
Test name
Test status
Simulation time 2831288793 ps
CPU time 4.26 seconds
Started Jun 26 06:23:03 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 195256 kb
Host smart-adf5890f-1638-4906-a95c-38ba318d2d66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679957106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3679957106
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.56447273
Short name T338
Test name
Test status
Simulation time 421814785 ps
CPU time 1.9 seconds
Started Jun 26 06:23:03 PM PDT 24
Finished Jun 26 06:23:08 PM PDT 24
Peak memory 198676 kb
Host smart-89259519-b402-43a1-bcff-82ebe30fb132
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56447273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.56447273
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4012971234
Short name T423
Test name
Test status
Simulation time 8736211217 ps
CPU time 12.49 seconds
Started Jun 26 06:23:03 PM PDT 24
Finished Jun 26 06:23:18 PM PDT 24
Peak memory 198404 kb
Host smart-917a38a2-5830-440c-a014-480724f5cf1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012971234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.4012971234
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.904699474
Short name T387
Test name
Test status
Simulation time 616783626 ps
CPU time 0.96 seconds
Started Jun 26 06:23:04 PM PDT 24
Finished Jun 26 06:23:08 PM PDT 24
Peak memory 196556 kb
Host smart-6aa5294c-f68c-48ed-9481-a1a3ed09cb58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904699474 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.904699474
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.117949637
Short name T302
Test name
Test status
Simulation time 498694944 ps
CPU time 1.22 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 193432 kb
Host smart-6949f7d7-bbe3-4e2f-8a16-6d6433825ee4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117949637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.117949637
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.439550127
Short name T356
Test name
Test status
Simulation time 367499778 ps
CPU time 1.08 seconds
Started Jun 26 06:23:02 PM PDT 24
Finished Jun 26 06:23:05 PM PDT 24
Peak memory 183776 kb
Host smart-b919f7ee-aa05-4e0f-979c-468c670341ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439550127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.439550127
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1114677322
Short name T65
Test name
Test status
Simulation time 1393137428 ps
CPU time 2.17 seconds
Started Jun 26 06:23:04 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 194184 kb
Host smart-02190b7a-04a2-4bc4-b5e6-278d0ff676a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114677322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1114677322
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3073943843
Short name T365
Test name
Test status
Simulation time 863100963 ps
CPU time 2.34 seconds
Started Jun 26 06:23:02 PM PDT 24
Finished Jun 26 06:23:06 PM PDT 24
Peak memory 198700 kb
Host smart-032fb8c5-f7b8-41ea-8677-626989d3b21f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073943843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3073943843
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.778248396
Short name T350
Test name
Test status
Simulation time 8630754604 ps
CPU time 13.72 seconds
Started Jun 26 06:23:01 PM PDT 24
Finished Jun 26 06:23:17 PM PDT 24
Peak memory 198284 kb
Host smart-34c7ece3-bb7e-41f0-91af-a2f15efab720
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778248396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.778248396
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3870106213
Short name T324
Test name
Test status
Simulation time 561140493 ps
CPU time 0.93 seconds
Started Jun 26 06:23:06 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 196388 kb
Host smart-791d4cd5-c6a4-45b6-89dc-6e5aa84f15c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870106213 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3870106213
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3174315995
Short name T49
Test name
Test status
Simulation time 427227661 ps
CPU time 0.71 seconds
Started Jun 26 06:23:03 PM PDT 24
Finished Jun 26 06:23:07 PM PDT 24
Peak memory 192120 kb
Host smart-46613b1c-4c96-4575-bd24-32d112024da1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174315995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3174315995
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2345145635
Short name T346
Test name
Test status
Simulation time 528988634 ps
CPU time 0.79 seconds
Started Jun 26 06:23:03 PM PDT 24
Finished Jun 26 06:23:07 PM PDT 24
Peak memory 183812 kb
Host smart-8f20cbdf-93ce-4c90-ac0d-9415bdbf7428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345145635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2345145635
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3305792424
Short name T62
Test name
Test status
Simulation time 2783348716 ps
CPU time 2.44 seconds
Started Jun 26 06:23:02 PM PDT 24
Finished Jun 26 06:23:07 PM PDT 24
Peak memory 193984 kb
Host smart-46ab6275-2c72-441a-bd9f-460e1f399d83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305792424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3305792424
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.950724872
Short name T393
Test name
Test status
Simulation time 434836031 ps
CPU time 3.1 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:10 PM PDT 24
Peak memory 198692 kb
Host smart-a3f0929e-d7df-4176-90fb-3e111281af28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950724872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.950724872
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.625177156
Short name T330
Test name
Test status
Simulation time 8718689796 ps
CPU time 4.01 seconds
Started Jun 26 06:23:02 PM PDT 24
Finished Jun 26 06:23:08 PM PDT 24
Peak memory 198312 kb
Host smart-caab292b-db4d-4547-83bc-24699372a893
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625177156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.625177156
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.899704020
Short name T293
Test name
Test status
Simulation time 539069287 ps
CPU time 1.41 seconds
Started Jun 26 06:23:02 PM PDT 24
Finished Jun 26 06:23:06 PM PDT 24
Peak memory 196240 kb
Host smart-25b77e3f-f9ba-4604-8f89-9d7a82265717
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899704020 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.899704020
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3192217480
Short name T68
Test name
Test status
Simulation time 434678768 ps
CPU time 0.78 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 193036 kb
Host smart-8798ac8c-13ad-47f8-b5fd-329501169d7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192217480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3192217480
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.325042504
Short name T416
Test name
Test status
Simulation time 416231599 ps
CPU time 0.88 seconds
Started Jun 26 06:23:07 PM PDT 24
Finished Jun 26 06:23:10 PM PDT 24
Peak memory 183836 kb
Host smart-4ed28e6f-6d11-45b4-9a88-40542e53ce54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325042504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.325042504
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.970184361
Short name T353
Test name
Test status
Simulation time 1495089108 ps
CPU time 1.17 seconds
Started Jun 26 06:23:04 PM PDT 24
Finished Jun 26 06:23:08 PM PDT 24
Peak memory 194068 kb
Host smart-a7942c9a-ff6e-425a-8274-f0db7edb8716
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970184361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.970184361
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.240949129
Short name T370
Test name
Test status
Simulation time 928888232 ps
CPU time 1.15 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 198480 kb
Host smart-162708c7-4f62-4cbb-8d70-488fbcf4ca50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240949129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.240949129
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2379846851
Short name T368
Test name
Test status
Simulation time 4790239639 ps
CPU time 2.25 seconds
Started Jun 26 06:23:07 PM PDT 24
Finished Jun 26 06:23:11 PM PDT 24
Peak memory 197796 kb
Host smart-fbc50e8c-a8e3-42cd-bede-347fe991d486
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379846851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2379846851
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2952127983
Short name T341
Test name
Test status
Simulation time 559596937 ps
CPU time 1.5 seconds
Started Jun 26 06:23:13 PM PDT 24
Finished Jun 26 06:23:16 PM PDT 24
Peak memory 196020 kb
Host smart-32b74f0a-cfa9-40fa-825d-9c1778cad22b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952127983 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2952127983
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2915831027
Short name T309
Test name
Test status
Simulation time 500721474 ps
CPU time 0.91 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:14 PM PDT 24
Peak memory 193032 kb
Host smart-7bd0550e-4640-45d7-94b7-5f79de9e2aba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915831027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2915831027
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2404237749
Short name T307
Test name
Test status
Simulation time 384966678 ps
CPU time 0.69 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:14 PM PDT 24
Peak memory 183852 kb
Host smart-c7fd303c-3feb-4e0f-b9fd-b79c35345e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404237749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2404237749
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2270345577
Short name T367
Test name
Test status
Simulation time 1864927645 ps
CPU time 3.62 seconds
Started Jun 26 06:23:13 PM PDT 24
Finished Jun 26 06:23:18 PM PDT 24
Peak memory 195084 kb
Host smart-63f9de4d-625d-4f13-95de-d03958cb11cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270345577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2270345577
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2035035348
Short name T426
Test name
Test status
Simulation time 609169561 ps
CPU time 2.69 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:11 PM PDT 24
Peak memory 198636 kb
Host smart-0f496310-5e14-48dc-a019-018f2554d7b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035035348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2035035348
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3623896672
Short name T408
Test name
Test status
Simulation time 8191408669 ps
CPU time 6.68 seconds
Started Jun 26 06:23:11 PM PDT 24
Finished Jun 26 06:23:19 PM PDT 24
Peak memory 198388 kb
Host smart-c0e04223-58aa-47e5-8476-0a835ee36e79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623896672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3623896672
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4087003628
Short name T339
Test name
Test status
Simulation time 576832634 ps
CPU time 1.01 seconds
Started Jun 26 06:23:14 PM PDT 24
Finished Jun 26 06:23:17 PM PDT 24
Peak memory 197308 kb
Host smart-7edda4c9-7a23-4f5b-af17-5113a79e24a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087003628 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.4087003628
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.764145556
Short name T61
Test name
Test status
Simulation time 462371315 ps
CPU time 0.87 seconds
Started Jun 26 06:23:14 PM PDT 24
Finished Jun 26 06:23:17 PM PDT 24
Peak memory 193224 kb
Host smart-7e2e0373-c028-463c-b6fb-55afb4354915
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764145556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.764145556
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2460188348
Short name T396
Test name
Test status
Simulation time 325531932 ps
CPU time 0.64 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:14 PM PDT 24
Peak memory 183772 kb
Host smart-d6adfbe6-f947-4ce2-9cfb-a18d8d8de5e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460188348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2460188348
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3705909653
Short name T390
Test name
Test status
Simulation time 1462012049 ps
CPU time 2.57 seconds
Started Jun 26 06:23:13 PM PDT 24
Finished Jun 26 06:23:18 PM PDT 24
Peak memory 193580 kb
Host smart-d98ce6b1-b44f-4edd-9acf-3a68958b6592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705909653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3705909653
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.322830959
Short name T381
Test name
Test status
Simulation time 708225870 ps
CPU time 1.71 seconds
Started Jun 26 06:23:11 PM PDT 24
Finished Jun 26 06:23:14 PM PDT 24
Peak memory 198664 kb
Host smart-a2adf739-331b-4566-aa06-6fadbf544d31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322830959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.322830959
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1410471575
Short name T193
Test name
Test status
Simulation time 4723265854 ps
CPU time 2.39 seconds
Started Jun 26 06:23:11 PM PDT 24
Finished Jun 26 06:23:14 PM PDT 24
Peak memory 196576 kb
Host smart-4d0637ea-1023-4eb2-8c82-71c19f4f34b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410471575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1410471575
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.686432084
Short name T415
Test name
Test status
Simulation time 521191343 ps
CPU time 1 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:15 PM PDT 24
Peak memory 196064 kb
Host smart-7d45db63-c22d-4183-904b-9c3748a62839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686432084 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.686432084
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.798974708
Short name T50
Test name
Test status
Simulation time 394155071 ps
CPU time 0.69 seconds
Started Jun 26 06:23:14 PM PDT 24
Finished Jun 26 06:23:17 PM PDT 24
Peak memory 193112 kb
Host smart-a85cbe3b-d864-45bc-b504-9b51fa218630
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798974708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.798974708
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2483290683
Short name T328
Test name
Test status
Simulation time 343815134 ps
CPU time 0.69 seconds
Started Jun 26 06:23:14 PM PDT 24
Finished Jun 26 06:23:17 PM PDT 24
Peak memory 193220 kb
Host smart-3d110f47-8426-4427-a971-8820ddf65164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483290683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2483290683
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2846449996
Short name T382
Test name
Test status
Simulation time 2050466499 ps
CPU time 1.99 seconds
Started Jun 26 06:23:11 PM PDT 24
Finished Jun 26 06:23:15 PM PDT 24
Peak memory 194424 kb
Host smart-97e80469-df6f-43b2-a010-dbf74e7949a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846449996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2846449996
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.290033843
Short name T290
Test name
Test status
Simulation time 607071157 ps
CPU time 1.71 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:15 PM PDT 24
Peak memory 198664 kb
Host smart-3074a8cc-5a19-4ac9-8278-ca024289a682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290033843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.290033843
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3816992784
Short name T347
Test name
Test status
Simulation time 391870849 ps
CPU time 0.99 seconds
Started Jun 26 06:23:17 PM PDT 24
Finished Jun 26 06:23:19 PM PDT 24
Peak memory 196772 kb
Host smart-9afdb37d-3981-4578-b218-ca95c963c870
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816992784 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3816992784
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.302527752
Short name T60
Test name
Test status
Simulation time 530122829 ps
CPU time 0.77 seconds
Started Jun 26 06:23:15 PM PDT 24
Finished Jun 26 06:23:17 PM PDT 24
Peak memory 192276 kb
Host smart-a642a084-a590-4599-83b4-f6973b2c7f36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302527752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.302527752
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4208284362
Short name T322
Test name
Test status
Simulation time 471563920 ps
CPU time 1.26 seconds
Started Jun 26 06:23:11 PM PDT 24
Finished Jun 26 06:23:13 PM PDT 24
Peak memory 183860 kb
Host smart-21edbe0b-ff05-4417-8016-522d99895a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208284362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.4208284362
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3473349400
Short name T63
Test name
Test status
Simulation time 2709379051 ps
CPU time 4.57 seconds
Started Jun 26 06:23:15 PM PDT 24
Finished Jun 26 06:23:21 PM PDT 24
Peak memory 195384 kb
Host smart-5ff752c2-9806-46eb-b39c-207f5c70eab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473349400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3473349400
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1951966857
Short name T326
Test name
Test status
Simulation time 1001401727 ps
CPU time 2 seconds
Started Jun 26 06:23:10 PM PDT 24
Finished Jun 26 06:23:13 PM PDT 24
Peak memory 198672 kb
Host smart-315b52d2-9991-44ee-ab51-f801690d3473
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951966857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1951966857
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1524806204
Short name T325
Test name
Test status
Simulation time 4648674196 ps
CPU time 1.98 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:16 PM PDT 24
Peak memory 197580 kb
Host smart-f5faa03f-cb9e-4c50-9449-3437fa992cd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524806204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1524806204
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2381698574
Short name T401
Test name
Test status
Simulation time 457250254 ps
CPU time 1.38 seconds
Started Jun 26 06:22:56 PM PDT 24
Finished Jun 26 06:23:01 PM PDT 24
Peak memory 194712 kb
Host smart-13bdeb0a-771b-4d22-951e-403b582d587b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381698574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2381698574
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2050959369
Short name T59
Test name
Test status
Simulation time 6212741450 ps
CPU time 13.29 seconds
Started Jun 26 06:22:59 PM PDT 24
Finished Jun 26 06:23:16 PM PDT 24
Peak memory 195340 kb
Host smart-d7d0de98-9356-47f1-9477-e517aef22f0e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050959369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2050959369
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2038092517
Short name T406
Test name
Test status
Simulation time 857227256 ps
CPU time 1.48 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:02 PM PDT 24
Peak memory 192036 kb
Host smart-b62b25c1-288a-43ca-a14a-ab82f82ea04f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038092517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2038092517
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2024741498
Short name T317
Test name
Test status
Simulation time 484441639 ps
CPU time 0.85 seconds
Started Jun 26 06:22:59 PM PDT 24
Finished Jun 26 06:23:03 PM PDT 24
Peak memory 195940 kb
Host smart-64f3c6f4-b512-48c8-949e-aeb11d371f14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024741498 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2024741498
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.313984799
Short name T56
Test name
Test status
Simulation time 448881851 ps
CPU time 0.73 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:01 PM PDT 24
Peak memory 194064 kb
Host smart-344dae64-d7fe-47a2-9d42-61fa628f0ea4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313984799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.313984799
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2486191069
Short name T399
Test name
Test status
Simulation time 526364763 ps
CPU time 0.87 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:01 PM PDT 24
Peak memory 183816 kb
Host smart-f9634995-b060-449a-98f3-a332b7a6d6fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486191069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2486191069
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.460370394
Short name T291
Test name
Test status
Simulation time 531696490 ps
CPU time 0.72 seconds
Started Jun 26 06:22:56 PM PDT 24
Finished Jun 26 06:23:00 PM PDT 24
Peak memory 183760 kb
Host smart-98414adc-efc6-4d61-88a2-ef8a9d9ab0e1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460370394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.460370394
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1939478611
Short name T407
Test name
Test status
Simulation time 379641906 ps
CPU time 0.71 seconds
Started Jun 26 06:22:54 PM PDT 24
Finished Jun 26 06:22:58 PM PDT 24
Peak memory 183776 kb
Host smart-a1ca0d2f-dc1d-4588-bb84-89e52144463c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939478611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1939478611
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2757323160
Short name T349
Test name
Test status
Simulation time 1038029562 ps
CPU time 1.49 seconds
Started Jun 26 06:22:56 PM PDT 24
Finished Jun 26 06:23:01 PM PDT 24
Peak memory 193028 kb
Host smart-1436e937-caee-4414-aeba-b6ce25d8cd8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757323160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2757323160
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3640102529
Short name T287
Test name
Test status
Simulation time 370464976 ps
CPU time 2.24 seconds
Started Jun 26 06:22:59 PM PDT 24
Finished Jun 26 06:23:04 PM PDT 24
Peak memory 198652 kb
Host smart-33121965-51c9-432c-96ed-08621ee851ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640102529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3640102529
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.802856846
Short name T327
Test name
Test status
Simulation time 4129236263 ps
CPU time 4.21 seconds
Started Jun 26 06:22:58 PM PDT 24
Finished Jun 26 06:23:06 PM PDT 24
Peak memory 196540 kb
Host smart-9d3dcabf-7b09-435b-9760-bc2121bdaa17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802856846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.802856846
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1395396263
Short name T306
Test name
Test status
Simulation time 469167858 ps
CPU time 1.15 seconds
Started Jun 26 06:23:13 PM PDT 24
Finished Jun 26 06:23:16 PM PDT 24
Peak memory 193056 kb
Host smart-069641b7-0eeb-4864-9124-247e85e7f6ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395396263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1395396263
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1251258167
Short name T288
Test name
Test status
Simulation time 390127210 ps
CPU time 0.81 seconds
Started Jun 26 06:23:11 PM PDT 24
Finished Jun 26 06:23:12 PM PDT 24
Peak memory 193080 kb
Host smart-1f15805a-79f7-46ee-ac71-343e452cb264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251258167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1251258167
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.305346074
Short name T400
Test name
Test status
Simulation time 458558551 ps
CPU time 0.71 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:15 PM PDT 24
Peak memory 193052 kb
Host smart-32bcd0d7-cf71-4447-83b6-02c5ce474cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305346074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.305346074
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2771842414
Short name T295
Test name
Test status
Simulation time 271062583 ps
CPU time 0.79 seconds
Started Jun 26 06:23:13 PM PDT 24
Finished Jun 26 06:23:16 PM PDT 24
Peak memory 183824 kb
Host smart-fd1d455e-d12f-48e9-aaac-d70236549df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771842414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2771842414
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3716753869
Short name T358
Test name
Test status
Simulation time 277253579 ps
CPU time 0.77 seconds
Started Jun 26 06:23:15 PM PDT 24
Finished Jun 26 06:23:18 PM PDT 24
Peak memory 184000 kb
Host smart-81f85cca-3728-43b2-9bb4-05318020c21a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716753869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3716753869
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2852108603
Short name T412
Test name
Test status
Simulation time 454683046 ps
CPU time 1.16 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:15 PM PDT 24
Peak memory 193040 kb
Host smart-c420606a-4bc8-43ac-bd06-3281a9021469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852108603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2852108603
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3953833138
Short name T286
Test name
Test status
Simulation time 528131208 ps
CPU time 0.69 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:14 PM PDT 24
Peak memory 193028 kb
Host smart-3cb43a8b-9a17-45ab-b8b5-e2447acdab5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953833138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3953833138
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3197946745
Short name T361
Test name
Test status
Simulation time 388716913 ps
CPU time 0.75 seconds
Started Jun 26 06:23:09 PM PDT 24
Finished Jun 26 06:23:11 PM PDT 24
Peak memory 183840 kb
Host smart-a281e617-dfc8-4294-8c3b-d38558b7ee02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197946745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3197946745
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3063043098
Short name T404
Test name
Test status
Simulation time 464495623 ps
CPU time 0.71 seconds
Started Jun 26 06:23:13 PM PDT 24
Finished Jun 26 06:23:16 PM PDT 24
Peak memory 183824 kb
Host smart-1f3a9f7d-2544-46d0-a629-be5fca9f45ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063043098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3063043098
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3834772356
Short name T320
Test name
Test status
Simulation time 461528765 ps
CPU time 0.9 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:15 PM PDT 24
Peak memory 192996 kb
Host smart-ccaf1599-62ca-425e-b688-873402a5a333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834772356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3834772356
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.578751534
Short name T421
Test name
Test status
Simulation time 585045150 ps
CPU time 1.01 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:02 PM PDT 24
Peak memory 183804 kb
Host smart-e4391e0c-795f-419b-a3fd-2cb19a0f12a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578751534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.578751534
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.522471698
Short name T316
Test name
Test status
Simulation time 7329234735 ps
CPU time 4.04 seconds
Started Jun 26 06:23:00 PM PDT 24
Finished Jun 26 06:23:07 PM PDT 24
Peak memory 192236 kb
Host smart-023a46e6-e38b-44e1-b353-35ddb18d494e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522471698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.522471698
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1236338944
Short name T354
Test name
Test status
Simulation time 1161977447 ps
CPU time 1.6 seconds
Started Jun 26 06:22:56 PM PDT 24
Finished Jun 26 06:23:01 PM PDT 24
Peak memory 193112 kb
Host smart-ea604db3-aca7-4921-a77f-414fbe3e498b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236338944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1236338944
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3489083450
Short name T335
Test name
Test status
Simulation time 350548812 ps
CPU time 1.08 seconds
Started Jun 26 06:22:55 PM PDT 24
Finished Jun 26 06:22:59 PM PDT 24
Peak memory 196692 kb
Host smart-571ffcdd-eb28-4f21-aef7-0c23c08cb500
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489083450 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3489083450
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1130159385
Short name T47
Test name
Test status
Simulation time 518703158 ps
CPU time 1 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:02 PM PDT 24
Peak memory 192980 kb
Host smart-90b8f03e-7d43-43c0-9aa4-772b26943bce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130159385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1130159385
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1183914548
Short name T331
Test name
Test status
Simulation time 434495214 ps
CPU time 1.16 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:02 PM PDT 24
Peak memory 183852 kb
Host smart-fbb2f93f-1043-430c-8187-f5fbf260def3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183914548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1183914548
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2600621516
Short name T310
Test name
Test status
Simulation time 326230428 ps
CPU time 0.81 seconds
Started Jun 26 06:22:59 PM PDT 24
Finished Jun 26 06:23:03 PM PDT 24
Peak memory 183736 kb
Host smart-9f9b4a2e-b0b4-40b8-aa3e-307e945647f6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600621516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2600621516
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.807710235
Short name T315
Test name
Test status
Simulation time 465269526 ps
CPU time 1.08 seconds
Started Jun 26 06:22:55 PM PDT 24
Finished Jun 26 06:22:59 PM PDT 24
Peak memory 183764 kb
Host smart-90ac6ecf-1f7f-4051-ad26-70b1659369d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807710235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.807710235
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1598504773
Short name T366
Test name
Test status
Simulation time 2848423189 ps
CPU time 1.34 seconds
Started Jun 26 06:22:55 PM PDT 24
Finished Jun 26 06:23:00 PM PDT 24
Peak memory 194180 kb
Host smart-a6d6dbac-643b-4373-bbc8-124a785c4277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598504773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1598504773
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1457617336
Short name T379
Test name
Test status
Simulation time 471349040 ps
CPU time 2.42 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:03 PM PDT 24
Peak memory 198676 kb
Host smart-0140f7dd-db39-4c39-ab17-48c813ebc8ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457617336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1457617336
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.602065533
Short name T192
Test name
Test status
Simulation time 4575833982 ps
CPU time 2.15 seconds
Started Jun 26 06:22:59 PM PDT 24
Finished Jun 26 06:23:04 PM PDT 24
Peak memory 197928 kb
Host smart-976731df-9e35-4a2e-87a9-f6f7f61da5c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602065533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.602065533
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.842943175
Short name T403
Test name
Test status
Simulation time 578784549 ps
CPU time 0.62 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:14 PM PDT 24
Peak memory 183776 kb
Host smart-1d292184-a390-445c-99f8-cbf36ade8045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842943175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.842943175
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3647324013
Short name T333
Test name
Test status
Simulation time 315763058 ps
CPU time 0.64 seconds
Started Jun 26 06:23:13 PM PDT 24
Finished Jun 26 06:23:15 PM PDT 24
Peak memory 183832 kb
Host smart-a54f09cc-6a50-4cf7-b282-a6e8c27abdf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647324013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3647324013
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1311713602
Short name T337
Test name
Test status
Simulation time 269158840 ps
CPU time 0.86 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:14 PM PDT 24
Peak memory 183860 kb
Host smart-0d2d4c5b-5403-4003-ab20-9bb96ba3b975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311713602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1311713602
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.589034467
Short name T294
Test name
Test status
Simulation time 417871216 ps
CPU time 0.63 seconds
Started Jun 26 06:23:11 PM PDT 24
Finished Jun 26 06:23:12 PM PDT 24
Peak memory 183836 kb
Host smart-aec06d55-b820-4f30-9f08-b4b7f7f8ccb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589034467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.589034467
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.342613365
Short name T303
Test name
Test status
Simulation time 349401386 ps
CPU time 0.71 seconds
Started Jun 26 06:23:20 PM PDT 24
Finished Jun 26 06:23:21 PM PDT 24
Peak memory 193028 kb
Host smart-23ff27b5-1313-4ca9-b5b7-49c1434535fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342613365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.342613365
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1405563103
Short name T386
Test name
Test status
Simulation time 520044857 ps
CPU time 0.83 seconds
Started Jun 26 06:23:15 PM PDT 24
Finished Jun 26 06:23:17 PM PDT 24
Peak memory 183840 kb
Host smart-a345cd97-b780-4a40-86a8-6deea1a3c5a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405563103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1405563103
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3976950780
Short name T323
Test name
Test status
Simulation time 499443236 ps
CPU time 0.9 seconds
Started Jun 26 06:23:14 PM PDT 24
Finished Jun 26 06:23:17 PM PDT 24
Peak memory 193044 kb
Host smart-eff1a7e4-6a70-44af-bf84-0bb39cae0168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976950780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3976950780
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.306996566
Short name T292
Test name
Test status
Simulation time 374044287 ps
CPU time 0.83 seconds
Started Jun 26 06:23:14 PM PDT 24
Finished Jun 26 06:23:17 PM PDT 24
Peak memory 183816 kb
Host smart-53c0a5b5-31a6-4cc2-8556-df6eb437773d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306996566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.306996566
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2385407394
Short name T359
Test name
Test status
Simulation time 437439191 ps
CPU time 1.18 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:16 PM PDT 24
Peak memory 183828 kb
Host smart-18db2aca-2fe9-4848-bcc7-d30aa2a44011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385407394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2385407394
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.385548013
Short name T410
Test name
Test status
Simulation time 300750708 ps
CPU time 0.95 seconds
Started Jun 26 06:23:13 PM PDT 24
Finished Jun 26 06:23:16 PM PDT 24
Peak memory 183836 kb
Host smart-6fefa5e9-9627-4942-957e-f64c4504ff90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385548013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.385548013
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1971302767
Short name T48
Test name
Test status
Simulation time 559237302 ps
CPU time 0.88 seconds
Started Jun 26 06:23:01 PM PDT 24
Finished Jun 26 06:23:04 PM PDT 24
Peak memory 194460 kb
Host smart-b47f0cdb-e084-4bdd-88b2-abf3d5f6f12d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971302767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1971302767
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2294381396
Short name T376
Test name
Test status
Simulation time 7747413551 ps
CPU time 2.26 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:02 PM PDT 24
Peak memory 184084 kb
Host smart-fc8b06cc-c8c8-4d6b-8523-f7dd431aaa0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294381396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2294381396
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1000682780
Short name T300
Test name
Test status
Simulation time 825560868 ps
CPU time 0.98 seconds
Started Jun 26 06:22:54 PM PDT 24
Finished Jun 26 06:22:58 PM PDT 24
Peak memory 183836 kb
Host smart-abc8f5c2-2e82-49d0-9baa-e1adbf86f3da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000682780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1000682780
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1821376997
Short name T395
Test name
Test status
Simulation time 509924966 ps
CPU time 0.9 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:02 PM PDT 24
Peak memory 196072 kb
Host smart-d0037279-5618-4755-8349-3b0739910a99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821376997 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1821376997
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2933923309
Short name T69
Test name
Test status
Simulation time 400369023 ps
CPU time 0.94 seconds
Started Jun 26 06:22:55 PM PDT 24
Finished Jun 26 06:22:59 PM PDT 24
Peak memory 193064 kb
Host smart-bc61868f-f1d0-4ea5-9b9f-b517501c2a3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933923309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2933923309
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1471784694
Short name T299
Test name
Test status
Simulation time 359070792 ps
CPU time 0.72 seconds
Started Jun 26 06:22:55 PM PDT 24
Finished Jun 26 06:22:59 PM PDT 24
Peak memory 183812 kb
Host smart-58a1b0cf-16f6-4fb5-8df2-d4da19bd9134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471784694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1471784694
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.328606482
Short name T301
Test name
Test status
Simulation time 338149740 ps
CPU time 0.66 seconds
Started Jun 26 06:23:00 PM PDT 24
Finished Jun 26 06:23:03 PM PDT 24
Peak memory 183748 kb
Host smart-d98d52dc-ef9f-49a4-916a-88587bcccfe6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328606482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.328606482
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4171971977
Short name T352
Test name
Test status
Simulation time 287221301 ps
CPU time 0.75 seconds
Started Jun 26 06:23:06 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 183760 kb
Host smart-e6c559af-ece8-4ada-b710-4b34e9793d50
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171971977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.4171971977
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1006077105
Short name T348
Test name
Test status
Simulation time 1315732015 ps
CPU time 1.25 seconds
Started Jun 26 06:22:56 PM PDT 24
Finished Jun 26 06:23:00 PM PDT 24
Peak memory 193736 kb
Host smart-61c2b111-4a24-4b5b-944e-fc2ecabb6cd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006077105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1006077105
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3736709250
Short name T373
Test name
Test status
Simulation time 492939780 ps
CPU time 2.82 seconds
Started Jun 26 06:22:58 PM PDT 24
Finished Jun 26 06:23:04 PM PDT 24
Peak memory 198688 kb
Host smart-55225b49-7436-4a11-bda2-91d8d1044d13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736709250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3736709250
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.819229961
Short name T191
Test name
Test status
Simulation time 5046406746 ps
CPU time 1.56 seconds
Started Jun 26 06:23:01 PM PDT 24
Finished Jun 26 06:23:05 PM PDT 24
Peak memory 197912 kb
Host smart-26583eed-f833-45a2-8345-63fe94f68673
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819229961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.819229961
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.415272300
Short name T296
Test name
Test status
Simulation time 473535728 ps
CPU time 1.28 seconds
Started Jun 26 06:23:15 PM PDT 24
Finished Jun 26 06:23:18 PM PDT 24
Peak memory 184004 kb
Host smart-d5c94270-cc2c-42fc-a34e-962e13e1f44d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415272300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.415272300
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.719206411
Short name T314
Test name
Test status
Simulation time 375902570 ps
CPU time 1.04 seconds
Started Jun 26 06:23:10 PM PDT 24
Finished Jun 26 06:23:12 PM PDT 24
Peak memory 193072 kb
Host smart-498f94c3-9aea-4c6b-b07d-fa8ac025d08a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719206411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.719206411
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.521985666
Short name T298
Test name
Test status
Simulation time 410061494 ps
CPU time 0.62 seconds
Started Jun 26 06:23:12 PM PDT 24
Finished Jun 26 06:23:15 PM PDT 24
Peak memory 183812 kb
Host smart-999d489a-51ea-413b-8c0a-5623dacdaf93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521985666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.521985666
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1183086282
Short name T311
Test name
Test status
Simulation time 267170131 ps
CPU time 1 seconds
Started Jun 26 06:23:13 PM PDT 24
Finished Jun 26 06:23:17 PM PDT 24
Peak memory 183860 kb
Host smart-3be60bd4-7bdb-4593-bb0c-60ee8accecc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183086282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1183086282
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2927178109
Short name T318
Test name
Test status
Simulation time 313500817 ps
CPU time 0.98 seconds
Started Jun 26 06:23:21 PM PDT 24
Finished Jun 26 06:23:23 PM PDT 24
Peak memory 183832 kb
Host smart-d1d4c723-9394-41bc-b11b-87cb463a8391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927178109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2927178109
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.11056921
Short name T343
Test name
Test status
Simulation time 498280016 ps
CPU time 1.18 seconds
Started Jun 26 06:23:18 PM PDT 24
Finished Jun 26 06:23:20 PM PDT 24
Peak memory 183828 kb
Host smart-1258e056-55c5-4ee2-b0cf-b77e8107bf74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11056921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.11056921
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2148618787
Short name T342
Test name
Test status
Simulation time 412734821 ps
CPU time 0.72 seconds
Started Jun 26 06:23:22 PM PDT 24
Finished Jun 26 06:23:23 PM PDT 24
Peak memory 183804 kb
Host smart-89dce381-b7a3-4cb8-8b5d-99a2171c69c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148618787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2148618787
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.40468201
Short name T360
Test name
Test status
Simulation time 357249015 ps
CPU time 1.11 seconds
Started Jun 26 06:23:19 PM PDT 24
Finished Jun 26 06:23:21 PM PDT 24
Peak memory 183808 kb
Host smart-c418fca5-637a-4403-bc0b-cfc8a6e26226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40468201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.40468201
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.706193772
Short name T380
Test name
Test status
Simulation time 461842271 ps
CPU time 1.32 seconds
Started Jun 26 06:23:21 PM PDT 24
Finished Jun 26 06:23:23 PM PDT 24
Peak memory 193056 kb
Host smart-f5c1be96-7004-49c7-ae55-f85ae781388f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706193772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.706193772
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3432803880
Short name T383
Test name
Test status
Simulation time 510543040 ps
CPU time 0.7 seconds
Started Jun 26 06:23:20 PM PDT 24
Finished Jun 26 06:23:22 PM PDT 24
Peak memory 184036 kb
Host smart-565c29c8-5b13-4751-8757-a86f2b02ac2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432803880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3432803880
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3631257584
Short name T297
Test name
Test status
Simulation time 488762389 ps
CPU time 1.04 seconds
Started Jun 26 06:22:56 PM PDT 24
Finished Jun 26 06:23:00 PM PDT 24
Peak memory 196564 kb
Host smart-7b6e8615-c537-4bac-997e-550b2d203bf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631257584 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3631257584
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3042581898
Short name T305
Test name
Test status
Simulation time 343703323 ps
CPU time 0.67 seconds
Started Jun 26 06:23:01 PM PDT 24
Finished Jun 26 06:23:04 PM PDT 24
Peak memory 192064 kb
Host smart-cd104fed-0613-4450-8bee-44389fde13c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042581898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3042581898
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.426789723
Short name T385
Test name
Test status
Simulation time 393478188 ps
CPU time 1.11 seconds
Started Jun 26 06:22:54 PM PDT 24
Finished Jun 26 06:22:58 PM PDT 24
Peak memory 183852 kb
Host smart-bdae6b79-9162-41b4-af08-842e6488ad3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426789723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.426789723
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.29592891
Short name T363
Test name
Test status
Simulation time 2883510185 ps
CPU time 7.9 seconds
Started Jun 26 06:23:00 PM PDT 24
Finished Jun 26 06:23:11 PM PDT 24
Peak memory 194104 kb
Host smart-63db9a38-ef30-4749-af19-726d3892f43b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29592891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_t
imer_same_csr_outstanding.29592891
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.842870147
Short name T308
Test name
Test status
Simulation time 1474679649 ps
CPU time 1.36 seconds
Started Jun 26 06:22:54 PM PDT 24
Finished Jun 26 06:22:58 PM PDT 24
Peak memory 198704 kb
Host smart-6a73ee01-19ff-4bb4-9c2c-433cab7a056f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842870147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.842870147
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1498505459
Short name T31
Test name
Test status
Simulation time 4487552539 ps
CPU time 3.07 seconds
Started Jun 26 06:22:59 PM PDT 24
Finished Jun 26 06:23:05 PM PDT 24
Peak memory 198000 kb
Host smart-78e16729-a0b1-4299-95b1-cd64fbbea88a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498505459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1498505459
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3087622157
Short name T202
Test name
Test status
Simulation time 505229607 ps
CPU time 1.09 seconds
Started Jun 26 06:22:56 PM PDT 24
Finished Jun 26 06:23:00 PM PDT 24
Peak memory 198500 kb
Host smart-c82d4b81-0daf-43ee-8a82-d22be8cad75f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087622157 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3087622157
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1391142788
Short name T58
Test name
Test status
Simulation time 539823103 ps
CPU time 0.68 seconds
Started Jun 26 06:23:00 PM PDT 24
Finished Jun 26 06:23:03 PM PDT 24
Peak memory 192992 kb
Host smart-2e988622-5a10-431a-86a0-3544d3fb2b09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391142788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1391142788
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3874954529
Short name T313
Test name
Test status
Simulation time 293652761 ps
CPU time 0.64 seconds
Started Jun 26 06:22:55 PM PDT 24
Finished Jun 26 06:22:59 PM PDT 24
Peak memory 183864 kb
Host smart-ac6b68b3-909f-4420-be2b-c7f6a2b65671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874954529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3874954529
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3047791692
Short name T419
Test name
Test status
Simulation time 2706639013 ps
CPU time 1.03 seconds
Started Jun 26 06:22:56 PM PDT 24
Finished Jun 26 06:23:01 PM PDT 24
Peak memory 195080 kb
Host smart-33bdff71-a223-4983-bb13-58edb3577e2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047791692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3047791692
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2760959563
Short name T397
Test name
Test status
Simulation time 668117885 ps
CPU time 1.31 seconds
Started Jun 26 06:23:00 PM PDT 24
Finished Jun 26 06:23:04 PM PDT 24
Peak memory 198476 kb
Host smart-7fd517fa-ddf5-47cb-bdd3-49730b9d086a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760959563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2760959563
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.810798812
Short name T321
Test name
Test status
Simulation time 8294594550 ps
CPU time 11.39 seconds
Started Jun 26 06:22:55 PM PDT 24
Finished Jun 26 06:23:10 PM PDT 24
Peak memory 198008 kb
Host smart-cc0eb296-0bdf-4930-b70a-3b89e16bdbba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810798812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.810798812
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3365181749
Short name T345
Test name
Test status
Simulation time 381127409 ps
CPU time 1.13 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:02 PM PDT 24
Peak memory 195504 kb
Host smart-db5b5302-7a50-4023-868d-e885e6379920
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365181749 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3365181749
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.652479409
Short name T424
Test name
Test status
Simulation time 386983988 ps
CPU time 1.12 seconds
Started Jun 26 06:23:00 PM PDT 24
Finished Jun 26 06:23:04 PM PDT 24
Peak memory 194040 kb
Host smart-f22b5321-7e18-47ab-996f-695a095633c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652479409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.652479409
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4070351192
Short name T355
Test name
Test status
Simulation time 330842354 ps
CPU time 0.71 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:01 PM PDT 24
Peak memory 183848 kb
Host smart-c11c1cd0-7f77-46a5-b091-20755257da4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070351192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4070351192
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2444172391
Short name T64
Test name
Test status
Simulation time 996884121 ps
CPU time 2.02 seconds
Started Jun 26 06:23:00 PM PDT 24
Finished Jun 26 06:23:05 PM PDT 24
Peak memory 194236 kb
Host smart-25a5dfe1-8d53-4838-be78-793398e07095
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444172391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2444172391
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1346516787
Short name T304
Test name
Test status
Simulation time 410597630 ps
CPU time 2.23 seconds
Started Jun 26 06:22:56 PM PDT 24
Finished Jun 26 06:23:02 PM PDT 24
Peak memory 198692 kb
Host smart-d1b0c5e2-094e-46c3-b0fd-c4b0fc8dd098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346516787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1346516787
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3162693774
Short name T195
Test name
Test status
Simulation time 8235179501 ps
CPU time 13.22 seconds
Started Jun 26 06:22:55 PM PDT 24
Finished Jun 26 06:23:11 PM PDT 24
Peak memory 198336 kb
Host smart-d77abde3-87c4-44d1-abd7-80c9769908b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162693774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3162693774
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2690395494
Short name T357
Test name
Test status
Simulation time 358369443 ps
CPU time 0.77 seconds
Started Jun 26 06:23:04 PM PDT 24
Finished Jun 26 06:23:08 PM PDT 24
Peak memory 195508 kb
Host smart-65b46eaa-231c-4862-97ca-7ca7281e5aec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690395494 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2690395494
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1630977286
Short name T53
Test name
Test status
Simulation time 433767482 ps
CPU time 0.87 seconds
Started Jun 26 06:22:56 PM PDT 24
Finished Jun 26 06:23:00 PM PDT 24
Peak memory 192952 kb
Host smart-ab36a66a-b24f-4983-bb7b-c7f79bfccf53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630977286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1630977286
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2620600187
Short name T398
Test name
Test status
Simulation time 427713630 ps
CPU time 0.8 seconds
Started Jun 26 06:22:56 PM PDT 24
Finished Jun 26 06:23:00 PM PDT 24
Peak memory 183852 kb
Host smart-ed2b9967-4c11-484e-b573-c4b518d6217e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620600187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2620600187
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2063580836
Short name T377
Test name
Test status
Simulation time 2062905946 ps
CPU time 2.76 seconds
Started Jun 26 06:23:01 PM PDT 24
Finished Jun 26 06:23:06 PM PDT 24
Peak memory 192048 kb
Host smart-938d3349-29c3-48c7-971d-e11fd4597def
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063580836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2063580836
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1342044286
Short name T351
Test name
Test status
Simulation time 511832463 ps
CPU time 2.1 seconds
Started Jun 26 06:22:55 PM PDT 24
Finished Jun 26 06:23:00 PM PDT 24
Peak memory 198628 kb
Host smart-e8e0248c-c62f-4fe6-9756-78e3bd518f1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342044286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1342044286
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.179347124
Short name T414
Test name
Test status
Simulation time 5255127372 ps
CPU time 1.43 seconds
Started Jun 26 06:22:57 PM PDT 24
Finished Jun 26 06:23:01 PM PDT 24
Peak memory 196624 kb
Host smart-57a0d532-fe4b-4cee-9180-4f360f9930c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179347124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.179347124
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4209743004
Short name T389
Test name
Test status
Simulation time 801988860 ps
CPU time 1.31 seconds
Started Jun 26 06:23:03 PM PDT 24
Finished Jun 26 06:23:07 PM PDT 24
Peak memory 198716 kb
Host smart-f320611d-dcdb-4f76-8a07-e5eb8664c876
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209743004 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.4209743004
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3750351711
Short name T369
Test name
Test status
Simulation time 342856434 ps
CPU time 1.06 seconds
Started Jun 26 06:23:06 PM PDT 24
Finished Jun 26 06:23:10 PM PDT 24
Peak memory 194052 kb
Host smart-6ac266c0-8aae-4b27-81ed-83f412662322
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750351711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3750351711
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3828931712
Short name T391
Test name
Test status
Simulation time 390228303 ps
CPU time 0.6 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:08 PM PDT 24
Peak memory 193060 kb
Host smart-082f36b1-6b37-4889-8fbb-60c2b9a9989b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828931712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3828931712
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.577952555
Short name T340
Test name
Test status
Simulation time 2417412422 ps
CPU time 2.5 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:10 PM PDT 24
Peak memory 193992 kb
Host smart-b9ecc020-e75d-4845-99bd-33155a328fe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577952555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.577952555
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2623278880
Short name T425
Test name
Test status
Simulation time 583155281 ps
CPU time 1.78 seconds
Started Jun 26 06:23:05 PM PDT 24
Finished Jun 26 06:23:09 PM PDT 24
Peak memory 198676 kb
Host smart-dafe0327-616a-4717-aa21-9ca8b40ffaf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623278880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2623278880
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3453655290
Short name T388
Test name
Test status
Simulation time 8412090323 ps
CPU time 7.24 seconds
Started Jun 26 06:23:07 PM PDT 24
Finished Jun 26 06:23:17 PM PDT 24
Peak memory 198260 kb
Host smart-4a6d9b3b-9602-4327-8639-ff088ef4b088
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453655290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3453655290
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.320926995
Short name T279
Test name
Test status
Simulation time 14502064205 ps
CPU time 19.72 seconds
Started Jun 26 06:48:35 PM PDT 24
Finished Jun 26 06:48:57 PM PDT 24
Peak memory 191724 kb
Host smart-9b1f084a-be4c-4768-bd78-990d1bb07513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320926995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.320926995
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1655114297
Short name T9
Test name
Test status
Simulation time 450150900 ps
CPU time 0.77 seconds
Started Jun 26 06:48:36 PM PDT 24
Finished Jun 26 06:48:38 PM PDT 24
Peak memory 191640 kb
Host smart-8ab138ef-c45d-428b-bef6-e6fb1f6a5048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655114297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1655114297
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3421801186
Short name T198
Test name
Test status
Simulation time 20818406866 ps
CPU time 6.08 seconds
Started Jun 26 06:48:34 PM PDT 24
Finished Jun 26 06:48:42 PM PDT 24
Peak memory 191736 kb
Host smart-9537f0ff-0144-41d6-b9e7-f708d306bc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421801186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3421801186
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2369138249
Short name T22
Test name
Test status
Simulation time 7701625844 ps
CPU time 11.09 seconds
Started Jun 26 06:48:35 PM PDT 24
Finished Jun 26 06:48:47 PM PDT 24
Peak memory 215836 kb
Host smart-0700c1c2-53f3-4ca6-91b6-603f99857ef5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369138249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2369138249
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1277830
Short name T226
Test name
Test status
Simulation time 376956482 ps
CPU time 0.89 seconds
Started Jun 26 06:48:35 PM PDT 24
Finished Jun 26 06:48:38 PM PDT 24
Peak memory 191648 kb
Host smart-bd4da129-ae54-48b6-b7b0-dd170c92f5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1277830
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3717539309
Short name T150
Test name
Test status
Simulation time 539235818 ps
CPU time 1.45 seconds
Started Jun 26 06:49:16 PM PDT 24
Finished Jun 26 06:49:19 PM PDT 24
Peak memory 196520 kb
Host smart-09c7f413-c91a-4c4e-a8ad-349a0a5b0ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717539309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3717539309
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2358432806
Short name T264
Test name
Test status
Simulation time 41430357320 ps
CPU time 14.58 seconds
Started Jun 26 06:49:16 PM PDT 24
Finished Jun 26 06:49:32 PM PDT 24
Peak memory 191700 kb
Host smart-dae4d2bd-55cf-42b2-8ca4-1e3a55162c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358432806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2358432806
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.243023092
Short name T244
Test name
Test status
Simulation time 566368201 ps
CPU time 0.76 seconds
Started Jun 26 06:49:16 PM PDT 24
Finished Jun 26 06:49:19 PM PDT 24
Peak memory 191660 kb
Host smart-2f04c6eb-770e-4091-8b07-891115632c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243023092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.243023092
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.4043063965
Short name T247
Test name
Test status
Simulation time 7017551054 ps
CPU time 2.99 seconds
Started Jun 26 06:49:29 PM PDT 24
Finished Jun 26 06:49:34 PM PDT 24
Peak memory 191356 kb
Host smart-2805c161-9963-4c27-9849-ffd4c65c92a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043063965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.4043063965
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2115221761
Short name T212
Test name
Test status
Simulation time 497458276 ps
CPU time 0.95 seconds
Started Jun 26 06:49:30 PM PDT 24
Finished Jun 26 06:49:33 PM PDT 24
Peak memory 191872 kb
Host smart-f12e2cb7-9a0e-4cbd-add0-03760945a4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115221761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2115221761
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.546931320
Short name T281
Test name
Test status
Simulation time 8348309219 ps
CPU time 3.41 seconds
Started Jun 26 06:49:32 PM PDT 24
Finished Jun 26 06:49:37 PM PDT 24
Peak memory 191676 kb
Host smart-b370993f-9900-4b53-8ad7-9aaade6db00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546931320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.546931320
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2023422556
Short name T7
Test name
Test status
Simulation time 531987372 ps
CPU time 0.72 seconds
Started Jun 26 06:49:27 PM PDT 24
Finished Jun 26 06:49:29 PM PDT 24
Peak memory 191684 kb
Host smart-eb4fa43a-b899-433e-85e7-f032238a14b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023422556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2023422556
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1517884979
Short name T285
Test name
Test status
Simulation time 10325885150 ps
CPU time 8.11 seconds
Started Jun 26 06:49:29 PM PDT 24
Finished Jun 26 06:49:38 PM PDT 24
Peak memory 191736 kb
Host smart-6989eec1-07c8-4f30-abdb-f8902f1671a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517884979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1517884979
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1294044888
Short name T158
Test name
Test status
Simulation time 424652447 ps
CPU time 1.11 seconds
Started Jun 26 06:49:29 PM PDT 24
Finished Jun 26 06:49:32 PM PDT 24
Peak memory 191668 kb
Host smart-06aa2dc6-efa1-4da3-8102-5262c977a2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294044888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1294044888
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.4275620605
Short name T14
Test name
Test status
Simulation time 3776790010 ps
CPU time 5.41 seconds
Started Jun 26 06:49:31 PM PDT 24
Finished Jun 26 06:49:38 PM PDT 24
Peak memory 191748 kb
Host smart-70e69960-0680-477c-9e09-d2b5b0e2f87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275620605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.4275620605
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1027974211
Short name T252
Test name
Test status
Simulation time 460620531 ps
CPU time 0.74 seconds
Started Jun 26 06:49:29 PM PDT 24
Finished Jun 26 06:49:31 PM PDT 24
Peak memory 191688 kb
Host smart-45f42945-2fac-48ff-9865-dd5da6373dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027974211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1027974211
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3028964904
Short name T166
Test name
Test status
Simulation time 422824791 ps
CPU time 0.76 seconds
Started Jun 26 06:49:39 PM PDT 24
Finished Jun 26 06:49:41 PM PDT 24
Peak memory 196384 kb
Host smart-c30a81b2-a879-4b33-9c61-61469488b5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028964904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3028964904
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1070101039
Short name T243
Test name
Test status
Simulation time 31592215661 ps
CPU time 12.57 seconds
Started Jun 26 06:49:40 PM PDT 24
Finished Jun 26 06:49:53 PM PDT 24
Peak memory 191744 kb
Host smart-1b339af7-0061-4ae0-817b-479b69b1a6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070101039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1070101039
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3557068062
Short name T266
Test name
Test status
Simulation time 591893879 ps
CPU time 0.98 seconds
Started Jun 26 06:49:39 PM PDT 24
Finished Jun 26 06:49:41 PM PDT 24
Peak memory 191672 kb
Host smart-bff8c6cc-2495-42fa-867e-3d3958f1de04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557068062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3557068062
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1925822748
Short name T185
Test name
Test status
Simulation time 378173656 ps
CPU time 0.72 seconds
Started Jun 26 06:49:42 PM PDT 24
Finished Jun 26 06:49:43 PM PDT 24
Peak memory 196436 kb
Host smart-050b7250-656e-4514-8a59-f976e914f238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925822748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1925822748
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2067399284
Short name T196
Test name
Test status
Simulation time 6528810142 ps
CPU time 3.11 seconds
Started Jun 26 06:49:42 PM PDT 24
Finished Jun 26 06:49:46 PM PDT 24
Peak memory 196740 kb
Host smart-c04efb48-54ba-4ef6-bc76-2a4e8ada32c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067399284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2067399284
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3846680158
Short name T204
Test name
Test status
Simulation time 457984206 ps
CPU time 1.12 seconds
Started Jun 26 06:49:42 PM PDT 24
Finished Jun 26 06:49:44 PM PDT 24
Peak memory 191676 kb
Host smart-d22cf12e-7e1d-4067-aed5-c57e1778673d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846680158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3846680158
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.733626651
Short name T257
Test name
Test status
Simulation time 8439163008 ps
CPU time 13.43 seconds
Started Jun 26 06:49:42 PM PDT 24
Finished Jun 26 06:49:56 PM PDT 24
Peak memory 191944 kb
Host smart-259619f0-e7c6-4d1c-9b6a-7bdc454dd52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733626651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.733626651
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1638661143
Short name T219
Test name
Test status
Simulation time 509579516 ps
CPU time 1.31 seconds
Started Jun 26 06:49:43 PM PDT 24
Finished Jun 26 06:49:45 PM PDT 24
Peak memory 191680 kb
Host smart-3a61f217-2859-4431-9e77-3f6a4466af54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638661143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1638661143
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2043750796
Short name T230
Test name
Test status
Simulation time 5466754177 ps
CPU time 4.69 seconds
Started Jun 26 06:49:52 PM PDT 24
Finished Jun 26 06:49:59 PM PDT 24
Peak memory 191684 kb
Host smart-13ac3848-20f0-4fb4-bf23-33b582459e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043750796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2043750796
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1486596826
Short name T245
Test name
Test status
Simulation time 382031142 ps
CPU time 0.72 seconds
Started Jun 26 06:49:51 PM PDT 24
Finished Jun 26 06:49:53 PM PDT 24
Peak memory 191656 kb
Host smart-184dd138-8303-463a-99f3-79771dc90088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486596826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1486596826
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1284240735
Short name T276
Test name
Test status
Simulation time 4206318072 ps
CPU time 5.99 seconds
Started Jun 26 06:49:51 PM PDT 24
Finished Jun 26 06:49:59 PM PDT 24
Peak memory 191748 kb
Host smart-3c3ff2ce-a7b5-40dc-98d0-3e4e97681456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284240735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1284240735
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2669059013
Short name T11
Test name
Test status
Simulation time 583621145 ps
CPU time 1.31 seconds
Started Jun 26 06:49:52 PM PDT 24
Finished Jun 26 06:49:54 PM PDT 24
Peak memory 196492 kb
Host smart-55b0573f-dfb9-4590-82a0-fcff6a79e41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669059013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2669059013
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.103934253
Short name T206
Test name
Test status
Simulation time 12571656600 ps
CPU time 19.38 seconds
Started Jun 26 06:48:50 PM PDT 24
Finished Jun 26 06:49:11 PM PDT 24
Peak memory 191692 kb
Host smart-2a25ffdd-6f26-498d-91a4-52fb2af423f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103934253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.103934253
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1674208040
Short name T19
Test name
Test status
Simulation time 4282198510 ps
CPU time 3.51 seconds
Started Jun 26 06:48:51 PM PDT 24
Finished Jun 26 06:48:56 PM PDT 24
Peak memory 215380 kb
Host smart-95697533-b027-472b-aa76-62becd5f96e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674208040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1674208040
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1965989838
Short name T251
Test name
Test status
Simulation time 433336020 ps
CPU time 1.22 seconds
Started Jun 26 06:48:36 PM PDT 24
Finished Jun 26 06:48:39 PM PDT 24
Peak memory 191636 kb
Host smart-7694bb5b-e699-4198-9d0f-fa0cd52ac7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965989838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1965989838
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.4133044396
Short name T277
Test name
Test status
Simulation time 10555632100 ps
CPU time 1.72 seconds
Started Jun 26 06:49:52 PM PDT 24
Finished Jun 26 06:49:55 PM PDT 24
Peak memory 191748 kb
Host smart-b666043f-4d4d-442a-9026-e1ae8acb4232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133044396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.4133044396
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1743105920
Short name T231
Test name
Test status
Simulation time 591266202 ps
CPU time 0.82 seconds
Started Jun 26 06:49:51 PM PDT 24
Finished Jun 26 06:49:53 PM PDT 24
Peak memory 191872 kb
Host smart-31f3f6bb-9105-480a-845b-0d55271a7d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743105920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1743105920
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3581757730
Short name T210
Test name
Test status
Simulation time 14072094756 ps
CPU time 11.72 seconds
Started Jun 26 06:50:04 PM PDT 24
Finished Jun 26 06:50:17 PM PDT 24
Peak memory 196584 kb
Host smart-17864063-4712-4e54-aa9a-c571fe940fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581757730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3581757730
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3908506324
Short name T282
Test name
Test status
Simulation time 338997119 ps
CPU time 0.77 seconds
Started Jun 26 06:50:08 PM PDT 24
Finished Jun 26 06:50:10 PM PDT 24
Peak memory 196548 kb
Host smart-557d83c7-9ebb-4b63-aae1-b5efd06ddfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908506324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3908506324
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3796141839
Short name T186
Test name
Test status
Simulation time 340844454 ps
CPU time 0.87 seconds
Started Jun 26 06:50:04 PM PDT 24
Finished Jun 26 06:50:07 PM PDT 24
Peak memory 196460 kb
Host smart-38fe3e22-fd4e-4d9a-ac70-ad4ad0eb5ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796141839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3796141839
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.4241883073
Short name T211
Test name
Test status
Simulation time 15030089343 ps
CPU time 3.23 seconds
Started Jun 26 06:50:04 PM PDT 24
Finished Jun 26 06:50:09 PM PDT 24
Peak memory 191748 kb
Host smart-b3cd0824-87b2-4a94-8fe8-273a4d693b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241883073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.4241883073
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.569649016
Short name T225
Test name
Test status
Simulation time 488614881 ps
CPU time 0.98 seconds
Started Jun 26 06:50:04 PM PDT 24
Finished Jun 26 06:50:06 PM PDT 24
Peak memory 191660 kb
Host smart-f2663b53-0a87-4956-8c42-a2f623c6cdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569649016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.569649016
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.4291209247
Short name T268
Test name
Test status
Simulation time 8597936336 ps
CPU time 13.41 seconds
Started Jun 26 06:50:04 PM PDT 24
Finished Jun 26 06:50:19 PM PDT 24
Peak memory 191724 kb
Host smart-2fe051e5-5cbc-4434-b58d-36de2513bdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291209247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.4291209247
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.336856495
Short name T205
Test name
Test status
Simulation time 415518958 ps
CPU time 1.04 seconds
Started Jun 26 06:50:05 PM PDT 24
Finished Jun 26 06:50:08 PM PDT 24
Peak memory 191636 kb
Host smart-734ada47-f794-42a4-a4a1-85deb92b04be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336856495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.336856495
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.699477816
Short name T201
Test name
Test status
Simulation time 24102087522 ps
CPU time 32.27 seconds
Started Jun 26 06:50:05 PM PDT 24
Finished Jun 26 06:50:39 PM PDT 24
Peak memory 196736 kb
Host smart-0c69fdf3-861e-49fe-91a6-95c75250f8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699477816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.699477816
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3687327993
Short name T249
Test name
Test status
Simulation time 552173515 ps
CPU time 0.76 seconds
Started Jun 26 06:50:04 PM PDT 24
Finished Jun 26 06:50:06 PM PDT 24
Peak memory 191652 kb
Host smart-bc76e8d3-c723-45c5-9f22-5f7ab43e24d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687327993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3687327993
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2329676336
Short name T197
Test name
Test status
Simulation time 11109204836 ps
CPU time 4.67 seconds
Started Jun 26 06:50:08 PM PDT 24
Finished Jun 26 06:50:14 PM PDT 24
Peak memory 191736 kb
Host smart-0413f325-5f92-41bf-bce5-03792330fbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329676336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2329676336
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2229211078
Short name T274
Test name
Test status
Simulation time 472988394 ps
CPU time 0.78 seconds
Started Jun 26 06:50:05 PM PDT 24
Finished Jun 26 06:50:07 PM PDT 24
Peak memory 191664 kb
Host smart-1edd509f-1b97-41f6-8943-beb75a41feeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229211078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2229211078
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1486584954
Short name T271
Test name
Test status
Simulation time 52195647939 ps
CPU time 73.24 seconds
Started Jun 26 06:50:16 PM PDT 24
Finished Jun 26 06:51:31 PM PDT 24
Peak memory 191712 kb
Host smart-040a14e0-75d8-456f-90e3-f3e851c2a491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486584954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1486584954
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2462261408
Short name T203
Test name
Test status
Simulation time 375633950 ps
CPU time 1.14 seconds
Started Jun 26 06:50:17 PM PDT 24
Finished Jun 26 06:50:20 PM PDT 24
Peak memory 191864 kb
Host smart-1af6034f-eb99-4e7d-b151-bc086cd70bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462261408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2462261408
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1694330212
Short name T222
Test name
Test status
Simulation time 36419240661 ps
CPU time 14.22 seconds
Started Jun 26 06:50:17 PM PDT 24
Finished Jun 26 06:50:33 PM PDT 24
Peak memory 191728 kb
Host smart-0d60593f-94e5-4636-b7a3-53f4129f38e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694330212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1694330212
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.212306434
Short name T258
Test name
Test status
Simulation time 532071123 ps
CPU time 1.12 seconds
Started Jun 26 06:50:14 PM PDT 24
Finished Jun 26 06:50:17 PM PDT 24
Peak memory 191668 kb
Host smart-edd9d159-d14e-4f05-8066-9692a22cb2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212306434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.212306434
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1207910358
Short name T39
Test name
Test status
Simulation time 14484523540 ps
CPU time 15.07 seconds
Started Jun 26 06:50:16 PM PDT 24
Finished Jun 26 06:50:34 PM PDT 24
Peak memory 196720 kb
Host smart-806ef165-1ede-46ee-8e3b-52d293111746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207910358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1207910358
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3986303301
Short name T227
Test name
Test status
Simulation time 536584024 ps
CPU time 1.35 seconds
Started Jun 26 06:50:17 PM PDT 24
Finished Jun 26 06:50:20 PM PDT 24
Peak memory 191872 kb
Host smart-419af47f-4924-4f72-80a6-9f2fcf314d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986303301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3986303301
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2975030018
Short name T184
Test name
Test status
Simulation time 573965676 ps
CPU time 0.8 seconds
Started Jun 26 06:50:17 PM PDT 24
Finished Jun 26 06:50:21 PM PDT 24
Peak memory 196416 kb
Host smart-801683ea-f2c7-4d68-b49e-a3aa0b729151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975030018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2975030018
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.969923060
Short name T250
Test name
Test status
Simulation time 4556982553 ps
CPU time 3.53 seconds
Started Jun 26 06:50:19 PM PDT 24
Finished Jun 26 06:50:24 PM PDT 24
Peak memory 191680 kb
Host smart-62fb523c-9b4b-430a-8a3f-c937dc66aaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969923060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.969923060
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.976052053
Short name T209
Test name
Test status
Simulation time 502969217 ps
CPU time 0.94 seconds
Started Jun 26 06:50:18 PM PDT 24
Finished Jun 26 06:50:21 PM PDT 24
Peak memory 196440 kb
Host smart-433bd3fc-1d30-47ba-afaa-afbc82b60580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976052053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.976052053
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3542095230
Short name T272
Test name
Test status
Simulation time 176397553090 ps
CPU time 34.11 seconds
Started Jun 26 06:50:21 PM PDT 24
Finished Jun 26 06:50:56 PM PDT 24
Peak memory 198040 kb
Host smart-2b44f2b5-d205-4fac-aa2d-1d53f8ad3649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542095230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3542095230
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2246399734
Short name T199
Test name
Test status
Simulation time 14278439476 ps
CPU time 3.83 seconds
Started Jun 26 06:48:49 PM PDT 24
Finished Jun 26 06:48:55 PM PDT 24
Peak memory 191728 kb
Host smart-e1a815e1-c749-420a-a08c-34413ab9b9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246399734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2246399734
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.140455031
Short name T18
Test name
Test status
Simulation time 4447957754 ps
CPU time 1.43 seconds
Started Jun 26 06:48:50 PM PDT 24
Finished Jun 26 06:48:53 PM PDT 24
Peak memory 215804 kb
Host smart-98a16114-7c06-4667-b7d2-01943dba18c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140455031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.140455031
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2278148210
Short name T265
Test name
Test status
Simulation time 552617098 ps
CPU time 1.25 seconds
Started Jun 26 06:48:52 PM PDT 24
Finished Jun 26 06:48:55 PM PDT 24
Peak memory 191640 kb
Host smart-f5b115c1-abff-4d2b-8f19-140500480d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278148210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2278148210
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1413658177
Short name T267
Test name
Test status
Simulation time 30783436936 ps
CPU time 19.28 seconds
Started Jun 26 06:50:16 PM PDT 24
Finished Jun 26 06:50:36 PM PDT 24
Peak memory 191748 kb
Host smart-ca9b46c9-84f1-4cd9-8400-dc8f6285140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413658177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1413658177
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1750837379
Short name T260
Test name
Test status
Simulation time 496799715 ps
CPU time 0.97 seconds
Started Jun 26 06:50:16 PM PDT 24
Finished Jun 26 06:50:18 PM PDT 24
Peak memory 196496 kb
Host smart-298e7898-3ac7-4608-bc96-8564a28e8e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750837379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1750837379
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3932181570
Short name T273
Test name
Test status
Simulation time 41074443225 ps
CPU time 25.96 seconds
Started Jun 26 06:50:31 PM PDT 24
Finished Jun 26 06:51:01 PM PDT 24
Peak memory 196652 kb
Host smart-632cac90-6b40-49a7-9798-60ca7d24a753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932181570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3932181570
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.347666698
Short name T44
Test name
Test status
Simulation time 603901562 ps
CPU time 0.72 seconds
Started Jun 26 06:50:28 PM PDT 24
Finished Jun 26 06:50:30 PM PDT 24
Peak memory 191664 kb
Host smart-f05bcbdc-d24b-4491-b54c-ddf32292c0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347666698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.347666698
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3530723800
Short name T235
Test name
Test status
Simulation time 49634950523 ps
CPU time 8.33 seconds
Started Jun 26 06:50:31 PM PDT 24
Finished Jun 26 06:50:42 PM PDT 24
Peak memory 191716 kb
Host smart-535b20fe-7717-4f96-8cb5-97dd8c2eecc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530723800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3530723800
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.450725831
Short name T233
Test name
Test status
Simulation time 486686027 ps
CPU time 0.67 seconds
Started Jun 26 06:50:30 PM PDT 24
Finished Jun 26 06:50:32 PM PDT 24
Peak memory 191680 kb
Host smart-ce4e5e2b-4e8a-448f-b932-dd5b98561533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450725831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.450725831
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.661654440
Short name T280
Test name
Test status
Simulation time 2869919989 ps
CPU time 4.92 seconds
Started Jun 26 06:50:28 PM PDT 24
Finished Jun 26 06:50:35 PM PDT 24
Peak memory 196568 kb
Host smart-f48f7978-6c3c-4a07-8eb4-8d4c81edb7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661654440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.661654440
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1347904736
Short name T275
Test name
Test status
Simulation time 414765545 ps
CPU time 0.81 seconds
Started Jun 26 06:50:31 PM PDT 24
Finished Jun 26 06:50:35 PM PDT 24
Peak memory 196492 kb
Host smart-13236ad3-ea5c-4eb5-8089-998a7bef3264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347904736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1347904736
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3128873628
Short name T242
Test name
Test status
Simulation time 23184454128 ps
CPU time 8.08 seconds
Started Jun 26 06:50:31 PM PDT 24
Finished Jun 26 06:50:42 PM PDT 24
Peak memory 196720 kb
Host smart-bae3df0d-e3e6-45d9-887a-3b11f36e81fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128873628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3128873628
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3946458889
Short name T215
Test name
Test status
Simulation time 491743797 ps
CPU time 0.76 seconds
Started Jun 26 06:50:31 PM PDT 24
Finished Jun 26 06:50:33 PM PDT 24
Peak memory 191688 kb
Host smart-d1e8c9b9-6f89-4ecc-95e0-d9ea37bc9a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946458889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3946458889
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1385310049
Short name T182
Test name
Test status
Simulation time 577809304 ps
CPU time 0.83 seconds
Started Jun 26 06:50:30 PM PDT 24
Finished Jun 26 06:50:33 PM PDT 24
Peak memory 196460 kb
Host smart-ca4ed594-e50b-42d4-a190-0047699ef939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385310049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1385310049
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2277479952
Short name T254
Test name
Test status
Simulation time 47966821542 ps
CPU time 33.87 seconds
Started Jun 26 06:50:31 PM PDT 24
Finished Jun 26 06:51:07 PM PDT 24
Peak memory 196712 kb
Host smart-e44e8ba6-87ee-4bcb-a5da-9d6ed7906f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277479952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2277479952
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2844506744
Short name T259
Test name
Test status
Simulation time 493383755 ps
CPU time 1.21 seconds
Started Jun 26 06:50:30 PM PDT 24
Finished Jun 26 06:50:33 PM PDT 24
Peak memory 196472 kb
Host smart-7c0728f2-8590-4cea-8a4d-f6113fb8afbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844506744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2844506744
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.105526558
Short name T229
Test name
Test status
Simulation time 14527713267 ps
CPU time 6.31 seconds
Started Jun 26 06:50:28 PM PDT 24
Finished Jun 26 06:50:35 PM PDT 24
Peak memory 191692 kb
Host smart-64b7a2ca-d375-4627-b9f3-d84ba94993ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105526558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.105526558
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2841888353
Short name T213
Test name
Test status
Simulation time 530739474 ps
CPU time 0.91 seconds
Started Jun 26 06:50:31 PM PDT 24
Finished Jun 26 06:50:34 PM PDT 24
Peak memory 191680 kb
Host smart-d13ff7a1-7430-4677-8797-130cb4b8c0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841888353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2841888353
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2875065334
Short name T221
Test name
Test status
Simulation time 10663124267 ps
CPU time 11.4 seconds
Started Jun 26 06:50:47 PM PDT 24
Finished Jun 26 06:51:00 PM PDT 24
Peak memory 191672 kb
Host smart-6bf54283-c2e4-42c9-9f95-9ac2978ddb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875065334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2875065334
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1178016345
Short name T207
Test name
Test status
Simulation time 559949852 ps
CPU time 1.33 seconds
Started Jun 26 06:50:45 PM PDT 24
Finished Jun 26 06:50:48 PM PDT 24
Peak memory 191624 kb
Host smart-8b94af77-9bdc-4f2c-a9e5-ef21c3eaf991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178016345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1178016345
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3875649776
Short name T214
Test name
Test status
Simulation time 9904028458 ps
CPU time 1.68 seconds
Started Jun 26 06:50:42 PM PDT 24
Finished Jun 26 06:50:45 PM PDT 24
Peak memory 196792 kb
Host smart-97a4e7eb-1b52-4c50-9413-86ab0f53aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875649776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3875649776
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3365643694
Short name T217
Test name
Test status
Simulation time 380469919 ps
CPU time 0.75 seconds
Started Jun 26 06:50:43 PM PDT 24
Finished Jun 26 06:50:46 PM PDT 24
Peak memory 191632 kb
Host smart-c890a547-03e3-4fc2-b0ee-1250326dafa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365643694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3365643694
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1470139304
Short name T170
Test name
Test status
Simulation time 422049253 ps
CPU time 0.96 seconds
Started Jun 26 06:50:42 PM PDT 24
Finished Jun 26 06:50:44 PM PDT 24
Peak memory 196440 kb
Host smart-cb9b255d-dcd2-4d92-b14f-0a96f4adb1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470139304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1470139304
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2122010119
Short name T283
Test name
Test status
Simulation time 43649810434 ps
CPU time 50.27 seconds
Started Jun 26 06:50:47 PM PDT 24
Finished Jun 26 06:51:38 PM PDT 24
Peak memory 191672 kb
Host smart-6bf1fea8-7b4a-47c8-9b87-1b7912f4d589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122010119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2122010119
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.819832404
Short name T237
Test name
Test status
Simulation time 664846274 ps
CPU time 0.65 seconds
Started Jun 26 06:50:44 PM PDT 24
Finished Jun 26 06:50:46 PM PDT 24
Peak memory 191868 kb
Host smart-8cdce06c-c512-4da1-ba48-9cc666f6b17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819832404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.819832404
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1234311266
Short name T262
Test name
Test status
Simulation time 4172582007 ps
CPU time 6.11 seconds
Started Jun 26 06:49:03 PM PDT 24
Finished Jun 26 06:49:10 PM PDT 24
Peak memory 191732 kb
Host smart-7fd07c7c-1598-465c-8597-7c16e4fc08e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234311266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1234311266
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2546220243
Short name T17
Test name
Test status
Simulation time 4407789374 ps
CPU time 3.8 seconds
Started Jun 26 06:49:04 PM PDT 24
Finished Jun 26 06:49:10 PM PDT 24
Peak memory 215696 kb
Host smart-bb6389c1-8bba-41e4-bb47-6058e21c7a48
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546220243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2546220243
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3197320449
Short name T8
Test name
Test status
Simulation time 460653137 ps
CPU time 1.25 seconds
Started Jun 26 06:48:49 PM PDT 24
Finished Jun 26 06:48:52 PM PDT 24
Peak memory 196536 kb
Host smart-4bf13120-3487-4f42-8c1d-f66f23edbcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197320449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3197320449
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2592002050
Short name T255
Test name
Test status
Simulation time 36645569083 ps
CPU time 23.1 seconds
Started Jun 26 06:50:43 PM PDT 24
Finished Jun 26 06:51:07 PM PDT 24
Peak memory 196748 kb
Host smart-76f334a8-9bd9-4738-b517-6f11d38c3aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592002050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2592002050
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2886882691
Short name T270
Test name
Test status
Simulation time 412017096 ps
CPU time 0.88 seconds
Started Jun 26 06:50:42 PM PDT 24
Finished Jun 26 06:50:44 PM PDT 24
Peak memory 196548 kb
Host smart-52c27981-5ca8-4cb3-9cac-85c99be4b319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886882691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2886882691
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1466043284
Short name T239
Test name
Test status
Simulation time 18783722580 ps
CPU time 7.04 seconds
Started Jun 26 06:51:02 PM PDT 24
Finished Jun 26 06:51:10 PM PDT 24
Peak memory 191728 kb
Host smart-9f9cf295-d45c-4c30-90c9-7a0d34e031e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466043284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1466043284
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2415010251
Short name T241
Test name
Test status
Simulation time 407411109 ps
CPU time 0.75 seconds
Started Jun 26 06:51:02 PM PDT 24
Finished Jun 26 06:51:05 PM PDT 24
Peak memory 191692 kb
Host smart-e126cdf9-ed5c-4f2a-8d2e-68cc9e07da89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415010251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2415010251
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1957407785
Short name T269
Test name
Test status
Simulation time 18529882944 ps
CPU time 7.25 seconds
Started Jun 26 06:51:03 PM PDT 24
Finished Jun 26 06:51:13 PM PDT 24
Peak memory 196748 kb
Host smart-dd6ae56b-bbc4-4e61-9047-98da0342651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957407785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1957407785
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1870439439
Short name T228
Test name
Test status
Simulation time 601560253 ps
CPU time 1.39 seconds
Started Jun 26 06:51:02 PM PDT 24
Finished Jun 26 06:51:05 PM PDT 24
Peak memory 191660 kb
Host smart-2954aeb5-11f0-4302-ba75-2c647a7dba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870439439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1870439439
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1547215971
Short name T77
Test name
Test status
Simulation time 117961216806 ps
CPU time 241.4 seconds
Started Jun 26 06:51:02 PM PDT 24
Finished Jun 26 06:55:05 PM PDT 24
Peak memory 208688 kb
Host smart-af537ce3-effb-4c9e-b45a-eac777848020
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547215971 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1547215971
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.467159711
Short name T216
Test name
Test status
Simulation time 60711594742 ps
CPU time 17.15 seconds
Started Jun 26 06:51:03 PM PDT 24
Finished Jun 26 06:51:22 PM PDT 24
Peak memory 191748 kb
Host smart-872ca05d-c42f-4c5c-adba-03c912d381f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467159711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.467159711
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.343986463
Short name T278
Test name
Test status
Simulation time 507191280 ps
CPU time 0.95 seconds
Started Jun 26 06:51:03 PM PDT 24
Finished Jun 26 06:51:05 PM PDT 24
Peak memory 191660 kb
Host smart-4638418d-950c-4e76-a8c6-630095035787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343986463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.343986463
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.364310805
Short name T284
Test name
Test status
Simulation time 38549338378 ps
CPU time 6.47 seconds
Started Jun 26 06:51:03 PM PDT 24
Finished Jun 26 06:51:11 PM PDT 24
Peak memory 196740 kb
Host smart-5cee46d2-7b7a-46fa-8799-4c292a8eb7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364310805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.364310805
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1552508143
Short name T238
Test name
Test status
Simulation time 516503472 ps
CPU time 0.74 seconds
Started Jun 26 06:51:03 PM PDT 24
Finished Jun 26 06:51:06 PM PDT 24
Peak memory 191688 kb
Host smart-4070378a-9c74-4be5-8c88-3fd0aa82fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552508143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1552508143
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2441721814
Short name T200
Test name
Test status
Simulation time 16762446765 ps
CPU time 6.02 seconds
Started Jun 26 06:51:22 PM PDT 24
Finished Jun 26 06:51:29 PM PDT 24
Peak memory 191704 kb
Host smart-66f546b0-9782-47fa-b2e5-50a3991db3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441721814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2441721814
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1364125460
Short name T256
Test name
Test status
Simulation time 556528745 ps
CPU time 0.95 seconds
Started Jun 26 06:51:24 PM PDT 24
Finished Jun 26 06:51:27 PM PDT 24
Peak memory 191656 kb
Host smart-734a4524-5b4a-4fff-be1a-6f8015cf001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364125460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1364125460
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.4104647995
Short name T223
Test name
Test status
Simulation time 17837091986 ps
CPU time 6.61 seconds
Started Jun 26 06:51:23 PM PDT 24
Finished Jun 26 06:51:31 PM PDT 24
Peak memory 191792 kb
Host smart-5d638b1e-c792-4d1c-ae93-e07addbe5baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104647995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.4104647995
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.372807136
Short name T246
Test name
Test status
Simulation time 414412070 ps
CPU time 0.88 seconds
Started Jun 26 06:51:24 PM PDT 24
Finished Jun 26 06:51:26 PM PDT 24
Peak memory 196460 kb
Host smart-18987ce2-2b07-4913-9fd9-4e76cd542c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372807136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.372807136
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2389928584
Short name T41
Test name
Test status
Simulation time 21910652476 ps
CPU time 8.25 seconds
Started Jun 26 06:51:25 PM PDT 24
Finished Jun 26 06:51:35 PM PDT 24
Peak memory 191740 kb
Host smart-65c94aa7-f1b7-49f6-b7fc-d280f06a5a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389928584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2389928584
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3880481936
Short name T27
Test name
Test status
Simulation time 433787780 ps
CPU time 1 seconds
Started Jun 26 06:51:24 PM PDT 24
Finished Jun 26 06:51:27 PM PDT 24
Peak memory 196464 kb
Host smart-a1ea6f54-94ab-4d14-a511-aa7e58a4b090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880481936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3880481936
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.624440158
Short name T236
Test name
Test status
Simulation time 26528161225 ps
CPU time 19.16 seconds
Started Jun 26 06:51:23 PM PDT 24
Finished Jun 26 06:51:42 PM PDT 24
Peak memory 191708 kb
Host smart-c0f827ed-32d8-4cf6-a615-598f7b195cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624440158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.624440158
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2817072713
Short name T208
Test name
Test status
Simulation time 374757359 ps
CPU time 1.09 seconds
Started Jun 26 06:51:26 PM PDT 24
Finished Jun 26 06:51:30 PM PDT 24
Peak memory 191692 kb
Host smart-8074ae4e-d13c-4145-87e5-161fa3f8e80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817072713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2817072713
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.4072742451
Short name T248
Test name
Test status
Simulation time 36924764841 ps
CPU time 13.22 seconds
Started Jun 26 06:51:25 PM PDT 24
Finished Jun 26 06:51:40 PM PDT 24
Peak memory 191748 kb
Host smart-5d2051cc-d2d3-4a73-820a-43d47591a360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072742451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.4072742451
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.4197793952
Short name T261
Test name
Test status
Simulation time 362457017 ps
CPU time 1.17 seconds
Started Jun 26 06:51:24 PM PDT 24
Finished Jun 26 06:51:27 PM PDT 24
Peak memory 196548 kb
Host smart-048aa5f9-44ab-48cb-b537-dd95068d8592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197793952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4197793952
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3211530594
Short name T2
Test name
Test status
Simulation time 33205309391 ps
CPU time 49.51 seconds
Started Jun 26 06:49:04 PM PDT 24
Finished Jun 26 06:49:55 PM PDT 24
Peak memory 191944 kb
Host smart-32ac1dbb-f4b7-4488-b689-fcc35056c137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211530594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3211530594
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.4218811827
Short name T220
Test name
Test status
Simulation time 545555194 ps
CPU time 0.99 seconds
Started Jun 26 06:49:05 PM PDT 24
Finished Jun 26 06:49:07 PM PDT 24
Peak memory 191680 kb
Host smart-8d2fc9db-7299-4492-a31e-2f4206d9b343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218811827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.4218811827
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.4281543677
Short name T12
Test name
Test status
Simulation time 5950118686 ps
CPU time 8.04 seconds
Started Jun 26 06:49:07 PM PDT 24
Finished Jun 26 06:49:16 PM PDT 24
Peak memory 191748 kb
Host smart-dedc2038-4177-49ed-9632-2e27111041cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281543677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4281543677
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1442382040
Short name T224
Test name
Test status
Simulation time 519714334 ps
CPU time 0.76 seconds
Started Jun 26 06:49:05 PM PDT 24
Finished Jun 26 06:49:07 PM PDT 24
Peak memory 191672 kb
Host smart-408e1506-4240-4990-abd3-bc974551a4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442382040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1442382040
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1218735012
Short name T263
Test name
Test status
Simulation time 49491807144 ps
CPU time 30.44 seconds
Started Jun 26 06:49:06 PM PDT 24
Finished Jun 26 06:49:37 PM PDT 24
Peak memory 196744 kb
Host smart-bf1659f7-7aa8-438c-9fe7-d075e524bdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218735012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1218735012
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.564609741
Short name T232
Test name
Test status
Simulation time 403439471 ps
CPU time 1.12 seconds
Started Jun 26 06:49:05 PM PDT 24
Finished Jun 26 06:49:07 PM PDT 24
Peak memory 196504 kb
Host smart-15b26ce4-5649-464d-9d97-b25353d76867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564609741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.564609741
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3211040735
Short name T253
Test name
Test status
Simulation time 51309340691 ps
CPU time 4.5 seconds
Started Jun 26 06:49:18 PM PDT 24
Finished Jun 26 06:49:24 PM PDT 24
Peak memory 191724 kb
Host smart-9d7edfce-3978-48e8-acc4-f428603f44f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211040735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3211040735
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.956842234
Short name T234
Test name
Test status
Simulation time 455753901 ps
CPU time 0.94 seconds
Started Jun 26 06:49:16 PM PDT 24
Finished Jun 26 06:49:18 PM PDT 24
Peak memory 191644 kb
Host smart-7e2edce2-9a00-41e3-98c3-7795c6b64cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956842234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.956842234
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.50516500
Short name T240
Test name
Test status
Simulation time 38316415737 ps
CPU time 15.49 seconds
Started Jun 26 06:49:16 PM PDT 24
Finished Jun 26 06:49:33 PM PDT 24
Peak memory 196692 kb
Host smart-11566b52-4abf-417b-93ce-1b7ebcea2aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50516500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.50516500
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3380672583
Short name T218
Test name
Test status
Simulation time 405791728 ps
CPU time 0.73 seconds
Started Jun 26 06:49:17 PM PDT 24
Finished Jun 26 06:49:19 PM PDT 24
Peak memory 191656 kb
Host smart-9fdb5ee1-809f-4157-a6ff-d6096c7937f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380672583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3380672583
Directory /workspace/9.aon_timer_smoke/latest
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