Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	30192	1		T1	12		T3	666		T5	265
bark[1]	1218	1		T6	178		T36	26		T40	14
bark[2]	263	1		T5	21		T141	14		T98	42
bark[3]	526	1		T7	21		T150	39		T83	21
bark[4]	466	1		T30	21		T147	7		T84	113
bark[5]	510	1		T11	93		T92	21		T83	312
bark[6]	813	1		T3	237		T28	21		T108	14
bark[7]	290	1		T3	21		T42	21		T47	73
bark[8]	769	1		T13	31		T29	212		T136	321
bark[9]	541	1		T14	14		T113	14		T29	201
bark[10]	1108	1		T6	26		T12	84		T36	14
bark[11]	721	1		T5	21		T6	269		T7	21
bark[12]	844	1		T3	97		T30	300		T92	21
bark[13]	1059	1		T2	14		T6	21		T7	21
bark[14]	739	1		T11	30		T35	19		T108	21
bark[15]	836	1		T12	14		T29	21		T128	14
bark[16]	361	1		T108	21		T132	21		T136	102
bark[17]	881	1		T7	44		T29	140		T30	21
bark[18]	370	1		T38	14		T175	14		T134	14
bark[19]	459	1		T147	134		T87	7		T101	21
bark[20]	1122	1		T147	44		T80	48		T91	12
bark[21]	534	1		T8	21		T30	106		T95	14
bark[22]	428	1		T141	42		T129	59		T84	187
bark[23]	957	1		T39	14		T83	21		T136	96
bark[24]	542	1		T6	21		T8	31		T29	65
bark[25]	479	1		T8	21		T42	42		T47	44
bark[26]	626	1		T11	114		T35	63		T108	39
bark[27]	523	1		T3	30		T11	21		T12	21
bark[28]	271	1		T156	14		T136	30		T152	14
bark[29]	942	1		T3	266		T13	21		T29	21
bark[30]	231	1		T142	14		T82	49		T159	112
bark[31]	572	1		T8	21		T28	175		T29	21
bark_0	4962	1		T1	7		T2	7		T3	108

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	29553	1		T1	11		T3	659		T5	264
bite[1]	250	1		T108	21		T95	13		T164	13
bite[2]	540	1		T13	211		T29	21		T98	21
bite[3]	1015	1		T6	223		T141	13		T132	45
bite[4]	253	1		T7	13		T98	42		T84	22
bite[5]	233	1		T13	30		T29	72		T156	13
bite[6]	475	1		T28	174		T42	21		T93	30
bite[7]	582	1		T8	31		T92	21		T150	21
bite[8]	824	1		T30	21		T43	21		T88	13
bite[9]	1209	1		T5	21		T7	21		T8	21
bite[10]	1266	1		T3	265		T28	40		T31	281
bite[11]	1052	1		T3	236		T7	30		T29	21
bite[12]	616	1		T29	200		T79	26		T118	21
bite[13]	1005	1		T108	21		T132	34		T42	21
bite[14]	759	1		T3	51		T11	92		T34	88
bite[15]	192	1		T11	6		T12	84		T36	26
bite[16]	634	1		T7	21		T8	13		T13	21
bite[17]	810	1		T28	21		T29	21		T35	21
bite[18]	493	1		T11	113		T38	13		T92	21
bite[19]	860	1		T2	13		T12	13		T34	21
bite[20]	675	1		T5	21		T12	21		T108	21
bite[21]	485	1		T92	30		T42	21		T43	21
bite[22]	1272	1		T6	21		T11	21		T78	223
bite[23]	339	1		T8	21		T29	21		T108	13
bite[24]	286	1		T14	13		T128	13		T108	39
bite[25]	675	1		T29	139		T34	21		T35	18
bite[26]	775	1		T6	268		T40	13		T32	15
bite[27]	394	1		T11	30		T132	21		T157	13
bite[28]	701	1		T3	96		T7	21		T113	13
bite[29]	283	1		T8	21		T92	21		T179	13
bite[30]	448	1		T35	42		T168	13		T153	26
bite[31]	726	1		T36	13		T41	13		T147	6
bite_0	5475	1		T1	8		T2	8		T3	118

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	55155	1		T1	19		T2	21		T3	1425

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	840	1		T6	120		T7	19		T12	55
prescale[1]	1324	1		T3	80		T6	38		T7	9
prescale[2]	1214	1		T3	20		T6	21		T13	45
prescale[3]	840	1		T3	46		T6	40		T28	88
prescale[4]	730	1		T5	24		T7	2		T29	51
prescale[5]	1316	1		T3	303		T6	19		T28	148
prescale[6]	776	1		T3	82		T28	58		T30	19
prescale[7]	678	1		T1	9		T7	2		T28	40
prescale[8]	843	1		T3	114		T5	49		T6	2
prescale[9]	1436	1		T3	2		T6	105		T11	2
prescale[10]	1090	1		T28	23		T36	45		T30	122
prescale[11]	846	1		T6	40		T11	47		T13	102
prescale[12]	775	1		T28	60		T43	44		T78	100
prescale[13]	749	1		T6	28		T7	2		T13	2
prescale[14]	760	1		T12	19		T28	2		T29	20
prescale[15]	1037	1		T3	9		T5	28		T6	340
prescale[16]	1359	1		T3	2		T11	20		T28	2
prescale[17]	972	1		T6	2		T29	2		T30	37
prescale[18]	949	1		T6	20		T13	2		T92	19
prescale[19]	853	1		T33	9		T28	59		T29	2
prescale[20]	1093	1		T3	37		T5	19		T6	71
prescale[21]	1086	1		T11	2		T13	2		T32	70
prescale[22]	886	1		T3	78		T5	19		T29	79
prescale[23]	463	1		T6	33		T7	19		T11	76
prescale[24]	644	1		T6	110		T47	2		T150	24
prescale[25]	1042	1		T7	70		T43	19		T47	2
prescale[26]	703	1		T3	37		T12	23		T28	2
prescale[27]	835	1		T5	52		T11	58		T29	171
prescale[28]	1299	1		T8	132		T28	4		T30	78
prescale[29]	597	1		T3	19		T30	2		T43	19
prescale[30]	627	1		T6	2		T12	103		T13	41
prescale[31]	796	1		T3	2		T6	130		T7	97
prescale_0	25697	1		T1	10		T2	21		T3	594

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40903	1		T1	19		T2	9		T3	1200
auto[1]	14252	1		T2	12		T3	225		T5	226

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	55155	1		T1	19		T2	21		T3	1425

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	32061	1		T1	14		T2	1		T3	779
wkup[1]	292	1		T28	8		T136	21		T79	30
wkup[2]	295	1		T36	15		T43	21		T136	51
wkup[3]	364	1		T11	30		T35	20		T30	21
wkup[4]	379	1		T6	42		T11	21		T29	53
wkup[5]	378	1		T13	21		T28	31		T29	21
wkup[6]	307	1		T6	21		T7	21		T92	21
wkup[7]	157	1		T132	21		T47	21		T147	8
wkup[8]	251	1		T6	21		T8	21		T28	21
wkup[9]	192	1		T138	15		T136	21		T79	21
wkup[10]	387	1		T3	35		T29	42		T30	21
wkup[11]	399	1		T6	42		T11	8		T13	21
wkup[12]	336	1		T6	26		T7	30		T28	15
wkup[13]	140	1		T34	21		T35	21		T43	21
wkup[14]	325	1		T150	26		T83	52		T84	21
wkup[15]	358	1		T3	67		T28	30		T29	21
wkup[16]	293	1		T5	21		T29	21		T47	26
wkup[17]	298	1		T6	42		T7	21		T38	15
wkup[18]	431	1		T5	21		T6	47		T13	21
wkup[19]	143	1		T3	8		T32	21		T83	21
wkup[20]	313	1		T7	21		T11	21		T12	21
wkup[21]	154	1		T12	21		T92	21		T147	21
wkup[22]	338	1		T28	40		T42	21		T47	21
wkup[23]	264	1		T108	21		T92	20		T32	21
wkup[24]	338	1		T11	21		T40	15		T88	15
wkup[25]	242	1		T34	21		T42	26		T78	15
wkup[26]	273	1		T11	21		T156	15		T147	21
wkup[27]	300	1		T7	21		T11	21		T28	21
wkup[28]	372	1		T3	30		T29	21		T31	15
wkup[29]	344	1		T6	21		T28	26		T30	21
wkup[30]	164	1		T12	21		T42	21		T78	21
wkup[31]	402	1		T29	35		T30	56		T132	26
wkup[32]	321	1		T3	44		T128	15		T35	26
wkup[33]	366	1		T3	48		T34	21		T47	21
wkup[34]	376	1		T132	21		T98	21		T136	63
wkup[35]	336	1		T8	52		T11	21		T34	21
wkup[36]	130	1		T30	21		T140	15		T100	42
wkup[37]	276	1		T5	30		T29	47		T32	8
wkup[38]	390	1		T3	21		T6	21		T7	21
wkup[39]	212	1		T83	39		T147	21		T125	26
wkup[40]	388	1		T3	42		T6	21		T8	21
wkup[41]	211	1		T31	21		T141	15		T144	15
wkup[42]	228	1		T29	30		T78	47		T136	26
wkup[43]	317	1		T3	47		T11	47		T29	21
wkup[44]	412	1		T2	15		T3	51		T6	42
wkup[45]	341	1		T6	21		T29	51		T30	21
wkup[46]	369	1		T29	26		T35	21		T30	21
wkup[47]	315	1		T11	44		T12	15		T29	45
wkup[48]	257	1		T3	21		T6	21		T35	21
wkup[49]	248	1		T6	21		T30	21		T42	21
wkup[50]	283	1		T3	50		T29	21		T83	30
wkup[51]	292	1		T13	26		T29	26		T78	21
wkup[52]	311	1		T7	15		T42	21		T78	21
wkup[53]	449	1		T7	30		T42	21		T78	30
wkup[54]	296	1		T12	21		T29	45		T31	30
wkup[55]	400	1		T28	21		T29	21		T168	15
wkup[56]	338	1		T108	21		T95	15		T48	15
wkup[57]	335	1		T30	52		T151	15		T50	21
wkup[58]	380	1		T6	49		T108	15		T78	21
wkup[59]	324	1		T3	47		T6	26		T12	21
wkup[60]	241	1		T3	21		T30	21		T132	26
wkup[61]	264	1		T108	21		T164	15		T79	21
wkup[62]	343	1		T6	42		T7	21		T36	26
wkup[63]	272	1		T3	26		T92	21		T42	30
wkup_0	3844	1		T1	5		T2	5		T3	88