Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
3401 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T2 |
3 |
all_pins[1] |
3401 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T2 |
3 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
4670 |
1 |
|
T1 |
5 |
|
T4 |
2 |
|
T2 |
4 |
values[0x1] |
2132 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
32 |
transitions[0x0=>0x1] |
1641 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
29 |
transitions[0x1=>0x0] |
1576 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
29 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
2675 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T2 |
2 |
all_pins[0] |
values[0x1] |
726 |
1 |
|
T2 |
1 |
|
T3 |
6 |
|
T5 |
11 |
all_pins[0] |
transitions[0x0=>0x1] |
396 |
1 |
|
T2 |
1 |
|
T3 |
3 |
|
T5 |
6 |
all_pins[0] |
transitions[0x1=>0x0] |
1076 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
23 |
all_pins[1] |
values[0x0] |
1995 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T2 |
2 |
all_pins[1] |
values[0x1] |
1406 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
26 |
all_pins[1] |
transitions[0x0=>0x1] |
1245 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
26 |
all_pins[1] |
transitions[0x1=>0x0] |
500 |
1 |
|
T3 |
6 |
|
T5 |
8 |
|
T6 |
9 |