Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.31 99.33 93.67 100.00 98.40 99.51 50.96


Total test records in report: 420
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T21 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1372532783 Jun 27 06:09:02 PM PDT 24 Jun 27 06:09:05 PM PDT 24 383939248 ps
T282 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2032834206 Jun 27 06:09:00 PM PDT 24 Jun 27 06:09:02 PM PDT 24 563967335 ps
T22 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3145756508 Jun 27 06:08:53 PM PDT 24 Jun 27 06:08:57 PM PDT 24 4291968550 ps
T27 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.881167492 Jun 27 06:08:52 PM PDT 24 Jun 27 06:08:54 PM PDT 24 446053016 ps
T70 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2828144641 Jun 27 06:08:43 PM PDT 24 Jun 27 06:08:47 PM PDT 24 445352452 ps
T283 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.4178528073 Jun 27 06:09:01 PM PDT 24 Jun 27 06:09:04 PM PDT 24 411917900 ps
T284 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1976675348 Jun 27 06:09:08 PM PDT 24 Jun 27 06:09:10 PM PDT 24 381956505 ps
T23 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.850622512 Jun 27 06:08:40 PM PDT 24 Jun 27 06:08:46 PM PDT 24 4494048339 ps
T193 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4100328108 Jun 27 06:09:02 PM PDT 24 Jun 27 06:09:05 PM PDT 24 472824182 ps
T285 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.543188792 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:12 PM PDT 24 380361206 ps
T286 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1369492986 Jun 27 06:08:53 PM PDT 24 Jun 27 06:08:56 PM PDT 24 488639545 ps
T287 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1042606746 Jun 27 06:09:00 PM PDT 24 Jun 27 06:09:04 PM PDT 24 454816517 ps
T288 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.613463846 Jun 27 06:08:57 PM PDT 24 Jun 27 06:09:00 PM PDT 24 521911886 ps
T289 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4143362554 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:12 PM PDT 24 459398623 ps
T71 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2462539299 Jun 27 06:08:45 PM PDT 24 Jun 27 06:08:49 PM PDT 24 1004734034 ps
T24 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.826069971 Jun 27 06:09:00 PM PDT 24 Jun 27 06:09:03 PM PDT 24 3893308259 ps
T290 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.680321253 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:12 PM PDT 24 528244103 ps
T291 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2997195132 Jun 27 06:09:10 PM PDT 24 Jun 27 06:09:13 PM PDT 24 442978105 ps
T292 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.878829576 Jun 27 06:09:02 PM PDT 24 Jun 27 06:09:06 PM PDT 24 538450285 ps
T72 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3738831898 Jun 27 06:08:54 PM PDT 24 Jun 27 06:08:58 PM PDT 24 2756630692 ps
T293 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3214054902 Jun 27 06:08:42 PM PDT 24 Jun 27 06:08:46 PM PDT 24 335870563 ps
T188 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3015390718 Jun 27 06:08:53 PM PDT 24 Jun 27 06:09:01 PM PDT 24 7865116807 ps
T189 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1675131094 Jun 27 06:08:43 PM PDT 24 Jun 27 06:08:52 PM PDT 24 8692247089 ps
T294 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1963223424 Jun 27 06:09:00 PM PDT 24 Jun 27 06:09:02 PM PDT 24 395751900 ps
T190 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1206768727 Jun 27 06:09:00 PM PDT 24 Jun 27 06:09:08 PM PDT 24 4167675070 ps
T295 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1361561806 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:12 PM PDT 24 395035411 ps
T296 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2135988109 Jun 27 06:09:08 PM PDT 24 Jun 27 06:09:11 PM PDT 24 491056985 ps
T297 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.113410358 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:12 PM PDT 24 532127804 ps
T298 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2728821463 Jun 27 06:08:42 PM PDT 24 Jun 27 06:08:47 PM PDT 24 328489818 ps
T73 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2285150493 Jun 27 06:08:40 PM PDT 24 Jun 27 06:08:45 PM PDT 24 1908907299 ps
T299 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3794808539 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:12 PM PDT 24 549895472 ps
T52 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2521295316 Jun 27 06:08:41 PM PDT 24 Jun 27 06:08:45 PM PDT 24 397538328 ps
T300 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3147162721 Jun 27 06:08:54 PM PDT 24 Jun 27 06:08:57 PM PDT 24 475954314 ps
T53 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2454520344 Jun 27 06:08:59 PM PDT 24 Jun 27 06:09:02 PM PDT 24 330433286 ps
T301 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2664155073 Jun 27 06:08:38 PM PDT 24 Jun 27 06:08:40 PM PDT 24 746797038 ps
T74 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2903253641 Jun 27 06:08:56 PM PDT 24 Jun 27 06:08:59 PM PDT 24 1365846194 ps
T302 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2901314063 Jun 27 06:09:08 PM PDT 24 Jun 27 06:09:10 PM PDT 24 535819867 ps
T303 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1565929863 Jun 27 06:09:02 PM PDT 24 Jun 27 06:09:05 PM PDT 24 502779685 ps
T54 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.834689299 Jun 27 06:08:40 PM PDT 24 Jun 27 06:08:45 PM PDT 24 571448003 ps
T304 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2052890206 Jun 27 06:08:37 PM PDT 24 Jun 27 06:08:40 PM PDT 24 521632642 ps
T305 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2009488154 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:14 PM PDT 24 1867796032 ps
T306 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1949311617 Jun 27 06:08:56 PM PDT 24 Jun 27 06:09:00 PM PDT 24 428985479 ps
T307 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1901087721 Jun 27 06:08:56 PM PDT 24 Jun 27 06:08:59 PM PDT 24 385560297 ps
T308 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1855190469 Jun 27 06:09:18 PM PDT 24 Jun 27 06:09:20 PM PDT 24 304918281 ps
T309 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3830320254 Jun 27 06:09:30 PM PDT 24 Jun 27 06:09:33 PM PDT 24 480440425 ps
T56 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2503255904 Jun 27 06:08:40 PM PDT 24 Jun 27 06:08:43 PM PDT 24 522994494 ps
T310 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1699387399 Jun 27 06:08:52 PM PDT 24 Jun 27 06:08:55 PM PDT 24 521899577 ps
T311 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3085603424 Jun 27 06:08:41 PM PDT 24 Jun 27 06:08:46 PM PDT 24 410035605 ps
T312 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1481244904 Jun 27 06:09:08 PM PDT 24 Jun 27 06:09:10 PM PDT 24 291038430 ps
T313 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.249809644 Jun 27 06:08:45 PM PDT 24 Jun 27 06:08:49 PM PDT 24 882588085 ps
T314 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1841318472 Jun 27 06:08:56 PM PDT 24 Jun 27 06:08:59 PM PDT 24 384517285 ps
T75 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.608951144 Jun 27 06:08:52 PM PDT 24 Jun 27 06:08:55 PM PDT 24 1104198941 ps
T315 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1999056344 Jun 27 06:09:12 PM PDT 24 Jun 27 06:09:14 PM PDT 24 459866428 ps
T316 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3147941677 Jun 27 06:09:17 PM PDT 24 Jun 27 06:09:19 PM PDT 24 511138323 ps
T317 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2780599617 Jun 27 06:09:13 PM PDT 24 Jun 27 06:09:15 PM PDT 24 274296904 ps
T57 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1010916271 Jun 27 06:08:42 PM PDT 24 Jun 27 06:08:46 PM PDT 24 540395162 ps
T318 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3278769717 Jun 27 06:08:59 PM PDT 24 Jun 27 06:09:01 PM PDT 24 485070933 ps
T76 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1391586927 Jun 27 06:08:43 PM PDT 24 Jun 27 06:08:48 PM PDT 24 2047655417 ps
T319 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1289781663 Jun 27 06:09:02 PM PDT 24 Jun 27 06:09:05 PM PDT 24 371639026 ps
T320 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.924125248 Jun 27 06:08:43 PM PDT 24 Jun 27 06:08:48 PM PDT 24 604965238 ps
T321 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.169189710 Jun 27 06:09:31 PM PDT 24 Jun 27 06:09:34 PM PDT 24 300949352 ps
T77 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2594057587 Jun 27 06:08:55 PM PDT 24 Jun 27 06:08:58 PM PDT 24 355226340 ps
T322 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1453792331 Jun 27 06:08:57 PM PDT 24 Jun 27 06:09:00 PM PDT 24 487346839 ps
T323 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.705520756 Jun 27 06:08:42 PM PDT 24 Jun 27 06:08:48 PM PDT 24 7443108791 ps
T324 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1282994377 Jun 27 06:08:52 PM PDT 24 Jun 27 06:08:55 PM PDT 24 433204062 ps
T325 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3324357727 Jun 27 06:09:08 PM PDT 24 Jun 27 06:09:10 PM PDT 24 317213734 ps
T326 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1110942181 Jun 27 06:08:42 PM PDT 24 Jun 27 06:08:46 PM PDT 24 507081336 ps
T327 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1500612092 Jun 27 06:08:40 PM PDT 24 Jun 27 06:08:44 PM PDT 24 502046074 ps
T328 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3975527275 Jun 27 06:08:37 PM PDT 24 Jun 27 06:08:38 PM PDT 24 307481875 ps
T329 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1410022069 Jun 27 06:08:39 PM PDT 24 Jun 27 06:08:43 PM PDT 24 397868453 ps
T330 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2676161289 Jun 27 06:08:40 PM PDT 24 Jun 27 06:08:44 PM PDT 24 451802824 ps
T331 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.840337993 Jun 27 06:08:42 PM PDT 24 Jun 27 06:08:46 PM PDT 24 1647194644 ps
T332 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2037772134 Jun 27 06:08:56 PM PDT 24 Jun 27 06:09:03 PM PDT 24 2427322609 ps
T333 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.787146585 Jun 27 06:09:08 PM PDT 24 Jun 27 06:09:09 PM PDT 24 341467846 ps
T185 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1966382882 Jun 27 06:09:00 PM PDT 24 Jun 27 06:09:09 PM PDT 24 4487773923 ps
T334 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2781801989 Jun 27 06:08:53 PM PDT 24 Jun 27 06:08:55 PM PDT 24 467573421 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1976305415 Jun 27 06:08:45 PM PDT 24 Jun 27 06:08:49 PM PDT 24 485366819 ps
T335 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2820320537 Jun 27 06:08:40 PM PDT 24 Jun 27 06:08:45 PM PDT 24 4524873386 ps
T336 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.965091202 Jun 27 06:09:17 PM PDT 24 Jun 27 06:09:19 PM PDT 24 400220614 ps
T337 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2085535540 Jun 27 06:08:56 PM PDT 24 Jun 27 06:09:00 PM PDT 24 467865681 ps
T338 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3235847256 Jun 27 06:08:54 PM PDT 24 Jun 27 06:08:58 PM PDT 24 494147566 ps
T55 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3633244253 Jun 27 06:08:39 PM PDT 24 Jun 27 06:08:45 PM PDT 24 5225453018 ps
T339 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2341965587 Jun 27 06:09:07 PM PDT 24 Jun 27 06:09:09 PM PDT 24 570270538 ps
T340 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.722636518 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:19 PM PDT 24 4269062285 ps
T341 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3808279757 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:12 PM PDT 24 326218509 ps
T342 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2600458849 Jun 27 06:08:55 PM PDT 24 Jun 27 06:09:04 PM PDT 24 2508182740 ps
T343 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1204486392 Jun 27 06:09:10 PM PDT 24 Jun 27 06:09:13 PM PDT 24 1464437408 ps
T344 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3504653283 Jun 27 06:09:02 PM PDT 24 Jun 27 06:09:04 PM PDT 24 268114575 ps
T345 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2209172840 Jun 27 06:08:53 PM PDT 24 Jun 27 06:08:56 PM PDT 24 553234816 ps
T346 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3142811530 Jun 27 06:09:30 PM PDT 24 Jun 27 06:09:34 PM PDT 24 386762316 ps
T347 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3972119329 Jun 27 06:09:18 PM PDT 24 Jun 27 06:09:19 PM PDT 24 452794406 ps
T348 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1439978150 Jun 27 06:08:54 PM PDT 24 Jun 27 06:08:58 PM PDT 24 2109326990 ps
T349 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2130291218 Jun 27 06:09:29 PM PDT 24 Jun 27 06:09:33 PM PDT 24 276944792 ps
T350 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3007861547 Jun 27 06:08:42 PM PDT 24 Jun 27 06:08:45 PM PDT 24 424467219 ps
T351 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.534716530 Jun 27 06:08:40 PM PDT 24 Jun 27 06:08:44 PM PDT 24 396948123 ps
T352 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2053290688 Jun 27 06:08:57 PM PDT 24 Jun 27 06:09:00 PM PDT 24 324579222 ps
T353 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4024011468 Jun 27 06:08:45 PM PDT 24 Jun 27 06:08:48 PM PDT 24 391009133 ps
T354 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4227525044 Jun 27 06:08:39 PM PDT 24 Jun 27 06:08:48 PM PDT 24 13949563473 ps
T191 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3152424520 Jun 27 06:08:55 PM PDT 24 Jun 27 06:09:00 PM PDT 24 8162904569 ps
T355 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3647637889 Jun 27 06:09:12 PM PDT 24 Jun 27 06:09:14 PM PDT 24 474550371 ps
T356 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4234147359 Jun 27 06:08:38 PM PDT 24 Jun 27 06:08:41 PM PDT 24 848142716 ps
T357 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2407197717 Jun 27 06:08:54 PM PDT 24 Jun 27 06:08:56 PM PDT 24 444784643 ps
T358 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.996423160 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:13 PM PDT 24 2266619579 ps
T186 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.61936641 Jun 27 06:08:53 PM PDT 24 Jun 27 06:08:57 PM PDT 24 4353728246 ps
T359 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2381035741 Jun 27 06:08:57 PM PDT 24 Jun 27 06:09:03 PM PDT 24 4867016273 ps
T360 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3956480278 Jun 27 06:08:43 PM PDT 24 Jun 27 06:08:48 PM PDT 24 953028991 ps
T361 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2441194615 Jun 27 06:09:02 PM PDT 24 Jun 27 06:09:05 PM PDT 24 2218105874 ps
T362 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2172272424 Jun 27 06:09:10 PM PDT 24 Jun 27 06:09:13 PM PDT 24 349762877 ps
T363 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3420479336 Jun 27 06:09:08 PM PDT 24 Jun 27 06:09:11 PM PDT 24 478581372 ps
T364 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3076317973 Jun 27 06:08:59 PM PDT 24 Jun 27 06:09:01 PM PDT 24 312972333 ps
T365 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1870259707 Jun 27 06:08:53 PM PDT 24 Jun 27 06:08:55 PM PDT 24 327716560 ps
T366 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.810898470 Jun 27 06:09:10 PM PDT 24 Jun 27 06:09:19 PM PDT 24 4019725957 ps
T367 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3406623677 Jun 27 06:09:18 PM PDT 24 Jun 27 06:09:20 PM PDT 24 341255436 ps
T368 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3844624021 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:12 PM PDT 24 332673218 ps
T369 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3086294074 Jun 27 06:08:54 PM PDT 24 Jun 27 06:08:57 PM PDT 24 423365054 ps
T370 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1411919037 Jun 27 06:09:19 PM PDT 24 Jun 27 06:09:21 PM PDT 24 366641177 ps
T371 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.173254253 Jun 27 06:09:00 PM PDT 24 Jun 27 06:09:03 PM PDT 24 602133213 ps
T372 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3309864754 Jun 27 06:08:54 PM PDT 24 Jun 27 06:08:56 PM PDT 24 434700185 ps
T373 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2862644367 Jun 27 06:08:37 PM PDT 24 Jun 27 06:08:40 PM PDT 24 490683232 ps
T374 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3346734532 Jun 27 06:09:17 PM PDT 24 Jun 27 06:09:19 PM PDT 24 454365987 ps
T375 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.517203718 Jun 27 06:09:18 PM PDT 24 Jun 27 06:09:20 PM PDT 24 483704813 ps
T376 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.87445867 Jun 27 06:08:42 PM PDT 24 Jun 27 06:08:48 PM PDT 24 2156700889 ps
T377 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.268898237 Jun 27 06:09:07 PM PDT 24 Jun 27 06:09:09 PM PDT 24 366227729 ps
T378 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.891615118 Jun 27 06:08:38 PM PDT 24 Jun 27 06:08:40 PM PDT 24 517903784 ps
T379 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4104477126 Jun 27 06:08:38 PM PDT 24 Jun 27 06:08:40 PM PDT 24 404995548 ps
T380 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1535493124 Jun 27 06:08:52 PM PDT 24 Jun 27 06:08:56 PM PDT 24 998459938 ps
T381 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1555996969 Jun 27 06:08:40 PM PDT 24 Jun 27 06:08:44 PM PDT 24 488628752 ps
T382 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1337459458 Jun 27 06:08:40 PM PDT 24 Jun 27 06:08:42 PM PDT 24 275868832 ps
T383 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4294966160 Jun 27 06:08:41 PM PDT 24 Jun 27 06:08:45 PM PDT 24 469188562 ps
T384 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2486571639 Jun 27 06:08:39 PM PDT 24 Jun 27 06:08:41 PM PDT 24 415354930 ps
T385 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1387259967 Jun 27 06:09:08 PM PDT 24 Jun 27 06:09:10 PM PDT 24 394258856 ps
T192 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2560714810 Jun 27 06:08:36 PM PDT 24 Jun 27 06:08:42 PM PDT 24 8834411797 ps
T386 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.844527397 Jun 27 06:09:10 PM PDT 24 Jun 27 06:09:13 PM PDT 24 432871424 ps
T387 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.4256895392 Jun 27 06:09:18 PM PDT 24 Jun 27 06:09:20 PM PDT 24 509831996 ps
T388 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1702013512 Jun 27 06:09:18 PM PDT 24 Jun 27 06:09:20 PM PDT 24 465332269 ps
T389 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2642477956 Jun 27 06:09:11 PM PDT 24 Jun 27 06:09:16 PM PDT 24 519751838 ps
T390 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1369466269 Jun 27 06:08:39 PM PDT 24 Jun 27 06:08:44 PM PDT 24 9162174430 ps
T391 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2638119397 Jun 27 06:09:02 PM PDT 24 Jun 27 06:09:07 PM PDT 24 2083188304 ps
T392 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.359011563 Jun 27 06:08:54 PM PDT 24 Jun 27 06:08:58 PM PDT 24 539939080 ps
T393 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.697593842 Jun 27 06:09:08 PM PDT 24 Jun 27 06:09:10 PM PDT 24 449828469 ps
T187 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.769245231 Jun 27 06:08:54 PM PDT 24 Jun 27 06:09:03 PM PDT 24 8370546198 ps
T394 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1881983923 Jun 27 06:09:08 PM PDT 24 Jun 27 06:09:13 PM PDT 24 9393251798 ps
T59 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3601041523 Jun 27 06:08:41 PM PDT 24 Jun 27 06:08:49 PM PDT 24 5099159734 ps
T395 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3911829110 Jun 27 06:09:01 PM PDT 24 Jun 27 06:09:05 PM PDT 24 336381915 ps
T396 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3579101206 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:18 PM PDT 24 4215511644 ps
T60 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.482498227 Jun 27 06:08:40 PM PDT 24 Jun 27 06:08:45 PM PDT 24 278167469 ps
T397 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3973023729 Jun 27 06:08:52 PM PDT 24 Jun 27 06:08:57 PM PDT 24 8226196542 ps
T398 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.470146657 Jun 27 06:08:56 PM PDT 24 Jun 27 06:08:59 PM PDT 24 549515988 ps
T399 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1983367469 Jun 27 06:09:01 PM PDT 24 Jun 27 06:09:05 PM PDT 24 410359164 ps
T400 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1287704144 Jun 27 06:08:40 PM PDT 24 Jun 27 06:08:45 PM PDT 24 505911065 ps
T401 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2451210686 Jun 27 06:09:02 PM PDT 24 Jun 27 06:09:05 PM PDT 24 4483495167 ps
T402 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.780477996 Jun 27 06:08:38 PM PDT 24 Jun 27 06:08:41 PM PDT 24 492548305 ps
T403 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.229131719 Jun 27 06:08:38 PM PDT 24 Jun 27 06:08:42 PM PDT 24 390671871 ps
T404 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.637432441 Jun 27 06:09:02 PM PDT 24 Jun 27 06:09:04 PM PDT 24 771328961 ps
T405 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2379141730 Jun 27 06:09:02 PM PDT 24 Jun 27 06:09:10 PM PDT 24 2677371298 ps
T406 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2074116853 Jun 27 06:09:10 PM PDT 24 Jun 27 06:09:16 PM PDT 24 2522525096 ps
T407 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3938594372 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:13 PM PDT 24 360403366 ps
T408 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2798795129 Jun 27 06:08:52 PM PDT 24 Jun 27 06:08:55 PM PDT 24 1054070194 ps
T409 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2874753920 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:12 PM PDT 24 463986454 ps
T410 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3412328239 Jun 27 06:08:38 PM PDT 24 Jun 27 06:08:42 PM PDT 24 465223545 ps
T411 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2374964574 Jun 27 06:08:54 PM PDT 24 Jun 27 06:08:56 PM PDT 24 574349584 ps
T412 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3892003336 Jun 27 06:08:39 PM PDT 24 Jun 27 06:08:41 PM PDT 24 482796320 ps
T413 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2271887276 Jun 27 06:09:02 PM PDT 24 Jun 27 06:09:05 PM PDT 24 466516068 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3632839793 Jun 27 06:08:42 PM PDT 24 Jun 27 06:08:46 PM PDT 24 543150056 ps
T415 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.439801454 Jun 27 06:08:56 PM PDT 24 Jun 27 06:08:59 PM PDT 24 448550414 ps
T416 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1613296195 Jun 27 06:09:08 PM PDT 24 Jun 27 06:09:11 PM PDT 24 421734071 ps
T417 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3363824423 Jun 27 06:08:52 PM PDT 24 Jun 27 06:08:55 PM PDT 24 518603393 ps
T418 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.184369603 Jun 27 06:09:18 PM PDT 24 Jun 27 06:09:22 PM PDT 24 1744007880 ps
T419 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3038793480 Jun 27 06:09:09 PM PDT 24 Jun 27 06:09:12 PM PDT 24 287923930 ps
T420 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3201314608 Jun 27 06:09:00 PM PDT 24 Jun 27 06:09:05 PM PDT 24 2009356313 ps

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1759890015
Short name T7
Test name
Test status
Simulation time 67914490235 ps
CPU time 469.17 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:11:31 PM PDT 24
Peak memory 214256 kb
Host smart-db10ee45-7c10-4241-adc2-ffcb46b7557a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759890015 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1759890015
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.850622512
Short name T23
Test name
Test status
Simulation time 4494048339 ps
CPU time 2.51 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:46 PM PDT 24
Peak memory 197900 kb
Host smart-ea4b0a94-ef8b-4bf0-9f08-13a04d26ccd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850622512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.850622512
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.186090768
Short name T3
Test name
Test status
Simulation time 425191123180 ps
CPU time 912.32 seconds
Started Jun 27 06:03:36 PM PDT 24
Finished Jun 27 06:18:52 PM PDT 24
Peak memory 214836 kb
Host smart-e3de5993-20a4-4589-b34e-f7258926bc79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186090768 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.186090768
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1966213442
Short name T29
Test name
Test status
Simulation time 182275600149 ps
CPU time 320.13 seconds
Started Jun 27 06:04:11 PM PDT 24
Finished Jun 27 06:09:33 PM PDT 24
Peak memory 206548 kb
Host smart-80231e06-ba04-46fa-b5d4-8feb475b5b2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966213442 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1966213442
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3430977077
Short name T50
Test name
Test status
Simulation time 587909004480 ps
CPU time 727.15 seconds
Started Jun 27 06:03:36 PM PDT 24
Finished Jun 27 06:15:46 PM PDT 24
Peak memory 207208 kb
Host smart-bbcb3589-0127-48a6-9a63-5e50585badf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430977077 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3430977077
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.715007244
Short name T136
Test name
Test status
Simulation time 439639617282 ps
CPU time 602.08 seconds
Started Jun 27 06:03:12 PM PDT 24
Finished Jun 27 06:13:16 PM PDT 24
Peak memory 206816 kb
Host smart-000e21e0-268c-4f09-95e9-60e5c4bfb60f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715007244 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.715007244
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3652604381
Short name T8
Test name
Test status
Simulation time 297400707429 ps
CPU time 304.99 seconds
Started Jun 27 06:02:53 PM PDT 24
Finished Jun 27 06:07:59 PM PDT 24
Peak memory 191744 kb
Host smart-f0e5a579-5b4a-4d02-b712-5879bab622ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652604381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3652604381
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.392812466
Short name T100
Test name
Test status
Simulation time 223698167400 ps
CPU time 571.08 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:13:32 PM PDT 24
Peak memory 205144 kb
Host smart-e7aafb2e-d35d-42aa-bc76-fe9476d328ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392812466 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.392812466
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3222376584
Short name T82
Test name
Test status
Simulation time 246576965078 ps
CPU time 419.26 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:10:59 PM PDT 24
Peak memory 202708 kb
Host smart-cb66ea1c-3995-49fc-863f-1225288e678a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222376584 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3222376584
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1509256358
Short name T79
Test name
Test status
Simulation time 389941515650 ps
CPU time 703.73 seconds
Started Jun 27 06:02:56 PM PDT 24
Finished Jun 27 06:14:42 PM PDT 24
Peak memory 206068 kb
Host smart-19aacab4-775f-4b8a-a9b8-df6e765c9177
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509256358 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1509256358
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.881167492
Short name T27
Test name
Test status
Simulation time 446053016 ps
CPU time 0.73 seconds
Started Jun 27 06:08:52 PM PDT 24
Finished Jun 27 06:08:54 PM PDT 24
Peak memory 193052 kb
Host smart-313f45c0-0ce1-40b0-b226-4ac79d002700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881167492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.881167492
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3339869338
Short name T153
Test name
Test status
Simulation time 191160040914 ps
CPU time 1025.01 seconds
Started Jun 27 06:03:58 PM PDT 24
Finished Jun 27 06:21:07 PM PDT 24
Peak memory 209824 kb
Host smart-7d64a6af-62c8-488c-98b7-34352ac08b3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339869338 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3339869338
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2779827519
Short name T4
Test name
Test status
Simulation time 7455005875 ps
CPU time 5.21 seconds
Started Jun 27 06:02:52 PM PDT 24
Finished Jun 27 06:02:58 PM PDT 24
Peak memory 215840 kb
Host smart-85b7e746-fff1-423d-8dc5-4694439c8487
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779827519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2779827519
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3464790773
Short name T101
Test name
Test status
Simulation time 170328536052 ps
CPU time 945.63 seconds
Started Jun 27 06:03:33 PM PDT 24
Finished Jun 27 06:19:21 PM PDT 24
Peak memory 214784 kb
Host smart-7da39039-4ddf-4358-b0f7-c15315bbf8ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464790773 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3464790773
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.618749521
Short name T78
Test name
Test status
Simulation time 338552015891 ps
CPU time 805.85 seconds
Started Jun 27 06:04:13 PM PDT 24
Finished Jun 27 06:17:41 PM PDT 24
Peak memory 207388 kb
Host smart-ac8661b2-59ff-47cb-8cb2-1e034e6ebd7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618749521 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.618749521
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.4212353215
Short name T92
Test name
Test status
Simulation time 433385544041 ps
CPU time 278.01 seconds
Started Jun 27 06:04:17 PM PDT 24
Finished Jun 27 06:08:57 PM PDT 24
Peak memory 197928 kb
Host smart-5059600d-f8ea-45bf-b5bd-f90f4dc320e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212353215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.4212353215
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2605930771
Short name T42
Test name
Test status
Simulation time 60348920585 ps
CPU time 252.57 seconds
Started Jun 27 06:03:56 PM PDT 24
Finished Jun 27 06:08:11 PM PDT 24
Peak memory 214096 kb
Host smart-ad220117-718b-4564-ae8f-732872d4393f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605930771 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2605930771
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3714050834
Short name T131
Test name
Test status
Simulation time 97259790814 ps
CPU time 141.89 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:06:22 PM PDT 24
Peak memory 192816 kb
Host smart-5ca26ff1-be7a-4a90-951b-c5db1fc03035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714050834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3714050834
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.294552121
Short name T83
Test name
Test status
Simulation time 31442557619 ps
CPU time 226.47 seconds
Started Jun 27 06:03:33 PM PDT 24
Finished Jun 27 06:07:21 PM PDT 24
Peak memory 198380 kb
Host smart-744f9389-3ba4-4908-853f-0e5b055beab3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294552121 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.294552121
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2287898264
Short name T93
Test name
Test status
Simulation time 14790746086 ps
CPU time 114.3 seconds
Started Jun 27 06:04:12 PM PDT 24
Finished Jun 27 06:06:08 PM PDT 24
Peak memory 206664 kb
Host smart-d049e9a8-59d5-4ca7-adfc-5caa329a04c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287898264 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2287898264
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2224240538
Short name T91
Test name
Test status
Simulation time 121866340918 ps
CPU time 267.66 seconds
Started Jun 27 06:03:33 PM PDT 24
Finished Jun 27 06:08:04 PM PDT 24
Peak memory 209364 kb
Host smart-09582ac3-971a-4734-af0e-29e76cb5b372
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224240538 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2224240538
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2421818584
Short name T107
Test name
Test status
Simulation time 33575799451 ps
CPU time 268.79 seconds
Started Jun 27 06:03:12 PM PDT 24
Finished Jun 27 06:07:43 PM PDT 24
Peak memory 214536 kb
Host smart-1f2fc554-c522-4a52-9012-b8586d5f2d5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421818584 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2421818584
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3154811584
Short name T96
Test name
Test status
Simulation time 42831461970 ps
CPU time 34.76 seconds
Started Jun 27 06:03:33 PM PDT 24
Finished Jun 27 06:04:09 PM PDT 24
Peak memory 184524 kb
Host smart-aa8109dd-ccf8-4ba3-8579-a6eab3fe433f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154811584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3154811584
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.485188576
Short name T108
Test name
Test status
Simulation time 277120631050 ps
CPU time 195.02 seconds
Started Jun 27 06:03:33 PM PDT 24
Finished Jun 27 06:06:49 PM PDT 24
Peak memory 192744 kb
Host smart-71168966-d67a-4d19-b287-7de35f4ee1d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485188576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.485188576
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.4185620307
Short name T28
Test name
Test status
Simulation time 140918238155 ps
CPU time 280.57 seconds
Started Jun 27 06:03:16 PM PDT 24
Finished Jun 27 06:08:00 PM PDT 24
Peak memory 206680 kb
Host smart-3987550e-29d8-4ded-bac8-d125ae28ece7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185620307 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.4185620307
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2577630129
Short name T30
Test name
Test status
Simulation time 48422997009 ps
CPU time 500.25 seconds
Started Jun 27 06:03:36 PM PDT 24
Finished Jun 27 06:12:01 PM PDT 24
Peak memory 201260 kb
Host smart-c5cd7d72-b86e-4777-b6ed-614f10646abe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577630129 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2577630129
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.125803953
Short name T89
Test name
Test status
Simulation time 20191528437 ps
CPU time 216.43 seconds
Started Jun 27 06:02:53 PM PDT 24
Finished Jun 27 06:06:30 PM PDT 24
Peak memory 206608 kb
Host smart-09f939a9-170e-4cd7-892a-47150a889ae6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125803953 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.125803953
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.954430915
Short name T116
Test name
Test status
Simulation time 207760947107 ps
CPU time 314.51 seconds
Started Jun 27 06:03:14 PM PDT 24
Finished Jun 27 06:08:31 PM PDT 24
Peak memory 192800 kb
Host smart-1009691a-4b6d-44de-a08b-b7429af9cdc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954430915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.954430915
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1020542763
Short name T12
Test name
Test status
Simulation time 380080523016 ps
CPU time 101.15 seconds
Started Jun 27 06:03:36 PM PDT 24
Finished Jun 27 06:05:21 PM PDT 24
Peak memory 192828 kb
Host smart-2b0ad8b5-9344-4dee-b22b-c66fd4eb4999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020542763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1020542763
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.22531224
Short name T104
Test name
Test status
Simulation time 53348845560 ps
CPU time 82.25 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:05:22 PM PDT 24
Peak memory 183972 kb
Host smart-7ab22150-e249-4288-9731-ed67a0b143fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22531224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_al
l.22531224
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3478839485
Short name T102
Test name
Test status
Simulation time 103944810585 ps
CPU time 24.54 seconds
Started Jun 27 06:02:55 PM PDT 24
Finished Jun 27 06:03:21 PM PDT 24
Peak memory 192824 kb
Host smart-164c476f-8e03-469f-a45f-7baff43dd8f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478839485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3478839485
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3843180307
Short name T97
Test name
Test status
Simulation time 49831983600 ps
CPU time 276.49 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:08:18 PM PDT 24
Peak memory 198648 kb
Host smart-f0b0eafd-5a17-4141-8090-ca754a2570e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843180307 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3843180307
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2407118206
Short name T6
Test name
Test status
Simulation time 546103263336 ps
CPU time 1057.72 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:21:38 PM PDT 24
Peak memory 211624 kb
Host smart-c7c3f271-9b4e-4d6b-8611-a08db7beb022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407118206 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2407118206
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1353221513
Short name T117
Test name
Test status
Simulation time 71347545148 ps
CPU time 23.82 seconds
Started Jun 27 06:03:17 PM PDT 24
Finished Jun 27 06:03:45 PM PDT 24
Peak memory 192652 kb
Host smart-1c4d716e-6c71-4ecd-8d5c-a5d2be66ef33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353221513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1353221513
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.4097634775
Short name T159
Test name
Test status
Simulation time 78519527247 ps
CPU time 608.41 seconds
Started Jun 27 06:03:32 PM PDT 24
Finished Jun 27 06:13:42 PM PDT 24
Peak memory 214248 kb
Host smart-ae02f643-ac29-4b33-9d32-e3311c172dc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097634775 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.4097634775
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1303838351
Short name T126
Test name
Test status
Simulation time 104391535310 ps
CPU time 78.9 seconds
Started Jun 27 06:02:57 PM PDT 24
Finished Jun 27 06:04:18 PM PDT 24
Peak memory 198036 kb
Host smart-ac55b29b-75df-4ac8-8d58-312659894e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303838351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1303838351
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3801062615
Short name T147
Test name
Test status
Simulation time 398264404799 ps
CPU time 367.6 seconds
Started Jun 27 06:03:54 PM PDT 24
Finished Jun 27 06:10:03 PM PDT 24
Peak memory 211008 kb
Host smart-043b4941-a922-4ffe-a151-c49b081745fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801062615 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3801062615
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.806461277
Short name T105
Test name
Test status
Simulation time 12677636892 ps
CPU time 10.11 seconds
Started Jun 27 06:03:38 PM PDT 24
Finished Jun 27 06:03:52 PM PDT 24
Peak memory 192256 kb
Host smart-9eec410b-f515-48e2-9523-51682a5dd07f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806461277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.806461277
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3995919025
Short name T129
Test name
Test status
Simulation time 7899722391 ps
CPU time 3.44 seconds
Started Jun 27 06:03:34 PM PDT 24
Finished Jun 27 06:03:41 PM PDT 24
Peak memory 191652 kb
Host smart-1e660505-4f9d-4bf3-a0d8-a3fee9d8164b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995919025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3995919025
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3491354122
Short name T67
Test name
Test status
Simulation time 223116864629 ps
CPU time 463.59 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:11:44 PM PDT 24
Peak memory 211904 kb
Host smart-a16fe513-012e-4e8a-ad49-c71137c54fe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491354122 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3491354122
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.689584556
Short name T122
Test name
Test status
Simulation time 51587351489 ps
CPU time 126.31 seconds
Started Jun 27 06:04:12 PM PDT 24
Finished Jun 27 06:06:21 PM PDT 24
Peak memory 213796 kb
Host smart-8ba3824e-241b-4414-9f94-675110707e74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689584556 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.689584556
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.599222018
Short name T149
Test name
Test status
Simulation time 248085523553 ps
CPU time 79.48 seconds
Started Jun 27 06:04:11 PM PDT 24
Finished Jun 27 06:05:33 PM PDT 24
Peak memory 191728 kb
Host smart-ef7832a9-89a9-476a-b8d6-8bf3e9cf8518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599222018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.599222018
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2837780008
Short name T80
Test name
Test status
Simulation time 232980364704 ps
CPU time 433.2 seconds
Started Jun 27 06:03:15 PM PDT 24
Finished Jun 27 06:10:32 PM PDT 24
Peak memory 211000 kb
Host smart-3763fe13-a729-4c57-97c9-d3601251b5d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837780008 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2837780008
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3120121481
Short name T118
Test name
Test status
Simulation time 138394167878 ps
CPU time 39.59 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:04:20 PM PDT 24
Peak memory 198256 kb
Host smart-1a743275-21e2-47e7-b00a-8024b9b0952b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120121481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3120121481
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2532297614
Short name T132
Test name
Test status
Simulation time 49785065022 ps
CPU time 31.19 seconds
Started Jun 27 06:03:55 PM PDT 24
Finished Jun 27 06:04:28 PM PDT 24
Peak memory 191772 kb
Host smart-e361dd30-494e-4335-9ce8-f633e2d49261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532297614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2532297614
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3134931173
Short name T62
Test name
Test status
Simulation time 274339329751 ps
CPU time 343.49 seconds
Started Jun 27 06:02:57 PM PDT 24
Finished Jun 27 06:08:42 PM PDT 24
Peak memory 192840 kb
Host smart-a4417095-930c-496a-b424-839471e13dc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134931173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3134931173
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1909321880
Short name T111
Test name
Test status
Simulation time 121165231070 ps
CPU time 161.58 seconds
Started Jun 27 06:03:56 PM PDT 24
Finished Jun 27 06:06:40 PM PDT 24
Peak memory 192764 kb
Host smart-d854b11e-5d46-4493-aa8e-cc92639b3359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909321880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1909321880
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2592855815
Short name T145
Test name
Test status
Simulation time 411774492299 ps
CPU time 544.91 seconds
Started Jun 27 06:03:58 PM PDT 24
Finished Jun 27 06:13:06 PM PDT 24
Peak memory 192612 kb
Host smart-6b908db2-9a0b-4b80-8235-2f9b766437a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592855815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2592855815
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3684314732
Short name T120
Test name
Test status
Simulation time 181312074185 ps
CPU time 147.85 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:06:28 PM PDT 24
Peak memory 192768 kb
Host smart-a0267ce8-1436-486d-b34a-5a4e2a611814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684314732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3684314732
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.184545602
Short name T34
Test name
Test status
Simulation time 247314040116 ps
CPU time 48.88 seconds
Started Jun 27 06:04:18 PM PDT 24
Finished Jun 27 06:05:08 PM PDT 24
Peak memory 197940 kb
Host smart-eeec4677-e0c8-41ad-854f-a58763a2b77e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184545602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.184545602
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1612275809
Short name T81
Test name
Test status
Simulation time 221112100055 ps
CPU time 362.8 seconds
Started Jun 27 06:04:11 PM PDT 24
Finished Jun 27 06:10:16 PM PDT 24
Peak memory 200820 kb
Host smart-236000e0-ced2-4df7-8701-8cf90ecc8735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612275809 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1612275809
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.818040333
Short name T123
Test name
Test status
Simulation time 23998032410 ps
CPU time 192.75 seconds
Started Jun 27 06:03:36 PM PDT 24
Finished Jun 27 06:06:52 PM PDT 24
Peak memory 198532 kb
Host smart-4a5b7c3f-19a4-4e63-ba6f-70af3829c6c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818040333 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.818040333
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1194482532
Short name T146
Test name
Test status
Simulation time 96659129363 ps
CPU time 62.26 seconds
Started Jun 27 06:03:34 PM PDT 24
Finished Jun 27 06:04:39 PM PDT 24
Peak memory 192784 kb
Host smart-554e98db-b0ad-423e-af46-268f4bc9c128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194482532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1194482532
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3164844401
Short name T106
Test name
Test status
Simulation time 156407659484 ps
CPU time 123.32 seconds
Started Jun 27 06:04:03 PM PDT 24
Finished Jun 27 06:06:08 PM PDT 24
Peak memory 192560 kb
Host smart-2f92c98b-99f1-453a-9133-8b8cba0814ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164844401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3164844401
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.774255299
Short name T150
Test name
Test status
Simulation time 195250630570 ps
CPU time 72.15 seconds
Started Jun 27 06:03:34 PM PDT 24
Finished Jun 27 06:04:49 PM PDT 24
Peak memory 192828 kb
Host smart-a3feb5f4-64b8-493e-952d-510aa1c92b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774255299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.774255299
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.60279681
Short name T84
Test name
Test status
Simulation time 152630950607 ps
CPU time 321.45 seconds
Started Jun 27 06:03:33 PM PDT 24
Finished Jun 27 06:08:56 PM PDT 24
Peak memory 214316 kb
Host smart-6b0f3887-1671-462d-b874-7d7256b8cd7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60279681 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.60279681
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1900523814
Short name T51
Test name
Test status
Simulation time 230890937278 ps
CPU time 441.88 seconds
Started Jun 27 06:03:34 PM PDT 24
Finished Jun 27 06:10:58 PM PDT 24
Peak memory 206672 kb
Host smart-1c17af59-5427-489c-aa06-92b9e1959e9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900523814 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1900523814
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3509980238
Short name T94
Test name
Test status
Simulation time 154935504462 ps
CPU time 201.55 seconds
Started Jun 27 06:04:00 PM PDT 24
Finished Jun 27 06:07:25 PM PDT 24
Peak memory 198040 kb
Host smart-8f90afa2-8425-4e03-9a5c-02042e940cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509980238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3509980238
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2070964335
Short name T90
Test name
Test status
Simulation time 69293284552 ps
CPU time 156.29 seconds
Started Jun 27 06:04:18 PM PDT 24
Finished Jun 27 06:06:56 PM PDT 24
Peak memory 206820 kb
Host smart-0b98f7c5-0cb9-4f7f-ba4f-60dd4826e5fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070964335 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2070964335
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1347572824
Short name T139
Test name
Test status
Simulation time 174529693269 ps
CPU time 56.14 seconds
Started Jun 27 06:04:15 PM PDT 24
Finished Jun 27 06:05:13 PM PDT 24
Peak memory 192736 kb
Host smart-ccd4f60b-1639-4001-9275-0f0307c9cb2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347572824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1347572824
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4117727079
Short name T43
Test name
Test status
Simulation time 103614927819 ps
CPU time 35.61 seconds
Started Jun 27 06:03:12 PM PDT 24
Finished Jun 27 06:03:48 PM PDT 24
Peak memory 198020 kb
Host smart-ec8b7ee5-2747-433d-9856-fd8ae6efd01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117727079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4117727079
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3866401146
Short name T125
Test name
Test status
Simulation time 65611198257 ps
CPU time 214.02 seconds
Started Jun 27 06:03:17 PM PDT 24
Finished Jun 27 06:06:56 PM PDT 24
Peak memory 207184 kb
Host smart-9dcb0d9b-eb91-452d-be84-917b9014595f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866401146 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3866401146
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.4242088053
Short name T11
Test name
Test status
Simulation time 40465444403 ps
CPU time 203.86 seconds
Started Jun 27 06:03:58 PM PDT 24
Finished Jun 27 06:07:25 PM PDT 24
Peak memory 198400 kb
Host smart-46f50559-8c1b-400e-af1b-105bf1d32707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242088053 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.4242088053
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2991025795
Short name T140
Test name
Test status
Simulation time 35204336321 ps
CPU time 202.04 seconds
Started Jun 27 06:02:55 PM PDT 24
Finished Jun 27 06:06:18 PM PDT 24
Peak memory 198424 kb
Host smart-2e39b7ec-06a5-43bd-81c4-79bf7056cd02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991025795 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2991025795
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3219648766
Short name T13
Test name
Test status
Simulation time 136174277748 ps
CPU time 200.66 seconds
Started Jun 27 06:04:17 PM PDT 24
Finished Jun 27 06:07:40 PM PDT 24
Peak memory 206560 kb
Host smart-76129d3d-8ad1-4414-b409-5b6bc5ab0595
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219648766 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3219648766
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3871372185
Short name T133
Test name
Test status
Simulation time 158902554384 ps
CPU time 302.86 seconds
Started Jun 27 06:03:14 PM PDT 24
Finished Jun 27 06:08:20 PM PDT 24
Peak memory 209968 kb
Host smart-a8a702d3-f23c-4f7f-86bd-12551b82e60e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871372185 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3871372185
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2368487010
Short name T66
Test name
Test status
Simulation time 28583628858 ps
CPU time 196.65 seconds
Started Jun 27 06:02:55 PM PDT 24
Finished Jun 27 06:06:14 PM PDT 24
Peak memory 198452 kb
Host smart-86afba3c-8d84-483c-b907-ce94aca92dd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368487010 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2368487010
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3029856683
Short name T98
Test name
Test status
Simulation time 159000546063 ps
CPU time 218.2 seconds
Started Jun 27 06:03:14 PM PDT 24
Finished Jun 27 06:06:55 PM PDT 24
Peak memory 197992 kb
Host smart-1af442d2-ca5f-46b3-ac4f-727f58e3b89b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029856683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3029856683
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1487487301
Short name T47
Test name
Test status
Simulation time 77724765005 ps
CPU time 574.92 seconds
Started Jun 27 06:03:17 PM PDT 24
Finished Jun 27 06:12:56 PM PDT 24
Peak memory 206624 kb
Host smart-86b6dea4-b487-4fbf-bf55-077de6c80646
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487487301 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1487487301
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1375955897
Short name T130
Test name
Test status
Simulation time 122452072301 ps
CPU time 40.18 seconds
Started Jun 27 06:03:34 PM PDT 24
Finished Jun 27 06:04:16 PM PDT 24
Peak memory 191696 kb
Host smart-bd45c6d2-25ff-438d-ba86-4d73d05d6dee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375955897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1375955897
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3327037442
Short name T14
Test name
Test status
Simulation time 486315675 ps
CPU time 0.79 seconds
Started Jun 27 06:03:35 PM PDT 24
Finished Jun 27 06:03:38 PM PDT 24
Peak memory 196300 kb
Host smart-5a60f8f9-1f8f-4f6c-a923-51002b6d56a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327037442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3327037442
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1325196219
Short name T137
Test name
Test status
Simulation time 514454859 ps
CPU time 0.8 seconds
Started Jun 27 06:04:12 PM PDT 24
Finished Jun 27 06:04:15 PM PDT 24
Peak memory 196436 kb
Host smart-bdcc0aad-df78-429f-affe-1e9a27e35fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325196219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1325196219
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1279541975
Short name T36
Test name
Test status
Simulation time 189258014789 ps
CPU time 34.66 seconds
Started Jun 27 06:03:35 PM PDT 24
Finished Jun 27 06:04:12 PM PDT 24
Peak memory 192516 kb
Host smart-72de80d6-09f2-4d93-81fa-6433ed4c7b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279541975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1279541975
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.437986805
Short name T114
Test name
Test status
Simulation time 588873706 ps
CPU time 0.96 seconds
Started Jun 27 06:03:55 PM PDT 24
Finished Jun 27 06:03:57 PM PDT 24
Peak memory 196512 kb
Host smart-db1f3dbf-3e67-438f-9ba7-6cd3fe769c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437986805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.437986805
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3555432849
Short name T134
Test name
Test status
Simulation time 378957919 ps
CPU time 0.87 seconds
Started Jun 27 06:03:16 PM PDT 24
Finished Jun 27 06:03:20 PM PDT 24
Peak memory 196516 kb
Host smart-fd862287-4010-46b8-b45e-30edcddb1d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555432849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3555432849
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1426834316
Short name T88
Test name
Test status
Simulation time 407263216 ps
CPU time 0.86 seconds
Started Jun 27 06:03:39 PM PDT 24
Finished Jun 27 06:03:44 PM PDT 24
Peak memory 196476 kb
Host smart-d36ae3a5-1e6d-44c5-8847-aba1802afb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426834316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1426834316
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3690149733
Short name T65
Test name
Test status
Simulation time 145308338087 ps
CPU time 47.6 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:04:29 PM PDT 24
Peak memory 184252 kb
Host smart-818a2ac2-b901-497f-8165-d728c2d56156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690149733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3690149733
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3065581846
Short name T151
Test name
Test status
Simulation time 492915808 ps
CPU time 1.32 seconds
Started Jun 27 06:02:53 PM PDT 24
Finished Jun 27 06:02:55 PM PDT 24
Peak memory 196492 kb
Host smart-a22d7201-ac3c-47a4-a0a7-91a8542f5da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065581846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3065581846
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2874503334
Short name T95
Test name
Test status
Simulation time 483610436 ps
CPU time 0.79 seconds
Started Jun 27 06:03:36 PM PDT 24
Finished Jun 27 06:03:40 PM PDT 24
Peak memory 196496 kb
Host smart-4c9e991f-be70-4b2c-b770-e4407609abbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874503334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2874503334
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.329966131
Short name T144
Test name
Test status
Simulation time 402935500 ps
CPU time 1.18 seconds
Started Jun 27 06:04:13 PM PDT 24
Finished Jun 27 06:04:16 PM PDT 24
Peak memory 196456 kb
Host smart-db33aa0d-ae0a-4d81-b3c4-16ffdb023787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329966131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.329966131
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1252970333
Short name T112
Test name
Test status
Simulation time 584411677 ps
CPU time 1.51 seconds
Started Jun 27 06:02:54 PM PDT 24
Finished Jun 27 06:02:57 PM PDT 24
Peak memory 196392 kb
Host smart-c9007850-766e-4529-ba1f-cb473e5c7c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252970333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1252970333
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.167208644
Short name T135
Test name
Test status
Simulation time 85885399506 ps
CPU time 91.02 seconds
Started Jun 27 06:03:13 PM PDT 24
Finished Jun 27 06:04:46 PM PDT 24
Peak memory 191688 kb
Host smart-6de9dcc0-1f10-4b8d-945a-84f9912174eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167208644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.167208644
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1027504751
Short name T68
Test name
Test status
Simulation time 261673720785 ps
CPU time 181.65 seconds
Started Jun 27 06:03:12 PM PDT 24
Finished Jun 27 06:06:16 PM PDT 24
Peak memory 191720 kb
Host smart-0008206a-12e7-4063-bb7b-0338d80dbb90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027504751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1027504751
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2796096706
Short name T103
Test name
Test status
Simulation time 486630695 ps
CPU time 0.74 seconds
Started Jun 27 06:02:55 PM PDT 24
Finished Jun 27 06:02:58 PM PDT 24
Peak memory 196500 kb
Host smart-4ce085e2-0641-4fbb-b08a-6e462b6ca5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796096706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2796096706
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2691451858
Short name T115
Test name
Test status
Simulation time 388718445 ps
CPU time 1.12 seconds
Started Jun 27 06:03:43 PM PDT 24
Finished Jun 27 06:03:46 PM PDT 24
Peak memory 196392 kb
Host smart-eac23d45-138a-4a5e-b30b-9fd54a53bc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691451858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2691451858
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1810771391
Short name T121
Test name
Test status
Simulation time 442032060 ps
CPU time 0.93 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:03:43 PM PDT 24
Peak memory 196700 kb
Host smart-3bb9ec39-b274-4cfc-85b0-cc31477f614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810771391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1810771391
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3364857938
Short name T143
Test name
Test status
Simulation time 392233355 ps
CPU time 0.67 seconds
Started Jun 27 06:03:56 PM PDT 24
Finished Jun 27 06:03:58 PM PDT 24
Peak memory 196428 kb
Host smart-9ccdc218-2e2f-4d08-ac2c-515aa8fc2eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364857938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3364857938
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3186819033
Short name T35
Test name
Test status
Simulation time 54911365814 ps
CPU time 72.75 seconds
Started Jun 27 06:03:56 PM PDT 24
Finished Jun 27 06:05:10 PM PDT 24
Peak memory 192828 kb
Host smart-8a6820d5-fb8c-47fa-bbbd-153f40166c4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186819033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3186819033
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2933336285
Short name T128
Test name
Test status
Simulation time 531301724 ps
CPU time 0.8 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:01 PM PDT 24
Peak memory 196528 kb
Host smart-78218570-5e84-4a6c-9bc4-d788c88defaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933336285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2933336285
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.202735587
Short name T158
Test name
Test status
Simulation time 90634934883 ps
CPU time 135.84 seconds
Started Jun 27 06:04:14 PM PDT 24
Finished Jun 27 06:06:32 PM PDT 24
Peak memory 191968 kb
Host smart-ecf57403-f9ad-4d3d-b178-6d3565a883fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202735587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.202735587
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3505374524
Short name T2
Test name
Test status
Simulation time 406242352 ps
CPU time 1.14 seconds
Started Jun 27 06:04:11 PM PDT 24
Finished Jun 27 06:04:14 PM PDT 24
Peak memory 196440 kb
Host smart-fc4e4187-6cdf-446a-943a-789b9be95135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505374524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3505374524
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3565909600
Short name T124
Test name
Test status
Simulation time 83669471475 ps
CPU time 158.78 seconds
Started Jun 27 06:03:34 PM PDT 24
Finished Jun 27 06:06:16 PM PDT 24
Peak memory 213996 kb
Host smart-31957b23-d7ea-4d70-beee-6c5f3a1f4f17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565909600 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3565909600
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3502130622
Short name T152
Test name
Test status
Simulation time 494641308 ps
CPU time 0.94 seconds
Started Jun 27 06:03:41 PM PDT 24
Finished Jun 27 06:03:45 PM PDT 24
Peak memory 196492 kb
Host smart-98799e12-60c9-4d02-9611-e9ac0034ff2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502130622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3502130622
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2193593712
Short name T141
Test name
Test status
Simulation time 132772262986 ps
CPU time 49.37 seconds
Started Jun 27 06:03:41 PM PDT 24
Finished Jun 27 06:04:33 PM PDT 24
Peak memory 191732 kb
Host smart-1bacc12d-d75f-44fb-bcb3-9fa9902f3732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193593712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2193593712
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1105958457
Short name T113
Test name
Test status
Simulation time 501443562 ps
CPU time 1 seconds
Started Jun 27 06:03:55 PM PDT 24
Finished Jun 27 06:03:57 PM PDT 24
Peak memory 196488 kb
Host smart-1b77da0b-0566-4dec-ab01-69d24c2041ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105958457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1105958457
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1899804183
Short name T138
Test name
Test status
Simulation time 420895587 ps
CPU time 0.73 seconds
Started Jun 27 06:03:58 PM PDT 24
Finished Jun 27 06:04:01 PM PDT 24
Peak memory 196468 kb
Host smart-408e260f-0fb6-4282-b912-00523d78a3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899804183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1899804183
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.711492002
Short name T5
Test name
Test status
Simulation time 213787494271 ps
CPU time 336.56 seconds
Started Jun 27 06:04:03 PM PDT 24
Finished Jun 27 06:09:42 PM PDT 24
Peak memory 198004 kb
Host smart-fbd8074b-6e02-4fe4-8972-2edc1c445c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711492002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.711492002
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2255069245
Short name T110
Test name
Test status
Simulation time 415248680 ps
CPU time 1.29 seconds
Started Jun 27 06:04:12 PM PDT 24
Finished Jun 27 06:04:15 PM PDT 24
Peak memory 196592 kb
Host smart-d0df7727-ed39-4c6a-862e-e72eabde808c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255069245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2255069245
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.4092151836
Short name T178
Test name
Test status
Simulation time 611670264 ps
CPU time 1.39 seconds
Started Jun 27 06:03:36 PM PDT 24
Finished Jun 27 06:03:42 PM PDT 24
Peak memory 196576 kb
Host smart-7fa0c7f4-69b9-481b-9251-aaf0184cb2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092151836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.4092151836
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1423491006
Short name T183
Test name
Test status
Simulation time 486191244 ps
CPU time 1.09 seconds
Started Jun 27 06:03:39 PM PDT 24
Finished Jun 27 06:03:44 PM PDT 24
Peak memory 196296 kb
Host smart-ce53fbfa-882e-4cb0-8634-5d964dd7ae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423491006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1423491006
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2445694587
Short name T142
Test name
Test status
Simulation time 363848914 ps
CPU time 0.86 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:01 PM PDT 24
Peak memory 196476 kb
Host smart-1f481584-83e6-4931-a661-77b235e8120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445694587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2445694587
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2444696497
Short name T154
Test name
Test status
Simulation time 118719826286 ps
CPU time 35.42 seconds
Started Jun 27 06:04:12 PM PDT 24
Finished Jun 27 06:04:50 PM PDT 24
Peak memory 198020 kb
Host smart-52820a1d-1d46-4d43-8c8f-1d19600d44e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444696497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2444696497
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.769245231
Short name T187
Test name
Test status
Simulation time 8370546198 ps
CPU time 7.25 seconds
Started Jun 27 06:08:54 PM PDT 24
Finished Jun 27 06:09:03 PM PDT 24
Peak memory 198280 kb
Host smart-e7c35ad2-338e-444e-be10-31c83f6b6038
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769245231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.769245231
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1431694630
Short name T109
Test name
Test status
Simulation time 378039428 ps
CPU time 0.83 seconds
Started Jun 27 06:03:14 PM PDT 24
Finished Jun 27 06:03:18 PM PDT 24
Peak memory 196416 kb
Host smart-cbf00d62-e7ab-4aec-b59c-676bc69fa433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431694630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1431694630
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.595251837
Short name T173
Test name
Test status
Simulation time 375413414458 ps
CPU time 450.42 seconds
Started Jun 27 06:03:17 PM PDT 24
Finished Jun 27 06:10:52 PM PDT 24
Peak memory 191724 kb
Host smart-ee29781a-44e4-4856-a763-7165102b6daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595251837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.595251837
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3118023998
Short name T40
Test name
Test status
Simulation time 512727444 ps
CPU time 0.79 seconds
Started Jun 27 06:03:34 PM PDT 24
Finished Jun 27 06:03:37 PM PDT 24
Peak memory 196420 kb
Host smart-5ffc152a-5fac-4786-aa81-a5aea08d9de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118023998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3118023998
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3531294214
Short name T161
Test name
Test status
Simulation time 588190525 ps
CPU time 0.84 seconds
Started Jun 27 06:03:36 PM PDT 24
Finished Jun 27 06:03:40 PM PDT 24
Peak memory 196568 kb
Host smart-57b44504-c934-4c9c-9bbb-b113c4a7cb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531294214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3531294214
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1504995686
Short name T119
Test name
Test status
Simulation time 71228339426 ps
CPU time 25.26 seconds
Started Jun 27 06:03:36 PM PDT 24
Finished Jun 27 06:04:06 PM PDT 24
Peak memory 192504 kb
Host smart-af8666a4-f028-44f7-a5a8-41deeea10fd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504995686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1504995686
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4227241979
Short name T157
Test name
Test status
Simulation time 723752844 ps
CPU time 0.67 seconds
Started Jun 27 06:03:38 PM PDT 24
Finished Jun 27 06:03:43 PM PDT 24
Peak memory 196500 kb
Host smart-01b328d7-e8c6-4d46-ab30-92473c250f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227241979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4227241979
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.451427461
Short name T170
Test name
Test status
Simulation time 458883643 ps
CPU time 0.94 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:03:43 PM PDT 24
Peak memory 196448 kb
Host smart-4c5966fe-2e19-40bc-b8a5-531dc480e851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451427461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.451427461
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1814563289
Short name T165
Test name
Test status
Simulation time 491334634 ps
CPU time 0.98 seconds
Started Jun 27 06:03:39 PM PDT 24
Finished Jun 27 06:03:44 PM PDT 24
Peak memory 196480 kb
Host smart-8f56a456-d28f-4c7f-b61f-12fed0997034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814563289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1814563289
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1952955541
Short name T87
Test name
Test status
Simulation time 8779245803 ps
CPU time 64.91 seconds
Started Jun 27 06:03:42 PM PDT 24
Finished Jun 27 06:04:49 PM PDT 24
Peak memory 206644 kb
Host smart-e6655807-db74-48fd-b0e4-6ab73648b082
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952955541 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1952955541
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3055657940
Short name T38
Test name
Test status
Simulation time 579532384 ps
CPU time 1.46 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:01 PM PDT 24
Peak memory 196448 kb
Host smart-f750855f-162d-4b2f-a378-ec6ad2d2f159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055657940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3055657940
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4107552536
Short name T168
Test name
Test status
Simulation time 367295492 ps
CPU time 0.85 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:01 PM PDT 24
Peak memory 196544 kb
Host smart-02b60113-675e-4e15-8fea-9914929a31d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107552536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4107552536
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1931520268
Short name T31
Test name
Test status
Simulation time 77425658196 ps
CPU time 162.97 seconds
Started Jun 27 06:04:00 PM PDT 24
Finished Jun 27 06:06:46 PM PDT 24
Peak memory 198840 kb
Host smart-ff7c1b2f-b644-4ee7-81c0-a0ee5cad95d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931520268 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1931520268
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.108660948
Short name T156
Test name
Test status
Simulation time 577023436 ps
CPU time 0.79 seconds
Started Jun 27 06:04:12 PM PDT 24
Finished Jun 27 06:04:15 PM PDT 24
Peak memory 196448 kb
Host smart-99cf4727-db88-4bd0-8cb2-5c513cef5655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108660948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.108660948
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2270600576
Short name T182
Test name
Test status
Simulation time 609485011 ps
CPU time 0.8 seconds
Started Jun 27 06:03:13 PM PDT 24
Finished Jun 27 06:03:16 PM PDT 24
Peak memory 196568 kb
Host smart-304f989d-89ca-43c5-adcb-8d02ce497f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270600576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2270600576
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2883833379
Short name T169
Test name
Test status
Simulation time 492177918 ps
CPU time 0.73 seconds
Started Jun 27 06:02:55 PM PDT 24
Finished Jun 27 06:02:57 PM PDT 24
Peak memory 196540 kb
Host smart-b21f3813-b1aa-49fa-8321-a42f1534984f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883833379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2883833379
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.835401423
Short name T160
Test name
Test status
Simulation time 540392969 ps
CPU time 0.83 seconds
Started Jun 27 06:03:16 PM PDT 24
Finished Jun 27 06:03:21 PM PDT 24
Peak memory 196508 kb
Host smart-4599cd9c-34bf-4797-9973-22bc066b5ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835401423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.835401423
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.671043056
Short name T99
Test name
Test status
Simulation time 390589843 ps
CPU time 0.8 seconds
Started Jun 27 06:03:33 PM PDT 24
Finished Jun 27 06:03:36 PM PDT 24
Peak memory 196504 kb
Host smart-b8b15aa9-bfe8-487c-b551-2d6cab379e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671043056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.671043056
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3499219282
Short name T148
Test name
Test status
Simulation time 476691161 ps
CPU time 1.31 seconds
Started Jun 27 06:02:57 PM PDT 24
Finished Jun 27 06:03:00 PM PDT 24
Peak memory 196460 kb
Host smart-5528ee6d-93e0-4038-a173-2abe05ca4bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499219282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3499219282
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.982098837
Short name T181
Test name
Test status
Simulation time 454761910663 ps
CPU time 147.91 seconds
Started Jun 27 06:02:59 PM PDT 24
Finished Jun 27 06:05:29 PM PDT 24
Peak memory 191672 kb
Host smart-fd1a657d-98a8-423d-8324-32bfe75df049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982098837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.982098837
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.505180984
Short name T171
Test name
Test status
Simulation time 445012370748 ps
CPU time 79.44 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:05:01 PM PDT 24
Peak memory 192420 kb
Host smart-7526b382-9876-4022-a893-c84db5b52b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505180984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.505180984
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1285515862
Short name T48
Test name
Test status
Simulation time 597821723 ps
CPU time 0.94 seconds
Started Jun 27 06:03:43 PM PDT 24
Finished Jun 27 06:03:46 PM PDT 24
Peak memory 196352 kb
Host smart-6963bf32-abcc-4e68-97d1-c976ca6c79a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285515862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1285515862
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.605884609
Short name T180
Test name
Test status
Simulation time 184684073526 ps
CPU time 120.6 seconds
Started Jun 27 06:03:55 PM PDT 24
Finished Jun 27 06:05:56 PM PDT 24
Peak memory 192816 kb
Host smart-9b1dedd5-40a5-4e51-8124-9b57d52da0cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605884609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.605884609
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2439780944
Short name T177
Test name
Test status
Simulation time 511279044 ps
CPU time 0.8 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:01 PM PDT 24
Peak memory 196460 kb
Host smart-42c97927-0408-4abf-915a-944ba0b62046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439780944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2439780944
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3435134987
Short name T172
Test name
Test status
Simulation time 186013702206 ps
CPU time 55.13 seconds
Started Jun 27 06:03:58 PM PDT 24
Finished Jun 27 06:04:56 PM PDT 24
Peak memory 192736 kb
Host smart-e0079b2c-d8a8-4225-b846-5185381a9f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435134987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3435134987
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2124503162
Short name T166
Test name
Test status
Simulation time 575904021 ps
CPU time 1.41 seconds
Started Jun 27 06:03:00 PM PDT 24
Finished Jun 27 06:03:02 PM PDT 24
Peak memory 196416 kb
Host smart-e9546ccd-ffb2-49b3-8ac1-d99666b2e3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124503162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2124503162
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1128153841
Short name T174
Test name
Test status
Simulation time 487235392 ps
CPU time 0.9 seconds
Started Jun 27 06:04:12 PM PDT 24
Finished Jun 27 06:04:15 PM PDT 24
Peak memory 196524 kb
Host smart-0e01f228-1836-4d14-a365-499a59e221f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128153841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1128153841
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2484584584
Short name T162
Test name
Test status
Simulation time 16047845277 ps
CPU time 60.98 seconds
Started Jun 27 06:02:55 PM PDT 24
Finished Jun 27 06:03:57 PM PDT 24
Peak memory 206632 kb
Host smart-182a09c6-713a-46c9-a7e1-361ccaaf12db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484584584 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2484584584
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2369917044
Short name T163
Test name
Test status
Simulation time 644860436 ps
CPU time 0.85 seconds
Started Jun 27 06:03:15 PM PDT 24
Finished Jun 27 06:03:20 PM PDT 24
Peak memory 196452 kb
Host smart-ae1ebbe4-4fa5-4c85-ac32-dc09a1a62cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369917044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2369917044
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.834689299
Short name T54
Test name
Test status
Simulation time 571448003 ps
CPU time 1.79 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:45 PM PDT 24
Peak memory 194040 kb
Host smart-c18bc221-b99a-412a-822e-72cb2b42d56f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834689299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.834689299
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4227525044
Short name T354
Test name
Test status
Simulation time 13949563473 ps
CPU time 7.2 seconds
Started Jun 27 06:08:39 PM PDT 24
Finished Jun 27 06:08:48 PM PDT 24
Peak memory 196288 kb
Host smart-ffe0ac10-4b1e-4bd2-aabc-757a70872c44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227525044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.4227525044
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.183551497
Short name T20
Test name
Test status
Simulation time 892586795 ps
CPU time 0.81 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:43 PM PDT 24
Peak memory 183812 kb
Host smart-bd20d6d2-f2be-46e8-8dbc-f5d116bda1a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183551497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.183551497
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4104477126
Short name T379
Test name
Test status
Simulation time 404995548 ps
CPU time 0.85 seconds
Started Jun 27 06:08:38 PM PDT 24
Finished Jun 27 06:08:40 PM PDT 24
Peak memory 195276 kb
Host smart-66685ac8-6352-441c-ab0f-fc044d2532d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104477126 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.4104477126
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2503255904
Short name T56
Test name
Test status
Simulation time 522994494 ps
CPU time 1.18 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:43 PM PDT 24
Peak memory 193364 kb
Host smart-bb690d86-d994-42e4-a990-799147ea5c4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503255904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2503255904
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1555996969
Short name T381
Test name
Test status
Simulation time 488628752 ps
CPU time 1.29 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:44 PM PDT 24
Peak memory 183836 kb
Host smart-c474f970-dec5-455e-88bb-f98f5ab34e46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555996969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1555996969
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.891615118
Short name T378
Test name
Test status
Simulation time 517903784 ps
CPU time 0.69 seconds
Started Jun 27 06:08:38 PM PDT 24
Finished Jun 27 06:08:40 PM PDT 24
Peak memory 183756 kb
Host smart-b55be7fc-19c4-4027-b2c3-5121bd7f47b1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891615118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.891615118
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2676161289
Short name T330
Test name
Test status
Simulation time 451802824 ps
CPU time 0.67 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:44 PM PDT 24
Peak memory 183716 kb
Host smart-5f85ce87-7264-4d3f-bdf6-8cbe6bc0241d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676161289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2676161289
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.87445867
Short name T376
Test name
Test status
Simulation time 2156700889 ps
CPU time 2.92 seconds
Started Jun 27 06:08:42 PM PDT 24
Finished Jun 27 06:08:48 PM PDT 24
Peak memory 194036 kb
Host smart-f596b39f-30aa-4366-8d73-b0d6840f1e00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87445867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_same_csr_outstanding.87445867
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.924125248
Short name T320
Test name
Test status
Simulation time 604965238 ps
CPU time 1.77 seconds
Started Jun 27 06:08:43 PM PDT 24
Finished Jun 27 06:08:48 PM PDT 24
Peak memory 198560 kb
Host smart-1e6c6841-521a-4b2d-a823-e834417a948f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924125248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.924125248
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2560714810
Short name T192
Test name
Test status
Simulation time 8834411797 ps
CPU time 4.63 seconds
Started Jun 27 06:08:36 PM PDT 24
Finished Jun 27 06:08:42 PM PDT 24
Peak memory 198292 kb
Host smart-6b920f0d-fb0a-4bef-834c-4fa491d94296
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560714810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2560714810
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3412328239
Short name T410
Test name
Test status
Simulation time 465223545 ps
CPU time 1.43 seconds
Started Jun 27 06:08:38 PM PDT 24
Finished Jun 27 06:08:42 PM PDT 24
Peak memory 183780 kb
Host smart-891b23d1-f153-44d9-ae79-f188bb1c0bf8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412328239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3412328239
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3633244253
Short name T55
Test name
Test status
Simulation time 5225453018 ps
CPU time 5.12 seconds
Started Jun 27 06:08:39 PM PDT 24
Finished Jun 27 06:08:45 PM PDT 24
Peak memory 192268 kb
Host smart-832ccd11-892e-4c72-84eb-ac76740269e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633244253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3633244253
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2664155073
Short name T301
Test name
Test status
Simulation time 746797038 ps
CPU time 0.83 seconds
Started Jun 27 06:08:38 PM PDT 24
Finished Jun 27 06:08:40 PM PDT 24
Peak memory 192368 kb
Host smart-474da999-77fa-4a51-82d1-305a52bf9078
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664155073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2664155073
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4294966160
Short name T383
Test name
Test status
Simulation time 469188562 ps
CPU time 0.93 seconds
Started Jun 27 06:08:41 PM PDT 24
Finished Jun 27 06:08:45 PM PDT 24
Peak memory 196872 kb
Host smart-4c8d13eb-aee9-411d-b286-8c92d960e713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294966160 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.4294966160
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2862644367
Short name T373
Test name
Test status
Simulation time 490683232 ps
CPU time 1.2 seconds
Started Jun 27 06:08:37 PM PDT 24
Finished Jun 27 06:08:40 PM PDT 24
Peak memory 193196 kb
Host smart-75728ceb-c9ce-4902-a238-9643a65c9be6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862644367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2862644367
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3892003336
Short name T412
Test name
Test status
Simulation time 482796320 ps
CPU time 0.7 seconds
Started Jun 27 06:08:39 PM PDT 24
Finished Jun 27 06:08:41 PM PDT 24
Peak memory 183808 kb
Host smart-8f20470a-0017-4408-8498-012dc1560c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892003336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3892003336
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1410022069
Short name T329
Test name
Test status
Simulation time 397868453 ps
CPU time 1.09 seconds
Started Jun 27 06:08:39 PM PDT 24
Finished Jun 27 06:08:43 PM PDT 24
Peak memory 183756 kb
Host smart-49563558-85ff-47a9-af95-cd2834a793b8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410022069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1410022069
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3975527275
Short name T328
Test name
Test status
Simulation time 307481875 ps
CPU time 0.62 seconds
Started Jun 27 06:08:37 PM PDT 24
Finished Jun 27 06:08:38 PM PDT 24
Peak memory 183744 kb
Host smart-ab38b6dd-62ba-4070-8fee-0abed1b971dd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975527275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3975527275
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.840337993
Short name T331
Test name
Test status
Simulation time 1647194644 ps
CPU time 1.21 seconds
Started Jun 27 06:08:42 PM PDT 24
Finished Jun 27 06:08:46 PM PDT 24
Peak memory 193996 kb
Host smart-9e11380b-43cd-48c9-b956-f700a5b25070
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840337993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.840337993
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.229131719
Short name T403
Test name
Test status
Simulation time 390671871 ps
CPU time 2.62 seconds
Started Jun 27 06:08:38 PM PDT 24
Finished Jun 27 06:08:42 PM PDT 24
Peak memory 198652 kb
Host smart-623686cd-bd50-4918-95e0-040860dd6de4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229131719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.229131719
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1289781663
Short name T319
Test name
Test status
Simulation time 371639026 ps
CPU time 0.78 seconds
Started Jun 27 06:09:02 PM PDT 24
Finished Jun 27 06:09:05 PM PDT 24
Peak memory 196312 kb
Host smart-87d2c1ff-ec2d-4205-8e46-f96c46e15c6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289781663 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1289781663
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2594057587
Short name T77
Test name
Test status
Simulation time 355226340 ps
CPU time 0.62 seconds
Started Jun 27 06:08:55 PM PDT 24
Finished Jun 27 06:08:58 PM PDT 24
Peak memory 193372 kb
Host smart-dcb0351c-3038-4c15-9ee0-3c52856b2e52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594057587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2594057587
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3278769717
Short name T318
Test name
Test status
Simulation time 485070933 ps
CPU time 0.7 seconds
Started Jun 27 06:08:59 PM PDT 24
Finished Jun 27 06:09:01 PM PDT 24
Peak memory 183812 kb
Host smart-9d765856-fa7b-4f37-82a9-26069c52aa52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278769717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3278769717
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2379141730
Short name T405
Test name
Test status
Simulation time 2677371298 ps
CPU time 6.21 seconds
Started Jun 27 06:09:02 PM PDT 24
Finished Jun 27 06:09:10 PM PDT 24
Peak memory 195104 kb
Host smart-68dd5a2e-5abb-4171-9bbc-7548b7056681
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379141730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2379141730
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1282994377
Short name T324
Test name
Test status
Simulation time 433204062 ps
CPU time 1.1 seconds
Started Jun 27 06:08:52 PM PDT 24
Finished Jun 27 06:08:55 PM PDT 24
Peak memory 198124 kb
Host smart-d4780e5e-0000-495d-b1d0-869ab9e6067b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282994377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1282994377
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1966382882
Short name T185
Test name
Test status
Simulation time 4487773923 ps
CPU time 7.4 seconds
Started Jun 27 06:09:00 PM PDT 24
Finished Jun 27 06:09:09 PM PDT 24
Peak memory 198156 kb
Host smart-67dfb1b3-189d-4001-8bcd-9029301392d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966382882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1966382882
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1699387399
Short name T310
Test name
Test status
Simulation time 521899577 ps
CPU time 0.81 seconds
Started Jun 27 06:08:52 PM PDT 24
Finished Jun 27 06:08:55 PM PDT 24
Peak memory 197388 kb
Host smart-06facaa0-f304-4464-bf34-313df11fb11e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699387399 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1699387399
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2407197717
Short name T357
Test name
Test status
Simulation time 444784643 ps
CPU time 0.88 seconds
Started Jun 27 06:08:54 PM PDT 24
Finished Jun 27 06:08:56 PM PDT 24
Peak memory 183824 kb
Host smart-e7af2aba-4e17-4b85-a9cf-aa9955ecd00f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407197717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2407197717
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2441194615
Short name T361
Test name
Test status
Simulation time 2218105874 ps
CPU time 1.33 seconds
Started Jun 27 06:09:02 PM PDT 24
Finished Jun 27 06:09:05 PM PDT 24
Peak memory 194512 kb
Host smart-8c8d1681-a777-48ee-8655-fadd7fd53451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441194615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2441194615
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1369492986
Short name T286
Test name
Test status
Simulation time 488639545 ps
CPU time 1.52 seconds
Started Jun 27 06:08:53 PM PDT 24
Finished Jun 27 06:08:56 PM PDT 24
Peak memory 198624 kb
Host smart-b2a510e6-0571-46f1-a987-b1f60e975c26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369492986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1369492986
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.470146657
Short name T398
Test name
Test status
Simulation time 549515988 ps
CPU time 0.94 seconds
Started Jun 27 06:08:56 PM PDT 24
Finished Jun 27 06:08:59 PM PDT 24
Peak memory 197076 kb
Host smart-b24908c8-8eed-4c39-817f-048be72f5fa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470146657 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.470146657
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2053290688
Short name T352
Test name
Test status
Simulation time 324579222 ps
CPU time 0.83 seconds
Started Jun 27 06:08:57 PM PDT 24
Finished Jun 27 06:09:00 PM PDT 24
Peak memory 193368 kb
Host smart-8f7c0d2a-226d-4501-8c3f-6d2aae1d9f1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053290688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2053290688
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2032834206
Short name T282
Test name
Test status
Simulation time 563967335 ps
CPU time 0.62 seconds
Started Jun 27 06:09:00 PM PDT 24
Finished Jun 27 06:09:02 PM PDT 24
Peak memory 183832 kb
Host smart-bd904484-0fb3-420b-915d-50873f251061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032834206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2032834206
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1535493124
Short name T380
Test name
Test status
Simulation time 998459938 ps
CPU time 2.13 seconds
Started Jun 27 06:08:52 PM PDT 24
Finished Jun 27 06:08:56 PM PDT 24
Peak memory 194244 kb
Host smart-60dd4f91-5d01-4f11-8371-c14a31732344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535493124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1535493124
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1949311617
Short name T306
Test name
Test status
Simulation time 428985479 ps
CPU time 2.02 seconds
Started Jun 27 06:08:56 PM PDT 24
Finished Jun 27 06:09:00 PM PDT 24
Peak memory 198688 kb
Host smart-f59f5fc4-e6c7-4d31-8fe8-cff79799900b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949311617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1949311617
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3145756508
Short name T22
Test name
Test status
Simulation time 4291968550 ps
CPU time 1.89 seconds
Started Jun 27 06:08:53 PM PDT 24
Finished Jun 27 06:08:57 PM PDT 24
Peak memory 197912 kb
Host smart-c79f9aab-65ea-4bd1-a6ed-20c0ad852df4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145756508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3145756508
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.439801454
Short name T415
Test name
Test status
Simulation time 448550414 ps
CPU time 0.83 seconds
Started Jun 27 06:08:56 PM PDT 24
Finished Jun 27 06:08:59 PM PDT 24
Peak memory 196328 kb
Host smart-b8053021-9b27-4021-bbe0-916b6e28f9b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439801454 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.439801454
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.359011563
Short name T392
Test name
Test status
Simulation time 539939080 ps
CPU time 1.28 seconds
Started Jun 27 06:08:54 PM PDT 24
Finished Jun 27 06:08:58 PM PDT 24
Peak memory 193340 kb
Host smart-7dd307f0-ba06-4d5b-8a2d-79c85296e9a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359011563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.359011563
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3309864754
Short name T372
Test name
Test status
Simulation time 434700185 ps
CPU time 0.82 seconds
Started Jun 27 06:08:54 PM PDT 24
Finished Jun 27 06:08:56 PM PDT 24
Peak memory 183836 kb
Host smart-05161d4c-13e4-465f-aa29-3159749a8bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309864754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3309864754
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3201314608
Short name T420
Test name
Test status
Simulation time 2009356313 ps
CPU time 4.42 seconds
Started Jun 27 06:09:00 PM PDT 24
Finished Jun 27 06:09:05 PM PDT 24
Peak memory 195092 kb
Host smart-0f489796-93f6-48f9-b103-ce6349b8529c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201314608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3201314608
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3911829110
Short name T395
Test name
Test status
Simulation time 336381915 ps
CPU time 2.51 seconds
Started Jun 27 06:09:01 PM PDT 24
Finished Jun 27 06:09:05 PM PDT 24
Peak memory 198672 kb
Host smart-1633e951-4586-4e10-9d63-586223d9c678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911829110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3911829110
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3152424520
Short name T191
Test name
Test status
Simulation time 8162904569 ps
CPU time 2.66 seconds
Started Jun 27 06:08:55 PM PDT 24
Finished Jun 27 06:09:00 PM PDT 24
Peak memory 198108 kb
Host smart-747e2a99-c409-493c-8855-adff995985c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152424520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3152424520
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.637432441
Short name T404
Test name
Test status
Simulation time 771328961 ps
CPU time 0.87 seconds
Started Jun 27 06:09:02 PM PDT 24
Finished Jun 27 06:09:04 PM PDT 24
Peak memory 197724 kb
Host smart-20001cc6-8f07-4bca-b7f7-d803088e71ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637432441 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.637432441
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1870259707
Short name T365
Test name
Test status
Simulation time 327716560 ps
CPU time 0.81 seconds
Started Jun 27 06:08:53 PM PDT 24
Finished Jun 27 06:08:55 PM PDT 24
Peak memory 193316 kb
Host smart-5565ea50-072b-4f23-9dc6-cb88cd354309
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870259707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1870259707
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1901087721
Short name T307
Test name
Test status
Simulation time 385560297 ps
CPU time 0.64 seconds
Started Jun 27 06:08:56 PM PDT 24
Finished Jun 27 06:08:59 PM PDT 24
Peak memory 183832 kb
Host smart-0f212ecb-eb1a-4ff7-b28e-8edea8dfb1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901087721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1901087721
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2903253641
Short name T74
Test name
Test status
Simulation time 1365846194 ps
CPU time 0.86 seconds
Started Jun 27 06:08:56 PM PDT 24
Finished Jun 27 06:08:59 PM PDT 24
Peak memory 183824 kb
Host smart-f662e885-0b3f-4f47-a394-eb12512bc26c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903253641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2903253641
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1042606746
Short name T287
Test name
Test status
Simulation time 454816517 ps
CPU time 2.8 seconds
Started Jun 27 06:09:00 PM PDT 24
Finished Jun 27 06:09:04 PM PDT 24
Peak memory 198664 kb
Host smart-0999f6e2-bf70-475a-9ab2-7ccaa14eed1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042606746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1042606746
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1206768727
Short name T190
Test name
Test status
Simulation time 4167675070 ps
CPU time 7.01 seconds
Started Jun 27 06:09:00 PM PDT 24
Finished Jun 27 06:09:08 PM PDT 24
Peak memory 197556 kb
Host smart-35fa279b-4918-4047-86de-76a2504c1fc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206768727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1206768727
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1963223424
Short name T294
Test name
Test status
Simulation time 395751900 ps
CPU time 0.9 seconds
Started Jun 27 06:09:00 PM PDT 24
Finished Jun 27 06:09:02 PM PDT 24
Peak memory 196196 kb
Host smart-84ff5689-124c-429d-b161-f00285386dd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963223424 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1963223424
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.613463846
Short name T288
Test name
Test status
Simulation time 521911886 ps
CPU time 0.76 seconds
Started Jun 27 06:08:57 PM PDT 24
Finished Jun 27 06:09:00 PM PDT 24
Peak memory 193036 kb
Host smart-4c307819-5d36-4688-809e-103e1cdfd2df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613463846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.613463846
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1565929863
Short name T303
Test name
Test status
Simulation time 502779685 ps
CPU time 0.68 seconds
Started Jun 27 06:09:02 PM PDT 24
Finished Jun 27 06:09:05 PM PDT 24
Peak memory 193004 kb
Host smart-6aad2743-468e-4c1c-aab3-ccd90ea3803a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565929863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1565929863
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2037772134
Short name T332
Test name
Test status
Simulation time 2427322609 ps
CPU time 4.07 seconds
Started Jun 27 06:08:56 PM PDT 24
Finished Jun 27 06:09:03 PM PDT 24
Peak memory 195092 kb
Host smart-86eecc6e-5af1-4220-8546-5b9981e2cee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037772134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2037772134
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2271887276
Short name T413
Test name
Test status
Simulation time 466516068 ps
CPU time 1.69 seconds
Started Jun 27 06:09:02 PM PDT 24
Finished Jun 27 06:09:05 PM PDT 24
Peak memory 198292 kb
Host smart-087a2e20-951c-468c-8599-e287ad6bfeec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271887276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2271887276
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.826069971
Short name T24
Test name
Test status
Simulation time 3893308259 ps
CPU time 2.28 seconds
Started Jun 27 06:09:00 PM PDT 24
Finished Jun 27 06:09:03 PM PDT 24
Peak memory 197892 kb
Host smart-b07cbff0-1e4c-4f01-8778-18eb2b4dbe44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826069971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.826069971
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.113410358
Short name T297
Test name
Test status
Simulation time 532127804 ps
CPU time 0.76 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:12 PM PDT 24
Peak memory 196420 kb
Host smart-d836e566-0b1e-46d7-a136-c0b9fe5e6c9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113410358 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.113410358
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.844527397
Short name T386
Test name
Test status
Simulation time 432871424 ps
CPU time 1.15 seconds
Started Jun 27 06:09:10 PM PDT 24
Finished Jun 27 06:09:13 PM PDT 24
Peak memory 193412 kb
Host smart-7a0a913e-6cbc-46be-b618-12460bb0782a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844527397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.844527397
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3647637889
Short name T355
Test name
Test status
Simulation time 474550371 ps
CPU time 0.68 seconds
Started Jun 27 06:09:12 PM PDT 24
Finished Jun 27 06:09:14 PM PDT 24
Peak memory 193044 kb
Host smart-943268a8-b77f-4f57-ba17-323285f2b76c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647637889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3647637889
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.996423160
Short name T358
Test name
Test status
Simulation time 2266619579 ps
CPU time 0.91 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:13 PM PDT 24
Peak memory 193868 kb
Host smart-8c47417a-0d76-4ce1-ba70-d1150a7033b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996423160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.996423160
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2874753920
Short name T409
Test name
Test status
Simulation time 463986454 ps
CPU time 1.5 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:12 PM PDT 24
Peak memory 198676 kb
Host smart-ee6ce14a-8f8f-4eb6-9d8e-3b13c06e5bed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874753920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2874753920
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.722636518
Short name T340
Test name
Test status
Simulation time 4269062285 ps
CPU time 7.62 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:19 PM PDT 24
Peak memory 197972 kb
Host smart-21246bd1-13b8-4271-9d19-af1c9b3eecb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722636518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.722636518
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3346734532
Short name T374
Test name
Test status
Simulation time 454365987 ps
CPU time 0.9 seconds
Started Jun 27 06:09:17 PM PDT 24
Finished Jun 27 06:09:19 PM PDT 24
Peak memory 196020 kb
Host smart-267ddacb-be74-4f00-bea7-ac7a22740c5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346734532 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3346734532
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3406623677
Short name T367
Test name
Test status
Simulation time 341255436 ps
CPU time 1.03 seconds
Started Jun 27 06:09:18 PM PDT 24
Finished Jun 27 06:09:20 PM PDT 24
Peak memory 193044 kb
Host smart-fddae351-5381-49d4-baa0-8c687049d39f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406623677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3406623677
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.965091202
Short name T336
Test name
Test status
Simulation time 400220614 ps
CPU time 0.63 seconds
Started Jun 27 06:09:17 PM PDT 24
Finished Jun 27 06:09:19 PM PDT 24
Peak memory 183788 kb
Host smart-95a65626-38cb-4450-8c28-231792f71167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965091202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.965091202
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2074116853
Short name T406
Test name
Test status
Simulation time 2522525096 ps
CPU time 3.9 seconds
Started Jun 27 06:09:10 PM PDT 24
Finished Jun 27 06:09:16 PM PDT 24
Peak memory 193816 kb
Host smart-96b59318-897e-448e-adf5-c44913e05eca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074116853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2074116853
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2009488154
Short name T305
Test name
Test status
Simulation time 1867796032 ps
CPU time 2.35 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:14 PM PDT 24
Peak memory 198660 kb
Host smart-56d71273-2e5c-496e-aa58-03b6846debc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009488154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2009488154
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1881983923
Short name T394
Test name
Test status
Simulation time 9393251798 ps
CPU time 2.51 seconds
Started Jun 27 06:09:08 PM PDT 24
Finished Jun 27 06:09:13 PM PDT 24
Peak memory 198268 kb
Host smart-0358d734-72a9-49db-b065-1346824a74ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881983923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1881983923
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.268898237
Short name T377
Test name
Test status
Simulation time 366227729 ps
CPU time 0.77 seconds
Started Jun 27 06:09:07 PM PDT 24
Finished Jun 27 06:09:09 PM PDT 24
Peak memory 195616 kb
Host smart-ed330303-8d64-40fa-99aa-9264d0f950d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268898237 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.268898237
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2135988109
Short name T296
Test name
Test status
Simulation time 491056985 ps
CPU time 0.76 seconds
Started Jun 27 06:09:08 PM PDT 24
Finished Jun 27 06:09:11 PM PDT 24
Peak memory 194064 kb
Host smart-e9da728f-4ddf-4c9b-b05c-4aed93798fbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135988109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2135988109
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.543188792
Short name T285
Test name
Test status
Simulation time 380361206 ps
CPU time 1.01 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:12 PM PDT 24
Peak memory 183836 kb
Host smart-c3c39cdb-63ef-49aa-be07-77b8f00a565e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543188792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.543188792
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.184369603
Short name T418
Test name
Test status
Simulation time 1744007880 ps
CPU time 2.8 seconds
Started Jun 27 06:09:18 PM PDT 24
Finished Jun 27 06:09:22 PM PDT 24
Peak memory 193876 kb
Host smart-6036afe1-d61c-4057-a860-344635e918a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184369603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.184369603
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3844624021
Short name T368
Test name
Test status
Simulation time 332673218 ps
CPU time 1.22 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:12 PM PDT 24
Peak memory 198424 kb
Host smart-eb17e36b-44eb-44a2-acb9-08622dc50ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844624021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3844624021
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.810898470
Short name T366
Test name
Test status
Simulation time 4019725957 ps
CPU time 6.55 seconds
Started Jun 27 06:09:10 PM PDT 24
Finished Jun 27 06:09:19 PM PDT 24
Peak memory 198088 kb
Host smart-5703d65a-6ce8-4d6e-9318-0c41a2b72ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810898470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.810898470
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2341965587
Short name T339
Test name
Test status
Simulation time 570270538 ps
CPU time 1.07 seconds
Started Jun 27 06:09:07 PM PDT 24
Finished Jun 27 06:09:09 PM PDT 24
Peak memory 198452 kb
Host smart-692b147c-4165-446f-9578-063d3ebf5ea2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341965587 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2341965587
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1411919037
Short name T370
Test name
Test status
Simulation time 366641177 ps
CPU time 0.63 seconds
Started Jun 27 06:09:19 PM PDT 24
Finished Jun 27 06:09:21 PM PDT 24
Peak memory 193048 kb
Host smart-8b2f966a-a5a7-45a2-a4cb-c84fcae6e68d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411919037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1411919037
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3038793480
Short name T419
Test name
Test status
Simulation time 287923930 ps
CPU time 0.94 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:12 PM PDT 24
Peak memory 183804 kb
Host smart-dd01166e-1e12-4e30-9239-cb96398a22ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038793480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3038793480
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1204486392
Short name T343
Test name
Test status
Simulation time 1464437408 ps
CPU time 1.12 seconds
Started Jun 27 06:09:10 PM PDT 24
Finished Jun 27 06:09:13 PM PDT 24
Peak memory 183828 kb
Host smart-37569eec-59d6-4002-934f-58360583d55a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204486392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1204486392
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2642477956
Short name T389
Test name
Test status
Simulation time 519751838 ps
CPU time 3.02 seconds
Started Jun 27 06:09:11 PM PDT 24
Finished Jun 27 06:09:16 PM PDT 24
Peak memory 198644 kb
Host smart-7f3c1700-f5a8-49b2-ab80-007c96ebd762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642477956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2642477956
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3579101206
Short name T396
Test name
Test status
Simulation time 4215511644 ps
CPU time 7.52 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:18 PM PDT 24
Peak memory 197700 kb
Host smart-6fc6bd7c-3733-4936-95ee-ae101ef94763
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579101206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3579101206
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.482498227
Short name T60
Test name
Test status
Simulation time 278167469 ps
CPU time 1.03 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:45 PM PDT 24
Peak memory 193192 kb
Host smart-8f6623f7-4c07-4678-b4ce-7e25096724e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482498227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.482498227
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4285667204
Short name T26
Test name
Test status
Simulation time 1842380487 ps
CPU time 1.72 seconds
Started Jun 27 06:08:38 PM PDT 24
Finished Jun 27 06:08:41 PM PDT 24
Peak memory 196304 kb
Host smart-d2c6763c-fbb5-4c9f-b56c-b6120636a7c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285667204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.4285667204
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.531822140
Short name T19
Test name
Test status
Simulation time 1285640558 ps
CPU time 0.77 seconds
Started Jun 27 06:08:38 PM PDT 24
Finished Jun 27 06:08:41 PM PDT 24
Peak memory 183828 kb
Host smart-b215ce25-68dd-4072-a514-4f3d590a64c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531822140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.531822140
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1500612092
Short name T327
Test name
Test status
Simulation time 502046074 ps
CPU time 0.84 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:44 PM PDT 24
Peak memory 196572 kb
Host smart-381cc5e5-b133-419a-b920-3b51999ed69e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500612092 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1500612092
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1287704144
Short name T400
Test name
Test status
Simulation time 505911065 ps
CPU time 1.22 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:45 PM PDT 24
Peak memory 193040 kb
Host smart-f30ab2c4-a6e4-4868-b2a1-37fba8688d4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287704144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1287704144
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2052890206
Short name T304
Test name
Test status
Simulation time 521632642 ps
CPU time 0.75 seconds
Started Jun 27 06:08:37 PM PDT 24
Finished Jun 27 06:08:40 PM PDT 24
Peak memory 183848 kb
Host smart-6964143e-ee9a-4c1b-a175-ad614b588cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052890206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2052890206
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3007861547
Short name T350
Test name
Test status
Simulation time 424467219 ps
CPU time 0.63 seconds
Started Jun 27 06:08:42 PM PDT 24
Finished Jun 27 06:08:45 PM PDT 24
Peak memory 183736 kb
Host smart-c5c07b11-647e-4d77-8843-c7a23c55171d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007861547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3007861547
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.534716530
Short name T351
Test name
Test status
Simulation time 396948123 ps
CPU time 0.61 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:44 PM PDT 24
Peak memory 183748 kb
Host smart-7c08c56c-3628-4a12-bed7-d8a9ad1eec9f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534716530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.534716530
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2285150493
Short name T73
Test name
Test status
Simulation time 1908907299 ps
CPU time 1.57 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:45 PM PDT 24
Peak memory 194136 kb
Host smart-f835f783-d964-45bf-bb32-ef5d363760ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285150493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2285150493
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.780477996
Short name T402
Test name
Test status
Simulation time 492548305 ps
CPU time 1.5 seconds
Started Jun 27 06:08:38 PM PDT 24
Finished Jun 27 06:08:41 PM PDT 24
Peak memory 198688 kb
Host smart-88622df3-659e-4dc6-adfc-f95755961711
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780477996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.780477996
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2820320537
Short name T335
Test name
Test status
Simulation time 4524873386 ps
CPU time 2.11 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:45 PM PDT 24
Peak memory 196644 kb
Host smart-b1122bb5-826b-4c7a-aaba-a0d9ab708bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820320537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2820320537
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2172272424
Short name T362
Test name
Test status
Simulation time 349762877 ps
CPU time 0.8 seconds
Started Jun 27 06:09:10 PM PDT 24
Finished Jun 27 06:09:13 PM PDT 24
Peak memory 183800 kb
Host smart-507c642f-3e7b-4801-8583-0ada5c3b4541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172272424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2172272424
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2901314063
Short name T302
Test name
Test status
Simulation time 535819867 ps
CPU time 0.74 seconds
Started Jun 27 06:09:08 PM PDT 24
Finished Jun 27 06:09:10 PM PDT 24
Peak memory 183832 kb
Host smart-b9f9bdbe-9ed4-45b7-b6e3-9d90ad92aedd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901314063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2901314063
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1387259967
Short name T385
Test name
Test status
Simulation time 394258856 ps
CPU time 0.67 seconds
Started Jun 27 06:09:08 PM PDT 24
Finished Jun 27 06:09:10 PM PDT 24
Peak memory 183840 kb
Host smart-7782103b-5b4d-4712-8393-94b0580e9bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387259967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1387259967
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3324357727
Short name T325
Test name
Test status
Simulation time 317213734 ps
CPU time 0.78 seconds
Started Jun 27 06:09:08 PM PDT 24
Finished Jun 27 06:09:10 PM PDT 24
Peak memory 183824 kb
Host smart-157b6201-9525-4921-ae1d-52a9b3decebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324357727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3324357727
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3794808539
Short name T299
Test name
Test status
Simulation time 549895472 ps
CPU time 0.6 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:12 PM PDT 24
Peak memory 183740 kb
Host smart-43ecd72f-13d8-46a8-b0d8-2446510f072f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794808539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3794808539
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3147941677
Short name T316
Test name
Test status
Simulation time 511138323 ps
CPU time 0.86 seconds
Started Jun 27 06:09:17 PM PDT 24
Finished Jun 27 06:09:19 PM PDT 24
Peak memory 183840 kb
Host smart-57b66dac-47dd-4030-b450-24e34e5ba015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147941677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3147941677
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1306721552
Short name T281
Test name
Test status
Simulation time 323172724 ps
CPU time 1.01 seconds
Started Jun 27 06:09:08 PM PDT 24
Finished Jun 27 06:09:10 PM PDT 24
Peak memory 183836 kb
Host smart-b647af67-f41e-4819-9c9d-b874cf26f359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306721552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1306721552
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.680321253
Short name T290
Test name
Test status
Simulation time 528244103 ps
CPU time 0.74 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:12 PM PDT 24
Peak memory 183840 kb
Host smart-d021068a-9d4b-424c-8da2-c146f463e571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680321253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.680321253
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1999056344
Short name T315
Test name
Test status
Simulation time 459866428 ps
CPU time 1.22 seconds
Started Jun 27 06:09:12 PM PDT 24
Finished Jun 27 06:09:14 PM PDT 24
Peak memory 183836 kb
Host smart-36a18b76-cdd8-4be3-9fd2-a4b2e749396a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999056344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1999056344
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2780599617
Short name T317
Test name
Test status
Simulation time 274296904 ps
CPU time 0.97 seconds
Started Jun 27 06:09:13 PM PDT 24
Finished Jun 27 06:09:15 PM PDT 24
Peak memory 183836 kb
Host smart-0df1bb0f-5be0-41be-b4be-8608d229730c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780599617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2780599617
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2521295316
Short name T52
Test name
Test status
Simulation time 397538328 ps
CPU time 1.27 seconds
Started Jun 27 06:08:41 PM PDT 24
Finished Jun 27 06:08:45 PM PDT 24
Peak memory 193316 kb
Host smart-b0ac5089-e2aa-481e-887e-8ba2ec370dcc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521295316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2521295316
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3601041523
Short name T59
Test name
Test status
Simulation time 5099159734 ps
CPU time 4.41 seconds
Started Jun 27 06:08:41 PM PDT 24
Finished Jun 27 06:08:49 PM PDT 24
Peak memory 192244 kb
Host smart-943f053f-4e7b-44ca-b7cb-9108639ec359
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601041523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3601041523
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4234147359
Short name T356
Test name
Test status
Simulation time 848142716 ps
CPU time 1.71 seconds
Started Jun 27 06:08:38 PM PDT 24
Finished Jun 27 06:08:41 PM PDT 24
Peak memory 192152 kb
Host smart-a12b23a1-6885-4574-acb0-bc9cd1e59f76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234147359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.4234147359
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3085603424
Short name T311
Test name
Test status
Simulation time 410035605 ps
CPU time 1.17 seconds
Started Jun 27 06:08:41 PM PDT 24
Finished Jun 27 06:08:46 PM PDT 24
Peak memory 196156 kb
Host smart-83651a71-4a78-4459-b507-cf229c3d335f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085603424 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3085603424
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1010916271
Short name T57
Test name
Test status
Simulation time 540395162 ps
CPU time 0.7 seconds
Started Jun 27 06:08:42 PM PDT 24
Finished Jun 27 06:08:46 PM PDT 24
Peak memory 193284 kb
Host smart-5dc7d53b-fb5d-4bf2-aa1c-cf9e201d2c90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010916271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1010916271
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1337459458
Short name T382
Test name
Test status
Simulation time 275868832 ps
CPU time 0.73 seconds
Started Jun 27 06:08:40 PM PDT 24
Finished Jun 27 06:08:42 PM PDT 24
Peak memory 183804 kb
Host smart-f434ebd4-0441-44e9-885b-ef17865838c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337459458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1337459458
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2486571639
Short name T384
Test name
Test status
Simulation time 415354930 ps
CPU time 0.64 seconds
Started Jun 27 06:08:39 PM PDT 24
Finished Jun 27 06:08:41 PM PDT 24
Peak memory 183720 kb
Host smart-938ce40d-e080-4de8-bbd3-2d79eb5559af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486571639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2486571639
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1110942181
Short name T326
Test name
Test status
Simulation time 507081336 ps
CPU time 0.6 seconds
Started Jun 27 06:08:42 PM PDT 24
Finished Jun 27 06:08:46 PM PDT 24
Peak memory 183452 kb
Host smart-3d64d7c4-ecda-4070-b1ea-4c05e09ffeb9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110942181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1110942181
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2462539299
Short name T71
Test name
Test status
Simulation time 1004734034 ps
CPU time 1.77 seconds
Started Jun 27 06:08:45 PM PDT 24
Finished Jun 27 06:08:49 PM PDT 24
Peak memory 193612 kb
Host smart-f8bc7ac4-ef90-4bfc-98e3-6038b17b8004
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462539299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2462539299
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2728821463
Short name T298
Test name
Test status
Simulation time 328489818 ps
CPU time 1.62 seconds
Started Jun 27 06:08:42 PM PDT 24
Finished Jun 27 06:08:47 PM PDT 24
Peak memory 198488 kb
Host smart-d4924422-ae5f-46b0-aa08-53664cb2c618
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728821463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2728821463
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1369466269
Short name T390
Test name
Test status
Simulation time 9162174430 ps
CPU time 3.23 seconds
Started Jun 27 06:08:39 PM PDT 24
Finished Jun 27 06:08:44 PM PDT 24
Peak memory 198252 kb
Host smart-643af50c-46b9-4d4b-9fd8-f41d29c3e925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369466269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1369466269
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.4256895392
Short name T387
Test name
Test status
Simulation time 509831996 ps
CPU time 0.77 seconds
Started Jun 27 06:09:18 PM PDT 24
Finished Jun 27 06:09:20 PM PDT 24
Peak memory 183840 kb
Host smart-a9181a6e-9318-48fa-9e08-74961a66d138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256895392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.4256895392
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3972119329
Short name T347
Test name
Test status
Simulation time 452794406 ps
CPU time 0.7 seconds
Started Jun 27 06:09:18 PM PDT 24
Finished Jun 27 06:09:19 PM PDT 24
Peak memory 183840 kb
Host smart-0ad259fc-9f86-4047-8f55-7e906adae41f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972119329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3972119329
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3808279757
Short name T341
Test name
Test status
Simulation time 326218509 ps
CPU time 1.04 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:12 PM PDT 24
Peak memory 183720 kb
Host smart-319e3336-1c48-4e9d-87d5-23dfea5aba48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808279757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3808279757
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1976675348
Short name T284
Test name
Test status
Simulation time 381956505 ps
CPU time 1 seconds
Started Jun 27 06:09:08 PM PDT 24
Finished Jun 27 06:09:10 PM PDT 24
Peak memory 183832 kb
Host smart-127f4f9c-a906-4291-b505-cc00da2fb2c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976675348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1976675348
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1481244904
Short name T312
Test name
Test status
Simulation time 291038430 ps
CPU time 0.75 seconds
Started Jun 27 06:09:08 PM PDT 24
Finished Jun 27 06:09:10 PM PDT 24
Peak memory 193060 kb
Host smart-74b5fc05-6bf0-490d-8092-20b744a29dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481244904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1481244904
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1855190469
Short name T308
Test name
Test status
Simulation time 304918281 ps
CPU time 1.03 seconds
Started Jun 27 06:09:18 PM PDT 24
Finished Jun 27 06:09:20 PM PDT 24
Peak memory 183568 kb
Host smart-fd88d86c-d577-4098-a5be-c4cd5a589eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855190469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1855190469
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1361561806
Short name T295
Test name
Test status
Simulation time 395035411 ps
CPU time 0.68 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:12 PM PDT 24
Peak memory 183780 kb
Host smart-7f05c600-6ec4-4543-bfbc-fa623fe10610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361561806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1361561806
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3420479336
Short name T363
Test name
Test status
Simulation time 478581372 ps
CPU time 0.91 seconds
Started Jun 27 06:09:08 PM PDT 24
Finished Jun 27 06:09:11 PM PDT 24
Peak memory 183836 kb
Host smart-b652ca96-fe10-445b-b5ad-980157449f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420479336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3420479336
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2997195132
Short name T291
Test name
Test status
Simulation time 442978105 ps
CPU time 1.2 seconds
Started Jun 27 06:09:10 PM PDT 24
Finished Jun 27 06:09:13 PM PDT 24
Peak memory 183796 kb
Host smart-79bd735f-55cf-4521-b61a-5ef3026767b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997195132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2997195132
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.517203718
Short name T375
Test name
Test status
Simulation time 483704813 ps
CPU time 0.89 seconds
Started Jun 27 06:09:18 PM PDT 24
Finished Jun 27 06:09:20 PM PDT 24
Peak memory 193060 kb
Host smart-540763a0-b741-47f9-ac9a-15c0c76c4933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517203718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.517203718
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1976305415
Short name T58
Test name
Test status
Simulation time 485366819 ps
CPU time 1.67 seconds
Started Jun 27 06:08:45 PM PDT 24
Finished Jun 27 06:08:49 PM PDT 24
Peak memory 183800 kb
Host smart-dc0b1388-2a12-4591-9130-8bcd78d09634
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976305415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1976305415
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.705520756
Short name T323
Test name
Test status
Simulation time 7443108791 ps
CPU time 3.08 seconds
Started Jun 27 06:08:42 PM PDT 24
Finished Jun 27 06:08:48 PM PDT 24
Peak memory 192252 kb
Host smart-e9d4caff-51a8-4231-af1f-c2f03cb72319
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705520756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.705520756
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.249809644
Short name T313
Test name
Test status
Simulation time 882588085 ps
CPU time 1.2 seconds
Started Jun 27 06:08:45 PM PDT 24
Finished Jun 27 06:08:49 PM PDT 24
Peak memory 183728 kb
Host smart-c7bf9e3f-17a9-415b-a4ac-712c6f27a071
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249809644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.249809644
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1372532783
Short name T21
Test name
Test status
Simulation time 383939248 ps
CPU time 1.17 seconds
Started Jun 27 06:09:02 PM PDT 24
Finished Jun 27 06:09:05 PM PDT 24
Peak memory 196036 kb
Host smart-9b60e3f3-143a-4534-bf99-b9758e224ad1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372532783 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1372532783
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2828144641
Short name T70
Test name
Test status
Simulation time 445352452 ps
CPU time 0.78 seconds
Started Jun 27 06:08:43 PM PDT 24
Finished Jun 27 06:08:47 PM PDT 24
Peak memory 193352 kb
Host smart-8af4a1f3-d3bc-4dbd-b8de-6f0e6b203fb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828144641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2828144641
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3214054902
Short name T293
Test name
Test status
Simulation time 335870563 ps
CPU time 0.6 seconds
Started Jun 27 06:08:42 PM PDT 24
Finished Jun 27 06:08:46 PM PDT 24
Peak memory 183836 kb
Host smart-dfb4b4fe-d905-46ef-83fb-3f63d2462175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214054902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3214054902
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3632839793
Short name T414
Test name
Test status
Simulation time 543150056 ps
CPU time 0.59 seconds
Started Jun 27 06:08:42 PM PDT 24
Finished Jun 27 06:08:46 PM PDT 24
Peak memory 183748 kb
Host smart-b47f37a8-d431-419d-8b7e-1d182256bca7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632839793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3632839793
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4024011468
Short name T353
Test name
Test status
Simulation time 391009133 ps
CPU time 0.67 seconds
Started Jun 27 06:08:45 PM PDT 24
Finished Jun 27 06:08:48 PM PDT 24
Peak memory 183728 kb
Host smart-d20ce764-e846-42b1-9d7d-2837d263e181
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024011468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.4024011468
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1391586927
Short name T76
Test name
Test status
Simulation time 2047655417 ps
CPU time 1.43 seconds
Started Jun 27 06:08:43 PM PDT 24
Finished Jun 27 06:08:48 PM PDT 24
Peak memory 194104 kb
Host smart-58760e16-af5c-471b-87b6-fbdbc0bedd0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391586927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1391586927
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3956480278
Short name T360
Test name
Test status
Simulation time 953028991 ps
CPU time 2.22 seconds
Started Jun 27 06:08:43 PM PDT 24
Finished Jun 27 06:08:48 PM PDT 24
Peak memory 198632 kb
Host smart-4ab4df68-aa7b-4bdf-9b3c-920fdd8fca04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956480278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3956480278
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1675131094
Short name T189
Test name
Test status
Simulation time 8692247089 ps
CPU time 5.1 seconds
Started Jun 27 06:08:43 PM PDT 24
Finished Jun 27 06:08:52 PM PDT 24
Peak memory 198160 kb
Host smart-8eda9c6b-a968-4caa-b76a-7cd702b40fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675131094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1675131094
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1613296195
Short name T416
Test name
Test status
Simulation time 421734071 ps
CPU time 1.18 seconds
Started Jun 27 06:09:08 PM PDT 24
Finished Jun 27 06:09:11 PM PDT 24
Peak memory 183816 kb
Host smart-5d615d0e-d43a-4443-b8a6-00aa6627866e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613296195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1613296195
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4143362554
Short name T289
Test name
Test status
Simulation time 459398623 ps
CPU time 0.83 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:12 PM PDT 24
Peak memory 183724 kb
Host smart-6d9c512b-92b1-445b-8ffe-c3bc4329d8cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143362554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.4143362554
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.787146585
Short name T333
Test name
Test status
Simulation time 341467846 ps
CPU time 0.81 seconds
Started Jun 27 06:09:08 PM PDT 24
Finished Jun 27 06:09:09 PM PDT 24
Peak memory 183824 kb
Host smart-2733b00f-17bf-4d41-abbc-7482366d7985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787146585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.787146585
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.697593842
Short name T393
Test name
Test status
Simulation time 449828469 ps
CPU time 0.71 seconds
Started Jun 27 06:09:08 PM PDT 24
Finished Jun 27 06:09:10 PM PDT 24
Peak memory 183820 kb
Host smart-72dc7050-ccbe-4c81-8e42-2a2aad6e0b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697593842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.697593842
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3938594372
Short name T407
Test name
Test status
Simulation time 360403366 ps
CPU time 1.1 seconds
Started Jun 27 06:09:09 PM PDT 24
Finished Jun 27 06:09:13 PM PDT 24
Peak memory 183704 kb
Host smart-39498fec-8d56-499d-a99d-7eb45eb78464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938594372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3938594372
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1702013512
Short name T388
Test name
Test status
Simulation time 465332269 ps
CPU time 0.7 seconds
Started Jun 27 06:09:18 PM PDT 24
Finished Jun 27 06:09:20 PM PDT 24
Peak memory 183788 kb
Host smart-742b0233-2e6d-4e8f-a28a-78cda5dc4cfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702013512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1702013512
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.169189710
Short name T321
Test name
Test status
Simulation time 300949352 ps
CPU time 0.67 seconds
Started Jun 27 06:09:31 PM PDT 24
Finished Jun 27 06:09:34 PM PDT 24
Peak memory 193044 kb
Host smart-7f538957-9374-4a93-83a5-eb30662ebcf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169189710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.169189710
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3142811530
Short name T346
Test name
Test status
Simulation time 386762316 ps
CPU time 1.12 seconds
Started Jun 27 06:09:30 PM PDT 24
Finished Jun 27 06:09:34 PM PDT 24
Peak memory 183832 kb
Host smart-581ec0a8-af8e-4a70-87f7-cd35f9d3b671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142811530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3142811530
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3830320254
Short name T309
Test name
Test status
Simulation time 480440425 ps
CPU time 1.18 seconds
Started Jun 27 06:09:30 PM PDT 24
Finished Jun 27 06:09:33 PM PDT 24
Peak memory 193032 kb
Host smart-18ecac74-5d21-46d6-8ff8-e83e1735ebc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830320254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3830320254
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2130291218
Short name T349
Test name
Test status
Simulation time 276944792 ps
CPU time 0.96 seconds
Started Jun 27 06:09:29 PM PDT 24
Finished Jun 27 06:09:33 PM PDT 24
Peak memory 183828 kb
Host smart-8b895506-cb1a-4c1e-8f14-35acf5b8673e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130291218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2130291218
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3086294074
Short name T369
Test name
Test status
Simulation time 423365054 ps
CPU time 1.22 seconds
Started Jun 27 06:08:54 PM PDT 24
Finished Jun 27 06:08:57 PM PDT 24
Peak memory 196020 kb
Host smart-72a1ded8-5668-4390-b000-aa81d258717f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086294074 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3086294074
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2454520344
Short name T53
Test name
Test status
Simulation time 330433286 ps
CPU time 0.89 seconds
Started Jun 27 06:08:59 PM PDT 24
Finished Jun 27 06:09:02 PM PDT 24
Peak memory 193304 kb
Host smart-4a14993e-4f85-4e2e-a237-5cb335e1b7ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454520344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2454520344
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3504653283
Short name T344
Test name
Test status
Simulation time 268114575 ps
CPU time 0.89 seconds
Started Jun 27 06:09:02 PM PDT 24
Finished Jun 27 06:09:04 PM PDT 24
Peak memory 193056 kb
Host smart-e9f9762b-c5c5-42cd-a2bd-dfa5069e200b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504653283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3504653283
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.608951144
Short name T75
Test name
Test status
Simulation time 1104198941 ps
CPU time 2.13 seconds
Started Jun 27 06:08:52 PM PDT 24
Finished Jun 27 06:08:55 PM PDT 24
Peak memory 193536 kb
Host smart-e54d4056-1f6f-4d57-b511-714aabbd8b20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608951144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.608951144
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2085535540
Short name T337
Test name
Test status
Simulation time 467865681 ps
CPU time 1.93 seconds
Started Jun 27 06:08:56 PM PDT 24
Finished Jun 27 06:09:00 PM PDT 24
Peak memory 198688 kb
Host smart-2c0efc1e-ad9a-4e7f-bf9e-de1dc4b0d900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085535540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2085535540
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3015390718
Short name T188
Test name
Test status
Simulation time 7865116807 ps
CPU time 6.4 seconds
Started Jun 27 06:08:53 PM PDT 24
Finished Jun 27 06:09:01 PM PDT 24
Peak memory 198320 kb
Host smart-f6c79718-5b15-4e1b-8d40-330a6b17bda6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015390718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3015390718
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2374964574
Short name T411
Test name
Test status
Simulation time 574349584 ps
CPU time 0.82 seconds
Started Jun 27 06:08:54 PM PDT 24
Finished Jun 27 06:08:56 PM PDT 24
Peak memory 196564 kb
Host smart-6b84b566-bb4f-4edc-a2e9-eee2471cfdee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374964574 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2374964574
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3076317973
Short name T364
Test name
Test status
Simulation time 312972333 ps
CPU time 0.64 seconds
Started Jun 27 06:08:59 PM PDT 24
Finished Jun 27 06:09:01 PM PDT 24
Peak memory 192072 kb
Host smart-4ef209ac-3c3d-44b0-8fd8-a373ea74fc00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076317973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3076317973
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1453792331
Short name T322
Test name
Test status
Simulation time 487346839 ps
CPU time 0.91 seconds
Started Jun 27 06:08:57 PM PDT 24
Finished Jun 27 06:09:00 PM PDT 24
Peak memory 183832 kb
Host smart-23597df0-c8ee-495d-9f45-ea56455a51e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453792331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1453792331
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2600458849
Short name T342
Test name
Test status
Simulation time 2508182740 ps
CPU time 6.54 seconds
Started Jun 27 06:08:55 PM PDT 24
Finished Jun 27 06:09:04 PM PDT 24
Peak memory 195104 kb
Host smart-6d471262-f487-4e52-a2fb-3a1fd81ea694
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600458849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2600458849
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1983367469
Short name T399
Test name
Test status
Simulation time 410359164 ps
CPU time 1.76 seconds
Started Jun 27 06:09:01 PM PDT 24
Finished Jun 27 06:09:05 PM PDT 24
Peak memory 198632 kb
Host smart-49f98465-6ed5-48f8-8bed-5bf9490c1ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983367469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1983367469
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3973023729
Short name T397
Test name
Test status
Simulation time 8226196542 ps
CPU time 4.09 seconds
Started Jun 27 06:08:52 PM PDT 24
Finished Jun 27 06:08:57 PM PDT 24
Peak memory 198412 kb
Host smart-2f67cef3-dfb5-4c8b-9712-fbd08a3c1995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973023729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3973023729
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.841630949
Short name T25
Test name
Test status
Simulation time 406145882 ps
CPU time 0.78 seconds
Started Jun 27 06:09:01 PM PDT 24
Finished Jun 27 06:09:03 PM PDT 24
Peak memory 195232 kb
Host smart-52fbe4c4-6a5f-4e3a-a119-d9ff091517fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841630949 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.841630949
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.4100328108
Short name T193
Test name
Test status
Simulation time 472824182 ps
CPU time 1.21 seconds
Started Jun 27 06:09:02 PM PDT 24
Finished Jun 27 06:09:05 PM PDT 24
Peak memory 192096 kb
Host smart-19f3b9e4-7ae2-4071-a52d-73d5787674e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100328108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.4100328108
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3147162721
Short name T300
Test name
Test status
Simulation time 475954314 ps
CPU time 1.11 seconds
Started Jun 27 06:08:54 PM PDT 24
Finished Jun 27 06:08:57 PM PDT 24
Peak memory 183832 kb
Host smart-238dbde3-d78b-42e0-b7ed-0aa117d3fb48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147162721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3147162721
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2638119397
Short name T391
Test name
Test status
Simulation time 2083188304 ps
CPU time 3.11 seconds
Started Jun 27 06:09:02 PM PDT 24
Finished Jun 27 06:09:07 PM PDT 24
Peak memory 193900 kb
Host smart-90f9fb29-9f9c-4009-89d5-5f6d09404c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638119397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2638119397
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3235847256
Short name T338
Test name
Test status
Simulation time 494147566 ps
CPU time 1.53 seconds
Started Jun 27 06:08:54 PM PDT 24
Finished Jun 27 06:08:58 PM PDT 24
Peak memory 198612 kb
Host smart-56ecf3ff-5e49-4ea1-8180-9a385d9e5bec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235847256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3235847256
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.61936641
Short name T186
Test name
Test status
Simulation time 4353728246 ps
CPU time 2.26 seconds
Started Jun 27 06:08:53 PM PDT 24
Finished Jun 27 06:08:57 PM PDT 24
Peak memory 197836 kb
Host smart-8e5d8362-5b63-40fc-bc3a-9abf28aa442e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61936641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_i
ntg_err.61936641
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1841318472
Short name T314
Test name
Test status
Simulation time 384517285 ps
CPU time 0.98 seconds
Started Jun 27 06:08:56 PM PDT 24
Finished Jun 27 06:08:59 PM PDT 24
Peak memory 195984 kb
Host smart-081ff3d4-fd1e-4400-9abb-783628720c0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841318472 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1841318472
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2209172840
Short name T345
Test name
Test status
Simulation time 553234816 ps
CPU time 1.2 seconds
Started Jun 27 06:08:53 PM PDT 24
Finished Jun 27 06:08:56 PM PDT 24
Peak memory 193496 kb
Host smart-4b9bb7d2-9292-422c-9497-13fa4be2a2df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209172840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2209172840
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3363824423
Short name T417
Test name
Test status
Simulation time 518603393 ps
CPU time 1.22 seconds
Started Jun 27 06:08:52 PM PDT 24
Finished Jun 27 06:08:55 PM PDT 24
Peak memory 193024 kb
Host smart-9426d82a-05f3-4a15-b35e-bfb102b7e474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363824423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3363824423
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3738831898
Short name T72
Test name
Test status
Simulation time 2756630692 ps
CPU time 1.57 seconds
Started Jun 27 06:08:54 PM PDT 24
Finished Jun 27 06:08:58 PM PDT 24
Peak memory 192076 kb
Host smart-7682cb29-a341-4277-825a-cb1ccddfa6de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738831898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3738831898
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1439978150
Short name T348
Test name
Test status
Simulation time 2109326990 ps
CPU time 1.9 seconds
Started Jun 27 06:08:54 PM PDT 24
Finished Jun 27 06:08:58 PM PDT 24
Peak memory 198656 kb
Host smart-66024230-49ff-476b-9803-91e115610f21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439978150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1439978150
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2451210686
Short name T401
Test name
Test status
Simulation time 4483495167 ps
CPU time 1.45 seconds
Started Jun 27 06:09:02 PM PDT 24
Finished Jun 27 06:09:05 PM PDT 24
Peak memory 196800 kb
Host smart-7521ff18-b253-4570-b909-1ef571de8f54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451210686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2451210686
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.173254253
Short name T371
Test name
Test status
Simulation time 602133213 ps
CPU time 1.06 seconds
Started Jun 27 06:09:00 PM PDT 24
Finished Jun 27 06:09:03 PM PDT 24
Peak memory 198424 kb
Host smart-8eac02bc-a552-4aff-8e5b-07ae80cd09e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173254253 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.173254253
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2781801989
Short name T334
Test name
Test status
Simulation time 467573421 ps
CPU time 0.83 seconds
Started Jun 27 06:08:53 PM PDT 24
Finished Jun 27 06:08:55 PM PDT 24
Peak memory 193020 kb
Host smart-12a7df47-1117-4d4b-bad0-5cdd62d46eb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781801989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2781801989
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.4178528073
Short name T283
Test name
Test status
Simulation time 411917900 ps
CPU time 0.71 seconds
Started Jun 27 06:09:01 PM PDT 24
Finished Jun 27 06:09:04 PM PDT 24
Peak memory 183832 kb
Host smart-e6972659-8848-4162-89d0-0bd4f710c0c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178528073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.4178528073
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2798795129
Short name T408
Test name
Test status
Simulation time 1054070194 ps
CPU time 1.86 seconds
Started Jun 27 06:08:52 PM PDT 24
Finished Jun 27 06:08:55 PM PDT 24
Peak memory 193816 kb
Host smart-a16d6c6d-fecc-4872-882b-79ca009587b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798795129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2798795129
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.878829576
Short name T292
Test name
Test status
Simulation time 538450285 ps
CPU time 1.8 seconds
Started Jun 27 06:09:02 PM PDT 24
Finished Jun 27 06:09:06 PM PDT 24
Peak memory 198608 kb
Host smart-ed712c31-41b3-4195-bf71-ff028dab4a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878829576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.878829576
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2381035741
Short name T359
Test name
Test status
Simulation time 4867016273 ps
CPU time 4.19 seconds
Started Jun 27 06:08:57 PM PDT 24
Finished Jun 27 06:09:03 PM PDT 24
Peak memory 198012 kb
Host smart-ae764aa5-5363-425a-8f90-cece18de2a84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381035741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2381035741
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3045553272
Short name T220
Test name
Test status
Simulation time 17087574885 ps
CPU time 4.7 seconds
Started Jun 27 06:02:56 PM PDT 24
Finished Jun 27 06:03:02 PM PDT 24
Peak memory 196656 kb
Host smart-432c5998-ceb2-4306-8143-b044a9a8830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045553272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3045553272
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.826553291
Short name T216
Test name
Test status
Simulation time 593929698 ps
CPU time 0.75 seconds
Started Jun 27 06:02:58 PM PDT 24
Finished Jun 27 06:03:00 PM PDT 24
Peak memory 191612 kb
Host smart-0ae6d0c1-b9a2-404e-85e6-4b1ba52ea50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826553291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.826553291
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3077467791
Short name T64
Test name
Test status
Simulation time 13180934507 ps
CPU time 9.79 seconds
Started Jun 27 06:02:55 PM PDT 24
Finished Jun 27 06:03:06 PM PDT 24
Peak memory 191648 kb
Host smart-c381d395-cecd-4525-9620-a170e7f6f7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077467791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3077467791
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1918390596
Short name T18
Test name
Test status
Simulation time 4115550106 ps
CPU time 2.25 seconds
Started Jun 27 06:02:53 PM PDT 24
Finished Jun 27 06:02:57 PM PDT 24
Peak memory 215392 kb
Host smart-3afd8109-13dd-4edd-9a0f-174565c6d514
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918390596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1918390596
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2885761930
Short name T268
Test name
Test status
Simulation time 462028884 ps
CPU time 0.77 seconds
Started Jun 27 06:02:58 PM PDT 24
Finished Jun 27 06:03:00 PM PDT 24
Peak memory 196552 kb
Host smart-a8ac2894-d420-4f73-9fdc-fca9eaae01d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885761930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2885761930
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1878564930
Short name T237
Test name
Test status
Simulation time 40330395624 ps
CPU time 50.21 seconds
Started Jun 27 06:03:12 PM PDT 24
Finished Jun 27 06:04:05 PM PDT 24
Peak memory 191712 kb
Host smart-f3edcc4a-38cf-4694-92f4-26bd7f3a6a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878564930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1878564930
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3391409376
Short name T197
Test name
Test status
Simulation time 443840733 ps
CPU time 0.68 seconds
Started Jun 27 06:03:14 PM PDT 24
Finished Jun 27 06:03:17 PM PDT 24
Peak memory 191580 kb
Host smart-132393d2-af9d-4f24-88a7-2bc29d6b1c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391409376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3391409376
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1597064493
Short name T207
Test name
Test status
Simulation time 30586728350 ps
CPU time 9.55 seconds
Started Jun 27 06:03:13 PM PDT 24
Finished Jun 27 06:03:25 PM PDT 24
Peak memory 191652 kb
Host smart-2dd2c5c2-3b20-4010-b618-3a7d5fd458f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597064493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1597064493
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.339815341
Short name T213
Test name
Test status
Simulation time 397339526 ps
CPU time 1.13 seconds
Started Jun 27 06:03:15 PM PDT 24
Finished Jun 27 06:03:19 PM PDT 24
Peak memory 196516 kb
Host smart-1226a2e6-0cff-4161-bf7d-199f449b49f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339815341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.339815341
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2677077650
Short name T127
Test name
Test status
Simulation time 575311502 ps
CPU time 1.28 seconds
Started Jun 27 06:03:16 PM PDT 24
Finished Jun 27 06:03:22 PM PDT 24
Peak memory 196488 kb
Host smart-f12b0fae-913e-4c64-92b0-c7874bb8615d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677077650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2677077650
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1278662525
Short name T49
Test name
Test status
Simulation time 33164233378 ps
CPU time 45.28 seconds
Started Jun 27 06:03:13 PM PDT 24
Finished Jun 27 06:04:02 PM PDT 24
Peak memory 191724 kb
Host smart-c4ddd2e8-bd54-4c56-a83d-a4245cab3e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278662525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1278662525
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2295097044
Short name T203
Test name
Test status
Simulation time 497468075 ps
CPU time 1.33 seconds
Started Jun 27 06:03:17 PM PDT 24
Finished Jun 27 06:03:23 PM PDT 24
Peak memory 196556 kb
Host smart-eb3c0632-e124-4242-9b66-4deb99561374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295097044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2295097044
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3983969466
Short name T86
Test name
Test status
Simulation time 31848241690 ps
CPU time 247.67 seconds
Started Jun 27 06:03:16 PM PDT 24
Finished Jun 27 06:07:28 PM PDT 24
Peak memory 206644 kb
Host smart-045d0de3-5e2f-43c6-bab7-a3940e1fc39a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983969466 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3983969466
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1533688644
Short name T232
Test name
Test status
Simulation time 9264891239 ps
CPU time 3.92 seconds
Started Jun 27 06:03:15 PM PDT 24
Finished Jun 27 06:03:23 PM PDT 24
Peak memory 196704 kb
Host smart-a36e3f03-1cbd-497f-9753-59f00ba13dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533688644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1533688644
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1649548088
Short name T211
Test name
Test status
Simulation time 420439026 ps
CPU time 0.78 seconds
Started Jun 27 06:03:15 PM PDT 24
Finished Jun 27 06:03:19 PM PDT 24
Peak memory 191668 kb
Host smart-ab6f9f59-bde6-44ff-a5ae-f95e361cf43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649548088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1649548088
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3350537750
Short name T175
Test name
Test status
Simulation time 555384541 ps
CPU time 1.34 seconds
Started Jun 27 06:03:15 PM PDT 24
Finished Jun 27 06:03:20 PM PDT 24
Peak memory 196404 kb
Host smart-3c2315a8-9d16-4abe-890f-2d5d82a0d496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350537750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3350537750
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3785666991
Short name T1
Test name
Test status
Simulation time 15376666459 ps
CPU time 5.09 seconds
Started Jun 27 06:03:16 PM PDT 24
Finished Jun 27 06:03:26 PM PDT 24
Peak memory 191688 kb
Host smart-e8da6908-88cb-4a2c-8bb0-5be565bd63cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785666991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3785666991
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1390818823
Short name T270
Test name
Test status
Simulation time 542915307 ps
CPU time 0.99 seconds
Started Jun 27 06:03:15 PM PDT 24
Finished Jun 27 06:03:20 PM PDT 24
Peak memory 196480 kb
Host smart-e226068f-908f-4014-b359-39c86e692637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390818823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1390818823
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.901270208
Short name T200
Test name
Test status
Simulation time 22983833807 ps
CPU time 34.41 seconds
Started Jun 27 06:03:35 PM PDT 24
Finished Jun 27 06:04:12 PM PDT 24
Peak memory 191740 kb
Host smart-fea634ee-9d0a-45b7-9a94-7d451eebade2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901270208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.901270208
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2396497391
Short name T195
Test name
Test status
Simulation time 448055546 ps
CPU time 0.73 seconds
Started Jun 27 06:03:15 PM PDT 24
Finished Jun 27 06:03:20 PM PDT 24
Peak memory 196420 kb
Host smart-52085f00-380e-4521-91b1-78838be4b755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396497391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2396497391
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3164775622
Short name T221
Test name
Test status
Simulation time 4756651450 ps
CPU time 3.82 seconds
Started Jun 27 06:03:33 PM PDT 24
Finished Jun 27 06:03:39 PM PDT 24
Peak memory 191708 kb
Host smart-36b880e9-9496-40f8-9a32-e5f09a38126b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164775622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3164775622
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1347219168
Short name T155
Test name
Test status
Simulation time 398014010 ps
CPU time 1.14 seconds
Started Jun 27 06:03:36 PM PDT 24
Finished Jun 27 06:03:41 PM PDT 24
Peak memory 191676 kb
Host smart-b74b7ee2-ad12-45d1-b3fe-3ff1a3feb754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347219168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1347219168
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.883353162
Short name T233
Test name
Test status
Simulation time 49853752833 ps
CPU time 58.73 seconds
Started Jun 27 06:03:35 PM PDT 24
Finished Jun 27 06:04:37 PM PDT 24
Peak memory 196716 kb
Host smart-314b8e3b-1137-42db-9e41-1fb30a0c607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883353162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.883353162
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1953559700
Short name T278
Test name
Test status
Simulation time 576414303 ps
CPU time 0.93 seconds
Started Jun 27 06:03:33 PM PDT 24
Finished Jun 27 06:03:37 PM PDT 24
Peak memory 191580 kb
Host smart-bb93024e-c8cb-4efa-83bd-b557ec3de846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953559700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1953559700
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1356336100
Short name T266
Test name
Test status
Simulation time 18169713975 ps
CPU time 6.7 seconds
Started Jun 27 06:03:33 PM PDT 24
Finished Jun 27 06:03:43 PM PDT 24
Peak memory 191728 kb
Host smart-8a15aad9-98bd-4bb3-9e65-2f8794657b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356336100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1356336100
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1429564001
Short name T228
Test name
Test status
Simulation time 506451237 ps
CPU time 0.78 seconds
Started Jun 27 06:03:35 PM PDT 24
Finished Jun 27 06:03:39 PM PDT 24
Peak memory 196460 kb
Host smart-a274b389-323e-460d-a3f5-8958ad762e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429564001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1429564001
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3260240794
Short name T196
Test name
Test status
Simulation time 4932798678 ps
CPU time 4.27 seconds
Started Jun 27 06:03:39 PM PDT 24
Finished Jun 27 06:03:47 PM PDT 24
Peak memory 191412 kb
Host smart-4d10e523-7adc-455e-871b-22faaa388fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260240794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3260240794
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3567450676
Short name T205
Test name
Test status
Simulation time 434361569 ps
CPU time 1.24 seconds
Started Jun 27 06:03:33 PM PDT 24
Finished Jun 27 06:03:36 PM PDT 24
Peak memory 196464 kb
Host smart-e294c5c3-2d1f-4712-99fc-a76d2d7edb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567450676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3567450676
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2632747885
Short name T239
Test name
Test status
Simulation time 24631745427 ps
CPU time 36.1 seconds
Started Jun 27 06:02:56 PM PDT 24
Finished Jun 27 06:03:34 PM PDT 24
Peak memory 191728 kb
Host smart-71731795-8870-427a-92d1-646e5670853c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632747885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2632747885
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3556265271
Short name T16
Test name
Test status
Simulation time 4203357073 ps
CPU time 6.78 seconds
Started Jun 27 06:02:53 PM PDT 24
Finished Jun 27 06:03:00 PM PDT 24
Peak memory 215320 kb
Host smart-5e0ab604-7413-47e0-88da-d77a612927e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556265271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3556265271
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2156871853
Short name T235
Test name
Test status
Simulation time 509018836 ps
CPU time 1.36 seconds
Started Jun 27 06:03:00 PM PDT 24
Finished Jun 27 06:03:02 PM PDT 24
Peak memory 196500 kb
Host smart-ad13aed2-cb86-4285-aeb4-504bad677842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156871853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2156871853
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.291730590
Short name T85
Test name
Test status
Simulation time 14590580452 ps
CPU time 105.89 seconds
Started Jun 27 06:03:09 PM PDT 24
Finished Jun 27 06:04:56 PM PDT 24
Peak memory 206544 kb
Host smart-f7a98883-b156-449f-92b8-0bb8766e3064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291730590 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.291730590
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.170330975
Short name T63
Test name
Test status
Simulation time 5058158631 ps
CPU time 4.69 seconds
Started Jun 27 06:03:34 PM PDT 24
Finished Jun 27 06:03:42 PM PDT 24
Peak memory 191716 kb
Host smart-c09ccb7a-07cc-418f-8f83-cf9e559bbcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170330975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.170330975
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.4034735783
Short name T206
Test name
Test status
Simulation time 574039084 ps
CPU time 1.43 seconds
Started Jun 27 06:03:34 PM PDT 24
Finished Jun 27 06:03:39 PM PDT 24
Peak memory 196500 kb
Host smart-7a255c38-abb2-4c7d-baab-679b9d0faf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034735783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.4034735783
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1469871378
Short name T223
Test name
Test status
Simulation time 28075711008 ps
CPU time 20.71 seconds
Started Jun 27 06:03:38 PM PDT 24
Finished Jun 27 06:04:03 PM PDT 24
Peak memory 191696 kb
Host smart-b3c2e311-cc66-402f-8784-13ecf66c9fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469871378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1469871378
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2546174013
Short name T46
Test name
Test status
Simulation time 582472758 ps
CPU time 0.76 seconds
Started Jun 27 06:03:35 PM PDT 24
Finished Jun 27 06:03:39 PM PDT 24
Peak memory 191684 kb
Host smart-30a2834a-2686-408a-810c-140c2f5a5f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546174013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2546174013
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3247794951
Short name T32
Test name
Test status
Simulation time 85163015209 ps
CPU time 808.54 seconds
Started Jun 27 06:03:35 PM PDT 24
Finished Jun 27 06:17:07 PM PDT 24
Peak memory 207228 kb
Host smart-96068f4d-58e4-490d-80ba-9c6fbcb309d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247794951 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3247794951
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1407731722
Short name T33
Test name
Test status
Simulation time 38387345356 ps
CPU time 55.95 seconds
Started Jun 27 06:03:34 PM PDT 24
Finished Jun 27 06:04:33 PM PDT 24
Peak memory 191712 kb
Host smart-2816474d-c513-4c6f-999c-3c28276b6827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407731722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1407731722
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3942630142
Short name T250
Test name
Test status
Simulation time 352872401 ps
CPU time 0.84 seconds
Started Jun 27 06:03:34 PM PDT 24
Finished Jun 27 06:03:37 PM PDT 24
Peak memory 196464 kb
Host smart-68330874-6380-4468-b9bb-17f9b42ebe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942630142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3942630142
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3706757388
Short name T262
Test name
Test status
Simulation time 32247967777 ps
CPU time 12.84 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:03:54 PM PDT 24
Peak memory 196752 kb
Host smart-e13dac44-cd25-49ee-8d76-b3f6a800a4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706757388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3706757388
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1496789604
Short name T209
Test name
Test status
Simulation time 518227750 ps
CPU time 1.27 seconds
Started Jun 27 06:03:33 PM PDT 24
Finished Jun 27 06:03:37 PM PDT 24
Peak memory 191668 kb
Host smart-30052a69-dfca-4646-86bd-bc16921b3ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496789604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1496789604
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2219334172
Short name T231
Test name
Test status
Simulation time 16892940824 ps
CPU time 22.4 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:04:04 PM PDT 24
Peak memory 191692 kb
Host smart-0c608850-123a-465b-a0cd-eb0f999db650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219334172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2219334172
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2375740853
Short name T45
Test name
Test status
Simulation time 418094958 ps
CPU time 0.69 seconds
Started Jun 27 06:03:36 PM PDT 24
Finished Jun 27 06:03:41 PM PDT 24
Peak memory 196548 kb
Host smart-1f31a5cb-6262-4e67-9095-658c242a6a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375740853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2375740853
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2361326309
Short name T164
Test name
Test status
Simulation time 373854397 ps
CPU time 0.73 seconds
Started Jun 27 06:03:35 PM PDT 24
Finished Jun 27 06:03:39 PM PDT 24
Peak memory 196548 kb
Host smart-417cd468-6efc-4725-a2e5-6bd3e3e4256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361326309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2361326309
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1253807154
Short name T246
Test name
Test status
Simulation time 40287145802 ps
CPU time 20.66 seconds
Started Jun 27 06:03:35 PM PDT 24
Finished Jun 27 06:03:59 PM PDT 24
Peak memory 191740 kb
Host smart-17d95549-6d54-43cd-9be4-e22abaf0965a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253807154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1253807154
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.387150332
Short name T251
Test name
Test status
Simulation time 337655208 ps
CPU time 1.02 seconds
Started Jun 27 06:03:36 PM PDT 24
Finished Jun 27 06:03:42 PM PDT 24
Peak memory 191500 kb
Host smart-db720167-79da-425d-9ea2-84f0827e777e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387150332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.387150332
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3847863611
Short name T61
Test name
Test status
Simulation time 4364470333 ps
CPU time 0.94 seconds
Started Jun 27 06:03:42 PM PDT 24
Finished Jun 27 06:03:46 PM PDT 24
Peak memory 191700 kb
Host smart-5911ca79-2ad7-4322-b5d6-da92ab9f2c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847863611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3847863611
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.469551880
Short name T210
Test name
Test status
Simulation time 501154086 ps
CPU time 1.26 seconds
Started Jun 27 06:03:32 PM PDT 24
Finished Jun 27 06:03:35 PM PDT 24
Peak memory 191576 kb
Host smart-b772ac92-476a-4ee2-ae87-2f0ef3e9c643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469551880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.469551880
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3909299576
Short name T227
Test name
Test status
Simulation time 11291993578 ps
CPU time 2.12 seconds
Started Jun 27 06:03:41 PM PDT 24
Finished Jun 27 06:03:46 PM PDT 24
Peak memory 191704 kb
Host smart-fa279b28-c749-454f-9d33-87fece9aba85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909299576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3909299576
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.734736210
Short name T272
Test name
Test status
Simulation time 374582707 ps
CPU time 1.1 seconds
Started Jun 27 06:03:38 PM PDT 24
Finished Jun 27 06:03:43 PM PDT 24
Peak memory 196412 kb
Host smart-10c8b026-c403-4065-8006-8d1d34607319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734736210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.734736210
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.484733882
Short name T267
Test name
Test status
Simulation time 27849050508 ps
CPU time 12.4 seconds
Started Jun 27 06:03:35 PM PDT 24
Finished Jun 27 06:03:51 PM PDT 24
Peak memory 196732 kb
Host smart-1578b070-b95e-482c-a249-b1b50c1e9883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484733882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.484733882
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1744900056
Short name T243
Test name
Test status
Simulation time 351086610 ps
CPU time 0.81 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:03:42 PM PDT 24
Peak memory 191872 kb
Host smart-eae93d18-6ea9-4a1d-9eff-d9753824f7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744900056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1744900056
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1413744480
Short name T41
Test name
Test status
Simulation time 510163647 ps
CPU time 1.06 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:03:42 PM PDT 24
Peak memory 196492 kb
Host smart-e1d81edd-cf31-42af-a695-507344eaed45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413744480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1413744480
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3904674457
Short name T241
Test name
Test status
Simulation time 16747669009 ps
CPU time 23.73 seconds
Started Jun 27 06:03:38 PM PDT 24
Finished Jun 27 06:04:06 PM PDT 24
Peak memory 191664 kb
Host smart-16353195-97c3-40b8-8de8-6ce1b31b51a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904674457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3904674457
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.736760373
Short name T240
Test name
Test status
Simulation time 448115611 ps
CPU time 1.28 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:03:43 PM PDT 24
Peak memory 191672 kb
Host smart-1e15388b-1bc9-49ec-ba78-2e737f982470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736760373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.736760373
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2871649057
Short name T269
Test name
Test status
Simulation time 25216991519 ps
CPU time 9.37 seconds
Started Jun 27 06:02:55 PM PDT 24
Finished Jun 27 06:03:05 PM PDT 24
Peak memory 196756 kb
Host smart-706dd0ad-9a8f-45a3-8e03-e87c9a82fd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871649057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2871649057
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.449140122
Short name T17
Test name
Test status
Simulation time 4426554517 ps
CPU time 1.28 seconds
Started Jun 27 06:02:55 PM PDT 24
Finished Jun 27 06:02:58 PM PDT 24
Peak memory 215608 kb
Host smart-b5fe6a28-4468-4a0c-97bc-63b8921cc79e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449140122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.449140122
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2485022385
Short name T202
Test name
Test status
Simulation time 467721132 ps
CPU time 0.68 seconds
Started Jun 27 06:02:54 PM PDT 24
Finished Jun 27 06:02:56 PM PDT 24
Peak memory 191608 kb
Host smart-8ef884fa-a45f-4e1d-b6e8-555d162bcbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485022385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2485022385
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.322667999
Short name T229
Test name
Test status
Simulation time 9760056689 ps
CPU time 3.25 seconds
Started Jun 27 06:03:41 PM PDT 24
Finished Jun 27 06:03:47 PM PDT 24
Peak memory 191732 kb
Host smart-ec7790f2-024c-482d-a3e3-3b54b6ce6c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322667999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.322667999
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1575345024
Short name T274
Test name
Test status
Simulation time 584103321 ps
CPU time 1.26 seconds
Started Jun 27 06:03:37 PM PDT 24
Finished Jun 27 06:03:43 PM PDT 24
Peak memory 191600 kb
Host smart-7d674632-3bf7-4330-85a8-3bd285fe8f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575345024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1575345024
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.435117842
Short name T201
Test name
Test status
Simulation time 39593841024 ps
CPU time 51.69 seconds
Started Jun 27 06:03:40 PM PDT 24
Finished Jun 27 06:04:35 PM PDT 24
Peak memory 196752 kb
Host smart-ab1de4d4-e9b6-463b-96f2-706b8e45084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435117842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.435117842
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.958048630
Short name T212
Test name
Test status
Simulation time 395969865 ps
CPU time 0.65 seconds
Started Jun 27 06:03:40 PM PDT 24
Finished Jun 27 06:03:44 PM PDT 24
Peak memory 191668 kb
Host smart-07b769cd-4db2-4eb5-ae2e-0ff57cf975ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958048630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.958048630
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1007208665
Short name T258
Test name
Test status
Simulation time 31958238387 ps
CPU time 4.25 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:04 PM PDT 24
Peak memory 191724 kb
Host smart-f44e5991-bfd0-412f-a9cd-ec7872c5c0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007208665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1007208665
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3339375925
Short name T249
Test name
Test status
Simulation time 588612639 ps
CPU time 0.76 seconds
Started Jun 27 06:03:56 PM PDT 24
Finished Jun 27 06:03:59 PM PDT 24
Peak memory 196496 kb
Host smart-c53e5f94-f950-4a3a-83d0-f1faf49ae5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339375925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3339375925
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.4021068625
Short name T252
Test name
Test status
Simulation time 28046049008 ps
CPU time 6.35 seconds
Started Jun 27 06:03:55 PM PDT 24
Finished Jun 27 06:04:03 PM PDT 24
Peak memory 196740 kb
Host smart-6bb136b6-d0cc-4ac3-b1cd-c852f8233b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021068625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.4021068625
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.449121387
Short name T69
Test name
Test status
Simulation time 583451737 ps
CPU time 1.52 seconds
Started Jun 27 06:03:58 PM PDT 24
Finished Jun 27 06:04:03 PM PDT 24
Peak memory 191620 kb
Host smart-1fad19f3-3294-4d93-bf92-98210d7b8932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449121387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.449121387
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.618565637
Short name T219
Test name
Test status
Simulation time 6763170482 ps
CPU time 9.95 seconds
Started Jun 27 06:03:56 PM PDT 24
Finished Jun 27 06:04:09 PM PDT 24
Peak memory 191712 kb
Host smart-ae3e1750-fb7c-4ebd-8a28-a5329454181e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618565637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.618565637
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.944083572
Short name T208
Test name
Test status
Simulation time 503788430 ps
CPU time 0.78 seconds
Started Jun 27 06:03:55 PM PDT 24
Finished Jun 27 06:03:57 PM PDT 24
Peak memory 191620 kb
Host smart-772f004d-5ca7-42d0-96bc-a6e9eb8c0c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944083572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.944083572
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2613261349
Short name T214
Test name
Test status
Simulation time 20898364481 ps
CPU time 7.81 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:07 PM PDT 24
Peak memory 191732 kb
Host smart-5cb77d14-46c9-4e14-828c-80e13d04000e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613261349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2613261349
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2789955706
Short name T271
Test name
Test status
Simulation time 370887035 ps
CPU time 0.83 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:01 PM PDT 24
Peak memory 196412 kb
Host smart-da8e816b-87d6-415d-9452-5e0b58e18d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789955706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2789955706
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3190786592
Short name T44
Test name
Test status
Simulation time 29685380459 ps
CPU time 39.67 seconds
Started Jun 27 06:03:55 PM PDT 24
Finished Jun 27 06:04:36 PM PDT 24
Peak memory 191740 kb
Host smart-8074617c-7fc8-4835-8150-e15a8782b316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190786592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3190786592
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3382322466
Short name T276
Test name
Test status
Simulation time 449337087 ps
CPU time 1.21 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:01 PM PDT 24
Peak memory 191672 kb
Host smart-3cafea90-87f0-4b41-a599-58c714091d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382322466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3382322466
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3937467065
Short name T260
Test name
Test status
Simulation time 37621265210 ps
CPU time 49.28 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:49 PM PDT 24
Peak memory 191728 kb
Host smart-05b7a88f-6bab-45db-bea9-2d6b9019d7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937467065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3937467065
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2703887958
Short name T259
Test name
Test status
Simulation time 516195525 ps
CPU time 1.39 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:01 PM PDT 24
Peak memory 191672 kb
Host smart-546e193d-369d-47c7-a5a0-48b3d72db286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703887958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2703887958
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3984441086
Short name T264
Test name
Test status
Simulation time 3891638155 ps
CPU time 5.56 seconds
Started Jun 27 06:03:55 PM PDT 24
Finished Jun 27 06:04:02 PM PDT 24
Peak memory 191732 kb
Host smart-c85b6610-20e0-45c1-95aa-14e87fe7e79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984441086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3984441086
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3646191081
Short name T242
Test name
Test status
Simulation time 558863615 ps
CPU time 0.79 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:01 PM PDT 24
Peak memory 196540 kb
Host smart-d2e2398f-43ff-4aad-b17f-d41b54959400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646191081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3646191081
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.4087344166
Short name T204
Test name
Test status
Simulation time 18510134564 ps
CPU time 14.95 seconds
Started Jun 27 06:03:58 PM PDT 24
Finished Jun 27 06:04:16 PM PDT 24
Peak memory 196744 kb
Host smart-63c9d959-eeea-475f-b854-6b658e9c0b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087344166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.4087344166
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1729466810
Short name T222
Test name
Test status
Simulation time 401017381 ps
CPU time 1.18 seconds
Started Jun 27 06:03:58 PM PDT 24
Finished Jun 27 06:04:03 PM PDT 24
Peak memory 191668 kb
Host smart-4514bdd9-792e-4265-8a49-d0bd106af66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729466810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1729466810
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.327048515
Short name T238
Test name
Test status
Simulation time 13135373437 ps
CPU time 17.15 seconds
Started Jun 27 06:02:57 PM PDT 24
Finished Jun 27 06:03:16 PM PDT 24
Peak memory 191724 kb
Host smart-0c0ae25a-116c-489d-bea1-95a87b2d277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327048515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.327048515
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2111142601
Short name T15
Test name
Test status
Simulation time 3978326894 ps
CPU time 3.46 seconds
Started Jun 27 06:03:00 PM PDT 24
Finished Jun 27 06:03:05 PM PDT 24
Peak memory 215404 kb
Host smart-18f78fba-14c5-4625-a44a-1ebd793823c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111142601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2111142601
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.108489513
Short name T194
Test name
Test status
Simulation time 453790517 ps
CPU time 0.64 seconds
Started Jun 27 06:02:58 PM PDT 24
Finished Jun 27 06:03:00 PM PDT 24
Peak memory 191612 kb
Host smart-677122a7-d219-4741-9da0-2ffff3b1c637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108489513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.108489513
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.334627825
Short name T248
Test name
Test status
Simulation time 60316754540 ps
CPU time 77.95 seconds
Started Jun 27 06:03:58 PM PDT 24
Finished Jun 27 06:05:19 PM PDT 24
Peak memory 196756 kb
Host smart-668de330-b814-464d-94de-f9347710b0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334627825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.334627825
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2537466279
Short name T254
Test name
Test status
Simulation time 378029800 ps
CPU time 1.09 seconds
Started Jun 27 06:03:55 PM PDT 24
Finished Jun 27 06:03:58 PM PDT 24
Peak memory 191692 kb
Host smart-72c1cbe7-ef22-4043-8a20-26a9321770cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537466279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2537466279
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_jump.192822960
Short name T179
Test name
Test status
Simulation time 554582424 ps
CPU time 0.8 seconds
Started Jun 27 06:03:59 PM PDT 24
Finished Jun 27 06:04:04 PM PDT 24
Peak memory 196436 kb
Host smart-59688d01-34c5-4983-bab4-7dd064505c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192822960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.192822960
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1133279958
Short name T280
Test name
Test status
Simulation time 1676450880 ps
CPU time 1.83 seconds
Started Jun 27 06:04:03 PM PDT 24
Finished Jun 27 06:04:07 PM PDT 24
Peak memory 196196 kb
Host smart-a06fb496-1b11-428e-89dc-cc7316ab3c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133279958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1133279958
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3829443298
Short name T10
Test name
Test status
Simulation time 455690852 ps
CPU time 0.81 seconds
Started Jun 27 06:03:59 PM PDT 24
Finished Jun 27 06:04:03 PM PDT 24
Peak memory 196528 kb
Host smart-2ec74291-a21a-4a0a-9e8f-b85f16cbc244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829443298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3829443298
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3709941607
Short name T256
Test name
Test status
Simulation time 89788471829 ps
CPU time 258.69 seconds
Started Jun 27 06:03:59 PM PDT 24
Finished Jun 27 06:08:21 PM PDT 24
Peak memory 200844 kb
Host smart-d3e1f688-de26-49d5-982f-72e31f8bcf42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709941607 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3709941607
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1958452222
Short name T184
Test name
Test status
Simulation time 438482114 ps
CPU time 0.94 seconds
Started Jun 27 06:03:58 PM PDT 24
Finished Jun 27 06:04:02 PM PDT 24
Peak memory 196424 kb
Host smart-e183ef4c-9438-412f-b316-8f2dad133418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958452222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1958452222
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3280371106
Short name T215
Test name
Test status
Simulation time 6149753833 ps
CPU time 10.64 seconds
Started Jun 27 06:03:57 PM PDT 24
Finished Jun 27 06:04:11 PM PDT 24
Peak memory 191720 kb
Host smart-62ab6d5d-ff01-42a3-890d-5cd584d3c179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280371106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3280371106
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1731475945
Short name T261
Test name
Test status
Simulation time 466322802 ps
CPU time 1.29 seconds
Started Jun 27 06:03:59 PM PDT 24
Finished Jun 27 06:04:04 PM PDT 24
Peak memory 196528 kb
Host smart-f4380f9c-a1d5-4e8a-80ea-ec81706d742a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731475945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1731475945
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4136101322
Short name T176
Test name
Test status
Simulation time 432116622 ps
CPU time 1.29 seconds
Started Jun 27 06:03:59 PM PDT 24
Finished Jun 27 06:04:04 PM PDT 24
Peak memory 196472 kb
Host smart-9326f653-f30b-41f3-86cf-51749344bab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136101322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4136101322
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.36887550
Short name T263
Test name
Test status
Simulation time 32274246782 ps
CPU time 12.35 seconds
Started Jun 27 06:04:03 PM PDT 24
Finished Jun 27 06:04:17 PM PDT 24
Peak memory 191664 kb
Host smart-2a2bc629-60c1-40f8-85e7-73d8ac34cfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36887550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.36887550
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1532972693
Short name T9
Test name
Test status
Simulation time 439127078 ps
CPU time 0.7 seconds
Started Jun 27 06:03:56 PM PDT 24
Finished Jun 27 06:03:58 PM PDT 24
Peak memory 191692 kb
Host smart-d1031f25-f3c4-4ce5-baa1-eaa1d296f315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532972693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1532972693
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1870989063
Short name T275
Test name
Test status
Simulation time 12319950551 ps
CPU time 5.27 seconds
Started Jun 27 06:04:13 PM PDT 24
Finished Jun 27 06:04:21 PM PDT 24
Peak memory 191636 kb
Host smart-2f33dc9b-29fb-41c5-8fb5-dc33b18baa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870989063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1870989063
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2732874567
Short name T234
Test name
Test status
Simulation time 561880465 ps
CPU time 1.02 seconds
Started Jun 27 06:04:11 PM PDT 24
Finished Jun 27 06:04:14 PM PDT 24
Peak memory 196496 kb
Host smart-1aed02b1-8fa1-403f-afbf-104d38f24641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732874567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2732874567
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1876479431
Short name T257
Test name
Test status
Simulation time 23127437609 ps
CPU time 9.04 seconds
Started Jun 27 06:04:16 PM PDT 24
Finished Jun 27 06:04:27 PM PDT 24
Peak memory 196668 kb
Host smart-82ce5d1c-2918-47c5-bcbc-ef88bf6edd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876479431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1876479431
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3118460032
Short name T277
Test name
Test status
Simulation time 414823312 ps
CPU time 0.76 seconds
Started Jun 27 06:04:16 PM PDT 24
Finished Jun 27 06:04:19 PM PDT 24
Peak memory 191640 kb
Host smart-72cd53f4-5f13-4710-b8dc-322b5c90da1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118460032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3118460032
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1999589540
Short name T218
Test name
Test status
Simulation time 31824193323 ps
CPU time 20.39 seconds
Started Jun 27 06:04:16 PM PDT 24
Finished Jun 27 06:04:38 PM PDT 24
Peak memory 196644 kb
Host smart-15217c2c-50c6-419e-9558-d687bc0c6665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999589540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1999589540
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3441965290
Short name T245
Test name
Test status
Simulation time 381012961 ps
CPU time 1.09 seconds
Started Jun 27 06:04:11 PM PDT 24
Finished Jun 27 06:04:14 PM PDT 24
Peak memory 191644 kb
Host smart-cfb1102b-1177-4681-ab4b-710fedd7a8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441965290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3441965290
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1458048724
Short name T224
Test name
Test status
Simulation time 23022399420 ps
CPU time 33.31 seconds
Started Jun 27 06:04:12 PM PDT 24
Finished Jun 27 06:04:47 PM PDT 24
Peak memory 191728 kb
Host smart-ba9bda8e-7177-4632-bead-a8463b05f4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458048724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1458048724
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2307608069
Short name T244
Test name
Test status
Simulation time 590899060 ps
CPU time 0.73 seconds
Started Jun 27 06:04:15 PM PDT 24
Finished Jun 27 06:04:18 PM PDT 24
Peak memory 191668 kb
Host smart-167a18e0-836a-4334-b8a8-cf259dc107bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307608069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2307608069
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3313946653
Short name T226
Test name
Test status
Simulation time 25283583422 ps
CPU time 9.97 seconds
Started Jun 27 06:04:10 PM PDT 24
Finished Jun 27 06:04:21 PM PDT 24
Peak memory 196732 kb
Host smart-555e99fe-c6c1-4886-8367-ca0c591af9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313946653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3313946653
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.105558123
Short name T199
Test name
Test status
Simulation time 359926626 ps
CPU time 0.86 seconds
Started Jun 27 06:04:25 PM PDT 24
Finished Jun 27 06:04:27 PM PDT 24
Peak memory 191612 kb
Host smart-3eb66cfb-7868-4c53-9a21-3ce785e28689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105558123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.105558123
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2043426009
Short name T236
Test name
Test status
Simulation time 33334542826 ps
CPU time 51.38 seconds
Started Jun 27 06:04:25 PM PDT 24
Finished Jun 27 06:05:17 PM PDT 24
Peak memory 196672 kb
Host smart-093b490d-49af-47b2-b502-8e0803ee30b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043426009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2043426009
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1033410642
Short name T273
Test name
Test status
Simulation time 480333804 ps
CPU time 0.89 seconds
Started Jun 27 06:04:12 PM PDT 24
Finished Jun 27 06:04:14 PM PDT 24
Peak memory 191628 kb
Host smart-eb0f9d8d-3c04-4347-ab16-6054dcb15bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033410642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1033410642
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3340097534
Short name T265
Test name
Test status
Simulation time 54602305044 ps
CPU time 85.84 seconds
Started Jun 27 06:02:57 PM PDT 24
Finished Jun 27 06:04:25 PM PDT 24
Peak memory 191732 kb
Host smart-5e55ed64-6914-48c1-a03d-edcb9ddf3ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340097534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3340097534
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.378039640
Short name T279
Test name
Test status
Simulation time 502422232 ps
CPU time 1.35 seconds
Started Jun 27 06:02:55 PM PDT 24
Finished Jun 27 06:02:58 PM PDT 24
Peak memory 191628 kb
Host smart-ef98123b-9cae-4131-b909-d905db871a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378039640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.378039640
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3095118406
Short name T39
Test name
Test status
Simulation time 564970204 ps
CPU time 0.85 seconds
Started Jun 27 06:03:13 PM PDT 24
Finished Jun 27 06:03:17 PM PDT 24
Peak memory 196452 kb
Host smart-dd92c0aa-d4f4-4cca-8db9-731ace56fd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095118406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3095118406
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2077525537
Short name T253
Test name
Test status
Simulation time 33783389257 ps
CPU time 49.44 seconds
Started Jun 27 06:03:16 PM PDT 24
Finished Jun 27 06:04:10 PM PDT 24
Peak memory 196692 kb
Host smart-00797f8e-929e-40e7-9421-5a9fce4ae308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077525537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2077525537
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2638841337
Short name T198
Test name
Test status
Simulation time 479721535 ps
CPU time 0.71 seconds
Started Jun 27 06:02:58 PM PDT 24
Finished Jun 27 06:03:00 PM PDT 24
Peak memory 196496 kb
Host smart-d42a338d-ddd5-47fe-86e6-43bcd83ca2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638841337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2638841337
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1895090799
Short name T167
Test name
Test status
Simulation time 568970032 ps
CPU time 0.76 seconds
Started Jun 27 06:03:12 PM PDT 24
Finished Jun 27 06:03:14 PM PDT 24
Peak memory 196456 kb
Host smart-9fcc9576-b912-48fb-a414-ddc35f7dc866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895090799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1895090799
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3972596295
Short name T230
Test name
Test status
Simulation time 41746094880 ps
CPU time 11.63 seconds
Started Jun 27 06:03:14 PM PDT 24
Finished Jun 27 06:03:29 PM PDT 24
Peak memory 191664 kb
Host smart-5388d722-73a2-4d9d-abb3-54b777e0e235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972596295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3972596295
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3790168842
Short name T217
Test name
Test status
Simulation time 539479824 ps
CPU time 0.74 seconds
Started Jun 27 06:03:15 PM PDT 24
Finished Jun 27 06:03:19 PM PDT 24
Peak memory 191672 kb
Host smart-54c7adb4-1fbb-4ba0-ba09-e9a5b29d6524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790168842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3790168842
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2726960247
Short name T255
Test name
Test status
Simulation time 20682930689 ps
CPU time 3.71 seconds
Started Jun 27 06:03:14 PM PDT 24
Finished Jun 27 06:03:21 PM PDT 24
Peak memory 191684 kb
Host smart-d216e94c-6004-4fb4-9df1-f3d2851bed76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726960247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2726960247
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3168055545
Short name T225
Test name
Test status
Simulation time 594810330 ps
CPU time 0.99 seconds
Started Jun 27 06:03:12 PM PDT 24
Finished Jun 27 06:03:15 PM PDT 24
Peak memory 191668 kb
Host smart-3a68864a-86fc-4284-a1bf-4b0656b38cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168055545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3168055545
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2992213631
Short name T37
Test name
Test status
Simulation time 2531685329 ps
CPU time 1.37 seconds
Started Jun 27 06:03:13 PM PDT 24
Finished Jun 27 06:03:18 PM PDT 24
Peak memory 196472 kb
Host smart-61ed30ae-ad54-4345-af30-7457b4af0786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992213631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2992213631
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1877986221
Short name T247
Test name
Test status
Simulation time 505392550 ps
CPU time 0.89 seconds
Started Jun 27 06:03:15 PM PDT 24
Finished Jun 27 06:03:20 PM PDT 24
Peak memory 191636 kb
Host smart-4d771796-5875-476e-9d0e-9bd1099ba182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877986221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1877986221
Directory /workspace/9.aon_timer_smoke/latest
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