Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	30651	1		T1	233		T3	52		T4	176
bark[1]	267	1		T7	21		T38	47		T179	80
bark[2]	841	1		T2	14		T8	21		T152	58
bark[3]	1722	1		T29	14		T149	80		T97	14
bark[4]	462	1		T9	21		T44	21		T152	14
bark[5]	863	1		T8	30		T80	14		T114	14
bark[6]	349	1		T38	21		T102	14		T129	21
bark[7]	355	1		T4	21		T38	26		T88	21
bark[8]	769	1		T8	23		T9	21		T28	21
bark[9]	452	1		T4	42		T84	21		T172	14
bark[10]	701	1		T9	21		T149	57		T88	21
bark[11]	415	1		T6	42		T13	14		T44	21
bark[12]	463	1		T6	14		T46	39		T39	47
bark[13]	505	1		T1	26		T88	21		T126	21
bark[14]	255	1		T44	21		T152	68		T40	14
bark[15]	294	1		T3	67		T6	21		T9	21
bark[16]	693	1		T4	21		T6	21		T7	73
bark[17]	152	1		T6	21		T7	21		T159	14
bark[18]	376	1		T43	14		T124	21		T119	26
bark[19]	573	1		T9	21		T124	21		T38	47
bark[20]	316	1		T28	21		T45	14		T138	26
bark[21]	368	1		T6	21		T124	21		T119	21
bark[22]	914	1		T6	26		T7	21		T124	49
bark[23]	687	1		T40	283		T134	30		T99	21
bark[24]	1032	1		T3	264		T39	61		T41	21
bark[25]	841	1		T9	26		T44	44		T30	21
bark[26]	810	1		T162	61		T47	21		T156	86
bark[27]	671	1		T1	39		T6	125		T134	21
bark[28]	557	1		T153	14		T41	21		T24	21
bark[29]	818	1		T134	74		T99	65		T90	21
bark[30]	464	1		T8	21		T9	21		T44	21
bark[31]	419	1		T7	30		T28	21		T44	21
bark_0	4861	1		T1	37		T2	7		T3	44

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	30539	1		T1	191		T3	49		T4	175
bite[1]	745	1		T7	21		T88	21		T102	13
bite[2]	657	1		T29	13		T44	21		T97	13
bite[3]	576	1		T4	42		T88	42		T40	26
bite[4]	950	1		T2	13		T119	30		T113	305
bite[5]	583	1		T145	166		T127	284		T110	127
bite[6]	743	1		T8	30		T152	58		T24	21
bite[7]	484	1		T1	39		T39	46		T23	21
bite[8]	351	1		T1	25		T45	13		T38	46
bite[9]	592	1		T40	282		T114	13		T113	21
bite[10]	399	1		T6	25		T124	21		T119	26
bite[11]	466	1		T4	21		T119	21		T179	80
bite[12]	537	1		T46	39		T38	25		T189	13
bite[13]	619	1		T6	21		T9	21		T124	21
bite[14]	201	1		T84	21		T88	21		T41	42
bite[15]	324	1		T6	21		T8	21		T39	60
bite[16]	169	1		T7	21		T38	46		T84	13
bite[17]	444	1		T8	22		T9	42		T43	13
bite[18]	520	1		T8	100		T9	21		T149	57
bite[19]	421	1		T13	13		T183	13		T41	25
bite[20]	448	1		T44	21		T21	13		T24	21
bite[21]	1070	1		T9	21		T190	13		T152	21
bite[22]	516	1		T90	21		T47	193		T132	217
bite[23]	665	1		T4	21		T6	21		T28	21
bite[24]	899	1		T3	263		T6	34		T44	42
bite[25]	601	1		T7	30		T9	21		T28	21
bite[26]	947	1		T1	39		T7	72		T9	26
bite[27]	335	1		T44	65		T152	21		T134	73
bite[28]	1096	1		T7	21		T124	21		T85	13
bite[29]	368	1		T6	145		T8	21		T24	21
bite[30]	793	1		T28	21		T149	59		T38	106
bite[31]	494	1		T3	66		T6	21		T30	21
bite_0	5364	1		T1	41		T2	8		T3	49

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	53916	1		T1	335		T2	21		T3	427

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	923	1		T30	37		T88	19		T41	90
prescale[1]	1359	1		T6	42		T30	68		T41	108
prescale[2]	671	1		T9	24		T40	20		T99	19
prescale[3]	1201	1		T134	23		T126	28		T99	59
prescale[4]	925	1		T3	4		T44	9		T40	33
prescale[5]	1130	1		T1	28		T4	60		T6	32
prescale[6]	952	1		T6	27		T38	2		T39	146
prescale[7]	1148	1		T5	9		T6	84		T7	19
prescale[8]	845	1		T3	123		T4	24		T13	37
prescale[9]	627	1		T6	92		T7	32		T9	19
prescale[10]	990	1		T1	19		T28	37		T152	44
prescale[11]	869	1		T3	32		T6	66		T9	19
prescale[12]	680	1		T1	40		T119	28		T149	19
prescale[13]	690	1		T1	9		T3	103		T8	23
prescale[14]	715	1		T4	9		T7	30		T46	19
prescale[15]	709	1		T6	109		T44	19		T46	58
prescale[16]	558	1		T6	136		T196	9		T42	40
prescale[17]	1119	1		T13	19		T124	19		T30	70
prescale[18]	508	1		T152	23		T21	20		T138	23
prescale[19]	958	1		T38	2		T40	2		T21	20
prescale[20]	802	1		T3	45		T13	24		T44	37
prescale[21]	750	1		T6	19		T38	2		T39	2
prescale[22]	749	1		T4	28		T6	23		T8	41
prescale[23]	925	1		T3	9		T7	19		T119	53
prescale[24]	867	1		T6	9		T39	95		T162	2
prescale[25]	951	1		T1	19		T13	29		T30	2
prescale[26]	374	1		T4	23		T12	9		T21	63
prescale[27]	903	1		T149	41		T39	19		T81	9
prescale[28]	634	1		T1	70		T4	19		T6	40
prescale[29]	1382	1		T28	19		T119	37		T46	9
prescale[30]	550	1		T28	19		T24	56		T42	39
prescale[31]	608	1		T1	2		T6	68		T9	9
prescale_0	26844	1		T1	148		T2	21		T3	111

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40303	1		T1	202		T2	9		T3	339
auto[1]	13613	1		T1	133		T2	12		T3	88

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	53916	1		T1	335		T2	21		T3	427

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	31001	1		T1	152		T2	1		T3	253
wkup[1]	225	1		T124	42		T42	21		T71	15
wkup[2]	230	1		T6	21		T39	21		T80	15
wkup[3]	177	1		T6	21		T7	21		T38	21
wkup[4]	323	1		T6	21		T30	30		T41	42
wkup[5]	298	1		T3	21		T28	21		T41	42
wkup[6]	358	1		T119	26		T40	78		T138	26
wkup[7]	243	1		T43	15		T124	30		T40	26
wkup[8]	358	1		T3	30		T6	30		T41	21
wkup[9]	253	1		T1	26		T164	15		T157	21
wkup[10]	326	1		T3	26		T8	42		T9	21
wkup[11]	271	1		T44	21		T152	21		T38	21
wkup[12]	201	1		T8	30		T9	21		T30	42
wkup[13]	375	1		T41	21		T21	21		T126	21
wkup[14]	179	1		T116	26		T145	39		T79	30
wkup[15]	241	1		T38	21		T39	21		T85	15
wkup[16]	294	1		T6	21		T149	42		T152	21
wkup[17]	343	1		T6	21		T30	29		T39	21
wkup[18]	353	1		T7	30		T46	21		T88	21
wkup[19]	282	1		T1	8		T2	15		T41	21
wkup[20]	329	1		T152	15		T21	42		T138	21
wkup[21]	275	1		T6	26		T9	21		T39	26
wkup[22]	438	1		T6	21		T8	21		T9	21
wkup[23]	374	1		T7	21		T124	21		T38	21
wkup[24]	331	1		T6	30		T42	30		T176	21
wkup[25]	430	1		T3	21		T40	21		T21	21
wkup[26]	258	1		T44	21		T119	30		T161	21
wkup[27]	308	1		T6	42		T84	21		T24	21
wkup[28]	470	1		T6	56		T152	21		T39	21
wkup[29]	348	1		T6	21		T9	21		T13	15
wkup[30]	318	1		T1	21		T4	21		T21	21
wkup[31]	296	1		T30	47		T99	21		T89	42
wkup[32]	271	1		T46	21		T114	15		T21	21
wkup[33]	254	1		T1	39		T138	21		T71	21
wkup[34]	364	1		T3	21		T9	21		T28	26
wkup[35]	202	1		T8	24		T88	42		T188	15
wkup[36]	229	1		T1	21		T44	21		T21	21
wkup[37]	265	1		T44	21		T30	21		T19	15
wkup[38]	319	1		T6	21		T149	21		T30	21
wkup[39]	302	1		T6	15		T38	21		T179	21
wkup[40]	207	1		T6	21		T21	8		T24	21
wkup[41]	354	1		T6	47		T152	21		T41	21
wkup[42]	296	1		T45	15		T72	30		T89	63
wkup[43]	211	1		T149	21		T42	8		T134	21
wkup[44]	554	1		T6	42		T9	21		T38	21
wkup[45]	260	1		T88	21		T179	21		T40	21
wkup[46]	331	1		T6	21		T84	30		T115	15
wkup[47]	336	1		T99	8		T102	21		T71	21
wkup[48]	377	1		T6	39		T39	15		T84	21
wkup[49]	341	1		T7	21		T9	26		T30	21
wkup[50]	228	1		T39	29		T21	21		T172	15
wkup[51]	245	1		T7	21		T84	21		T179	21
wkup[52]	326	1		T7	15		T97	15		T40	68
wkup[53]	242	1		T21	21		T42	21		T102	15
wkup[54]	357	1		T6	8		T8	21		T28	21
wkup[55]	218	1		T21	21		T90	20		T47	21
wkup[56]	218	1		T119	21		T152	26		T21	15
wkup[57]	259	1		T4	21		T6	21		T8	21
wkup[58]	209	1		T44	44		T30	47		T93	15
wkup[59]	373	1		T1	39		T4	21		T102	21
wkup[60]	398	1		T3	21		T4	21		T24	21
wkup[61]	379	1		T6	21		T29	15		T38	42
wkup[62]	407	1		T28	21		T44	21		T124	21
wkup[63]	296	1		T149	30		T21	26		T24	21
wkup_0	3782	1		T1	29		T2	5		T3	34