Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.34 99.33 93.67 100.00 98.40 99.51 51.14


Total test records in report: 422
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T31 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3798325244 Jun 28 06:35:48 PM PDT 24 Jun 28 06:35:51 PM PDT 24 539024029 ps
T285 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4007505003 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:30 PM PDT 24 686241179 ps
T32 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3317611997 Jun 28 06:36:14 PM PDT 24 Jun 28 06:36:16 PM PDT 24 419926342 ps
T37 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3994129556 Jun 28 06:35:41 PM PDT 24 Jun 28 06:35:49 PM PDT 24 7153292955 ps
T286 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.859149720 Jun 28 06:36:18 PM PDT 24 Jun 28 06:36:21 PM PDT 24 570740318 ps
T33 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3607656295 Jun 28 06:35:53 PM PDT 24 Jun 28 06:35:57 PM PDT 24 476637456 ps
T287 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3154554798 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:27 PM PDT 24 465766900 ps
T288 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3483605587 Jun 28 06:36:17 PM PDT 24 Jun 28 06:36:19 PM PDT 24 483272514 ps
T64 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4179481675 Jun 28 06:36:12 PM PDT 24 Jun 28 06:36:16 PM PDT 24 1686232042 ps
T34 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.513879941 Jun 28 06:36:11 PM PDT 24 Jun 28 06:36:26 PM PDT 24 7897847483 ps
T289 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2958855772 Jun 28 06:35:45 PM PDT 24 Jun 28 06:35:50 PM PDT 24 302810867 ps
T35 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.62593719 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:30 PM PDT 24 4150461041 ps
T36 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1814894114 Jun 28 06:36:02 PM PDT 24 Jun 28 06:36:15 PM PDT 24 8242517813 ps
T290 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1977211702 Jun 28 06:36:38 PM PDT 24 Jun 28 06:36:40 PM PDT 24 303633997 ps
T291 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.741366864 Jun 28 06:36:27 PM PDT 24 Jun 28 06:36:33 PM PDT 24 400642100 ps
T292 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3727843400 Jun 28 06:35:47 PM PDT 24 Jun 28 06:35:50 PM PDT 24 497842116 ps
T49 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3381166082 Jun 28 06:36:03 PM PDT 24 Jun 28 06:36:06 PM PDT 24 461693167 ps
T65 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.506174100 Jun 28 06:35:40 PM PDT 24 Jun 28 06:35:46 PM PDT 24 1262886901 ps
T293 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3374672816 Jun 28 06:35:42 PM PDT 24 Jun 28 06:35:47 PM PDT 24 372328124 ps
T294 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.118602831 Jun 28 06:36:21 PM PDT 24 Jun 28 06:36:26 PM PDT 24 413819780 ps
T295 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2340100404 Jun 28 06:35:55 PM PDT 24 Jun 28 06:35:58 PM PDT 24 575996475 ps
T50 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.391587495 Jun 28 06:36:05 PM PDT 24 Jun 28 06:36:07 PM PDT 24 320451006 ps
T296 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.604640006 Jun 28 06:36:12 PM PDT 24 Jun 28 06:36:16 PM PDT 24 440271725 ps
T297 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2793130988 Jun 28 06:36:03 PM PDT 24 Jun 28 06:36:05 PM PDT 24 274336748 ps
T298 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3039609048 Jun 28 06:36:24 PM PDT 24 Jun 28 06:36:30 PM PDT 24 508580146 ps
T299 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.608046438 Jun 28 06:36:13 PM PDT 24 Jun 28 06:36:16 PM PDT 24 723617693 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4087150070 Jun 28 06:35:53 PM PDT 24 Jun 28 06:36:00 PM PDT 24 2152016622 ps
T300 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2601761181 Jun 28 06:36:20 PM PDT 24 Jun 28 06:36:23 PM PDT 24 378005291 ps
T51 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1553106192 Jun 28 06:36:24 PM PDT 24 Jun 28 06:36:30 PM PDT 24 313116020 ps
T67 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.569853985 Jun 28 06:36:03 PM PDT 24 Jun 28 06:36:07 PM PDT 24 1167811248 ps
T68 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.840185406 Jun 28 06:36:00 PM PDT 24 Jun 28 06:36:02 PM PDT 24 469704076 ps
T301 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1270217867 Jun 28 06:36:36 PM PDT 24 Jun 28 06:36:38 PM PDT 24 507950791 ps
T302 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2443626611 Jun 28 06:36:06 PM PDT 24 Jun 28 06:36:09 PM PDT 24 411212079 ps
T69 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2394585387 Jun 28 06:36:13 PM PDT 24 Jun 28 06:36:17 PM PDT 24 1816325800 ps
T303 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3487315724 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:27 PM PDT 24 517925380 ps
T194 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2199721112 Jun 28 06:36:13 PM PDT 24 Jun 28 06:36:19 PM PDT 24 4257303739 ps
T304 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3925941482 Jun 28 06:36:01 PM PDT 24 Jun 28 06:36:05 PM PDT 24 470233003 ps
T305 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2449837254 Jun 28 06:36:34 PM PDT 24 Jun 28 06:36:37 PM PDT 24 424068042 ps
T306 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1857051529 Jun 28 06:35:54 PM PDT 24 Jun 28 06:35:59 PM PDT 24 395131168 ps
T307 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3133495701 Jun 28 06:36:02 PM PDT 24 Jun 28 06:36:05 PM PDT 24 429635414 ps
T308 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3537590157 Jun 28 06:36:12 PM PDT 24 Jun 28 06:36:16 PM PDT 24 499080363 ps
T309 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2538477556 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:28 PM PDT 24 358036102 ps
T70 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1678790006 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:30 PM PDT 24 1151472429 ps
T310 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2153699201 Jun 28 06:35:54 PM PDT 24 Jun 28 06:35:57 PM PDT 24 400715832 ps
T311 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1559180923 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:29 PM PDT 24 498857212 ps
T312 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3939124201 Jun 28 06:36:26 PM PDT 24 Jun 28 06:36:31 PM PDT 24 343123315 ps
T191 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1848517492 Jun 28 06:36:11 PM PDT 24 Jun 28 06:36:20 PM PDT 24 8040489408 ps
T52 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3757362997 Jun 28 06:35:53 PM PDT 24 Jun 28 06:35:56 PM PDT 24 406872531 ps
T313 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.849979811 Jun 28 06:35:53 PM PDT 24 Jun 28 06:35:56 PM PDT 24 623227039 ps
T314 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.513710509 Jun 28 06:36:12 PM PDT 24 Jun 28 06:36:18 PM PDT 24 2685927511 ps
T315 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2462537847 Jun 28 06:36:04 PM PDT 24 Jun 28 06:36:15 PM PDT 24 7108383221 ps
T316 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3212774458 Jun 28 06:36:33 PM PDT 24 Jun 28 06:36:35 PM PDT 24 404967120 ps
T317 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2753495712 Jun 28 06:35:40 PM PDT 24 Jun 28 06:35:44 PM PDT 24 555773163 ps
T318 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3897694203 Jun 28 06:36:33 PM PDT 24 Jun 28 06:36:35 PM PDT 24 299384294 ps
T319 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3394699980 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:26 PM PDT 24 377821395 ps
T320 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3073507290 Jun 28 06:36:12 PM PDT 24 Jun 28 06:36:16 PM PDT 24 502035008 ps
T321 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3785214049 Jun 28 06:36:14 PM PDT 24 Jun 28 06:36:18 PM PDT 24 370913267 ps
T322 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1337296921 Jun 28 06:36:01 PM PDT 24 Jun 28 06:36:02 PM PDT 24 356241666 ps
T323 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1796267150 Jun 28 06:35:55 PM PDT 24 Jun 28 06:35:58 PM PDT 24 1266479749 ps
T324 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.240802047 Jun 28 06:35:43 PM PDT 24 Jun 28 06:35:47 PM PDT 24 549943679 ps
T325 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2879624894 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:27 PM PDT 24 455141368 ps
T326 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3035280735 Jun 28 06:36:10 PM PDT 24 Jun 28 06:36:11 PM PDT 24 591264215 ps
T195 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1440018938 Jun 28 06:36:13 PM PDT 24 Jun 28 06:36:17 PM PDT 24 4148688590 ps
T327 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2116379851 Jun 28 06:36:24 PM PDT 24 Jun 28 06:36:30 PM PDT 24 475447614 ps
T328 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.639415857 Jun 28 06:35:43 PM PDT 24 Jun 28 06:35:50 PM PDT 24 2630236068 ps
T329 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3947880090 Jun 28 06:36:21 PM PDT 24 Jun 28 06:36:23 PM PDT 24 408832479 ps
T330 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.451557650 Jun 28 06:36:05 PM PDT 24 Jun 28 06:36:11 PM PDT 24 8283752281 ps
T331 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1182271762 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:29 PM PDT 24 304640423 ps
T332 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.643421245 Jun 28 06:35:53 PM PDT 24 Jun 28 06:35:57 PM PDT 24 419822671 ps
T333 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3023316879 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:27 PM PDT 24 333943244 ps
T334 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1419969044 Jun 28 06:36:33 PM PDT 24 Jun 28 06:36:36 PM PDT 24 278337323 ps
T53 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4225814297 Jun 28 06:36:13 PM PDT 24 Jun 28 06:36:15 PM PDT 24 456489703 ps
T54 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3645222891 Jun 28 06:35:55 PM PDT 24 Jun 28 06:35:58 PM PDT 24 565353045 ps
T335 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3726622903 Jun 28 06:36:05 PM PDT 24 Jun 28 06:36:07 PM PDT 24 430900565 ps
T336 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3758625553 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:28 PM PDT 24 464127032 ps
T337 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1091201187 Jun 28 06:36:13 PM PDT 24 Jun 28 06:36:17 PM PDT 24 394297634 ps
T338 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.750305085 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:27 PM PDT 24 578967735 ps
T339 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3824928792 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:28 PM PDT 24 392419428 ps
T340 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2375275678 Jun 28 06:36:37 PM PDT 24 Jun 28 06:36:39 PM PDT 24 388236066 ps
T55 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.788941844 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:27 PM PDT 24 363847505 ps
T341 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2816170496 Jun 28 06:36:06 PM PDT 24 Jun 28 06:36:08 PM PDT 24 749724414 ps
T342 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2402693557 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:30 PM PDT 24 1194310534 ps
T343 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2846634065 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:29 PM PDT 24 391209662 ps
T344 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3069987067 Jun 28 06:36:06 PM PDT 24 Jun 28 06:36:11 PM PDT 24 431634174 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4278349672 Jun 28 06:35:43 PM PDT 24 Jun 28 06:36:05 PM PDT 24 7632716246 ps
T345 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.568354266 Jun 28 06:35:44 PM PDT 24 Jun 28 06:35:47 PM PDT 24 519878355 ps
T346 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2496239981 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:27 PM PDT 24 346185061 ps
T347 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2546657980 Jun 28 06:35:54 PM PDT 24 Jun 28 06:35:56 PM PDT 24 392626610 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3585487454 Jun 28 06:36:03 PM PDT 24 Jun 28 06:36:06 PM PDT 24 512033230 ps
T348 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3548992638 Jun 28 06:36:03 PM PDT 24 Jun 28 06:36:06 PM PDT 24 314643317 ps
T349 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1340032015 Jun 28 06:35:44 PM PDT 24 Jun 28 06:35:50 PM PDT 24 8393511113 ps
T350 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1065972027 Jun 28 06:36:25 PM PDT 24 Jun 28 06:36:31 PM PDT 24 296307363 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.108161938 Jun 28 06:35:42 PM PDT 24 Jun 28 06:35:47 PM PDT 24 603883142 ps
T351 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3378041688 Jun 28 06:36:13 PM PDT 24 Jun 28 06:36:18 PM PDT 24 2487938261 ps
T62 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3819675656 Jun 28 06:35:48 PM PDT 24 Jun 28 06:35:53 PM PDT 24 1312839745 ps
T352 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3832061710 Jun 28 06:36:11 PM PDT 24 Jun 28 06:36:13 PM PDT 24 447298995 ps
T353 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.724793608 Jun 28 06:36:13 PM PDT 24 Jun 28 06:36:17 PM PDT 24 1138269976 ps
T354 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2177624865 Jun 28 06:35:53 PM PDT 24 Jun 28 06:35:57 PM PDT 24 4286108811 ps
T355 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.479245968 Jun 28 06:35:48 PM PDT 24 Jun 28 06:35:51 PM PDT 24 359609999 ps
T356 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.61204778 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:29 PM PDT 24 415625240 ps
T357 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2902970516 Jun 28 06:35:54 PM PDT 24 Jun 28 06:36:02 PM PDT 24 14413781960 ps
T358 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.142495797 Jun 28 06:35:52 PM PDT 24 Jun 28 06:35:54 PM PDT 24 305423305 ps
T359 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1677321565 Jun 28 06:36:13 PM PDT 24 Jun 28 06:36:16 PM PDT 24 282242631 ps
T360 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4188584001 Jun 28 06:35:53 PM PDT 24 Jun 28 06:35:56 PM PDT 24 451136654 ps
T361 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3406319921 Jun 28 06:36:04 PM PDT 24 Jun 28 06:36:08 PM PDT 24 4528688403 ps
T362 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1098756012 Jun 28 06:36:12 PM PDT 24 Jun 28 06:36:15 PM PDT 24 2184847808 ps
T363 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2175314113 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:29 PM PDT 24 475506300 ps
T364 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1573850706 Jun 28 06:36:21 PM PDT 24 Jun 28 06:36:24 PM PDT 24 742753199 ps
T365 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1640719593 Jun 28 06:36:21 PM PDT 24 Jun 28 06:36:23 PM PDT 24 459000311 ps
T366 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.391735365 Jun 28 06:35:54 PM PDT 24 Jun 28 06:35:58 PM PDT 24 470864158 ps
T367 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.185895769 Jun 28 06:36:12 PM PDT 24 Jun 28 06:36:16 PM PDT 24 593758721 ps
T368 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2767672926 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:29 PM PDT 24 485675411 ps
T369 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.160849489 Jun 28 06:35:45 PM PDT 24 Jun 28 06:35:49 PM PDT 24 4397149806 ps
T370 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.933606348 Jun 28 06:36:02 PM PDT 24 Jun 28 06:36:05 PM PDT 24 401143286 ps
T371 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.107955745 Jun 28 06:36:10 PM PDT 24 Jun 28 06:36:12 PM PDT 24 554559079 ps
T372 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2205173426 Jun 28 06:36:32 PM PDT 24 Jun 28 06:36:35 PM PDT 24 282989968 ps
T373 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3731985947 Jun 28 06:35:56 PM PDT 24 Jun 28 06:35:59 PM PDT 24 445702814 ps
T374 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.517189283 Jun 28 06:36:14 PM PDT 24 Jun 28 06:36:17 PM PDT 24 282087237 ps
T375 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2809934391 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:26 PM PDT 24 531962410 ps
T376 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3050675051 Jun 28 06:35:54 PM PDT 24 Jun 28 06:35:59 PM PDT 24 1331336766 ps
T192 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3451983262 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:32 PM PDT 24 4342466773 ps
T377 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1469421781 Jun 28 06:36:03 PM PDT 24 Jun 28 06:36:18 PM PDT 24 8264495644 ps
T378 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3947370232 Jun 28 06:35:56 PM PDT 24 Jun 28 06:36:01 PM PDT 24 8341611705 ps
T379 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3963530554 Jun 28 06:36:06 PM PDT 24 Jun 28 06:36:09 PM PDT 24 618540012 ps
T380 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1799275145 Jun 28 06:35:52 PM PDT 24 Jun 28 06:35:55 PM PDT 24 536348794 ps
T381 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2896514708 Jun 28 06:35:52 PM PDT 24 Jun 28 06:35:54 PM PDT 24 482546353 ps
T382 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2058232237 Jun 28 06:36:16 PM PDT 24 Jun 28 06:36:18 PM PDT 24 499723138 ps
T383 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.838284308 Jun 28 06:36:21 PM PDT 24 Jun 28 06:36:25 PM PDT 24 362126844 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1142499755 Jun 28 06:35:42 PM PDT 24 Jun 28 06:35:46 PM PDT 24 295510739 ps
T384 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2111778968 Jun 28 06:36:24 PM PDT 24 Jun 28 06:36:30 PM PDT 24 535159488 ps
T385 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1806163395 Jun 28 06:36:11 PM PDT 24 Jun 28 06:36:14 PM PDT 24 474850442 ps
T386 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3320078157 Jun 28 06:36:35 PM PDT 24 Jun 28 06:36:38 PM PDT 24 271626548 ps
T387 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3416669539 Jun 28 06:36:02 PM PDT 24 Jun 28 06:36:05 PM PDT 24 1049329634 ps
T388 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1213417312 Jun 28 06:35:55 PM PDT 24 Jun 28 06:35:58 PM PDT 24 657631383 ps
T389 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3848469801 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:26 PM PDT 24 295826746 ps
T193 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2011605410 Jun 28 06:36:11 PM PDT 24 Jun 28 06:36:17 PM PDT 24 8705101758 ps
T390 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2351947160 Jun 28 06:36:02 PM PDT 24 Jun 28 06:36:04 PM PDT 24 366399883 ps
T391 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2039987146 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:27 PM PDT 24 453978562 ps
T60 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3062102795 Jun 28 06:36:02 PM PDT 24 Jun 28 06:36:04 PM PDT 24 403630581 ps
T392 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3180874682 Jun 28 06:35:42 PM PDT 24 Jun 28 06:35:46 PM PDT 24 451725140 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.978151433 Jun 28 06:35:56 PM PDT 24 Jun 28 06:36:12 PM PDT 24 13306904637 ps
T393 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2494253917 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:26 PM PDT 24 1263215089 ps
T394 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2592810684 Jun 28 06:36:04 PM PDT 24 Jun 28 06:36:10 PM PDT 24 8253115726 ps
T395 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4039238920 Jun 28 06:36:21 PM PDT 24 Jun 28 06:36:23 PM PDT 24 1120891362 ps
T396 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1719073994 Jun 28 06:36:02 PM PDT 24 Jun 28 06:36:04 PM PDT 24 336622383 ps
T397 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2676143304 Jun 28 06:35:54 PM PDT 24 Jun 28 06:35:57 PM PDT 24 322800396 ps
T398 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.906601106 Jun 28 06:36:04 PM PDT 24 Jun 28 06:36:06 PM PDT 24 418965611 ps
T399 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2623621170 Jun 28 06:35:46 PM PDT 24 Jun 28 06:35:49 PM PDT 24 797992621 ps
T400 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3065950629 Jun 28 06:36:24 PM PDT 24 Jun 28 06:36:30 PM PDT 24 392704973 ps
T401 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1369676517 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:38 PM PDT 24 8482406740 ps
T402 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2568183802 Jun 28 06:35:54 PM PDT 24 Jun 28 06:35:58 PM PDT 24 365579374 ps
T403 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3892038927 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:29 PM PDT 24 750065145 ps
T404 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.75802318 Jun 28 06:36:04 PM PDT 24 Jun 28 06:36:08 PM PDT 24 444200077 ps
T405 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2256533087 Jun 28 06:35:54 PM PDT 24 Jun 28 06:35:58 PM PDT 24 1295061791 ps
T406 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4231968197 Jun 28 06:36:20 PM PDT 24 Jun 28 06:36:23 PM PDT 24 1504005992 ps
T407 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1333390064 Jun 28 06:35:53 PM PDT 24 Jun 28 06:36:08 PM PDT 24 8158198939 ps
T408 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3767916941 Jun 28 06:36:25 PM PDT 24 Jun 28 06:36:31 PM PDT 24 379664628 ps
T409 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1009227438 Jun 28 06:36:22 PM PDT 24 Jun 28 06:36:27 PM PDT 24 433590198 ps
T410 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.737468877 Jun 28 06:35:43 PM PDT 24 Jun 28 06:35:46 PM PDT 24 373367625 ps
T411 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3018471842 Jun 28 06:36:06 PM PDT 24 Jun 28 06:36:09 PM PDT 24 576601397 ps
T412 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2518769346 Jun 28 06:36:08 PM PDT 24 Jun 28 06:36:11 PM PDT 24 961510196 ps
T413 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2908876561 Jun 28 06:36:06 PM PDT 24 Jun 28 06:36:12 PM PDT 24 3102121562 ps
T414 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4034409777 Jun 28 06:36:06 PM PDT 24 Jun 28 06:36:11 PM PDT 24 1972306833 ps
T415 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.364515072 Jun 28 06:36:10 PM PDT 24 Jun 28 06:36:13 PM PDT 24 357403217 ps
T416 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3923380576 Jun 28 06:36:21 PM PDT 24 Jun 28 06:36:35 PM PDT 24 8632387806 ps
T417 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3811962687 Jun 28 06:36:11 PM PDT 24 Jun 28 06:36:13 PM PDT 24 381584954 ps
T57 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.930421594 Jun 28 06:35:47 PM PDT 24 Jun 28 06:35:49 PM PDT 24 341551186 ps
T418 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.611379989 Jun 28 06:36:27 PM PDT 24 Jun 28 06:36:38 PM PDT 24 4617715591 ps
T419 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.929642880 Jun 28 06:36:12 PM PDT 24 Jun 28 06:36:16 PM PDT 24 436526253 ps
T420 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1710269241 Jun 28 06:36:23 PM PDT 24 Jun 28 06:36:28 PM PDT 24 454955503 ps
T421 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3125292189 Jun 28 06:36:02 PM PDT 24 Jun 28 06:36:07 PM PDT 24 2068218882 ps
T422 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1412106876 Jun 28 06:36:24 PM PDT 24 Jun 28 06:36:31 PM PDT 24 501597620 ps

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1676294510
Short name T6
Test name
Test status
Simulation time 92214499224 ps
CPU time 756.57 seconds
Started Jun 28 07:26:50 PM PDT 24
Finished Jun 28 07:40:01 PM PDT 24
Peak memory 207284 kb
Host smart-b111619a-5896-4ef9-bd38-2344076705ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676294510 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1676294510
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.256759369
Short name T9
Test name
Test status
Simulation time 100188638742 ps
CPU time 34.28 seconds
Started Jun 28 07:26:43 PM PDT 24
Finished Jun 28 07:27:50 PM PDT 24
Peak memory 198068 kb
Host smart-ff915a50-6350-4c20-ada1-c3ae8ce303f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256759369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.256759369
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.189818830
Short name T48
Test name
Test status
Simulation time 344188110092 ps
CPU time 530.74 seconds
Started Jun 28 07:26:06 PM PDT 24
Finished Jun 28 07:35:17 PM PDT 24
Peak memory 214452 kb
Host smart-385e4f20-dd39-49d6-a363-4f443414be90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189818830 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.189818830
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.513879941
Short name T34
Test name
Test status
Simulation time 7897847483 ps
CPU time 13.1 seconds
Started Jun 28 06:36:11 PM PDT 24
Finished Jun 28 06:36:26 PM PDT 24
Peak memory 198252 kb
Host smart-1fffeda6-2550-4b0c-bc8a-fbf38b3262ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513879941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.513879941
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3721202951
Short name T116
Test name
Test status
Simulation time 30444531356 ps
CPU time 222.52 seconds
Started Jun 28 07:26:04 PM PDT 24
Finished Jun 28 07:30:07 PM PDT 24
Peak memory 206628 kb
Host smart-f1ad75d5-f7ac-413e-b127-3bdf9d858d4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721202951 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3721202951
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2056493885
Short name T38
Test name
Test status
Simulation time 68938765166 ps
CPU time 529.9 seconds
Started Jun 28 07:26:05 PM PDT 24
Finished Jun 28 07:35:15 PM PDT 24
Peak memory 203352 kb
Host smart-2374f366-8b67-45ee-b844-a57bfab4aa7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056493885 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2056493885
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2221616096
Short name T77
Test name
Test status
Simulation time 208166142898 ps
CPU time 394.27 seconds
Started Jun 28 07:26:37 PM PDT 24
Finished Jun 28 07:33:45 PM PDT 24
Peak memory 210840 kb
Host smart-666bf332-d122-41cd-8da3-86a309a4a00b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221616096 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2221616096
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1464147649
Short name T110
Test name
Test status
Simulation time 230953903611 ps
CPU time 644.86 seconds
Started Jun 28 07:25:48 PM PDT 24
Finished Jun 28 07:36:46 PM PDT 24
Peak memory 207672 kb
Host smart-ea8f77ca-c7a7-4d58-aeb8-4e60aef8d170
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464147649 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1464147649
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.292616467
Short name T21
Test name
Test status
Simulation time 1563117010972 ps
CPU time 671.92 seconds
Started Jun 28 07:26:08 PM PDT 24
Finished Jun 28 07:37:42 PM PDT 24
Peak memory 213756 kb
Host smart-3bd1adf6-1c79-483a-bbe2-3e90c7a02864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292616467 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.292616467
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.4236417486
Short name T99
Test name
Test status
Simulation time 287733853941 ps
CPU time 629.39 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:36:34 PM PDT 24
Peak memory 204964 kb
Host smart-02ab626f-c217-4b2f-9c6f-64e5bbd3eba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236417486 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.4236417486
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2429316248
Short name T89
Test name
Test status
Simulation time 239184507704 ps
CPU time 464.75 seconds
Started Jun 28 07:26:07 PM PDT 24
Finished Jun 28 07:34:12 PM PDT 24
Peak memory 211712 kb
Host smart-6e91923a-03b4-4a2f-9e6e-740c6373874d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429316248 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2429316248
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1623600121
Short name T14
Test name
Test status
Simulation time 7840269511 ps
CPU time 7.63 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:25:47 PM PDT 24
Peak memory 215808 kb
Host smart-553b3af0-d864-4bb6-a1f5-8277ef4eb453
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623600121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1623600121
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.4062040902
Short name T150
Test name
Test status
Simulation time 174997817961 ps
CPU time 799.84 seconds
Started Jun 28 07:26:42 PM PDT 24
Finished Jun 28 07:40:35 PM PDT 24
Peak memory 207340 kb
Host smart-918ecd8c-1d2a-474b-a139-a74f00e7a0d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062040902 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.4062040902
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2995129046
Short name T88
Test name
Test status
Simulation time 81977587412 ps
CPU time 122.02 seconds
Started Jun 28 07:25:52 PM PDT 24
Finished Jun 28 07:28:08 PM PDT 24
Peak memory 192748 kb
Host smart-74c00253-61af-4cb3-bd2a-c74dfa19510e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995129046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2995129046
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.337929980
Short name T98
Test name
Test status
Simulation time 6615590272 ps
CPU time 2.25 seconds
Started Jun 28 07:26:06 PM PDT 24
Finished Jun 28 07:26:29 PM PDT 24
Peak memory 184008 kb
Host smart-38df6504-8646-47ae-9d9a-55498690c6d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337929980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.337929980
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1112023260
Short name T100
Test name
Test status
Simulation time 66626920837 ps
CPU time 6.54 seconds
Started Jun 28 07:26:10 PM PDT 24
Finished Jun 28 07:26:39 PM PDT 24
Peak memory 192836 kb
Host smart-27942a19-3aab-4939-a831-8165e85cd19c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112023260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1112023260
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.281721137
Short name T132
Test name
Test status
Simulation time 69513264775 ps
CPU time 387.99 seconds
Started Jun 28 07:26:26 PM PDT 24
Finished Jun 28 07:33:20 PM PDT 24
Peak memory 201616 kb
Host smart-3fe9dcc2-7522-4477-a7c9-9b90e67c1bb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281721137 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.281721137
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.4232674771
Short name T47
Test name
Test status
Simulation time 440430094565 ps
CPU time 239.66 seconds
Started Jun 28 07:25:53 PM PDT 24
Finished Jun 28 07:30:07 PM PDT 24
Peak memory 207728 kb
Host smart-409c315a-db6a-44c3-8433-6ad644c4109d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232674771 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.4232674771
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1949622707
Short name T124
Test name
Test status
Simulation time 25968860734 ps
CPU time 10.12 seconds
Started Jun 28 07:26:42 PM PDT 24
Finished Jun 28 07:27:24 PM PDT 24
Peak memory 191712 kb
Host smart-c2f3251a-85c5-419c-b061-3b9df96ae2a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949622707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1949622707
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3580460132
Short name T71
Test name
Test status
Simulation time 84620546166 ps
CPU time 549.69 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:35:14 PM PDT 24
Peak memory 213884 kb
Host smart-06d4807c-3843-4f57-a16a-5a4264cc69d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580460132 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3580460132
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3110110500
Short name T84
Test name
Test status
Simulation time 43447923783 ps
CPU time 68.03 seconds
Started Jun 28 07:25:49 PM PDT 24
Finished Jun 28 07:27:11 PM PDT 24
Peak memory 192748 kb
Host smart-7dfa203f-2346-467e-ba4f-583b89b5cd28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110110500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3110110500
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1645577553
Short name T131
Test name
Test status
Simulation time 121471212367 ps
CPU time 258.8 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:29:56 PM PDT 24
Peak memory 208856 kb
Host smart-60adb1de-4465-4778-bf7e-75b7fcaacc9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645577553 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1645577553
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.890301518
Short name T72
Test name
Test status
Simulation time 76666018454 ps
CPU time 550.96 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:35:17 PM PDT 24
Peak memory 214032 kb
Host smart-140851d7-0647-4b89-9d56-1416203bc365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890301518 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.890301518
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3022032212
Short name T104
Test name
Test status
Simulation time 66686955400 ps
CPU time 502.23 seconds
Started Jun 28 07:26:08 PM PDT 24
Finished Jun 28 07:34:53 PM PDT 24
Peak memory 210640 kb
Host smart-6231bf2c-325c-460f-b447-d7fd7d4c21d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022032212 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3022032212
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.4057054131
Short name T24
Test name
Test status
Simulation time 148306451305 ps
CPU time 29.96 seconds
Started Jun 28 07:25:58 PM PDT 24
Finished Jun 28 07:26:43 PM PDT 24
Peak memory 198088 kb
Host smart-508eb478-3b3a-4beb-99cf-c938245dea67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057054131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.4057054131
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.557720044
Short name T135
Test name
Test status
Simulation time 242670285423 ps
CPU time 649 seconds
Started Jun 28 07:26:06 PM PDT 24
Finished Jun 28 07:37:15 PM PDT 24
Peak memory 206108 kb
Host smart-00ac6ac9-2cc6-44e3-9b88-b70f0660740c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557720044 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.557720044
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3876703405
Short name T44
Test name
Test status
Simulation time 238409683597 ps
CPU time 352.43 seconds
Started Jun 28 07:26:26 PM PDT 24
Finished Jun 28 07:32:44 PM PDT 24
Peak memory 192740 kb
Host smart-45b36b44-3062-434f-a8a8-04f558b3c5ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876703405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3876703405
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3801418405
Short name T109
Test name
Test status
Simulation time 77048623042 ps
CPU time 117.82 seconds
Started Jun 28 07:26:40 PM PDT 24
Finished Jun 28 07:29:11 PM PDT 24
Peak memory 191712 kb
Host smart-aa3d4362-b6a9-44c4-8231-384eebf99fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801418405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3801418405
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3279679684
Short name T42
Test name
Test status
Simulation time 94510926871 ps
CPU time 683.26 seconds
Started Jun 28 07:26:38 PM PDT 24
Finished Jun 28 07:38:34 PM PDT 24
Peak memory 213996 kb
Host smart-b9fb91c6-b104-4068-8dcb-7ed71bcbbce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279679684 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3279679684
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3395635898
Short name T152
Test name
Test status
Simulation time 88145676542 ps
CPU time 16.13 seconds
Started Jun 28 07:26:27 PM PDT 24
Finished Jun 28 07:27:12 PM PDT 24
Peak memory 191728 kb
Host smart-1be614d1-6c0b-4157-938b-3336b1b8a041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395635898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3395635898
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.553558577
Short name T118
Test name
Test status
Simulation time 63884825448 ps
CPU time 664.43 seconds
Started Jun 28 07:26:26 PM PDT 24
Finished Jun 28 07:37:56 PM PDT 24
Peak memory 204584 kb
Host smart-6980b57a-39cb-452b-9aa0-9b13320b7d59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553558577 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.553558577
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2053857641
Short name T121
Test name
Test status
Simulation time 490145676131 ps
CPU time 414.13 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:33:00 PM PDT 24
Peak memory 210952 kb
Host smart-a498f883-141f-41a6-a422-1e1d5216f23b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053857641 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2053857641
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3675107436
Short name T111
Test name
Test status
Simulation time 73262971034 ps
CPU time 619.9 seconds
Started Jun 28 07:26:26 PM PDT 24
Finished Jun 28 07:37:11 PM PDT 24
Peak memory 206616 kb
Host smart-c187bbcf-0318-4461-8fdb-8efc1deb740d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675107436 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3675107436
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3232940615
Short name T40
Test name
Test status
Simulation time 28659205078 ps
CPU time 295.17 seconds
Started Jun 28 07:26:46 PM PDT 24
Finished Jun 28 07:32:17 PM PDT 24
Peak memory 214716 kb
Host smart-88dcaa30-2d52-436e-9b19-44aed415c7a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232940615 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3232940615
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3757362997
Short name T52
Test name
Test status
Simulation time 406872531 ps
CPU time 1.17 seconds
Started Jun 28 06:35:53 PM PDT 24
Finished Jun 28 06:35:56 PM PDT 24
Peak memory 193604 kb
Host smart-eed142e6-f560-4613-b6d2-6c14965f6295
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757362997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3757362997
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2000524661
Short name T141
Test name
Test status
Simulation time 79878022005 ps
CPU time 125.1 seconds
Started Jun 28 07:26:44 PM PDT 24
Finished Jun 28 07:29:23 PM PDT 24
Peak memory 191728 kb
Host smart-be3132ac-292f-4f92-89c2-9b26c8490e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000524661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2000524661
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.510700659
Short name T79
Test name
Test status
Simulation time 29339441333 ps
CPU time 201.43 seconds
Started Jun 28 07:26:45 PM PDT 24
Finished Jun 28 07:30:41 PM PDT 24
Peak memory 214076 kb
Host smart-17a88cc2-1534-4472-9997-8e5d76b32fb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510700659 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.510700659
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2500788113
Short name T126
Test name
Test status
Simulation time 88209211810 ps
CPU time 64.98 seconds
Started Jun 28 07:26:08 PM PDT 24
Finished Jun 28 07:27:35 PM PDT 24
Peak memory 191736 kb
Host smart-c053fecf-4c90-4b7a-857e-00fd35ee08b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500788113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2500788113
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2398603042
Short name T1
Test name
Test status
Simulation time 42686920539 ps
CPU time 164.44 seconds
Started Jun 28 07:26:26 PM PDT 24
Finished Jun 28 07:29:36 PM PDT 24
Peak memory 206596 kb
Host smart-d8cc92e7-5a00-4e5f-a453-152816415b34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398603042 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2398603042
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3158881200
Short name T108
Test name
Test status
Simulation time 43894163772 ps
CPU time 84.49 seconds
Started Jun 28 07:25:49 PM PDT 24
Finished Jun 28 07:27:26 PM PDT 24
Peak memory 198448 kb
Host smart-7b2cbf32-76fb-4e97-aa71-0e773efb954d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158881200 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3158881200
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2422373561
Short name T102
Test name
Test status
Simulation time 128629616193 ps
CPU time 41 seconds
Started Jun 28 07:26:47 PM PDT 24
Finished Jun 28 07:28:04 PM PDT 24
Peak memory 184016 kb
Host smart-a929e263-573f-4480-8694-f90af1c0f0fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422373561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2422373561
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3279536217
Short name T90
Test name
Test status
Simulation time 76804356300 ps
CPU time 23.41 seconds
Started Jun 28 07:26:07 PM PDT 24
Finished Jun 28 07:26:51 PM PDT 24
Peak memory 198088 kb
Host smart-12a7f866-30c3-4af7-a7d8-12f443ca4aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279536217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3279536217
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1070973628
Short name T120
Test name
Test status
Simulation time 32254344808 ps
CPU time 23.13 seconds
Started Jun 28 07:26:07 PM PDT 24
Finished Jun 28 07:26:51 PM PDT 24
Peak memory 192744 kb
Host smart-51e0f331-7058-40ca-a66d-4d212187c204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070973628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1070973628
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3854980225
Short name T95
Test name
Test status
Simulation time 34840006445 ps
CPU time 287.23 seconds
Started Jun 28 07:26:37 PM PDT 24
Finished Jun 28 07:31:56 PM PDT 24
Peak memory 206672 kb
Host smart-9a1e8840-8e3f-4a30-9044-6763f5a70fca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854980225 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3854980225
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1725754614
Short name T117
Test name
Test status
Simulation time 93475193413 ps
CPU time 58.88 seconds
Started Jun 28 07:26:50 PM PDT 24
Finished Jun 28 07:28:24 PM PDT 24
Peak memory 184016 kb
Host smart-a0864b12-6fdc-4349-bc1c-ccc83da564d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725754614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1725754614
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.317680506
Short name T75
Test name
Test status
Simulation time 51054255961 ps
CPU time 197.79 seconds
Started Jun 28 07:25:35 PM PDT 24
Finished Jun 28 07:28:58 PM PDT 24
Peak memory 206612 kb
Host smart-40b74c6c-90aa-484f-bcdd-dfa35cad381c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317680506 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.317680506
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.807885133
Short name T41
Test name
Test status
Simulation time 49266708993 ps
CPU time 346.67 seconds
Started Jun 28 07:25:53 PM PDT 24
Finished Jun 28 07:31:54 PM PDT 24
Peak memory 206616 kb
Host smart-48a18678-85f3-4308-91b3-b22709aa07e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807885133 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.807885133
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1345238413
Short name T91
Test name
Test status
Simulation time 48415427204 ps
CPU time 72.82 seconds
Started Jun 28 07:26:27 PM PDT 24
Finished Jun 28 07:28:05 PM PDT 24
Peak memory 192740 kb
Host smart-762c9a11-d45c-4c45-9071-419fabd4d006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345238413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1345238413
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2513389977
Short name T151
Test name
Test status
Simulation time 264185971003 ps
CPU time 362.68 seconds
Started Jun 28 07:26:37 PM PDT 24
Finished Jun 28 07:33:11 PM PDT 24
Peak memory 198076 kb
Host smart-02c83414-1d09-443b-b8b4-fb8f5841fa85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513389977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2513389977
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.167507546
Short name T136
Test name
Test status
Simulation time 21023514360 ps
CPU time 219.02 seconds
Started Jun 28 07:26:09 PM PDT 24
Finished Jun 28 07:30:11 PM PDT 24
Peak memory 206736 kb
Host smart-58b7856d-2517-4fd5-a496-63397148c788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167507546 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.167507546
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3474319876
Short name T127
Test name
Test status
Simulation time 233547760578 ps
CPU time 443.42 seconds
Started Jun 28 07:26:08 PM PDT 24
Finished Jun 28 07:33:54 PM PDT 24
Peak memory 211160 kb
Host smart-b4aa036c-e181-4f46-ab1d-994b5e472902
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474319876 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3474319876
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3716057138
Short name T8
Test name
Test status
Simulation time 20683385199 ps
CPU time 28.24 seconds
Started Jun 28 07:26:09 PM PDT 24
Finished Jun 28 07:27:00 PM PDT 24
Peak memory 192308 kb
Host smart-ec758273-58b6-4071-8918-d781b7766dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716057138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3716057138
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.136004809
Short name T148
Test name
Test status
Simulation time 46548016903 ps
CPU time 63.99 seconds
Started Jun 28 07:25:34 PM PDT 24
Finished Jun 28 07:26:44 PM PDT 24
Peak memory 198004 kb
Host smart-bc976961-8046-4149-b073-11088f2ac8ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136004809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.136004809
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2950792729
Short name T158
Test name
Test status
Simulation time 428247979486 ps
CPU time 505.65 seconds
Started Jun 28 07:26:10 PM PDT 24
Finished Jun 28 07:34:58 PM PDT 24
Peak memory 191868 kb
Host smart-ecea0128-d185-46a7-897f-1a66941676d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950792729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2950792729
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2370325426
Short name T28
Test name
Test status
Simulation time 151747123246 ps
CPU time 191.05 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:30:01 PM PDT 24
Peak memory 192324 kb
Host smart-608fd718-edef-4e6b-96d6-8c54f501fc7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370325426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2370325426
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.44233580
Short name T144
Test name
Test status
Simulation time 146952289410 ps
CPU time 218.01 seconds
Started Jun 28 07:26:39 PM PDT 24
Finished Jun 28 07:30:49 PM PDT 24
Peak memory 191624 kb
Host smart-fbea35eb-e853-43a3-82a8-11580bc27e44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44233580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_al
l.44233580
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1689629653
Short name T149
Test name
Test status
Simulation time 75356859062 ps
CPU time 26.47 seconds
Started Jun 28 07:25:31 PM PDT 24
Finished Jun 28 07:26:01 PM PDT 24
Peak memory 192956 kb
Host smart-9756cb54-1ccb-4669-b5d9-a8627fc3225d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689629653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1689629653
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3560056510
Short name T157
Test name
Test status
Simulation time 162749054516 ps
CPU time 354.88 seconds
Started Jun 28 07:26:27 PM PDT 24
Finished Jun 28 07:32:47 PM PDT 24
Peak memory 201952 kb
Host smart-ac875c1c-be41-42b1-83de-80774649da42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560056510 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3560056510
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.4031856312
Short name T140
Test name
Test status
Simulation time 146575715239 ps
CPU time 39.61 seconds
Started Jun 28 07:26:26 PM PDT 24
Finished Jun 28 07:27:31 PM PDT 24
Peak memory 193060 kb
Host smart-04bbb7fa-3dab-4e91-aaed-235be435bb86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031856312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.4031856312
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3219541622
Short name T78
Test name
Test status
Simulation time 72989032708 ps
CPU time 556.54 seconds
Started Jun 28 07:26:40 PM PDT 24
Finished Jun 28 07:36:30 PM PDT 24
Peak memory 213940 kb
Host smart-1de48242-c3a9-45d0-a6c9-7e9c493d380c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219541622 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3219541622
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1430835709
Short name T145
Test name
Test status
Simulation time 179051615278 ps
CPU time 505.05 seconds
Started Jun 28 07:26:52 PM PDT 24
Finished Jun 28 07:35:54 PM PDT 24
Peak memory 206660 kb
Host smart-28b1d53e-947d-4388-bb27-18f5243feffb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430835709 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1430835709
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1082741324
Short name T138
Test name
Test status
Simulation time 386825812286 ps
CPU time 76.98 seconds
Started Jun 28 07:25:49 PM PDT 24
Finished Jun 28 07:27:18 PM PDT 24
Peak memory 192816 kb
Host smart-6603fffb-eccb-49b5-bff1-a1c4cfd2354b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082741324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1082741324
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.4175745581
Short name T7
Test name
Test status
Simulation time 98493783092 ps
CPU time 31.41 seconds
Started Jun 28 07:26:40 PM PDT 24
Finished Jun 28 07:27:44 PM PDT 24
Peak memory 192528 kb
Host smart-9a29aa87-0f85-47a8-8c53-aa6404935054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175745581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.4175745581
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3741627610
Short name T30
Test name
Test status
Simulation time 61447927566 ps
CPU time 130.57 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:27:48 PM PDT 24
Peak memory 198856 kb
Host smart-f4a0580c-4840-4674-a173-b3a7464dfd5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741627610 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3741627610
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.371232704
Short name T134
Test name
Test status
Simulation time 417130456050 ps
CPU time 285.3 seconds
Started Jun 28 07:25:34 PM PDT 24
Finished Jun 28 07:30:25 PM PDT 24
Peak memory 184168 kb
Host smart-5f58db23-6d98-4c69-8323-1cc968a5c12a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371232704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.371232704
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.4011965946
Short name T73
Test name
Test status
Simulation time 37816299128 ps
CPU time 331.41 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:32:21 PM PDT 24
Peak memory 214868 kb
Host smart-f2efe7ac-9b0c-459d-bc09-3597a5d6ae47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011965946 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.4011965946
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3118528591
Short name T119
Test name
Test status
Simulation time 171780732480 ps
CPU time 120.89 seconds
Started Jun 28 07:26:46 PM PDT 24
Finished Jun 28 07:29:23 PM PDT 24
Peak memory 191720 kb
Host smart-4e7c880b-586d-4320-82c9-517e9ac078cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118528591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3118528591
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3949466464
Short name T169
Test name
Test status
Simulation time 190489973786 ps
CPU time 45.41 seconds
Started Jun 28 07:25:31 PM PDT 24
Finished Jun 28 07:26:19 PM PDT 24
Peak memory 191720 kb
Host smart-5d9a7896-90ee-45e2-b594-be30fff597b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949466464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3949466464
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2587588759
Short name T179
Test name
Test status
Simulation time 285069339906 ps
CPU time 46.65 seconds
Started Jun 28 07:25:38 PM PDT 24
Finished Jun 28 07:26:31 PM PDT 24
Peak memory 192396 kb
Host smart-8c1f0431-237d-4192-92a0-64bcae24914c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587588759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2587588759
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3927668649
Short name T161
Test name
Test status
Simulation time 285015793873 ps
CPU time 202.97 seconds
Started Jun 28 07:26:08 PM PDT 24
Finished Jun 28 07:29:53 PM PDT 24
Peak memory 191728 kb
Host smart-72c506f9-da2a-4a47-9ff4-549bf7ce11d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927668649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3927668649
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.50195278
Short name T114
Test name
Test status
Simulation time 544718907 ps
CPU time 1.29 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:26:51 PM PDT 24
Peak memory 196708 kb
Host smart-80136c4f-d8b5-4497-9dac-2e3d626cada0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50195278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.50195278
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3347411099
Short name T2
Test name
Test status
Simulation time 507631268 ps
CPU time 0.78 seconds
Started Jun 28 07:26:27 PM PDT 24
Finished Jun 28 07:26:53 PM PDT 24
Peak memory 196508 kb
Host smart-367d7788-b8a7-416a-81a7-7b62ee75b4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347411099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3347411099
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.506446441
Short name T146
Test name
Test status
Simulation time 397809537 ps
CPU time 0.79 seconds
Started Jun 28 07:25:31 PM PDT 24
Finished Jun 28 07:25:35 PM PDT 24
Peak memory 196656 kb
Host smart-0dc25e7c-4256-49c0-9e00-e81d61427b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506446441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.506446441
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2465185872
Short name T122
Test name
Test status
Simulation time 385276530 ps
CPU time 0.71 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:26:06 PM PDT 24
Peak memory 196480 kb
Host smart-a6dce107-ff7d-42ce-ba81-c3146afac11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465185872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2465185872
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2628847418
Short name T39
Test name
Test status
Simulation time 55520026468 ps
CPU time 250.12 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:30:15 PM PDT 24
Peak memory 206644 kb
Host smart-036949f8-9ffe-4295-9e3c-a5c3dee1476a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628847418 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2628847418
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.4116143576
Short name T112
Test name
Test status
Simulation time 551231755 ps
CPU time 1.3 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:25:40 PM PDT 24
Peak memory 196496 kb
Host smart-85ab5a35-8add-4046-ab1d-02f85e895336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116143576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.4116143576
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1655765701
Short name T23
Test name
Test status
Simulation time 392200009380 ps
CPU time 514.21 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:34:39 PM PDT 24
Peak memory 198092 kb
Host smart-5c7ee289-51e8-4ed0-9767-e80d2aeffcc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655765701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1655765701
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1575956556
Short name T185
Test name
Test status
Simulation time 535211545365 ps
CPU time 150.82 seconds
Started Jun 28 07:26:05 PM PDT 24
Finished Jun 28 07:28:57 PM PDT 24
Peak memory 191744 kb
Host smart-50d4b22b-6af4-440d-bcca-12fb101a52dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575956556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1575956556
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3055500003
Short name T130
Test name
Test status
Simulation time 483601414 ps
CPU time 0.95 seconds
Started Jun 28 07:26:07 PM PDT 24
Finished Jun 28 07:26:29 PM PDT 24
Peak memory 196456 kb
Host smart-e1add8f5-7f0c-42eb-9aed-9a4fc85c53ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055500003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3055500003
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3337591403
Short name T74
Test name
Test status
Simulation time 623079873857 ps
CPU time 92.01 seconds
Started Jun 28 07:26:45 PM PDT 24
Finished Jun 28 07:28:52 PM PDT 24
Peak memory 198412 kb
Host smart-8f158a27-0f0a-498b-8e43-db3161ea17b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337591403 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3337591403
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2150858222
Short name T113
Test name
Test status
Simulation time 30214837137 ps
CPU time 258.37 seconds
Started Jun 28 07:26:45 PM PDT 24
Finished Jun 28 07:31:38 PM PDT 24
Peak memory 214516 kb
Host smart-61a2ffff-8b71-40e3-a5a6-e89127dd0981
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150858222 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2150858222
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1626893121
Short name T137
Test name
Test status
Simulation time 439889574 ps
CPU time 0.71 seconds
Started Jun 28 07:26:50 PM PDT 24
Finished Jun 28 07:27:25 PM PDT 24
Peak memory 196464 kb
Host smart-19f8ac4d-3d82-4be3-8ab9-dd884ecde9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626893121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1626893121
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.880491806
Short name T143
Test name
Test status
Simulation time 472808137 ps
CPU time 0.77 seconds
Started Jun 28 07:26:08 PM PDT 24
Finished Jun 28 07:26:29 PM PDT 24
Peak memory 196468 kb
Host smart-ce250b8e-1e56-4a28-b2cb-c01d4b61f675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880491806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.880491806
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1128096389
Short name T103
Test name
Test status
Simulation time 356077768 ps
CPU time 0.94 seconds
Started Jun 28 07:26:11 PM PDT 24
Finished Jun 28 07:26:34 PM PDT 24
Peak memory 196488 kb
Host smart-a92c7f79-0d96-41b7-a337-fea659427949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128096389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1128096389
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.679021135
Short name T29
Test name
Test status
Simulation time 375102194 ps
CPU time 1.11 seconds
Started Jun 28 07:26:42 PM PDT 24
Finished Jun 28 07:27:15 PM PDT 24
Peak memory 196476 kb
Host smart-c1d7965c-2d76-4a84-a821-1f6ac7b5389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679021135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.679021135
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3176168236
Short name T93
Test name
Test status
Simulation time 452616101 ps
CPU time 1.15 seconds
Started Jun 28 07:26:45 PM PDT 24
Finished Jun 28 07:27:20 PM PDT 24
Peak memory 196464 kb
Host smart-dea339b7-cdf2-44ef-b72f-28a80c3de4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176168236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3176168236
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1447884314
Short name T147
Test name
Test status
Simulation time 550902136 ps
CPU time 0.75 seconds
Started Jun 28 07:25:34 PM PDT 24
Finished Jun 28 07:25:41 PM PDT 24
Peak memory 196468 kb
Host smart-5ff35c82-251b-4f32-b5b9-8c559edc2c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447884314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1447884314
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3977690373
Short name T123
Test name
Test status
Simulation time 166039791747 ps
CPU time 242.4 seconds
Started Jun 28 07:25:53 PM PDT 24
Finished Jun 28 07:30:10 PM PDT 24
Peak memory 191704 kb
Host smart-52e3c949-c9d7-4221-8df2-4670d101295b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977690373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3977690373
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.862875046
Short name T19
Test name
Test status
Simulation time 494892167 ps
CPU time 1.01 seconds
Started Jun 28 07:25:53 PM PDT 24
Finished Jun 28 07:26:08 PM PDT 24
Peak memory 196492 kb
Host smart-b7a09c80-27fd-4780-a179-21917059812b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862875046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.862875046
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.4122869854
Short name T4
Test name
Test status
Simulation time 201908061414 ps
CPU time 304.41 seconds
Started Jun 28 07:25:46 PM PDT 24
Finished Jun 28 07:31:02 PM PDT 24
Peak memory 191724 kb
Host smart-7ad82559-9f1e-4bef-9684-e759ff0ca460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122869854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.4122869854
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3851675357
Short name T139
Test name
Test status
Simulation time 563644656 ps
CPU time 0.78 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:26:05 PM PDT 24
Peak memory 196448 kb
Host smart-e4c9b297-3129-4a68-9677-4da64f956aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851675357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3851675357
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.4100674222
Short name T96
Test name
Test status
Simulation time 377190550 ps
CPU time 0.89 seconds
Started Jun 28 07:26:04 PM PDT 24
Finished Jun 28 07:26:25 PM PDT 24
Peak memory 196472 kb
Host smart-45eb8517-0fd6-4b9a-8a91-1e3c19b464b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100674222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.4100674222
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2195246442
Short name T129
Test name
Test status
Simulation time 80288023446 ps
CPU time 216.51 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:30:26 PM PDT 24
Peak memory 207920 kb
Host smart-3387368a-fbbd-4920-862c-4ee0b85429ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195246442 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2195246442
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2247322230
Short name T45
Test name
Test status
Simulation time 537663770 ps
CPU time 0.76 seconds
Started Jun 28 07:25:32 PM PDT 24
Finished Jun 28 07:25:36 PM PDT 24
Peak memory 196520 kb
Host smart-7d998300-1381-42a4-9e56-8689d8fa71cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247322230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2247322230
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1925279869
Short name T97
Test name
Test status
Simulation time 392004171 ps
CPU time 0.83 seconds
Started Jun 28 07:26:40 PM PDT 24
Finished Jun 28 07:27:14 PM PDT 24
Peak memory 196408 kb
Host smart-643b3b4c-656a-42f7-9219-1e0ceb26f8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925279869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1925279869
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2953500133
Short name T154
Test name
Test status
Simulation time 64896047747 ps
CPU time 50 seconds
Started Jun 28 07:25:36 PM PDT 24
Finished Jun 28 07:26:32 PM PDT 24
Peak memory 191724 kb
Host smart-6dc96905-38b4-44ce-b1c2-2fadb9d15efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953500133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2953500133
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.4144786950
Short name T162
Test name
Test status
Simulation time 143641963519 ps
CPU time 603.43 seconds
Started Jun 28 07:25:49 PM PDT 24
Finished Jun 28 07:36:05 PM PDT 24
Peak memory 206688 kb
Host smart-60d56946-2ae3-4e4a-b3b7-0d34c4ca9836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144786950 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.4144786950
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1679460961
Short name T128
Test name
Test status
Simulation time 440068342 ps
CPU time 1.17 seconds
Started Jun 28 07:25:49 PM PDT 24
Finished Jun 28 07:26:02 PM PDT 24
Peak memory 196512 kb
Host smart-3c18c0a4-6c10-4cac-b779-5caa4be2bcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679460961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1679460961
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2464594460
Short name T106
Test name
Test status
Simulation time 115264870432 ps
CPU time 44.57 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:26:49 PM PDT 24
Peak memory 198084 kb
Host smart-0dec4367-c352-42e8-b6da-0fe6317e8971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464594460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2464594460
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1457313946
Short name T101
Test name
Test status
Simulation time 577548096 ps
CPU time 0.96 seconds
Started Jun 28 07:25:35 PM PDT 24
Finished Jun 28 07:25:43 PM PDT 24
Peak memory 196540 kb
Host smart-9d7a4e47-1db3-4e62-81a7-ad887ce75a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457313946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1457313946
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1805984062
Short name T115
Test name
Test status
Simulation time 447783860 ps
CPU time 1.19 seconds
Started Jun 28 07:25:53 PM PDT 24
Finished Jun 28 07:26:09 PM PDT 24
Peak memory 196408 kb
Host smart-6849bb5d-b1d2-4cc5-8c14-4259afd3dcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805984062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1805984062
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1909939187
Short name T155
Test name
Test status
Simulation time 508407565 ps
CPU time 0.98 seconds
Started Jun 28 07:25:34 PM PDT 24
Finished Jun 28 07:25:41 PM PDT 24
Peak memory 196500 kb
Host smart-de2b5cb3-f4bf-4616-aa12-df5f14ff36f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909939187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1909939187
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3153850765
Short name T94
Test name
Test status
Simulation time 375842053 ps
CPU time 0.73 seconds
Started Jun 28 07:26:04 PM PDT 24
Finished Jun 28 07:26:25 PM PDT 24
Peak memory 196564 kb
Host smart-fe7ca77c-55ae-4eeb-945d-c52a1d08cf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153850765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3153850765
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.261416245
Short name T176
Test name
Test status
Simulation time 38683220903 ps
CPU time 26.86 seconds
Started Jun 28 07:26:09 PM PDT 24
Finished Jun 28 07:26:58 PM PDT 24
Peak memory 197996 kb
Host smart-44cce057-3352-467d-b9d8-a011ee810bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261416245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.261416245
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3657272734
Short name T159
Test name
Test status
Simulation time 214394122763 ps
CPU time 74.87 seconds
Started Jun 28 07:26:51 PM PDT 24
Finished Jun 28 07:28:41 PM PDT 24
Peak memory 192320 kb
Host smart-21e15cfa-f046-495f-881a-034fdfa18b01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657272734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3657272734
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1848517492
Short name T191
Test name
Test status
Simulation time 8040489408 ps
CPU time 7.38 seconds
Started Jun 28 06:36:11 PM PDT 24
Finished Jun 28 06:36:20 PM PDT 24
Peak memory 198272 kb
Host smart-5ee91a54-3c87-4352-ab0b-599ac2acbcfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848517492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1848517492
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1086272401
Short name T163
Test name
Test status
Simulation time 648771372 ps
CPU time 0.7 seconds
Started Jun 28 07:26:07 PM PDT 24
Finished Jun 28 07:26:29 PM PDT 24
Peak memory 196432 kb
Host smart-617857ca-d27f-46fb-86a1-ad1d18585db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086272401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1086272401
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.681168836
Short name T165
Test name
Test status
Simulation time 74832061886 ps
CPU time 201.24 seconds
Started Jun 28 07:26:08 PM PDT 24
Finished Jun 28 07:29:51 PM PDT 24
Peak memory 214508 kb
Host smart-2df74926-f79a-4d41-b56f-bd9617c79c55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681168836 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.681168836
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.138726153
Short name T166
Test name
Test status
Simulation time 423846559 ps
CPU time 0.92 seconds
Started Jun 28 07:26:06 PM PDT 24
Finished Jun 28 07:26:27 PM PDT 24
Peak memory 196384 kb
Host smart-20cfddbb-bece-485e-b6db-693a7b24db86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138726153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.138726153
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.4043919822
Short name T175
Test name
Test status
Simulation time 419396397 ps
CPU time 1.16 seconds
Started Jun 28 07:26:26 PM PDT 24
Finished Jun 28 07:26:51 PM PDT 24
Peak memory 196424 kb
Host smart-c9692634-2780-4f84-a43f-5b7a11a3c3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043919822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4043919822
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2437444645
Short name T182
Test name
Test status
Simulation time 455463628 ps
CPU time 0.79 seconds
Started Jun 28 07:26:40 PM PDT 24
Finished Jun 28 07:27:14 PM PDT 24
Peak memory 196460 kb
Host smart-ddfdd6f4-8f20-44e7-9390-737e425646d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437444645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2437444645
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3880818905
Short name T133
Test name
Test status
Simulation time 429895061 ps
CPU time 0.69 seconds
Started Jun 28 07:26:43 PM PDT 24
Finished Jun 28 07:27:17 PM PDT 24
Peak memory 196500 kb
Host smart-ed850085-b1c3-4543-805d-e29b6dde10b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880818905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3880818905
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.548289852
Short name T76
Test name
Test status
Simulation time 19405756961 ps
CPU time 144.44 seconds
Started Jun 28 07:25:35 PM PDT 24
Finished Jun 28 07:28:06 PM PDT 24
Peak memory 198456 kb
Host smart-64a8fdba-13ea-4949-9ed4-603a95e4fcde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548289852 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.548289852
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1616442983
Short name T172
Test name
Test status
Simulation time 500723137 ps
CPU time 1.4 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:26:06 PM PDT 24
Peak memory 196452 kb
Host smart-53958b41-8a26-4fd7-91e7-2f77983afc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616442983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1616442983
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2112948808
Short name T177
Test name
Test status
Simulation time 508568560 ps
CPU time 0.75 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:26:05 PM PDT 24
Peak memory 196476 kb
Host smart-c1e30f4f-e1f1-4427-9f41-1077d9806541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112948808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2112948808
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.952128551
Short name T43
Test name
Test status
Simulation time 593925818 ps
CPU time 0.79 seconds
Started Jun 28 07:26:06 PM PDT 24
Finished Jun 28 07:26:27 PM PDT 24
Peak memory 196444 kb
Host smart-6439b04e-37ce-4a02-aa30-ed2e0216fd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952128551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.952128551
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.306045150
Short name T156
Test name
Test status
Simulation time 429137210857 ps
CPU time 63.9 seconds
Started Jun 28 07:26:23 PM PDT 24
Finished Jun 28 07:27:53 PM PDT 24
Peak memory 192704 kb
Host smart-26f989c0-a9d3-46f2-b6ec-a0e960fc0384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306045150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.306045150
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2568919544
Short name T80
Test name
Test status
Simulation time 446003891 ps
CPU time 0.74 seconds
Started Jun 28 07:26:24 PM PDT 24
Finished Jun 28 07:26:50 PM PDT 24
Peak memory 196432 kb
Host smart-08f66dd8-ce3a-4f06-aecc-8b3b21439bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568919544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2568919544
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1138509784
Short name T170
Test name
Test status
Simulation time 64838028297 ps
CPU time 21.63 seconds
Started Jun 28 07:26:38 PM PDT 24
Finished Jun 28 07:27:33 PM PDT 24
Peak memory 192728 kb
Host smart-71f45782-0a63-4f0a-91a5-6099d898aa39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138509784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1138509784
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.415743066
Short name T167
Test name
Test status
Simulation time 201354695017 ps
CPU time 157.69 seconds
Started Jun 28 07:26:47 PM PDT 24
Finished Jun 28 07:30:01 PM PDT 24
Peak memory 191608 kb
Host smart-f6ee0b63-c354-4a9c-ad58-e79fc7335560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415743066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.415743066
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3483154059
Short name T160
Test name
Test status
Simulation time 609057505 ps
CPU time 1.03 seconds
Started Jun 28 07:26:45 PM PDT 24
Finished Jun 28 07:27:20 PM PDT 24
Peak memory 196472 kb
Host smart-f2376067-4965-4189-97f3-fcac1cacfa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483154059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3483154059
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3604170772
Short name T190
Test name
Test status
Simulation time 597962329 ps
CPU time 0.65 seconds
Started Jun 28 07:26:40 PM PDT 24
Finished Jun 28 07:27:14 PM PDT 24
Peak memory 196532 kb
Host smart-77d2fcad-9139-488e-9f5a-6646048c310d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604170772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3604170772
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2063049125
Short name T125
Test name
Test status
Simulation time 519004913 ps
CPU time 0.94 seconds
Started Jun 28 07:26:40 PM PDT 24
Finished Jun 28 07:27:14 PM PDT 24
Peak memory 196460 kb
Host smart-c9c5cef5-22dd-4b87-b205-2ba626fc83d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063049125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2063049125
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.729908391
Short name T107
Test name
Test status
Simulation time 177506780727 ps
CPU time 131.31 seconds
Started Jun 28 07:26:46 PM PDT 24
Finished Jun 28 07:29:33 PM PDT 24
Peak memory 191720 kb
Host smart-d1a5ddd8-22f4-4e0b-a430-23c82ae3dfa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729908391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.729908391
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3038893952
Short name T181
Test name
Test status
Simulation time 68667141607 ps
CPU time 215.03 seconds
Started Jun 28 07:26:43 PM PDT 24
Finished Jun 28 07:30:51 PM PDT 24
Peak memory 214768 kb
Host smart-169a5da7-0536-42a8-9085-e3a0f3ba5a20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038893952 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3038893952
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2452617254
Short name T188
Test name
Test status
Simulation time 480299765 ps
CPU time 0.76 seconds
Started Jun 28 07:25:31 PM PDT 24
Finished Jun 28 07:25:35 PM PDT 24
Peak memory 196512 kb
Host smart-49cab6bc-2310-4de9-9b0c-5768990c718c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452617254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2452617254
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2011605410
Short name T193
Test name
Test status
Simulation time 8705101758 ps
CPU time 4.3 seconds
Started Jun 28 06:36:11 PM PDT 24
Finished Jun 28 06:36:17 PM PDT 24
Peak memory 198304 kb
Host smart-5b255dcd-9f8b-4011-89f2-235010b58ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011605410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2011605410
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2452994917
Short name T3
Test name
Test status
Simulation time 65884925393 ps
CPU time 144.77 seconds
Started Jun 28 07:25:48 PM PDT 24
Finished Jun 28 07:28:24 PM PDT 24
Peak memory 206644 kb
Host smart-5c691ddf-442f-47ba-a5e0-4dae82a6f995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452994917 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2452994917
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2924230802
Short name T186
Test name
Test status
Simulation time 546085868 ps
CPU time 1.33 seconds
Started Jun 28 07:25:53 PM PDT 24
Finished Jun 28 07:26:09 PM PDT 24
Peak memory 196548 kb
Host smart-3245bcc1-4638-43b6-af78-1f70efab29ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924230802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2924230802
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.807762460
Short name T178
Test name
Test status
Simulation time 590122918 ps
CPU time 0.82 seconds
Started Jun 28 07:25:52 PM PDT 24
Finished Jun 28 07:26:08 PM PDT 24
Peak memory 196504 kb
Host smart-ff03a3f0-0a7f-411d-a38a-47fa53670e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807762460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.807762460
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1123064087
Short name T13
Test name
Test status
Simulation time 203289869716 ps
CPU time 274.51 seconds
Started Jun 28 07:25:49 PM PDT 24
Finished Jun 28 07:30:36 PM PDT 24
Peak memory 198048 kb
Host smart-2550494a-1d41-49f3-ad0f-58f6e3d9acde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123064087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1123064087
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2638153159
Short name T180
Test name
Test status
Simulation time 123748528199 ps
CPU time 149.06 seconds
Started Jun 28 07:25:48 PM PDT 24
Finished Jun 28 07:28:30 PM PDT 24
Peak memory 198084 kb
Host smart-34d51120-09d9-406e-8035-7637e100a5bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638153159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2638153159
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1723744291
Short name T92
Test name
Test status
Simulation time 621063442 ps
CPU time 0.81 seconds
Started Jun 28 07:26:10 PM PDT 24
Finished Jun 28 07:26:33 PM PDT 24
Peak memory 196624 kb
Host smart-db0c5d85-654d-43eb-b37c-7372a3e17156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723744291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1723744291
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1874594243
Short name T168
Test name
Test status
Simulation time 328032326220 ps
CPU time 611.53 seconds
Started Jun 28 07:26:08 PM PDT 24
Finished Jun 28 07:36:42 PM PDT 24
Peak memory 205356 kb
Host smart-2bed4047-f4e8-4770-b86a-f16bfd3b141e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874594243 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1874594243
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1069612904
Short name T153
Test name
Test status
Simulation time 569666074 ps
CPU time 1.5 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:26:51 PM PDT 24
Peak memory 196500 kb
Host smart-23200dea-c41a-4640-82d6-f9ce43381b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069612904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1069612904
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3432821997
Short name T105
Test name
Test status
Simulation time 417115076 ps
CPU time 1.18 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:26:51 PM PDT 24
Peak memory 196556 kb
Host smart-121236f3-1a0c-45d8-b495-77d32c554d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432821997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3432821997
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1835980205
Short name T189
Test name
Test status
Simulation time 585112504 ps
CPU time 1.34 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:26:51 PM PDT 24
Peak memory 196436 kb
Host smart-cd305ed9-6543-48e0-8d37-f3eb5fc60775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835980205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1835980205
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.664616641
Short name T142
Test name
Test status
Simulation time 524971645 ps
CPU time 0.83 seconds
Started Jun 28 07:26:23 PM PDT 24
Finished Jun 28 07:26:50 PM PDT 24
Peak memory 196476 kb
Host smart-a15a1863-9409-4cd7-8dff-564d3668c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664616641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.664616641
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3922714381
Short name T46
Test name
Test status
Simulation time 259988523313 ps
CPU time 403.73 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:33:33 PM PDT 24
Peak memory 183972 kb
Host smart-5ed876a2-88ff-4c5e-ab57-7a1268f22013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922714381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3922714381
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2017405892
Short name T174
Test name
Test status
Simulation time 530868227 ps
CPU time 1.2 seconds
Started Jun 28 07:26:39 PM PDT 24
Finished Jun 28 07:27:13 PM PDT 24
Peak memory 196532 kb
Host smart-34acdc84-ad4a-452a-b322-5f79bd2abc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017405892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2017405892
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.637109680
Short name T183
Test name
Test status
Simulation time 437196543 ps
CPU time 0.65 seconds
Started Jun 28 07:26:40 PM PDT 24
Finished Jun 28 07:27:14 PM PDT 24
Peak memory 196400 kb
Host smart-7e3b6bce-5e80-4eea-a9b0-1fcc1b2e7e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637109680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.637109680
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.108161938
Short name T59
Test name
Test status
Simulation time 603883142 ps
CPU time 1.87 seconds
Started Jun 28 06:35:42 PM PDT 24
Finished Jun 28 06:35:47 PM PDT 24
Peak memory 194376 kb
Host smart-09547668-7df9-4d63-ae77-c30d92f8b247
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108161938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.108161938
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3994129556
Short name T37
Test name
Test status
Simulation time 7153292955 ps
CPU time 4.67 seconds
Started Jun 28 06:35:41 PM PDT 24
Finished Jun 28 06:35:49 PM PDT 24
Peak memory 195784 kb
Host smart-7879d6b6-25d7-4f0f-aaec-a886b39e824b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994129556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3994129556
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3819675656
Short name T62
Test name
Test status
Simulation time 1312839745 ps
CPU time 2.63 seconds
Started Jun 28 06:35:48 PM PDT 24
Finished Jun 28 06:35:53 PM PDT 24
Peak memory 193164 kb
Host smart-4b00cc2d-4db5-499e-8bce-a0e2b2f2cdad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819675656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3819675656
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.240802047
Short name T324
Test name
Test status
Simulation time 549943679 ps
CPU time 0.96 seconds
Started Jun 28 06:35:43 PM PDT 24
Finished Jun 28 06:35:47 PM PDT 24
Peak memory 196144 kb
Host smart-3ec6630a-588b-44c9-8338-cafc47a79429
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240802047 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.240802047
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.930421594
Short name T57
Test name
Test status
Simulation time 341551186 ps
CPU time 0.73 seconds
Started Jun 28 06:35:47 PM PDT 24
Finished Jun 28 06:35:49 PM PDT 24
Peak memory 193360 kb
Host smart-24c7986e-b37f-4b04-b795-0a8fa968a42a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930421594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.930421594
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2753495712
Short name T317
Test name
Test status
Simulation time 555773163 ps
CPU time 0.63 seconds
Started Jun 28 06:35:40 PM PDT 24
Finished Jun 28 06:35:44 PM PDT 24
Peak memory 183844 kb
Host smart-a72ca9a4-bc82-4a0b-a5ee-ea37e74d69c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753495712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2753495712
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.568354266
Short name T345
Test name
Test status
Simulation time 519878355 ps
CPU time 0.7 seconds
Started Jun 28 06:35:44 PM PDT 24
Finished Jun 28 06:35:47 PM PDT 24
Peak memory 183760 kb
Host smart-ce5e9e38-80e1-4d63-b08b-de3e06ef93ba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568354266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.568354266
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.479245968
Short name T355
Test name
Test status
Simulation time 359609999 ps
CPU time 0.58 seconds
Started Jun 28 06:35:48 PM PDT 24
Finished Jun 28 06:35:51 PM PDT 24
Peak memory 183708 kb
Host smart-b05f9e38-b2e4-4636-945e-83b6a92974aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479245968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.479245968
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.506174100
Short name T65
Test name
Test status
Simulation time 1262886901 ps
CPU time 2.24 seconds
Started Jun 28 06:35:40 PM PDT 24
Finished Jun 28 06:35:46 PM PDT 24
Peak memory 193028 kb
Host smart-a9e40cec-08ba-4b2a-ac9a-42a76eabd212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506174100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.506174100
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2958855772
Short name T289
Test name
Test status
Simulation time 302810867 ps
CPU time 2.32 seconds
Started Jun 28 06:35:45 PM PDT 24
Finished Jun 28 06:35:50 PM PDT 24
Peak memory 198780 kb
Host smart-8444e269-ba99-4e66-971f-aefde26d9404
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958855772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2958855772
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1340032015
Short name T349
Test name
Test status
Simulation time 8393511113 ps
CPU time 3.81 seconds
Started Jun 28 06:35:44 PM PDT 24
Finished Jun 28 06:35:50 PM PDT 24
Peak memory 198348 kb
Host smart-875bb5fe-43e8-4d69-aa59-28167edadaf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340032015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1340032015
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3798325244
Short name T31
Test name
Test status
Simulation time 539024029 ps
CPU time 1.04 seconds
Started Jun 28 06:35:48 PM PDT 24
Finished Jun 28 06:35:51 PM PDT 24
Peak memory 183780 kb
Host smart-53f8ec4a-75b0-4782-9cf7-e9c67a2ee554
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798325244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3798325244
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4278349672
Short name T56
Test name
Test status
Simulation time 7632716246 ps
CPU time 19.17 seconds
Started Jun 28 06:35:43 PM PDT 24
Finished Jun 28 06:36:05 PM PDT 24
Peak memory 192228 kb
Host smart-dc106566-87af-4b92-b796-8aaa1e14c390
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278349672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.4278349672
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2623621170
Short name T399
Test name
Test status
Simulation time 797992621 ps
CPU time 0.83 seconds
Started Jun 28 06:35:46 PM PDT 24
Finished Jun 28 06:35:49 PM PDT 24
Peak memory 183916 kb
Host smart-cb4c894e-bdd2-4d32-bf16-7c6764821149
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623621170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2623621170
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.849979811
Short name T313
Test name
Test status
Simulation time 623227039 ps
CPU time 0.86 seconds
Started Jun 28 06:35:53 PM PDT 24
Finished Jun 28 06:35:56 PM PDT 24
Peak memory 197704 kb
Host smart-d45c1e5d-b119-4e8e-8dd8-2f07f0e528f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849979811 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.849979811
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1142499755
Short name T63
Test name
Test status
Simulation time 295510739 ps
CPU time 1.02 seconds
Started Jun 28 06:35:42 PM PDT 24
Finished Jun 28 06:35:46 PM PDT 24
Peak memory 193452 kb
Host smart-18c79a23-d2be-4879-ab09-a09c8ebd13f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142499755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1142499755
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3180874682
Short name T392
Test name
Test status
Simulation time 451725140 ps
CPU time 0.9 seconds
Started Jun 28 06:35:42 PM PDT 24
Finished Jun 28 06:35:46 PM PDT 24
Peak memory 193052 kb
Host smart-0f4d2257-6ae4-42f5-8975-6a2f71d8e4fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180874682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3180874682
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3727843400
Short name T292
Test name
Test status
Simulation time 497842116 ps
CPU time 1.25 seconds
Started Jun 28 06:35:47 PM PDT 24
Finished Jun 28 06:35:50 PM PDT 24
Peak memory 183716 kb
Host smart-a08bfd27-1319-414a-98f4-d452f9568321
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727843400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3727843400
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.737468877
Short name T410
Test name
Test status
Simulation time 373367625 ps
CPU time 0.57 seconds
Started Jun 28 06:35:43 PM PDT 24
Finished Jun 28 06:35:46 PM PDT 24
Peak memory 183716 kb
Host smart-2a8e7b98-2de4-41b7-ad73-73babccc0125
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737468877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.737468877
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.639415857
Short name T328
Test name
Test status
Simulation time 2630236068 ps
CPU time 4.42 seconds
Started Jun 28 06:35:43 PM PDT 24
Finished Jun 28 06:35:50 PM PDT 24
Peak memory 195084 kb
Host smart-ccd09703-86ff-440a-97a8-353df4d9fe90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639415857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.639415857
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3374672816
Short name T293
Test name
Test status
Simulation time 372328124 ps
CPU time 1.5 seconds
Started Jun 28 06:35:42 PM PDT 24
Finished Jun 28 06:35:47 PM PDT 24
Peak memory 198484 kb
Host smart-fa7943a2-d961-4003-bb11-801cc0e33caa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374672816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3374672816
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.160849489
Short name T369
Test name
Test status
Simulation time 4397149806 ps
CPU time 1.7 seconds
Started Jun 28 06:35:45 PM PDT 24
Finished Jun 28 06:35:49 PM PDT 24
Peak memory 197944 kb
Host smart-756c1dfe-85a6-44b0-b552-258b044e2b34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160849489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.160849489
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3537590157
Short name T308
Test name
Test status
Simulation time 499080363 ps
CPU time 1.25 seconds
Started Jun 28 06:36:12 PM PDT 24
Finished Jun 28 06:36:16 PM PDT 24
Peak memory 195672 kb
Host smart-17d379a0-37c7-40b8-8da6-b9cff07ab4cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537590157 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3537590157
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3317611997
Short name T32
Test name
Test status
Simulation time 419926342 ps
CPU time 0.7 seconds
Started Jun 28 06:36:14 PM PDT 24
Finished Jun 28 06:36:16 PM PDT 24
Peak memory 193036 kb
Host smart-5a824724-427c-4c1a-9c3e-868881738fe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317611997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3317611997
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.107955745
Short name T371
Test name
Test status
Simulation time 554559079 ps
CPU time 0.66 seconds
Started Jun 28 06:36:10 PM PDT 24
Finished Jun 28 06:36:12 PM PDT 24
Peak memory 193064 kb
Host smart-b50fe19c-b1f6-4282-8082-7819dd847a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107955745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.107955745
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.513710509
Short name T314
Test name
Test status
Simulation time 2685927511 ps
CPU time 4.19 seconds
Started Jun 28 06:36:12 PM PDT 24
Finished Jun 28 06:36:18 PM PDT 24
Peak memory 194244 kb
Host smart-0f398197-4411-4426-b4fb-eb43c133fcbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513710509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.513710509
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1091201187
Short name T337
Test name
Test status
Simulation time 394297634 ps
CPU time 1.68 seconds
Started Jun 28 06:36:13 PM PDT 24
Finished Jun 28 06:36:17 PM PDT 24
Peak memory 198680 kb
Host smart-09162130-9c36-421f-a4f3-cc3f3b44206d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091201187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1091201187
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3035280735
Short name T326
Test name
Test status
Simulation time 591264215 ps
CPU time 0.83 seconds
Started Jun 28 06:36:10 PM PDT 24
Finished Jun 28 06:36:11 PM PDT 24
Peak memory 196140 kb
Host smart-69db7151-1595-41d4-811e-8d7b8cb89ced
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035280735 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3035280735
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2058232237
Short name T382
Test name
Test status
Simulation time 499723138 ps
CPU time 0.64 seconds
Started Jun 28 06:36:16 PM PDT 24
Finished Jun 28 06:36:18 PM PDT 24
Peak memory 193128 kb
Host smart-4ae744ab-2d07-4e90-96d4-49feb717f311
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058232237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2058232237
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.364515072
Short name T415
Test name
Test status
Simulation time 357403217 ps
CPU time 1.04 seconds
Started Jun 28 06:36:10 PM PDT 24
Finished Jun 28 06:36:13 PM PDT 24
Peak memory 183836 kb
Host smart-20dd75dc-cb13-44e9-9177-64912d6ea70c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364515072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.364515072
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2394585387
Short name T69
Test name
Test status
Simulation time 1816325800 ps
CPU time 1.23 seconds
Started Jun 28 06:36:13 PM PDT 24
Finished Jun 28 06:36:17 PM PDT 24
Peak memory 192008 kb
Host smart-ed963b05-1b77-483c-a046-e9acfe780753
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394585387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2394585387
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3785214049
Short name T321
Test name
Test status
Simulation time 370913267 ps
CPU time 1.76 seconds
Started Jun 28 06:36:14 PM PDT 24
Finished Jun 28 06:36:18 PM PDT 24
Peak memory 198684 kb
Host smart-c5f69aa3-54f4-4d4f-8142-f90b670a6f89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785214049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3785214049
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1440018938
Short name T195
Test name
Test status
Simulation time 4148688590 ps
CPU time 2.67 seconds
Started Jun 28 06:36:13 PM PDT 24
Finished Jun 28 06:36:17 PM PDT 24
Peak memory 196880 kb
Host smart-df67bbfd-e4a1-4325-832c-3daf19e3e00c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440018938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1440018938
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.185895769
Short name T367
Test name
Test status
Simulation time 593758721 ps
CPU time 1.31 seconds
Started Jun 28 06:36:12 PM PDT 24
Finished Jun 28 06:36:16 PM PDT 24
Peak memory 197192 kb
Host smart-f1295509-7661-4a13-8d1b-c31e0ce34fb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185895769 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.185895769
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4225814297
Short name T53
Test name
Test status
Simulation time 456489703 ps
CPU time 0.64 seconds
Started Jun 28 06:36:13 PM PDT 24
Finished Jun 28 06:36:15 PM PDT 24
Peak memory 193260 kb
Host smart-ed991fe7-29d9-4f77-b400-7300427ceeb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225814297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.4225814297
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3483605587
Short name T288
Test name
Test status
Simulation time 483272514 ps
CPU time 0.72 seconds
Started Jun 28 06:36:17 PM PDT 24
Finished Jun 28 06:36:19 PM PDT 24
Peak memory 192984 kb
Host smart-8feb435e-f6e0-4f76-a018-4f452bb7c298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483605587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3483605587
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4179481675
Short name T64
Test name
Test status
Simulation time 1686232042 ps
CPU time 1.98 seconds
Started Jun 28 06:36:12 PM PDT 24
Finished Jun 28 06:36:16 PM PDT 24
Peak memory 193264 kb
Host smart-4d645f1b-26a5-4246-bbcf-a3aab9b87ae1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179481675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.4179481675
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.929642880
Short name T419
Test name
Test status
Simulation time 436526253 ps
CPU time 1.56 seconds
Started Jun 28 06:36:12 PM PDT 24
Finished Jun 28 06:36:16 PM PDT 24
Peak memory 198688 kb
Host smart-a2fce2f1-79aa-465d-9eeb-57951f6b5a94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929642880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.929642880
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2199721112
Short name T194
Test name
Test status
Simulation time 4257303739 ps
CPU time 4.03 seconds
Started Jun 28 06:36:13 PM PDT 24
Finished Jun 28 06:36:19 PM PDT 24
Peak memory 198000 kb
Host smart-19d544ea-3c46-498c-a40e-cbd7317f02a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199721112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2199721112
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.604640006
Short name T296
Test name
Test status
Simulation time 440271725 ps
CPU time 0.95 seconds
Started Jun 28 06:36:12 PM PDT 24
Finished Jun 28 06:36:16 PM PDT 24
Peak memory 196456 kb
Host smart-abebc990-1b26-4e6a-b18c-4e4a0c8e3ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604640006 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.604640006
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1806163395
Short name T385
Test name
Test status
Simulation time 474850442 ps
CPU time 0.74 seconds
Started Jun 28 06:36:11 PM PDT 24
Finished Jun 28 06:36:14 PM PDT 24
Peak memory 193436 kb
Host smart-44e8690f-9d5a-4841-aa11-7831d1720fe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806163395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1806163395
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1677321565
Short name T359
Test name
Test status
Simulation time 282242631 ps
CPU time 0.95 seconds
Started Jun 28 06:36:13 PM PDT 24
Finished Jun 28 06:36:16 PM PDT 24
Peak memory 183832 kb
Host smart-6e100e77-2043-4dca-9431-85ef97a48941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677321565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1677321565
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1098756012
Short name T362
Test name
Test status
Simulation time 2184847808 ps
CPU time 1.45 seconds
Started Jun 28 06:36:12 PM PDT 24
Finished Jun 28 06:36:15 PM PDT 24
Peak memory 193116 kb
Host smart-d6d57efc-f507-4cdf-a9eb-2ae187c90d34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098756012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1098756012
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.859149720
Short name T286
Test name
Test status
Simulation time 570740318 ps
CPU time 2.8 seconds
Started Jun 28 06:36:18 PM PDT 24
Finished Jun 28 06:36:21 PM PDT 24
Peak memory 198568 kb
Host smart-5e435df1-37ca-477c-84aa-a8c9b884943c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859149720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.859149720
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.608046438
Short name T299
Test name
Test status
Simulation time 723617693 ps
CPU time 0.91 seconds
Started Jun 28 06:36:13 PM PDT 24
Finished Jun 28 06:36:16 PM PDT 24
Peak memory 197364 kb
Host smart-3955165f-2282-4726-b1db-e19286551e46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608046438 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.608046438
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3811962687
Short name T417
Test name
Test status
Simulation time 381584954 ps
CPU time 0.67 seconds
Started Jun 28 06:36:11 PM PDT 24
Finished Jun 28 06:36:13 PM PDT 24
Peak memory 192112 kb
Host smart-74b2a79a-d74f-4ca1-9486-62f40aaa15f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811962687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3811962687
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.517189283
Short name T374
Test name
Test status
Simulation time 282087237 ps
CPU time 0.77 seconds
Started Jun 28 06:36:14 PM PDT 24
Finished Jun 28 06:36:17 PM PDT 24
Peak memory 193076 kb
Host smart-66700b3a-2294-42a7-9473-70c57d2328d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517189283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.517189283
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3378041688
Short name T351
Test name
Test status
Simulation time 2487938261 ps
CPU time 2.38 seconds
Started Jun 28 06:36:13 PM PDT 24
Finished Jun 28 06:36:18 PM PDT 24
Peak memory 195476 kb
Host smart-eb1a2e40-93e1-48d1-9d35-04da7e526346
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378041688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3378041688
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3073507290
Short name T320
Test name
Test status
Simulation time 502035008 ps
CPU time 2.66 seconds
Started Jun 28 06:36:12 PM PDT 24
Finished Jun 28 06:36:16 PM PDT 24
Peak memory 198636 kb
Host smart-3be82745-c9c9-48a3-b176-b168c5649ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073507290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3073507290
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.61204778
Short name T356
Test name
Test status
Simulation time 415625240 ps
CPU time 1.15 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:29 PM PDT 24
Peak memory 195964 kb
Host smart-a8cd9da0-6102-44bd-ab37-ba35dc40ac80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61204778 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.61204778
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.788941844
Short name T55
Test name
Test status
Simulation time 363847505 ps
CPU time 0.88 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:27 PM PDT 24
Peak memory 193140 kb
Host smart-d4cb5b4d-eb9c-464a-af11-9114c95681f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788941844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.788941844
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2846634065
Short name T343
Test name
Test status
Simulation time 391209662 ps
CPU time 1.07 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:29 PM PDT 24
Peak memory 183792 kb
Host smart-7cf4b65a-298b-43db-a8ef-8f1bdf0b64f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846634065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2846634065
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4039238920
Short name T395
Test name
Test status
Simulation time 1120891362 ps
CPU time 1 seconds
Started Jun 28 06:36:21 PM PDT 24
Finished Jun 28 06:36:23 PM PDT 24
Peak memory 193096 kb
Host smart-e4a169b3-e61d-4e15-9926-612a88e7cca3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039238920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.4039238920
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1573850706
Short name T364
Test name
Test status
Simulation time 742753199 ps
CPU time 2.3 seconds
Started Jun 28 06:36:21 PM PDT 24
Finished Jun 28 06:36:24 PM PDT 24
Peak memory 198660 kb
Host smart-bee91d16-bb5f-44ce-ae10-d486981ffa30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573850706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1573850706
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1369676517
Short name T401
Test name
Test status
Simulation time 8482406740 ps
CPU time 10.66 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:38 PM PDT 24
Peak memory 198284 kb
Host smart-e774836e-4ae6-433b-a067-7bea7a6736e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369676517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1369676517
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2039987146
Short name T391
Test name
Test status
Simulation time 453978562 ps
CPU time 0.99 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:27 PM PDT 24
Peak memory 198496 kb
Host smart-74fb9e2f-635d-469e-92c8-8ffc74e9a12c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039987146 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2039987146
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2809934391
Short name T375
Test name
Test status
Simulation time 531962410 ps
CPU time 1.14 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:26 PM PDT 24
Peak memory 192092 kb
Host smart-45e2de63-467f-4fbc-9414-232af52f11cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809934391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2809934391
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3065950629
Short name T400
Test name
Test status
Simulation time 392704973 ps
CPU time 1.12 seconds
Started Jun 28 06:36:24 PM PDT 24
Finished Jun 28 06:36:30 PM PDT 24
Peak memory 183832 kb
Host smart-6186cea3-c95e-424e-bc54-63d855a6ba3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065950629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3065950629
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1678790006
Short name T70
Test name
Test status
Simulation time 1151472429 ps
CPU time 1.59 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:30 PM PDT 24
Peak memory 193040 kb
Host smart-097765d6-c3e6-48e3-99f2-c88d63ead070
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678790006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1678790006
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4007505003
Short name T285
Test name
Test status
Simulation time 686241179 ps
CPU time 1.7 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:30 PM PDT 24
Peak memory 198640 kb
Host smart-8090787e-a0ad-4289-b1b1-dc805422d244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007505003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4007505003
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3451983262
Short name T192
Test name
Test status
Simulation time 4342466773 ps
CPU time 3.95 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:32 PM PDT 24
Peak memory 197968 kb
Host smart-ab13891e-c7f4-482c-a265-f2fbf785eeaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451983262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3451983262
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3947880090
Short name T329
Test name
Test status
Simulation time 408832479 ps
CPU time 1.01 seconds
Started Jun 28 06:36:21 PM PDT 24
Finished Jun 28 06:36:23 PM PDT 24
Peak memory 195892 kb
Host smart-615da694-acb9-4f19-813c-a85dae8d352b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947880090 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3947880090
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.838284308
Short name T383
Test name
Test status
Simulation time 362126844 ps
CPU time 0.71 seconds
Started Jun 28 06:36:21 PM PDT 24
Finished Jun 28 06:36:25 PM PDT 24
Peak memory 192100 kb
Host smart-9d3d1d78-368f-4c34-83ec-66c58eeb1ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838284308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.838284308
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3154554798
Short name T287
Test name
Test status
Simulation time 465766900 ps
CPU time 0.69 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:27 PM PDT 24
Peak memory 183832 kb
Host smart-ddda4249-2815-4d2d-9c6b-efc0db60ae41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154554798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3154554798
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4231968197
Short name T406
Test name
Test status
Simulation time 1504005992 ps
CPU time 0.82 seconds
Started Jun 28 06:36:20 PM PDT 24
Finished Jun 28 06:36:23 PM PDT 24
Peak memory 193096 kb
Host smart-40333c21-9322-41a3-ba00-db8c8244ad85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231968197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.4231968197
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3824928792
Short name T339
Test name
Test status
Simulation time 392419428 ps
CPU time 1.86 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:28 PM PDT 24
Peak memory 198684 kb
Host smart-6e452c51-2ab5-4a49-9eef-cda318168133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824928792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3824928792
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.611379989
Short name T418
Test name
Test status
Simulation time 4617715591 ps
CPU time 6.6 seconds
Started Jun 28 06:36:27 PM PDT 24
Finished Jun 28 06:36:38 PM PDT 24
Peak memory 197876 kb
Host smart-3ebe88e0-d284-436e-b22f-2bd235c3738a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611379989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.611379989
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2116379851
Short name T327
Test name
Test status
Simulation time 475447614 ps
CPU time 0.93 seconds
Started Jun 28 06:36:24 PM PDT 24
Finished Jun 28 06:36:30 PM PDT 24
Peak memory 195684 kb
Host smart-0d6104c5-f86d-4938-a3b2-79035ddd7001
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116379851 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2116379851
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1553106192
Short name T51
Test name
Test status
Simulation time 313116020 ps
CPU time 1.06 seconds
Started Jun 28 06:36:24 PM PDT 24
Finished Jun 28 06:36:30 PM PDT 24
Peak memory 193368 kb
Host smart-b8f4fa16-9932-45a3-bdb6-7c16bd19c48b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553106192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1553106192
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1009227438
Short name T409
Test name
Test status
Simulation time 433590198 ps
CPU time 1.16 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:27 PM PDT 24
Peak memory 183836 kb
Host smart-13e6ed60-adae-4c54-a982-b8ea9874421c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009227438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1009227438
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2494253917
Short name T393
Test name
Test status
Simulation time 1263215089 ps
CPU time 0.84 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:26 PM PDT 24
Peak memory 193648 kb
Host smart-8ca6e43c-833f-451d-8dfd-ab2191f43277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494253917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2494253917
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.741366864
Short name T291
Test name
Test status
Simulation time 400642100 ps
CPU time 1.65 seconds
Started Jun 28 06:36:27 PM PDT 24
Finished Jun 28 06:36:33 PM PDT 24
Peak memory 198420 kb
Host smart-971206ee-8b6e-4ae7-8386-4d7c9df4e348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741366864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.741366864
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3923380576
Short name T416
Test name
Test status
Simulation time 8632387806 ps
CPU time 12.31 seconds
Started Jun 28 06:36:21 PM PDT 24
Finished Jun 28 06:36:35 PM PDT 24
Peak memory 198264 kb
Host smart-292f4d45-8aea-4840-9ee4-46f063f65258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923380576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3923380576
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3892038927
Short name T403
Test name
Test status
Simulation time 750065145 ps
CPU time 0.95 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:29 PM PDT 24
Peak memory 198468 kb
Host smart-98293342-87c4-44cf-a6f8-269cc7d2885f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892038927 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3892038927
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3394699980
Short name T319
Test name
Test status
Simulation time 377821395 ps
CPU time 0.71 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:26 PM PDT 24
Peak memory 193016 kb
Host smart-c6518ba9-2f40-433a-9e18-f6586b0cfcbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394699980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3394699980
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2767672926
Short name T368
Test name
Test status
Simulation time 485675411 ps
CPU time 0.95 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:29 PM PDT 24
Peak memory 183840 kb
Host smart-9825dd8b-7736-4bcf-a460-0cad001debc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767672926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2767672926
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2402693557
Short name T342
Test name
Test status
Simulation time 1194310534 ps
CPU time 1.5 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:30 PM PDT 24
Peak memory 193048 kb
Host smart-e2c4aefa-9683-4545-bbeb-e2ac02e41207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402693557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2402693557
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.118602831
Short name T294
Test name
Test status
Simulation time 413819780 ps
CPU time 2.45 seconds
Started Jun 28 06:36:21 PM PDT 24
Finished Jun 28 06:36:26 PM PDT 24
Peak memory 198692 kb
Host smart-e5a86590-4058-4152-a98d-81fd7740de02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118602831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.118602831
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.62593719
Short name T35
Test name
Test status
Simulation time 4150461041 ps
CPU time 3.37 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:30 PM PDT 24
Peak memory 197856 kb
Host smart-05c16b81-3a63-4263-b7ec-efee4a170384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62593719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_
intg_err.62593719
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3645222891
Short name T54
Test name
Test status
Simulation time 565353045 ps
CPU time 1.13 seconds
Started Jun 28 06:35:55 PM PDT 24
Finished Jun 28 06:35:58 PM PDT 24
Peak memory 183820 kb
Host smart-5fb447a8-302c-40a9-b044-12f87d2e0454
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645222891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3645222891
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.978151433
Short name T61
Test name
Test status
Simulation time 13306904637 ps
CPU time 13.79 seconds
Started Jun 28 06:35:56 PM PDT 24
Finished Jun 28 06:36:12 PM PDT 24
Peak memory 192208 kb
Host smart-e6099656-b35e-4553-81e7-f8eb8c5e4b0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978151433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.978151433
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1796267150
Short name T323
Test name
Test status
Simulation time 1266479749 ps
CPU time 1.4 seconds
Started Jun 28 06:35:55 PM PDT 24
Finished Jun 28 06:35:58 PM PDT 24
Peak memory 193104 kb
Host smart-c3d9361d-1ebe-4dbb-a222-5d471e81147d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796267150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1796267150
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2153699201
Short name T310
Test name
Test status
Simulation time 400715832 ps
CPU time 0.85 seconds
Started Jun 28 06:35:54 PM PDT 24
Finished Jun 28 06:35:57 PM PDT 24
Peak memory 197108 kb
Host smart-7f152a35-068e-4a45-9dd7-8d369d5febe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153699201 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2153699201
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2568183802
Short name T402
Test name
Test status
Simulation time 365579374 ps
CPU time 1.01 seconds
Started Jun 28 06:35:54 PM PDT 24
Finished Jun 28 06:35:58 PM PDT 24
Peak memory 183844 kb
Host smart-509a6015-227b-4ae1-89cb-73037dbf3f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568183802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2568183802
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.643421245
Short name T332
Test name
Test status
Simulation time 419822671 ps
CPU time 1.08 seconds
Started Jun 28 06:35:53 PM PDT 24
Finished Jun 28 06:35:57 PM PDT 24
Peak memory 183760 kb
Host smart-21912ea5-ab46-47ca-92f3-d82121aa3d67
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643421245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.643421245
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4188584001
Short name T360
Test name
Test status
Simulation time 451136654 ps
CPU time 0.6 seconds
Started Jun 28 06:35:53 PM PDT 24
Finished Jun 28 06:35:56 PM PDT 24
Peak memory 183748 kb
Host smart-c4cd9490-9739-4b87-ab15-aaad11129ff9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188584001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.4188584001
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3050675051
Short name T376
Test name
Test status
Simulation time 1331336766 ps
CPU time 3.34 seconds
Started Jun 28 06:35:54 PM PDT 24
Finished Jun 28 06:35:59 PM PDT 24
Peak memory 193264 kb
Host smart-eef8831f-0936-4d88-99fb-a2a3ad141597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050675051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3050675051
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1213417312
Short name T388
Test name
Test status
Simulation time 657631383 ps
CPU time 1.75 seconds
Started Jun 28 06:35:55 PM PDT 24
Finished Jun 28 06:35:58 PM PDT 24
Peak memory 198628 kb
Host smart-731c07fd-25c0-49cb-88ac-161ad145e495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213417312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1213417312
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2177624865
Short name T354
Test name
Test status
Simulation time 4286108811 ps
CPU time 2.26 seconds
Started Jun 28 06:35:53 PM PDT 24
Finished Jun 28 06:35:57 PM PDT 24
Peak memory 197908 kb
Host smart-b7b0d8df-c9b6-4832-9894-d75010e96121
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177624865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2177624865
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1640719593
Short name T365
Test name
Test status
Simulation time 459000311 ps
CPU time 1.22 seconds
Started Jun 28 06:36:21 PM PDT 24
Finished Jun 28 06:36:23 PM PDT 24
Peak memory 183832 kb
Host smart-e10cadf8-444a-4a79-8350-9f554e35ed2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640719593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1640719593
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2538477556
Short name T309
Test name
Test status
Simulation time 358036102 ps
CPU time 0.65 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:28 PM PDT 24
Peak memory 183832 kb
Host smart-60ab6b0e-c800-4e16-b498-6e97f268fc0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538477556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2538477556
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2601761181
Short name T300
Test name
Test status
Simulation time 378005291 ps
CPU time 0.76 seconds
Started Jun 28 06:36:20 PM PDT 24
Finished Jun 28 06:36:23 PM PDT 24
Peak memory 183828 kb
Host smart-c9287dab-e0a8-4d7d-8ce1-57948b477ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601761181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2601761181
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.750305085
Short name T338
Test name
Test status
Simulation time 578967735 ps
CPU time 0.63 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:27 PM PDT 24
Peak memory 183832 kb
Host smart-dd814a2f-2cfb-473d-9482-5004efb42286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750305085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.750305085
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1710269241
Short name T420
Test name
Test status
Simulation time 454955503 ps
CPU time 0.76 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:28 PM PDT 24
Peak memory 193056 kb
Host smart-020f057e-1a10-4d10-bd39-293093a3547d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710269241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1710269241
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3939124201
Short name T312
Test name
Test status
Simulation time 343123315 ps
CPU time 0.61 seconds
Started Jun 28 06:36:26 PM PDT 24
Finished Jun 28 06:36:31 PM PDT 24
Peak memory 183764 kb
Host smart-e6e57f6c-6c55-44b2-afc5-355773dc86b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939124201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3939124201
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2111778968
Short name T384
Test name
Test status
Simulation time 535159488 ps
CPU time 0.74 seconds
Started Jun 28 06:36:24 PM PDT 24
Finished Jun 28 06:36:30 PM PDT 24
Peak memory 193036 kb
Host smart-c71bee85-2ea2-439e-9df0-5657bd6a72a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111778968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2111778968
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3023316879
Short name T333
Test name
Test status
Simulation time 333943244 ps
CPU time 0.71 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:27 PM PDT 24
Peak memory 183844 kb
Host smart-211e9e9c-7687-4dfa-aedc-53ab6b2bfb24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023316879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3023316879
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3848469801
Short name T389
Test name
Test status
Simulation time 295826746 ps
CPU time 0.99 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:26 PM PDT 24
Peak memory 193052 kb
Host smart-498ffde5-b775-4f06-a47e-427409b861b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848469801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3848469801
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3039609048
Short name T298
Test name
Test status
Simulation time 508580146 ps
CPU time 0.83 seconds
Started Jun 28 06:36:24 PM PDT 24
Finished Jun 28 06:36:30 PM PDT 24
Peak memory 193052 kb
Host smart-50cc3e2f-6a3b-4ae5-b806-e7332731331f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039609048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3039609048
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3607656295
Short name T33
Test name
Test status
Simulation time 476637456 ps
CPU time 1.9 seconds
Started Jun 28 06:35:53 PM PDT 24
Finished Jun 28 06:35:57 PM PDT 24
Peak memory 194692 kb
Host smart-12032e48-f251-46fa-8472-76701105ac3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607656295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3607656295
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2902970516
Short name T357
Test name
Test status
Simulation time 14413781960 ps
CPU time 6.26 seconds
Started Jun 28 06:35:54 PM PDT 24
Finished Jun 28 06:36:02 PM PDT 24
Peak memory 196456 kb
Host smart-bbd076c8-2e6a-4726-a388-6f60f6e01f75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902970516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2902970516
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2256533087
Short name T405
Test name
Test status
Simulation time 1295061791 ps
CPU time 1.47 seconds
Started Jun 28 06:35:54 PM PDT 24
Finished Jun 28 06:35:58 PM PDT 24
Peak memory 193048 kb
Host smart-ef544322-8aba-4e10-af3c-a203fb735676
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256533087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2256533087
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2340100404
Short name T295
Test name
Test status
Simulation time 575996475 ps
CPU time 1.04 seconds
Started Jun 28 06:35:55 PM PDT 24
Finished Jun 28 06:35:58 PM PDT 24
Peak memory 198496 kb
Host smart-36c25e5b-44c5-4c3c-8e28-98b83f7064ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340100404 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2340100404
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.391735365
Short name T366
Test name
Test status
Simulation time 470864158 ps
CPU time 1.21 seconds
Started Jun 28 06:35:54 PM PDT 24
Finished Jun 28 06:35:58 PM PDT 24
Peak memory 193268 kb
Host smart-3d268d4e-d800-4162-a2d3-b6bc4756d3d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391735365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.391735365
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3377589333
Short name T283
Test name
Test status
Simulation time 312902040 ps
CPU time 0.68 seconds
Started Jun 28 06:35:55 PM PDT 24
Finished Jun 28 06:35:58 PM PDT 24
Peak memory 183816 kb
Host smart-fa350a3d-9fea-4ccd-993a-458e4b54f1f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377589333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3377589333
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.142495797
Short name T358
Test name
Test status
Simulation time 305423305 ps
CPU time 0.66 seconds
Started Jun 28 06:35:52 PM PDT 24
Finished Jun 28 06:35:54 PM PDT 24
Peak memory 183704 kb
Host smart-04054e17-8e87-4d24-851a-ee8a81210b82
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142495797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.142495797
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2676143304
Short name T397
Test name
Test status
Simulation time 322800396 ps
CPU time 0.95 seconds
Started Jun 28 06:35:54 PM PDT 24
Finished Jun 28 06:35:57 PM PDT 24
Peak memory 183756 kb
Host smart-e6a7433e-a304-4d43-aed5-b87ed9064e08
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676143304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2676143304
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4087150070
Short name T66
Test name
Test status
Simulation time 2152016622 ps
CPU time 5.55 seconds
Started Jun 28 06:35:53 PM PDT 24
Finished Jun 28 06:36:00 PM PDT 24
Peak memory 195136 kb
Host smart-d1466c08-5cbf-4768-b78c-03d0be48fb6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087150070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.4087150070
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1857051529
Short name T306
Test name
Test status
Simulation time 395131168 ps
CPU time 2.35 seconds
Started Jun 28 06:35:54 PM PDT 24
Finished Jun 28 06:35:59 PM PDT 24
Peak memory 198692 kb
Host smart-7af0df20-5685-4a10-849e-1127e8e3ab25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857051529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1857051529
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1333390064
Short name T407
Test name
Test status
Simulation time 8158198939 ps
CPU time 13.74 seconds
Started Jun 28 06:35:53 PM PDT 24
Finished Jun 28 06:36:08 PM PDT 24
Peak memory 198268 kb
Host smart-73dbce84-e137-4cf2-9a6e-c880cfd1060f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333390064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1333390064
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1182271762
Short name T331
Test name
Test status
Simulation time 304640423 ps
CPU time 0.67 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:29 PM PDT 24
Peak memory 193020 kb
Host smart-da75b96d-9e74-43cc-b871-8f57926c6c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182271762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1182271762
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2879624894
Short name T325
Test name
Test status
Simulation time 455141368 ps
CPU time 0.7 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:27 PM PDT 24
Peak memory 193056 kb
Host smart-24e45b65-5db8-45bb-9f19-86fb5b27338a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879624894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2879624894
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2496239981
Short name T346
Test name
Test status
Simulation time 346185061 ps
CPU time 0.97 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:27 PM PDT 24
Peak memory 183744 kb
Host smart-8ccec5b0-46ee-4dae-a72f-85a7200b76fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496239981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2496239981
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3758625553
Short name T336
Test name
Test status
Simulation time 464127032 ps
CPU time 0.78 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:28 PM PDT 24
Peak memory 183836 kb
Host smart-c213058b-f8a3-40c4-8c21-ec2009b73bb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758625553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3758625553
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1475870631
Short name T284
Test name
Test status
Simulation time 284863911 ps
CPU time 0.74 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:29 PM PDT 24
Peak memory 183836 kb
Host smart-514ef971-31eb-4dc3-8948-c38f1481ecbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475870631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1475870631
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3767916941
Short name T408
Test name
Test status
Simulation time 379664628 ps
CPU time 0.68 seconds
Started Jun 28 06:36:25 PM PDT 24
Finished Jun 28 06:36:31 PM PDT 24
Peak memory 193020 kb
Host smart-eb7ad83f-389a-4392-ac79-22fc62fbf0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767916941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3767916941
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1065972027
Short name T350
Test name
Test status
Simulation time 296307363 ps
CPU time 0.93 seconds
Started Jun 28 06:36:25 PM PDT 24
Finished Jun 28 06:36:31 PM PDT 24
Peak memory 183836 kb
Host smart-072ba998-6687-4717-9265-3e4554e589be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065972027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1065972027
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1559180923
Short name T311
Test name
Test status
Simulation time 498857212 ps
CPU time 0.71 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:29 PM PDT 24
Peak memory 183800 kb
Host smart-dbae9bfd-7670-4c4e-88aa-25fc3a0acd84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559180923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1559180923
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3487315724
Short name T303
Test name
Test status
Simulation time 517925380 ps
CPU time 0.72 seconds
Started Jun 28 06:36:22 PM PDT 24
Finished Jun 28 06:36:27 PM PDT 24
Peak memory 183744 kb
Host smart-e55b4d43-7d57-43bd-847a-358b33c000b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487315724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3487315724
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2175314113
Short name T363
Test name
Test status
Simulation time 475506300 ps
CPU time 1.15 seconds
Started Jun 28 06:36:23 PM PDT 24
Finished Jun 28 06:36:29 PM PDT 24
Peak memory 183768 kb
Host smart-101b21f0-7adb-4d83-9bf9-44072db0c0af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175314113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2175314113
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3585487454
Short name T58
Test name
Test status
Simulation time 512033230 ps
CPU time 1.51 seconds
Started Jun 28 06:36:03 PM PDT 24
Finished Jun 28 06:36:06 PM PDT 24
Peak memory 183820 kb
Host smart-f43f4646-84cc-4d37-a2fd-d53101cfee67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585487454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3585487454
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2462537847
Short name T315
Test name
Test status
Simulation time 7108383221 ps
CPU time 9.25 seconds
Started Jun 28 06:36:04 PM PDT 24
Finished Jun 28 06:36:15 PM PDT 24
Peak memory 184084 kb
Host smart-17e9f774-5d31-44e1-87f7-c59e19d3c823
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462537847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2462537847
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2518769346
Short name T412
Test name
Test status
Simulation time 961510196 ps
CPU time 2.08 seconds
Started Jun 28 06:36:08 PM PDT 24
Finished Jun 28 06:36:11 PM PDT 24
Peak memory 192120 kb
Host smart-49810422-4b37-48b2-897f-1025eefddd3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518769346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2518769346
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.933606348
Short name T370
Test name
Test status
Simulation time 401143286 ps
CPU time 1.21 seconds
Started Jun 28 06:36:02 PM PDT 24
Finished Jun 28 06:36:05 PM PDT 24
Peak memory 195884 kb
Host smart-3e32ea1b-32c3-41b1-9ed7-c7e332885b0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933606348 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.933606348
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.840185406
Short name T68
Test name
Test status
Simulation time 469704076 ps
CPU time 0.77 seconds
Started Jun 28 06:36:00 PM PDT 24
Finished Jun 28 06:36:02 PM PDT 24
Peak memory 192100 kb
Host smart-b9005115-85fc-44ad-b27b-cc27f257a4fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840185406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.840185406
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2896514708
Short name T381
Test name
Test status
Simulation time 482546353 ps
CPU time 1.26 seconds
Started Jun 28 06:35:52 PM PDT 24
Finished Jun 28 06:35:54 PM PDT 24
Peak memory 183836 kb
Host smart-10ca70c1-f6c9-40d0-a185-4a3ecb46fba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896514708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2896514708
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3731985947
Short name T373
Test name
Test status
Simulation time 445702814 ps
CPU time 1.19 seconds
Started Jun 28 06:35:56 PM PDT 24
Finished Jun 28 06:35:59 PM PDT 24
Peak memory 183736 kb
Host smart-eb98b0c9-c7a4-4623-a00d-20ca4bf2c357
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731985947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3731985947
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2546657980
Short name T347
Test name
Test status
Simulation time 392626610 ps
CPU time 0.85 seconds
Started Jun 28 06:35:54 PM PDT 24
Finished Jun 28 06:35:56 PM PDT 24
Peak memory 183748 kb
Host smart-70470efc-0de5-4d15-827f-633cca293f40
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546657980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2546657980
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3416669539
Short name T387
Test name
Test status
Simulation time 1049329634 ps
CPU time 1.75 seconds
Started Jun 28 06:36:02 PM PDT 24
Finished Jun 28 06:36:05 PM PDT 24
Peak memory 193024 kb
Host smart-ec75bf3e-3dd2-4af9-9e02-13387060b89a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416669539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3416669539
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1799275145
Short name T380
Test name
Test status
Simulation time 536348794 ps
CPU time 1.53 seconds
Started Jun 28 06:35:52 PM PDT 24
Finished Jun 28 06:35:55 PM PDT 24
Peak memory 198164 kb
Host smart-97160b3f-822c-4106-bbdc-ca9e8125deee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799275145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1799275145
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3947370232
Short name T378
Test name
Test status
Simulation time 8341611705 ps
CPU time 2.1 seconds
Started Jun 28 06:35:56 PM PDT 24
Finished Jun 28 06:36:01 PM PDT 24
Peak memory 198364 kb
Host smart-3b279387-20ca-4841-9db3-da6d8b0a616e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947370232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3947370232
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1412106876
Short name T422
Test name
Test status
Simulation time 501597620 ps
CPU time 1.34 seconds
Started Jun 28 06:36:24 PM PDT 24
Finished Jun 28 06:36:31 PM PDT 24
Peak memory 193052 kb
Host smart-a3531a74-f8ca-4106-890c-27b832bf4ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412106876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1412106876
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2205173426
Short name T372
Test name
Test status
Simulation time 282989968 ps
CPU time 0.95 seconds
Started Jun 28 06:36:32 PM PDT 24
Finished Jun 28 06:36:35 PM PDT 24
Peak memory 183808 kb
Host smart-4bbaa66e-0e47-488f-875b-5f34537f427a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205173426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2205173426
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1977211702
Short name T290
Test name
Test status
Simulation time 303633997 ps
CPU time 0.77 seconds
Started Jun 28 06:36:38 PM PDT 24
Finished Jun 28 06:36:40 PM PDT 24
Peak memory 183836 kb
Host smart-150920cd-ec62-4e72-9515-5b0e217f955f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977211702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1977211702
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1270217867
Short name T301
Test name
Test status
Simulation time 507950791 ps
CPU time 0.82 seconds
Started Jun 28 06:36:36 PM PDT 24
Finished Jun 28 06:36:38 PM PDT 24
Peak memory 193056 kb
Host smart-dd1a7cdb-0790-45c6-a027-63ca3804790b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270217867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1270217867
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3212774458
Short name T316
Test name
Test status
Simulation time 404967120 ps
CPU time 1.12 seconds
Started Jun 28 06:36:33 PM PDT 24
Finished Jun 28 06:36:35 PM PDT 24
Peak memory 183828 kb
Host smart-35c9884d-5d4d-4b59-84d2-f57dd7699f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212774458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3212774458
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1419969044
Short name T334
Test name
Test status
Simulation time 278337323 ps
CPU time 0.74 seconds
Started Jun 28 06:36:33 PM PDT 24
Finished Jun 28 06:36:36 PM PDT 24
Peak memory 183816 kb
Host smart-e57004bc-d556-43f8-955e-232ebf88ef83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419969044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1419969044
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2449837254
Short name T305
Test name
Test status
Simulation time 424068042 ps
CPU time 0.68 seconds
Started Jun 28 06:36:34 PM PDT 24
Finished Jun 28 06:36:37 PM PDT 24
Peak memory 183800 kb
Host smart-6a79f56b-1bbc-4c01-82e8-ec02a901e8eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449837254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2449837254
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2375275678
Short name T340
Test name
Test status
Simulation time 388236066 ps
CPU time 1.18 seconds
Started Jun 28 06:36:37 PM PDT 24
Finished Jun 28 06:36:39 PM PDT 24
Peak memory 183836 kb
Host smart-95060e6d-c375-4d33-857a-0e3c418152c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375275678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2375275678
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3897694203
Short name T318
Test name
Test status
Simulation time 299384294 ps
CPU time 0.95 seconds
Started Jun 28 06:36:33 PM PDT 24
Finished Jun 28 06:36:35 PM PDT 24
Peak memory 183836 kb
Host smart-996aac18-705d-407d-80dc-844ce54f38ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897694203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3897694203
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3320078157
Short name T386
Test name
Test status
Simulation time 271626548 ps
CPU time 0.82 seconds
Started Jun 28 06:36:35 PM PDT 24
Finished Jun 28 06:36:38 PM PDT 24
Peak memory 183808 kb
Host smart-f29782bb-3ba7-430a-8f57-f640871152a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320078157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3320078157
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3133495701
Short name T307
Test name
Test status
Simulation time 429635414 ps
CPU time 1.01 seconds
Started Jun 28 06:36:02 PM PDT 24
Finished Jun 28 06:36:05 PM PDT 24
Peak memory 196392 kb
Host smart-00c548da-bf84-41f9-bfe9-6b5b53f30c4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133495701 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3133495701
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1719073994
Short name T396
Test name
Test status
Simulation time 336622383 ps
CPU time 1.04 seconds
Started Jun 28 06:36:02 PM PDT 24
Finished Jun 28 06:36:04 PM PDT 24
Peak memory 193040 kb
Host smart-7f3aadbb-534d-430c-94c2-a124811d3d2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719073994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1719073994
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3548992638
Short name T348
Test name
Test status
Simulation time 314643317 ps
CPU time 0.8 seconds
Started Jun 28 06:36:03 PM PDT 24
Finished Jun 28 06:36:06 PM PDT 24
Peak memory 183840 kb
Host smart-33f08010-c12a-4c8f-b0ff-b443925db9bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548992638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3548992638
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4034409777
Short name T414
Test name
Test status
Simulation time 1972306833 ps
CPU time 3.03 seconds
Started Jun 28 06:36:06 PM PDT 24
Finished Jun 28 06:36:11 PM PDT 24
Peak memory 194148 kb
Host smart-ea099dc2-e1be-4e15-961a-beb345a27456
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034409777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.4034409777
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3963530554
Short name T379
Test name
Test status
Simulation time 618540012 ps
CPU time 1.58 seconds
Started Jun 28 06:36:06 PM PDT 24
Finished Jun 28 06:36:09 PM PDT 24
Peak memory 198472 kb
Host smart-55cd6fe2-385f-4b5c-9d8b-fc445b32660b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963530554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3963530554
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1469421781
Short name T377
Test name
Test status
Simulation time 8264495644 ps
CPU time 13.94 seconds
Started Jun 28 06:36:03 PM PDT 24
Finished Jun 28 06:36:18 PM PDT 24
Peak memory 198364 kb
Host smart-d2ec45bc-a52d-4061-85ee-76361827a36c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469421781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1469421781
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3726622903
Short name T335
Test name
Test status
Simulation time 430900565 ps
CPU time 0.78 seconds
Started Jun 28 06:36:05 PM PDT 24
Finished Jun 28 06:36:07 PM PDT 24
Peak memory 195584 kb
Host smart-be354877-4eb2-4a0d-9b60-0bba3ccc5186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726622903 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3726622903
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.906601106
Short name T398
Test name
Test status
Simulation time 418965611 ps
CPU time 0.7 seconds
Started Jun 28 06:36:04 PM PDT 24
Finished Jun 28 06:36:06 PM PDT 24
Peak memory 193092 kb
Host smart-9e739662-c782-415b-8152-4ee6b31076e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906601106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.906601106
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2793130988
Short name T297
Test name
Test status
Simulation time 274336748 ps
CPU time 0.75 seconds
Started Jun 28 06:36:03 PM PDT 24
Finished Jun 28 06:36:05 PM PDT 24
Peak memory 193000 kb
Host smart-56363e15-018d-4c86-9f56-0da33e1bf637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793130988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2793130988
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.569853985
Short name T67
Test name
Test status
Simulation time 1167811248 ps
CPU time 1.48 seconds
Started Jun 28 06:36:03 PM PDT 24
Finished Jun 28 06:36:07 PM PDT 24
Peak memory 193012 kb
Host smart-9871b857-ef4d-4283-8dfb-ce57a7872f6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569853985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.569853985
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3069987067
Short name T344
Test name
Test status
Simulation time 431634174 ps
CPU time 2.68 seconds
Started Jun 28 06:36:06 PM PDT 24
Finished Jun 28 06:36:11 PM PDT 24
Peak memory 198608 kb
Host smart-45794433-25f1-4633-b6fe-6f642272a7ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069987067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3069987067
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2592810684
Short name T394
Test name
Test status
Simulation time 8253115726 ps
CPU time 4.35 seconds
Started Jun 28 06:36:04 PM PDT 24
Finished Jun 28 06:36:10 PM PDT 24
Peak memory 198008 kb
Host smart-ad3613ae-fdcd-45da-b15e-9108102f249d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592810684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2592810684
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3018471842
Short name T411
Test name
Test status
Simulation time 576601397 ps
CPU time 1.4 seconds
Started Jun 28 06:36:06 PM PDT 24
Finished Jun 28 06:36:09 PM PDT 24
Peak memory 196324 kb
Host smart-40d8491c-d3c8-418e-951e-b57e03d44f78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018471842 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3018471842
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3062102795
Short name T60
Test name
Test status
Simulation time 403630581 ps
CPU time 1.22 seconds
Started Jun 28 06:36:02 PM PDT 24
Finished Jun 28 06:36:04 PM PDT 24
Peak memory 193200 kb
Host smart-96d07507-6496-4dc3-871f-6507752ff1ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062102795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3062102795
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2443626611
Short name T302
Test name
Test status
Simulation time 411212079 ps
CPU time 1.1 seconds
Started Jun 28 06:36:06 PM PDT 24
Finished Jun 28 06:36:09 PM PDT 24
Peak memory 183832 kb
Host smart-4c467c39-6ae0-42ec-8d30-5ddb450a0a52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443626611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2443626611
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3125292189
Short name T421
Test name
Test status
Simulation time 2068218882 ps
CPU time 2.98 seconds
Started Jun 28 06:36:02 PM PDT 24
Finished Jun 28 06:36:07 PM PDT 24
Peak memory 193940 kb
Host smart-30e8be39-1404-46f8-9daa-e1f15a7cce76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125292189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3125292189
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.75802318
Short name T404
Test name
Test status
Simulation time 444200077 ps
CPU time 2.05 seconds
Started Jun 28 06:36:04 PM PDT 24
Finished Jun 28 06:36:08 PM PDT 24
Peak memory 198656 kb
Host smart-47e54004-8463-4d70-be2d-86dfabfccf79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75802318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.75802318
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3406319921
Short name T361
Test name
Test status
Simulation time 4528688403 ps
CPU time 3.12 seconds
Started Jun 28 06:36:04 PM PDT 24
Finished Jun 28 06:36:08 PM PDT 24
Peak memory 198188 kb
Host smart-1e3e3af8-3d4c-4cae-9d91-7cf6c112e895
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406319921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3406319921
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1337296921
Short name T322
Test name
Test status
Simulation time 356241666 ps
CPU time 1.13 seconds
Started Jun 28 06:36:01 PM PDT 24
Finished Jun 28 06:36:02 PM PDT 24
Peak memory 196104 kb
Host smart-f064abd5-49b1-42a0-b925-d0f19c486805
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337296921 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1337296921
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.391587495
Short name T50
Test name
Test status
Simulation time 320451006 ps
CPU time 0.98 seconds
Started Jun 28 06:36:05 PM PDT 24
Finished Jun 28 06:36:07 PM PDT 24
Peak memory 192088 kb
Host smart-be97fdec-d1f0-4af9-91c1-533642439d61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391587495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.391587495
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3283798253
Short name T282
Test name
Test status
Simulation time 481261451 ps
CPU time 0.58 seconds
Started Jun 28 06:36:02 PM PDT 24
Finished Jun 28 06:36:04 PM PDT 24
Peak memory 183748 kb
Host smart-ea101b44-5148-42fa-b0d1-95ee3b84eaa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283798253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3283798253
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2908876561
Short name T413
Test name
Test status
Simulation time 3102121562 ps
CPU time 4.27 seconds
Started Jun 28 06:36:06 PM PDT 24
Finished Jun 28 06:36:12 PM PDT 24
Peak memory 195032 kb
Host smart-191984b2-24aa-4e97-8989-61363a29a8c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908876561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2908876561
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2816170496
Short name T341
Test name
Test status
Simulation time 749724414 ps
CPU time 0.96 seconds
Started Jun 28 06:36:06 PM PDT 24
Finished Jun 28 06:36:08 PM PDT 24
Peak memory 197084 kb
Host smart-9e1be41e-2fed-4328-b1a1-ea5926a00b95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816170496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2816170496
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1814894114
Short name T36
Test name
Test status
Simulation time 8242517813 ps
CPU time 11.71 seconds
Started Jun 28 06:36:02 PM PDT 24
Finished Jun 28 06:36:15 PM PDT 24
Peak memory 198204 kb
Host smart-0ab096a6-3fee-4cd9-832d-bd9ab6e908c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814894114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1814894114
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3832061710
Short name T352
Test name
Test status
Simulation time 447298995 ps
CPU time 0.95 seconds
Started Jun 28 06:36:11 PM PDT 24
Finished Jun 28 06:36:13 PM PDT 24
Peak memory 196196 kb
Host smart-4811a60d-1614-42c7-a662-1c3c443b7090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832061710 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3832061710
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3381166082
Short name T49
Test name
Test status
Simulation time 461693167 ps
CPU time 1.15 seconds
Started Jun 28 06:36:03 PM PDT 24
Finished Jun 28 06:36:06 PM PDT 24
Peak memory 193096 kb
Host smart-f6cd7d37-7a73-401f-8dbd-cb600e1b3695
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381166082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3381166082
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2351947160
Short name T390
Test name
Test status
Simulation time 366399883 ps
CPU time 1.08 seconds
Started Jun 28 06:36:02 PM PDT 24
Finished Jun 28 06:36:04 PM PDT 24
Peak memory 193028 kb
Host smart-d9c60733-e80c-4374-af46-4e11ea6cd465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351947160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2351947160
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.724793608
Short name T353
Test name
Test status
Simulation time 1138269976 ps
CPU time 2.28 seconds
Started Jun 28 06:36:13 PM PDT 24
Finished Jun 28 06:36:17 PM PDT 24
Peak memory 183984 kb
Host smart-8bd830f4-1e7c-44cf-b386-817edd4e21cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724793608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.724793608
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3925941482
Short name T304
Test name
Test status
Simulation time 470233003 ps
CPU time 2.92 seconds
Started Jun 28 06:36:01 PM PDT 24
Finished Jun 28 06:36:05 PM PDT 24
Peak memory 198688 kb
Host smart-9d2f37f0-d6ba-4de5-8ed4-858823118975
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925941482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3925941482
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.451557650
Short name T330
Test name
Test status
Simulation time 8283752281 ps
CPU time 4.44 seconds
Started Jun 28 06:36:05 PM PDT 24
Finished Jun 28 06:36:11 PM PDT 24
Peak memory 198388 kb
Host smart-c867bf97-da74-4589-a5ec-8c9f43774a78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451557650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.451557650
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.994675137
Short name T260
Test name
Test status
Simulation time 51025637812 ps
CPU time 75.09 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:26:52 PM PDT 24
Peak memory 191744 kb
Host smart-0336700a-2ca3-42ff-a6a4-a70c6350d843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994675137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.994675137
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2434457808
Short name T245
Test name
Test status
Simulation time 464446737 ps
CPU time 1.27 seconds
Started Jun 28 07:25:34 PM PDT 24
Finished Jun 28 07:25:42 PM PDT 24
Peak memory 191656 kb
Host smart-827e0f79-017d-487e-bc84-072b7c886734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434457808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2434457808
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1397040106
Short name T220
Test name
Test status
Simulation time 25701202932 ps
CPU time 9.73 seconds
Started Jun 28 07:25:34 PM PDT 24
Finished Jun 28 07:25:50 PM PDT 24
Peak memory 191720 kb
Host smart-8eeeaf92-23ab-441c-b95e-3c1b3d60725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397040106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1397040106
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1641012602
Short name T16
Test name
Test status
Simulation time 4343676450 ps
CPU time 2.13 seconds
Started Jun 28 07:25:32 PM PDT 24
Finished Jun 28 07:25:38 PM PDT 24
Peak memory 215796 kb
Host smart-a8c421e1-92a5-4541-a2fc-82c6eaf840c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641012602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1641012602
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2440484854
Short name T279
Test name
Test status
Simulation time 481515186 ps
CPU time 1.34 seconds
Started Jun 28 07:25:31 PM PDT 24
Finished Jun 28 07:25:36 PM PDT 24
Peak memory 191588 kb
Host smart-fcb53f46-c261-4320-a444-b2988be3ebbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440484854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2440484854
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.900340771
Short name T238
Test name
Test status
Simulation time 37038214423 ps
CPU time 8.04 seconds
Started Jun 28 07:25:48 PM PDT 24
Finished Jun 28 07:26:09 PM PDT 24
Peak memory 191836 kb
Host smart-cb04175b-37f0-4bad-81e8-c062d7592a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900340771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.900340771
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3707219379
Short name T275
Test name
Test status
Simulation time 481570500 ps
CPU time 1.31 seconds
Started Jun 28 07:25:53 PM PDT 24
Finished Jun 28 07:26:09 PM PDT 24
Peak memory 196536 kb
Host smart-c7f21e6f-61a5-40b1-a738-a21c52223189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707219379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3707219379
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.4101441994
Short name T241
Test name
Test status
Simulation time 19914148852 ps
CPU time 25.81 seconds
Started Jun 28 07:25:48 PM PDT 24
Finished Jun 28 07:26:26 PM PDT 24
Peak memory 191660 kb
Host smart-3616c70a-532e-4056-b87d-f878e951181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101441994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.4101441994
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2710768370
Short name T11
Test name
Test status
Simulation time 547375588 ps
CPU time 1.07 seconds
Started Jun 28 07:25:47 PM PDT 24
Finished Jun 28 07:26:00 PM PDT 24
Peak memory 191668 kb
Host smart-d0a536d9-59f1-4ecc-a0ff-fdcb35f0d401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710768370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2710768370
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.469258534
Short name T248
Test name
Test status
Simulation time 4572184319 ps
CPU time 6.14 seconds
Started Jun 28 07:25:48 PM PDT 24
Finished Jun 28 07:26:07 PM PDT 24
Peak memory 191744 kb
Host smart-01008483-8174-405c-9e75-40ee0267e4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469258534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.469258534
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.929310279
Short name T198
Test name
Test status
Simulation time 509306228 ps
CPU time 0.99 seconds
Started Jun 28 07:25:52 PM PDT 24
Finished Jun 28 07:26:07 PM PDT 24
Peak memory 191656 kb
Host smart-66bf067b-3f25-4e12-9cb6-cfdbc85d9c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929310279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.929310279
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3458345626
Short name T237
Test name
Test status
Simulation time 24604211669 ps
CPU time 37.49 seconds
Started Jun 28 07:25:52 PM PDT 24
Finished Jun 28 07:26:44 PM PDT 24
Peak memory 191708 kb
Host smart-39ff9419-f47e-4aec-a141-6fbe000da20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458345626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3458345626
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2249742147
Short name T278
Test name
Test status
Simulation time 383525935 ps
CPU time 0.85 seconds
Started Jun 28 07:25:52 PM PDT 24
Finished Jun 28 07:26:08 PM PDT 24
Peak memory 196508 kb
Host smart-3e8431ce-135b-461e-8ccf-58dd5ed0660c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249742147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2249742147
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_jump.4124842291
Short name T184
Test name
Test status
Simulation time 414621254 ps
CPU time 0.78 seconds
Started Jun 28 07:25:49 PM PDT 24
Finished Jun 28 07:26:03 PM PDT 24
Peak memory 196532 kb
Host smart-46555bc0-32f3-4ebb-8adc-c967e564c2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124842291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.4124842291
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3520127097
Short name T26
Test name
Test status
Simulation time 9253682854 ps
CPU time 3.89 seconds
Started Jun 28 07:25:47 PM PDT 24
Finished Jun 28 07:26:02 PM PDT 24
Peak memory 191724 kb
Host smart-725267f1-2702-438f-9897-297558c35911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520127097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3520127097
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2187569114
Short name T273
Test name
Test status
Simulation time 690192275 ps
CPU time 0.65 seconds
Started Jun 28 07:25:49 PM PDT 24
Finished Jun 28 07:26:03 PM PDT 24
Peak memory 191672 kb
Host smart-b6ec7b7d-9b04-4133-8db1-7296cab1e096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187569114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2187569114
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1693231351
Short name T276
Test name
Test status
Simulation time 25759194250 ps
CPU time 10.58 seconds
Started Jun 28 07:25:48 PM PDT 24
Finished Jun 28 07:26:12 PM PDT 24
Peak memory 196780 kb
Host smart-2ba260fc-1d92-4052-8265-e36a58f33c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693231351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1693231351
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2596916438
Short name T228
Test name
Test status
Simulation time 455512195 ps
CPU time 1.2 seconds
Started Jun 28 07:25:52 PM PDT 24
Finished Jun 28 07:26:07 PM PDT 24
Peak memory 191664 kb
Host smart-6bc6a27d-2ccb-42fa-8795-524a6c1cf5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596916438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2596916438
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.164836189
Short name T196
Test name
Test status
Simulation time 31702868646 ps
CPU time 12.94 seconds
Started Jun 28 07:25:48 PM PDT 24
Finished Jun 28 07:26:14 PM PDT 24
Peak memory 196756 kb
Host smart-eed2d594-79f8-401d-ba79-593faeefb1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164836189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.164836189
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3524391493
Short name T197
Test name
Test status
Simulation time 384364900 ps
CPU time 1.17 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:26:05 PM PDT 24
Peak memory 191668 kb
Host smart-0ba9fb05-b6c3-4817-90f5-1423e8ef3e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524391493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3524391493
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2532433851
Short name T251
Test name
Test status
Simulation time 35318351645 ps
CPU time 52.06 seconds
Started Jun 28 07:25:52 PM PDT 24
Finished Jun 28 07:26:58 PM PDT 24
Peak memory 196744 kb
Host smart-518aea72-c4ff-4547-98fd-2911853c95a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532433851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2532433851
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.251592896
Short name T211
Test name
Test status
Simulation time 442151942 ps
CPU time 1.08 seconds
Started Jun 28 07:25:49 PM PDT 24
Finished Jun 28 07:26:03 PM PDT 24
Peak memory 196504 kb
Host smart-f7e01592-1830-49b4-b03a-a41d50b90cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251592896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.251592896
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1242645289
Short name T257
Test name
Test status
Simulation time 55626609539 ps
CPU time 77.81 seconds
Started Jun 28 07:25:48 PM PDT 24
Finished Jun 28 07:27:18 PM PDT 24
Peak memory 191712 kb
Host smart-7b7ba82a-ca02-4f5b-9c0d-cdb8058c8db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242645289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1242645289
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1094728344
Short name T227
Test name
Test status
Simulation time 551284625 ps
CPU time 1.39 seconds
Started Jun 28 07:25:50 PM PDT 24
Finished Jun 28 07:26:06 PM PDT 24
Peak memory 191676 kb
Host smart-19c8b3fa-85c8-44e3-b76e-1ae487e1e1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094728344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1094728344
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1097431084
Short name T209
Test name
Test status
Simulation time 41355460787 ps
CPU time 4.45 seconds
Started Jun 28 07:26:10 PM PDT 24
Finished Jun 28 07:26:37 PM PDT 24
Peak memory 191728 kb
Host smart-e6fa7330-7e4b-4538-bc69-c90d046c36f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097431084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1097431084
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3349432798
Short name T272
Test name
Test status
Simulation time 452878919 ps
CPU time 0.75 seconds
Started Jun 28 07:26:05 PM PDT 24
Finished Jun 28 07:26:27 PM PDT 24
Peak memory 196504 kb
Host smart-c1308078-a51a-4bc8-94f6-6657a6816b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349432798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3349432798
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.775735494
Short name T244
Test name
Test status
Simulation time 27473625784 ps
CPU time 39.78 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:26:18 PM PDT 24
Peak memory 191668 kb
Host smart-102e72d2-560e-431d-9a81-10ad0518741f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775735494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.775735494
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2405960234
Short name T17
Test name
Test status
Simulation time 3895187354 ps
CPU time 5.7 seconds
Started Jun 28 07:25:36 PM PDT 24
Finished Jun 28 07:25:48 PM PDT 24
Peak memory 215400 kb
Host smart-72a03d4b-c309-4acb-a194-2876605d3915
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405960234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2405960234
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2558968029
Short name T266
Test name
Test status
Simulation time 494154050 ps
CPU time 1.21 seconds
Started Jun 28 07:25:32 PM PDT 24
Finished Jun 28 07:25:37 PM PDT 24
Peak memory 191660 kb
Host smart-08fabd16-8a96-4259-bdb9-b66a72bb0847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558968029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2558968029
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2020052865
Short name T187
Test name
Test status
Simulation time 411091591 ps
CPU time 1.21 seconds
Started Jun 28 07:26:04 PM PDT 24
Finished Jun 28 07:26:25 PM PDT 24
Peak memory 196416 kb
Host smart-f59cc681-e8f1-40ac-9893-a21ff83e7598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020052865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2020052865
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3362837639
Short name T217
Test name
Test status
Simulation time 17766738764 ps
CPU time 7.15 seconds
Started Jun 28 07:26:04 PM PDT 24
Finished Jun 28 07:26:31 PM PDT 24
Peak memory 196744 kb
Host smart-e8e05cd1-4eb7-4c47-9042-90c130c801bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362837639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3362837639
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.22286750
Short name T212
Test name
Test status
Simulation time 540982698 ps
CPU time 0.78 seconds
Started Jun 28 07:26:10 PM PDT 24
Finished Jun 28 07:26:34 PM PDT 24
Peak memory 196432 kb
Host smart-befde98f-3650-45de-a7ea-1d0425b9b999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22286750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.22286750
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3491578853
Short name T265
Test name
Test status
Simulation time 16120616895 ps
CPU time 22.32 seconds
Started Jun 28 07:26:04 PM PDT 24
Finished Jun 28 07:26:47 PM PDT 24
Peak memory 196752 kb
Host smart-0f05ec89-99b1-4f0a-bf67-b2d1d57c2616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491578853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3491578853
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3805894191
Short name T219
Test name
Test status
Simulation time 432020934 ps
CPU time 1.31 seconds
Started Jun 28 07:26:05 PM PDT 24
Finished Jun 28 07:26:27 PM PDT 24
Peak memory 191656 kb
Host smart-63678b34-825f-4b89-b5fe-98d614c77fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805894191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3805894191
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2639160178
Short name T243
Test name
Test status
Simulation time 18729111748 ps
CPU time 25.46 seconds
Started Jun 28 07:26:09 PM PDT 24
Finished Jun 28 07:26:58 PM PDT 24
Peak memory 191640 kb
Host smart-8190bd0d-1805-4728-96c8-6884bfc35120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639160178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2639160178
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2984667516
Short name T208
Test name
Test status
Simulation time 585850624 ps
CPU time 1.37 seconds
Started Jun 28 07:26:10 PM PDT 24
Finished Jun 28 07:26:34 PM PDT 24
Peak memory 191588 kb
Host smart-5fdc7562-ad09-4cfc-89ee-a158bbe7152c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984667516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2984667516
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3516517635
Short name T252
Test name
Test status
Simulation time 17034675990 ps
CPU time 24.41 seconds
Started Jun 28 07:26:08 PM PDT 24
Finished Jun 28 07:26:55 PM PDT 24
Peak memory 196752 kb
Host smart-7848381f-c86b-42ef-825e-f325df795f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516517635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3516517635
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3092911973
Short name T202
Test name
Test status
Simulation time 498344208 ps
CPU time 0.78 seconds
Started Jun 28 07:26:10 PM PDT 24
Finished Jun 28 07:26:33 PM PDT 24
Peak memory 196504 kb
Host smart-9ce8b18b-9438-4188-8925-521bdc3f4060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092911973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3092911973
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3416620223
Short name T218
Test name
Test status
Simulation time 59908798554 ps
CPU time 8.99 seconds
Started Jun 28 07:26:11 PM PDT 24
Finished Jun 28 07:26:42 PM PDT 24
Peak memory 191732 kb
Host smart-2b2ea11d-5c9a-49e8-88db-e69fdd09cec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416620223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3416620223
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3726472280
Short name T230
Test name
Test status
Simulation time 637512786 ps
CPU time 0.66 seconds
Started Jun 28 07:26:07 PM PDT 24
Finished Jun 28 07:26:28 PM PDT 24
Peak memory 191672 kb
Host smart-49671e1b-b139-4217-a36a-eca1eca360e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726472280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3726472280
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3377709995
Short name T86
Test name
Test status
Simulation time 22838664269 ps
CPU time 30.45 seconds
Started Jun 28 07:26:05 PM PDT 24
Finished Jun 28 07:26:55 PM PDT 24
Peak memory 191732 kb
Host smart-2e7da3ce-bad1-40df-a25c-51c6d7dc22eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377709995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3377709995
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1459369439
Short name T268
Test name
Test status
Simulation time 498118799 ps
CPU time 1.37 seconds
Started Jun 28 07:26:08 PM PDT 24
Finished Jun 28 07:26:32 PM PDT 24
Peak memory 191676 kb
Host smart-12965d13-b54d-4a41-8654-d6f046188ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459369439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1459369439
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3699251460
Short name T85
Test name
Test status
Simulation time 342343196 ps
CPU time 0.85 seconds
Started Jun 28 07:26:06 PM PDT 24
Finished Jun 28 07:26:27 PM PDT 24
Peak memory 196548 kb
Host smart-3eb0c673-a66f-4dac-bdf1-05ecfba21873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699251460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3699251460
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2737578795
Short name T203
Test name
Test status
Simulation time 40287814605 ps
CPU time 10.64 seconds
Started Jun 28 07:26:05 PM PDT 24
Finished Jun 28 07:26:37 PM PDT 24
Peak memory 191732 kb
Host smart-08867ead-95a8-4ebe-a2fc-fb255f52d9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737578795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2737578795
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2898569726
Short name T10
Test name
Test status
Simulation time 521415625 ps
CPU time 1.18 seconds
Started Jun 28 07:26:05 PM PDT 24
Finished Jun 28 07:26:27 PM PDT 24
Peak memory 191672 kb
Host smart-1f8ca9de-000e-401d-a6dc-909e0023c2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898569726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2898569726
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1754332764
Short name T236
Test name
Test status
Simulation time 34011116660 ps
CPU time 52.47 seconds
Started Jun 28 07:26:10 PM PDT 24
Finished Jun 28 07:27:25 PM PDT 24
Peak memory 191644 kb
Host smart-5e5bdb6a-04f6-4c64-a198-c001df468e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754332764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1754332764
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3040338139
Short name T207
Test name
Test status
Simulation time 499485078 ps
CPU time 0.67 seconds
Started Jun 28 07:26:04 PM PDT 24
Finished Jun 28 07:26:25 PM PDT 24
Peak memory 196532 kb
Host smart-aac2fa9f-7353-4fac-9b45-b2e0ad035351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040338139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3040338139
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.331627590
Short name T246
Test name
Test status
Simulation time 26313928613 ps
CPU time 10.6 seconds
Started Jun 28 07:26:12 PM PDT 24
Finished Jun 28 07:26:45 PM PDT 24
Peak memory 191664 kb
Host smart-c62571a7-f05a-4a5c-8f59-b879684f7b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331627590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.331627590
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.899707022
Short name T226
Test name
Test status
Simulation time 462655240 ps
CPU time 0.73 seconds
Started Jun 28 07:26:10 PM PDT 24
Finished Jun 28 07:26:33 PM PDT 24
Peak memory 191796 kb
Host smart-de3e896c-ac51-4de4-8fcd-2390eed57b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899707022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.899707022
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1278865214
Short name T262
Test name
Test status
Simulation time 5368502565 ps
CPU time 7.81 seconds
Started Jun 28 07:26:24 PM PDT 24
Finished Jun 28 07:26:57 PM PDT 24
Peak memory 196724 kb
Host smart-7c79ea16-9fd3-4360-a8c3-cfafa3482c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278865214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1278865214
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2578715055
Short name T214
Test name
Test status
Simulation time 380089162 ps
CPU time 0.7 seconds
Started Jun 28 07:26:08 PM PDT 24
Finished Jun 28 07:26:31 PM PDT 24
Peak memory 191668 kb
Host smart-e0b0d7fb-10a9-4c4d-9b29-301c338b493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578715055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2578715055
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3991211163
Short name T269
Test name
Test status
Simulation time 7463849261 ps
CPU time 9.94 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:25:48 PM PDT 24
Peak memory 196740 kb
Host smart-f3e1e7bf-e478-4ffb-8967-328492649460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991211163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3991211163
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2390102949
Short name T18
Test name
Test status
Simulation time 7611439763 ps
CPU time 11.39 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:25:49 PM PDT 24
Peak memory 215836 kb
Host smart-b7252e93-7ae3-4f84-9927-914ff99a200b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390102949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2390102949
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.768465848
Short name T259
Test name
Test status
Simulation time 438641632 ps
CPU time 0.88 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:25:40 PM PDT 24
Peak memory 191636 kb
Host smart-216aefc6-b9a9-4925-9690-fd247a69d080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768465848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.768465848
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2916199068
Short name T83
Test name
Test status
Simulation time 26301635743 ps
CPU time 4.32 seconds
Started Jun 28 07:26:27 PM PDT 24
Finished Jun 28 07:26:56 PM PDT 24
Peak memory 191736 kb
Host smart-31bc2ca1-4d8d-4651-b479-e5f4756c83c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916199068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2916199068
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.113973908
Short name T87
Test name
Test status
Simulation time 516857276 ps
CPU time 0.95 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:26:50 PM PDT 24
Peak memory 191692 kb
Host smart-96766d80-6df3-4878-806c-14781764408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113973908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.113973908
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3245445260
Short name T221
Test name
Test status
Simulation time 20063868592 ps
CPU time 7.32 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:26:57 PM PDT 24
Peak memory 196752 kb
Host smart-6ad3b9c0-9a0f-48f0-9288-845480446bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245445260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3245445260
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2087475854
Short name T256
Test name
Test status
Simulation time 610855889 ps
CPU time 0.73 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:26:50 PM PDT 24
Peak memory 191676 kb
Host smart-3c842e71-27b5-46c7-bda4-f6c2cbe5dd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087475854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2087475854
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3402602647
Short name T5
Test name
Test status
Simulation time 10195431901 ps
CPU time 15.86 seconds
Started Jun 28 07:26:23 PM PDT 24
Finished Jun 28 07:27:04 PM PDT 24
Peak memory 191652 kb
Host smart-806b1d45-b212-4a00-955f-6131d08b7ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402602647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3402602647
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.4232698536
Short name T229
Test name
Test status
Simulation time 584576349 ps
CPU time 1.44 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:26:51 PM PDT 24
Peak memory 191668 kb
Host smart-a24466f7-7d6e-4029-9327-64743695edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232698536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.4232698536
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3070205110
Short name T213
Test name
Test status
Simulation time 40473694122 ps
CPU time 15.59 seconds
Started Jun 28 07:26:26 PM PDT 24
Finished Jun 28 07:27:07 PM PDT 24
Peak memory 191724 kb
Host smart-7aed0ce7-dd2a-47e1-8149-11ed421502b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070205110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3070205110
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3435849553
Short name T247
Test name
Test status
Simulation time 534246281 ps
CPU time 1.22 seconds
Started Jun 28 07:26:24 PM PDT 24
Finished Jun 28 07:26:51 PM PDT 24
Peak memory 191644 kb
Host smart-26abbf86-0cfa-4463-baac-fd5bd342b162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435849553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3435849553
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1944497771
Short name T199
Test name
Test status
Simulation time 43850455320 ps
CPU time 17 seconds
Started Jun 28 07:26:25 PM PDT 24
Finished Jun 28 07:27:07 PM PDT 24
Peak memory 191720 kb
Host smart-15f4c34e-d85b-4790-9050-409a80e35c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944497771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1944497771
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1393256614
Short name T215
Test name
Test status
Simulation time 516942770 ps
CPU time 1.42 seconds
Started Jun 28 07:26:23 PM PDT 24
Finished Jun 28 07:26:50 PM PDT 24
Peak memory 191668 kb
Host smart-730d44a0-78c8-4b1b-8583-5fbd8d62d415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393256614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1393256614
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3651804111
Short name T249
Test name
Test status
Simulation time 29948032542 ps
CPU time 12.01 seconds
Started Jun 28 07:26:27 PM PDT 24
Finished Jun 28 07:27:04 PM PDT 24
Peak memory 191728 kb
Host smart-d420fdc8-7b40-462c-ae03-74f2aabd41cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651804111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3651804111
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1431425291
Short name T206
Test name
Test status
Simulation time 430904226 ps
CPU time 1.17 seconds
Started Jun 28 07:26:27 PM PDT 24
Finished Jun 28 07:26:57 PM PDT 24
Peak memory 196516 kb
Host smart-29dc1047-e97b-45fa-a514-41759c0890a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431425291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1431425291
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.793844826
Short name T223
Test name
Test status
Simulation time 35851602517 ps
CPU time 51.96 seconds
Started Jun 28 07:26:26 PM PDT 24
Finished Jun 28 07:27:44 PM PDT 24
Peak memory 191732 kb
Host smart-87eb3177-7222-4adf-aa8e-f44bdccb3f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793844826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.793844826
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3179755073
Short name T264
Test name
Test status
Simulation time 384801693 ps
CPU time 0.81 seconds
Started Jun 28 07:26:27 PM PDT 24
Finished Jun 28 07:26:53 PM PDT 24
Peak memory 191672 kb
Host smart-f90694ea-500e-48ac-9084-21cbd9d6f7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179755073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3179755073
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.910144298
Short name T250
Test name
Test status
Simulation time 35161475305 ps
CPU time 12.41 seconds
Started Jun 28 07:26:38 PM PDT 24
Finished Jun 28 07:27:23 PM PDT 24
Peak memory 196740 kb
Host smart-d6834f3a-c4c0-4ac7-a121-b6e6d8025083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910144298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.910144298
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1485457291
Short name T233
Test name
Test status
Simulation time 465870974 ps
CPU time 0.87 seconds
Started Jun 28 07:26:38 PM PDT 24
Finished Jun 28 07:27:12 PM PDT 24
Peak memory 196484 kb
Host smart-2ca02736-bf6f-4edd-a2bc-d48e4e3a40e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485457291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1485457291
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.256593121
Short name T173
Test name
Test status
Simulation time 464116101 ps
CPU time 1.32 seconds
Started Jun 28 07:26:37 PM PDT 24
Finished Jun 28 07:27:12 PM PDT 24
Peak memory 196468 kb
Host smart-17c99c13-6fb8-4ee5-98bd-0c3d4f5fcf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256593121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.256593121
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2642853955
Short name T242
Test name
Test status
Simulation time 20659069282 ps
CPU time 6.69 seconds
Started Jun 28 07:26:40 PM PDT 24
Finished Jun 28 07:27:19 PM PDT 24
Peak memory 191728 kb
Host smart-6f25d31a-70a3-4a09-9bee-216de3ddf823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642853955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2642853955
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1286890686
Short name T267
Test name
Test status
Simulation time 428419169 ps
CPU time 0.84 seconds
Started Jun 28 07:26:38 PM PDT 24
Finished Jun 28 07:27:12 PM PDT 24
Peak memory 191664 kb
Host smart-b3ac3c32-5f35-424e-934a-f545eda35510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286890686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1286890686
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3408264931
Short name T280
Test name
Test status
Simulation time 40146230950 ps
CPU time 59.49 seconds
Started Jun 28 07:26:47 PM PDT 24
Finished Jun 28 07:28:22 PM PDT 24
Peak memory 191732 kb
Host smart-46c1aab9-001b-454d-97da-8b4c711301f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408264931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3408264931
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3403560563
Short name T263
Test name
Test status
Simulation time 386709340 ps
CPU time 1.15 seconds
Started Jun 28 07:26:38 PM PDT 24
Finished Jun 28 07:27:12 PM PDT 24
Peak memory 196500 kb
Host smart-7c396932-ac11-4b1a-a914-30367ec634f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403560563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3403560563
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1263395704
Short name T232
Test name
Test status
Simulation time 27654347540 ps
CPU time 9.2 seconds
Started Jun 28 07:25:32 PM PDT 24
Finished Jun 28 07:25:45 PM PDT 24
Peak memory 191644 kb
Host smart-5d42fd07-821d-424d-8a18-135453cf69be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263395704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1263395704
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3202181755
Short name T15
Test name
Test status
Simulation time 8078423142 ps
CPU time 13.02 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:25:52 PM PDT 24
Peak memory 215824 kb
Host smart-95406226-ed62-42ef-a1da-b2d931d2e351
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202181755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3202181755
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3658965711
Short name T224
Test name
Test status
Simulation time 668087980 ps
CPU time 0.66 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:25:38 PM PDT 24
Peak memory 191660 kb
Host smart-d9366e75-117e-48a2-bb4e-4b0136883312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658965711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3658965711
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2747086739
Short name T222
Test name
Test status
Simulation time 34620694132 ps
CPU time 5.37 seconds
Started Jun 28 07:26:47 PM PDT 24
Finished Jun 28 07:27:28 PM PDT 24
Peak memory 191472 kb
Host smart-9243abc1-fe61-42a4-a6d3-fb0e69268dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747086739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2747086739
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1790956835
Short name T253
Test name
Test status
Simulation time 528426464 ps
CPU time 0.75 seconds
Started Jun 28 07:26:47 PM PDT 24
Finished Jun 28 07:27:24 PM PDT 24
Peak memory 191676 kb
Host smart-73c66537-4432-4472-ab1c-0b7b799229b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790956835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1790956835
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1872390989
Short name T240
Test name
Test status
Simulation time 36406292478 ps
CPU time 13.83 seconds
Started Jun 28 07:26:45 PM PDT 24
Finished Jun 28 07:27:33 PM PDT 24
Peak memory 191732 kb
Host smart-30c9893a-0b58-4376-ac40-1b8083ccddaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872390989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1872390989
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.392667227
Short name T277
Test name
Test status
Simulation time 430664075 ps
CPU time 1.2 seconds
Started Jun 28 07:26:38 PM PDT 24
Finished Jun 28 07:27:12 PM PDT 24
Peak memory 191652 kb
Host smart-d9247512-4317-4af5-9a4b-0bcccc175a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392667227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.392667227
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1689094209
Short name T210
Test name
Test status
Simulation time 16913381653 ps
CPU time 23.6 seconds
Started Jun 28 07:26:39 PM PDT 24
Finished Jun 28 07:27:36 PM PDT 24
Peak memory 191728 kb
Host smart-94896823-b464-4565-9488-dcdd6cee1e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689094209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1689094209
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2556711795
Short name T204
Test name
Test status
Simulation time 431941086 ps
CPU time 0.84 seconds
Started Jun 28 07:26:39 PM PDT 24
Finished Jun 28 07:27:12 PM PDT 24
Peak memory 196484 kb
Host smart-d80b136a-5240-4dbb-af94-953f69c75a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556711795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2556711795
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2886581899
Short name T254
Test name
Test status
Simulation time 19023249480 ps
CPU time 14.01 seconds
Started Jun 28 07:26:38 PM PDT 24
Finished Jun 28 07:27:25 PM PDT 24
Peak memory 191728 kb
Host smart-429e925b-7f0c-4a8d-85b8-c3dfc4575786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886581899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2886581899
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3350044256
Short name T20
Test name
Test status
Simulation time 417118881 ps
CPU time 0.69 seconds
Started Jun 28 07:26:38 PM PDT 24
Finished Jun 28 07:27:12 PM PDT 24
Peak memory 196500 kb
Host smart-96559629-74ad-45e0-8149-920635b4451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350044256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3350044256
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3383540786
Short name T82
Test name
Test status
Simulation time 30584853858 ps
CPU time 47.08 seconds
Started Jun 28 07:26:47 PM PDT 24
Finished Jun 28 07:28:09 PM PDT 24
Peak memory 196744 kb
Host smart-ca86f9a3-1675-43f0-a5dc-1eb9a739370c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383540786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3383540786
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1704043637
Short name T234
Test name
Test status
Simulation time 560094960 ps
CPU time 1.28 seconds
Started Jun 28 07:26:47 PM PDT 24
Finished Jun 28 07:27:24 PM PDT 24
Peak memory 191224 kb
Host smart-51ffc6ad-b802-41aa-8e12-c045e2ef75ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704043637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1704043637
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3194363342
Short name T225
Test name
Test status
Simulation time 36725433528 ps
CPU time 7.22 seconds
Started Jun 28 07:26:47 PM PDT 24
Finished Jun 28 07:27:30 PM PDT 24
Peak memory 191608 kb
Host smart-406ac5e4-9b1f-47e9-83b6-06bcaa679452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194363342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3194363342
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1640896893
Short name T261
Test name
Test status
Simulation time 457113070 ps
CPU time 1.3 seconds
Started Jun 28 07:26:47 PM PDT 24
Finished Jun 28 07:27:24 PM PDT 24
Peak memory 196424 kb
Host smart-9d254a65-e745-413f-bba5-f0fba69751cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640896893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1640896893
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1554165058
Short name T12
Test name
Test status
Simulation time 50615140796 ps
CPU time 16.29 seconds
Started Jun 28 07:26:38 PM PDT 24
Finished Jun 28 07:27:27 PM PDT 24
Peak memory 196744 kb
Host smart-5d82ff87-eee1-4eb6-9923-ddda9d111270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554165058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1554165058
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2753174609
Short name T216
Test name
Test status
Simulation time 588464564 ps
CPU time 0.7 seconds
Started Jun 28 07:26:39 PM PDT 24
Finished Jun 28 07:27:12 PM PDT 24
Peak memory 196520 kb
Host smart-690e4625-230f-4e40-9a6c-04c47fbbbd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753174609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2753174609
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3682634833
Short name T235
Test name
Test status
Simulation time 22921972212 ps
CPU time 4.77 seconds
Started Jun 28 07:26:39 PM PDT 24
Finished Jun 28 07:27:16 PM PDT 24
Peak memory 191640 kb
Host smart-08aeba4c-7c35-4ca4-bc39-e77b55918d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682634833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3682634833
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1926296949
Short name T27
Test name
Test status
Simulation time 427419122 ps
CPU time 0.74 seconds
Started Jun 28 07:26:37 PM PDT 24
Finished Jun 28 07:27:09 PM PDT 24
Peak memory 196512 kb
Host smart-bced6a7a-b030-4e8d-871d-dadbf8a568b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926296949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1926296949
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_jump.793758944
Short name T164
Test name
Test status
Simulation time 495035876 ps
CPU time 0.92 seconds
Started Jun 28 07:26:51 PM PDT 24
Finished Jun 28 07:27:27 PM PDT 24
Peak memory 196528 kb
Host smart-592ab3f0-5730-49c6-aa08-142c8ca523af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793758944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.793758944
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.4048954163
Short name T239
Test name
Test status
Simulation time 13626364336 ps
CPU time 2.56 seconds
Started Jun 28 07:26:50 PM PDT 24
Finished Jun 28 07:27:28 PM PDT 24
Peak memory 191732 kb
Host smart-2f28a56e-64d9-44c1-893e-e10c1c9a2404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048954163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4048954163
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.520164700
Short name T258
Test name
Test status
Simulation time 539568927 ps
CPU time 0.79 seconds
Started Jun 28 07:26:52 PM PDT 24
Finished Jun 28 07:27:30 PM PDT 24
Peak memory 191664 kb
Host smart-5042f0fb-37d6-48c0-a568-d719deb4e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520164700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.520164700
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1267102459
Short name T81
Test name
Test status
Simulation time 52536851218 ps
CPU time 80.3 seconds
Started Jun 28 07:26:49 PM PDT 24
Finished Jun 28 07:28:44 PM PDT 24
Peak memory 191664 kb
Host smart-0c830fb1-98de-44a0-a73a-5e4544077d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267102459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1267102459
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1848963297
Short name T274
Test name
Test status
Simulation time 430677228 ps
CPU time 1.19 seconds
Started Jun 28 07:26:52 PM PDT 24
Finished Jun 28 07:27:29 PM PDT 24
Peak memory 191676 kb
Host smart-2a0f2cfa-41eb-4f0e-adb6-9cb259457bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848963297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1848963297
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.4156324425
Short name T270
Test name
Test status
Simulation time 19145671289 ps
CPU time 29.75 seconds
Started Jun 28 07:25:38 PM PDT 24
Finished Jun 28 07:26:14 PM PDT 24
Peak memory 196724 kb
Host smart-7fb07a7f-2292-4e11-a02c-05059dc8c853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156324425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4156324425
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3322647147
Short name T205
Test name
Test status
Simulation time 571211386 ps
CPU time 1.06 seconds
Started Jun 28 07:25:37 PM PDT 24
Finished Jun 28 07:25:45 PM PDT 24
Peak memory 191656 kb
Host smart-d7e9e95b-186d-4ce0-ac30-300d9b6a78a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322647147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3322647147
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1558172110
Short name T271
Test name
Test status
Simulation time 4396304643 ps
CPU time 3.54 seconds
Started Jun 28 07:25:35 PM PDT 24
Finished Jun 28 07:25:45 PM PDT 24
Peak memory 191732 kb
Host smart-8680dfef-0941-45ff-829e-6f6c29110a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558172110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1558172110
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2068986195
Short name T22
Test name
Test status
Simulation time 575625648 ps
CPU time 1.2 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:25:39 PM PDT 24
Peak memory 191668 kb
Host smart-1b1e36f0-9542-434d-b291-bb64bedef1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068986195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2068986195
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2622154869
Short name T281
Test name
Test status
Simulation time 21126487725 ps
CPU time 14.92 seconds
Started Jun 28 07:25:53 PM PDT 24
Finished Jun 28 07:26:23 PM PDT 24
Peak memory 196752 kb
Host smart-4922cff1-7f97-42bf-b93b-8d2ee2377685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622154869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2622154869
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1842030324
Short name T25
Test name
Test status
Simulation time 519469669 ps
CPU time 0.82 seconds
Started Jun 28 07:25:49 PM PDT 24
Finished Jun 28 07:26:03 PM PDT 24
Peak memory 191664 kb
Host smart-76581083-0f5e-44e3-b9fa-40cd9c321782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842030324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1842030324
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1300043861
Short name T171
Test name
Test status
Simulation time 432204067 ps
CPU time 0.74 seconds
Started Jun 28 07:25:50 PM PDT 24
Finished Jun 28 07:26:04 PM PDT 24
Peak memory 196468 kb
Host smart-c2d80896-7d97-49fc-a694-cc170e3b4dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300043861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1300043861
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1920639544
Short name T255
Test name
Test status
Simulation time 39877347112 ps
CPU time 8.87 seconds
Started Jun 28 07:25:51 PM PDT 24
Finished Jun 28 07:26:15 PM PDT 24
Peak memory 191736 kb
Host smart-beb25c23-c566-425a-8370-ae121b269819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920639544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1920639544
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3593581115
Short name T201
Test name
Test status
Simulation time 475341348 ps
CPU time 1.22 seconds
Started Jun 28 07:25:53 PM PDT 24
Finished Jun 28 07:26:10 PM PDT 24
Peak memory 191580 kb
Host smart-cfaa03c8-a31b-49fb-99c7-5dba6daad2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593581115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3593581115
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2000738576
Short name T231
Test name
Test status
Simulation time 46902278204 ps
CPU time 10.4 seconds
Started Jun 28 07:25:50 PM PDT 24
Finished Jun 28 07:26:13 PM PDT 24
Peak memory 191660 kb
Host smart-1396c0b9-dce0-4899-b029-1cb5e87ab205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000738576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2000738576
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1298052038
Short name T200
Test name
Test status
Simulation time 475689895 ps
CPU time 0.72 seconds
Started Jun 28 07:25:49 PM PDT 24
Finished Jun 28 07:26:03 PM PDT 24
Peak memory 196520 kb
Host smart-a79a7760-9e01-49e8-a05e-7a1de0012849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298052038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1298052038
Directory /workspace/9.aon_timer_smoke/latest
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