Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.11 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 5 168 97.11


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 29785 1 T1 12 T3 149 T4 203
bark[1] 874 1 T13 162 T46 14 T95 220
bark[2] 679 1 T77 14 T100 21 T24 21
bark[3] 119 1 T146 21 T80 35 T165 21
bark[4] 555 1 T5 7 T13 21 T28 258
bark[5] 673 1 T3 21 T28 21 T38 52
bark[6] 578 1 T13 21 T114 14 T38 253
bark[7] 544 1 T3 30 T28 31 T41 128
bark[8] 800 1 T6 51 T123 14 T41 45
bark[9] 587 1 T6 31 T13 141 T37 79
bark[10] 636 1 T6 21 T11 5 T27 14
bark[11] 514 1 T12 14 T179 42 T37 125
bark[12] 301 1 T3 30 T13 21 T100 21
bark[13] 923 1 T5 313 T36 52 T146 21
bark[14] 676 1 T37 5 T89 294 T100 47
bark[15] 603 1 T38 42 T39 310 T134 14
bark[16] 572 1 T8 21 T28 21 T40 21
bark[17] 511 1 T3 30 T4 21 T7 42
bark[18] 643 1 T37 35 T24 26 T117 21
bark[19] 415 1 T4 21 T5 45 T97 21
bark[20] 365 1 T171 30 T96 21 T82 90
bark[21] 793 1 T3 21 T8 44 T189 14
bark[22] 297 1 T100 5 T99 21 T127 30
bark[23] 1269 1 T2 14 T3 21 T4 49
bark[24] 201 1 T13 73 T179 30 T170 14
bark[25] 1244 1 T5 31 T36 197 T143 21
bark[26] 443 1 T36 72 T80 21 T96 30
bark[27] 511 1 T5 21 T11 21 T166 14
bark[28] 98 1 T7 21 T26 30 T83 21
bark[29] 478 1 T3 30 T5 71 T6 21
bark[30] 450 1 T11 21 T186 21 T117 249
bark[31] 716 1 T11 349 T28 21 T102 47
bark_0 4561 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 30130 1 T1 11 T3 127 T4 202
bite[1] 363 1 T95 26 T107 18 T171 51
bite[2] 619 1 T5 44 T8 44 T102 30
bite[3] 455 1 T3 21 T179 30 T95 219
bite[4] 455 1 T11 21 T95 48 T100 286
bite[5] 470 1 T5 312 T38 51 T96 21
bite[6] 299 1 T27 13 T28 31 T39 6
bite[7] 613 1 T3 30 T5 161 T41 127
bite[8] 701 1 T13 161 T39 21 T24 21
bite[9] 568 1 T6 31 T37 78 T38 21
bite[10] 253 1 T4 21 T123 13 T100 21
bite[11] 553 1 T5 30 T100 223 T177 102
bite[12] 770 1 T3 21 T13 72 T36 71
bite[13] 230 1 T4 49 T7 42 T114 13
bite[14] 523 1 T13 21 T38 252 T102 21
bite[15] 363 1 T3 30 T6 21 T179 21
bite[16] 419 1 T13 21 T28 21 T102 21
bite[17] 55 1 T121 21 T155 21 T112 13
bite[18] 990 1 T3 21 T12 13 T80 21
bite[19] 412 1 T179 21 T146 21 T40 21
bite[20] 595 1 T3 30 T11 348 T80 21
bite[21] 378 1 T5 6 T6 21 T49 13
bite[22] 621 1 T3 21 T37 21 T134 13
bite[23] 862 1 T11 21 T37 27 T182 42
bite[24] 861 1 T46 13 T38 42 T39 309
bite[25] 436 1 T3 30 T8 21 T77 13
bite[26] 1419 1 T4 21 T7 21 T13 21
bite[27] 375 1 T2 13 T11 4 T28 21
bite[28] 798 1 T6 51 T9 13 T80 21
bite[29] 160 1 T5 70 T160 13 T24 35
bite[30] 1257 1 T5 21 T28 278 T36 196
bite[31] 375 1 T13 140 T37 4 T38 21
bite_0 5036 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 52414 1 T1 19 T2 21 T3 339


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1011 1 T13 40 T28 143 T50 9
prescale[1] 1149 1 T38 19 T39 19 T41 39
prescale[2] 814 1 T28 103 T146 49 T102 19
prescale[3] 615 1 T28 99 T146 19 T38 46
prescale[4] 1003 1 T5 61 T7 19 T11 2
prescale[5] 521 1 T5 23 T6 23 T43 9
prescale[6] 989 1 T5 55 T13 217 T38 19
prescale[7] 1048 1 T5 20 T41 19 T95 171
prescale[8] 770 1 T5 108 T11 2 T13 2
prescale[9] 962 1 T5 85 T13 74 T28 33
prescale[10] 1191 1 T3 37 T4 46 T28 2
prescale[11] 993 1 T28 56 T47 9 T146 19
prescale[12] 1226 1 T10 9 T28 19 T179 56
prescale[13] 779 1 T3 30 T39 23 T41 79
prescale[14] 599 1 T4 28 T5 2 T6 23
prescale[15] 1036 1 T5 174 T13 132 T39 84
prescale[16] 638 1 T7 19 T13 89 T36 109
prescale[17] 780 1 T13 20 T28 83 T45 9
prescale[18] 899 1 T5 86 T7 19 T13 61
prescale[19] 767 1 T5 2 T179 19 T146 19
prescale[20] 1001 1 T5 40 T13 28 T36 19
prescale[21] 728 1 T3 44 T5 21 T6 19
prescale[22] 759 1 T6 23 T11 9 T28 79
prescale[23] 652 1 T7 23 T28 19 T37 46
prescale[24] 765 1 T6 55 T11 59 T13 20
prescale[25] 1168 1 T7 19 T8 65 T11 76
prescale[26] 468 1 T11 2 T39 25 T41 19
prescale[27] 894 1 T7 9 T11 48 T13 2
prescale[28] 861 1 T1 9 T11 85 T39 77
prescale[29] 672 1 T4 109 T36 9 T48 9
prescale[30] 390 1 T37 4 T171 46 T182 33
prescale[31] 685 1 T5 21 T11 42 T13 2
prescale_0 25581 1 T1 10 T2 21 T3 228


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 39473 1 T1 9 T2 21 T3 186
auto[1] 12941 1 T1 10 T3 153 T4 50


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 52414 1 T1 19 T2 21 T3 339


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 31667 1 T1 14 T2 1 T3 115
wkup[1] 366 1 T5 21 T6 31 T41 39
wkup[2] 367 1 T38 21 T39 31 T95 26
wkup[3] 427 1 T3 21 T11 6 T28 65
wkup[4] 284 1 T36 21 T41 21 T102 21
wkup[5] 335 1 T4 21 T27 15 T28 39
wkup[6] 317 1 T4 30 T28 42 T114 15
wkup[7] 300 1 T49 15 T95 26 T89 8
wkup[8] 251 1 T5 8 T28 26 T123 15
wkup[9] 278 1 T28 61 T95 26 T100 21
wkup[10] 320 1 T3 30 T13 21 T38 60
wkup[11] 324 1 T13 21 T28 21 T38 21
wkup[12] 175 1 T36 26 T40 15 T188 15
wkup[13] 304 1 T8 30 T36 21 T82 21
wkup[14] 439 1 T12 15 T13 29 T38 21
wkup[15] 266 1 T6 21 T13 84 T80 21
wkup[16] 266 1 T39 42 T95 26 T100 30
wkup[17] 285 1 T11 21 T28 21 T179 21
wkup[18] 186 1 T80 21 T82 30 T91 21
wkup[19] 197 1 T7 21 T11 21 T160 15
wkup[20] 325 1 T4 21 T5 30 T100 21
wkup[21] 180 1 T38 21 T39 21 T102 21
wkup[22] 136 1 T77 15 T39 26 T26 53
wkup[23] 212 1 T5 21 T36 39 T38 26
wkup[24] 239 1 T11 21 T13 26 T41 42
wkup[25] 426 1 T5 26 T6 21 T28 47
wkup[26] 200 1 T2 15 T3 30 T38 42
wkup[27] 173 1 T3 21 T90 21 T92 21
wkup[28] 191 1 T4 21 T46 15 T37 21
wkup[29] 259 1 T5 21 T11 21 T37 21
wkup[30] 194 1 T5 26 T13 51 T177 21
wkup[31] 255 1 T6 30 T37 14 T89 21
wkup[32] 189 1 T4 21 T100 81 T82 21
wkup[33] 217 1 T13 21 T28 21 T37 21
wkup[34] 183 1 T5 21 T8 20 T134 15
wkup[35] 196 1 T5 15 T39 47 T41 21
wkup[36] 186 1 T11 26 T13 35 T131 21
wkup[37] 260 1 T5 26 T36 21 T24 26
wkup[38] 229 1 T3 30 T5 21 T13 21
wkup[39] 406 1 T179 30 T36 21 T37 21
wkup[40] 275 1 T13 52 T95 26 T99 21
wkup[41] 274 1 T3 45 T7 21 T38 47
wkup[42] 260 1 T28 21 T39 21 T95 21
wkup[43] 268 1 T5 35 T38 21 T41 21
wkup[44] 125 1 T5 21 T28 21 T41 21
wkup[45] 209 1 T9 15 T13 21 T38 21
wkup[46] 472 1 T8 44 T13 8 T36 51
wkup[47] 267 1 T13 21 T38 21 T39 8
wkup[48] 323 1 T5 21 T13 42 T38 21
wkup[49] 302 1 T5 21 T11 21 T95 15
wkup[50] 216 1 T7 21 T8 21 T13 15
wkup[51] 331 1 T4 21 T36 26 T40 21
wkup[52] 290 1 T3 21 T13 21 T38 30
wkup[53] 319 1 T5 8 T41 21 T135 15
wkup[54] 319 1 T28 21 T37 21 T38 21
wkup[55] 178 1 T5 21 T39 26 T82 21
wkup[56] 341 1 T11 21 T179 21 T36 6
wkup[57] 413 1 T7 21 T13 35 T36 21
wkup[58] 457 1 T5 21 T28 21 T146 21
wkup[59] 214 1 T166 15 T39 21 T100 42
wkup[60] 384 1 T5 21 T37 30 T39 30
wkup[61] 203 1 T3 21 T6 21 T40 6
wkup[62] 187 1 T7 21 T24 31 T83 21
wkup[63] 208 1 T13 35 T38 30 T41 21
wkup_0 3569 1 T1 5 T2 5 T3 5

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