Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.21 99.33 93.67 100.00 98.40 99.51 50.34


Total test records in report: 423
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T29 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4089087332 Jun 29 05:17:07 PM PDT 24 Jun 29 05:17:10 PM PDT 24 1011997713 ps
T288 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.206628827 Jun 29 05:17:36 PM PDT 24 Jun 29 05:17:37 PM PDT 24 458024153 ps
T34 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3155919320 Jun 29 05:17:17 PM PDT 24 Jun 29 05:17:18 PM PDT 24 358360695 ps
T289 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2541861305 Jun 29 05:17:49 PM PDT 24 Jun 29 05:17:51 PM PDT 24 476075018 ps
T30 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3021922629 Jun 29 05:17:37 PM PDT 24 Jun 29 05:17:40 PM PDT 24 464507112 ps
T290 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3781825898 Jun 29 05:17:41 PM PDT 24 Jun 29 05:17:42 PM PDT 24 306773615 ps
T291 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2086077529 Jun 29 05:17:23 PM PDT 24 Jun 29 05:17:25 PM PDT 24 354229666 ps
T35 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1445511263 Jun 29 05:17:37 PM PDT 24 Jun 29 05:17:39 PM PDT 24 424449694 ps
T31 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3869815782 Jun 29 05:17:38 PM PDT 24 Jun 29 05:17:53 PM PDT 24 8528576322 ps
T292 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4249452443 Jun 29 05:17:39 PM PDT 24 Jun 29 05:17:43 PM PDT 24 584519473 ps
T88 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2527938981 Jun 29 05:17:35 PM PDT 24 Jun 29 05:17:36 PM PDT 24 310240259 ps
T293 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3029627585 Jun 29 05:17:52 PM PDT 24 Jun 29 05:17:53 PM PDT 24 468992608 ps
T202 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1193618835 Jun 29 05:17:11 PM PDT 24 Jun 29 05:17:17 PM PDT 24 7204975818 ps
T32 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2179642873 Jun 29 05:17:26 PM PDT 24 Jun 29 05:17:34 PM PDT 24 8075378342 ps
T294 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2165627734 Jun 29 05:17:48 PM PDT 24 Jun 29 05:17:50 PM PDT 24 426081001 ps
T295 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2157729447 Jun 29 05:17:18 PM PDT 24 Jun 29 05:17:19 PM PDT 24 426069325 ps
T296 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1365132120 Jun 29 05:17:07 PM PDT 24 Jun 29 05:17:09 PM PDT 24 409750499 ps
T33 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1980779169 Jun 29 05:17:38 PM PDT 24 Jun 29 05:17:42 PM PDT 24 8683655269 ps
T297 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.788024172 Jun 29 05:17:36 PM PDT 24 Jun 29 05:17:38 PM PDT 24 409434694 ps
T298 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.4223578407 Jun 29 05:17:49 PM PDT 24 Jun 29 05:17:51 PM PDT 24 381673933 ps
T299 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2249880239 Jun 29 05:17:51 PM PDT 24 Jun 29 05:17:52 PM PDT 24 287224826 ps
T199 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2993269705 Jun 29 05:17:08 PM PDT 24 Jun 29 05:17:10 PM PDT 24 4805449707 ps
T300 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3348194505 Jun 29 05:17:38 PM PDT 24 Jun 29 05:17:40 PM PDT 24 337293520 ps
T301 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1206364837 Jun 29 05:17:48 PM PDT 24 Jun 29 05:17:49 PM PDT 24 336875536 ps
T302 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3127818210 Jun 29 05:17:24 PM PDT 24 Jun 29 05:17:26 PM PDT 24 366744126 ps
T303 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1909117278 Jun 29 05:17:39 PM PDT 24 Jun 29 05:17:41 PM PDT 24 679639387 ps
T67 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2369328954 Jun 29 05:17:40 PM PDT 24 Jun 29 05:17:42 PM PDT 24 436732634 ps
T68 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4256503837 Jun 29 05:17:38 PM PDT 24 Jun 29 05:17:41 PM PDT 24 3180154649 ps
T304 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1413515592 Jun 29 05:17:08 PM PDT 24 Jun 29 05:17:11 PM PDT 24 400247903 ps
T305 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.751858290 Jun 29 05:17:48 PM PDT 24 Jun 29 05:17:49 PM PDT 24 283805913 ps
T306 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2804444101 Jun 29 05:17:36 PM PDT 24 Jun 29 05:17:39 PM PDT 24 865457561 ps
T307 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2195436440 Jun 29 05:17:23 PM PDT 24 Jun 29 05:17:24 PM PDT 24 585122140 ps
T308 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.991110582 Jun 29 05:17:07 PM PDT 24 Jun 29 05:17:09 PM PDT 24 611513868 ps
T309 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1201694035 Jun 29 05:17:11 PM PDT 24 Jun 29 05:17:12 PM PDT 24 402413094 ps
T310 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1380048990 Jun 29 05:17:40 PM PDT 24 Jun 29 05:17:41 PM PDT 24 348340948 ps
T311 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1486417215 Jun 29 05:17:40 PM PDT 24 Jun 29 05:17:41 PM PDT 24 401714573 ps
T200 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3780478505 Jun 29 05:17:25 PM PDT 24 Jun 29 05:17:38 PM PDT 24 8207806653 ps
T69 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2195736536 Jun 29 05:17:45 PM PDT 24 Jun 29 05:17:49 PM PDT 24 2570200547 ps
T312 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1443930548 Jun 29 05:17:36 PM PDT 24 Jun 29 05:17:38 PM PDT 24 308124452 ps
T313 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1318937517 Jun 29 05:17:42 PM PDT 24 Jun 29 05:17:44 PM PDT 24 517812491 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3570547961 Jun 29 05:17:09 PM PDT 24 Jun 29 05:17:11 PM PDT 24 332737780 ps
T314 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2940836618 Jun 29 05:17:09 PM PDT 24 Jun 29 05:17:11 PM PDT 24 475554213 ps
T315 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2287514182 Jun 29 05:17:23 PM PDT 24 Jun 29 05:17:24 PM PDT 24 434176932 ps
T316 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1668305500 Jun 29 05:17:49 PM PDT 24 Jun 29 05:17:51 PM PDT 24 422481511 ps
T51 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1081239892 Jun 29 05:17:26 PM PDT 24 Jun 29 05:17:27 PM PDT 24 373660758 ps
T317 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2655948314 Jun 29 05:17:18 PM PDT 24 Jun 29 05:17:20 PM PDT 24 4404715947 ps
T318 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4076153397 Jun 29 05:17:36 PM PDT 24 Jun 29 05:17:38 PM PDT 24 566217240 ps
T71 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1047253115 Jun 29 05:17:43 PM PDT 24 Jun 29 05:17:46 PM PDT 24 2029113914 ps
T72 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3331325277 Jun 29 05:17:23 PM PDT 24 Jun 29 05:17:27 PM PDT 24 1699057717 ps
T319 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2237103251 Jun 29 05:17:24 PM PDT 24 Jun 29 05:17:26 PM PDT 24 644968642 ps
T320 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1932304577 Jun 29 05:17:48 PM PDT 24 Jun 29 05:17:50 PM PDT 24 492056741 ps
T321 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1481327864 Jun 29 05:17:50 PM PDT 24 Jun 29 05:17:52 PM PDT 24 297013754 ps
T52 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3840407921 Jun 29 05:17:07 PM PDT 24 Jun 29 05:17:09 PM PDT 24 1060070274 ps
T322 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2697469721 Jun 29 05:17:48 PM PDT 24 Jun 29 05:17:51 PM PDT 24 402810140 ps
T323 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2358540439 Jun 29 05:17:38 PM PDT 24 Jun 29 05:17:46 PM PDT 24 4431328279 ps
T324 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2990959800 Jun 29 05:17:41 PM PDT 24 Jun 29 05:17:43 PM PDT 24 338022625 ps
T73 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1863225342 Jun 29 05:17:37 PM PDT 24 Jun 29 05:17:41 PM PDT 24 2501789532 ps
T74 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1712840165 Jun 29 05:17:47 PM PDT 24 Jun 29 05:17:49 PM PDT 24 489519709 ps
T75 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3299509661 Jun 29 05:17:35 PM PDT 24 Jun 29 05:17:38 PM PDT 24 1085777919 ps
T53 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2437070021 Jun 29 05:17:17 PM PDT 24 Jun 29 05:17:18 PM PDT 24 440949970 ps
T325 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4079440548 Jun 29 05:17:11 PM PDT 24 Jun 29 05:17:12 PM PDT 24 473890685 ps
T326 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3908300563 Jun 29 05:17:41 PM PDT 24 Jun 29 05:17:47 PM PDT 24 4311558368 ps
T327 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3923378210 Jun 29 05:17:43 PM PDT 24 Jun 29 05:17:52 PM PDT 24 4360575325 ps
T328 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.4051961969 Jun 29 05:17:50 PM PDT 24 Jun 29 05:17:52 PM PDT 24 300110302 ps
T329 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2625541178 Jun 29 05:17:26 PM PDT 24 Jun 29 05:17:28 PM PDT 24 432177622 ps
T330 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.921872534 Jun 29 05:17:48 PM PDT 24 Jun 29 05:17:49 PM PDT 24 315433478 ps
T331 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2459865314 Jun 29 05:17:08 PM PDT 24 Jun 29 05:17:09 PM PDT 24 487119413 ps
T332 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3042652096 Jun 29 05:17:52 PM PDT 24 Jun 29 05:17:53 PM PDT 24 504298491 ps
T333 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.388127727 Jun 29 05:17:25 PM PDT 24 Jun 29 05:17:27 PM PDT 24 578528189 ps
T334 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.912238988 Jun 29 05:17:08 PM PDT 24 Jun 29 05:17:10 PM PDT 24 301315682 ps
T335 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1838815115 Jun 29 05:17:41 PM PDT 24 Jun 29 05:17:45 PM PDT 24 2109366562 ps
T336 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.694728627 Jun 29 05:17:37 PM PDT 24 Jun 29 05:17:41 PM PDT 24 1228774585 ps
T337 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3060268580 Jun 29 05:17:18 PM PDT 24 Jun 29 05:17:19 PM PDT 24 433593191 ps
T54 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1489279310 Jun 29 05:17:10 PM PDT 24 Jun 29 05:17:12 PM PDT 24 492050569 ps
T338 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1070611357 Jun 29 05:17:16 PM PDT 24 Jun 29 05:17:17 PM PDT 24 898018066 ps
T339 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.301312036 Jun 29 05:17:06 PM PDT 24 Jun 29 05:17:21 PM PDT 24 9035581943 ps
T340 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1894401982 Jun 29 05:17:49 PM PDT 24 Jun 29 05:17:51 PM PDT 24 388041654 ps
T341 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.338199360 Jun 29 05:17:25 PM PDT 24 Jun 29 05:17:30 PM PDT 24 8122951368 ps
T55 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3805658936 Jun 29 05:17:40 PM PDT 24 Jun 29 05:17:42 PM PDT 24 427345368 ps
T342 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1897314462 Jun 29 05:17:08 PM PDT 24 Jun 29 05:17:10 PM PDT 24 425068550 ps
T343 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.137446461 Jun 29 05:17:35 PM PDT 24 Jun 29 05:17:38 PM PDT 24 566368700 ps
T344 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1883467275 Jun 29 05:17:08 PM PDT 24 Jun 29 05:17:10 PM PDT 24 364843478 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3118046268 Jun 29 05:17:07 PM PDT 24 Jun 29 05:17:09 PM PDT 24 651167173 ps
T345 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3595777336 Jun 29 05:17:26 PM PDT 24 Jun 29 05:17:31 PM PDT 24 2787662967 ps
T346 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.720826874 Jun 29 05:17:40 PM PDT 24 Jun 29 05:17:42 PM PDT 24 4547004042 ps
T347 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3844098159 Jun 29 05:17:18 PM PDT 24 Jun 29 05:17:20 PM PDT 24 1315675333 ps
T57 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2181474257 Jun 29 05:17:10 PM PDT 24 Jun 29 05:17:12 PM PDT 24 617924919 ps
T348 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1176257179 Jun 29 05:17:25 PM PDT 24 Jun 29 05:17:30 PM PDT 24 8779437547 ps
T201 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.70500499 Jun 29 05:17:26 PM PDT 24 Jun 29 05:17:38 PM PDT 24 8362358338 ps
T349 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3107356507 Jun 29 05:17:19 PM PDT 24 Jun 29 05:17:20 PM PDT 24 474876178 ps
T350 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3505184906 Jun 29 05:17:48 PM PDT 24 Jun 29 05:17:50 PM PDT 24 360720296 ps
T351 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2836185511 Jun 29 05:17:26 PM PDT 24 Jun 29 05:17:27 PM PDT 24 368628455 ps
T352 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.889094364 Jun 29 05:17:16 PM PDT 24 Jun 29 05:17:23 PM PDT 24 8354197011 ps
T353 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3635976063 Jun 29 05:17:25 PM PDT 24 Jun 29 05:17:29 PM PDT 24 4238820156 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4010785249 Jun 29 05:17:23 PM PDT 24 Jun 29 05:17:24 PM PDT 24 345249948 ps
T58 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3494334439 Jun 29 05:17:48 PM PDT 24 Jun 29 05:17:49 PM PDT 24 500766330 ps
T355 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3085995664 Jun 29 05:17:40 PM PDT 24 Jun 29 05:17:42 PM PDT 24 351350361 ps
T356 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2539725634 Jun 29 05:17:07 PM PDT 24 Jun 29 05:17:10 PM PDT 24 549563108 ps
T357 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1663671738 Jun 29 05:17:26 PM PDT 24 Jun 29 05:17:28 PM PDT 24 652201800 ps
T358 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3196001581 Jun 29 05:17:36 PM PDT 24 Jun 29 05:17:37 PM PDT 24 321691698 ps
T59 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3738395372 Jun 29 05:17:16 PM PDT 24 Jun 29 05:17:18 PM PDT 24 1047577418 ps
T359 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1991439881 Jun 29 05:17:22 PM PDT 24 Jun 29 05:17:27 PM PDT 24 2848911834 ps
T360 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1653241285 Jun 29 05:17:54 PM PDT 24 Jun 29 05:17:55 PM PDT 24 463182118 ps
T361 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2844200017 Jun 29 05:17:48 PM PDT 24 Jun 29 05:17:49 PM PDT 24 447102857 ps
T362 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2476503728 Jun 29 05:17:49 PM PDT 24 Jun 29 05:17:51 PM PDT 24 477622410 ps
T363 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2563852534 Jun 29 05:17:44 PM PDT 24 Jun 29 05:17:45 PM PDT 24 442427738 ps
T60 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3607027101 Jun 29 05:17:45 PM PDT 24 Jun 29 05:17:47 PM PDT 24 375687701 ps
T364 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.362900564 Jun 29 05:17:18 PM PDT 24 Jun 29 05:17:19 PM PDT 24 532175392 ps
T365 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1503884709 Jun 29 05:17:27 PM PDT 24 Jun 29 05:17:29 PM PDT 24 538902175 ps
T366 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3671228348 Jun 29 05:17:28 PM PDT 24 Jun 29 05:17:30 PM PDT 24 460882241 ps
T367 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3287010469 Jun 29 05:17:17 PM PDT 24 Jun 29 05:17:33 PM PDT 24 7035339622 ps
T368 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1197097247 Jun 29 05:17:08 PM PDT 24 Jun 29 05:17:10 PM PDT 24 467431165 ps
T369 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.238812393 Jun 29 05:17:37 PM PDT 24 Jun 29 05:17:39 PM PDT 24 313582655 ps
T370 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3242884994 Jun 29 05:17:17 PM PDT 24 Jun 29 05:17:32 PM PDT 24 8234644240 ps
T371 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.411623798 Jun 29 05:17:07 PM PDT 24 Jun 29 05:17:13 PM PDT 24 2233977146 ps
T372 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.180514744 Jun 29 05:17:45 PM PDT 24 Jun 29 05:17:47 PM PDT 24 546803784 ps
T373 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.365944567 Jun 29 05:17:36 PM PDT 24 Jun 29 05:17:43 PM PDT 24 4070138496 ps
T374 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2541974627 Jun 29 05:17:10 PM PDT 24 Jun 29 05:17:12 PM PDT 24 2301002556 ps
T375 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2578028458 Jun 29 05:17:49 PM PDT 24 Jun 29 05:17:50 PM PDT 24 374371289 ps
T376 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.372864586 Jun 29 05:17:37 PM PDT 24 Jun 29 05:17:40 PM PDT 24 843582677 ps
T62 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.211730653 Jun 29 05:17:18 PM PDT 24 Jun 29 05:17:20 PM PDT 24 474607506 ps
T377 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1884138329 Jun 29 05:17:25 PM PDT 24 Jun 29 05:17:27 PM PDT 24 335686981 ps
T378 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1868085464 Jun 29 05:17:16 PM PDT 24 Jun 29 05:17:17 PM PDT 24 378189980 ps
T379 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2651758359 Jun 29 05:17:50 PM PDT 24 Jun 29 05:17:52 PM PDT 24 283559288 ps
T380 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2621512953 Jun 29 05:17:36 PM PDT 24 Jun 29 05:17:38 PM PDT 24 905582505 ps
T381 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1495538294 Jun 29 05:17:17 PM PDT 24 Jun 29 05:17:19 PM PDT 24 499369974 ps
T382 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2432711539 Jun 29 05:17:19 PM PDT 24 Jun 29 05:17:21 PM PDT 24 834943602 ps
T383 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.278587948 Jun 29 05:17:47 PM PDT 24 Jun 29 05:17:51 PM PDT 24 8982171844 ps
T384 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2877009351 Jun 29 05:17:48 PM PDT 24 Jun 29 05:17:49 PM PDT 24 468821346 ps
T385 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1690689623 Jun 29 05:17:17 PM PDT 24 Jun 29 05:17:20 PM PDT 24 2481491981 ps
T386 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.366838992 Jun 29 05:17:50 PM PDT 24 Jun 29 05:17:51 PM PDT 24 375380649 ps
T387 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3597824079 Jun 29 05:17:41 PM PDT 24 Jun 29 05:17:44 PM PDT 24 478197518 ps
T388 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1162228762 Jun 29 05:17:23 PM PDT 24 Jun 29 05:17:24 PM PDT 24 389127050 ps
T389 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2118504652 Jun 29 05:17:39 PM PDT 24 Jun 29 05:17:41 PM PDT 24 407469454 ps
T390 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3010868833 Jun 29 05:17:36 PM PDT 24 Jun 29 05:17:38 PM PDT 24 387732893 ps
T65 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4245583342 Jun 29 05:17:08 PM PDT 24 Jun 29 05:17:10 PM PDT 24 297151452 ps
T391 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2864505220 Jun 29 05:17:09 PM PDT 24 Jun 29 05:17:11 PM PDT 24 520816383 ps
T392 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1580796125 Jun 29 05:17:18 PM PDT 24 Jun 29 05:17:19 PM PDT 24 1528786652 ps
T393 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2645109287 Jun 29 05:17:09 PM PDT 24 Jun 29 05:17:11 PM PDT 24 520890102 ps
T394 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2683923680 Jun 29 05:17:23 PM PDT 24 Jun 29 05:17:25 PM PDT 24 505454384 ps
T395 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3314531048 Jun 29 05:17:43 PM PDT 24 Jun 29 05:17:44 PM PDT 24 557313099 ps
T396 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1355692516 Jun 29 05:17:41 PM PDT 24 Jun 29 05:17:43 PM PDT 24 354685359 ps
T397 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1034371436 Jun 29 05:17:51 PM PDT 24 Jun 29 05:17:53 PM PDT 24 418586414 ps
T398 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2701045278 Jun 29 05:17:21 PM PDT 24 Jun 29 05:17:22 PM PDT 24 538657148 ps
T399 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3509785060 Jun 29 05:17:37 PM PDT 24 Jun 29 05:17:39 PM PDT 24 499689889 ps
T400 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1258746637 Jun 29 05:17:47 PM PDT 24 Jun 29 05:17:49 PM PDT 24 468246698 ps
T63 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1660305088 Jun 29 05:17:10 PM PDT 24 Jun 29 05:17:12 PM PDT 24 597757747 ps
T401 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1752690829 Jun 29 05:17:23 PM PDT 24 Jun 29 05:17:25 PM PDT 24 549693803 ps
T61 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2602208678 Jun 29 05:17:16 PM PDT 24 Jun 29 05:17:27 PM PDT 24 6909541377 ps
T402 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3241723765 Jun 29 05:17:37 PM PDT 24 Jun 29 05:17:40 PM PDT 24 2162967168 ps
T403 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2323766985 Jun 29 05:17:25 PM PDT 24 Jun 29 05:17:27 PM PDT 24 513861753 ps
T404 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2748013827 Jun 29 05:17:29 PM PDT 24 Jun 29 05:17:32 PM PDT 24 1219509793 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3478060601 Jun 29 05:17:11 PM PDT 24 Jun 29 05:17:17 PM PDT 24 6357398315 ps
T66 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4139573021 Jun 29 05:17:39 PM PDT 24 Jun 29 05:17:41 PM PDT 24 385931624 ps
T405 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1007149944 Jun 29 05:17:28 PM PDT 24 Jun 29 05:17:31 PM PDT 24 2581483072 ps
T406 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3950113089 Jun 29 05:17:11 PM PDT 24 Jun 29 05:17:21 PM PDT 24 7299831317 ps
T407 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.218057882 Jun 29 05:17:23 PM PDT 24 Jun 29 05:17:24 PM PDT 24 418927806 ps
T408 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2320708808 Jun 29 05:17:16 PM PDT 24 Jun 29 05:17:18 PM PDT 24 456587075 ps
T409 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3133191362 Jun 29 05:17:38 PM PDT 24 Jun 29 05:17:39 PM PDT 24 372203775 ps
T410 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3977921262 Jun 29 05:17:41 PM PDT 24 Jun 29 05:17:44 PM PDT 24 1778508478 ps
T411 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1159676108 Jun 29 05:17:49 PM PDT 24 Jun 29 05:17:51 PM PDT 24 480724089 ps
T412 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1457675663 Jun 29 05:17:15 PM PDT 24 Jun 29 05:17:18 PM PDT 24 522826439 ps
T413 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1458203292 Jun 29 05:17:23 PM PDT 24 Jun 29 05:17:25 PM PDT 24 394162433 ps
T414 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3533260710 Jun 29 05:17:37 PM PDT 24 Jun 29 05:17:39 PM PDT 24 519816806 ps
T415 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3859122935 Jun 29 05:17:48 PM PDT 24 Jun 29 05:17:51 PM PDT 24 431462873 ps
T416 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3570398555 Jun 29 05:17:48 PM PDT 24 Jun 29 05:17:50 PM PDT 24 505239732 ps
T417 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2429746759 Jun 29 05:17:40 PM PDT 24 Jun 29 05:17:43 PM PDT 24 1072644635 ps
T418 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3326435275 Jun 29 05:17:24 PM PDT 24 Jun 29 05:17:25 PM PDT 24 577935266 ps
T419 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2720962547 Jun 29 05:17:10 PM PDT 24 Jun 29 05:17:11 PM PDT 24 423524350 ps
T420 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4103346581 Jun 29 05:17:08 PM PDT 24 Jun 29 05:17:11 PM PDT 24 4074957876 ps
T421 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3198426569 Jun 29 05:17:37 PM PDT 24 Jun 29 05:17:39 PM PDT 24 331769683 ps
T422 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1874486095 Jun 29 05:17:47 PM PDT 24 Jun 29 05:17:49 PM PDT 24 373796088 ps
T423 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3086070177 Jun 29 05:17:18 PM PDT 24 Jun 29 05:17:19 PM PDT 24 475360866 ps

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2311332911
Short name T5
Test name
Test status
Simulation time 206199325381 ps
CPU time 424.68 seconds
Started Jun 29 06:17:23 PM PDT 24
Finished Jun 29 06:24:28 PM PDT 24
Peak memory 213856 kb
Host smart-dc400f7d-5422-4432-bf4a-05bcfcf4535d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311332911 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2311332911
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.854930627
Short name T8
Test name
Test status
Simulation time 120676385926 ps
CPU time 14.86 seconds
Started Jun 29 06:17:14 PM PDT 24
Finished Jun 29 06:17:29 PM PDT 24
Peak memory 184024 kb
Host smart-4439b672-1ed2-45e2-929f-0810bb4abb88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854930627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.854930627
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3869815782
Short name T31
Test name
Test status
Simulation time 8528576322 ps
CPU time 13.85 seconds
Started Jun 29 05:17:38 PM PDT 24
Finished Jun 29 05:17:53 PM PDT 24
Peak memory 198332 kb
Host smart-6f6be3a9-03ee-4997-a301-2bdf5a05c4b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869815782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3869815782
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2714638243
Short name T38
Test name
Test status
Simulation time 118767529661 ps
CPU time 591.37 seconds
Started Jun 29 06:16:40 PM PDT 24
Finished Jun 29 06:26:32 PM PDT 24
Peak memory 204968 kb
Host smart-89416355-103f-4584-8822-782b20951859
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714638243 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2714638243
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1701735453
Short name T13
Test name
Test status
Simulation time 406912613652 ps
CPU time 455.44 seconds
Started Jun 29 06:16:27 PM PDT 24
Finished Jun 29 06:24:03 PM PDT 24
Peak memory 211232 kb
Host smart-c4413f22-7223-44ce-8fe3-42cf4abca352
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701735453 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1701735453
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3712804630
Short name T100
Test name
Test status
Simulation time 108453666350 ps
CPU time 912.67 seconds
Started Jun 29 06:17:14 PM PDT 24
Finished Jun 29 06:32:27 PM PDT 24
Peak memory 210056 kb
Host smart-1559468e-4486-4458-87e0-b29d0ded0acd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712804630 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3712804630
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.781033399
Short name T28
Test name
Test status
Simulation time 1644126674446 ps
CPU time 811.2 seconds
Started Jun 29 06:16:45 PM PDT 24
Finished Jun 29 06:30:17 PM PDT 24
Peak memory 208568 kb
Host smart-8326cba6-7709-409a-9d1a-76263288cb91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781033399 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.781033399
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1489279310
Short name T54
Test name
Test status
Simulation time 492050569 ps
CPU time 1.51 seconds
Started Jun 29 05:17:10 PM PDT 24
Finished Jun 29 05:17:12 PM PDT 24
Peak memory 194344 kb
Host smart-d87261c5-7247-4a16-b125-73ae579c996e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489279310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1489279310
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2881670009
Short name T87
Test name
Test status
Simulation time 666301729053 ps
CPU time 610.36 seconds
Started Jun 29 06:17:07 PM PDT 24
Finished Jun 29 06:27:18 PM PDT 24
Peak memory 205544 kb
Host smart-531dcf27-7fb3-4a18-b6f9-825bb4700b00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881670009 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2881670009
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3520078384
Short name T3
Test name
Test status
Simulation time 308722860490 ps
CPU time 474.47 seconds
Started Jun 29 06:16:29 PM PDT 24
Finished Jun 29 06:24:24 PM PDT 24
Peak memory 193036 kb
Host smart-1d82fffe-7731-419f-a5f2-8a035819411c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520078384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3520078384
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2152963836
Short name T99
Test name
Test status
Simulation time 90932044517 ps
CPU time 196.86 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:20:33 PM PDT 24
Peak memory 208280 kb
Host smart-cc9e93fa-f87b-4d16-8c8a-a294bf0421b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152963836 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2152963836
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.4258809235
Short name T92
Test name
Test status
Simulation time 171833454919 ps
CPU time 640.26 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:27:47 PM PDT 24
Peak memory 213644 kb
Host smart-db680d2a-edb8-4518-854b-03939da43752
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258809235 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.4258809235
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.4028638471
Short name T83
Test name
Test status
Simulation time 75086332636 ps
CPU time 560.97 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:26:37 PM PDT 24
Peak memory 202168 kb
Host smart-e9e667fc-298c-4a1b-ae3c-20489d9f5265
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028638471 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.4028638471
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.397368223
Short name T15
Test name
Test status
Simulation time 4466843052 ps
CPU time 7.79 seconds
Started Jun 29 06:16:28 PM PDT 24
Finished Jun 29 06:16:36 PM PDT 24
Peak memory 215648 kb
Host smart-370c8bf8-bb25-486b-9c00-af33fb9cb462
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397368223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.397368223
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2735423178
Short name T91
Test name
Test status
Simulation time 44341845299 ps
CPU time 331.39 seconds
Started Jun 29 06:16:30 PM PDT 24
Finished Jun 29 06:22:02 PM PDT 24
Peak memory 214772 kb
Host smart-8944ac76-0763-4750-9d2a-da7e0536a0bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735423178 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2735423178
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1243107115
Short name T85
Test name
Test status
Simulation time 85118706342 ps
CPU time 963.45 seconds
Started Jun 29 06:17:07 PM PDT 24
Finished Jun 29 06:33:12 PM PDT 24
Peak memory 214848 kb
Host smart-dcbff8cf-17ee-4c9c-85f6-3b2de97a4273
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243107115 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1243107115
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2852880508
Short name T95
Test name
Test status
Simulation time 82657467704 ps
CPU time 127.9 seconds
Started Jun 29 06:16:32 PM PDT 24
Finished Jun 29 06:18:40 PM PDT 24
Peak memory 206384 kb
Host smart-25563ec7-cc43-4715-aae5-e6dcd172e4cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852880508 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2852880508
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3533425659
Short name T104
Test name
Test status
Simulation time 109906686070 ps
CPU time 317.64 seconds
Started Jun 29 06:16:37 PM PDT 24
Finished Jun 29 06:21:55 PM PDT 24
Peak memory 213872 kb
Host smart-8d79691f-8723-4d42-81df-3e7af5095862
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533425659 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3533425659
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.78737685
Short name T93
Test name
Test status
Simulation time 419900359061 ps
CPU time 855.95 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:31:23 PM PDT 24
Peak memory 214844 kb
Host smart-cb22e417-cef2-4fff-9cf6-f5821aed0806
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78737685 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.78737685
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.269316362
Short name T125
Test name
Test status
Simulation time 94834622258 ps
CPU time 153.41 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:19:39 PM PDT 24
Peak memory 198072 kb
Host smart-7248e88f-343f-4ea5-8624-8be278ccbcdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269316362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.269316362
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3424931462
Short name T98
Test name
Test status
Simulation time 97057444171 ps
CPU time 154.01 seconds
Started Jun 29 06:17:08 PM PDT 24
Finished Jun 29 06:19:43 PM PDT 24
Peak memory 207664 kb
Host smart-980581be-e8eb-42b3-9969-82faf7d5d86f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424931462 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3424931462
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.619122815
Short name T127
Test name
Test status
Simulation time 4776881576 ps
CPU time 6.7 seconds
Started Jun 29 06:16:30 PM PDT 24
Finished Jun 29 06:16:38 PM PDT 24
Peak memory 198068 kb
Host smart-b35be710-6733-4e52-b981-238c51b1f58f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619122815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.619122815
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.4033753391
Short name T131
Test name
Test status
Simulation time 357642616387 ps
CPU time 536.95 seconds
Started Jun 29 06:16:43 PM PDT 24
Finished Jun 29 06:25:42 PM PDT 24
Peak memory 192760 kb
Host smart-6a5923d9-5141-4e92-95cf-120053c99668
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033753391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.4033753391
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1134159085
Short name T117
Test name
Test status
Simulation time 124730825630 ps
CPU time 714.58 seconds
Started Jun 29 06:17:17 PM PDT 24
Finished Jun 29 06:29:12 PM PDT 24
Peak memory 214748 kb
Host smart-175d8098-daa4-4950-b392-2a22539e68f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134159085 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1134159085
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1009333670
Short name T94
Test name
Test status
Simulation time 169145427724 ps
CPU time 330.49 seconds
Started Jun 29 06:16:27 PM PDT 24
Finished Jun 29 06:21:58 PM PDT 24
Peak memory 206620 kb
Host smart-6aec4804-6fc0-42a8-b3e0-5ceee42b02ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009333670 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1009333670
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2137049890
Short name T80
Test name
Test status
Simulation time 211206551193 ps
CPU time 276.33 seconds
Started Jun 29 06:16:59 PM PDT 24
Finished Jun 29 06:21:36 PM PDT 24
Peak memory 192800 kb
Host smart-517924ce-0a03-4f17-9507-5f3a5482027a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137049890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2137049890
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.4174847630
Short name T113
Test name
Test status
Simulation time 151060526946 ps
CPU time 201.48 seconds
Started Jun 29 06:17:14 PM PDT 24
Finished Jun 29 06:20:36 PM PDT 24
Peak memory 191720 kb
Host smart-22fc0bf6-2280-49a8-8166-e91ab3c8b677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174847630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.4174847630
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2737231248
Short name T107
Test name
Test status
Simulation time 40893049039 ps
CPU time 41.05 seconds
Started Jun 29 06:17:09 PM PDT 24
Finished Jun 29 06:17:51 PM PDT 24
Peak memory 192756 kb
Host smart-2cd4c572-54b3-48c1-a2cd-f65ec4b598fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737231248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2737231248
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.427738383
Short name T37
Test name
Test status
Simulation time 179594797757 ps
CPU time 701.38 seconds
Started Jun 29 06:17:23 PM PDT 24
Finished Jun 29 06:29:05 PM PDT 24
Peak memory 206000 kb
Host smart-2df6fd75-3f65-4020-b537-ec707f00acee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427738383 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.427738383
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.864450370
Short name T111
Test name
Test status
Simulation time 171134543829 ps
CPU time 245.07 seconds
Started Jun 29 06:17:17 PM PDT 24
Finished Jun 29 06:21:22 PM PDT 24
Peak memory 198012 kb
Host smart-f8c99104-f590-4956-a666-0996f40bbcc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864450370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.864450370
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1938946685
Short name T138
Test name
Test status
Simulation time 88565827520 ps
CPU time 133.59 seconds
Started Jun 29 06:16:49 PM PDT 24
Finished Jun 29 06:19:03 PM PDT 24
Peak memory 191716 kb
Host smart-ff8c4fb0-165b-48c8-bc84-8ca4b94dbaf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938946685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1938946685
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3541693656
Short name T97
Test name
Test status
Simulation time 191918223998 ps
CPU time 33.28 seconds
Started Jun 29 06:16:29 PM PDT 24
Finished Jun 29 06:17:03 PM PDT 24
Peak memory 198100 kb
Host smart-dad162dd-74e0-4d6e-a085-81e318072a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541693656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3541693656
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.4072618635
Short name T137
Test name
Test status
Simulation time 36585402722 ps
CPU time 5.53 seconds
Started Jun 29 06:17:08 PM PDT 24
Finished Jun 29 06:17:14 PM PDT 24
Peak memory 191716 kb
Host smart-18e3c609-24ea-411a-b278-08f70b8aba72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072618635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.4072618635
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.183908868
Short name T102
Test name
Test status
Simulation time 74249727057 ps
CPU time 10.36 seconds
Started Jun 29 06:16:34 PM PDT 24
Finished Jun 29 06:16:45 PM PDT 24
Peak memory 198084 kb
Host smart-921098e0-ce52-4bf2-b850-94b0b4829565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183908868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.183908868
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2731512387
Short name T36
Test name
Test status
Simulation time 86671842754 ps
CPU time 229.16 seconds
Started Jun 29 06:16:44 PM PDT 24
Finished Jun 29 06:20:35 PM PDT 24
Peak memory 209128 kb
Host smart-d402d6c2-7101-4e69-8ec9-4e97769616a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731512387 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2731512387
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.14443413
Short name T155
Test name
Test status
Simulation time 286143538490 ps
CPU time 381.06 seconds
Started Jun 29 06:17:07 PM PDT 24
Finished Jun 29 06:23:29 PM PDT 24
Peak memory 198028 kb
Host smart-1e5f3960-4c42-4870-a98d-7965242c4b33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14443413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_al
l.14443413
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3017311548
Short name T106
Test name
Test status
Simulation time 156626996467 ps
CPU time 235.25 seconds
Started Jun 29 06:16:45 PM PDT 24
Finished Jun 29 06:20:41 PM PDT 24
Peak memory 191692 kb
Host smart-17aa2a62-72ea-4f5b-b555-a241d7a77d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017311548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3017311548
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2686075268
Short name T119
Test name
Test status
Simulation time 133231201534 ps
CPU time 87 seconds
Started Jun 29 06:17:14 PM PDT 24
Finished Jun 29 06:18:42 PM PDT 24
Peak memory 192828 kb
Host smart-3b4f21e2-d111-4510-a127-5286a10f9191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686075268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2686075268
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2191744038
Short name T89
Test name
Test status
Simulation time 61828820205 ps
CPU time 263.08 seconds
Started Jun 29 06:16:21 PM PDT 24
Finished Jun 29 06:20:45 PM PDT 24
Peak memory 207092 kb
Host smart-fa7dddc8-df6b-475b-a384-1f02b1e38abb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191744038 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2191744038
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.620962089
Short name T109
Test name
Test status
Simulation time 74965441456 ps
CPU time 23.6 seconds
Started Jun 29 06:16:36 PM PDT 24
Finished Jun 29 06:17:01 PM PDT 24
Peak memory 197880 kb
Host smart-9ff20fdf-5dee-49fa-90b9-821af668fe40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620962089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.620962089
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3178554328
Short name T7
Test name
Test status
Simulation time 176976324088 ps
CPU time 217.85 seconds
Started Jun 29 06:16:31 PM PDT 24
Finished Jun 29 06:20:09 PM PDT 24
Peak memory 198052 kb
Host smart-14777a97-9587-4bbc-b97b-a7d36f51d6c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178554328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3178554328
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1424841576
Short name T140
Test name
Test status
Simulation time 248668445841 ps
CPU time 682.8 seconds
Started Jun 29 06:17:02 PM PDT 24
Finished Jun 29 06:28:25 PM PDT 24
Peak memory 206572 kb
Host smart-33329d31-f2a2-4e27-ad97-2e9bd4683776
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424841576 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1424841576
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2617096222
Short name T6
Test name
Test status
Simulation time 266025415073 ps
CPU time 369.53 seconds
Started Jun 29 06:16:57 PM PDT 24
Finished Jun 29 06:23:07 PM PDT 24
Peak memory 198080 kb
Host smart-e2ef36c0-ed9d-408e-a596-d0d95483a478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617096222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2617096222
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1530421354
Short name T136
Test name
Test status
Simulation time 117963699230 ps
CPU time 84.99 seconds
Started Jun 29 06:17:17 PM PDT 24
Finished Jun 29 06:18:43 PM PDT 24
Peak memory 198032 kb
Host smart-15369317-3a4e-4db9-bad8-c8cfa673310c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530421354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1530421354
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.421646717
Short name T129
Test name
Test status
Simulation time 242688426279 ps
CPU time 435.77 seconds
Started Jun 29 06:16:35 PM PDT 24
Finished Jun 29 06:23:52 PM PDT 24
Peak memory 211096 kb
Host smart-9b287f32-0d0b-4945-8b75-5e28554a5673
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421646717 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.421646717
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2732675222
Short name T24
Test name
Test status
Simulation time 113859679872 ps
CPU time 252.53 seconds
Started Jun 29 06:16:49 PM PDT 24
Finished Jun 29 06:21:03 PM PDT 24
Peak memory 206664 kb
Host smart-ec222962-f89e-4ca4-a003-6b9c1b9c121d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732675222 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2732675222
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1824989993
Short name T158
Test name
Test status
Simulation time 20120579879 ps
CPU time 160.2 seconds
Started Jun 29 06:16:43 PM PDT 24
Finished Jun 29 06:19:25 PM PDT 24
Peak memory 198420 kb
Host smart-7a4bee5b-ba52-482c-8ee1-324dd390ba19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824989993 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1824989993
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3569205599
Short name T40
Test name
Test status
Simulation time 4640705984 ps
CPU time 30.48 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:17:37 PM PDT 24
Peak memory 214624 kb
Host smart-cc1ae899-a8f8-43c4-9f57-ff35abcee4c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569205599 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3569205599
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3120422040
Short name T39
Test name
Test status
Simulation time 348423299253 ps
CPU time 514.63 seconds
Started Jun 29 06:17:24 PM PDT 24
Finished Jun 29 06:25:59 PM PDT 24
Peak memory 203600 kb
Host smart-68d655c1-6a81-404b-b84e-2cbe6fbda965
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120422040 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3120422040
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2731778269
Short name T46
Test name
Test status
Simulation time 357943202 ps
CPU time 0.9 seconds
Started Jun 29 06:16:58 PM PDT 24
Finished Jun 29 06:16:59 PM PDT 24
Peak memory 196436 kb
Host smart-05c5939a-97f4-4275-9f2a-892d6be6ee5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731778269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2731778269
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.4132993513
Short name T4
Test name
Test status
Simulation time 418381270776 ps
CPU time 293.78 seconds
Started Jun 29 06:16:44 PM PDT 24
Finished Jun 29 06:21:39 PM PDT 24
Peak memory 192460 kb
Host smart-c9e4aec4-8e16-4222-bdcf-a9222c6e6dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132993513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.4132993513
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.363469916
Short name T150
Test name
Test status
Simulation time 185162781862 ps
CPU time 126.46 seconds
Started Jun 29 06:16:30 PM PDT 24
Finished Jun 29 06:18:37 PM PDT 24
Peak memory 207596 kb
Host smart-ac038720-4deb-409f-a09e-e9bcab02c8f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363469916 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.363469916
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2246016749
Short name T128
Test name
Test status
Simulation time 15364104000 ps
CPU time 161.66 seconds
Started Jun 29 06:16:27 PM PDT 24
Finished Jun 29 06:19:09 PM PDT 24
Peak memory 214392 kb
Host smart-495ccef7-122b-4dc6-a64d-14c20ca1966a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246016749 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2246016749
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3570547961
Short name T70
Test name
Test status
Simulation time 332737780 ps
CPU time 0.76 seconds
Started Jun 29 05:17:09 PM PDT 24
Finished Jun 29 05:17:11 PM PDT 24
Peak memory 193036 kb
Host smart-a397e95e-e30a-4ebb-8961-58cb44d3a3a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570547961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3570547961
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.773019320
Short name T26
Test name
Test status
Simulation time 112067766936 ps
CPU time 39.69 seconds
Started Jun 29 06:16:55 PM PDT 24
Finished Jun 29 06:17:35 PM PDT 24
Peak memory 192736 kb
Host smart-7618d9b6-ff92-42db-8513-b7bcdad92dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773019320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.773019320
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1648752419
Short name T151
Test name
Test status
Simulation time 429721692244 ps
CPU time 197.44 seconds
Started Jun 29 06:17:21 PM PDT 24
Finished Jun 29 06:20:39 PM PDT 24
Peak memory 198096 kb
Host smart-547716d7-6128-4a9c-97a8-0c6c1300f0f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648752419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1648752419
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.133102252
Short name T118
Test name
Test status
Simulation time 263384734313 ps
CPU time 165.43 seconds
Started Jun 29 06:16:38 PM PDT 24
Finished Jun 29 06:19:24 PM PDT 24
Peak memory 192752 kb
Host smart-0a283ff2-856e-486f-bc95-462fa4f02746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133102252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.133102252
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2631825694
Short name T121
Test name
Test status
Simulation time 58056948805 ps
CPU time 38.74 seconds
Started Jun 29 06:16:44 PM PDT 24
Finished Jun 29 06:17:24 PM PDT 24
Peak memory 191624 kb
Host smart-53004205-9281-4cdb-9d4c-d54718080181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631825694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2631825694
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1768251326
Short name T120
Test name
Test status
Simulation time 153985350585 ps
CPU time 237.22 seconds
Started Jun 29 06:16:59 PM PDT 24
Finished Jun 29 06:20:57 PM PDT 24
Peak memory 197984 kb
Host smart-e18275dd-7c23-44c9-b83d-366504d4c7eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768251326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1768251326
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.915853352
Short name T154
Test name
Test status
Simulation time 146761122888 ps
CPU time 48.75 seconds
Started Jun 29 06:17:00 PM PDT 24
Finished Jun 29 06:17:49 PM PDT 24
Peak memory 191716 kb
Host smart-07c6a116-115d-4ef9-b06c-444947415a0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915853352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.915853352
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.528206895
Short name T122
Test name
Test status
Simulation time 4028422619 ps
CPU time 2.46 seconds
Started Jun 29 06:17:07 PM PDT 24
Finished Jun 29 06:17:11 PM PDT 24
Peak memory 191712 kb
Host smart-f18a3d3f-396b-4318-a19a-bf447e149e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528206895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.528206895
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1032807829
Short name T126
Test name
Test status
Simulation time 16278227748 ps
CPU time 6.96 seconds
Started Jun 29 06:17:16 PM PDT 24
Finished Jun 29 06:17:23 PM PDT 24
Peak memory 191720 kb
Host smart-64507cdd-8187-4c82-a363-f2d4dce6bf51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032807829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1032807829
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3696446943
Short name T86
Test name
Test status
Simulation time 22297260705 ps
CPU time 237.79 seconds
Started Jun 29 06:16:36 PM PDT 24
Finished Jun 29 06:20:34 PM PDT 24
Peak memory 206680 kb
Host smart-a63642bd-fd3b-4fee-9d1c-0d880adbca41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696446943 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3696446943
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.4187149518
Short name T144
Test name
Test status
Simulation time 3619502020 ps
CPU time 6.43 seconds
Started Jun 29 06:16:54 PM PDT 24
Finished Jun 29 06:17:00 PM PDT 24
Peak memory 184020 kb
Host smart-ab9dfcf6-50da-440f-9188-7eec570c93cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187149518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.4187149518
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3828411377
Short name T41
Test name
Test status
Simulation time 180996524415 ps
CPU time 511.84 seconds
Started Jun 29 06:17:05 PM PDT 24
Finished Jun 29 06:25:38 PM PDT 24
Peak memory 212544 kb
Host smart-3534c483-5c86-4b63-a633-79b09b162dec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828411377 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3828411377
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1158943930
Short name T116
Test name
Test status
Simulation time 311581550494 ps
CPU time 464.34 seconds
Started Jun 29 06:16:55 PM PDT 24
Finished Jun 29 06:24:40 PM PDT 24
Peak memory 198080 kb
Host smart-b7222cc8-233a-462c-a1a4-223126382893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158943930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1158943930
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1216430397
Short name T153
Test name
Test status
Simulation time 53159188940 ps
CPU time 126.32 seconds
Started Jun 29 06:16:29 PM PDT 24
Finished Jun 29 06:18:37 PM PDT 24
Peak memory 206640 kb
Host smart-ebec3b2d-45ab-4252-9e60-d067b73720a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216430397 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1216430397
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1615180373
Short name T11
Test name
Test status
Simulation time 54928169937 ps
CPU time 443.52 seconds
Started Jun 29 06:17:27 PM PDT 24
Finished Jun 29 06:24:51 PM PDT 24
Peak memory 209400 kb
Host smart-cfaeff00-deb4-4690-817c-f7f23a35032a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615180373 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1615180373
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2959353831
Short name T167
Test name
Test status
Simulation time 229370685953 ps
CPU time 146.24 seconds
Started Jun 29 06:16:39 PM PDT 24
Finished Jun 29 06:19:05 PM PDT 24
Peak memory 192820 kb
Host smart-204f4f27-0905-42bc-a71b-2e7390966860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959353831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2959353831
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3337230429
Short name T25
Test name
Test status
Simulation time 445502357 ps
CPU time 0.9 seconds
Started Jun 29 06:16:48 PM PDT 24
Finished Jun 29 06:16:49 PM PDT 24
Peak memory 196520 kb
Host smart-a63e25c2-5ed6-4e80-85ec-f802cfb5f7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337230429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3337230429
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2911030371
Short name T152
Test name
Test status
Simulation time 488689676 ps
CPU time 0.79 seconds
Started Jun 29 06:16:56 PM PDT 24
Finished Jun 29 06:16:57 PM PDT 24
Peak memory 196564 kb
Host smart-ccee95e1-3059-45b9-a74d-e64bae482e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911030371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2911030371
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3203996596
Short name T114
Test name
Test status
Simulation time 536821038 ps
CPU time 1.25 seconds
Started Jun 29 06:16:55 PM PDT 24
Finished Jun 29 06:16:56 PM PDT 24
Peak memory 196480 kb
Host smart-13bdbd9c-b740-4778-a510-51535564de73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203996596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3203996596
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1458809930
Short name T162
Test name
Test status
Simulation time 645028322911 ps
CPU time 897.84 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:32:04 PM PDT 24
Peak memory 191672 kb
Host smart-961e266d-9b53-4a78-b4d3-7e9675e94511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458809930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1458809930
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3658076628
Short name T148
Test name
Test status
Simulation time 363993661 ps
CPU time 0.68 seconds
Started Jun 29 06:17:08 PM PDT 24
Finished Jun 29 06:17:09 PM PDT 24
Peak memory 196476 kb
Host smart-c543a019-0197-42a6-8265-5bb4d641488b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658076628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3658076628
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.4128463231
Short name T105
Test name
Test status
Simulation time 91216819026 ps
CPU time 35.56 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:51 PM PDT 24
Peak memory 198072 kb
Host smart-c2f49971-2e9a-481c-9486-303369227cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128463231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.4128463231
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.146610750
Short name T108
Test name
Test status
Simulation time 613062542 ps
CPU time 0.79 seconds
Started Jun 29 06:17:24 PM PDT 24
Finished Jun 29 06:17:26 PM PDT 24
Peak memory 196568 kb
Host smart-3dc1a0cd-89b4-4cd4-8f5a-a9ecfdd1360f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146610750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.146610750
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2130648298
Short name T160
Test name
Test status
Simulation time 449319496 ps
CPU time 1.29 seconds
Started Jun 29 06:17:09 PM PDT 24
Finished Jun 29 06:17:11 PM PDT 24
Peak memory 196464 kb
Host smart-8d6d3427-81d5-4301-ba0a-bc7a1ec0c859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130648298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2130648298
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.244726207
Short name T115
Test name
Test status
Simulation time 398576253 ps
CPU time 1.21 seconds
Started Jun 29 06:17:08 PM PDT 24
Finished Jun 29 06:17:10 PM PDT 24
Peak memory 196516 kb
Host smart-82190f5f-f636-4da5-8ff2-7ca359e79d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244726207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.244726207
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.752756930
Short name T143
Test name
Test status
Simulation time 143778622750 ps
CPU time 48.5 seconds
Started Jun 29 06:17:07 PM PDT 24
Finished Jun 29 06:17:57 PM PDT 24
Peak memory 191720 kb
Host smart-0bd65b49-a775-4db6-9a08-e406e723aaf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752756930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.752756930
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3264936776
Short name T84
Test name
Test status
Simulation time 66252808171 ps
CPU time 497.27 seconds
Started Jun 29 06:17:23 PM PDT 24
Finished Jun 29 06:25:41 PM PDT 24
Peak memory 201620 kb
Host smart-6950373a-5467-4c23-bd16-5e381bc64d59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264936776 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3264936776
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2397190574
Short name T132
Test name
Test status
Simulation time 132963746351 ps
CPU time 44.15 seconds
Started Jun 29 06:16:27 PM PDT 24
Finished Jun 29 06:17:12 PM PDT 24
Peak memory 192348 kb
Host smart-7955c3d8-1b02-4400-8212-5778ffbb5a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397190574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2397190574
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.401344905
Short name T112
Test name
Test status
Simulation time 644941534 ps
CPU time 0.65 seconds
Started Jun 29 06:16:37 PM PDT 24
Finished Jun 29 06:16:38 PM PDT 24
Peak memory 196456 kb
Host smart-a3503f86-bbae-4f90-a808-286b56c719a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401344905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.401344905
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2002042436
Short name T169
Test name
Test status
Simulation time 34017898983 ps
CPU time 331.72 seconds
Started Jun 29 06:16:57 PM PDT 24
Finished Jun 29 06:22:29 PM PDT 24
Peak memory 206668 kb
Host smart-998bbafa-1801-40db-932e-f3ef513633f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002042436 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2002042436
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.4163587302
Short name T174
Test name
Test status
Simulation time 31670222935 ps
CPU time 3.9 seconds
Started Jun 29 06:17:25 PM PDT 24
Finished Jun 29 06:17:29 PM PDT 24
Peak memory 191712 kb
Host smart-1d426288-23e7-4c25-bc03-e07015a3ad20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163587302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.4163587302
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.692473427
Short name T139
Test name
Test status
Simulation time 109335636518 ps
CPU time 18.29 seconds
Started Jun 29 06:17:24 PM PDT 24
Finished Jun 29 06:17:43 PM PDT 24
Peak memory 198068 kb
Host smart-c7fd911d-a520-4add-a9d0-fbb701a9bf15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692473427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.692473427
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1055328194
Short name T133
Test name
Test status
Simulation time 466670517 ps
CPU time 1.3 seconds
Started Jun 29 06:16:30 PM PDT 24
Finished Jun 29 06:16:32 PM PDT 24
Peak memory 196480 kb
Host smart-8e7f05c3-1a82-48b8-b7b1-962ec8a0be4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055328194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1055328194
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.4214084238
Short name T145
Test name
Test status
Simulation time 591421392 ps
CPU time 0.83 seconds
Started Jun 29 06:16:28 PM PDT 24
Finished Jun 29 06:16:30 PM PDT 24
Peak memory 196328 kb
Host smart-1da46a95-a776-47e2-9dca-ff6e25d92956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214084238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.4214084238
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2797467266
Short name T123
Test name
Test status
Simulation time 395702758 ps
CPU time 1.04 seconds
Started Jun 29 06:16:20 PM PDT 24
Finished Jun 29 06:16:22 PM PDT 24
Peak memory 196480 kb
Host smart-96745a27-5adc-4460-a82a-12eb18dd0246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797467266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2797467266
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3163603558
Short name T27
Test name
Test status
Simulation time 630489360 ps
CPU time 0.83 seconds
Started Jun 29 06:16:35 PM PDT 24
Finished Jun 29 06:16:37 PM PDT 24
Peak memory 196404 kb
Host smart-b8032ce1-4b02-4639-b945-97338fb1928c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163603558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3163603558
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3095277936
Short name T9
Test name
Test status
Simulation time 362800457 ps
CPU time 1.2 seconds
Started Jun 29 06:16:43 PM PDT 24
Finished Jun 29 06:16:45 PM PDT 24
Peak memory 196520 kb
Host smart-b3c4f19c-cc73-4118-8251-7bd42e6e925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095277936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3095277936
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2473744128
Short name T110
Test name
Test status
Simulation time 484521542 ps
CPU time 1.01 seconds
Started Jun 29 06:17:09 PM PDT 24
Finished Jun 29 06:17:10 PM PDT 24
Peak memory 196560 kb
Host smart-b4a2724a-9af7-4c76-940b-8f20ce12e874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473744128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2473744128
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.742265417
Short name T178
Test name
Test status
Simulation time 110899059883 ps
CPU time 188.58 seconds
Started Jun 29 06:17:14 PM PDT 24
Finished Jun 29 06:20:24 PM PDT 24
Peak memory 213836 kb
Host smart-c62a09f2-71cd-442f-a386-7698a5e90e71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742265417 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.742265417
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2831948909
Short name T134
Test name
Test status
Simulation time 549235064 ps
CPU time 1.4 seconds
Started Jun 29 06:17:23 PM PDT 24
Finished Jun 29 06:17:25 PM PDT 24
Peak memory 196468 kb
Host smart-65cd1f45-bb72-46a3-bdb5-eb078b16517c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831948909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2831948909
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.403667930
Short name T141
Test name
Test status
Simulation time 426064720 ps
CPU time 1.14 seconds
Started Jun 29 06:16:29 PM PDT 24
Finished Jun 29 06:16:31 PM PDT 24
Peak memory 196468 kb
Host smart-23b128e9-b4ff-44ca-b692-8c394df4b2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403667930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.403667930
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.994655903
Short name T177
Test name
Test status
Simulation time 9071408268 ps
CPU time 68.45 seconds
Started Jun 29 06:16:36 PM PDT 24
Finished Jun 29 06:17:45 PM PDT 24
Peak memory 206740 kb
Host smart-02f21064-5207-4d07-bb8e-5daf6e889aa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994655903 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.994655903
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1980779169
Short name T33
Test name
Test status
Simulation time 8683655269 ps
CPU time 2.91 seconds
Started Jun 29 05:17:38 PM PDT 24
Finished Jun 29 05:17:42 PM PDT 24
Peak memory 197972 kb
Host smart-8fc8a1bf-4f2f-4021-b09f-288dea2c99b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980779169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1980779169
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.4135512428
Short name T190
Test name
Test status
Simulation time 465138895092 ps
CPU time 619.48 seconds
Started Jun 29 06:16:21 PM PDT 24
Finished Jun 29 06:26:42 PM PDT 24
Peak memory 198056 kb
Host smart-4a3f1893-4056-4280-8230-d5803851506d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135512428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.4135512428
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1889140739
Short name T103
Test name
Test status
Simulation time 392508858 ps
CPU time 0.92 seconds
Started Jun 29 06:16:29 PM PDT 24
Finished Jun 29 06:16:30 PM PDT 24
Peak memory 196352 kb
Host smart-1506c621-8a08-4182-aeee-3c1f66ce8b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889140739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1889140739
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3492647021
Short name T146
Test name
Test status
Simulation time 82319984544 ps
CPU time 64.87 seconds
Started Jun 29 06:16:27 PM PDT 24
Finished Jun 29 06:17:32 PM PDT 24
Peak memory 198044 kb
Host smart-030a2e84-1018-4849-9d93-bb9d02dd57f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492647021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3492647021
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1111594155
Short name T165
Test name
Test status
Simulation time 228838397467 ps
CPU time 343.57 seconds
Started Jun 29 06:16:38 PM PDT 24
Finished Jun 29 06:22:22 PM PDT 24
Peak memory 192812 kb
Host smart-babe9328-44ee-416e-bd36-6cd331044a6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111594155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1111594155
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3070243751
Short name T171
Test name
Test status
Simulation time 379397569412 ps
CPU time 558.28 seconds
Started Jun 29 06:16:38 PM PDT 24
Finished Jun 29 06:25:57 PM PDT 24
Peak memory 191464 kb
Host smart-cf1cc442-b14a-4379-9e8e-dfe49ec0f98b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070243751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3070243751
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1533456879
Short name T157
Test name
Test status
Simulation time 389175816 ps
CPU time 1.06 seconds
Started Jun 29 06:16:31 PM PDT 24
Finished Jun 29 06:16:33 PM PDT 24
Peak memory 196492 kb
Host smart-b0853c00-4216-461d-8d44-e4d74dffd3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533456879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1533456879
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.504756564
Short name T149
Test name
Test status
Simulation time 542668752 ps
CPU time 0.98 seconds
Started Jun 29 06:16:54 PM PDT 24
Finished Jun 29 06:16:55 PM PDT 24
Peak memory 196404 kb
Host smart-5e03f761-d68a-412a-bbc1-9ed33b849c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504756564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.504756564
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2834922170
Short name T176
Test name
Test status
Simulation time 50537295680 ps
CPU time 63.97 seconds
Started Jun 29 06:16:59 PM PDT 24
Finished Jun 29 06:18:03 PM PDT 24
Peak memory 214108 kb
Host smart-26b8866d-9bd0-4039-9c65-86de6429c171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834922170 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2834922170
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1143430854
Short name T96
Test name
Test status
Simulation time 282540905823 ps
CPU time 377.55 seconds
Started Jun 29 06:17:08 PM PDT 24
Finished Jun 29 06:23:27 PM PDT 24
Peak memory 191668 kb
Host smart-23af191b-715b-4de5-a2ce-e3b25b4a7be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143430854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1143430854
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.433678015
Short name T159
Test name
Test status
Simulation time 405086459 ps
CPU time 0.9 seconds
Started Jun 29 06:16:29 PM PDT 24
Finished Jun 29 06:16:31 PM PDT 24
Peak memory 196524 kb
Host smart-e6d91088-5cb1-4991-9075-69020f7af5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433678015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.433678015
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1443486900
Short name T77
Test name
Test status
Simulation time 509661586 ps
CPU time 1.34 seconds
Started Jun 29 06:17:22 PM PDT 24
Finished Jun 29 06:17:24 PM PDT 24
Peak memory 196560 kb
Host smart-66c50154-4317-4435-a913-f4b9cfbac16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443486900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1443486900
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.4161558641
Short name T163
Test name
Test status
Simulation time 48152326340 ps
CPU time 7.06 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:23 PM PDT 24
Peak memory 191712 kb
Host smart-559a735a-f43b-420b-ad4b-6be2695b421a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161558641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.4161558641
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3529250021
Short name T182
Test name
Test status
Simulation time 458377582797 ps
CPU time 170.42 seconds
Started Jun 29 06:16:35 PM PDT 24
Finished Jun 29 06:19:26 PM PDT 24
Peak memory 192480 kb
Host smart-63e05cf3-1237-4f45-a5db-760ec672a832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529250021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3529250021
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.4048555268
Short name T192
Test name
Test status
Simulation time 56290378181 ps
CPU time 114.36 seconds
Started Jun 29 06:16:44 PM PDT 24
Finished Jun 29 06:18:40 PM PDT 24
Peak memory 213884 kb
Host smart-4b896b1e-45bf-440c-b7c3-bf5e9258a1be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048555268 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.4048555268
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.752460525
Short name T156
Test name
Test status
Simulation time 22417884457 ps
CPU time 197.52 seconds
Started Jun 29 06:16:54 PM PDT 24
Finished Jun 29 06:20:12 PM PDT 24
Peak memory 206644 kb
Host smart-41664d04-1808-44b7-b789-b1d7afea196c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752460525 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.752460525
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3004632343
Short name T147
Test name
Test status
Simulation time 147178394745 ps
CPU time 188.24 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:20:14 PM PDT 24
Peak memory 192732 kb
Host smart-9252aa7d-ab0a-46e0-b924-1e5e795c5cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004632343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3004632343
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.983413102
Short name T142
Test name
Test status
Simulation time 373454841 ps
CPU time 0.74 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:17 PM PDT 24
Peak memory 196464 kb
Host smart-f5bd4009-5fb1-468e-8e58-32958da0f4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983413102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.983413102
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1936834551
Short name T173
Test name
Test status
Simulation time 194969485929 ps
CPU time 152.32 seconds
Started Jun 29 06:16:30 PM PDT 24
Finished Jun 29 06:19:04 PM PDT 24
Peak memory 191684 kb
Host smart-a4befb98-60a8-4359-9987-e0384edca8b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936834551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1936834551
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1342545390
Short name T179
Test name
Test status
Simulation time 158047592075 ps
CPU time 55.88 seconds
Started Jun 29 06:16:38 PM PDT 24
Finished Jun 29 06:17:35 PM PDT 24
Peak memory 191432 kb
Host smart-719696c4-da2d-4ac2-8c72-01cfd548d079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342545390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1342545390
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2186087140
Short name T188
Test name
Test status
Simulation time 325036600892 ps
CPU time 470.15 seconds
Started Jun 29 06:16:44 PM PDT 24
Finished Jun 29 06:24:35 PM PDT 24
Peak memory 192228 kb
Host smart-def5f2b7-9a0e-4094-ac6e-10f17c183a2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186087140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2186087140
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1175304808
Short name T161
Test name
Test status
Simulation time 107056384779 ps
CPU time 227.62 seconds
Started Jun 29 06:16:44 PM PDT 24
Finished Jun 29 06:20:33 PM PDT 24
Peak memory 200368 kb
Host smart-d1b0b615-7608-4aee-941d-8c0dde6cf244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175304808 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1175304808
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.561809061
Short name T195
Test name
Test status
Simulation time 388785280 ps
CPU time 0.76 seconds
Started Jun 29 06:16:47 PM PDT 24
Finished Jun 29 06:16:48 PM PDT 24
Peak memory 196536 kb
Host smart-7a94c943-b4bd-4e5c-9642-3688d388b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561809061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.561809061
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.4257311795
Short name T170
Test name
Test status
Simulation time 527388016 ps
CPU time 0.75 seconds
Started Jun 29 06:17:00 PM PDT 24
Finished Jun 29 06:17:01 PM PDT 24
Peak memory 196524 kb
Host smart-ed303d99-4804-4b22-94ef-f85164af2024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257311795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4257311795
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1225876333
Short name T172
Test name
Test status
Simulation time 575931919 ps
CPU time 0.84 seconds
Started Jun 29 06:16:59 PM PDT 24
Finished Jun 29 06:17:00 PM PDT 24
Peak memory 196440 kb
Host smart-a67b9234-1cee-4315-a60f-990ce3aaa0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225876333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1225876333
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.826895754
Short name T19
Test name
Test status
Simulation time 435329817 ps
CPU time 1.25 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:17:08 PM PDT 24
Peak memory 196440 kb
Host smart-b0d073c8-ee5b-4201-b3be-aa6cea815535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826895754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.826895754
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1863238638
Short name T184
Test name
Test status
Simulation time 417418065 ps
CPU time 1.21 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:17:08 PM PDT 24
Peak memory 196524 kb
Host smart-6e6d954e-d512-44a4-bd13-864be27a0787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863238638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1863238638
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2394294963
Short name T197
Test name
Test status
Simulation time 605983703 ps
CPU time 1 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:17 PM PDT 24
Peak memory 196416 kb
Host smart-88d8e2b7-a6e3-4665-b282-235f9d0e63ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394294963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2394294963
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3601305745
Short name T82
Test name
Test status
Simulation time 32820822968 ps
CPU time 292.05 seconds
Started Jun 29 06:17:14 PM PDT 24
Finished Jun 29 06:22:07 PM PDT 24
Peak memory 206664 kb
Host smart-de3a5958-9687-406e-b9d4-09883a22510c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601305745 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3601305745
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2282632434
Short name T166
Test name
Test status
Simulation time 437583140 ps
CPU time 0.75 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:16 PM PDT 24
Peak memory 196396 kb
Host smart-b5398246-f09d-47d9-90d2-ebb56a5c2742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282632434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2282632434
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.727332249
Short name T2
Test name
Test status
Simulation time 563109549 ps
CPU time 1.34 seconds
Started Jun 29 06:16:36 PM PDT 24
Finished Jun 29 06:16:38 PM PDT 24
Peak memory 196436 kb
Host smart-2bddcc94-90bf-4413-ac4c-321cbd9c485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727332249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.727332249
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1362605109
Short name T124
Test name
Test status
Simulation time 440973147 ps
CPU time 1.23 seconds
Started Jun 29 06:16:40 PM PDT 24
Finished Jun 29 06:16:42 PM PDT 24
Peak memory 196560 kb
Host smart-0f78c3b2-56fe-48e8-bc03-101f41414db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362605109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1362605109
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.4168313419
Short name T135
Test name
Test status
Simulation time 439855665 ps
CPU time 0.73 seconds
Started Jun 29 06:16:37 PM PDT 24
Finished Jun 29 06:16:39 PM PDT 24
Peak memory 196504 kb
Host smart-65ba76b7-3607-4f22-a624-306d9db90193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168313419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4168313419
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.763789296
Short name T168
Test name
Test status
Simulation time 494565326 ps
CPU time 0.82 seconds
Started Jun 29 06:16:44 PM PDT 24
Finished Jun 29 06:16:47 PM PDT 24
Peak memory 196444 kb
Host smart-1d6c943f-e528-4814-9ab3-6b57dd66b064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763789296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.763789296
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.77875987
Short name T164
Test name
Test status
Simulation time 664969611 ps
CPU time 0.71 seconds
Started Jun 29 06:16:49 PM PDT 24
Finished Jun 29 06:16:50 PM PDT 24
Peak memory 196544 kb
Host smart-2cc5d54b-2bca-4754-8e6a-49485a59560e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77875987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.77875987
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1402426199
Short name T194
Test name
Test status
Simulation time 381336623 ps
CPU time 0.89 seconds
Started Jun 29 06:16:58 PM PDT 24
Finished Jun 29 06:16:59 PM PDT 24
Peak memory 196500 kb
Host smart-631557a8-a879-4dbe-9afa-900e377b25a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402426199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1402426199
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.477478819
Short name T101
Test name
Test status
Simulation time 546516842 ps
CPU time 1.04 seconds
Started Jun 29 06:16:59 PM PDT 24
Finished Jun 29 06:17:01 PM PDT 24
Peak memory 196568 kb
Host smart-e04f1cfe-2da3-4cd1-aebc-4c0cebfd60fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477478819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.477478819
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3887159486
Short name T49
Test name
Test status
Simulation time 457992290 ps
CPU time 0.77 seconds
Started Jun 29 06:17:13 PM PDT 24
Finished Jun 29 06:17:14 PM PDT 24
Peak memory 196444 kb
Host smart-106d3e34-e4c5-4bf5-878c-f8a485c55376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887159486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3887159486
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2245397391
Short name T180
Test name
Test status
Simulation time 464566202 ps
CPU time 1.14 seconds
Started Jun 29 06:17:13 PM PDT 24
Finished Jun 29 06:17:15 PM PDT 24
Peak memory 196456 kb
Host smart-ffdd7df6-61cb-4cf3-9cfe-6ef7ad8cb652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245397391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2245397391
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.382150448
Short name T175
Test name
Test status
Simulation time 410738279 ps
CPU time 1.16 seconds
Started Jun 29 06:17:14 PM PDT 24
Finished Jun 29 06:17:16 PM PDT 24
Peak memory 196424 kb
Host smart-2ce688b5-5aa1-4812-9c71-ba8e65469878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382150448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.382150448
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3840533781
Short name T186
Test name
Test status
Simulation time 217646012100 ps
CPU time 281.47 seconds
Started Jun 29 06:17:22 PM PDT 24
Finished Jun 29 06:22:04 PM PDT 24
Peak memory 192524 kb
Host smart-7fd971bb-0b0f-447d-a683-5d711c9c725f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840533781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3840533781
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2344965897
Short name T12
Test name
Test status
Simulation time 433570688 ps
CPU time 0.68 seconds
Started Jun 29 06:16:28 PM PDT 24
Finished Jun 29 06:16:30 PM PDT 24
Peak memory 196452 kb
Host smart-da12bdb8-986a-4465-8d55-2c574f411516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344965897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2344965897
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3950113089
Short name T406
Test name
Test status
Simulation time 7299831317 ps
CPU time 9.94 seconds
Started Jun 29 05:17:11 PM PDT 24
Finished Jun 29 05:17:21 PM PDT 24
Peak memory 192268 kb
Host smart-b83fa2b6-273c-42e4-9fa8-6a8809712f78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950113089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3950113089
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3840407921
Short name T52
Test name
Test status
Simulation time 1060070274 ps
CPU time 1.93 seconds
Started Jun 29 05:17:07 PM PDT 24
Finished Jun 29 05:17:09 PM PDT 24
Peak memory 193304 kb
Host smart-1588f88f-b772-4bc4-8780-25a137e30d19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840407921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3840407921
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.991110582
Short name T308
Test name
Test status
Simulation time 611513868 ps
CPU time 1.42 seconds
Started Jun 29 05:17:07 PM PDT 24
Finished Jun 29 05:17:09 PM PDT 24
Peak memory 198544 kb
Host smart-632c33ba-801b-49b2-aa57-f43d6377220d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991110582 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.991110582
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4245583342
Short name T65
Test name
Test status
Simulation time 297151452 ps
CPU time 1.08 seconds
Started Jun 29 05:17:08 PM PDT 24
Finished Jun 29 05:17:10 PM PDT 24
Peak memory 193036 kb
Host smart-b1ea91f5-c5e4-4149-8aef-a9bf0d10b599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245583342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.4245583342
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1201694035
Short name T309
Test name
Test status
Simulation time 402413094 ps
CPU time 0.72 seconds
Started Jun 29 05:17:11 PM PDT 24
Finished Jun 29 05:17:12 PM PDT 24
Peak memory 183824 kb
Host smart-b78e1dae-bf1a-4fa7-9815-31cc1b69c22d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201694035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1201694035
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2459865314
Short name T331
Test name
Test status
Simulation time 487119413 ps
CPU time 0.71 seconds
Started Jun 29 05:17:08 PM PDT 24
Finished Jun 29 05:17:09 PM PDT 24
Peak memory 183752 kb
Host smart-037207e9-1fd9-49bc-a443-7802436484e5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459865314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2459865314
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1883467275
Short name T344
Test name
Test status
Simulation time 364843478 ps
CPU time 0.96 seconds
Started Jun 29 05:17:08 PM PDT 24
Finished Jun 29 05:17:10 PM PDT 24
Peak memory 183744 kb
Host smart-a4256dd3-3f90-4e3f-9306-3a6029c0c8c9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883467275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1883467275
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.411623798
Short name T371
Test name
Test status
Simulation time 2233977146 ps
CPU time 4.57 seconds
Started Jun 29 05:17:07 PM PDT 24
Finished Jun 29 05:17:13 PM PDT 24
Peak memory 193952 kb
Host smart-db92f662-82e8-44da-a039-8ca5b89dbf8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411623798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.411623798
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4079440548
Short name T325
Test name
Test status
Simulation time 473890685 ps
CPU time 1.4 seconds
Started Jun 29 05:17:11 PM PDT 24
Finished Jun 29 05:17:12 PM PDT 24
Peak memory 198536 kb
Host smart-c9a59262-4761-4321-8943-9e5632be8ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079440548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.4079440548
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4103346581
Short name T420
Test name
Test status
Simulation time 4074957876 ps
CPU time 2.49 seconds
Started Jun 29 05:17:08 PM PDT 24
Finished Jun 29 05:17:11 PM PDT 24
Peak memory 197764 kb
Host smart-f5fbf980-ef6e-41e0-9ded-40a122356d86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103346581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.4103346581
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2181474257
Short name T57
Test name
Test status
Simulation time 617924919 ps
CPU time 1.68 seconds
Started Jun 29 05:17:10 PM PDT 24
Finished Jun 29 05:17:12 PM PDT 24
Peak memory 194448 kb
Host smart-4667114a-c189-4d18-9963-84cd14373d6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181474257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2181474257
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1193618835
Short name T202
Test name
Test status
Simulation time 7204975818 ps
CPU time 5.28 seconds
Started Jun 29 05:17:11 PM PDT 24
Finished Jun 29 05:17:17 PM PDT 24
Peak memory 192132 kb
Host smart-65747e9f-7ffa-4a4e-b648-e7be0252e8b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193618835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1193618835
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3118046268
Short name T56
Test name
Test status
Simulation time 651167173 ps
CPU time 1.49 seconds
Started Jun 29 05:17:07 PM PDT 24
Finished Jun 29 05:17:09 PM PDT 24
Peak memory 193032 kb
Host smart-89cb9a27-b357-4f54-a139-c6eb2e383228
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118046268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3118046268
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2645109287
Short name T393
Test name
Test status
Simulation time 520890102 ps
CPU time 1.01 seconds
Started Jun 29 05:17:09 PM PDT 24
Finished Jun 29 05:17:11 PM PDT 24
Peak memory 195860 kb
Host smart-5c340aa6-7a80-4bd5-8a90-936f3edc57f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645109287 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2645109287
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.912238988
Short name T334
Test name
Test status
Simulation time 301315682 ps
CPU time 0.77 seconds
Started Jun 29 05:17:08 PM PDT 24
Finished Jun 29 05:17:10 PM PDT 24
Peak memory 193020 kb
Host smart-b39b3f95-3045-47a4-9f1a-7b57f8fba086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912238988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.912238988
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2940836618
Short name T314
Test name
Test status
Simulation time 475554213 ps
CPU time 0.6 seconds
Started Jun 29 05:17:09 PM PDT 24
Finished Jun 29 05:17:11 PM PDT 24
Peak memory 183752 kb
Host smart-efff9259-316c-4d80-88a9-103a52456f99
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940836618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2940836618
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1197097247
Short name T368
Test name
Test status
Simulation time 467431165 ps
CPU time 0.93 seconds
Started Jun 29 05:17:08 PM PDT 24
Finished Jun 29 05:17:10 PM PDT 24
Peak memory 183744 kb
Host smart-c58926ef-614f-4386-83fa-2a4ea5fca58b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197097247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1197097247
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2541974627
Short name T374
Test name
Test status
Simulation time 2301002556 ps
CPU time 1.53 seconds
Started Jun 29 05:17:10 PM PDT 24
Finished Jun 29 05:17:12 PM PDT 24
Peak memory 192044 kb
Host smart-45cc7abf-c14a-4b96-9311-db034f3b8527
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541974627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2541974627
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2539725634
Short name T356
Test name
Test status
Simulation time 549563108 ps
CPU time 2.29 seconds
Started Jun 29 05:17:07 PM PDT 24
Finished Jun 29 05:17:10 PM PDT 24
Peak memory 198588 kb
Host smart-19da0bd8-e790-4b44-bd54-8c7c78ce168c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539725634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2539725634
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.301312036
Short name T339
Test name
Test status
Simulation time 9035581943 ps
CPU time 14.22 seconds
Started Jun 29 05:17:06 PM PDT 24
Finished Jun 29 05:17:21 PM PDT 24
Peak memory 198396 kb
Host smart-2aa7bc4f-cdd1-4446-b3db-35ac8d52bb1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301312036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.301312036
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1162228762
Short name T388
Test name
Test status
Simulation time 389127050 ps
CPU time 1.19 seconds
Started Jun 29 05:17:23 PM PDT 24
Finished Jun 29 05:17:24 PM PDT 24
Peak memory 197344 kb
Host smart-acfa8a9d-e667-4d17-930b-9d9c35aa7c5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162228762 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1162228762
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3805658936
Short name T55
Test name
Test status
Simulation time 427345368 ps
CPU time 0.92 seconds
Started Jun 29 05:17:40 PM PDT 24
Finished Jun 29 05:17:42 PM PDT 24
Peak memory 193316 kb
Host smart-8727b041-0a4d-42b1-b6b3-ef6c248276df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805658936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3805658936
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2683923680
Short name T394
Test name
Test status
Simulation time 505454384 ps
CPU time 0.91 seconds
Started Jun 29 05:17:23 PM PDT 24
Finished Jun 29 05:17:25 PM PDT 24
Peak memory 193052 kb
Host smart-56b4dc7e-4752-4ff4-8261-d3286b03e244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683923680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2683923680
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2621512953
Short name T380
Test name
Test status
Simulation time 905582505 ps
CPU time 1.66 seconds
Started Jun 29 05:17:36 PM PDT 24
Finished Jun 29 05:17:38 PM PDT 24
Peak memory 193036 kb
Host smart-c30fa8be-a0db-4e72-9e83-6d2dc5f7e6d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621512953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2621512953
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1503884709
Short name T365
Test name
Test status
Simulation time 538902175 ps
CPU time 2.08 seconds
Started Jun 29 05:17:27 PM PDT 24
Finished Jun 29 05:17:29 PM PDT 24
Peak memory 198580 kb
Host smart-7a5b86bc-4895-4208-9b3f-7d8133f1ccf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503884709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1503884709
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2836185511
Short name T351
Test name
Test status
Simulation time 368628455 ps
CPU time 1.04 seconds
Started Jun 29 05:17:26 PM PDT 24
Finished Jun 29 05:17:27 PM PDT 24
Peak memory 197412 kb
Host smart-6c1faffa-6962-4dde-81e5-36c9f09cdd76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836185511 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2836185511
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2323766985
Short name T403
Test name
Test status
Simulation time 513861753 ps
CPU time 1.08 seconds
Started Jun 29 05:17:25 PM PDT 24
Finished Jun 29 05:17:27 PM PDT 24
Peak memory 192096 kb
Host smart-f9d05efd-20aa-4658-af5c-49d8de80bb74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323766985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2323766985
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2625541178
Short name T329
Test name
Test status
Simulation time 432177622 ps
CPU time 1.26 seconds
Started Jun 29 05:17:26 PM PDT 24
Finished Jun 29 05:17:28 PM PDT 24
Peak memory 183832 kb
Host smart-f07f9d96-1ac0-435f-b7b6-5b818eb5fa59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625541178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2625541178
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2748013827
Short name T404
Test name
Test status
Simulation time 1219509793 ps
CPU time 3.05 seconds
Started Jun 29 05:17:29 PM PDT 24
Finished Jun 29 05:17:32 PM PDT 24
Peak memory 193036 kb
Host smart-75d77669-958d-48ec-a475-3dc84acc3fab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748013827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2748013827
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2237103251
Short name T319
Test name
Test status
Simulation time 644968642 ps
CPU time 1.54 seconds
Started Jun 29 05:17:24 PM PDT 24
Finished Jun 29 05:17:26 PM PDT 24
Peak memory 198632 kb
Host smart-815df1c3-f02d-41a8-aa76-1b2ae817f7f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237103251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2237103251
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.70500499
Short name T201
Test name
Test status
Simulation time 8362358338 ps
CPU time 10.99 seconds
Started Jun 29 05:17:26 PM PDT 24
Finished Jun 29 05:17:38 PM PDT 24
Peak memory 198232 kb
Host smart-841e202d-094c-4731-bddd-6cdf8bb91c20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70500499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_
intg_err.70500499
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4076153397
Short name T318
Test name
Test status
Simulation time 566217240 ps
CPU time 1.5 seconds
Started Jun 29 05:17:36 PM PDT 24
Finished Jun 29 05:17:38 PM PDT 24
Peak memory 197232 kb
Host smart-f00158bf-db0f-449a-aef3-cf0d79dd04fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076153397 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.4076153397
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3010868833
Short name T390
Test name
Test status
Simulation time 387732893 ps
CPU time 0.71 seconds
Started Jun 29 05:17:36 PM PDT 24
Finished Jun 29 05:17:38 PM PDT 24
Peak memory 193024 kb
Host smart-466e4989-7223-4d3c-a68e-56610a74721b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010868833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3010868833
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3348194505
Short name T300
Test name
Test status
Simulation time 337293520 ps
CPU time 0.76 seconds
Started Jun 29 05:17:38 PM PDT 24
Finished Jun 29 05:17:40 PM PDT 24
Peak memory 193052 kb
Host smart-a782e6a5-0788-4359-9c14-f4c83a9d7723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348194505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3348194505
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1863225342
Short name T73
Test name
Test status
Simulation time 2501789532 ps
CPU time 3.13 seconds
Started Jun 29 05:17:37 PM PDT 24
Finished Jun 29 05:17:41 PM PDT 24
Peak memory 194512 kb
Host smart-9229dd77-f0cf-4b15-9459-a2803329d47d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863225342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1863225342
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.137446461
Short name T343
Test name
Test status
Simulation time 566368700 ps
CPU time 1.85 seconds
Started Jun 29 05:17:35 PM PDT 24
Finished Jun 29 05:17:38 PM PDT 24
Peak memory 198672 kb
Host smart-298e5fd8-b632-4c7c-8977-2b3fafa5250b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137446461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.137446461
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1176257179
Short name T348
Test name
Test status
Simulation time 8779437547 ps
CPU time 4.86 seconds
Started Jun 29 05:17:25 PM PDT 24
Finished Jun 29 05:17:30 PM PDT 24
Peak memory 198300 kb
Host smart-7ec6e716-0766-4549-95f0-8ee8fd6a0ac7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176257179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1176257179
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2844200017
Short name T361
Test name
Test status
Simulation time 447102857 ps
CPU time 1.05 seconds
Started Jun 29 05:17:48 PM PDT 24
Finished Jun 29 05:17:49 PM PDT 24
Peak memory 196376 kb
Host smart-9843b9c8-2597-49e7-a549-869c490a892c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844200017 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2844200017
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3607027101
Short name T60
Test name
Test status
Simulation time 375687701 ps
CPU time 1.16 seconds
Started Jun 29 05:17:45 PM PDT 24
Finished Jun 29 05:17:47 PM PDT 24
Peak memory 193276 kb
Host smart-0688ea0b-9836-4dca-8f8b-d268072abc89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607027101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3607027101
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3133191362
Short name T409
Test name
Test status
Simulation time 372203775 ps
CPU time 0.61 seconds
Started Jun 29 05:17:38 PM PDT 24
Finished Jun 29 05:17:39 PM PDT 24
Peak memory 193052 kb
Host smart-dc19fb58-1fbc-49d3-9790-c341d1b46b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133191362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3133191362
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3299509661
Short name T75
Test name
Test status
Simulation time 1085777919 ps
CPU time 2.78 seconds
Started Jun 29 05:17:35 PM PDT 24
Finished Jun 29 05:17:38 PM PDT 24
Peak memory 192936 kb
Host smart-5e2cb5f1-8506-4f5f-a8b5-a10fab7343d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299509661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3299509661
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.372864586
Short name T376
Test name
Test status
Simulation time 843582677 ps
CPU time 1.69 seconds
Started Jun 29 05:17:37 PM PDT 24
Finished Jun 29 05:17:40 PM PDT 24
Peak memory 198656 kb
Host smart-a051e090-0f27-4746-99b7-5de07247ecb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372864586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.372864586
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.365944567
Short name T373
Test name
Test status
Simulation time 4070138496 ps
CPU time 6.72 seconds
Started Jun 29 05:17:36 PM PDT 24
Finished Jun 29 05:17:43 PM PDT 24
Peak memory 196696 kb
Host smart-7a56744b-d9a0-40a4-ab59-a84a10bba1df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365944567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.365944567
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1445511263
Short name T35
Test name
Test status
Simulation time 424449694 ps
CPU time 1.05 seconds
Started Jun 29 05:17:37 PM PDT 24
Finished Jun 29 05:17:39 PM PDT 24
Peak memory 198448 kb
Host smart-880fe16e-0926-427b-8bbe-deb0e258e1a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445511263 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1445511263
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3198426569
Short name T421
Test name
Test status
Simulation time 331769683 ps
CPU time 1.04 seconds
Started Jun 29 05:17:37 PM PDT 24
Finished Jun 29 05:17:39 PM PDT 24
Peak memory 192272 kb
Host smart-d803e460-8284-48ef-b3c1-f1017c2fe070
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198426569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3198426569
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.788024172
Short name T297
Test name
Test status
Simulation time 409434694 ps
CPU time 1.18 seconds
Started Jun 29 05:17:36 PM PDT 24
Finished Jun 29 05:17:38 PM PDT 24
Peak memory 193052 kb
Host smart-4d00fd46-2c0e-4fce-9fd0-51b74e0340b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788024172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.788024172
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2195736536
Short name T69
Test name
Test status
Simulation time 2570200547 ps
CPU time 3.49 seconds
Started Jun 29 05:17:45 PM PDT 24
Finished Jun 29 05:17:49 PM PDT 24
Peak memory 195436 kb
Host smart-6027dc8b-bcd9-49b6-9d33-84c37aeb8689
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195736536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2195736536
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2313161393
Short name T287
Test name
Test status
Simulation time 518553417 ps
CPU time 2.69 seconds
Started Jun 29 05:17:37 PM PDT 24
Finished Jun 29 05:17:41 PM PDT 24
Peak memory 198684 kb
Host smart-c48f998e-77eb-47f0-80f8-1bcffb459fa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313161393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2313161393
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.180514744
Short name T372
Test name
Test status
Simulation time 546803784 ps
CPU time 0.97 seconds
Started Jun 29 05:17:45 PM PDT 24
Finished Jun 29 05:17:47 PM PDT 24
Peak memory 197348 kb
Host smart-ae18ba97-a0c0-4499-bebe-a14abb3caf60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180514744 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.180514744
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1712840165
Short name T74
Test name
Test status
Simulation time 489519709 ps
CPU time 1.41 seconds
Started Jun 29 05:17:47 PM PDT 24
Finished Jun 29 05:17:49 PM PDT 24
Peak memory 194060 kb
Host smart-f07cef01-4150-44ac-819c-e380e8162fb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712840165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1712840165
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3509785060
Short name T399
Test name
Test status
Simulation time 499689889 ps
CPU time 0.72 seconds
Started Jun 29 05:17:37 PM PDT 24
Finished Jun 29 05:17:39 PM PDT 24
Peak memory 183832 kb
Host smart-88a4c290-209a-4d6e-a32d-a20b80b98b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509785060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3509785060
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4256503837
Short name T68
Test name
Test status
Simulation time 3180154649 ps
CPU time 1.87 seconds
Started Jun 29 05:17:38 PM PDT 24
Finished Jun 29 05:17:41 PM PDT 24
Peak memory 192088 kb
Host smart-4f1d4062-ad1d-48f3-a8b5-0a00ef803be2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256503837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.4256503837
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3977921262
Short name T410
Test name
Test status
Simulation time 1778508478 ps
CPU time 1.94 seconds
Started Jun 29 05:17:41 PM PDT 24
Finished Jun 29 05:17:44 PM PDT 24
Peak memory 198660 kb
Host smart-2c5a7cdf-49a7-46a7-b282-c1e4be0ea112
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977921262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3977921262
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2358540439
Short name T323
Test name
Test status
Simulation time 4431328279 ps
CPU time 7.67 seconds
Started Jun 29 05:17:38 PM PDT 24
Finished Jun 29 05:17:46 PM PDT 24
Peak memory 196632 kb
Host smart-ccfc372e-6769-45e6-acff-6156f6ff61f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358540439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2358540439
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3021922629
Short name T30
Test name
Test status
Simulation time 464507112 ps
CPU time 1.25 seconds
Started Jun 29 05:17:37 PM PDT 24
Finished Jun 29 05:17:40 PM PDT 24
Peak memory 196144 kb
Host smart-081b4d33-b885-4f69-a427-72190c2f6cb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021922629 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3021922629
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2369328954
Short name T67
Test name
Test status
Simulation time 436732634 ps
CPU time 0.74 seconds
Started Jun 29 05:17:40 PM PDT 24
Finished Jun 29 05:17:42 PM PDT 24
Peak memory 193040 kb
Host smart-d0da50db-bff2-4686-adf7-1f28ddf772d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369328954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2369328954
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3196001581
Short name T358
Test name
Test status
Simulation time 321691698 ps
CPU time 1.03 seconds
Started Jun 29 05:17:36 PM PDT 24
Finished Jun 29 05:17:37 PM PDT 24
Peak memory 183828 kb
Host smart-9e164a7c-2411-4163-abf5-7754d21d1e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196001581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3196001581
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.694728627
Short name T336
Test name
Test status
Simulation time 1228774585 ps
CPU time 2.13 seconds
Started Jun 29 05:17:37 PM PDT 24
Finished Jun 29 05:17:41 PM PDT 24
Peak memory 193036 kb
Host smart-55fe2b2c-319f-431a-85cb-6f40067828ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694728627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.694728627
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2990959800
Short name T324
Test name
Test status
Simulation time 338022625 ps
CPU time 1.48 seconds
Started Jun 29 05:17:41 PM PDT 24
Finished Jun 29 05:17:43 PM PDT 24
Peak memory 198480 kb
Host smart-2661c3a7-aa73-4638-8306-47d06e7d36fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990959800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2990959800
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3908300563
Short name T326
Test name
Test status
Simulation time 4311558368 ps
CPU time 5.42 seconds
Started Jun 29 05:17:41 PM PDT 24
Finished Jun 29 05:17:47 PM PDT 24
Peak memory 196972 kb
Host smart-c3f45629-f601-47f1-b0e3-ffa2e4a9dfbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908300563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3908300563
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3570398555
Short name T416
Test name
Test status
Simulation time 505239732 ps
CPU time 1.48 seconds
Started Jun 29 05:17:48 PM PDT 24
Finished Jun 29 05:17:50 PM PDT 24
Peak memory 196160 kb
Host smart-e528a654-a706-45f2-a72b-e36d98337543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570398555 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3570398555
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3859122935
Short name T415
Test name
Test status
Simulation time 431462873 ps
CPU time 1.33 seconds
Started Jun 29 05:17:48 PM PDT 24
Finished Jun 29 05:17:51 PM PDT 24
Peak memory 193196 kb
Host smart-3d2f8d15-fd24-4341-9235-c64f4e14cc67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859122935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3859122935
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2877009351
Short name T384
Test name
Test status
Simulation time 468821346 ps
CPU time 0.7 seconds
Started Jun 29 05:17:48 PM PDT 24
Finished Jun 29 05:17:49 PM PDT 24
Peak memory 193052 kb
Host smart-6a27f310-b067-4e74-a2eb-809737bd5cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877009351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2877009351
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1838815115
Short name T335
Test name
Test status
Simulation time 2109366562 ps
CPU time 2.99 seconds
Started Jun 29 05:17:41 PM PDT 24
Finished Jun 29 05:17:45 PM PDT 24
Peak memory 195364 kb
Host smart-feb4ca68-1293-405a-8646-6491a6722552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838815115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1838815115
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4249452443
Short name T292
Test name
Test status
Simulation time 584519473 ps
CPU time 2.77 seconds
Started Jun 29 05:17:39 PM PDT 24
Finished Jun 29 05:17:43 PM PDT 24
Peak memory 198700 kb
Host smart-3ab9eb0d-807a-479c-bab9-295861be9c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249452443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.4249452443
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3923378210
Short name T327
Test name
Test status
Simulation time 4360575325 ps
CPU time 7.3 seconds
Started Jun 29 05:17:43 PM PDT 24
Finished Jun 29 05:17:52 PM PDT 24
Peak memory 197764 kb
Host smart-0f341aae-6dc3-4700-bfb5-894b772452f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923378210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3923378210
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3314531048
Short name T395
Test name
Test status
Simulation time 557313099 ps
CPU time 1.27 seconds
Started Jun 29 05:17:43 PM PDT 24
Finished Jun 29 05:17:44 PM PDT 24
Peak memory 195900 kb
Host smart-00b3eb1d-b8e7-4d2e-9894-b0804e2d49fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314531048 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3314531048
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4139573021
Short name T66
Test name
Test status
Simulation time 385931624 ps
CPU time 0.69 seconds
Started Jun 29 05:17:39 PM PDT 24
Finished Jun 29 05:17:41 PM PDT 24
Peak memory 193004 kb
Host smart-2a000e5a-9231-4e80-a602-a210d70f1d5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139573021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.4139573021
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2118504652
Short name T389
Test name
Test status
Simulation time 407469454 ps
CPU time 0.96 seconds
Started Jun 29 05:17:39 PM PDT 24
Finished Jun 29 05:17:41 PM PDT 24
Peak memory 183832 kb
Host smart-075ce5b5-4f05-49ea-9ed9-b38260aac695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118504652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2118504652
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1047253115
Short name T71
Test name
Test status
Simulation time 2029113914 ps
CPU time 1.64 seconds
Started Jun 29 05:17:43 PM PDT 24
Finished Jun 29 05:17:46 PM PDT 24
Peak memory 193848 kb
Host smart-9aeee95a-8825-42f8-abc3-6cb6a9efed1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047253115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1047253115
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2697469721
Short name T322
Test name
Test status
Simulation time 402810140 ps
CPU time 1.89 seconds
Started Jun 29 05:17:48 PM PDT 24
Finished Jun 29 05:17:51 PM PDT 24
Peak memory 198560 kb
Host smart-7d1d73f4-0e82-4db5-bf89-c0cd04650e18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697469721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2697469721
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.278587948
Short name T383
Test name
Test status
Simulation time 8982171844 ps
CPU time 3.44 seconds
Started Jun 29 05:17:47 PM PDT 24
Finished Jun 29 05:17:51 PM PDT 24
Peak memory 198420 kb
Host smart-dbd992fc-1529-4449-8e70-6a9146475f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278587948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.278587948
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2563852534
Short name T363
Test name
Test status
Simulation time 442427738 ps
CPU time 1.26 seconds
Started Jun 29 05:17:44 PM PDT 24
Finished Jun 29 05:17:45 PM PDT 24
Peak memory 195728 kb
Host smart-a799a558-30e9-4141-ba8b-7048a776232a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563852534 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2563852534
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3494334439
Short name T58
Test name
Test status
Simulation time 500766330 ps
CPU time 0.91 seconds
Started Jun 29 05:17:48 PM PDT 24
Finished Jun 29 05:17:49 PM PDT 24
Peak memory 193524 kb
Host smart-8e77425e-5944-406d-a3ff-4b3d665e180b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494334439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3494334439
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3085995664
Short name T355
Test name
Test status
Simulation time 351350361 ps
CPU time 1.07 seconds
Started Jun 29 05:17:40 PM PDT 24
Finished Jun 29 05:17:42 PM PDT 24
Peak memory 183824 kb
Host smart-051e5d9c-2ed2-4d62-85cb-d8d8dce859b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085995664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3085995664
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2429746759
Short name T417
Test name
Test status
Simulation time 1072644635 ps
CPU time 2.05 seconds
Started Jun 29 05:17:40 PM PDT 24
Finished Jun 29 05:17:43 PM PDT 24
Peak memory 193744 kb
Host smart-9c92591a-41ff-4b0c-ab9b-b0637d990ad9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429746759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2429746759
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3597824079
Short name T387
Test name
Test status
Simulation time 478197518 ps
CPU time 2.11 seconds
Started Jun 29 05:17:41 PM PDT 24
Finished Jun 29 05:17:44 PM PDT 24
Peak memory 198684 kb
Host smart-7f982a5b-2403-4b1f-9602-39a61cc56076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597824079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3597824079
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.720826874
Short name T346
Test name
Test status
Simulation time 4547004042 ps
CPU time 1.74 seconds
Started Jun 29 05:17:40 PM PDT 24
Finished Jun 29 05:17:42 PM PDT 24
Peak memory 197944 kb
Host smart-7fc9fcac-ae1e-4dd2-9014-677fb41525c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720826874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.720826874
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1660305088
Short name T63
Test name
Test status
Simulation time 597757747 ps
CPU time 1.61 seconds
Started Jun 29 05:17:10 PM PDT 24
Finished Jun 29 05:17:12 PM PDT 24
Peak memory 183812 kb
Host smart-427ff082-1c03-46bc-9d06-489fc8d27a5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660305088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1660305088
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3478060601
Short name T64
Test name
Test status
Simulation time 6357398315 ps
CPU time 5.81 seconds
Started Jun 29 05:17:11 PM PDT 24
Finished Jun 29 05:17:17 PM PDT 24
Peak memory 192440 kb
Host smart-a8582d1c-b467-451a-987e-b89d08fe02cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478060601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3478060601
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4089087332
Short name T29
Test name
Test status
Simulation time 1011997713 ps
CPU time 1.92 seconds
Started Jun 29 05:17:07 PM PDT 24
Finished Jun 29 05:17:10 PM PDT 24
Peak memory 183712 kb
Host smart-ed2e1475-f4b2-4480-bcb7-51b2a86cfdc4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089087332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.4089087332
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.218057882
Short name T407
Test name
Test status
Simulation time 418927806 ps
CPU time 0.93 seconds
Started Jun 29 05:17:23 PM PDT 24
Finished Jun 29 05:17:24 PM PDT 24
Peak memory 195640 kb
Host smart-1dbc4b6b-986d-41ed-b1ac-d5d249f94c3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218057882 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.218057882
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1365132120
Short name T296
Test name
Test status
Simulation time 409750499 ps
CPU time 0.76 seconds
Started Jun 29 05:17:07 PM PDT 24
Finished Jun 29 05:17:09 PM PDT 24
Peak memory 193004 kb
Host smart-0b7e2ac8-56f1-4d81-8250-84b2aba907b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365132120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1365132120
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1897314462
Short name T342
Test name
Test status
Simulation time 425068550 ps
CPU time 0.71 seconds
Started Jun 29 05:17:08 PM PDT 24
Finished Jun 29 05:17:10 PM PDT 24
Peak memory 183824 kb
Host smart-babe1f57-02b8-4e9c-91a0-65f5f923e319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897314462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1897314462
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2864505220
Short name T391
Test name
Test status
Simulation time 520816383 ps
CPU time 0.84 seconds
Started Jun 29 05:17:09 PM PDT 24
Finished Jun 29 05:17:11 PM PDT 24
Peak memory 183720 kb
Host smart-eeb1f884-4857-4a68-b031-d0a23b0a6757
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864505220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2864505220
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2720962547
Short name T419
Test name
Test status
Simulation time 423524350 ps
CPU time 0.6 seconds
Started Jun 29 05:17:10 PM PDT 24
Finished Jun 29 05:17:11 PM PDT 24
Peak memory 183916 kb
Host smart-58c0c197-06de-4c92-9fbb-64f62eae5fb2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720962547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2720962547
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1991439881
Short name T359
Test name
Test status
Simulation time 2848911834 ps
CPU time 4.54 seconds
Started Jun 29 05:17:22 PM PDT 24
Finished Jun 29 05:17:27 PM PDT 24
Peak memory 193872 kb
Host smart-78f4bc64-5049-4a7b-ab9f-832e0368126b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991439881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1991439881
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1413515592
Short name T304
Test name
Test status
Simulation time 400247903 ps
CPU time 1.69 seconds
Started Jun 29 05:17:08 PM PDT 24
Finished Jun 29 05:17:11 PM PDT 24
Peak memory 198664 kb
Host smart-3d953442-dceb-4099-b847-0c0d278dc4b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413515592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1413515592
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2993269705
Short name T199
Test name
Test status
Simulation time 4805449707 ps
CPU time 1.69 seconds
Started Jun 29 05:17:08 PM PDT 24
Finished Jun 29 05:17:10 PM PDT 24
Peak memory 196848 kb
Host smart-d9a2ae7f-a027-49c4-99a0-6e899820a992
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993269705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2993269705
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1318937517
Short name T313
Test name
Test status
Simulation time 517812491 ps
CPU time 1.33 seconds
Started Jun 29 05:17:42 PM PDT 24
Finished Jun 29 05:17:44 PM PDT 24
Peak memory 192952 kb
Host smart-b4d9e950-60b4-4c9e-8c01-fa1b7677dee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318937517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1318937517
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1355692516
Short name T396
Test name
Test status
Simulation time 354685359 ps
CPU time 1.01 seconds
Started Jun 29 05:17:41 PM PDT 24
Finished Jun 29 05:17:43 PM PDT 24
Peak memory 183832 kb
Host smart-0ade0fbe-109c-4d5c-9ff8-6858883cb0d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355692516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1355692516
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3781825898
Short name T290
Test name
Test status
Simulation time 306773615 ps
CPU time 0.65 seconds
Started Jun 29 05:17:41 PM PDT 24
Finished Jun 29 05:17:42 PM PDT 24
Peak memory 183820 kb
Host smart-2e7cea80-fd24-4835-96cd-a6bef501d9d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781825898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3781825898
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1380048990
Short name T310
Test name
Test status
Simulation time 348340948 ps
CPU time 0.67 seconds
Started Jun 29 05:17:40 PM PDT 24
Finished Jun 29 05:17:41 PM PDT 24
Peak memory 183828 kb
Host smart-4987101c-a6e6-4970-b57e-ee027f99e87c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380048990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1380048990
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1486417215
Short name T311
Test name
Test status
Simulation time 401714573 ps
CPU time 0.67 seconds
Started Jun 29 05:17:40 PM PDT 24
Finished Jun 29 05:17:41 PM PDT 24
Peak memory 193052 kb
Host smart-763dd6cf-e249-46ee-aeb7-c6a2d3935146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486417215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1486417215
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2476503728
Short name T362
Test name
Test status
Simulation time 477622410 ps
CPU time 1.27 seconds
Started Jun 29 05:17:49 PM PDT 24
Finished Jun 29 05:17:51 PM PDT 24
Peak memory 183832 kb
Host smart-70357f29-a7c4-4a7b-ab10-14610c20864a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476503728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2476503728
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1932304577
Short name T320
Test name
Test status
Simulation time 492056741 ps
CPU time 1.13 seconds
Started Jun 29 05:17:48 PM PDT 24
Finished Jun 29 05:17:50 PM PDT 24
Peak memory 183808 kb
Host smart-58716fb9-de84-46e2-a122-b5654f09736c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932304577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1932304577
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1874486095
Short name T422
Test name
Test status
Simulation time 373796088 ps
CPU time 1.14 seconds
Started Jun 29 05:17:47 PM PDT 24
Finished Jun 29 05:17:49 PM PDT 24
Peak memory 193052 kb
Host smart-336b57b0-3690-4679-91b0-da9c5c4b8629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874486095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1874486095
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1894401982
Short name T340
Test name
Test status
Simulation time 388041654 ps
CPU time 1.02 seconds
Started Jun 29 05:17:49 PM PDT 24
Finished Jun 29 05:17:51 PM PDT 24
Peak memory 183832 kb
Host smart-92181c41-ef6c-4883-aaeb-f560fb888ba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894401982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1894401982
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2249880239
Short name T299
Test name
Test status
Simulation time 287224826 ps
CPU time 0.92 seconds
Started Jun 29 05:17:51 PM PDT 24
Finished Jun 29 05:17:52 PM PDT 24
Peak memory 183792 kb
Host smart-265ca2bb-bc48-46a2-9703-1fa7d9e2b6c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249880239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2249880239
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.211730653
Short name T62
Test name
Test status
Simulation time 474607506 ps
CPU time 1.28 seconds
Started Jun 29 05:17:18 PM PDT 24
Finished Jun 29 05:17:20 PM PDT 24
Peak memory 183804 kb
Host smart-16bdfeeb-c7a4-4cbf-ba25-6786bf06262c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211730653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.211730653
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3287010469
Short name T367
Test name
Test status
Simulation time 7035339622 ps
CPU time 15.08 seconds
Started Jun 29 05:17:17 PM PDT 24
Finished Jun 29 05:17:33 PM PDT 24
Peak memory 184068 kb
Host smart-7cb97fdb-c860-4e46-a5c0-e752a99c75c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287010469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3287010469
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1070611357
Short name T338
Test name
Test status
Simulation time 898018066 ps
CPU time 0.71 seconds
Started Jun 29 05:17:16 PM PDT 24
Finished Jun 29 05:17:17 PM PDT 24
Peak memory 193032 kb
Host smart-294d5385-b9ee-4cb2-b7aa-1bc5516e22ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070611357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1070611357
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1495538294
Short name T381
Test name
Test status
Simulation time 499369974 ps
CPU time 1.37 seconds
Started Jun 29 05:17:17 PM PDT 24
Finished Jun 29 05:17:19 PM PDT 24
Peak memory 195836 kb
Host smart-f5e5e221-d749-4e3b-a6cd-8aa3ae956bd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495538294 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1495538294
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2701045278
Short name T398
Test name
Test status
Simulation time 538657148 ps
CPU time 0.7 seconds
Started Jun 29 05:17:21 PM PDT 24
Finished Jun 29 05:17:22 PM PDT 24
Peak memory 192936 kb
Host smart-2dbaa010-ca03-49a0-bb40-30ddd60b6353
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701045278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2701045278
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4010785249
Short name T354
Test name
Test status
Simulation time 345249948 ps
CPU time 0.83 seconds
Started Jun 29 05:17:23 PM PDT 24
Finished Jun 29 05:17:24 PM PDT 24
Peak memory 183816 kb
Host smart-7872a3ef-f20b-400c-af90-915a291cae92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010785249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.4010785249
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.362900564
Short name T364
Test name
Test status
Simulation time 532175392 ps
CPU time 0.79 seconds
Started Jun 29 05:17:18 PM PDT 24
Finished Jun 29 05:17:19 PM PDT 24
Peak memory 183748 kb
Host smart-7d911124-7bca-483c-8cd4-17bdb54fe0e9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362900564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.362900564
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2157729447
Short name T295
Test name
Test status
Simulation time 426069325 ps
CPU time 0.67 seconds
Started Jun 29 05:17:18 PM PDT 24
Finished Jun 29 05:17:19 PM PDT 24
Peak memory 183744 kb
Host smart-f4316cd3-d7ee-43f9-b653-d9180b24c964
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157729447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2157729447
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1690689623
Short name T385
Test name
Test status
Simulation time 2481491981 ps
CPU time 2.34 seconds
Started Jun 29 05:17:17 PM PDT 24
Finished Jun 29 05:17:20 PM PDT 24
Peak memory 193880 kb
Host smart-2dd32ce4-d4e1-4931-a8a5-4a66eee23e67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690689623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1690689623
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2195436440
Short name T307
Test name
Test status
Simulation time 585122140 ps
CPU time 1.63 seconds
Started Jun 29 05:17:23 PM PDT 24
Finished Jun 29 05:17:24 PM PDT 24
Peak memory 198640 kb
Host smart-387a02f4-c282-423f-b4dd-724d01d3bc35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195436440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2195436440
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.889094364
Short name T352
Test name
Test status
Simulation time 8354197011 ps
CPU time 6.81 seconds
Started Jun 29 05:17:16 PM PDT 24
Finished Jun 29 05:17:23 PM PDT 24
Peak memory 198152 kb
Host smart-3fa7822a-e9a8-4c00-81b7-5140a68dafc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889094364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.889094364
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1206364837
Short name T301
Test name
Test status
Simulation time 336875536 ps
CPU time 0.68 seconds
Started Jun 29 05:17:48 PM PDT 24
Finished Jun 29 05:17:49 PM PDT 24
Peak memory 192944 kb
Host smart-4bbdf0df-e2b4-482b-9e0b-6be094a87e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206364837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1206364837
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1653241285
Short name T360
Test name
Test status
Simulation time 463182118 ps
CPU time 0.68 seconds
Started Jun 29 05:17:54 PM PDT 24
Finished Jun 29 05:17:55 PM PDT 24
Peak memory 183832 kb
Host smart-6e6691c7-a80b-422d-86b5-cbd226fc91ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653241285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1653241285
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2541861305
Short name T289
Test name
Test status
Simulation time 476075018 ps
CPU time 0.98 seconds
Started Jun 29 05:17:49 PM PDT 24
Finished Jun 29 05:17:51 PM PDT 24
Peak memory 192916 kb
Host smart-e21ee36c-6aa1-4ddb-9d88-b23fbaf3ce36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541861305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2541861305
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2651758359
Short name T379
Test name
Test status
Simulation time 283559288 ps
CPU time 0.98 seconds
Started Jun 29 05:17:50 PM PDT 24
Finished Jun 29 05:17:52 PM PDT 24
Peak memory 183728 kb
Host smart-24a01939-d2ca-47be-bdec-7a429e07c7d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651758359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2651758359
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1159676108
Short name T411
Test name
Test status
Simulation time 480724089 ps
CPU time 1.16 seconds
Started Jun 29 05:17:49 PM PDT 24
Finished Jun 29 05:17:51 PM PDT 24
Peak memory 183808 kb
Host smart-b5a06978-0742-4b57-8151-e42b3a15e251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159676108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1159676108
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3165000306
Short name T286
Test name
Test status
Simulation time 447759603 ps
CPU time 0.73 seconds
Started Jun 29 05:17:53 PM PDT 24
Finished Jun 29 05:17:54 PM PDT 24
Peak memory 183832 kb
Host smart-a551831c-f03a-4ba1-a5bd-aec55d97e4ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165000306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3165000306
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.4223578407
Short name T298
Test name
Test status
Simulation time 381673933 ps
CPU time 0.78 seconds
Started Jun 29 05:17:49 PM PDT 24
Finished Jun 29 05:17:51 PM PDT 24
Peak memory 193052 kb
Host smart-5350d80e-4519-42f1-a3b0-61f7ecbe0ffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223578407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.4223578407
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1258746637
Short name T400
Test name
Test status
Simulation time 468246698 ps
CPU time 1.09 seconds
Started Jun 29 05:17:47 PM PDT 24
Finished Jun 29 05:17:49 PM PDT 24
Peak memory 183728 kb
Host smart-d828f08b-e366-4c61-9cb3-2d12c431b6cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258746637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1258746637
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.366838992
Short name T386
Test name
Test status
Simulation time 375380649 ps
CPU time 0.84 seconds
Started Jun 29 05:17:50 PM PDT 24
Finished Jun 29 05:17:51 PM PDT 24
Peak memory 193020 kb
Host smart-e09201c5-19e8-4fac-9591-581b50883822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366838992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.366838992
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3505184906
Short name T350
Test name
Test status
Simulation time 360720296 ps
CPU time 0.68 seconds
Started Jun 29 05:17:48 PM PDT 24
Finished Jun 29 05:17:50 PM PDT 24
Peak memory 183832 kb
Host smart-01ccfd7d-410f-4b7f-9c67-6c1466b9d7f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505184906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3505184906
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2437070021
Short name T53
Test name
Test status
Simulation time 440949970 ps
CPU time 1.02 seconds
Started Jun 29 05:17:17 PM PDT 24
Finished Jun 29 05:17:18 PM PDT 24
Peak memory 193116 kb
Host smart-c8605b57-4278-4ef2-8ee3-d33368c06116
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437070021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2437070021
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2602208678
Short name T61
Test name
Test status
Simulation time 6909541377 ps
CPU time 10.92 seconds
Started Jun 29 05:17:16 PM PDT 24
Finished Jun 29 05:17:27 PM PDT 24
Peak memory 192240 kb
Host smart-7ef2681a-8c25-4c88-817a-0ecbe391b417
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602208678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2602208678
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3738395372
Short name T59
Test name
Test status
Simulation time 1047577418 ps
CPU time 1.33 seconds
Started Jun 29 05:17:16 PM PDT 24
Finished Jun 29 05:17:18 PM PDT 24
Peak memory 193200 kb
Host smart-987bf91b-2c2a-4fd3-96c6-db4c0289a4fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738395372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3738395372
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3155919320
Short name T34
Test name
Test status
Simulation time 358360695 ps
CPU time 0.84 seconds
Started Jun 29 05:17:17 PM PDT 24
Finished Jun 29 05:17:18 PM PDT 24
Peak memory 196312 kb
Host smart-cb931e12-688d-42ca-859a-eae74718f10e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155919320 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3155919320
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3086070177
Short name T423
Test name
Test status
Simulation time 475360866 ps
CPU time 0.86 seconds
Started Jun 29 05:17:18 PM PDT 24
Finished Jun 29 05:17:19 PM PDT 24
Peak memory 192088 kb
Host smart-34c51254-b1ad-4862-a711-f63ccf457c8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086070177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3086070177
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2287514182
Short name T315
Test name
Test status
Simulation time 434176932 ps
CPU time 0.84 seconds
Started Jun 29 05:17:23 PM PDT 24
Finished Jun 29 05:17:24 PM PDT 24
Peak memory 183816 kb
Host smart-e17ff2d4-605d-48bd-9818-d3c080681c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287514182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2287514182
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3060268580
Short name T337
Test name
Test status
Simulation time 433593191 ps
CPU time 0.64 seconds
Started Jun 29 05:17:18 PM PDT 24
Finished Jun 29 05:17:19 PM PDT 24
Peak memory 183752 kb
Host smart-6922c8dc-19c8-4277-aef7-bdab0f7a324d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060268580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3060268580
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1868085464
Short name T378
Test name
Test status
Simulation time 378189980 ps
CPU time 0.83 seconds
Started Jun 29 05:17:16 PM PDT 24
Finished Jun 29 05:17:17 PM PDT 24
Peak memory 183736 kb
Host smart-52a9a076-2479-44d8-911a-c6c57518d4d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868085464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1868085464
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1580796125
Short name T392
Test name
Test status
Simulation time 1528786652 ps
CPU time 0.85 seconds
Started Jun 29 05:17:18 PM PDT 24
Finished Jun 29 05:17:19 PM PDT 24
Peak memory 193036 kb
Host smart-3681cece-227a-44f2-83c0-6337a6b24e42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580796125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1580796125
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1457675663
Short name T412
Test name
Test status
Simulation time 522826439 ps
CPU time 2.25 seconds
Started Jun 29 05:17:15 PM PDT 24
Finished Jun 29 05:17:18 PM PDT 24
Peak memory 198668 kb
Host smart-25d98307-98f4-4082-87e0-05074cb0afe3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457675663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1457675663
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2655948314
Short name T317
Test name
Test status
Simulation time 4404715947 ps
CPU time 1.86 seconds
Started Jun 29 05:17:18 PM PDT 24
Finished Jun 29 05:17:20 PM PDT 24
Peak memory 196924 kb
Host smart-a3251e62-cbb0-4e43-b4ff-9b6546d49d90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655948314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2655948314
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.751858290
Short name T305
Test name
Test status
Simulation time 283805913 ps
CPU time 0.97 seconds
Started Jun 29 05:17:48 PM PDT 24
Finished Jun 29 05:17:49 PM PDT 24
Peak memory 183824 kb
Host smart-35929616-8563-4708-9f67-66ad5e519317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751858290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.751858290
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2165627734
Short name T294
Test name
Test status
Simulation time 426081001 ps
CPU time 0.69 seconds
Started Jun 29 05:17:48 PM PDT 24
Finished Jun 29 05:17:50 PM PDT 24
Peak memory 183800 kb
Host smart-7187f865-1584-454d-bab6-e814b12be708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165627734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2165627734
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3042652096
Short name T332
Test name
Test status
Simulation time 504298491 ps
CPU time 0.88 seconds
Started Jun 29 05:17:52 PM PDT 24
Finished Jun 29 05:17:53 PM PDT 24
Peak memory 193052 kb
Host smart-5a2e9874-689c-4312-9f4a-115aa33768f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042652096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3042652096
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2578028458
Short name T375
Test name
Test status
Simulation time 374371289 ps
CPU time 0.73 seconds
Started Jun 29 05:17:49 PM PDT 24
Finished Jun 29 05:17:50 PM PDT 24
Peak memory 183832 kb
Host smart-c0f70e4d-260e-4e22-bb88-915b2f41b210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578028458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2578028458
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.921872534
Short name T330
Test name
Test status
Simulation time 315433478 ps
CPU time 0.75 seconds
Started Jun 29 05:17:48 PM PDT 24
Finished Jun 29 05:17:49 PM PDT 24
Peak memory 192996 kb
Host smart-ce94f206-9607-43f5-8f67-bbfd5e8a9294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921872534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.921872534
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1668305500
Short name T316
Test name
Test status
Simulation time 422481511 ps
CPU time 0.81 seconds
Started Jun 29 05:17:49 PM PDT 24
Finished Jun 29 05:17:51 PM PDT 24
Peak memory 193040 kb
Host smart-a9fa9c0f-3eee-4389-b30f-4e01a6483de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668305500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1668305500
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.4051961969
Short name T328
Test name
Test status
Simulation time 300110302 ps
CPU time 0.66 seconds
Started Jun 29 05:17:50 PM PDT 24
Finished Jun 29 05:17:52 PM PDT 24
Peak memory 183800 kb
Host smart-78e5eac8-f96e-4e0f-b03e-8e68a6fc82d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051961969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.4051961969
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1034371436
Short name T397
Test name
Test status
Simulation time 418586414 ps
CPU time 1.15 seconds
Started Jun 29 05:17:51 PM PDT 24
Finished Jun 29 05:17:53 PM PDT 24
Peak memory 183832 kb
Host smart-e7f2f7ff-9414-4244-b319-20a651a50a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034371436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1034371436
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3029627585
Short name T293
Test name
Test status
Simulation time 468992608 ps
CPU time 0.9 seconds
Started Jun 29 05:17:52 PM PDT 24
Finished Jun 29 05:17:53 PM PDT 24
Peak memory 193052 kb
Host smart-994e29ca-12b4-4f1a-b9ef-5e6e820cf798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029627585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3029627585
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1481327864
Short name T321
Test name
Test status
Simulation time 297013754 ps
CPU time 0.81 seconds
Started Jun 29 05:17:50 PM PDT 24
Finished Jun 29 05:17:52 PM PDT 24
Peak memory 193224 kb
Host smart-0f332ed7-8824-46c2-8dd7-a54c58a2828f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481327864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1481327864
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1752690829
Short name T401
Test name
Test status
Simulation time 549693803 ps
CPU time 1 seconds
Started Jun 29 05:17:23 PM PDT 24
Finished Jun 29 05:17:25 PM PDT 24
Peak memory 198004 kb
Host smart-ce71f2c0-bba5-4797-86de-78c98b2350df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752690829 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1752690829
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2320708808
Short name T408
Test name
Test status
Simulation time 456587075 ps
CPU time 0.65 seconds
Started Jun 29 05:17:16 PM PDT 24
Finished Jun 29 05:17:18 PM PDT 24
Peak memory 193180 kb
Host smart-714d3cf3-4d95-43d2-ae0e-1c5df8b26e53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320708808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2320708808
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3107356507
Short name T349
Test name
Test status
Simulation time 474876178 ps
CPU time 0.57 seconds
Started Jun 29 05:17:19 PM PDT 24
Finished Jun 29 05:17:20 PM PDT 24
Peak memory 183756 kb
Host smart-80f0e5f3-b501-4b4f-935f-efcca10844b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107356507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3107356507
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3844098159
Short name T347
Test name
Test status
Simulation time 1315675333 ps
CPU time 1.01 seconds
Started Jun 29 05:17:18 PM PDT 24
Finished Jun 29 05:17:20 PM PDT 24
Peak memory 183952 kb
Host smart-99c18624-0c6a-42ec-9afb-534dbfb915ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844098159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3844098159
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2432711539
Short name T382
Test name
Test status
Simulation time 834943602 ps
CPU time 1.17 seconds
Started Jun 29 05:17:19 PM PDT 24
Finished Jun 29 05:17:21 PM PDT 24
Peak memory 198404 kb
Host smart-1d62eaf7-8404-4ff5-9a07-4aa06f4e039c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432711539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2432711539
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3242884994
Short name T370
Test name
Test status
Simulation time 8234644240 ps
CPU time 14.45 seconds
Started Jun 29 05:17:17 PM PDT 24
Finished Jun 29 05:17:32 PM PDT 24
Peak memory 198356 kb
Host smart-dbfde336-5b72-4ab3-bf34-180237b54b9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242884994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3242884994
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1884138329
Short name T377
Test name
Test status
Simulation time 335686981 ps
CPU time 1.2 seconds
Started Jun 29 05:17:25 PM PDT 24
Finished Jun 29 05:17:27 PM PDT 24
Peak memory 195588 kb
Host smart-c9aab14c-4b31-4201-88ae-126ee31f91aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884138329 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1884138329
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2527938981
Short name T88
Test name
Test status
Simulation time 310240259 ps
CPU time 0.82 seconds
Started Jun 29 05:17:35 PM PDT 24
Finished Jun 29 05:17:36 PM PDT 24
Peak memory 193036 kb
Host smart-9a089aac-e6f2-4861-a203-65d249e45c20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527938981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2527938981
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.206628827
Short name T288
Test name
Test status
Simulation time 458024153 ps
CPU time 0.7 seconds
Started Jun 29 05:17:36 PM PDT 24
Finished Jun 29 05:17:37 PM PDT 24
Peak memory 183788 kb
Host smart-40d1ae5e-c9bf-4760-9859-1d8a646b9ac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206628827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.206628827
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3331325277
Short name T72
Test name
Test status
Simulation time 1699057717 ps
CPU time 2.67 seconds
Started Jun 29 05:17:23 PM PDT 24
Finished Jun 29 05:17:27 PM PDT 24
Peak memory 193348 kb
Host smart-c89000c6-9553-4e3b-82cd-3707e31913da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331325277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3331325277
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2086077529
Short name T291
Test name
Test status
Simulation time 354229666 ps
CPU time 1.73 seconds
Started Jun 29 05:17:23 PM PDT 24
Finished Jun 29 05:17:25 PM PDT 24
Peak memory 198676 kb
Host smart-224b403a-c20c-4d7b-a4ed-08ebc7dc8d40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086077529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2086077529
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3780478505
Short name T200
Test name
Test status
Simulation time 8207806653 ps
CPU time 13.09 seconds
Started Jun 29 05:17:25 PM PDT 24
Finished Jun 29 05:17:38 PM PDT 24
Peak memory 198184 kb
Host smart-016dedd2-3eb8-4f64-a225-5f27cffa3b68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780478505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3780478505
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1663671738
Short name T357
Test name
Test status
Simulation time 652201800 ps
CPU time 1.22 seconds
Started Jun 29 05:17:26 PM PDT 24
Finished Jun 29 05:17:28 PM PDT 24
Peak memory 197316 kb
Host smart-22c9be63-f3bc-4ee1-b4f3-03f0eca7f860
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663671738 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1663671738
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1081239892
Short name T51
Test name
Test status
Simulation time 373660758 ps
CPU time 0.74 seconds
Started Jun 29 05:17:26 PM PDT 24
Finished Jun 29 05:17:27 PM PDT 24
Peak memory 194060 kb
Host smart-fe3d73a3-5790-4eed-80e2-04bd45fb0d3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081239892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1081239892
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1458203292
Short name T413
Test name
Test status
Simulation time 394162433 ps
CPU time 0.68 seconds
Started Jun 29 05:17:23 PM PDT 24
Finished Jun 29 05:17:25 PM PDT 24
Peak memory 183824 kb
Host smart-ae47ff35-a19d-4770-a19b-312652af16e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458203292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1458203292
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3595777336
Short name T345
Test name
Test status
Simulation time 2787662967 ps
CPU time 4.39 seconds
Started Jun 29 05:17:26 PM PDT 24
Finished Jun 29 05:17:31 PM PDT 24
Peak memory 184052 kb
Host smart-f8fa654d-d0be-4e69-ba2c-cf2f992dcc93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595777336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3595777336
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3127818210
Short name T302
Test name
Test status
Simulation time 366744126 ps
CPU time 2.19 seconds
Started Jun 29 05:17:24 PM PDT 24
Finished Jun 29 05:17:26 PM PDT 24
Peak memory 198604 kb
Host smart-1413c91d-6205-4857-9cb0-73b262e2d800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127818210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3127818210
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2179642873
Short name T32
Test name
Test status
Simulation time 8075378342 ps
CPU time 7.56 seconds
Started Jun 29 05:17:26 PM PDT 24
Finished Jun 29 05:17:34 PM PDT 24
Peak memory 197996 kb
Host smart-c5307739-1461-4ded-bebb-8e9cb91087d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179642873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2179642873
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1443930548
Short name T312
Test name
Test status
Simulation time 308124452 ps
CPU time 1.2 seconds
Started Jun 29 05:17:36 PM PDT 24
Finished Jun 29 05:17:38 PM PDT 24
Peak memory 196200 kb
Host smart-b136d0cc-819e-4a11-8010-b2cfaa9de213
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443930548 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1443930548
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.238812393
Short name T369
Test name
Test status
Simulation time 313582655 ps
CPU time 1.07 seconds
Started Jun 29 05:17:37 PM PDT 24
Finished Jun 29 05:17:39 PM PDT 24
Peak memory 194060 kb
Host smart-1e1a26a8-bc9d-4c38-9b87-03d44a33425a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238812393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.238812393
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3671228348
Short name T366
Test name
Test status
Simulation time 460882241 ps
CPU time 1.28 seconds
Started Jun 29 05:17:28 PM PDT 24
Finished Jun 29 05:17:30 PM PDT 24
Peak memory 183824 kb
Host smart-e9927e82-19ee-48a3-9258-00d6f9cc666b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671228348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3671228348
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3241723765
Short name T402
Test name
Test status
Simulation time 2162967168 ps
CPU time 2.33 seconds
Started Jun 29 05:17:37 PM PDT 24
Finished Jun 29 05:17:40 PM PDT 24
Peak memory 194208 kb
Host smart-8db3cf4f-f29f-4527-a90f-fae2b1782d2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241723765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3241723765
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1909117278
Short name T303
Test name
Test status
Simulation time 679639387 ps
CPU time 1.4 seconds
Started Jun 29 05:17:39 PM PDT 24
Finished Jun 29 05:17:41 PM PDT 24
Peak memory 198636 kb
Host smart-c5f8b9ac-d37a-4e79-a92b-fe9331452473
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909117278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1909117278
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.338199360
Short name T341
Test name
Test status
Simulation time 8122951368 ps
CPU time 4.26 seconds
Started Jun 29 05:17:25 PM PDT 24
Finished Jun 29 05:17:30 PM PDT 24
Peak memory 198148 kb
Host smart-2242c291-1ed4-46cf-803d-294cdf39dd8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338199360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.338199360
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.388127727
Short name T333
Test name
Test status
Simulation time 578528189 ps
CPU time 1.46 seconds
Started Jun 29 05:17:25 PM PDT 24
Finished Jun 29 05:17:27 PM PDT 24
Peak memory 196048 kb
Host smart-a45e42cc-37d6-4dba-9294-5d658858273e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388127727 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.388127727
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3326435275
Short name T418
Test name
Test status
Simulation time 577935266 ps
CPU time 0.74 seconds
Started Jun 29 05:17:24 PM PDT 24
Finished Jun 29 05:17:25 PM PDT 24
Peak memory 193324 kb
Host smart-7c5c405c-632c-443d-b945-4ba9db4eae22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326435275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3326435275
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3533260710
Short name T414
Test name
Test status
Simulation time 519816806 ps
CPU time 1.3 seconds
Started Jun 29 05:17:37 PM PDT 24
Finished Jun 29 05:17:39 PM PDT 24
Peak memory 193056 kb
Host smart-ba6f67ed-6c75-45a9-96a4-7b82be100745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533260710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3533260710
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1007149944
Short name T405
Test name
Test status
Simulation time 2581483072 ps
CPU time 2.4 seconds
Started Jun 29 05:17:28 PM PDT 24
Finished Jun 29 05:17:31 PM PDT 24
Peak memory 195296 kb
Host smart-891ea169-ec7e-43cc-942d-39a04b8b2643
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007149944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1007149944
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2804444101
Short name T306
Test name
Test status
Simulation time 865457561 ps
CPU time 1.53 seconds
Started Jun 29 05:17:36 PM PDT 24
Finished Jun 29 05:17:39 PM PDT 24
Peak memory 198572 kb
Host smart-f61bc0ca-f728-4e92-82ff-2dc64ac0dfd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804444101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2804444101
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3635976063
Short name T353
Test name
Test status
Simulation time 4238820156 ps
CPU time 4.07 seconds
Started Jun 29 05:17:25 PM PDT 24
Finished Jun 29 05:17:29 PM PDT 24
Peak memory 198156 kb
Host smart-007818e9-c861-429b-8c27-aa8e2a1c8763
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635976063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3635976063
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1599390178
Short name T223
Test name
Test status
Simulation time 38998700821 ps
CPU time 15.66 seconds
Started Jun 29 06:16:26 PM PDT 24
Finished Jun 29 06:16:42 PM PDT 24
Peak memory 191736 kb
Host smart-f13d3e9b-483c-4a4a-ae65-a69f104d85c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599390178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1599390178
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2947993869
Short name T231
Test name
Test status
Simulation time 370313603 ps
CPU time 0.73 seconds
Started Jun 29 06:16:22 PM PDT 24
Finished Jun 29 06:16:24 PM PDT 24
Peak memory 196532 kb
Host smart-d4c449da-7587-4bf9-9a2c-00eb616f6b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947993869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2947993869
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1352727414
Short name T230
Test name
Test status
Simulation time 26160390711 ps
CPU time 10.74 seconds
Started Jun 29 06:16:30 PM PDT 24
Finished Jun 29 06:16:42 PM PDT 24
Peak memory 196736 kb
Host smart-105af625-e685-491a-82e0-9becdcaced30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352727414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1352727414
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1564468196
Short name T16
Test name
Test status
Simulation time 7327133253 ps
CPU time 6.31 seconds
Started Jun 29 06:16:30 PM PDT 24
Finished Jun 29 06:16:37 PM PDT 24
Peak memory 215820 kb
Host smart-1d231bd3-2642-45a0-b0fd-9492176af70e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564468196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1564468196
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2401921984
Short name T240
Test name
Test status
Simulation time 372828884 ps
CPU time 1.15 seconds
Started Jun 29 06:16:28 PM PDT 24
Finished Jun 29 06:16:31 PM PDT 24
Peak memory 191664 kb
Host smart-1670c364-b2ff-435a-baf1-74f58f1b4aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401921984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2401921984
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4108378409
Short name T285
Test name
Test status
Simulation time 14828441166 ps
CPU time 19.24 seconds
Started Jun 29 06:16:35 PM PDT 24
Finished Jun 29 06:16:55 PM PDT 24
Peak memory 191688 kb
Host smart-a0ae7d70-ce5d-4ccb-a054-575b3d82a172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108378409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4108378409
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3626227508
Short name T216
Test name
Test status
Simulation time 417734573 ps
CPU time 1 seconds
Started Jun 29 06:16:36 PM PDT 24
Finished Jun 29 06:16:37 PM PDT 24
Peak memory 191644 kb
Host smart-28e4f031-4897-4bfc-9419-438971d3ddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626227508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3626227508
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2125337302
Short name T234
Test name
Test status
Simulation time 7525664453 ps
CPU time 6.35 seconds
Started Jun 29 06:16:36 PM PDT 24
Finished Jun 29 06:16:43 PM PDT 24
Peak memory 191732 kb
Host smart-326f5a48-d608-4551-8797-9833d27093f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125337302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2125337302
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2898176827
Short name T210
Test name
Test status
Simulation time 478214720 ps
CPU time 1.22 seconds
Started Jun 29 06:16:36 PM PDT 24
Finished Jun 29 06:16:38 PM PDT 24
Peak memory 191660 kb
Host smart-21cb9da0-f89c-442c-b289-10ddaf351b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898176827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2898176827
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2094488933
Short name T248
Test name
Test status
Simulation time 38886454520 ps
CPU time 13.06 seconds
Started Jun 29 06:16:35 PM PDT 24
Finished Jun 29 06:16:48 PM PDT 24
Peak memory 191640 kb
Host smart-463dd198-4e5b-42ff-8781-ea597e4dc91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094488933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2094488933
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2307235767
Short name T81
Test name
Test status
Simulation time 550400266 ps
CPU time 1.46 seconds
Started Jun 29 06:16:35 PM PDT 24
Finished Jun 29 06:16:37 PM PDT 24
Peak memory 196540 kb
Host smart-905c784f-5e5d-4fa4-9724-a200885193ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307235767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2307235767
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2894392919
Short name T130
Test name
Test status
Simulation time 497364786 ps
CPU time 0.79 seconds
Started Jun 29 06:16:35 PM PDT 24
Finished Jun 29 06:16:36 PM PDT 24
Peak memory 196480 kb
Host smart-acfde949-d6c9-4ac3-8100-599430a3387d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894392919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2894392919
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3797505207
Short name T225
Test name
Test status
Simulation time 18074116234 ps
CPU time 7.12 seconds
Started Jun 29 06:16:37 PM PDT 24
Finished Jun 29 06:16:45 PM PDT 24
Peak memory 196660 kb
Host smart-d8cc1502-01e8-4cdc-8974-7edfdf7ac0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797505207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3797505207
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1860450653
Short name T244
Test name
Test status
Simulation time 378325853 ps
CPU time 1.17 seconds
Started Jun 29 06:16:35 PM PDT 24
Finished Jun 29 06:16:36 PM PDT 24
Peak memory 191664 kb
Host smart-2cfec66b-7517-40d8-8ea7-9cfcff73b634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860450653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1860450653
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3924826978
Short name T196
Test name
Test status
Simulation time 486479237 ps
CPU time 1.23 seconds
Started Jun 29 06:16:37 PM PDT 24
Finished Jun 29 06:16:38 PM PDT 24
Peak memory 196516 kb
Host smart-63445dad-4758-4a4c-b9fa-183d207eb56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924826978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3924826978
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3362674258
Short name T78
Test name
Test status
Simulation time 31704119637 ps
CPU time 12.16 seconds
Started Jun 29 06:16:35 PM PDT 24
Finished Jun 29 06:16:48 PM PDT 24
Peak memory 196712 kb
Host smart-216c3523-d8b4-465c-b8d0-92fe21fed590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362674258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3362674258
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.484891742
Short name T42
Test name
Test status
Simulation time 417193483 ps
CPU time 1.21 seconds
Started Jun 29 06:16:35 PM PDT 24
Finished Jun 29 06:16:37 PM PDT 24
Peak memory 196484 kb
Host smart-b17f6c1d-8531-4ca1-b870-1c7c35abdf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484891742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.484891742
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.878985531
Short name T228
Test name
Test status
Simulation time 8524996374 ps
CPU time 12.47 seconds
Started Jun 29 06:16:36 PM PDT 24
Finished Jun 29 06:16:49 PM PDT 24
Peak memory 196720 kb
Host smart-6f5e176f-1743-4a68-9a2e-c841a38c59ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878985531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.878985531
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2182283034
Short name T222
Test name
Test status
Simulation time 447980597 ps
CPU time 0.66 seconds
Started Jun 29 06:16:39 PM PDT 24
Finished Jun 29 06:16:40 PM PDT 24
Peak memory 191664 kb
Host smart-a15f7039-8bc7-4e31-beee-8f52a9c89fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182283034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2182283034
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1165738258
Short name T211
Test name
Test status
Simulation time 17536861567 ps
CPU time 7.05 seconds
Started Jun 29 06:16:49 PM PDT 24
Finished Jun 29 06:16:57 PM PDT 24
Peak memory 191736 kb
Host smart-0ecc014c-a379-43ed-accf-affa6bed5d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165738258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1165738258
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2555185060
Short name T221
Test name
Test status
Simulation time 406743550 ps
CPU time 0.74 seconds
Started Jun 29 06:16:37 PM PDT 24
Finished Jun 29 06:16:39 PM PDT 24
Peak memory 191672 kb
Host smart-49f8cacd-fb9a-4b05-b290-c3701531a0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555185060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2555185060
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1314440318
Short name T283
Test name
Test status
Simulation time 14061362712 ps
CPU time 5.55 seconds
Started Jun 29 06:16:43 PM PDT 24
Finished Jun 29 06:16:50 PM PDT 24
Peak memory 196740 kb
Host smart-4bb45c9c-3b4c-4707-aa08-eaba74f26d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314440318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1314440318
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2025427864
Short name T203
Test name
Test status
Simulation time 525306904 ps
CPU time 1.06 seconds
Started Jun 29 06:16:55 PM PDT 24
Finished Jun 29 06:16:56 PM PDT 24
Peak memory 191668 kb
Host smart-a2a940a0-a69f-4ebf-9383-1e9dcc732984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025427864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2025427864
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1569956401
Short name T256
Test name
Test status
Simulation time 2863457211 ps
CPU time 5.33 seconds
Started Jun 29 06:16:42 PM PDT 24
Finished Jun 29 06:16:48 PM PDT 24
Peak memory 191732 kb
Host smart-0af1ff72-d643-4080-b011-40d8fe249194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569956401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1569956401
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3343961554
Short name T257
Test name
Test status
Simulation time 580177129 ps
CPU time 1.37 seconds
Started Jun 29 06:16:49 PM PDT 24
Finished Jun 29 06:16:51 PM PDT 24
Peak memory 191668 kb
Host smart-c10db856-8a1b-462a-ab38-4a86c9e1acb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343961554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3343961554
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1517775172
Short name T47
Test name
Test status
Simulation time 15101692373 ps
CPU time 11.61 seconds
Started Jun 29 06:16:44 PM PDT 24
Finished Jun 29 06:16:56 PM PDT 24
Peak memory 196664 kb
Host smart-d5916af1-b223-4e88-9e71-410c48dc66c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517775172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1517775172
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1544350437
Short name T259
Test name
Test status
Simulation time 380283398 ps
CPU time 0.83 seconds
Started Jun 29 06:16:46 PM PDT 24
Finished Jun 29 06:16:47 PM PDT 24
Peak memory 191660 kb
Host smart-a25de107-4a0f-49f7-9544-7b979e100fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544350437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1544350437
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2494986344
Short name T266
Test name
Test status
Simulation time 16264048792 ps
CPU time 6.9 seconds
Started Jun 29 06:16:26 PM PDT 24
Finished Jun 29 06:16:34 PM PDT 24
Peak memory 191740 kb
Host smart-55058b38-cd38-49ce-835d-77205bd9fb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494986344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2494986344
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.784181998
Short name T17
Test name
Test status
Simulation time 4256522684 ps
CPU time 7.47 seconds
Started Jun 29 06:16:28 PM PDT 24
Finished Jun 29 06:16:37 PM PDT 24
Peak memory 215348 kb
Host smart-6eaa2b6d-fe7d-4ff6-8487-0c14d4862d16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784181998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.784181998
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3803155379
Short name T282
Test name
Test status
Simulation time 558588024 ps
CPU time 1.41 seconds
Started Jun 29 06:16:32 PM PDT 24
Finished Jun 29 06:16:33 PM PDT 24
Peak memory 191380 kb
Host smart-a4a985c6-2058-4839-9522-87a1699488c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803155379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3803155379
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3546077177
Short name T247
Test name
Test status
Simulation time 6173045118 ps
CPU time 4.02 seconds
Started Jun 29 06:16:49 PM PDT 24
Finished Jun 29 06:16:54 PM PDT 24
Peak memory 191748 kb
Host smart-add01c58-e989-4a00-be4b-af3fd7f7a931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546077177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3546077177
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1150532159
Short name T262
Test name
Test status
Simulation time 498473164 ps
CPU time 0.67 seconds
Started Jun 29 06:16:44 PM PDT 24
Finished Jun 29 06:16:46 PM PDT 24
Peak memory 191672 kb
Host smart-2cc124b9-7fac-4382-8f6f-c845030a9164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150532159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1150532159
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2588379799
Short name T181
Test name
Test status
Simulation time 456215726 ps
CPU time 0.77 seconds
Started Jun 29 06:16:54 PM PDT 24
Finished Jun 29 06:16:55 PM PDT 24
Peak memory 196444 kb
Host smart-788901b0-c94c-4490-9a3d-99fb5dc6e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588379799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2588379799
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3674197094
Short name T45
Test name
Test status
Simulation time 34416900441 ps
CPU time 50.8 seconds
Started Jun 29 06:16:44 PM PDT 24
Finished Jun 29 06:17:36 PM PDT 24
Peak memory 196748 kb
Host smart-8e2ba182-fb13-4985-9237-fd3babfc8857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674197094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3674197094
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3153847623
Short name T207
Test name
Test status
Simulation time 460551220 ps
CPU time 1.27 seconds
Started Jun 29 06:16:44 PM PDT 24
Finished Jun 29 06:16:47 PM PDT 24
Peak memory 191668 kb
Host smart-8c4363a8-fac0-494b-9a9e-2ac327bcc57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153847623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3153847623
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_jump.492244324
Short name T185
Test name
Test status
Simulation time 480704589 ps
CPU time 1.32 seconds
Started Jun 29 06:16:45 PM PDT 24
Finished Jun 29 06:16:47 PM PDT 24
Peak memory 196524 kb
Host smart-076e5ba1-a293-4bfb-ab64-b9655bc94fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492244324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.492244324
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2238931594
Short name T241
Test name
Test status
Simulation time 2070376967 ps
CPU time 1.35 seconds
Started Jun 29 06:16:49 PM PDT 24
Finished Jun 29 06:16:51 PM PDT 24
Peak memory 191676 kb
Host smart-d9ebdc72-7acf-4db5-975c-bddce5aa8e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238931594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2238931594
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.4110450036
Short name T220
Test name
Test status
Simulation time 445054267 ps
CPU time 1.35 seconds
Started Jun 29 06:16:44 PM PDT 24
Finished Jun 29 06:16:46 PM PDT 24
Peak memory 196512 kb
Host smart-0b1b89ce-2460-482d-a268-453f666e63d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110450036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4110450036
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2861034705
Short name T284
Test name
Test status
Simulation time 25771019880 ps
CPU time 41.26 seconds
Started Jun 29 06:16:55 PM PDT 24
Finished Jun 29 06:17:37 PM PDT 24
Peak memory 191732 kb
Host smart-f9698d3f-3452-4727-b901-cbeee143f6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861034705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2861034705
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1228494354
Short name T209
Test name
Test status
Simulation time 504718401 ps
CPU time 1.33 seconds
Started Jun 29 06:16:53 PM PDT 24
Finished Jun 29 06:16:55 PM PDT 24
Peak memory 191668 kb
Host smart-b225dc8a-4d7b-453f-924d-29e36ba6f95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228494354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1228494354
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3416943996
Short name T268
Test name
Test status
Simulation time 4555994232 ps
CPU time 6.91 seconds
Started Jun 29 06:16:54 PM PDT 24
Finished Jun 29 06:17:01 PM PDT 24
Peak memory 191732 kb
Host smart-1ed06ea1-cc20-4bd2-a6f0-7f1d6cdf3f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416943996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3416943996
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.687886642
Short name T237
Test name
Test status
Simulation time 554370087 ps
CPU time 1.33 seconds
Started Jun 29 06:16:56 PM PDT 24
Finished Jun 29 06:16:57 PM PDT 24
Peak memory 191572 kb
Host smart-dc945937-ebc9-4a39-940d-ccbef354d5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687886642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.687886642
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.385039008
Short name T20
Test name
Test status
Simulation time 15159053992 ps
CPU time 11.03 seconds
Started Jun 29 06:16:55 PM PDT 24
Finished Jun 29 06:17:07 PM PDT 24
Peak memory 191712 kb
Host smart-d2bb6bc1-f8ec-4aaf-a18c-962006215a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385039008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.385039008
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4181601589
Short name T218
Test name
Test status
Simulation time 413401892 ps
CPU time 0.77 seconds
Started Jun 29 06:16:56 PM PDT 24
Finished Jun 29 06:16:57 PM PDT 24
Peak memory 191584 kb
Host smart-7c1c2e92-3918-479f-9c3b-f5c8a477d2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181601589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4181601589
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2689012623
Short name T271
Test name
Test status
Simulation time 48300997661 ps
CPU time 15.77 seconds
Started Jun 29 06:17:00 PM PDT 24
Finished Jun 29 06:17:16 PM PDT 24
Peak memory 196752 kb
Host smart-daccd5fc-56f4-470f-9912-0e078cc81fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689012623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2689012623
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1061035985
Short name T250
Test name
Test status
Simulation time 551161265 ps
CPU time 0.63 seconds
Started Jun 29 06:17:01 PM PDT 24
Finished Jun 29 06:17:02 PM PDT 24
Peak memory 196500 kb
Host smart-c542d8c9-6e47-408d-b69d-169e44b89d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061035985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1061035985
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.684945185
Short name T277
Test name
Test status
Simulation time 48238851627 ps
CPU time 18.6 seconds
Started Jun 29 06:16:59 PM PDT 24
Finished Jun 29 06:17:18 PM PDT 24
Peak memory 191740 kb
Host smart-659e78c4-632c-48a8-8888-6614cea056f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684945185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.684945185
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3652488028
Short name T21
Test name
Test status
Simulation time 528035401 ps
CPU time 1.4 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:17:08 PM PDT 24
Peak memory 191668 kb
Host smart-9705f43b-47fa-4f16-bb1c-2bdcfc942def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652488028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3652488028
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1738326283
Short name T50
Test name
Test status
Simulation time 1760326861 ps
CPU time 1.32 seconds
Started Jun 29 06:16:58 PM PDT 24
Finished Jun 29 06:16:59 PM PDT 24
Peak memory 191672 kb
Host smart-723698e1-4195-461d-b6bd-96a6a981003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738326283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1738326283
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1884283301
Short name T270
Test name
Test status
Simulation time 513878416 ps
CPU time 1.34 seconds
Started Jun 29 06:17:01 PM PDT 24
Finished Jun 29 06:17:03 PM PDT 24
Peak memory 191664 kb
Host smart-4de146e8-09a4-42a6-8be1-8c4a34833b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884283301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1884283301
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3426033546
Short name T212
Test name
Test status
Simulation time 13958028290 ps
CPU time 1.73 seconds
Started Jun 29 06:17:00 PM PDT 24
Finished Jun 29 06:17:02 PM PDT 24
Peak memory 196752 kb
Host smart-0ab268e3-1b49-4797-bf9b-5e029d0e29d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426033546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3426033546
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3842981955
Short name T263
Test name
Test status
Simulation time 464985271 ps
CPU time 0.75 seconds
Started Jun 29 06:17:01 PM PDT 24
Finished Jun 29 06:17:02 PM PDT 24
Peak memory 191880 kb
Host smart-70b68d53-69ed-4993-b0d8-41ae3c551ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842981955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3842981955
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.614656143
Short name T183
Test name
Test status
Simulation time 61831813210 ps
CPU time 134.94 seconds
Started Jun 29 06:17:01 PM PDT 24
Finished Jun 29 06:19:17 PM PDT 24
Peak memory 198432 kb
Host smart-365d05e1-119b-4a6e-b47a-c393041ecb45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614656143 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.614656143
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.4046147897
Short name T193
Test name
Test status
Simulation time 385340578 ps
CPU time 0.81 seconds
Started Jun 29 06:16:28 PM PDT 24
Finished Jun 29 06:16:29 PM PDT 24
Peak memory 196412 kb
Host smart-94c42356-d3e7-447c-8943-48437b260af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046147897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.4046147897
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3822287966
Short name T219
Test name
Test status
Simulation time 2853520909 ps
CPU time 1.27 seconds
Started Jun 29 06:16:28 PM PDT 24
Finished Jun 29 06:16:30 PM PDT 24
Peak memory 191636 kb
Host smart-e26cbf84-68cb-408f-92e6-b8708688a39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822287966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3822287966
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3948990556
Short name T18
Test name
Test status
Simulation time 7606768634 ps
CPU time 5.74 seconds
Started Jun 29 06:16:31 PM PDT 24
Finished Jun 29 06:16:38 PM PDT 24
Peak memory 215816 kb
Host smart-62d269a5-adc2-44fa-8d54-967d95810074
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948990556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3948990556
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.768612685
Short name T267
Test name
Test status
Simulation time 518499617 ps
CPU time 0.94 seconds
Started Jun 29 06:16:32 PM PDT 24
Finished Jun 29 06:16:33 PM PDT 24
Peak memory 196464 kb
Host smart-efd94a8e-4648-4529-92ed-ec98cb379682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768612685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.768612685
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2615177325
Short name T1
Test name
Test status
Simulation time 54446011238 ps
CPU time 42.93 seconds
Started Jun 29 06:17:01 PM PDT 24
Finished Jun 29 06:17:44 PM PDT 24
Peak memory 191732 kb
Host smart-50df8e86-ebf1-45e7-b710-3f1cb379494d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615177325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2615177325
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2966089593
Short name T274
Test name
Test status
Simulation time 534288194 ps
CPU time 0.77 seconds
Started Jun 29 06:16:58 PM PDT 24
Finished Jun 29 06:16:59 PM PDT 24
Peak memory 191668 kb
Host smart-3659a304-86a7-4163-8999-e61b5c9c954a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966089593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2966089593
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3382578708
Short name T191
Test name
Test status
Simulation time 440275218 ps
CPU time 1.26 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:17:08 PM PDT 24
Peak memory 196412 kb
Host smart-19bd27b1-a689-429d-9c13-f0a31c68603e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382578708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3382578708
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3627456568
Short name T280
Test name
Test status
Simulation time 27392745237 ps
CPU time 9.98 seconds
Started Jun 29 06:17:10 PM PDT 24
Finished Jun 29 06:17:20 PM PDT 24
Peak memory 196736 kb
Host smart-b7396023-3e5e-4b03-addc-60fc53973b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627456568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3627456568
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2630438390
Short name T213
Test name
Test status
Simulation time 571507798 ps
CPU time 1.01 seconds
Started Jun 29 06:17:08 PM PDT 24
Finished Jun 29 06:17:10 PM PDT 24
Peak memory 196472 kb
Host smart-d5ffc69f-6c7d-42d2-a0ce-b5845d97b8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630438390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2630438390
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.4155214611
Short name T251
Test name
Test status
Simulation time 15965687693 ps
CPU time 23.61 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:17:30 PM PDT 24
Peak memory 196656 kb
Host smart-8224847a-9f2b-4833-84a7-738c0158f436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155214611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.4155214611
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3768967641
Short name T22
Test name
Test status
Simulation time 540435704 ps
CPU time 0.97 seconds
Started Jun 29 06:17:05 PM PDT 24
Finished Jun 29 06:17:07 PM PDT 24
Peak memory 191672 kb
Host smart-223af8b5-e384-4d98-a3a6-6163a6cb5cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768967641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3768967641
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3721961542
Short name T10
Test name
Test status
Simulation time 16142944621 ps
CPU time 4.71 seconds
Started Jun 29 06:17:08 PM PDT 24
Finished Jun 29 06:17:14 PM PDT 24
Peak memory 191736 kb
Host smart-33693d73-65b2-41e2-82a6-e6d50bccfc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721961542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3721961542
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.4144896720
Short name T249
Test name
Test status
Simulation time 487920801 ps
CPU time 1.27 seconds
Started Jun 29 06:17:07 PM PDT 24
Finished Jun 29 06:17:09 PM PDT 24
Peak memory 191684 kb
Host smart-f2be2827-c447-4741-b986-7d32a27eb403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144896720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.4144896720
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3826066018
Short name T238
Test name
Test status
Simulation time 35892612314 ps
CPU time 12.3 seconds
Started Jun 29 06:17:07 PM PDT 24
Finished Jun 29 06:17:20 PM PDT 24
Peak memory 191732 kb
Host smart-0a70d651-b786-40fd-a592-d100523d318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826066018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3826066018
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2245781591
Short name T224
Test name
Test status
Simulation time 489017149 ps
CPU time 1.23 seconds
Started Jun 29 06:17:04 PM PDT 24
Finished Jun 29 06:17:06 PM PDT 24
Peak memory 196496 kb
Host smart-15842060-9252-43e8-841f-33e9fd4f5a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245781591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2245781591
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3212467184
Short name T242
Test name
Test status
Simulation time 20065173604 ps
CPU time 25.34 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:17:32 PM PDT 24
Peak memory 191716 kb
Host smart-3daf38cd-881f-4310-941d-964705ec954f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212467184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3212467184
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3494403984
Short name T278
Test name
Test status
Simulation time 516278085 ps
CPU time 0.65 seconds
Started Jun 29 06:17:07 PM PDT 24
Finished Jun 29 06:17:09 PM PDT 24
Peak memory 191668 kb
Host smart-853080e9-f4df-457c-ae8d-d4261f3b7dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494403984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3494403984
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2297544589
Short name T276
Test name
Test status
Simulation time 34094920763 ps
CPU time 12.63 seconds
Started Jun 29 06:17:07 PM PDT 24
Finished Jun 29 06:17:21 PM PDT 24
Peak memory 191708 kb
Host smart-ab655ecd-c64e-402d-8b6e-88d556f1fd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297544589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2297544589
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.4139409985
Short name T272
Test name
Test status
Simulation time 515024657 ps
CPU time 0.75 seconds
Started Jun 29 06:17:08 PM PDT 24
Finished Jun 29 06:17:10 PM PDT 24
Peak memory 191600 kb
Host smart-5bdbb928-cbcb-43d4-b9dd-3cf5aa5b6808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139409985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.4139409985
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2109784587
Short name T48
Test name
Test status
Simulation time 56368996896 ps
CPU time 18 seconds
Started Jun 29 06:17:08 PM PDT 24
Finished Jun 29 06:17:27 PM PDT 24
Peak memory 196752 kb
Host smart-af46e894-872e-4a5e-906c-e7efc6eb7190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109784587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2109784587
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.651455418
Short name T254
Test name
Test status
Simulation time 549536223 ps
CPU time 0.92 seconds
Started Jun 29 06:17:06 PM PDT 24
Finished Jun 29 06:17:08 PM PDT 24
Peak memory 196444 kb
Host smart-46566488-472e-4a88-9f70-1dcc6f665687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651455418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.651455418
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3432146986
Short name T187
Test name
Test status
Simulation time 491040726 ps
CPU time 0.75 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:17 PM PDT 24
Peak memory 196528 kb
Host smart-131ecc86-5465-4264-9bb2-5f2047e99950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432146986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3432146986
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1554502306
Short name T76
Test name
Test status
Simulation time 28872455759 ps
CPU time 11.6 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:27 PM PDT 24
Peak memory 191712 kb
Host smart-652e2537-758f-4488-9f5f-e9052d5cc894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554502306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1554502306
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3672610968
Short name T217
Test name
Test status
Simulation time 529204687 ps
CPU time 1.32 seconds
Started Jun 29 06:17:08 PM PDT 24
Finished Jun 29 06:17:10 PM PDT 24
Peak memory 196464 kb
Host smart-6f2de096-1f25-4692-81ae-70a23fce5fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672610968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3672610968
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1748374497
Short name T258
Test name
Test status
Simulation time 11249847925 ps
CPU time 16.93 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:32 PM PDT 24
Peak memory 191724 kb
Host smart-660a0344-de13-40da-80f5-84406e4b8c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748374497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1748374497
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.4218307400
Short name T265
Test name
Test status
Simulation time 500747279 ps
CPU time 1.3 seconds
Started Jun 29 06:17:14 PM PDT 24
Finished Jun 29 06:17:16 PM PDT 24
Peak memory 191668 kb
Host smart-31b5211f-9d65-45e4-bf93-a9f3333358df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218307400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.4218307400
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3570145495
Short name T44
Test name
Test status
Simulation time 18296562658 ps
CPU time 13.09 seconds
Started Jun 29 06:16:27 PM PDT 24
Finished Jun 29 06:16:40 PM PDT 24
Peak memory 196660 kb
Host smart-ad96b849-7841-4048-b1f6-e56cb849949e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570145495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3570145495
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2934741153
Short name T14
Test name
Test status
Simulation time 4762702397 ps
CPU time 1.13 seconds
Started Jun 29 06:16:27 PM PDT 24
Finished Jun 29 06:16:29 PM PDT 24
Peak memory 215668 kb
Host smart-bc82ed8a-aa0a-41ad-ae10-8c4b162a0f2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934741153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2934741153
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1567294270
Short name T229
Test name
Test status
Simulation time 492590629 ps
CPU time 0.76 seconds
Started Jun 29 06:16:28 PM PDT 24
Finished Jun 29 06:16:30 PM PDT 24
Peak memory 191656 kb
Host smart-9718c919-f255-4d1c-8d8d-1f0965e1d9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567294270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1567294270
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2942542148
Short name T215
Test name
Test status
Simulation time 25768152386 ps
CPU time 19.98 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:36 PM PDT 24
Peak memory 191736 kb
Host smart-d89ddf98-313e-4773-acd3-d728f4479aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942542148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2942542148
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.4185853677
Short name T253
Test name
Test status
Simulation time 563793826 ps
CPU time 0.8 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:16 PM PDT 24
Peak memory 196480 kb
Host smart-8fac243d-0101-4ff0-a092-d3342cd9a192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185853677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.4185853677
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3364707131
Short name T23
Test name
Test status
Simulation time 27802135175 ps
CPU time 11.42 seconds
Started Jun 29 06:17:19 PM PDT 24
Finished Jun 29 06:17:31 PM PDT 24
Peak memory 191732 kb
Host smart-d541d04b-b3cb-44fd-a59f-e391820733c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364707131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3364707131
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3664298052
Short name T260
Test name
Test status
Simulation time 530571974 ps
CPU time 1.3 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:17 PM PDT 24
Peak memory 191656 kb
Host smart-890c4362-28f2-40ae-8848-88021b7ee188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664298052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3664298052
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.447831904
Short name T239
Test name
Test status
Simulation time 2413605799 ps
CPU time 1.45 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:17 PM PDT 24
Peak memory 191724 kb
Host smart-3482cd4e-c882-4dce-bd00-62aaf0b8615a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447831904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.447831904
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3735771240
Short name T79
Test name
Test status
Simulation time 475840590 ps
CPU time 0.78 seconds
Started Jun 29 06:17:14 PM PDT 24
Finished Jun 29 06:17:15 PM PDT 24
Peak memory 196508 kb
Host smart-276c6a1b-5468-46b3-bcac-ae02747be130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735771240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3735771240
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2242932243
Short name T189
Test name
Test status
Simulation time 503668660 ps
CPU time 1.23 seconds
Started Jun 29 06:17:22 PM PDT 24
Finished Jun 29 06:17:23 PM PDT 24
Peak memory 196472 kb
Host smart-fe328d12-4ff6-41b1-899d-0fa4f98df654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242932243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2242932243
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.517936061
Short name T273
Test name
Test status
Simulation time 4399607362 ps
CPU time 6.26 seconds
Started Jun 29 06:17:14 PM PDT 24
Finished Jun 29 06:17:20 PM PDT 24
Peak memory 191740 kb
Host smart-e3ca98e9-3e43-44ac-95e5-27746f67515b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517936061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.517936061
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3590686263
Short name T269
Test name
Test status
Simulation time 596729330 ps
CPU time 1.37 seconds
Started Jun 29 06:17:16 PM PDT 24
Finished Jun 29 06:17:18 PM PDT 24
Peak memory 191668 kb
Host smart-da660b36-4a75-46c6-9531-7d07439da1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590686263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3590686263
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2765522306
Short name T226
Test name
Test status
Simulation time 15989963834 ps
CPU time 23.05 seconds
Started Jun 29 06:17:14 PM PDT 24
Finished Jun 29 06:17:38 PM PDT 24
Peak memory 196648 kb
Host smart-60804e7b-b5fd-413a-beb0-2e2fce78b106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765522306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2765522306
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.4086367071
Short name T243
Test name
Test status
Simulation time 369828887 ps
CPU time 1.1 seconds
Started Jun 29 06:17:14 PM PDT 24
Finished Jun 29 06:17:16 PM PDT 24
Peak memory 191652 kb
Host smart-9ac3be79-472a-4778-b0eb-85e06a6800fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086367071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.4086367071
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.70980432
Short name T255
Test name
Test status
Simulation time 27517273840 ps
CPU time 9.17 seconds
Started Jun 29 06:17:23 PM PDT 24
Finished Jun 29 06:17:32 PM PDT 24
Peak memory 191740 kb
Host smart-a13a429f-241d-4b69-b565-43f671b5c92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70980432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.70980432
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1662429289
Short name T204
Test name
Test status
Simulation time 553048147 ps
CPU time 1.34 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:17 PM PDT 24
Peak memory 191668 kb
Host smart-1f95bb18-479a-4eb8-b112-a25fe529263b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662429289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1662429289
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1758723764
Short name T43
Test name
Test status
Simulation time 8061053454 ps
CPU time 12.78 seconds
Started Jun 29 06:17:22 PM PDT 24
Finished Jun 29 06:17:35 PM PDT 24
Peak memory 191736 kb
Host smart-037f1886-feb3-4c81-b09b-62300b989733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758723764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1758723764
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1835026114
Short name T205
Test name
Test status
Simulation time 411034973 ps
CPU time 1.13 seconds
Started Jun 29 06:17:15 PM PDT 24
Finished Jun 29 06:17:17 PM PDT 24
Peak memory 191612 kb
Host smart-6c6de097-761f-410f-8a33-cce8394990c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835026114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1835026114
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1198916682
Short name T227
Test name
Test status
Simulation time 41431399817 ps
CPU time 20.51 seconds
Started Jun 29 06:17:26 PM PDT 24
Finished Jun 29 06:17:47 PM PDT 24
Peak memory 191736 kb
Host smart-430e760e-c208-4837-9b8e-ba54474fbfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198916682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1198916682
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3563176970
Short name T246
Test name
Test status
Simulation time 583392255 ps
CPU time 1.42 seconds
Started Jun 29 06:17:23 PM PDT 24
Finished Jun 29 06:17:25 PM PDT 24
Peak memory 191644 kb
Host smart-e7753f20-618a-49a5-9817-94f28210c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563176970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3563176970
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2909778313
Short name T198
Test name
Test status
Simulation time 497045479 ps
CPU time 0.93 seconds
Started Jun 29 06:17:23 PM PDT 24
Finished Jun 29 06:17:24 PM PDT 24
Peak memory 196540 kb
Host smart-5a69f1a2-82ac-4e6c-b758-feb51f9f9ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909778313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2909778313
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1866566903
Short name T252
Test name
Test status
Simulation time 28906089900 ps
CPU time 42.81 seconds
Started Jun 29 06:17:23 PM PDT 24
Finished Jun 29 06:18:06 PM PDT 24
Peak memory 191648 kb
Host smart-08adb047-c9ef-411a-b6da-70bedcf63e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866566903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1866566903
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2273094859
Short name T233
Test name
Test status
Simulation time 436136761 ps
CPU time 0.68 seconds
Started Jun 29 06:17:23 PM PDT 24
Finished Jun 29 06:17:24 PM PDT 24
Peak memory 191644 kb
Host smart-d884ab73-5b91-4b8c-a7b4-51540f2a5c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273094859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2273094859
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.4067529578
Short name T261
Test name
Test status
Simulation time 42006990485 ps
CPU time 7.44 seconds
Started Jun 29 06:17:25 PM PDT 24
Finished Jun 29 06:17:33 PM PDT 24
Peak memory 191736 kb
Host smart-0e3d59ff-ff76-4b4e-91c9-bd80f7c796be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067529578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.4067529578
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1431406229
Short name T245
Test name
Test status
Simulation time 489971275 ps
CPU time 1 seconds
Started Jun 29 06:17:24 PM PDT 24
Finished Jun 29 06:17:25 PM PDT 24
Peak memory 191664 kb
Host smart-05670d7e-4d41-40a6-b75d-f07d799a7618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431406229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1431406229
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.664465207
Short name T275
Test name
Test status
Simulation time 13823259695 ps
CPU time 20.41 seconds
Started Jun 29 06:16:30 PM PDT 24
Finished Jun 29 06:16:52 PM PDT 24
Peak memory 191716 kb
Host smart-c65720e1-629a-444f-9e46-85261ce0dd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664465207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.664465207
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.8480169
Short name T208
Test name
Test status
Simulation time 430946211 ps
CPU time 1.25 seconds
Started Jun 29 06:16:28 PM PDT 24
Finished Jun 29 06:16:30 PM PDT 24
Peak memory 196476 kb
Host smart-c1445573-22bb-4767-a26c-590eac2908c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8480169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.8480169
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3898946468
Short name T90
Test name
Test status
Simulation time 53282639109 ps
CPU time 111.75 seconds
Started Jun 29 06:16:29 PM PDT 24
Finished Jun 29 06:18:22 PM PDT 24
Peak memory 198472 kb
Host smart-1a4d3b5e-261f-4ed5-8c0f-eee82c094596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898946468 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3898946468
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.452885784
Short name T264
Test name
Test status
Simulation time 5366699107 ps
CPU time 4.85 seconds
Started Jun 29 06:16:27 PM PDT 24
Finished Jun 29 06:16:32 PM PDT 24
Peak memory 196700 kb
Host smart-d7d32873-07d8-4813-affa-8b5159cbb457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452885784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.452885784
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.27342268
Short name T279
Test name
Test status
Simulation time 516665009 ps
CPU time 0.76 seconds
Started Jun 29 06:16:28 PM PDT 24
Finished Jun 29 06:16:30 PM PDT 24
Peak memory 196500 kb
Host smart-aec1f577-ea5f-4e2e-bfe4-f46be5462d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27342268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.27342268
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2290590417
Short name T214
Test name
Test status
Simulation time 21967456245 ps
CPU time 8.26 seconds
Started Jun 29 06:16:30 PM PDT 24
Finished Jun 29 06:16:39 PM PDT 24
Peak memory 191664 kb
Host smart-68048186-9431-4e78-8faa-31391796cd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290590417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2290590417
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3348526091
Short name T206
Test name
Test status
Simulation time 423015482 ps
CPU time 0.76 seconds
Started Jun 29 06:16:29 PM PDT 24
Finished Jun 29 06:16:30 PM PDT 24
Peak memory 191660 kb
Host smart-c7a12d9b-2bf1-4ced-a44f-9107d62435ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348526091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3348526091
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2073534002
Short name T281
Test name
Test status
Simulation time 58278200237 ps
CPU time 90.91 seconds
Started Jun 29 06:16:29 PM PDT 24
Finished Jun 29 06:18:00 PM PDT 24
Peak memory 191632 kb
Host smart-819d0ba0-555f-41c0-be8f-6079fb5db5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073534002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2073534002
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.984458141
Short name T232
Test name
Test status
Simulation time 493592572 ps
CPU time 1.3 seconds
Started Jun 29 06:16:30 PM PDT 24
Finished Jun 29 06:16:32 PM PDT 24
Peak memory 191564 kb
Host smart-cd02df32-a731-4fef-9d6a-d7ca22d6bf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984458141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.984458141
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3958635873
Short name T236
Test name
Test status
Simulation time 38460298476 ps
CPU time 9.31 seconds
Started Jun 29 06:16:36 PM PDT 24
Finished Jun 29 06:16:46 PM PDT 24
Peak memory 196720 kb
Host smart-1ddfc0a3-3f60-439b-b313-73eaa24835a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958635873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3958635873
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2764690116
Short name T235
Test name
Test status
Simulation time 385807478 ps
CPU time 0.71 seconds
Started Jun 29 06:16:38 PM PDT 24
Finished Jun 29 06:16:39 PM PDT 24
Peak memory 191660 kb
Host smart-e3ed95b0-bfea-4fc3-93cc-ae92102aec9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764690116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2764690116
Directory /workspace/9.aon_timer_smoke/latest
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