Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	31944	1		T1	11		T2	361		T3	12
bark[1]	935	1		T18	21		T19	63		T134	14
bark[2]	1204	1		T2	285		T7	14		T9	21
bark[3]	526	1		T10	14		T34	21		T27	47
bark[4]	377	1		T112	14		T82	76		T48	21
bark[5]	264	1		T44	14		T89	14		T173	26
bark[6]	340	1		T12	7		T18	153		T47	21
bark[7]	396	1		T2	115		T47	21		T48	21
bark[8]	293	1		T27	38		T43	21		T171	14
bark[9]	664	1		T186	14		T129	21		T42	26
bark[10]	836	1		T12	31		T47	21		T42	128
bark[11]	548	1		T24	21		T172	14		T138	14
bark[12]	378	1		T9	26		T177	14		T189	14
bark[13]	722	1		T18	14		T111	77		T25	21
bark[14]	201	1		T103	30		T140	21		T142	101
bark[15]	269	1		T9	21		T19	14		T24	14
bark[16]	675	1		T34	7		T112	26		T121	21
bark[17]	1371	1		T31	14		T14	564		T191	14
bark[18]	357	1		T28	14		T42	79		T121	21
bark[19]	544	1		T111	42		T115	21		T45	220
bark[20]	648	1		T2	386		T139	14		T169	99
bark[21]	594	1		T47	21		T129	82		T103	21
bark[22]	589	1		T33	14		T27	146		T44	21
bark[23]	423	1		T34	21		T190	14		T131	21
bark[24]	356	1		T144	14		T82	143		T84	31
bark[25]	840	1		T42	45		T44	142		T45	200
bark[26]	194	1		T2	35		T113	84		T158	14
bark[27]	670	1		T9	42		T14	176		T28	21
bark[28]	619	1		T18	21		T47	30		T113	21
bark[29]	271	1		T46	14		T146	14		T101	21
bark[30]	354	1		T12	21		T14	26		T34	7
bark[31]	296	1		T8	14		T153	14		T121	39
bark_0	4822	1		T1	7		T2	89		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	32173	1		T1	10		T2	356		T3	11
bite[1]	290	1		T9	26		T44	21		T82	150
bite[2]	455	1		T9	21		T47	21		T170	13
bite[3]	195	1		T44	21		T84	26		T99	21
bite[4]	1139	1		T2	510		T111	21		T45	21
bite[5]	651	1		T111	76		T129	82		T112	21
bite[6]	443	1		T14	21		T113	21		T24	13
bite[7]	398	1		T12	6		T19	63		T114	35
bite[8]	662	1		T12	21		T129	21		T114	21
bite[9]	382	1		T2	35		T14	26		T27	47
bite[10]	292	1		T31	13		T114	42		T115	21
bite[11]	741	1		T2	151		T42	46		T121	21
bite[12]	566	1		T14	154		T18	13		T47	21
bite[13]	532	1		T47	30		T45	173		T145	26
bite[14]	691	1		T2	114		T33	13		T129	21
bite[15]	717	1		T9	42		T34	21		T47	21
bite[16]	570	1		T7	13		T186	13		T113	63
bite[17]	611	1		T8	13		T18	153		T28	21
bite[18]	687	1		T42	44		T171	13		T121	39
bite[19]	118	1		T18	21		T46	13		T42	21
bite[20]	592	1		T4	13		T113	21		T159	13
bite[21]	88	1		T112	13		T88	6		T166	13
bite[22]	262	1		T34	27		T27	37		T172	13
bite[23]	680	1		T2	6		T12	31		T34	21
bite[24]	642	1		T129	35		T42	78		T44	13
bite[25]	939	1		T9	21		T191	13		T153	13
bite[26]	220	1		T190	13		T146	13		T42	25
bite[27]	153	1		T143	21		T150	111		T109	21
bite[28]	641	1		T111	21		T28	13		T45	172
bite[29]	706	1		T14	563		T18	21		T19	13
bite[30]	539	1		T10	13		T47	21		T25	21
bite[31]	476	1		T34	6		T28	39		T115	21
bite_0	5269	1		T1	8		T2	99		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	53520	1		T1	18		T2	1271		T3	19

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	904	1		T198	9		T43	85		T44	9
prescale[1]	1007	1		T9	9		T18	37		T34	50
prescale[2]	689	1		T9	23		T112	37		T44	46
prescale[3]	1220	1		T2	19		T14	334		T25	140
prescale[4]	1074	1		T14	76		T18	71		T113	19
prescale[5]	1018	1		T111	33		T113	86		T44	171
prescale[6]	841	1		T14	19		T34	32		T41	49
prescale[7]	749	1		T2	19		T34	35		T24	19
prescale[8]	1006	1		T9	24		T14	33		T113	41
prescale[9]	938	1		T34	2		T22	9		T24	19
prescale[10]	893	1		T14	20		T199	9		T34	103
prescale[11]	458	1		T2	107		T24	19		T41	19
prescale[12]	760	1		T18	67		T34	19		T200	9
prescale[13]	1409	1		T2	44		T14	19		T34	88
prescale[14]	485	1		T2	79		T25	2		T44	40
prescale[15]	813	1		T2	2		T3	9		T14	19
prescale[16]	1155	1		T14	19		T18	19		T201	9
prescale[17]	832	1		T14	32		T25	2		T42	97
prescale[18]	796	1		T2	63		T19	37		T47	28
prescale[19]	1159	1		T2	2		T28	68		T42	44
prescale[20]	532	1		T2	28		T13	9		T14	40
prescale[21]	663	1		T44	19		T82	2		T168	45
prescale[22]	786	1		T9	19		T202	9		T42	20
prescale[23]	961	1		T12	2		T27	14		T41	27
prescale[24]	1073	1		T2	20		T111	35		T113	19
prescale[25]	640	1		T2	16		T12	16		T14	19
prescale[26]	650	1		T12	111		T24	59		T27	65
prescale[27]	497	1		T14	58		T42	2		T44	82
prescale[28]	960	1		T5	9		T18	24		T34	63
prescale[29]	639	1		T2	78		T14	9		T203	9
prescale[30]	906	1		T2	76		T12	2		T47	32
prescale[31]	682	1		T2	2		T14	40		T34	28
prescale_0	26325	1		T1	18		T2	716		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40431	1		T1	18		T2	1100		T3	9
auto[1]	13089	1		T2	171		T3	10		T4	12

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	53520	1		T1	18		T2	1271		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	31254	1		T1	13		T2	710		T3	14
wkup[1]	253	1		T2	21		T34	21		T28	21
wkup[2]	238	1		T41	26		T82	21		T84	21
wkup[3]	303	1		T34	8		T121	21		T44	29
wkup[4]	215	1		T34	30		T47	21		T101	21
wkup[5]	182	1		T33	15		T88	21		T145	26
wkup[6]	375	1		T14	21		T111	20		T42	8
wkup[7]	314	1		T2	60		T14	21		T18	21
wkup[8]	243	1		T24	21		T41	21		T42	60
wkup[9]	358	1		T2	35		T112	21		T42	21
wkup[10]	284	1		T27	26		T44	21		T101	21
wkup[11]	215	1		T25	21		T42	21		T44	21
wkup[12]	153	1		T158	15		T119	21		T134	15
wkup[13]	437	1		T2	26		T18	21		T177	15
wkup[14]	321	1		T47	30		T113	21		T45	30
wkup[15]	114	1		T9	21		T24	15		T85	15
wkup[16]	284	1		T112	45		T44	21		T45	42
wkup[17]	269	1		T42	21		T43	21		T44	21
wkup[18]	281	1		T2	14		T12	31		T14	21
wkup[19]	196	1		T144	15		T44	15		T57	21
wkup[20]	200	1		T2	21		T14	21		T34	21
wkup[21]	233	1		T2	26		T9	21		T84	21
wkup[22]	218	1		T2	21		T25	21		T114	35
wkup[23]	316	1		T114	21		T44	21		T45	30
wkup[24]	346	1		T14	21		T153	15		T25	21
wkup[25]	198	1		T12	21		T114	21		T82	21
wkup[26]	348	1		T12	30		T34	21		T170	15
wkup[27]	303	1		T19	21		T111	21		T114	21
wkup[28]	353	1		T2	15		T34	42		T186	15
wkup[29]	302	1		T2	21		T47	21		T45	21
wkup[30]	271	1		T34	8		T41	21		T45	42
wkup[31]	337	1		T2	21		T9	21		T14	21
wkup[32]	396	1		T9	21		T34	21		T111	21
wkup[33]	277	1		T42	21		T45	21		T82	8
wkup[34]	292	1		T10	15		T14	42		T190	15
wkup[35]	260	1		T2	68		T14	21		T88	21
wkup[36]	432	1		T44	21		T45	42		T86	21
wkup[37]	330	1		T47	38		T28	15		T45	21
wkup[38]	314	1		T113	21		T129	21		T121	21
wkup[39]	395	1		T4	15		T14	26		T24	21
wkup[40]	344	1		T12	8		T19	21		T27	21
wkup[41]	302	1		T14	35		T18	21		T44	21
wkup[42]	93	1		T2	21		T159	15		T44	21
wkup[43]	389	1		T34	21		T19	21		T27	21
wkup[44]	316	1		T2	30		T31	15		T25	21
wkup[45]	266	1		T2	21		T8	15		T129	21
wkup[46]	394	1		T2	21		T18	15		T34	26
wkup[47]	298	1		T18	21		T41	21		T44	21
wkup[48]	347	1		T14	21		T42	61		T44	21
wkup[49]	233	1		T12	21		T25	21		T28	21
wkup[50]	239	1		T113	21		T42	21		T43	21
wkup[51]	349	1		T14	21		T129	21		T112	26
wkup[52]	364	1		T2	21		T34	21		T44	63
wkup[53]	283	1		T14	26		T42	21		T44	21
wkup[54]	256	1		T2	26		T7	15		T14	21
wkup[55]	363	1		T14	21		T18	30		T47	21
wkup[56]	386	1		T19	15		T113	21		T45	30
wkup[57]	235	1		T191	15		T45	15		T82	31
wkup[58]	295	1		T9	21		T14	47		T27	21
wkup[59]	243	1		T46	15		T25	26		T119	21
wkup[60]	418	1		T2	8		T9	26		T146	15
wkup[61]	276	1		T114	21		T84	30		T101	21
wkup[62]	278	1		T34	42		T44	39		T45	21
wkup[63]	393	1		T129	21		T25	21		T41	21
wkup_0	3750	1		T1	5		T2	64		T3	5