Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.25 99.33 93.67 100.00 98.40 99.51 50.59


Total test records in report: 421
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T204 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2867403393 Jun 30 06:19:02 PM PDT 24 Jun 30 06:19:03 PM PDT 24 362331346 ps
T38 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.452565905 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:17 PM PDT 24 4328932145 ps
T283 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1488960861 Jun 30 06:19:13 PM PDT 24 Jun 30 06:19:15 PM PDT 24 328364896 ps
T284 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.186565993 Jun 30 06:19:04 PM PDT 24 Jun 30 06:19:06 PM PDT 24 639025208 ps
T39 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3331369698 Jun 30 06:19:12 PM PDT 24 Jun 30 06:19:18 PM PDT 24 8194550338 ps
T58 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3755853128 Jun 30 06:18:55 PM PDT 24 Jun 30 06:18:58 PM PDT 24 382338363 ps
T285 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2502667209 Jun 30 06:19:08 PM PDT 24 Jun 30 06:19:10 PM PDT 24 567570104 ps
T286 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.914666641 Jun 30 06:19:35 PM PDT 24 Jun 30 06:19:37 PM PDT 24 322009751 ps
T287 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2859071471 Jun 30 06:19:12 PM PDT 24 Jun 30 06:19:15 PM PDT 24 297800187 ps
T288 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3028400909 Jun 30 06:19:01 PM PDT 24 Jun 30 06:19:05 PM PDT 24 347359516 ps
T289 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3674059265 Jun 30 06:19:18 PM PDT 24 Jun 30 06:19:20 PM PDT 24 611732662 ps
T290 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3332364578 Jun 30 06:19:18 PM PDT 24 Jun 30 06:19:19 PM PDT 24 452625875 ps
T291 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1915030995 Jun 30 06:19:05 PM PDT 24 Jun 30 06:19:08 PM PDT 24 355986075 ps
T292 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3625875094 Jun 30 06:19:12 PM PDT 24 Jun 30 06:19:16 PM PDT 24 752144625 ps
T293 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3488122901 Jun 30 06:19:01 PM PDT 24 Jun 30 06:19:03 PM PDT 24 324320670 ps
T75 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3191478795 Jun 30 06:19:20 PM PDT 24 Jun 30 06:19:24 PM PDT 24 2461049627 ps
T294 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4226588333 Jun 30 06:19:35 PM PDT 24 Jun 30 06:19:39 PM PDT 24 389143833 ps
T295 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2880586230 Jun 30 06:19:37 PM PDT 24 Jun 30 06:19:41 PM PDT 24 298609580 ps
T296 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1435237848 Jun 30 06:19:08 PM PDT 24 Jun 30 06:19:15 PM PDT 24 4494686519 ps
T297 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2462800425 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:13 PM PDT 24 563568081 ps
T298 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4156305478 Jun 30 06:19:04 PM PDT 24 Jun 30 06:19:07 PM PDT 24 7287075246 ps
T59 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3327480784 Jun 30 06:19:12 PM PDT 24 Jun 30 06:19:14 PM PDT 24 517586972 ps
T193 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2229470944 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:04 PM PDT 24 8208593077 ps
T60 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3354226638 Jun 30 06:19:19 PM PDT 24 Jun 30 06:19:20 PM PDT 24 428128429 ps
T299 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.987789758 Jun 30 06:19:33 PM PDT 24 Jun 30 06:19:34 PM PDT 24 439456850 ps
T300 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1488461506 Jun 30 06:19:06 PM PDT 24 Jun 30 06:19:09 PM PDT 24 403526488 ps
T301 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1807845820 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:13 PM PDT 24 493439125 ps
T302 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3204838944 Jun 30 06:18:57 PM PDT 24 Jun 30 06:19:00 PM PDT 24 653572609 ps
T303 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3920608301 Jun 30 06:19:35 PM PDT 24 Jun 30 06:19:38 PM PDT 24 512485928 ps
T61 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3430858595 Jun 30 06:19:09 PM PDT 24 Jun 30 06:19:10 PM PDT 24 287430034 ps
T304 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1922379193 Jun 30 06:18:54 PM PDT 24 Jun 30 06:18:56 PM PDT 24 470316121 ps
T62 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1445033249 Jun 30 06:19:12 PM PDT 24 Jun 30 06:19:14 PM PDT 24 443865701 ps
T63 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.486708910 Jun 30 06:18:52 PM PDT 24 Jun 30 06:18:53 PM PDT 24 775463887 ps
T305 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1121425786 Jun 30 06:18:57 PM PDT 24 Jun 30 06:18:59 PM PDT 24 350336034 ps
T76 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3465914110 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:16 PM PDT 24 2171920615 ps
T306 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2554735082 Jun 30 06:19:08 PM PDT 24 Jun 30 06:19:10 PM PDT 24 393904301 ps
T307 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.931602669 Jun 30 06:19:05 PM PDT 24 Jun 30 06:19:08 PM PDT 24 632815150 ps
T308 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3648066858 Jun 30 06:19:33 PM PDT 24 Jun 30 06:19:35 PM PDT 24 429529765 ps
T309 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4028500263 Jun 30 06:19:39 PM PDT 24 Jun 30 06:19:44 PM PDT 24 460559894 ps
T77 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1757788172 Jun 30 06:19:37 PM PDT 24 Jun 30 06:19:42 PM PDT 24 1003155867 ps
T64 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2530454784 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:01 PM PDT 24 356294567 ps
T65 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1365304411 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:10 PM PDT 24 7013875874 ps
T78 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.668077341 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:02 PM PDT 24 1553580146 ps
T68 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1764751439 Jun 30 06:19:24 PM PDT 24 Jun 30 06:19:26 PM PDT 24 395910107 ps
T310 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.815366268 Jun 30 06:19:04 PM PDT 24 Jun 30 06:19:05 PM PDT 24 597971874 ps
T311 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1912924636 Jun 30 06:19:37 PM PDT 24 Jun 30 06:19:42 PM PDT 24 295765332 ps
T312 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1995559551 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:12 PM PDT 24 391986419 ps
T313 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.288292653 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:02 PM PDT 24 421820071 ps
T79 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1203350890 Jun 30 06:19:12 PM PDT 24 Jun 30 06:19:15 PM PDT 24 751589444 ps
T80 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3306850617 Jun 30 06:19:24 PM PDT 24 Jun 30 06:19:26 PM PDT 24 2871816210 ps
T314 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3593736653 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:13 PM PDT 24 396248584 ps
T81 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1611320861 Jun 30 06:19:14 PM PDT 24 Jun 30 06:19:17 PM PDT 24 925370044 ps
T315 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.455691895 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:40 PM PDT 24 342787938 ps
T316 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2482050242 Jun 30 06:19:04 PM PDT 24 Jun 30 06:19:07 PM PDT 24 302520035 ps
T317 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2881284492 Jun 30 06:19:13 PM PDT 24 Jun 30 06:19:15 PM PDT 24 497845642 ps
T194 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.180450312 Jun 30 06:19:04 PM PDT 24 Jun 30 06:19:12 PM PDT 24 4117640282 ps
T318 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2195481775 Jun 30 06:19:37 PM PDT 24 Jun 30 06:19:42 PM PDT 24 294912595 ps
T319 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2212375884 Jun 30 06:19:14 PM PDT 24 Jun 30 06:19:16 PM PDT 24 1333345522 ps
T320 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1254040999 Jun 30 06:19:33 PM PDT 24 Jun 30 06:19:35 PM PDT 24 437839341 ps
T321 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.569039039 Jun 30 06:19:09 PM PDT 24 Jun 30 06:19:12 PM PDT 24 792997572 ps
T322 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2927839673 Jun 30 06:19:25 PM PDT 24 Jun 30 06:19:28 PM PDT 24 4414341408 ps
T323 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2875358571 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:02 PM PDT 24 283535002 ps
T324 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3253740719 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:03 PM PDT 24 4089718268 ps
T325 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1881574064 Jun 30 06:19:12 PM PDT 24 Jun 30 06:19:18 PM PDT 24 8048329873 ps
T326 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3023393641 Jun 30 06:19:05 PM PDT 24 Jun 30 06:19:07 PM PDT 24 336223240 ps
T327 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1763741448 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:39 PM PDT 24 436513325 ps
T328 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1000422874 Jun 30 06:18:58 PM PDT 24 Jun 30 06:18:59 PM PDT 24 265268268 ps
T329 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3705257763 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:40 PM PDT 24 348133686 ps
T330 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2062342608 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:13 PM PDT 24 443371541 ps
T331 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2979102425 Jun 30 06:19:33 PM PDT 24 Jun 30 06:19:35 PM PDT 24 303941338 ps
T332 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4112120534 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:12 PM PDT 24 1503778041 ps
T73 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4119563353 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:13 PM PDT 24 322869464 ps
T333 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1929222151 Jun 30 06:19:38 PM PDT 24 Jun 30 06:19:43 PM PDT 24 492009811 ps
T334 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1792709281 Jun 30 06:19:37 PM PDT 24 Jun 30 06:19:41 PM PDT 24 349788756 ps
T69 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3620417223 Jun 30 06:18:54 PM PDT 24 Jun 30 06:18:57 PM PDT 24 481555012 ps
T335 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3625837767 Jun 30 06:19:12 PM PDT 24 Jun 30 06:19:15 PM PDT 24 445018794 ps
T336 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3583164967 Jun 30 06:19:13 PM PDT 24 Jun 30 06:19:17 PM PDT 24 538587483 ps
T337 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3628031034 Jun 30 06:18:53 PM PDT 24 Jun 30 06:18:56 PM PDT 24 4546821272 ps
T338 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.989883784 Jun 30 06:19:05 PM PDT 24 Jun 30 06:19:08 PM PDT 24 445448744 ps
T339 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.535480485 Jun 30 06:19:34 PM PDT 24 Jun 30 06:19:36 PM PDT 24 462051009 ps
T340 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.396451983 Jun 30 06:19:39 PM PDT 24 Jun 30 06:19:43 PM PDT 24 280552926 ps
T341 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4280631888 Jun 30 06:19:05 PM PDT 24 Jun 30 06:19:09 PM PDT 24 1150428574 ps
T342 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1398952261 Jun 30 06:19:20 PM PDT 24 Jun 30 06:19:27 PM PDT 24 4247343749 ps
T343 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1370648942 Jun 30 06:19:06 PM PDT 24 Jun 30 06:19:11 PM PDT 24 2578339072 ps
T344 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3784535689 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:41 PM PDT 24 491120019 ps
T345 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1338947032 Jun 30 06:19:14 PM PDT 24 Jun 30 06:19:16 PM PDT 24 2499815576 ps
T346 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.214595968 Jun 30 06:18:58 PM PDT 24 Jun 30 06:18:59 PM PDT 24 299625220 ps
T74 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2736819018 Jun 30 06:19:17 PM PDT 24 Jun 30 06:19:19 PM PDT 24 569556575 ps
T347 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1270155901 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:13 PM PDT 24 370365663 ps
T348 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.795485384 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:12 PM PDT 24 4657473204 ps
T349 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4136031937 Jun 30 06:19:18 PM PDT 24 Jun 30 06:19:20 PM PDT 24 369670182 ps
T350 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2849331779 Jun 30 06:19:35 PM PDT 24 Jun 30 06:19:39 PM PDT 24 509656736 ps
T351 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3382186725 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:04 PM PDT 24 2496916748 ps
T352 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3442706660 Jun 30 06:19:01 PM PDT 24 Jun 30 06:19:06 PM PDT 24 2649203212 ps
T353 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3247150495 Jun 30 06:19:33 PM PDT 24 Jun 30 06:19:36 PM PDT 24 453017449 ps
T354 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3319233227 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:17 PM PDT 24 4620072046 ps
T355 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3457684218 Jun 30 06:19:00 PM PDT 24 Jun 30 06:19:04 PM PDT 24 455671125 ps
T356 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2716636929 Jun 30 06:19:05 PM PDT 24 Jun 30 06:19:07 PM PDT 24 327733676 ps
T357 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1464845559 Jun 30 06:19:18 PM PDT 24 Jun 30 06:19:20 PM PDT 24 520393536 ps
T358 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.334481675 Jun 30 06:19:33 PM PDT 24 Jun 30 06:19:35 PM PDT 24 376945941 ps
T359 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1165159809 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:13 PM PDT 24 402644113 ps
T360 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2066053386 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:16 PM PDT 24 1275031094 ps
T361 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3580422227 Jun 30 06:19:16 PM PDT 24 Jun 30 06:19:17 PM PDT 24 449212351 ps
T362 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.735226566 Jun 30 06:19:16 PM PDT 24 Jun 30 06:19:19 PM PDT 24 525233891 ps
T363 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.316890197 Jun 30 06:18:57 PM PDT 24 Jun 30 06:18:59 PM PDT 24 427626266 ps
T364 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4175070174 Jun 30 06:19:17 PM PDT 24 Jun 30 06:19:18 PM PDT 24 365749223 ps
T365 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3012941781 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:14 PM PDT 24 538763905 ps
T366 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1225990300 Jun 30 06:19:34 PM PDT 24 Jun 30 06:19:36 PM PDT 24 466867490 ps
T367 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3504821423 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:13 PM PDT 24 491311044 ps
T368 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3869623818 Jun 30 06:19:22 PM PDT 24 Jun 30 06:19:23 PM PDT 24 489227823 ps
T70 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2926959038 Jun 30 06:18:53 PM PDT 24 Jun 30 06:18:58 PM PDT 24 9278328581 ps
T369 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3394300682 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:01 PM PDT 24 591244418 ps
T195 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.575136515 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:15 PM PDT 24 4613321967 ps
T370 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1716468270 Jun 30 06:19:34 PM PDT 24 Jun 30 06:19:37 PM PDT 24 513659679 ps
T371 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4137063467 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:40 PM PDT 24 382746146 ps
T372 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2387867416 Jun 30 06:19:18 PM PDT 24 Jun 30 06:19:19 PM PDT 24 474828587 ps
T373 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.737545817 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:00 PM PDT 24 567952701 ps
T71 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2955147660 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:01 PM PDT 24 471112114 ps
T374 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2470148117 Jun 30 06:19:19 PM PDT 24 Jun 30 06:19:22 PM PDT 24 1347215093 ps
T375 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4020800618 Jun 30 06:19:12 PM PDT 24 Jun 30 06:19:14 PM PDT 24 510124360 ps
T376 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2868498467 Jun 30 06:19:34 PM PDT 24 Jun 30 06:19:37 PM PDT 24 440975687 ps
T377 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2187599857 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:13 PM PDT 24 513797582 ps
T378 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3492108615 Jun 30 06:19:19 PM PDT 24 Jun 30 06:19:20 PM PDT 24 401869661 ps
T66 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.317353792 Jun 30 06:19:04 PM PDT 24 Jun 30 06:19:06 PM PDT 24 403883406 ps
T72 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1563093508 Jun 30 06:19:13 PM PDT 24 Jun 30 06:19:16 PM PDT 24 441852209 ps
T379 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1757009477 Jun 30 06:19:37 PM PDT 24 Jun 30 06:19:42 PM PDT 24 323104774 ps
T380 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3830040339 Jun 30 06:19:24 PM PDT 24 Jun 30 06:19:26 PM PDT 24 326563273 ps
T381 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.327308709 Jun 30 06:18:54 PM PDT 24 Jun 30 06:18:56 PM PDT 24 298269223 ps
T382 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1428798085 Jun 30 06:19:34 PM PDT 24 Jun 30 06:19:35 PM PDT 24 309973253 ps
T383 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.183831395 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:13 PM PDT 24 286647305 ps
T384 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3329479900 Jun 30 06:19:33 PM PDT 24 Jun 30 06:19:34 PM PDT 24 355342568 ps
T385 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.101186536 Jun 30 06:19:33 PM PDT 24 Jun 30 06:19:34 PM PDT 24 414680406 ps
T386 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.549105168 Jun 30 06:19:04 PM PDT 24 Jun 30 06:19:06 PM PDT 24 1040061967 ps
T196 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.910049901 Jun 30 06:19:17 PM PDT 24 Jun 30 06:19:29 PM PDT 24 7812933835 ps
T387 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2702164783 Jun 30 06:19:05 PM PDT 24 Jun 30 06:19:08 PM PDT 24 480369322 ps
T388 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3177288462 Jun 30 06:19:04 PM PDT 24 Jun 30 06:19:11 PM PDT 24 7114112442 ps
T389 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.204232866 Jun 30 06:19:14 PM PDT 24 Jun 30 06:19:17 PM PDT 24 571106744 ps
T390 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1782722810 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:04 PM PDT 24 4034262678 ps
T391 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.193037088 Jun 30 06:19:22 PM PDT 24 Jun 30 06:19:23 PM PDT 24 340528242 ps
T392 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.190850409 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:11 PM PDT 24 537431212 ps
T393 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3965969905 Jun 30 06:19:18 PM PDT 24 Jun 30 06:19:21 PM PDT 24 1553194514 ps
T394 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3839475585 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:14 PM PDT 24 921522671 ps
T395 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.664854670 Jun 30 06:19:03 PM PDT 24 Jun 30 06:19:04 PM PDT 24 399147358 ps
T396 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3885286122 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:15 PM PDT 24 8484354457 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2508324038 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:02 PM PDT 24 544264047 ps
T398 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1767964343 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:01 PM PDT 24 1223965361 ps
T399 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1218271641 Jun 30 06:19:12 PM PDT 24 Jun 30 06:19:14 PM PDT 24 426601675 ps
T400 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4054991311 Jun 30 06:19:07 PM PDT 24 Jun 30 06:19:11 PM PDT 24 587616173 ps
T401 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.451363798 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:14 PM PDT 24 383405595 ps
T402 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1939908144 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:15 PM PDT 24 911997189 ps
T403 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.165939521 Jun 30 06:19:14 PM PDT 24 Jun 30 06:19:16 PM PDT 24 667647011 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3825252742 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:12 PM PDT 24 762193647 ps
T405 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1796459445 Jun 30 06:19:05 PM PDT 24 Jun 30 06:19:08 PM PDT 24 550835837 ps
T406 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2586397327 Jun 30 06:19:19 PM PDT 24 Jun 30 06:19:20 PM PDT 24 363203074 ps
T407 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2307351163 Jun 30 06:19:19 PM PDT 24 Jun 30 06:19:23 PM PDT 24 4167049254 ps
T408 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3079763248 Jun 30 06:19:20 PM PDT 24 Jun 30 06:19:22 PM PDT 24 532378585 ps
T409 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1201070189 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:40 PM PDT 24 481961801 ps
T197 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2117009767 Jun 30 06:19:05 PM PDT 24 Jun 30 06:19:14 PM PDT 24 4216506998 ps
T410 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4277217138 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:14 PM PDT 24 925524087 ps
T411 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.535648458 Jun 30 06:19:17 PM PDT 24 Jun 30 06:19:21 PM PDT 24 1847152100 ps
T412 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2980662208 Jun 30 06:19:19 PM PDT 24 Jun 30 06:19:21 PM PDT 24 4356284906 ps
T413 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.791099694 Jun 30 06:19:36 PM PDT 24 Jun 30 06:19:40 PM PDT 24 358822498 ps
T414 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2830981284 Jun 30 06:19:19 PM PDT 24 Jun 30 06:19:21 PM PDT 24 403034081 ps
T415 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3113279395 Jun 30 06:19:11 PM PDT 24 Jun 30 06:19:13 PM PDT 24 394729021 ps
T416 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1670234716 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:12 PM PDT 24 503626697 ps
T417 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3416536635 Jun 30 06:19:00 PM PDT 24 Jun 30 06:19:22 PM PDT 24 7522177398 ps
T67 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.88879861 Jun 30 06:19:06 PM PDT 24 Jun 30 06:19:09 PM PDT 24 577107423 ps
T418 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1904154392 Jun 30 06:18:59 PM PDT 24 Jun 30 06:19:01 PM PDT 24 553322518 ps
T419 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1266921712 Jun 30 06:18:58 PM PDT 24 Jun 30 06:19:00 PM PDT 24 546484172 ps
T420 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1061635811 Jun 30 06:19:17 PM PDT 24 Jun 30 06:19:18 PM PDT 24 414761891 ps
T421 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1153342296 Jun 30 06:19:10 PM PDT 24 Jun 30 06:19:14 PM PDT 24 437669078 ps

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1089214061
Short name T2
Test name
Test status
Simulation time 933068744848 ps
CPU time 950.48 seconds
Started Jun 30 06:40:51 PM PDT 24
Finished Jun 30 06:56:43 PM PDT 24
Peak memory 208976 kb
Host smart-bffb5c23-b660-4220-9d98-54f8a1a1e2e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089214061 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1089214061
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3130968978
Short name T18
Test name
Test status
Simulation time 119668439182 ps
CPU time 160.88 seconds
Started Jun 30 06:41:11 PM PDT 24
Finished Jun 30 06:43:52 PM PDT 24
Peak memory 197984 kb
Host smart-9cab1fcf-04a1-4a2b-a812-00bfcf23ba1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130968978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3130968978
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3331369698
Short name T39
Test name
Test status
Simulation time 8194550338 ps
CPU time 4.19 seconds
Started Jun 30 06:19:12 PM PDT 24
Finished Jun 30 06:19:18 PM PDT 24
Peak memory 198248 kb
Host smart-c54331d7-e95c-4a07-8b25-c4125a252e6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331369698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3331369698
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2155176531
Short name T42
Test name
Test status
Simulation time 225298819688 ps
CPU time 461.15 seconds
Started Jun 30 06:40:47 PM PDT 24
Finished Jun 30 06:48:30 PM PDT 24
Peak memory 214260 kb
Host smart-098e9ed1-5724-4903-b093-e3c617b0fe81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155176531 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2155176531
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.114426897
Short name T95
Test name
Test status
Simulation time 258625502578 ps
CPU time 421.26 seconds
Started Jun 30 06:40:47 PM PDT 24
Finished Jun 30 06:47:49 PM PDT 24
Peak memory 202636 kb
Host smart-0dba9e52-cab8-46a0-b736-608a1c50c4ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114426897 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.114426897
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2530454784
Short name T64
Test name
Test status
Simulation time 356294567 ps
CPU time 0.73 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:01 PM PDT 24
Peak memory 194060 kb
Host smart-2aa2a48f-a5d8-4227-b6dd-d43931d884ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530454784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2530454784
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3759228807
Short name T84
Test name
Test status
Simulation time 87335565845 ps
CPU time 767.05 seconds
Started Jun 30 06:41:17 PM PDT 24
Finished Jun 30 06:54:04 PM PDT 24
Peak memory 205884 kb
Host smart-91f7cdf4-50de-4d9c-be27-7d422e452f85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759228807 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3759228807
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.583374625
Short name T9
Test name
Test status
Simulation time 57127599426 ps
CPU time 19.5 seconds
Started Jun 30 06:40:55 PM PDT 24
Finished Jun 30 06:41:16 PM PDT 24
Peak memory 197996 kb
Host smart-39be833e-6310-4658-bbe2-9c7c032d9cd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583374625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.583374625
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2143406128
Short name T142
Test name
Test status
Simulation time 203548514748 ps
CPU time 369.78 seconds
Started Jun 30 06:40:45 PM PDT 24
Finished Jun 30 06:46:55 PM PDT 24
Peak memory 210172 kb
Host smart-bd782313-8e9d-4dd8-8ae2-c8e931891836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143406128 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2143406128
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3385049189
Short name T116
Test name
Test status
Simulation time 109453899369 ps
CPU time 887 seconds
Started Jun 30 06:40:55 PM PDT 24
Finished Jun 30 06:55:43 PM PDT 24
Peak memory 209776 kb
Host smart-23d54577-b4a0-4d71-b1ee-1151b52ea243
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385049189 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3385049189
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2643988792
Short name T44
Test name
Test status
Simulation time 1589568926144 ps
CPU time 602.54 seconds
Started Jun 30 06:40:42 PM PDT 24
Finished Jun 30 06:50:45 PM PDT 24
Peak memory 214076 kb
Host smart-05275202-a603-4899-8bfc-35b0eef0874a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643988792 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2643988792
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1462562400
Short name T109
Test name
Test status
Simulation time 436755410241 ps
CPU time 739.24 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:53:07 PM PDT 24
Peak memory 214676 kb
Host smart-79495a1d-09a1-477e-ada9-4df289fdecee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462562400 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1462562400
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3530419669
Short name T45
Test name
Test status
Simulation time 100480539282 ps
CPU time 719.49 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:52:47 PM PDT 24
Peak memory 214700 kb
Host smart-9ea741d5-68af-4d8f-a649-e7bfdf1367cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530419669 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3530419669
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.4101664552
Short name T54
Test name
Test status
Simulation time 34087059270 ps
CPU time 261.53 seconds
Started Jun 30 06:40:32 PM PDT 24
Finished Jun 30 06:44:54 PM PDT 24
Peak memory 206588 kb
Host smart-61f013dc-b120-4810-b881-c9d090bf6f66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101664552 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.4101664552
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1289091657
Short name T15
Test name
Test status
Simulation time 7616862912 ps
CPU time 6.68 seconds
Started Jun 30 06:40:27 PM PDT 24
Finished Jun 30 06:40:35 PM PDT 24
Peak memory 215800 kb
Host smart-7a4c2bb0-1706-4d52-b9ac-9a5e539361ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289091657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1289091657
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2332421061
Short name T122
Test name
Test status
Simulation time 78131912930 ps
CPU time 864.25 seconds
Started Jun 30 06:40:27 PM PDT 24
Finished Jun 30 06:54:52 PM PDT 24
Peak memory 214788 kb
Host smart-95a9ae76-8014-4b61-b329-68170627500d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332421061 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2332421061
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2462956415
Short name T133
Test name
Test status
Simulation time 249458976675 ps
CPU time 504.91 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:49:28 PM PDT 24
Peak memory 204060 kb
Host smart-f95606dd-6719-47f0-9ddb-9ee4843873c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462956415 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2462956415
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2374759527
Short name T123
Test name
Test status
Simulation time 36973917277 ps
CPU time 277.44 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:45:40 PM PDT 24
Peak memory 198412 kb
Host smart-87845b9e-0291-4ba2-9638-4a759770fa5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374759527 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2374759527
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2390445802
Short name T101
Test name
Test status
Simulation time 161794675200 ps
CPU time 452.5 seconds
Started Jun 30 06:41:00 PM PDT 24
Finished Jun 30 06:48:33 PM PDT 24
Peak memory 211424 kb
Host smart-617be6a2-77e2-4d13-8711-3e6001b27b68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390445802 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2390445802
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.379504941
Short name T82
Test name
Test status
Simulation time 84774674700 ps
CPU time 958.37 seconds
Started Jun 30 06:40:25 PM PDT 24
Finished Jun 30 06:56:23 PM PDT 24
Peak memory 211052 kb
Host smart-a76884b3-3d1e-4fb3-bde3-57ad5d50d6c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379504941 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.379504941
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1719067206
Short name T99
Test name
Test status
Simulation time 24286646638 ps
CPU time 95.77 seconds
Started Jun 30 06:40:39 PM PDT 24
Finished Jun 30 06:42:16 PM PDT 24
Peak memory 206676 kb
Host smart-518cfb97-4f2f-4c12-979f-e728f06ae26e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719067206 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1719067206
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1375491257
Short name T34
Test name
Test status
Simulation time 34081247736 ps
CPU time 286.12 seconds
Started Jun 30 06:41:13 PM PDT 24
Finished Jun 30 06:46:00 PM PDT 24
Peak memory 213840 kb
Host smart-b8233e48-b8e0-437e-a4d5-225e42d14e84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375491257 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1375491257
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2909424376
Short name T104
Test name
Test status
Simulation time 176496303424 ps
CPU time 127.81 seconds
Started Jun 30 06:41:00 PM PDT 24
Finished Jun 30 06:43:09 PM PDT 24
Peak memory 192752 kb
Host smart-ad6c0737-6576-4111-b2d8-ab50fb30beb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909424376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2909424376
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1960464631
Short name T14
Test name
Test status
Simulation time 29118264473 ps
CPU time 201.08 seconds
Started Jun 30 06:40:55 PM PDT 24
Finished Jun 30 06:44:18 PM PDT 24
Peak memory 206648 kb
Host smart-d44a7e2e-99c1-410f-84ec-3471c34f1655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960464631 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1960464631
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3129813290
Short name T47
Test name
Test status
Simulation time 66731283133 ps
CPU time 45.26 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:41:32 PM PDT 24
Peak memory 198028 kb
Host smart-ace9e1e7-8c80-4969-be94-d628cbcde8fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129813290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3129813290
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2861432185
Short name T145
Test name
Test status
Simulation time 22356505759 ps
CPU time 36.19 seconds
Started Jun 30 06:41:00 PM PDT 24
Finished Jun 30 06:41:36 PM PDT 24
Peak memory 197940 kb
Host smart-bcbc6a7e-deb6-4409-8ec4-abe0e9a8e748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861432185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2861432185
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2473346106
Short name T108
Test name
Test status
Simulation time 130051801526 ps
CPU time 176.25 seconds
Started Jun 30 06:40:55 PM PDT 24
Finished Jun 30 06:43:53 PM PDT 24
Peak memory 192812 kb
Host smart-d8be4e23-843a-4d61-aa40-7c0130461d9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473346106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2473346106
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.729804104
Short name T114
Test name
Test status
Simulation time 35079069468 ps
CPU time 50.84 seconds
Started Jun 30 06:41:03 PM PDT 24
Finished Jun 30 06:41:55 PM PDT 24
Peak memory 198032 kb
Host smart-8e7e306d-9152-4730-88e3-bf4be048b1f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729804104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.729804104
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1542767515
Short name T53
Test name
Test status
Simulation time 55456945175 ps
CPU time 5.24 seconds
Started Jun 30 06:41:21 PM PDT 24
Finished Jun 30 06:41:27 PM PDT 24
Peak memory 192928 kb
Host smart-c83dd1a3-737f-4100-9c6d-af74b61d0ff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542767515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1542767515
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3202654531
Short name T110
Test name
Test status
Simulation time 89863750764 ps
CPU time 126.29 seconds
Started Jun 30 06:40:41 PM PDT 24
Finished Jun 30 06:42:48 PM PDT 24
Peak memory 184364 kb
Host smart-0e22ecc0-0d06-4c06-b7ac-c8745f955cf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202654531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3202654531
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2433546273
Short name T113
Test name
Test status
Simulation time 107583286455 ps
CPU time 153.16 seconds
Started Jun 30 06:40:29 PM PDT 24
Finished Jun 30 06:43:03 PM PDT 24
Peak memory 197964 kb
Host smart-dbf5c975-85a6-4a85-921b-d267c2d27f99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433546273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2433546273
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1117896275
Short name T127
Test name
Test status
Simulation time 266291942275 ps
CPU time 299.58 seconds
Started Jun 30 06:40:39 PM PDT 24
Finished Jun 30 06:45:40 PM PDT 24
Peak memory 213896 kb
Host smart-685d131d-8f5b-4ce6-ba33-0aa9befa7afc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117896275 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1117896275
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1355403633
Short name T149
Test name
Test status
Simulation time 123418842065 ps
CPU time 152.48 seconds
Started Jun 30 06:40:52 PM PDT 24
Finished Jun 30 06:43:26 PM PDT 24
Peak memory 198080 kb
Host smart-69c531d9-5118-4eee-8e3d-ae0ef042d060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355403633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1355403633
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.526983092
Short name T117
Test name
Test status
Simulation time 2106360431 ps
CPU time 1.57 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:41:05 PM PDT 24
Peak memory 197904 kb
Host smart-815c0139-a776-4622-8d94-8cef6a5501bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526983092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.526983092
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1901451006
Short name T129
Test name
Test status
Simulation time 96148468823 ps
CPU time 128.61 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:43:11 PM PDT 24
Peak memory 192820 kb
Host smart-d53b424a-ceae-435b-a3ff-dd809facd6b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901451006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1901451006
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.4081553338
Short name T131
Test name
Test status
Simulation time 229373221965 ps
CPU time 178.77 seconds
Started Jun 30 06:41:09 PM PDT 24
Finished Jun 30 06:44:08 PM PDT 24
Peak memory 198000 kb
Host smart-237c3570-16e5-4696-855e-6db0a984d8f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081553338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.4081553338
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.635939281
Short name T128
Test name
Test status
Simulation time 49097131414 ps
CPU time 403.72 seconds
Started Jun 30 06:40:27 PM PDT 24
Finished Jun 30 06:47:11 PM PDT 24
Peak memory 208188 kb
Host smart-9e890dcf-2e1f-4c70-b639-baf7961c9fdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635939281 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.635939281
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2382707750
Short name T96
Test name
Test status
Simulation time 37661965988 ps
CPU time 188.47 seconds
Started Jun 30 06:40:39 PM PDT 24
Finished Jun 30 06:43:48 PM PDT 24
Peak memory 206640 kb
Host smart-de857c89-1e3a-4f4a-8d90-9465ce8cbdff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382707750 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2382707750
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.4125220185
Short name T88
Test name
Test status
Simulation time 19875323606 ps
CPU time 202.16 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:44:10 PM PDT 24
Peak memory 198872 kb
Host smart-1af1a2e4-b3d3-42be-83b3-5b849e4e5edc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125220185 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.4125220185
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.816568826
Short name T126
Test name
Test status
Simulation time 115555098573 ps
CPU time 82.42 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:42:25 PM PDT 24
Peak memory 198048 kb
Host smart-03ad7d1a-e7cb-465d-90de-94f2c1c27d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816568826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.816568826
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3220896183
Short name T102
Test name
Test status
Simulation time 126380131051 ps
CPU time 88.17 seconds
Started Jun 30 06:41:13 PM PDT 24
Finished Jun 30 06:42:42 PM PDT 24
Peak memory 192448 kb
Host smart-c1a8b78c-5d35-4d95-814f-d57ade7aad01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220896183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3220896183
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2858901758
Short name T121
Test name
Test status
Simulation time 29917497829 ps
CPU time 27.49 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:41:22 PM PDT 24
Peak memory 192812 kb
Host smart-0d52d0a2-46d8-4ef1-b62f-e8e2d2701083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858901758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2858901758
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2259595325
Short name T103
Test name
Test status
Simulation time 111027533266 ps
CPU time 34.59 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:41:29 PM PDT 24
Peak memory 192816 kb
Host smart-5866a534-c27e-4cc5-880a-093e92b966af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259595325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2259595325
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.638364207
Short name T48
Test name
Test status
Simulation time 311090015628 ps
CPU time 533.42 seconds
Started Jun 30 06:40:56 PM PDT 24
Finished Jun 30 06:49:51 PM PDT 24
Peak memory 212360 kb
Host smart-cf095afd-b251-45d2-89d2-ca30be899989
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638364207 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.638364207
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2963984770
Short name T93
Test name
Test status
Simulation time 266968518015 ps
CPU time 813.63 seconds
Started Jun 30 06:41:00 PM PDT 24
Finished Jun 30 06:54:34 PM PDT 24
Peak memory 206772 kb
Host smart-de5daf6a-d09a-41eb-9ac4-6db621dd17d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963984770 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2963984770
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2988425607
Short name T90
Test name
Test status
Simulation time 211688280247 ps
CPU time 398.15 seconds
Started Jun 30 06:40:40 PM PDT 24
Finished Jun 30 06:47:19 PM PDT 24
Peak memory 210800 kb
Host smart-17f7d641-443e-40d4-94a9-9dfb39db61f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988425607 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2988425607
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2929557550
Short name T111
Test name
Test status
Simulation time 117872010965 ps
CPU time 12.23 seconds
Started Jun 30 06:40:40 PM PDT 24
Finished Jun 30 06:40:53 PM PDT 24
Peak memory 192736 kb
Host smart-9fa1398e-6edf-4752-ada2-425bd8281776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929557550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2929557550
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3502685495
Short name T115
Test name
Test status
Simulation time 240573680332 ps
CPU time 213.15 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:44:21 PM PDT 24
Peak memory 191792 kb
Host smart-18c17b54-0ae6-40c6-ae56-b60b7823dcd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502685495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3502685495
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3970651978
Short name T94
Test name
Test status
Simulation time 56579555289 ps
CPU time 584.83 seconds
Started Jun 30 06:40:33 PM PDT 24
Finished Jun 30 06:50:18 PM PDT 24
Peak memory 211344 kb
Host smart-7d06484a-c0a6-4a85-b1c3-5f5c40a46689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970651978 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3970651978
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2348497291
Short name T12
Test name
Test status
Simulation time 72710781772 ps
CPU time 269.97 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:45:24 PM PDT 24
Peak memory 199888 kb
Host smart-c2c8ae93-b9e0-45ac-b1db-987491281d48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348497291 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2348497291
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.886988303
Short name T86
Test name
Test status
Simulation time 131140693937 ps
CPU time 202.42 seconds
Started Jun 30 06:40:55 PM PDT 24
Finished Jun 30 06:44:19 PM PDT 24
Peak memory 192716 kb
Host smart-a239c46d-3d2a-4bba-a31e-82143975d071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886988303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.886988303
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3453263310
Short name T135
Test name
Test status
Simulation time 137372591243 ps
CPU time 293.75 seconds
Started Jun 30 06:41:00 PM PDT 24
Finished Jun 30 06:45:55 PM PDT 24
Peak memory 201224 kb
Host smart-4888b69f-c169-4e0b-bfa2-a0f6ad6cde80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453263310 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3453263310
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1295762539
Short name T27
Test name
Test status
Simulation time 211997454194 ps
CPU time 68.65 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:42:11 PM PDT 24
Peak memory 198068 kb
Host smart-7ab38875-5c31-44fe-b77d-3dfa514ad86b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295762539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1295762539
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1516695484
Short name T98
Test name
Test status
Simulation time 54859764758 ps
CPU time 204.15 seconds
Started Jun 30 06:41:13 PM PDT 24
Finished Jun 30 06:44:38 PM PDT 24
Peak memory 214188 kb
Host smart-028ecc52-fa9a-4311-bf45-f5c8ba63c22b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516695484 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1516695484
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1557158744
Short name T57
Test name
Test status
Simulation time 215756150437 ps
CPU time 39.12 seconds
Started Jun 30 06:40:35 PM PDT 24
Finished Jun 30 06:41:15 PM PDT 24
Peak memory 191720 kb
Host smart-ae17846f-8fa3-409f-9daf-657827e348bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557158744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1557158744
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3591314405
Short name T150
Test name
Test status
Simulation time 305850846961 ps
CPU time 196.4 seconds
Started Jun 30 06:40:48 PM PDT 24
Finished Jun 30 06:44:05 PM PDT 24
Peak memory 192816 kb
Host smart-36bbab43-5dd4-4342-8a65-06a1b5e9a85d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591314405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3591314405
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2639117738
Short name T120
Test name
Test status
Simulation time 125653674750 ps
CPU time 191.44 seconds
Started Jun 30 06:41:11 PM PDT 24
Finished Jun 30 06:44:23 PM PDT 24
Peak memory 199672 kb
Host smart-25201dc3-3841-4e1d-9e62-3b66a3406bbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639117738 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2639117738
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1745108775
Short name T124
Test name
Test status
Simulation time 136959202522 ps
CPU time 208.75 seconds
Started Jun 30 06:40:29 PM PDT 24
Finished Jun 30 06:43:59 PM PDT 24
Peak memory 198024 kb
Host smart-3199e2c5-b839-4c44-82ed-51e78d9b163d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745108775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1745108775
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.571244172
Short name T106
Test name
Test status
Simulation time 465925346847 ps
CPU time 178.81 seconds
Started Jun 30 06:40:40 PM PDT 24
Finished Jun 30 06:43:39 PM PDT 24
Peak memory 192424 kb
Host smart-16047be2-c21b-43ff-b9ae-9b540248b642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571244172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.571244172
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1716134070
Short name T143
Test name
Test status
Simulation time 185660064911 ps
CPU time 276.52 seconds
Started Jun 30 06:41:13 PM PDT 24
Finished Jun 30 06:45:50 PM PDT 24
Peak memory 201004 kb
Host smart-7ffa7e14-b770-4fd7-9333-fc6d6df2ff1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716134070 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1716134070
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2029490125
Short name T43
Test name
Test status
Simulation time 253223549181 ps
CPU time 256.36 seconds
Started Jun 30 06:41:20 PM PDT 24
Finished Jun 30 06:45:37 PM PDT 24
Peak memory 206664 kb
Host smart-ec5439c9-3ada-4a9a-b591-4ac94035324f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029490125 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2029490125
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3513507854
Short name T25
Test name
Test status
Simulation time 97082481755 ps
CPU time 173.32 seconds
Started Jun 30 06:41:07 PM PDT 24
Finished Jun 30 06:44:01 PM PDT 24
Peak memory 199840 kb
Host smart-0e067a2f-05f0-41ca-a1d9-ba2a5bafa700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513507854 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3513507854
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1648541654
Short name T97
Test name
Test status
Simulation time 44417667729 ps
CPU time 327.85 seconds
Started Jun 30 06:41:09 PM PDT 24
Finished Jun 30 06:46:38 PM PDT 24
Peak memory 206672 kb
Host smart-feebd14e-8d29-45fc-af18-8b35df7100f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648541654 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1648541654
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3805757643
Short name T137
Test name
Test status
Simulation time 224347639192 ps
CPU time 283.68 seconds
Started Jun 30 06:41:14 PM PDT 24
Finished Jun 30 06:45:59 PM PDT 24
Peak memory 192828 kb
Host smart-e39f46e7-7344-413e-861a-956569924a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805757643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3805757643
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3454447901
Short name T165
Test name
Test status
Simulation time 62479016385 ps
CPU time 85.66 seconds
Started Jun 30 06:40:40 PM PDT 24
Finished Jun 30 06:42:06 PM PDT 24
Peak memory 192812 kb
Host smart-5c17cf43-a140-4c5d-a766-5e07dbe8d58c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454447901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3454447901
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3478457446
Short name T112
Test name
Test status
Simulation time 54907266347 ps
CPU time 5.87 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:40:52 PM PDT 24
Peak memory 191640 kb
Host smart-b9045ea0-a81c-4a0e-a72e-ffba632e157a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478457446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3478457446
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.473286297
Short name T119
Test name
Test status
Simulation time 5391885581 ps
CPU time 37.58 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:41:32 PM PDT 24
Peak memory 206680 kb
Host smart-aff0bd85-a616-4d41-8888-42ef44dca4a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473286297 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.473286297
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1512587657
Short name T125
Test name
Test status
Simulation time 33913985079 ps
CPU time 274.13 seconds
Started Jun 30 06:40:59 PM PDT 24
Finished Jun 30 06:45:34 PM PDT 24
Peak memory 213800 kb
Host smart-ba6a924f-959d-45c3-9604-befd0aff8816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512587657 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1512587657
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1361162648
Short name T100
Test name
Test status
Simulation time 52660427596 ps
CPU time 259.68 seconds
Started Jun 30 06:40:32 PM PDT 24
Finished Jun 30 06:44:53 PM PDT 24
Peak memory 206604 kb
Host smart-0ffdcaa3-a794-44ec-b5e8-2bf95b8f96c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361162648 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1361162648
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.208630131
Short name T136
Test name
Test status
Simulation time 238725116280 ps
CPU time 95.35 seconds
Started Jun 30 06:40:34 PM PDT 24
Finished Jun 30 06:42:10 PM PDT 24
Peak memory 191916 kb
Host smart-913a8fbf-7091-4158-ad59-58ad58130a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208630131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.208630131
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.601237376
Short name T41
Test name
Test status
Simulation time 181353033778 ps
CPU time 322.21 seconds
Started Jun 30 06:40:32 PM PDT 24
Finished Jun 30 06:45:55 PM PDT 24
Peak memory 213932 kb
Host smart-e32a0e2d-4012-4880-8c09-39afc43c809c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601237376 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.601237376
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3741317113
Short name T107
Test name
Test status
Simulation time 375451828 ps
CPU time 0.88 seconds
Started Jun 30 06:40:52 PM PDT 24
Finished Jun 30 06:40:55 PM PDT 24
Peak memory 196444 kb
Host smart-7aeb42a2-0ead-4ea4-a138-347b92cce06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741317113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3741317113
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1326958323
Short name T148
Test name
Test status
Simulation time 355642075 ps
CPU time 1.08 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:40:55 PM PDT 24
Peak memory 196484 kb
Host smart-537c6232-b48c-49da-862e-97f4ff7a9793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326958323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1326958323
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2403238609
Short name T157
Test name
Test status
Simulation time 18936391231 ps
CPU time 204.41 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:44:27 PM PDT 24
Peak memory 198368 kb
Host smart-3ea32eaa-04e4-4f75-9585-7d4955a15aad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403238609 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2403238609
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.852280176
Short name T147
Test name
Test status
Simulation time 565863456 ps
CPU time 0.81 seconds
Started Jun 30 06:40:43 PM PDT 24
Finished Jun 30 06:40:44 PM PDT 24
Peak memory 196456 kb
Host smart-1ab6e666-a3d2-4d6a-81aa-d85bda8b96ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852280176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.852280176
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1295779837
Short name T153
Test name
Test status
Simulation time 584875001 ps
CPU time 0.68 seconds
Started Jun 30 06:40:44 PM PDT 24
Finished Jun 30 06:40:45 PM PDT 24
Peak memory 196476 kb
Host smart-d2d56c29-5e25-49c5-bf58-14afcaa9870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295779837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1295779837
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3553596449
Short name T51
Test name
Test status
Simulation time 444215300 ps
CPU time 0.75 seconds
Started Jun 30 06:40:47 PM PDT 24
Finished Jun 30 06:40:49 PM PDT 24
Peak memory 196524 kb
Host smart-c0dbf505-94fe-480b-8d15-4175eddf544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553596449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3553596449
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2073867299
Short name T46
Test name
Test status
Simulation time 532964907 ps
CPU time 0.82 seconds
Started Jun 30 06:40:45 PM PDT 24
Finished Jun 30 06:40:46 PM PDT 24
Peak memory 196452 kb
Host smart-84eac72c-0c89-4583-98cf-5b5addafa17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073867299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2073867299
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.129888349
Short name T144
Test name
Test status
Simulation time 516747795 ps
CPU time 1.25 seconds
Started Jun 30 06:41:00 PM PDT 24
Finished Jun 30 06:41:03 PM PDT 24
Peak memory 196532 kb
Host smart-c57e4564-4a78-4ce8-9efa-10b36afe0841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129888349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.129888349
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.211095107
Short name T31
Test name
Test status
Simulation time 539053289 ps
CPU time 1.47 seconds
Started Jun 30 06:40:28 PM PDT 24
Finished Jun 30 06:40:30 PM PDT 24
Peak memory 196560 kb
Host smart-5c3c0171-6ad0-445b-8563-4ac31cc4367e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211095107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.211095107
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2906560290
Short name T162
Test name
Test status
Simulation time 76102894574 ps
CPU time 42.9 seconds
Started Jun 30 06:41:16 PM PDT 24
Finished Jun 30 06:41:59 PM PDT 24
Peak memory 198084 kb
Host smart-58b8e2ba-99e2-4a4f-a051-568816f0b8ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906560290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2906560290
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3207780423
Short name T105
Test name
Test status
Simulation time 110782053291 ps
CPU time 40.67 seconds
Started Jun 30 06:41:16 PM PDT 24
Finished Jun 30 06:41:57 PM PDT 24
Peak memory 198036 kb
Host smart-80382369-1f77-45a7-805c-acb17f88e39d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207780423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3207780423
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.22676690
Short name T138
Test name
Test status
Simulation time 373482456 ps
CPU time 1.19 seconds
Started Jun 30 06:41:23 PM PDT 24
Finished Jun 30 06:41:25 PM PDT 24
Peak memory 196508 kb
Host smart-3c36c1f2-11d6-4a6f-99a9-c9ca41ecc976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22676690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.22676690
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1349877440
Short name T49
Test name
Test status
Simulation time 195957632963 ps
CPU time 80.18 seconds
Started Jun 30 06:41:23 PM PDT 24
Finished Jun 30 06:42:44 PM PDT 24
Peak memory 198080 kb
Host smart-437c5ec3-3de8-469a-8b4d-4f1b714dfa00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349877440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1349877440
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3908882577
Short name T155
Test name
Test status
Simulation time 105381893543 ps
CPU time 223.16 seconds
Started Jun 30 06:40:42 PM PDT 24
Finished Jun 30 06:44:26 PM PDT 24
Peak memory 200284 kb
Host smart-450256e7-1745-49a3-bb28-6ec49ef545f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908882577 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3908882577
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.398753367
Short name T174
Test name
Test status
Simulation time 11429421564 ps
CPU time 113.38 seconds
Started Jun 30 06:40:47 PM PDT 24
Finished Jun 30 06:42:42 PM PDT 24
Peak memory 198384 kb
Host smart-4d293be2-73de-48ec-989f-410b77036911
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398753367 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.398753367
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3910589214
Short name T92
Test name
Test status
Simulation time 358622002996 ps
CPU time 150.43 seconds
Started Jun 30 06:40:52 PM PDT 24
Finished Jun 30 06:43:24 PM PDT 24
Peak memory 207668 kb
Host smart-91b90c76-e77e-4ca5-8b12-4308e143c6ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910589214 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3910589214
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1843801234
Short name T19
Test name
Test status
Simulation time 140474455318 ps
CPU time 113.21 seconds
Started Jun 30 06:40:52 PM PDT 24
Finished Jun 30 06:42:46 PM PDT 24
Peak memory 198048 kb
Host smart-27fc34c3-d5f7-423d-a9c8-120e511f6e7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843801234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1843801234
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2553262687
Short name T4
Test name
Test status
Simulation time 462134841 ps
CPU time 1.32 seconds
Started Jun 30 06:41:07 PM PDT 24
Finished Jun 30 06:41:08 PM PDT 24
Peak memory 196588 kb
Host smart-353f63b3-f901-4479-b27f-fd6079f1bb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553262687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2553262687
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3660469392
Short name T146
Test name
Test status
Simulation time 356749227 ps
CPU time 1.08 seconds
Started Jun 30 06:41:17 PM PDT 24
Finished Jun 30 06:41:18 PM PDT 24
Peak memory 196536 kb
Host smart-4cdf5bb5-936d-407d-8641-047386549aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660469392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3660469392
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.146358964
Short name T178
Test name
Test status
Simulation time 157282279988 ps
CPU time 108.29 seconds
Started Jun 30 06:41:14 PM PDT 24
Finished Jun 30 06:43:03 PM PDT 24
Peak memory 198008 kb
Host smart-72045e57-91b0-4933-b959-3999796e19fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146358964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.146358964
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1419630656
Short name T56
Test name
Test status
Simulation time 470852367 ps
CPU time 1.28 seconds
Started Jun 30 06:41:14 PM PDT 24
Finished Jun 30 06:41:16 PM PDT 24
Peak memory 196484 kb
Host smart-3bf9db09-7018-45f2-8d1e-c959602fc38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419630656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1419630656
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.280551069
Short name T89
Test name
Test status
Simulation time 402670758 ps
CPU time 0.88 seconds
Started Jun 30 06:40:34 PM PDT 24
Finished Jun 30 06:40:35 PM PDT 24
Peak memory 196488 kb
Host smart-dec6cd09-ba21-486e-9c72-2188a981bcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280551069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.280551069
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3651915504
Short name T118
Test name
Test status
Simulation time 547403205 ps
CPU time 0.77 seconds
Started Jun 30 06:40:24 PM PDT 24
Finished Jun 30 06:40:25 PM PDT 24
Peak memory 196572 kb
Host smart-c9650236-e8c6-42d9-a3a1-d5fe3a31b0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651915504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3651915504
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1526621719
Short name T28
Test name
Test status
Simulation time 435145323755 ps
CPU time 329.33 seconds
Started Jun 30 06:40:27 PM PDT 24
Finished Jun 30 06:45:57 PM PDT 24
Peak memory 192320 kb
Host smart-6e0646b9-6fa5-4750-b46e-63b9e74da14e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526621719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1526621719
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1127166405
Short name T140
Test name
Test status
Simulation time 64974507599 ps
CPU time 84.71 seconds
Started Jun 30 06:40:41 PM PDT 24
Finished Jun 30 06:42:07 PM PDT 24
Peak memory 198024 kb
Host smart-0057d10b-6386-4bc8-a3a7-962b8c31f40f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127166405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1127166405
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2928174419
Short name T134
Test name
Test status
Simulation time 474347442 ps
CPU time 0.95 seconds
Started Jun 30 06:40:28 PM PDT 24
Finished Jun 30 06:40:29 PM PDT 24
Peak memory 196572 kb
Host smart-2198e5c9-c0d9-4ef5-82e9-b41ae0375b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928174419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2928174419
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2719355253
Short name T132
Test name
Test status
Simulation time 392580126 ps
CPU time 0.75 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:41:03 PM PDT 24
Peak memory 196472 kb
Host smart-c4af1a83-c237-4a11-b774-031f0e4b32fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719355253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2719355253
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.137730828
Short name T160
Test name
Test status
Simulation time 115152036568 ps
CPU time 59.24 seconds
Started Jun 30 06:41:09 PM PDT 24
Finished Jun 30 06:42:09 PM PDT 24
Peak memory 193020 kb
Host smart-a916c982-d6f7-4d5c-a14c-4be4faac1e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137730828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.137730828
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.201739090
Short name T179
Test name
Test status
Simulation time 379756082825 ps
CPU time 242.75 seconds
Started Jun 30 06:40:48 PM PDT 24
Finished Jun 30 06:44:52 PM PDT 24
Peak memory 191704 kb
Host smart-dba504de-df3e-4a4a-82ae-036449f0a827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201739090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.201739090
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.259291716
Short name T183
Test name
Test status
Simulation time 63482990902 ps
CPU time 229.76 seconds
Started Jun 30 06:40:28 PM PDT 24
Finished Jun 30 06:44:18 PM PDT 24
Peak memory 207328 kb
Host smart-fabbd8f9-6b3f-4a90-92da-5490f919a754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259291716 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.259291716
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.464782789
Short name T161
Test name
Test status
Simulation time 114113349469 ps
CPU time 173.54 seconds
Started Jun 30 06:40:26 PM PDT 24
Finished Jun 30 06:43:20 PM PDT 24
Peak memory 208080 kb
Host smart-d5073fcc-d476-40db-b835-cc79fc6b91d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464782789 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.464782789
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3425957710
Short name T130
Test name
Test status
Simulation time 565069756 ps
CPU time 0.78 seconds
Started Jun 30 06:41:21 PM PDT 24
Finished Jun 30 06:41:22 PM PDT 24
Peak memory 196500 kb
Host smart-81ee77b6-7528-4f1f-a409-75fbdaf7668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425957710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3425957710
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3902960466
Short name T175
Test name
Test status
Simulation time 450970140 ps
CPU time 0.75 seconds
Started Jun 30 06:40:26 PM PDT 24
Finished Jun 30 06:40:27 PM PDT 24
Peak memory 196452 kb
Host smart-80c17901-5867-48b4-8af8-f2ac5cbbed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902960466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3902960466
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.4100328630
Short name T159
Test name
Test status
Simulation time 436003665 ps
CPU time 0.94 seconds
Started Jun 30 06:40:41 PM PDT 24
Finished Jun 30 06:40:43 PM PDT 24
Peak memory 196452 kb
Host smart-98acd2f3-be43-4c3e-b243-f50237687cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100328630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4100328630
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3918289837
Short name T177
Test name
Test status
Simulation time 459999411 ps
CPU time 1.19 seconds
Started Jun 30 06:40:45 PM PDT 24
Finished Jun 30 06:40:46 PM PDT 24
Peak memory 196532 kb
Host smart-7444ef39-7274-4e95-b961-13ddf2b077eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918289837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3918289837
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.815867040
Short name T188
Test name
Test status
Simulation time 375995296 ps
CPU time 1.18 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:40:56 PM PDT 24
Peak memory 196452 kb
Host smart-be573fbb-3e0d-4603-99f3-0c10a5e1cafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815867040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.815867040
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.541251513
Short name T173
Test name
Test status
Simulation time 431350766581 ps
CPU time 593.96 seconds
Started Jun 30 06:40:55 PM PDT 24
Finished Jun 30 06:50:51 PM PDT 24
Peak memory 192716 kb
Host smart-081e6623-0050-416d-87c0-00f4d3547330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541251513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.541251513
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1662358600
Short name T33
Test name
Test status
Simulation time 538849060 ps
CPU time 0.97 seconds
Started Jun 30 06:41:00 PM PDT 24
Finished Jun 30 06:41:02 PM PDT 24
Peak memory 196480 kb
Host smart-8e92ef71-ce5a-4461-92cd-829816098b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662358600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1662358600
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2796861053
Short name T139
Test name
Test status
Simulation time 439922915 ps
CPU time 0.62 seconds
Started Jun 30 06:41:08 PM PDT 24
Finished Jun 30 06:41:10 PM PDT 24
Peak memory 196476 kb
Host smart-371943af-4f85-4807-8dc0-eb444e41d9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796861053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2796861053
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.699538704
Short name T151
Test name
Test status
Simulation time 528328672 ps
CPU time 1.32 seconds
Started Jun 30 06:41:17 PM PDT 24
Finished Jun 30 06:41:19 PM PDT 24
Peak memory 196556 kb
Host smart-1348d632-8385-493d-9e4e-ef6d74a12309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699538704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.699538704
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.59506862
Short name T152
Test name
Test status
Simulation time 516697484 ps
CPU time 0.96 seconds
Started Jun 30 06:40:33 PM PDT 24
Finished Jun 30 06:40:35 PM PDT 24
Peak memory 196544 kb
Host smart-77dd4117-37a6-465b-b86c-769c6b2c32d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59506862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.59506862
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1866422667
Short name T189
Test name
Test status
Simulation time 433126742 ps
CPU time 1.25 seconds
Started Jun 30 06:40:35 PM PDT 24
Finished Jun 30 06:40:37 PM PDT 24
Peak memory 196384 kb
Host smart-4ecda2d0-9338-4205-9684-e912742948ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866422667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1866422667
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3010368623
Short name T55
Test name
Test status
Simulation time 572541483 ps
CPU time 0.94 seconds
Started Jun 30 06:40:43 PM PDT 24
Finished Jun 30 06:40:44 PM PDT 24
Peak memory 196560 kb
Host smart-0b89ab73-094c-4c71-9401-acf8152349ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010368623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3010368623
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3208049077
Short name T191
Test name
Test status
Simulation time 412835020 ps
CPU time 0.87 seconds
Started Jun 30 06:40:41 PM PDT 24
Finished Jun 30 06:40:43 PM PDT 24
Peak memory 196540 kb
Host smart-75835744-d303-4abe-b445-e649212cdbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208049077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3208049077
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3651920007
Short name T172
Test name
Test status
Simulation time 421487721 ps
CPU time 0.69 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:40:48 PM PDT 24
Peak memory 196472 kb
Host smart-fa75e7a5-2b11-470e-b1d2-3a2abe70cba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651920007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3651920007
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.670801872
Short name T7
Test name
Test status
Simulation time 498042483 ps
CPU time 0.82 seconds
Started Jun 30 06:40:26 PM PDT 24
Finished Jun 30 06:40:28 PM PDT 24
Peak memory 196480 kb
Host smart-432de958-c161-4c1c-82d9-2e2aaeff4a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670801872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.670801872
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2201544564
Short name T182
Test name
Test status
Simulation time 401981249 ps
CPU time 1.08 seconds
Started Jun 30 06:40:55 PM PDT 24
Finished Jun 30 06:40:58 PM PDT 24
Peak memory 196448 kb
Host smart-3a2b0ebb-6da5-4d67-83d1-cebc59de81b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201544564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2201544564
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1887678014
Short name T170
Test name
Test status
Simulation time 426489706 ps
CPU time 0.76 seconds
Started Jun 30 06:40:55 PM PDT 24
Finished Jun 30 06:40:57 PM PDT 24
Peak memory 196548 kb
Host smart-7115aabf-b60a-447a-9cc2-9cb5ea77d969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887678014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1887678014
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1639455618
Short name T141
Test name
Test status
Simulation time 431087403 ps
CPU time 0.68 seconds
Started Jun 30 06:40:56 PM PDT 24
Finished Jun 30 06:40:57 PM PDT 24
Peak memory 196560 kb
Host smart-cc5648e6-785b-4fa7-b0bb-8bfcf584d183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639455618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1639455618
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2416971401
Short name T24
Test name
Test status
Simulation time 202738799517 ps
CPU time 134.64 seconds
Started Jun 30 06:40:29 PM PDT 24
Finished Jun 30 06:42:44 PM PDT 24
Peak memory 198060 kb
Host smart-52d94c0e-cdac-47cd-9840-10a855ce06a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416971401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2416971401
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3608539941
Short name T8
Test name
Test status
Simulation time 534636994 ps
CPU time 0.8 seconds
Started Jun 30 06:41:03 PM PDT 24
Finished Jun 30 06:41:05 PM PDT 24
Peak memory 196408 kb
Host smart-58d7d634-ffeb-400b-a93c-c5a4112d4183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608539941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3608539941
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2489853744
Short name T163
Test name
Test status
Simulation time 439648081 ps
CPU time 1 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:41:04 PM PDT 24
Peak memory 196404 kb
Host smart-f99c19b3-32ee-42b6-b646-04cf095e164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489853744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2489853744
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.978961820
Short name T181
Test name
Test status
Simulation time 475295920 ps
CPU time 0.8 seconds
Started Jun 30 06:41:08 PM PDT 24
Finished Jun 30 06:41:10 PM PDT 24
Peak memory 196420 kb
Host smart-85d9eb5d-fbdf-449c-8af6-3e68e86f8667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978961820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.978961820
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.884724496
Short name T167
Test name
Test status
Simulation time 532573576510 ps
CPU time 682.24 seconds
Started Jun 30 06:41:07 PM PDT 24
Finished Jun 30 06:52:30 PM PDT 24
Peak memory 192196 kb
Host smart-13e71713-5a2e-404d-9f13-8c19416466c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884724496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.884724496
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1549364626
Short name T171
Test name
Test status
Simulation time 463484747 ps
CPU time 1.31 seconds
Started Jun 30 06:41:16 PM PDT 24
Finished Jun 30 06:41:18 PM PDT 24
Peak memory 196464 kb
Host smart-85ad13d7-1ca1-47df-a4f6-5fb59e583c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549364626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1549364626
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.444740988
Short name T156
Test name
Test status
Simulation time 420167927 ps
CPU time 0.75 seconds
Started Jun 30 06:41:14 PM PDT 24
Finished Jun 30 06:41:15 PM PDT 24
Peak memory 196444 kb
Host smart-95e7e3d1-ff20-4f3f-b408-a6ab2290b6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444740988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.444740988
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2010125100
Short name T85
Test name
Test status
Simulation time 459990771 ps
CPU time 0.76 seconds
Started Jun 30 06:41:27 PM PDT 24
Finished Jun 30 06:41:28 PM PDT 24
Peak memory 196524 kb
Host smart-3c16a021-ecda-4302-be2f-4bc0fd073fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010125100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2010125100
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.4160138373
Short name T169
Test name
Test status
Simulation time 37501000964 ps
CPU time 26.07 seconds
Started Jun 30 06:41:22 PM PDT 24
Finished Jun 30 06:41:49 PM PDT 24
Peak memory 192836 kb
Host smart-212cee05-2cdd-4b2e-837e-23bcfbb86d6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160138373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.4160138373
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2229470944
Short name T193
Test name
Test status
Simulation time 8208593077 ps
CPU time 3.9 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:04 PM PDT 24
Peak memory 198288 kb
Host smart-44a3b5d9-e6c5-4c38-9581-446c88ca6bb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229470944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2229470944
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1055745837
Short name T186
Test name
Test status
Simulation time 446443227 ps
CPU time 0.93 seconds
Started Jun 30 06:40:49 PM PDT 24
Finished Jun 30 06:40:50 PM PDT 24
Peak memory 196428 kb
Host smart-80f735fa-329a-49f6-9657-afd774eb08ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055745837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1055745837
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.720296547
Short name T187
Test name
Test status
Simulation time 286036312726 ps
CPU time 213.71 seconds
Started Jun 30 06:40:45 PM PDT 24
Finished Jun 30 06:44:20 PM PDT 24
Peak memory 198064 kb
Host smart-c6ec939d-9947-4cdc-a7f5-7fc6a4a5a1ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720296547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.720296547
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1903319198
Short name T185
Test name
Test status
Simulation time 369110547083 ps
CPU time 157.32 seconds
Started Jun 30 06:40:27 PM PDT 24
Finished Jun 30 06:43:05 PM PDT 24
Peak memory 191920 kb
Host smart-3e0c25bb-d0bd-419c-bd55-9ecb78c0fa9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903319198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1903319198
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2452417160
Short name T190
Test name
Test status
Simulation time 438808495 ps
CPU time 1.18 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:40:47 PM PDT 24
Peak memory 196432 kb
Host smart-d60b021e-2ee5-4275-b13d-2132b07f3e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452417160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2452417160
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3506213028
Short name T184
Test name
Test status
Simulation time 433276401 ps
CPU time 0.77 seconds
Started Jun 30 06:40:52 PM PDT 24
Finished Jun 30 06:40:54 PM PDT 24
Peak memory 196544 kb
Host smart-1de511fb-18a6-4fbb-b3bb-886d72402d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506213028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3506213028
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2290673192
Short name T158
Test name
Test status
Simulation time 448807672 ps
CPU time 1.21 seconds
Started Jun 30 06:41:09 PM PDT 24
Finished Jun 30 06:41:11 PM PDT 24
Peak memory 196536 kb
Host smart-aabb3baf-9402-4133-b2cd-5f8d77a153c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290673192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2290673192
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3748597466
Short name T154
Test name
Test status
Simulation time 380421667 ps
CPU time 0.74 seconds
Started Jun 30 06:40:33 PM PDT 24
Finished Jun 30 06:40:34 PM PDT 24
Peak memory 196440 kb
Host smart-e93c2edb-d6fb-4d20-8cac-68da4a7918a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748597466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3748597466
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3620417223
Short name T69
Test name
Test status
Simulation time 481555012 ps
CPU time 1.31 seconds
Started Jun 30 06:18:54 PM PDT 24
Finished Jun 30 06:18:57 PM PDT 24
Peak memory 193212 kb
Host smart-7b2941b1-c480-4a07-968b-240284c30c34
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620417223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3620417223
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2926959038
Short name T70
Test name
Test status
Simulation time 9278328581 ps
CPU time 3.34 seconds
Started Jun 30 06:18:53 PM PDT 24
Finished Jun 30 06:18:58 PM PDT 24
Peak memory 196104 kb
Host smart-83aec1ca-f9ca-4c41-b47e-1ff070457ff2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926959038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2926959038
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.486708910
Short name T63
Test name
Test status
Simulation time 775463887 ps
CPU time 0.82 seconds
Started Jun 30 06:18:52 PM PDT 24
Finished Jun 30 06:18:53 PM PDT 24
Peak memory 183756 kb
Host smart-71651069-42eb-4e84-ac27-3432a4230362
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486708910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.486708910
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2867403393
Short name T204
Test name
Test status
Simulation time 362331346 ps
CPU time 1.11 seconds
Started Jun 30 06:19:02 PM PDT 24
Finished Jun 30 06:19:03 PM PDT 24
Peak memory 196464 kb
Host smart-7d65997f-e9eb-4894-8b2f-e225139e8ad1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867403393 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2867403393
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3755853128
Short name T58
Test name
Test status
Simulation time 382338363 ps
CPU time 1.1 seconds
Started Jun 30 06:18:55 PM PDT 24
Finished Jun 30 06:18:58 PM PDT 24
Peak memory 193016 kb
Host smart-d8c8676b-42f2-4481-95b2-9f24b97ae7f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755853128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3755853128
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1922379193
Short name T304
Test name
Test status
Simulation time 470316121 ps
CPU time 1.24 seconds
Started Jun 30 06:18:54 PM PDT 24
Finished Jun 30 06:18:56 PM PDT 24
Peak memory 193200 kb
Host smart-bf720b25-0d49-422a-bf16-737f7973b4b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922379193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1922379193
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.327308709
Short name T381
Test name
Test status
Simulation time 298269223 ps
CPU time 0.66 seconds
Started Jun 30 06:18:54 PM PDT 24
Finished Jun 30 06:18:56 PM PDT 24
Peak memory 183736 kb
Host smart-b679a340-8b07-4c76-a77d-ba5eca813f82
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327308709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.327308709
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1000422874
Short name T328
Test name
Test status
Simulation time 265268268 ps
CPU time 0.88 seconds
Started Jun 30 06:18:58 PM PDT 24
Finished Jun 30 06:18:59 PM PDT 24
Peak memory 183744 kb
Host smart-048e4bac-ccbb-4aec-9e93-ac4c9941d7ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000422874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1000422874
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3382186725
Short name T351
Test name
Test status
Simulation time 2496916748 ps
CPU time 2.88 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:04 PM PDT 24
Peak memory 194032 kb
Host smart-8dfe47eb-5f0e-4c24-9819-3ff8ddd5edc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382186725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3382186725
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1266921712
Short name T419
Test name
Test status
Simulation time 546484172 ps
CPU time 1.81 seconds
Started Jun 30 06:18:58 PM PDT 24
Finished Jun 30 06:19:00 PM PDT 24
Peak memory 198460 kb
Host smart-4a130a07-04d5-4e40-ac0d-ccc8d63ec5f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266921712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1266921712
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3628031034
Short name T337
Test name
Test status
Simulation time 4546821272 ps
CPU time 1.58 seconds
Started Jun 30 06:18:53 PM PDT 24
Finished Jun 30 06:18:56 PM PDT 24
Peak memory 196808 kb
Host smart-373a7379-8d1a-494b-b024-61e161cc3272
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628031034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3628031034
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1904154392
Short name T418
Test name
Test status
Simulation time 553322518 ps
CPU time 1.08 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:01 PM PDT 24
Peak memory 183796 kb
Host smart-da4c067e-ea41-4eab-b001-c5b906a8f043
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904154392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1904154392
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1365304411
Short name T65
Test name
Test status
Simulation time 7013875874 ps
CPU time 9.38 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:10 PM PDT 24
Peak memory 192256 kb
Host smart-e6713dcb-06c1-4b4e-9245-78976aee34ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365304411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1365304411
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1767964343
Short name T398
Test name
Test status
Simulation time 1223965361 ps
CPU time 1.06 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:01 PM PDT 24
Peak memory 192984 kb
Host smart-0aa6badd-5cc9-43c5-b113-0980a739eb3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767964343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1767964343
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3394300682
Short name T369
Test name
Test status
Simulation time 591244418 ps
CPU time 1.66 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:01 PM PDT 24
Peak memory 196688 kb
Host smart-1ea3568d-f1b9-4f64-96d4-9a33599d71ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394300682 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3394300682
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.214595968
Short name T346
Test name
Test status
Simulation time 299625220 ps
CPU time 0.92 seconds
Started Jun 30 06:18:58 PM PDT 24
Finished Jun 30 06:18:59 PM PDT 24
Peak memory 193052 kb
Host smart-9b8ea22d-d738-4898-ada9-c7c4b470b40d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214595968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.214595968
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2508324038
Short name T397
Test name
Test status
Simulation time 544264047 ps
CPU time 0.71 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:02 PM PDT 24
Peak memory 183732 kb
Host smart-46e1d07a-b739-4120-b054-6acd1ab7f03c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508324038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2508324038
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2875358571
Short name T323
Test name
Test status
Simulation time 283535002 ps
CPU time 0.91 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:02 PM PDT 24
Peak memory 183708 kb
Host smart-896d4407-4780-4f80-8778-28561c8dc217
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875358571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2875358571
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.668077341
Short name T78
Test name
Test status
Simulation time 1553580146 ps
CPU time 1.25 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:02 PM PDT 24
Peak memory 193000 kb
Host smart-6d9959ae-dc30-4e11-bf9f-0d1791c70d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668077341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.668077341
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3204838944
Short name T302
Test name
Test status
Simulation time 653572609 ps
CPU time 1.44 seconds
Started Jun 30 06:18:57 PM PDT 24
Finished Jun 30 06:19:00 PM PDT 24
Peak memory 198676 kb
Host smart-b0078c73-ea32-45fc-86d1-72e6335ec7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204838944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3204838944
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2187599857
Short name T377
Test name
Test status
Simulation time 513797582 ps
CPU time 0.84 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:13 PM PDT 24
Peak memory 196444 kb
Host smart-01fcbd51-2e01-40cd-9dc7-6ba18467a0f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187599857 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2187599857
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3327480784
Short name T59
Test name
Test status
Simulation time 517586972 ps
CPU time 1.36 seconds
Started Jun 30 06:19:12 PM PDT 24
Finished Jun 30 06:19:14 PM PDT 24
Peak memory 193168 kb
Host smart-09a1b15b-16d9-42ab-9db5-7d40010738f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327480784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3327480784
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2881284492
Short name T317
Test name
Test status
Simulation time 497845642 ps
CPU time 0.71 seconds
Started Jun 30 06:19:13 PM PDT 24
Finished Jun 30 06:19:15 PM PDT 24
Peak memory 183844 kb
Host smart-363477d1-ca15-44bc-b1c6-59b15bfd7dbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881284492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2881284492
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4112120534
Short name T332
Test name
Test status
Simulation time 1503778041 ps
CPU time 0.91 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:12 PM PDT 24
Peak memory 194048 kb
Host smart-932c4652-e408-4a80-8068-0d35031c1ead
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112120534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.4112120534
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.204232866
Short name T389
Test name
Test status
Simulation time 571106744 ps
CPU time 2.13 seconds
Started Jun 30 06:19:14 PM PDT 24
Finished Jun 30 06:19:17 PM PDT 24
Peak memory 198644 kb
Host smart-3d9eb5aa-982e-49b7-ba89-190d6be05501
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204232866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.204232866
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.795485384
Short name T348
Test name
Test status
Simulation time 4657473204 ps
CPU time 1.72 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:12 PM PDT 24
Peak memory 196768 kb
Host smart-74569a2d-6b0a-492f-9dff-7760e54eebe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795485384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.795485384
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1165159809
Short name T359
Test name
Test status
Simulation time 402644113 ps
CPU time 1.25 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:13 PM PDT 24
Peak memory 195292 kb
Host smart-6b602ef4-5417-4405-8f82-698c098c527b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165159809 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1165159809
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4119563353
Short name T73
Test name
Test status
Simulation time 322869464 ps
CPU time 0.7 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:13 PM PDT 24
Peak memory 194032 kb
Host smart-374d2cc8-c4af-4ed4-b25f-c35a6008b8e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119563353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4119563353
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1218271641
Short name T399
Test name
Test status
Simulation time 426601675 ps
CPU time 0.6 seconds
Started Jun 30 06:19:12 PM PDT 24
Finished Jun 30 06:19:14 PM PDT 24
Peak memory 183844 kb
Host smart-b13e564d-7762-48d0-b6dc-db4c631f50d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218271641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1218271641
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1105274217
Short name T40
Test name
Test status
Simulation time 1197406731 ps
CPU time 2.07 seconds
Started Jun 30 06:19:13 PM PDT 24
Finished Jun 30 06:19:16 PM PDT 24
Peak memory 193664 kb
Host smart-ce2f026d-0778-4961-b539-0c2ee46e0427
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105274217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1105274217
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1939908144
Short name T402
Test name
Test status
Simulation time 911997189 ps
CPU time 2.34 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:15 PM PDT 24
Peak memory 198628 kb
Host smart-dea1fd0d-da10-4b79-b37a-fa006eaa81be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939908144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1939908144
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.452565905
Short name T38
Test name
Test status
Simulation time 4328932145 ps
CPU time 6.56 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:17 PM PDT 24
Peak memory 196488 kb
Host smart-ed246afc-9dbe-40c5-a864-644a93638939
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452565905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.452565905
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3113279395
Short name T415
Test name
Test status
Simulation time 394729021 ps
CPU time 0.9 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:13 PM PDT 24
Peak memory 196092 kb
Host smart-c053cf8c-7a15-431d-bc31-7e795203b513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113279395 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3113279395
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3625837767
Short name T335
Test name
Test status
Simulation time 445018794 ps
CPU time 0.74 seconds
Started Jun 30 06:19:12 PM PDT 24
Finished Jun 30 06:19:15 PM PDT 24
Peak memory 194028 kb
Host smart-38db273d-bbf4-4276-8cbe-a91514436665
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625837767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3625837767
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.190850409
Short name T392
Test name
Test status
Simulation time 537431212 ps
CPU time 0.74 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:11 PM PDT 24
Peak memory 193032 kb
Host smart-782f539e-63bb-4173-9fe4-cda7bfad64f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190850409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.190850409
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1203350890
Short name T79
Test name
Test status
Simulation time 751589444 ps
CPU time 1.17 seconds
Started Jun 30 06:19:12 PM PDT 24
Finished Jun 30 06:19:15 PM PDT 24
Peak memory 193736 kb
Host smart-a71064ae-c1ee-4a60-a311-e748ed7a2ffe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203350890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1203350890
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3625875094
Short name T292
Test name
Test status
Simulation time 752144625 ps
CPU time 2 seconds
Started Jun 30 06:19:12 PM PDT 24
Finished Jun 30 06:19:16 PM PDT 24
Peak memory 198692 kb
Host smart-921e86d2-da75-482a-8ac7-1cc234760a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625875094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3625875094
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.575136515
Short name T195
Test name
Test status
Simulation time 4613321967 ps
CPU time 2.23 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:15 PM PDT 24
Peak memory 197896 kb
Host smart-0b867597-d0ee-4358-b98f-6ffbfa4b15d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575136515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.575136515
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1807845820
Short name T301
Test name
Test status
Simulation time 493439125 ps
CPU time 1.43 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:13 PM PDT 24
Peak memory 196544 kb
Host smart-bfcf9467-d938-4745-bff9-a919268dbae1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807845820 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1807845820
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2859071471
Short name T287
Test name
Test status
Simulation time 297800187 ps
CPU time 1.1 seconds
Started Jun 30 06:19:12 PM PDT 24
Finished Jun 30 06:19:15 PM PDT 24
Peak memory 192084 kb
Host smart-06fef28e-f84b-47ed-ae7e-d74d56f912ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859071471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2859071471
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4020800618
Short name T375
Test name
Test status
Simulation time 510124360 ps
CPU time 0.89 seconds
Started Jun 30 06:19:12 PM PDT 24
Finished Jun 30 06:19:14 PM PDT 24
Peak memory 183820 kb
Host smart-77aa77fb-cb5d-4330-9db9-c295b64c60b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020800618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4020800618
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2066053386
Short name T360
Test name
Test status
Simulation time 1275031094 ps
CPU time 3.29 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:16 PM PDT 24
Peak memory 193048 kb
Host smart-eca261b4-241e-445a-8eab-e1d2c8b57cf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066053386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2066053386
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3839475585
Short name T394
Test name
Test status
Simulation time 921522671 ps
CPU time 1.08 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:14 PM PDT 24
Peak memory 198416 kb
Host smart-155af6b8-7a4f-48a9-aa3c-c146df57e5a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839475585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3839475585
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1881574064
Short name T325
Test name
Test status
Simulation time 8048329873 ps
CPU time 4.72 seconds
Started Jun 30 06:19:12 PM PDT 24
Finished Jun 30 06:19:18 PM PDT 24
Peak memory 198288 kb
Host smart-15bcb1d4-45e3-4cb0-b098-d61b4bdd30d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881574064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1881574064
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1464845559
Short name T357
Test name
Test status
Simulation time 520393536 ps
CPU time 1.47 seconds
Started Jun 30 06:19:18 PM PDT 24
Finished Jun 30 06:19:20 PM PDT 24
Peak memory 196068 kb
Host smart-4623f220-4ff6-4d4b-a9b5-d93ad99c1244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464845559 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1464845559
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2462800425
Short name T297
Test name
Test status
Simulation time 563568081 ps
CPU time 0.72 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:13 PM PDT 24
Peak memory 193312 kb
Host smart-1ddb6165-a627-493b-8155-31e834ceed7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462800425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2462800425
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.451363798
Short name T401
Test name
Test status
Simulation time 383405595 ps
CPU time 0.68 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:14 PM PDT 24
Peak memory 193020 kb
Host smart-342dfa27-6594-467a-bf18-af48c644494c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451363798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.451363798
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2470148117
Short name T374
Test name
Test status
Simulation time 1347215093 ps
CPU time 3.29 seconds
Started Jun 30 06:19:19 PM PDT 24
Finished Jun 30 06:19:22 PM PDT 24
Peak memory 193048 kb
Host smart-538e813e-d944-4dd4-a895-474754bd0969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470148117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2470148117
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1153342296
Short name T421
Test name
Test status
Simulation time 437669078 ps
CPU time 2.93 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:14 PM PDT 24
Peak memory 198624 kb
Host smart-478e06bb-b130-4f87-a4d3-92696ef9da19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153342296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1153342296
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3869623818
Short name T368
Test name
Test status
Simulation time 489227823 ps
CPU time 0.79 seconds
Started Jun 30 06:19:22 PM PDT 24
Finished Jun 30 06:19:23 PM PDT 24
Peak memory 196572 kb
Host smart-fee62913-be80-437f-ba00-bf67c4871ec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869623818 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3869623818
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3332364578
Short name T290
Test name
Test status
Simulation time 452625875 ps
CPU time 0.91 seconds
Started Jun 30 06:19:18 PM PDT 24
Finished Jun 30 06:19:19 PM PDT 24
Peak memory 193288 kb
Host smart-232f67a9-56cc-4917-89a1-6757b7c1a4b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332364578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3332364578
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3492108615
Short name T378
Test name
Test status
Simulation time 401869661 ps
CPU time 0.64 seconds
Started Jun 30 06:19:19 PM PDT 24
Finished Jun 30 06:19:20 PM PDT 24
Peak memory 193032 kb
Host smart-755fc799-6e85-4042-897a-bf5c7b579d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492108615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3492108615
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.535648458
Short name T411
Test name
Test status
Simulation time 1847152100 ps
CPU time 3.57 seconds
Started Jun 30 06:19:17 PM PDT 24
Finished Jun 30 06:19:21 PM PDT 24
Peak memory 195084 kb
Host smart-ed965684-0d6c-4944-bdab-8a7858d04fca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535648458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.535648458
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.735226566
Short name T362
Test name
Test status
Simulation time 525233891 ps
CPU time 2.48 seconds
Started Jun 30 06:19:16 PM PDT 24
Finished Jun 30 06:19:19 PM PDT 24
Peak memory 198880 kb
Host smart-30fc3173-fe5e-44c2-8d28-7147c60a8b6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735226566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.735226566
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2980662208
Short name T412
Test name
Test status
Simulation time 4356284906 ps
CPU time 1.62 seconds
Started Jun 30 06:19:19 PM PDT 24
Finished Jun 30 06:19:21 PM PDT 24
Peak memory 197904 kb
Host smart-81289f40-df04-4546-926a-ed2bc9ef011b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980662208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2980662208
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3079763248
Short name T408
Test name
Test status
Simulation time 532378585 ps
CPU time 1.45 seconds
Started Jun 30 06:19:20 PM PDT 24
Finished Jun 30 06:19:22 PM PDT 24
Peak memory 195780 kb
Host smart-d3087671-c069-485f-8ae0-28095e9acf89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079763248 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3079763248
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1764751439
Short name T68
Test name
Test status
Simulation time 395910107 ps
CPU time 1.15 seconds
Started Jun 30 06:19:24 PM PDT 24
Finished Jun 30 06:19:26 PM PDT 24
Peak memory 193272 kb
Host smart-3bcdd9e8-1e28-4f45-821e-3370affda598
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764751439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1764751439
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3580422227
Short name T361
Test name
Test status
Simulation time 449212351 ps
CPU time 0.89 seconds
Started Jun 30 06:19:16 PM PDT 24
Finished Jun 30 06:19:17 PM PDT 24
Peak memory 193020 kb
Host smart-7f9da181-e2f5-44e8-a809-9d8427eabe0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580422227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3580422227
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3191478795
Short name T75
Test name
Test status
Simulation time 2461049627 ps
CPU time 3.93 seconds
Started Jun 30 06:19:20 PM PDT 24
Finished Jun 30 06:19:24 PM PDT 24
Peak memory 194960 kb
Host smart-67674f3c-dd4b-4446-9c3e-21ae09bfc9f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191478795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3191478795
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4136031937
Short name T349
Test name
Test status
Simulation time 369670182 ps
CPU time 1.91 seconds
Started Jun 30 06:19:18 PM PDT 24
Finished Jun 30 06:19:20 PM PDT 24
Peak memory 198652 kb
Host smart-82da22c9-dd1b-458d-9517-5665d4197e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136031937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4136031937
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.910049901
Short name T196
Test name
Test status
Simulation time 7812933835 ps
CPU time 10.8 seconds
Started Jun 30 06:19:17 PM PDT 24
Finished Jun 30 06:19:29 PM PDT 24
Peak memory 198348 kb
Host smart-d2649ba8-38e8-4343-96ca-c2c70863733c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910049901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.910049901
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1061635811
Short name T420
Test name
Test status
Simulation time 414761891 ps
CPU time 0.97 seconds
Started Jun 30 06:19:17 PM PDT 24
Finished Jun 30 06:19:18 PM PDT 24
Peak memory 196060 kb
Host smart-a90cf22d-3eba-4861-b14b-145ae157a48b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061635811 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1061635811
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3354226638
Short name T60
Test name
Test status
Simulation time 428128429 ps
CPU time 0.88 seconds
Started Jun 30 06:19:19 PM PDT 24
Finished Jun 30 06:19:20 PM PDT 24
Peak memory 193032 kb
Host smart-ae0c2225-a33f-4e65-a8ac-062b49ba5add
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354226638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3354226638
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4175070174
Short name T364
Test name
Test status
Simulation time 365749223 ps
CPU time 0.68 seconds
Started Jun 30 06:19:17 PM PDT 24
Finished Jun 30 06:19:18 PM PDT 24
Peak memory 193012 kb
Host smart-297face6-71d0-438f-8dfa-6e6d4d732d2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175070174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.4175070174
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3306850617
Short name T80
Test name
Test status
Simulation time 2871816210 ps
CPU time 1.6 seconds
Started Jun 30 06:19:24 PM PDT 24
Finished Jun 30 06:19:26 PM PDT 24
Peak memory 195120 kb
Host smart-0efe9850-57af-4585-a797-4b1a7ebffd32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306850617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3306850617
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3830040339
Short name T380
Test name
Test status
Simulation time 326563273 ps
CPU time 1.55 seconds
Started Jun 30 06:19:24 PM PDT 24
Finished Jun 30 06:19:26 PM PDT 24
Peak memory 198540 kb
Host smart-98ef9781-613c-4272-acf3-794ddb48564f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830040339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3830040339
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2307351163
Short name T407
Test name
Test status
Simulation time 4167049254 ps
CPU time 3.71 seconds
Started Jun 30 06:19:19 PM PDT 24
Finished Jun 30 06:19:23 PM PDT 24
Peak memory 197800 kb
Host smart-038cfdcc-0571-4dbe-a3b3-b25f15ed1342
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307351163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2307351163
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.193037088
Short name T391
Test name
Test status
Simulation time 340528242 ps
CPU time 0.74 seconds
Started Jun 30 06:19:22 PM PDT 24
Finished Jun 30 06:19:23 PM PDT 24
Peak memory 195796 kb
Host smart-58c826f8-1b36-46f2-98f4-59421b8eb843
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193037088 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.193037088
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2736819018
Short name T74
Test name
Test status
Simulation time 569556575 ps
CPU time 0.83 seconds
Started Jun 30 06:19:17 PM PDT 24
Finished Jun 30 06:19:19 PM PDT 24
Peak memory 194032 kb
Host smart-a0506cb8-c308-44c6-8002-95978b6fb61c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736819018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2736819018
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2387867416
Short name T372
Test name
Test status
Simulation time 474828587 ps
CPU time 1.11 seconds
Started Jun 30 06:19:18 PM PDT 24
Finished Jun 30 06:19:19 PM PDT 24
Peak memory 183788 kb
Host smart-8b471a7e-3fc2-454c-9ab3-e1edb052786b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387867416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2387867416
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3965969905
Short name T393
Test name
Test status
Simulation time 1553194514 ps
CPU time 2.53 seconds
Started Jun 30 06:19:18 PM PDT 24
Finished Jun 30 06:19:21 PM PDT 24
Peak memory 194096 kb
Host smart-4b7bf67a-cc9d-41a0-9ede-b92e65c4cda6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965969905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3965969905
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2830981284
Short name T414
Test name
Test status
Simulation time 403034081 ps
CPU time 1.98 seconds
Started Jun 30 06:19:19 PM PDT 24
Finished Jun 30 06:19:21 PM PDT 24
Peak memory 198648 kb
Host smart-d5dc9517-4c21-4821-b1ac-7d0e3bdd6968
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830981284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2830981284
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1398952261
Short name T342
Test name
Test status
Simulation time 4247343749 ps
CPU time 6.83 seconds
Started Jun 30 06:19:20 PM PDT 24
Finished Jun 30 06:19:27 PM PDT 24
Peak memory 197596 kb
Host smart-610cad1c-6ef3-459d-b6bd-27c935d89cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398952261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1398952261
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3247150495
Short name T353
Test name
Test status
Simulation time 453017449 ps
CPU time 0.86 seconds
Started Jun 30 06:19:33 PM PDT 24
Finished Jun 30 06:19:36 PM PDT 24
Peak memory 197004 kb
Host smart-6aae255e-78b6-4f16-9410-78d50b90c6f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247150495 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3247150495
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2979102425
Short name T331
Test name
Test status
Simulation time 303941338 ps
CPU time 1.04 seconds
Started Jun 30 06:19:33 PM PDT 24
Finished Jun 30 06:19:35 PM PDT 24
Peak memory 194028 kb
Host smart-702052ec-f7d3-4d7e-aeac-ff3934f25adf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979102425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2979102425
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2586397327
Short name T406
Test name
Test status
Simulation time 363203074 ps
CPU time 0.68 seconds
Started Jun 30 06:19:19 PM PDT 24
Finished Jun 30 06:19:20 PM PDT 24
Peak memory 193004 kb
Host smart-20bc3ba1-c409-4057-aeae-e04ac854ee6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586397327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2586397327
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1757788172
Short name T77
Test name
Test status
Simulation time 1003155867 ps
CPU time 1.11 seconds
Started Jun 30 06:19:37 PM PDT 24
Finished Jun 30 06:19:42 PM PDT 24
Peak memory 194080 kb
Host smart-4076fc5f-9976-4bd4-ab0d-c857a80de0df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757788172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1757788172
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3674059265
Short name T289
Test name
Test status
Simulation time 611732662 ps
CPU time 2.01 seconds
Started Jun 30 06:19:18 PM PDT 24
Finished Jun 30 06:19:20 PM PDT 24
Peak memory 198668 kb
Host smart-47dbeb9b-afcf-4be8-8ce7-9ea627ba4d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674059265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3674059265
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2927839673
Short name T322
Test name
Test status
Simulation time 4414341408 ps
CPU time 3.24 seconds
Started Jun 30 06:19:25 PM PDT 24
Finished Jun 30 06:19:28 PM PDT 24
Peak memory 196504 kb
Host smart-4533f445-77b2-4daf-b1ce-f0db37da771e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927839673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2927839673
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1090822580
Short name T36
Test name
Test status
Simulation time 518669051 ps
CPU time 1.38 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:02 PM PDT 24
Peak memory 183828 kb
Host smart-3f4b3433-8a5b-470d-8a12-3354216f411f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090822580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1090822580
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3416536635
Short name T417
Test name
Test status
Simulation time 7522177398 ps
CPU time 20.42 seconds
Started Jun 30 06:19:00 PM PDT 24
Finished Jun 30 06:19:22 PM PDT 24
Peak memory 195896 kb
Host smart-73c1373b-f5ea-4260-9991-6dbe02426977
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416536635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3416536635
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.549105168
Short name T386
Test name
Test status
Simulation time 1040061967 ps
CPU time 1.3 seconds
Started Jun 30 06:19:04 PM PDT 24
Finished Jun 30 06:19:06 PM PDT 24
Peak memory 183824 kb
Host smart-6b95819b-5fab-41ed-b344-71d11ca40f88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549105168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.549105168
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.316890197
Short name T363
Test name
Test status
Simulation time 427626266 ps
CPU time 1 seconds
Started Jun 30 06:18:57 PM PDT 24
Finished Jun 30 06:18:59 PM PDT 24
Peak memory 197280 kb
Host smart-a563320a-cd55-4d59-84a4-beb91f59642f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316890197 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.316890197
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2955147660
Short name T71
Test name
Test status
Simulation time 471112114 ps
CPU time 0.76 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:01 PM PDT 24
Peak memory 193304 kb
Host smart-8a9e8857-bf2d-4359-ae02-4279cfb80c3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955147660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2955147660
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1121425786
Short name T305
Test name
Test status
Simulation time 350336034 ps
CPU time 0.71 seconds
Started Jun 30 06:18:57 PM PDT 24
Finished Jun 30 06:18:59 PM PDT 24
Peak memory 183828 kb
Host smart-fbe091d4-efac-4a7f-870a-f2614a244821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121425786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1121425786
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.288292653
Short name T313
Test name
Test status
Simulation time 421820071 ps
CPU time 0.7 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:02 PM PDT 24
Peak memory 183720 kb
Host smart-32d15a64-5e4c-4b8e-a6d7-1dda8fd5f1fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288292653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.288292653
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.737545817
Short name T373
Test name
Test status
Simulation time 567952701 ps
CPU time 0.57 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:00 PM PDT 24
Peak memory 183736 kb
Host smart-364c0093-dd4e-4d73-9a48-334991573d68
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737545817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.737545817
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3442706660
Short name T352
Test name
Test status
Simulation time 2649203212 ps
CPU time 4.19 seconds
Started Jun 30 06:19:01 PM PDT 24
Finished Jun 30 06:19:06 PM PDT 24
Peak memory 194228 kb
Host smart-ab8a1928-ddca-4221-90c4-44d7759a346a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442706660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3442706660
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3457684218
Short name T355
Test name
Test status
Simulation time 455671125 ps
CPU time 2.57 seconds
Started Jun 30 06:19:00 PM PDT 24
Finished Jun 30 06:19:04 PM PDT 24
Peak memory 198672 kb
Host smart-ea810a81-2932-483c-8a09-87aee5b443da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457684218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3457684218
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3253740719
Short name T324
Test name
Test status
Simulation time 4089718268 ps
CPU time 2.63 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:03 PM PDT 24
Peak memory 197832 kb
Host smart-c16ffd37-11d1-4195-b2fd-85b124f797db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253740719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3253740719
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1201070189
Short name T409
Test name
Test status
Simulation time 481961801 ps
CPU time 1.31 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:40 PM PDT 24
Peak memory 183804 kb
Host smart-23d87cce-f41d-4654-9124-495b467c14e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201070189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1201070189
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2868498467
Short name T376
Test name
Test status
Simulation time 440975687 ps
CPU time 0.67 seconds
Started Jun 30 06:19:34 PM PDT 24
Finished Jun 30 06:19:37 PM PDT 24
Peak memory 183788 kb
Host smart-b611766a-81df-47bd-b408-87b5a37be66e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868498467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2868498467
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2849331779
Short name T350
Test name
Test status
Simulation time 509656736 ps
CPU time 1.24 seconds
Started Jun 30 06:19:35 PM PDT 24
Finished Jun 30 06:19:39 PM PDT 24
Peak memory 183820 kb
Host smart-69ba12ec-e839-43ae-9705-9ef8c3863dfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849331779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2849331779
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3329479900
Short name T384
Test name
Test status
Simulation time 355342568 ps
CPU time 0.64 seconds
Started Jun 30 06:19:33 PM PDT 24
Finished Jun 30 06:19:34 PM PDT 24
Peak memory 193044 kb
Host smart-015516a1-ee6a-4d49-95ff-b0608f84644d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329479900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3329479900
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4028500263
Short name T309
Test name
Test status
Simulation time 460559894 ps
CPU time 1.28 seconds
Started Jun 30 06:19:39 PM PDT 24
Finished Jun 30 06:19:44 PM PDT 24
Peak memory 183812 kb
Host smart-b12d66cd-c4d2-49f5-b428-2e11eb2c1385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028500263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4028500263
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1912924636
Short name T311
Test name
Test status
Simulation time 295765332 ps
CPU time 0.94 seconds
Started Jun 30 06:19:37 PM PDT 24
Finished Jun 30 06:19:42 PM PDT 24
Peak memory 183844 kb
Host smart-7b71e809-0806-40b2-9b06-3f6dbfb83a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912924636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1912924636
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1225990300
Short name T366
Test name
Test status
Simulation time 466867490 ps
CPU time 0.69 seconds
Started Jun 30 06:19:34 PM PDT 24
Finished Jun 30 06:19:36 PM PDT 24
Peak memory 183820 kb
Host smart-7149ae9f-bfd7-48a7-90f2-60546b900667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225990300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1225990300
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3784535689
Short name T344
Test name
Test status
Simulation time 491120019 ps
CPU time 0.96 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:41 PM PDT 24
Peak memory 193068 kb
Host smart-0ecc222e-c20b-4f88-b347-cf136de60571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784535689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3784535689
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1428798085
Short name T382
Test name
Test status
Simulation time 309973253 ps
CPU time 0.68 seconds
Started Jun 30 06:19:34 PM PDT 24
Finished Jun 30 06:19:35 PM PDT 24
Peak memory 183808 kb
Host smart-4ba83925-555e-4d39-95f7-265de5c60d75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428798085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1428798085
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.535480485
Short name T339
Test name
Test status
Simulation time 462051009 ps
CPU time 1.14 seconds
Started Jun 30 06:19:34 PM PDT 24
Finished Jun 30 06:19:36 PM PDT 24
Peak memory 193048 kb
Host smart-b7f6785b-8ba1-49f1-a897-8604a3e32d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535480485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.535480485
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2502667209
Short name T285
Test name
Test status
Simulation time 567570104 ps
CPU time 0.86 seconds
Started Jun 30 06:19:08 PM PDT 24
Finished Jun 30 06:19:10 PM PDT 24
Peak memory 194640 kb
Host smart-a40152dc-ee71-426a-aedc-18a389691e28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502667209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2502667209
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3177288462
Short name T388
Test name
Test status
Simulation time 7114112442 ps
CPU time 5.85 seconds
Started Jun 30 06:19:04 PM PDT 24
Finished Jun 30 06:19:11 PM PDT 24
Peak memory 192212 kb
Host smart-c271f1c0-3e6f-4970-b251-1383e3eb1f32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177288462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3177288462
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3825252742
Short name T404
Test name
Test status
Simulation time 762193647 ps
CPU time 0.89 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:12 PM PDT 24
Peak memory 193036 kb
Host smart-a907a7fd-7add-4a7c-bcd1-25215d2d1eed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825252742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3825252742
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1713151744
Short name T35
Test name
Test status
Simulation time 432893006 ps
CPU time 0.84 seconds
Started Jun 30 06:19:13 PM PDT 24
Finished Jun 30 06:19:15 PM PDT 24
Peak memory 197076 kb
Host smart-379db69d-2ee6-4835-b3d1-cec7501c4d99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713151744 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1713151744
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3430858595
Short name T61
Test name
Test status
Simulation time 287430034 ps
CPU time 0.97 seconds
Started Jun 30 06:19:09 PM PDT 24
Finished Jun 30 06:19:10 PM PDT 24
Peak memory 193016 kb
Host smart-a5a0b392-6f41-4eac-bda2-9319f6ac1c07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430858595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3430858595
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3488122901
Short name T293
Test name
Test status
Simulation time 324320670 ps
CPU time 0.79 seconds
Started Jun 30 06:19:01 PM PDT 24
Finished Jun 30 06:19:03 PM PDT 24
Peak memory 183820 kb
Host smart-5149997b-9842-4045-9418-287e662a33b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488122901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3488122901
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2554735082
Short name T306
Test name
Test status
Simulation time 393904301 ps
CPU time 0.77 seconds
Started Jun 30 06:19:08 PM PDT 24
Finished Jun 30 06:19:10 PM PDT 24
Peak memory 183736 kb
Host smart-84adcda8-4375-4f6b-9e85-f5340aa7b88f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554735082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2554735082
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.989883784
Short name T338
Test name
Test status
Simulation time 445448744 ps
CPU time 1.12 seconds
Started Jun 30 06:19:05 PM PDT 24
Finished Jun 30 06:19:08 PM PDT 24
Peak memory 183748 kb
Host smart-29a31601-a4ac-4695-8ebb-d2b970325471
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989883784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.989883784
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1338947032
Short name T345
Test name
Test status
Simulation time 2499815576 ps
CPU time 1.43 seconds
Started Jun 30 06:19:14 PM PDT 24
Finished Jun 30 06:19:16 PM PDT 24
Peak memory 194812 kb
Host smart-76044361-682e-4ba4-a804-699b92980eb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338947032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1338947032
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3028400909
Short name T288
Test name
Test status
Simulation time 347359516 ps
CPU time 2.85 seconds
Started Jun 30 06:19:01 PM PDT 24
Finished Jun 30 06:19:05 PM PDT 24
Peak memory 198672 kb
Host smart-83a49528-b27f-4560-9e84-efc6bbccac2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028400909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3028400909
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1782722810
Short name T390
Test name
Test status
Simulation time 4034262678 ps
CPU time 3.16 seconds
Started Jun 30 06:18:59 PM PDT 24
Finished Jun 30 06:19:04 PM PDT 24
Peak memory 197708 kb
Host smart-559611af-5ddf-4912-8db3-44529b63a4d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782722810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1782722810
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3705257763
Short name T329
Test name
Test status
Simulation time 348133686 ps
CPU time 0.84 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:40 PM PDT 24
Peak memory 183980 kb
Host smart-0f10af02-7b39-4543-8dcb-ca1e17ccb852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705257763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3705257763
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4137063467
Short name T371
Test name
Test status
Simulation time 382746146 ps
CPU time 0.67 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:40 PM PDT 24
Peak memory 193024 kb
Host smart-9deff438-4d5a-47c0-8791-0a20fb1c3f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137063467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.4137063467
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1716468270
Short name T370
Test name
Test status
Simulation time 513659679 ps
CPU time 1.24 seconds
Started Jun 30 06:19:34 PM PDT 24
Finished Jun 30 06:19:37 PM PDT 24
Peak memory 183820 kb
Host smart-cd860067-7432-4d77-a39f-0cdea48a0194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716468270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1716468270
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1254040999
Short name T320
Test name
Test status
Simulation time 437839341 ps
CPU time 0.72 seconds
Started Jun 30 06:19:33 PM PDT 24
Finished Jun 30 06:19:35 PM PDT 24
Peak memory 183804 kb
Host smart-ec35da50-95a7-4a3d-9ccf-efcc1501e43a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254040999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1254040999
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1929222151
Short name T333
Test name
Test status
Simulation time 492009811 ps
CPU time 1.24 seconds
Started Jun 30 06:19:38 PM PDT 24
Finished Jun 30 06:19:43 PM PDT 24
Peak memory 193056 kb
Host smart-93e19aaa-0c9f-490d-8f56-6a1cea320cbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929222151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1929222151
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1763741448
Short name T327
Test name
Test status
Simulation time 436513325 ps
CPU time 0.7 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:39 PM PDT 24
Peak memory 183980 kb
Host smart-947208ff-65f4-4952-8c1f-44761d2ca251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763741448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1763741448
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2195481775
Short name T318
Test name
Test status
Simulation time 294912595 ps
CPU time 0.69 seconds
Started Jun 30 06:19:37 PM PDT 24
Finished Jun 30 06:19:42 PM PDT 24
Peak memory 183796 kb
Host smart-baae83c1-7193-4129-9a04-f91a1eebdda3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195481775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2195481775
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.987789758
Short name T299
Test name
Test status
Simulation time 439456850 ps
CPU time 0.83 seconds
Started Jun 30 06:19:33 PM PDT 24
Finished Jun 30 06:19:34 PM PDT 24
Peak memory 183828 kb
Host smart-3ce070ed-57fd-4182-8238-a392afddd64d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987789758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.987789758
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.396451983
Short name T340
Test name
Test status
Simulation time 280552926 ps
CPU time 0.64 seconds
Started Jun 30 06:19:39 PM PDT 24
Finished Jun 30 06:19:43 PM PDT 24
Peak memory 193032 kb
Host smart-8d3ac1e8-8fab-4a37-a139-0031277f37ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396451983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.396451983
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1792709281
Short name T334
Test name
Test status
Simulation time 349788756 ps
CPU time 1.02 seconds
Started Jun 30 06:19:37 PM PDT 24
Finished Jun 30 06:19:41 PM PDT 24
Peak memory 193024 kb
Host smart-7dc56ffb-3909-4ce3-b0f7-776e3efba998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792709281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1792709281
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.88879861
Short name T67
Test name
Test status
Simulation time 577107423 ps
CPU time 0.97 seconds
Started Jun 30 06:19:06 PM PDT 24
Finished Jun 30 06:19:09 PM PDT 24
Peak memory 194452 kb
Host smart-196a7f1a-9591-4789-9e4c-ab9fd9e93184
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88879861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_ali
asing.88879861
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4156305478
Short name T298
Test name
Test status
Simulation time 7287075246 ps
CPU time 2.9 seconds
Started Jun 30 06:19:04 PM PDT 24
Finished Jun 30 06:19:07 PM PDT 24
Peak memory 184048 kb
Host smart-ac441760-76d7-43be-a9ab-f72f68a60262
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156305478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.4156305478
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.815366268
Short name T310
Test name
Test status
Simulation time 597971874 ps
CPU time 0.74 seconds
Started Jun 30 06:19:04 PM PDT 24
Finished Jun 30 06:19:05 PM PDT 24
Peak memory 183804 kb
Host smart-fb811bfd-a2cc-45e0-9591-b023c690a961
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815366268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.815366268
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.186565993
Short name T284
Test name
Test status
Simulation time 639025208 ps
CPU time 1.11 seconds
Started Jun 30 06:19:04 PM PDT 24
Finished Jun 30 06:19:06 PM PDT 24
Peak memory 198480 kb
Host smart-8f8456cd-ce7b-4eda-91ae-8117981195f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186565993 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.186565993
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1796459445
Short name T405
Test name
Test status
Simulation time 550835837 ps
CPU time 1.13 seconds
Started Jun 30 06:19:05 PM PDT 24
Finished Jun 30 06:19:08 PM PDT 24
Peak memory 193252 kb
Host smart-53700f0b-399d-4fd3-b7a7-66674dc7dd20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796459445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1796459445
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2702164783
Short name T387
Test name
Test status
Simulation time 480369322 ps
CPU time 1.27 seconds
Started Jun 30 06:19:05 PM PDT 24
Finished Jun 30 06:19:08 PM PDT 24
Peak memory 183804 kb
Host smart-1b1ae933-0b12-481b-8a77-adcc2e7516e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702164783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2702164783
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3023393641
Short name T326
Test name
Test status
Simulation time 336223240 ps
CPU time 0.98 seconds
Started Jun 30 06:19:05 PM PDT 24
Finished Jun 30 06:19:07 PM PDT 24
Peak memory 183716 kb
Host smart-df0511f0-f41f-4676-a237-5e9b8892461d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023393641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3023393641
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1995559551
Short name T312
Test name
Test status
Simulation time 391986419 ps
CPU time 0.73 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:12 PM PDT 24
Peak memory 183744 kb
Host smart-805bf1ec-18e8-49fb-a787-8948569d0ed4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995559551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1995559551
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2212375884
Short name T319
Test name
Test status
Simulation time 1333345522 ps
CPU time 1.48 seconds
Started Jun 30 06:19:14 PM PDT 24
Finished Jun 30 06:19:16 PM PDT 24
Peak memory 193416 kb
Host smart-7a6bbbec-770a-473f-aa78-90be0a4391b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212375884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2212375884
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4054991311
Short name T400
Test name
Test status
Simulation time 587616173 ps
CPU time 2.45 seconds
Started Jun 30 06:19:07 PM PDT 24
Finished Jun 30 06:19:11 PM PDT 24
Peak memory 198636 kb
Host smart-ae340602-879f-4626-a1bb-a9a1e00e4fad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054991311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4054991311
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1435237848
Short name T296
Test name
Test status
Simulation time 4494686519 ps
CPU time 6.89 seconds
Started Jun 30 06:19:08 PM PDT 24
Finished Jun 30 06:19:15 PM PDT 24
Peak memory 197908 kb
Host smart-a3c0c718-162e-475a-b0e2-5b44466b7eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435237848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1435237848
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4226588333
Short name T294
Test name
Test status
Simulation time 389143833 ps
CPU time 0.67 seconds
Started Jun 30 06:19:35 PM PDT 24
Finished Jun 30 06:19:39 PM PDT 24
Peak memory 183840 kb
Host smart-0f628cee-64c3-4691-af29-f1e2e6488225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226588333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4226588333
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.455691895
Short name T315
Test name
Test status
Simulation time 342787938 ps
CPU time 0.88 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:40 PM PDT 24
Peak memory 193044 kb
Host smart-ec2d4428-4a8c-4016-ae0e-c25d35573627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455691895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.455691895
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3920608301
Short name T303
Test name
Test status
Simulation time 512485928 ps
CPU time 1.15 seconds
Started Jun 30 06:19:35 PM PDT 24
Finished Jun 30 06:19:38 PM PDT 24
Peak memory 183788 kb
Host smart-ec8123f7-86a4-4538-a1b9-ee6b405acb5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920608301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3920608301
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3648066858
Short name T308
Test name
Test status
Simulation time 429529765 ps
CPU time 0.67 seconds
Started Jun 30 06:19:33 PM PDT 24
Finished Jun 30 06:19:35 PM PDT 24
Peak memory 183828 kb
Host smart-f97470ef-866f-4103-ae98-cbcdfbe4b6c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648066858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3648066858
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.914666641
Short name T286
Test name
Test status
Simulation time 322009751 ps
CPU time 0.64 seconds
Started Jun 30 06:19:35 PM PDT 24
Finished Jun 30 06:19:37 PM PDT 24
Peak memory 183768 kb
Host smart-89e7b489-8803-4b6a-8c62-74ad32c59334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914666641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.914666641
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.791099694
Short name T413
Test name
Test status
Simulation time 358822498 ps
CPU time 0.61 seconds
Started Jun 30 06:19:36 PM PDT 24
Finished Jun 30 06:19:40 PM PDT 24
Peak memory 183848 kb
Host smart-14cea266-8119-48f2-b612-540a0ca0c178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791099694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.791099694
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2880586230
Short name T295
Test name
Test status
Simulation time 298609580 ps
CPU time 0.71 seconds
Started Jun 30 06:19:37 PM PDT 24
Finished Jun 30 06:19:41 PM PDT 24
Peak memory 183804 kb
Host smart-a43a465b-c01e-4e46-84ad-e57abebff334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880586230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2880586230
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.101186536
Short name T385
Test name
Test status
Simulation time 414680406 ps
CPU time 1.13 seconds
Started Jun 30 06:19:33 PM PDT 24
Finished Jun 30 06:19:34 PM PDT 24
Peak memory 183820 kb
Host smart-4f737ebb-ee70-41b4-b270-01d00c1743a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101186536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.101186536
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.334481675
Short name T358
Test name
Test status
Simulation time 376945941 ps
CPU time 0.74 seconds
Started Jun 30 06:19:33 PM PDT 24
Finished Jun 30 06:19:35 PM PDT 24
Peak memory 183820 kb
Host smart-fc802250-1f33-415c-ac21-744f20dc2a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334481675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.334481675
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1757009477
Short name T379
Test name
Test status
Simulation time 323104774 ps
CPU time 0.97 seconds
Started Jun 30 06:19:37 PM PDT 24
Finished Jun 30 06:19:42 PM PDT 24
Peak memory 183832 kb
Host smart-70ee7cf2-4a02-452d-8133-ff8b4efb1cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757009477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1757009477
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.165939521
Short name T403
Test name
Test status
Simulation time 667647011 ps
CPU time 1.1 seconds
Started Jun 30 06:19:14 PM PDT 24
Finished Jun 30 06:19:16 PM PDT 24
Peak memory 198440 kb
Host smart-e79d4ab5-a686-46d8-83fa-3bf91978a858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165939521 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.165939521
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.317353792
Short name T66
Test name
Test status
Simulation time 403883406 ps
CPU time 1.1 seconds
Started Jun 30 06:19:04 PM PDT 24
Finished Jun 30 06:19:06 PM PDT 24
Peak memory 192056 kb
Host smart-d01724b6-2c11-4132-9003-ed652c11cecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317353792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.317353792
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1915030995
Short name T291
Test name
Test status
Simulation time 355986075 ps
CPU time 1.09 seconds
Started Jun 30 06:19:05 PM PDT 24
Finished Jun 30 06:19:08 PM PDT 24
Peak memory 183980 kb
Host smart-749544b3-aa9c-4410-a160-252104ce8799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915030995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1915030995
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4280631888
Short name T341
Test name
Test status
Simulation time 1150428574 ps
CPU time 2.54 seconds
Started Jun 30 06:19:05 PM PDT 24
Finished Jun 30 06:19:09 PM PDT 24
Peak memory 192016 kb
Host smart-9350f6d3-188f-4bfd-8482-8f273d2df089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280631888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.4280631888
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3504821423
Short name T367
Test name
Test status
Simulation time 491311044 ps
CPU time 1.53 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:13 PM PDT 24
Peak memory 198680 kb
Host smart-cf0bbf22-328a-4227-9439-81cf741d9c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504821423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3504821423
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.180450312
Short name T194
Test name
Test status
Simulation time 4117640282 ps
CPU time 7.42 seconds
Started Jun 30 06:19:04 PM PDT 24
Finished Jun 30 06:19:12 PM PDT 24
Peak memory 198204 kb
Host smart-7ee72127-77ac-4d70-829f-be02e9c749fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180450312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.180450312
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1488461506
Short name T300
Test name
Test status
Simulation time 403526488 ps
CPU time 1.13 seconds
Started Jun 30 06:19:06 PM PDT 24
Finished Jun 30 06:19:09 PM PDT 24
Peak memory 195992 kb
Host smart-9550ca1d-c222-41f5-bde7-5a15d1ce1e27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488461506 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1488461506
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2482050242
Short name T316
Test name
Test status
Simulation time 302520035 ps
CPU time 0.73 seconds
Started Jun 30 06:19:04 PM PDT 24
Finished Jun 30 06:19:07 PM PDT 24
Peak memory 193024 kb
Host smart-74f44f8d-f3c3-4034-96c3-3c363923eee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482050242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2482050242
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.664854670
Short name T395
Test name
Test status
Simulation time 399147358 ps
CPU time 0.62 seconds
Started Jun 30 06:19:03 PM PDT 24
Finished Jun 30 06:19:04 PM PDT 24
Peak memory 193004 kb
Host smart-5cf020eb-1f41-4897-bd1b-0c41789ab848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664854670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.664854670
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1370648942
Short name T343
Test name
Test status
Simulation time 2578339072 ps
CPU time 3.38 seconds
Started Jun 30 06:19:06 PM PDT 24
Finished Jun 30 06:19:11 PM PDT 24
Peak memory 193988 kb
Host smart-a815b16a-c693-419c-beef-e21d7204a392
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370648942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1370648942
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.931602669
Short name T307
Test name
Test status
Simulation time 632815150 ps
CPU time 1.47 seconds
Started Jun 30 06:19:05 PM PDT 24
Finished Jun 30 06:19:08 PM PDT 24
Peak memory 198628 kb
Host smart-111ae20d-548e-4600-9312-9e8edfe17aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931602669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.931602669
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2117009767
Short name T197
Test name
Test status
Simulation time 4216506998 ps
CPU time 6.72 seconds
Started Jun 30 06:19:05 PM PDT 24
Finished Jun 30 06:19:14 PM PDT 24
Peak memory 196520 kb
Host smart-1109d64e-1c13-404f-a4c7-2d67aee4caaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117009767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2117009767
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4277217138
Short name T410
Test name
Test status
Simulation time 925524087 ps
CPU time 0.89 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:14 PM PDT 24
Peak memory 198432 kb
Host smart-f4700208-a1a4-4458-b228-5daddaabf28c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277217138 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.4277217138
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2716636929
Short name T356
Test name
Test status
Simulation time 327733676 ps
CPU time 0.68 seconds
Started Jun 30 06:19:05 PM PDT 24
Finished Jun 30 06:19:07 PM PDT 24
Peak memory 193048 kb
Host smart-4b403691-9ba1-46e7-9ebd-d6c855007bcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716636929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2716636929
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1488960861
Short name T283
Test name
Test status
Simulation time 328364896 ps
CPU time 0.62 seconds
Started Jun 30 06:19:13 PM PDT 24
Finished Jun 30 06:19:15 PM PDT 24
Peak memory 193040 kb
Host smart-dae15e63-8c79-49dd-8b00-252c7ba0e9cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488960861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1488960861
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.569039039
Short name T321
Test name
Test status
Simulation time 792997572 ps
CPU time 1.56 seconds
Started Jun 30 06:19:09 PM PDT 24
Finished Jun 30 06:19:12 PM PDT 24
Peak memory 193560 kb
Host smart-6cefffe5-76ea-44e1-89f7-fc894c4c8126
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569039039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.569039039
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3583164967
Short name T336
Test name
Test status
Simulation time 538587483 ps
CPU time 2.16 seconds
Started Jun 30 06:19:13 PM PDT 24
Finished Jun 30 06:19:17 PM PDT 24
Peak memory 198620 kb
Host smart-e5b22020-01b6-4b08-9f54-a23f6325d606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583164967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3583164967
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2840462481
Short name T37
Test name
Test status
Simulation time 10563584585 ps
CPU time 2.21 seconds
Started Jun 30 06:19:05 PM PDT 24
Finished Jun 30 06:19:09 PM PDT 24
Peak memory 198124 kb
Host smart-1295d471-fb67-4c3e-b7e5-47d642f1d49b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840462481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2840462481
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2062342608
Short name T330
Test name
Test status
Simulation time 443371541 ps
CPU time 0.98 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:13 PM PDT 24
Peak memory 195732 kb
Host smart-e38d9d44-2c93-45d0-b9ec-8d367181b7ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062342608 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2062342608
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1563093508
Short name T72
Test name
Test status
Simulation time 441852209 ps
CPU time 1.28 seconds
Started Jun 30 06:19:13 PM PDT 24
Finished Jun 30 06:19:16 PM PDT 24
Peak memory 193344 kb
Host smart-328d102f-bd03-4d6f-b44e-5772a8ab3fb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563093508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1563093508
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1670234716
Short name T416
Test name
Test status
Simulation time 503626697 ps
CPU time 1.19 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:12 PM PDT 24
Peak memory 183840 kb
Host smart-58862158-43cd-4a75-a20c-d3d25e188ecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670234716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1670234716
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1611320861
Short name T81
Test name
Test status
Simulation time 925370044 ps
CPU time 1.41 seconds
Started Jun 30 06:19:14 PM PDT 24
Finished Jun 30 06:19:17 PM PDT 24
Peak memory 193028 kb
Host smart-9d12a225-386d-4bd1-b0c1-f4f1695bf6c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611320861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1611320861
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3593736653
Short name T314
Test name
Test status
Simulation time 396248584 ps
CPU time 2.42 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:13 PM PDT 24
Peak memory 198680 kb
Host smart-28f145a7-6805-4193-b392-1e46a98467a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593736653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3593736653
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3885286122
Short name T396
Test name
Test status
Simulation time 8484354457 ps
CPU time 3.52 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:15 PM PDT 24
Peak memory 198368 kb
Host smart-6371e82a-b53d-4c85-ba8f-73dd80d01b4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885286122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3885286122
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3012941781
Short name T365
Test name
Test status
Simulation time 538763905 ps
CPU time 1.37 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:14 PM PDT 24
Peak memory 195724 kb
Host smart-5f32c477-3dbd-4b2a-b914-6c9109265ea5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012941781 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3012941781
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1445033249
Short name T62
Test name
Test status
Simulation time 443865701 ps
CPU time 1.21 seconds
Started Jun 30 06:19:12 PM PDT 24
Finished Jun 30 06:19:14 PM PDT 24
Peak memory 192088 kb
Host smart-b778d692-6733-4016-a1de-2735a08407aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445033249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1445033249
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1270155901
Short name T347
Test name
Test status
Simulation time 370365663 ps
CPU time 1.08 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:13 PM PDT 24
Peak memory 193032 kb
Host smart-42771259-1724-406d-a18e-387a9e9f3f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270155901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1270155901
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3465914110
Short name T76
Test name
Test status
Simulation time 2171920615 ps
CPU time 3.5 seconds
Started Jun 30 06:19:11 PM PDT 24
Finished Jun 30 06:19:16 PM PDT 24
Peak memory 193792 kb
Host smart-30852f47-85bc-42f7-a220-cfb851fb721e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465914110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3465914110
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.183831395
Short name T383
Test name
Test status
Simulation time 286647305 ps
CPU time 2.15 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:13 PM PDT 24
Peak memory 198708 kb
Host smart-50bf8a6f-381b-4ac8-99fd-14f44c957d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183831395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.183831395
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3319233227
Short name T354
Test name
Test status
Simulation time 4620072046 ps
CPU time 5.38 seconds
Started Jun 30 06:19:10 PM PDT 24
Finished Jun 30 06:19:17 PM PDT 24
Peak memory 198052 kb
Host smart-13423724-a7c8-4a66-b629-74fa026c873a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319233227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3319233227
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3331257783
Short name T23
Test name
Test status
Simulation time 21061795194 ps
CPU time 9.84 seconds
Started Jun 30 06:40:22 PM PDT 24
Finished Jun 30 06:40:32 PM PDT 24
Peak memory 196736 kb
Host smart-9c16040d-8b1e-4d30-b33e-a8cb7307f13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331257783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3331257783
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.627231478
Short name T238
Test name
Test status
Simulation time 479762819 ps
CPU time 0.72 seconds
Started Jun 30 06:40:22 PM PDT 24
Finished Jun 30 06:40:23 PM PDT 24
Peak memory 191580 kb
Host smart-dc811174-09c6-4af1-a0bc-f1994a5f4017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627231478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.627231478
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.296491821
Short name T22
Test name
Test status
Simulation time 18762306679 ps
CPU time 28.17 seconds
Started Jun 30 06:40:27 PM PDT 24
Finished Jun 30 06:40:56 PM PDT 24
Peak memory 191740 kb
Host smart-2a3bec11-2038-4b7a-b318-c4e0a6ef08e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296491821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.296491821
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.4218433794
Short name T16
Test name
Test status
Simulation time 8255112985 ps
CPU time 12.3 seconds
Started Jun 30 06:40:29 PM PDT 24
Finished Jun 30 06:40:42 PM PDT 24
Peak memory 215824 kb
Host smart-c8cdb005-1a8f-41a3-9864-ac8e87124ca9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218433794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.4218433794
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.639953165
Short name T50
Test name
Test status
Simulation time 546925138 ps
CPU time 0.8 seconds
Started Jun 30 06:40:28 PM PDT 24
Finished Jun 30 06:40:30 PM PDT 24
Peak memory 191576 kb
Host smart-6a6570f0-f769-4d32-8897-63ae5007dad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639953165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.639953165
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.369148578
Short name T267
Test name
Test status
Simulation time 19892354304 ps
CPU time 25.67 seconds
Started Jun 30 06:40:41 PM PDT 24
Finished Jun 30 06:41:07 PM PDT 24
Peak memory 191728 kb
Host smart-ebc8c070-f5a2-418f-93d2-2490f9401327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369148578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.369148578
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3336498056
Short name T276
Test name
Test status
Simulation time 655275546 ps
CPU time 0.66 seconds
Started Jun 30 06:40:40 PM PDT 24
Finished Jun 30 06:40:41 PM PDT 24
Peak memory 191616 kb
Host smart-6a6818f7-e4dd-4384-bfff-66e2927c8c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336498056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3336498056
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2670247820
Short name T201
Test name
Test status
Simulation time 30975661314 ps
CPU time 31.77 seconds
Started Jun 30 06:40:39 PM PDT 24
Finished Jun 30 06:41:12 PM PDT 24
Peak memory 196688 kb
Host smart-ce097c79-a287-4f0a-871a-a929e82a9304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670247820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2670247820
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.120886855
Short name T249
Test name
Test status
Simulation time 597057572 ps
CPU time 1.04 seconds
Started Jun 30 06:40:40 PM PDT 24
Finished Jun 30 06:40:42 PM PDT 24
Peak memory 196744 kb
Host smart-36ba675c-0c1e-47fc-897f-2b8e34938e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120886855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.120886855
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3954705141
Short name T192
Test name
Test status
Simulation time 356459191 ps
CPU time 0.9 seconds
Started Jun 30 06:40:39 PM PDT 24
Finished Jun 30 06:40:41 PM PDT 24
Peak memory 196460 kb
Host smart-271815bc-f2b2-4287-b8c5-3b9ec3e0f952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954705141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3954705141
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2563469058
Short name T239
Test name
Test status
Simulation time 30476173932 ps
CPU time 27.29 seconds
Started Jun 30 06:40:39 PM PDT 24
Finished Jun 30 06:41:07 PM PDT 24
Peak memory 196724 kb
Host smart-317cd20d-dd7e-49f6-93b2-87859834dc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563469058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2563469058
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.35536693
Short name T252
Test name
Test status
Simulation time 430687530 ps
CPU time 0.75 seconds
Started Jun 30 06:40:41 PM PDT 24
Finished Jun 30 06:40:43 PM PDT 24
Peak memory 191652 kb
Host smart-433b4cbe-be0d-4c90-8580-e40adcc1f149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35536693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.35536693
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3898192273
Short name T13
Test name
Test status
Simulation time 39038008889 ps
CPU time 60.08 seconds
Started Jun 30 06:40:44 PM PDT 24
Finished Jun 30 06:41:44 PM PDT 24
Peak memory 196668 kb
Host smart-78b7fd42-ad58-4969-a9ad-8cbe2bfcdf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898192273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3898192273
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3876409269
Short name T263
Test name
Test status
Simulation time 456021865 ps
CPU time 0.73 seconds
Started Jun 30 06:40:40 PM PDT 24
Finished Jun 30 06:40:41 PM PDT 24
Peak memory 196524 kb
Host smart-de5a7e8f-da01-4595-b672-1561c8457f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876409269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3876409269
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2096731116
Short name T279
Test name
Test status
Simulation time 169692333365 ps
CPU time 245.88 seconds
Started Jun 30 06:40:41 PM PDT 24
Finished Jun 30 06:44:48 PM PDT 24
Peak memory 183948 kb
Host smart-27139341-ba07-4389-bdbe-54ae0774db4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096731116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2096731116
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2638274031
Short name T247
Test name
Test status
Simulation time 10556682538 ps
CPU time 15.6 seconds
Started Jun 30 06:40:43 PM PDT 24
Finished Jun 30 06:40:59 PM PDT 24
Peak memory 196724 kb
Host smart-331e9d96-74c5-4c40-97bf-2a105af49e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638274031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2638274031
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.465442258
Short name T209
Test name
Test status
Simulation time 465209883 ps
CPU time 1.3 seconds
Started Jun 30 06:40:44 PM PDT 24
Finished Jun 30 06:40:46 PM PDT 24
Peak memory 196424 kb
Host smart-4c5075fe-2656-45a7-8ba8-37781803e007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465442258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.465442258
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.580499210
Short name T203
Test name
Test status
Simulation time 38303781862 ps
CPU time 5.07 seconds
Started Jun 30 06:40:41 PM PDT 24
Finished Jun 30 06:40:47 PM PDT 24
Peak memory 191700 kb
Host smart-d16e4796-d4f5-46cc-9453-102539ea96c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580499210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.580499210
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3971270613
Short name T246
Test name
Test status
Simulation time 432081522 ps
CPU time 0.76 seconds
Started Jun 30 06:40:40 PM PDT 24
Finished Jun 30 06:40:41 PM PDT 24
Peak memory 196440 kb
Host smart-1eb16c8b-eb45-4f2c-adf6-5fe9624fd7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971270613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3971270613
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3934410276
Short name T222
Test name
Test status
Simulation time 29758740089 ps
CPU time 16.17 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:41:03 PM PDT 24
Peak memory 191640 kb
Host smart-9314785c-6cf1-48a0-ab61-d41eb62f41b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934410276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3934410276
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3412696364
Short name T216
Test name
Test status
Simulation time 459706087 ps
CPU time 1.21 seconds
Started Jun 30 06:40:49 PM PDT 24
Finished Jun 30 06:40:51 PM PDT 24
Peak memory 191664 kb
Host smart-16a33d86-65e1-4e6f-b844-90ab2cefbf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412696364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3412696364
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2064405884
Short name T229
Test name
Test status
Simulation time 36665107789 ps
CPU time 5.31 seconds
Started Jun 30 06:40:45 PM PDT 24
Finished Jun 30 06:40:51 PM PDT 24
Peak memory 191736 kb
Host smart-f03ba7b6-98df-4493-a478-85f0c3a38987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064405884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2064405884
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1872672658
Short name T243
Test name
Test status
Simulation time 388018482 ps
CPU time 0.69 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:40:48 PM PDT 24
Peak memory 191608 kb
Host smart-67f6a8a9-2add-4d4d-99e5-ab80183231e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872672658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1872672658
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2908357273
Short name T176
Test name
Test status
Simulation time 555991236 ps
CPU time 0.83 seconds
Started Jun 30 06:40:45 PM PDT 24
Finished Jun 30 06:40:46 PM PDT 24
Peak memory 196748 kb
Host smart-ac07fd0b-fb8d-4df0-bc41-d7994e8597f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908357273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2908357273
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.857066643
Short name T227
Test name
Test status
Simulation time 56598301497 ps
CPU time 85.31 seconds
Started Jun 30 06:40:45 PM PDT 24
Finished Jun 30 06:42:11 PM PDT 24
Peak memory 196688 kb
Host smart-de24f28d-5461-4d80-877f-2cde26e48117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857066643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.857066643
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.262914078
Short name T245
Test name
Test status
Simulation time 373860457 ps
CPU time 0.74 seconds
Started Jun 30 06:40:47 PM PDT 24
Finished Jun 30 06:40:49 PM PDT 24
Peak memory 191656 kb
Host smart-e55906c7-8adb-4f0b-929c-2f30515623dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262914078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.262914078
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.429631136
Short name T202
Test name
Test status
Simulation time 29510792450 ps
CPU time 42.21 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:41:30 PM PDT 24
Peak memory 196752 kb
Host smart-4b3e1064-6bb4-4c2e-bd48-98f4cb4399ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429631136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.429631136
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3127317658
Short name T248
Test name
Test status
Simulation time 495151369 ps
CPU time 1.25 seconds
Started Jun 30 06:40:45 PM PDT 24
Finished Jun 30 06:40:47 PM PDT 24
Peak memory 191656 kb
Host smart-5e831d8f-c694-4433-a504-948bbfa15905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127317658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3127317658
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.4003623163
Short name T241
Test name
Test status
Simulation time 4023593241 ps
CPU time 1.05 seconds
Started Jun 30 06:40:29 PM PDT 24
Finished Jun 30 06:40:30 PM PDT 24
Peak memory 196540 kb
Host smart-c8a37e07-fdf2-4c8f-9a80-8134f35a32a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003623163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.4003623163
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2522655630
Short name T20
Test name
Test status
Simulation time 7500440641 ps
CPU time 12.36 seconds
Started Jun 30 06:40:27 PM PDT 24
Finished Jun 30 06:40:39 PM PDT 24
Peak memory 215800 kb
Host smart-5430fe2a-24b3-48a2-bd34-8e452ecad83b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522655630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2522655630
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1112326111
Short name T32
Test name
Test status
Simulation time 541505638 ps
CPU time 0.93 seconds
Started Jun 30 06:40:28 PM PDT 24
Finished Jun 30 06:40:29 PM PDT 24
Peak memory 191668 kb
Host smart-36ed49ee-93cd-4721-a884-4d31406e8da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112326111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1112326111
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2256560329
Short name T212
Test name
Test status
Simulation time 5098437189 ps
CPU time 4.49 seconds
Started Jun 30 06:40:47 PM PDT 24
Finished Jun 30 06:40:52 PM PDT 24
Peak memory 191652 kb
Host smart-5b913cc0-de50-4aeb-b927-42c08a1865aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256560329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2256560329
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3387173810
Short name T208
Test name
Test status
Simulation time 387984059 ps
CPU time 0.91 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:40:48 PM PDT 24
Peak memory 191648 kb
Host smart-43f770dd-6293-4c9c-95d5-73b6d817837f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387173810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3387173810
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1036368347
Short name T282
Test name
Test status
Simulation time 40896156715 ps
CPU time 48.06 seconds
Started Jun 30 06:40:48 PM PDT 24
Finished Jun 30 06:41:37 PM PDT 24
Peak memory 191680 kb
Host smart-c66cb6e4-545d-4af8-a4d6-257923907acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036368347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1036368347
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.753242361
Short name T250
Test name
Test status
Simulation time 564060030 ps
CPU time 1.51 seconds
Started Jun 30 06:40:47 PM PDT 24
Finished Jun 30 06:40:50 PM PDT 24
Peak memory 196476 kb
Host smart-8a1e40b3-1cce-4930-bed0-6de188637431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753242361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.753242361
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.747319393
Short name T218
Test name
Test status
Simulation time 37720220196 ps
CPU time 43.91 seconds
Started Jun 30 06:40:46 PM PDT 24
Finished Jun 30 06:41:31 PM PDT 24
Peak memory 191732 kb
Host smart-1a9455f7-a209-4570-97e7-400199fe3d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747319393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.747319393
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1883763912
Short name T11
Test name
Test status
Simulation time 512921788 ps
CPU time 0.77 seconds
Started Jun 30 06:40:49 PM PDT 24
Finished Jun 30 06:40:50 PM PDT 24
Peak memory 191664 kb
Host smart-1f55099a-2051-4509-b014-59894d7e9718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883763912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1883763912
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.694011876
Short name T275
Test name
Test status
Simulation time 37194968352 ps
CPU time 18 seconds
Started Jun 30 06:40:47 PM PDT 24
Finished Jun 30 06:41:06 PM PDT 24
Peak memory 191724 kb
Host smart-09153edd-a5b2-4b05-a232-4db1e1977774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694011876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.694011876
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.780370949
Short name T6
Test name
Test status
Simulation time 571100955 ps
CPU time 1.39 seconds
Started Jun 30 06:40:47 PM PDT 24
Finished Jun 30 06:40:50 PM PDT 24
Peak memory 191644 kb
Host smart-bb33d61a-aa10-407c-aa45-36666ae098be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780370949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.780370949
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3225792837
Short name T278
Test name
Test status
Simulation time 54612508216 ps
CPU time 11.59 seconds
Started Jun 30 06:40:56 PM PDT 24
Finished Jun 30 06:41:09 PM PDT 24
Peak memory 191672 kb
Host smart-5d185020-b839-4fb6-bfd7-62d3337dc7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225792837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3225792837
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.761884308
Short name T213
Test name
Test status
Simulation time 361125847 ps
CPU time 1.16 seconds
Started Jun 30 06:40:56 PM PDT 24
Finished Jun 30 06:40:58 PM PDT 24
Peak memory 196464 kb
Host smart-4e13e4fd-43e3-4202-a637-2b0389e63b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761884308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.761884308
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3766823822
Short name T230
Test name
Test status
Simulation time 4790119273 ps
CPU time 7.92 seconds
Started Jun 30 06:40:55 PM PDT 24
Finished Jun 30 06:41:04 PM PDT 24
Peak memory 196680 kb
Host smart-8cb791a9-10c0-45a2-b1e0-a529cf7f1ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766823822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3766823822
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3655886337
Short name T217
Test name
Test status
Simulation time 373608408 ps
CPU time 1.17 seconds
Started Jun 30 06:40:54 PM PDT 24
Finished Jun 30 06:40:56 PM PDT 24
Peak memory 196532 kb
Host smart-5f451205-6ef3-49ce-89d3-3432e587ba38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655886337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3655886337
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3110817997
Short name T274
Test name
Test status
Simulation time 19817657133 ps
CPU time 14.55 seconds
Started Jun 30 06:40:52 PM PDT 24
Finished Jun 30 06:41:07 PM PDT 24
Peak memory 196616 kb
Host smart-644f143a-6bbc-4487-a5c6-c084aec3259a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110817997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3110817997
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2412946616
Short name T83
Test name
Test status
Simulation time 495361603 ps
CPU time 0.96 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:40:55 PM PDT 24
Peak memory 191660 kb
Host smart-1523d8bb-4f57-4e53-a2c2-91a6d48b108d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412946616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2412946616
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1731786180
Short name T232
Test name
Test status
Simulation time 26864181037 ps
CPU time 35.66 seconds
Started Jun 30 06:40:52 PM PDT 24
Finished Jun 30 06:41:30 PM PDT 24
Peak memory 196728 kb
Host smart-82a2ac82-39fc-409b-95d4-c1d71f33739d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731786180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1731786180
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2454164992
Short name T234
Test name
Test status
Simulation time 511984254 ps
CPU time 0.8 seconds
Started Jun 30 06:40:54 PM PDT 24
Finished Jun 30 06:40:56 PM PDT 24
Peak memory 196500 kb
Host smart-987f99b1-ba19-4953-8319-f8faf248db77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454164992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2454164992
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3952479360
Short name T228
Test name
Test status
Simulation time 18757728230 ps
CPU time 7.5 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:41:02 PM PDT 24
Peak memory 191740 kb
Host smart-bd926a3f-1568-4bd4-a5d3-514dcc1ef240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952479360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3952479360
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.854148752
Short name T87
Test name
Test status
Simulation time 608495897 ps
CPU time 0.69 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:40:56 PM PDT 24
Peak memory 196372 kb
Host smart-9134d9fe-6d00-4be6-9f91-415dca69f23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854148752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.854148752
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.695385540
Short name T280
Test name
Test status
Simulation time 48557981939 ps
CPU time 64.3 seconds
Started Jun 30 06:40:54 PM PDT 24
Finished Jun 30 06:42:00 PM PDT 24
Peak memory 191724 kb
Host smart-1a79e28a-00f6-4af2-aee9-abe486d83404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695385540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.695385540
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1658086639
Short name T268
Test name
Test status
Simulation time 472676218 ps
CPU time 0.75 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:40:56 PM PDT 24
Peak memory 191656 kb
Host smart-8e35f3c8-183c-4915-9478-9230db88c886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658086639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1658086639
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1631940562
Short name T199
Test name
Test status
Simulation time 20424025880 ps
CPU time 26.87 seconds
Started Jun 30 06:40:29 PM PDT 24
Finished Jun 30 06:40:56 PM PDT 24
Peak memory 196624 kb
Host smart-ba2b118b-b3bb-45fc-9fad-e0b3b99e5e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631940562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1631940562
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.48671668
Short name T17
Test name
Test status
Simulation time 8335350656 ps
CPU time 6.08 seconds
Started Jun 30 06:40:29 PM PDT 24
Finished Jun 30 06:40:36 PM PDT 24
Peak memory 215776 kb
Host smart-41d1e150-da0c-40d9-850c-0a725ff7a47b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48671668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.48671668
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.4126365821
Short name T26
Test name
Test status
Simulation time 355702636 ps
CPU time 1.15 seconds
Started Jun 30 06:40:28 PM PDT 24
Finished Jun 30 06:40:30 PM PDT 24
Peak memory 191652 kb
Host smart-ef0d323e-a27f-4b0e-87a0-ba4136813200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126365821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.4126365821
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3759369989
Short name T10
Test name
Test status
Simulation time 624196998 ps
CPU time 0.82 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:40:55 PM PDT 24
Peak memory 196492 kb
Host smart-e9bddd2c-dcfe-4445-b1e3-7f0fab1a8dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759369989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3759369989
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4067858765
Short name T200
Test name
Test status
Simulation time 17035431490 ps
CPU time 23.71 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:41:18 PM PDT 24
Peak memory 191684 kb
Host smart-392a8d98-5bb4-4b52-846a-bd04ddc6464c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067858765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4067858765
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.468211682
Short name T221
Test name
Test status
Simulation time 519113615 ps
CPU time 0.72 seconds
Started Jun 30 06:40:53 PM PDT 24
Finished Jun 30 06:40:55 PM PDT 24
Peak memory 196444 kb
Host smart-dca6d1a0-abb5-4b26-a16b-8153463b8e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468211682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.468211682
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.508821016
Short name T198
Test name
Test status
Simulation time 2083087373 ps
CPU time 1.2 seconds
Started Jun 30 06:41:02 PM PDT 24
Finished Jun 30 06:41:05 PM PDT 24
Peak memory 191564 kb
Host smart-d6ebaa49-68df-47eb-86ee-c0aae2c89cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508821016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.508821016
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2462983816
Short name T244
Test name
Test status
Simulation time 501356825 ps
CPU time 0.85 seconds
Started Jun 30 06:41:00 PM PDT 24
Finished Jun 30 06:41:02 PM PDT 24
Peak memory 191880 kb
Host smart-b995451b-3921-4b23-86dc-a2a1add0ade2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462983816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2462983816
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.482087645
Short name T226
Test name
Test status
Simulation time 49557296674 ps
CPU time 34.12 seconds
Started Jun 30 06:40:59 PM PDT 24
Finished Jun 30 06:41:33 PM PDT 24
Peak memory 191720 kb
Host smart-4dac2efb-fe23-4161-9a98-9868d63ffc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482087645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.482087645
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3671797005
Short name T1
Test name
Test status
Simulation time 383197357 ps
CPU time 0.75 seconds
Started Jun 30 06:41:00 PM PDT 24
Finished Jun 30 06:41:01 PM PDT 24
Peak memory 191668 kb
Host smart-5b6867a6-95b4-4bc6-aba5-e8c1acf4f5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671797005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3671797005
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3548445964
Short name T220
Test name
Test status
Simulation time 28727405389 ps
CPU time 11.51 seconds
Started Jun 30 06:41:02 PM PDT 24
Finished Jun 30 06:41:15 PM PDT 24
Peak memory 191724 kb
Host smart-1bd53561-50c0-44a2-953b-e246e3788fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548445964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3548445964
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3150128068
Short name T269
Test name
Test status
Simulation time 463277479 ps
CPU time 1.16 seconds
Started Jun 30 06:41:02 PM PDT 24
Finished Jun 30 06:41:04 PM PDT 24
Peak memory 196492 kb
Host smart-483c8fd2-1bfb-449e-b87b-a494ee5e23f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150128068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3150128068
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2876329115
Short name T166
Test name
Test status
Simulation time 428590813 ps
CPU time 0.75 seconds
Started Jun 30 06:41:03 PM PDT 24
Finished Jun 30 06:41:05 PM PDT 24
Peak memory 196516 kb
Host smart-84f0184e-56f4-4fc9-9407-062a2622ea44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876329115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2876329115
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3609079826
Short name T251
Test name
Test status
Simulation time 49334214872 ps
CPU time 43.73 seconds
Started Jun 30 06:40:59 PM PDT 24
Finished Jun 30 06:41:43 PM PDT 24
Peak memory 196688 kb
Host smart-330a3d14-57ed-4b12-9a8e-67e71c969d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609079826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3609079826
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1269737988
Short name T211
Test name
Test status
Simulation time 581949547 ps
CPU time 1.47 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:41:04 PM PDT 24
Peak memory 196464 kb
Host smart-2b0863d9-7758-43eb-b011-b40d9f9f9915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269737988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1269737988
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.505424435
Short name T242
Test name
Test status
Simulation time 18699071548 ps
CPU time 5.21 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:41:07 PM PDT 24
Peak memory 191716 kb
Host smart-4111a5cb-ed35-4f3e-a5da-202c257c781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505424435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.505424435
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2552240421
Short name T236
Test name
Test status
Simulation time 509893348 ps
CPU time 0.65 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:41:04 PM PDT 24
Peak memory 196504 kb
Host smart-a2042fdb-5194-4814-abde-9fdd5492787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552240421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2552240421
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2804881302
Short name T180
Test name
Test status
Simulation time 522153935 ps
CPU time 0.97 seconds
Started Jun 30 06:41:00 PM PDT 24
Finished Jun 30 06:41:02 PM PDT 24
Peak memory 196508 kb
Host smart-06cd6bc6-1c91-435e-9489-5bb0c4889ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804881302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2804881302
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2556228823
Short name T223
Test name
Test status
Simulation time 23700050246 ps
CPU time 33.7 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:41:36 PM PDT 24
Peak memory 191724 kb
Host smart-12c64d8f-b238-4d9c-8d4d-eae0d7e51c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556228823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2556228823
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.224580207
Short name T206
Test name
Test status
Simulation time 475782121 ps
CPU time 0.87 seconds
Started Jun 30 06:41:03 PM PDT 24
Finished Jun 30 06:41:05 PM PDT 24
Peak memory 191560 kb
Host smart-d9f0ab73-8fa3-46b0-aabd-7c989c6febf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224580207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.224580207
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1449024770
Short name T273
Test name
Test status
Simulation time 46951657671 ps
CPU time 73.39 seconds
Started Jun 30 06:40:59 PM PDT 24
Finished Jun 30 06:42:14 PM PDT 24
Peak memory 196740 kb
Host smart-d6c23576-77c6-4458-a84c-f17458e745ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449024770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1449024770
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3434291344
Short name T225
Test name
Test status
Simulation time 518156319 ps
CPU time 0.75 seconds
Started Jun 30 06:41:01 PM PDT 24
Finished Jun 30 06:41:03 PM PDT 24
Peak memory 196524 kb
Host smart-785197cd-eae7-4f60-bf59-7bde4e902b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434291344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3434291344
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.4187401819
Short name T235
Test name
Test status
Simulation time 6635737898 ps
CPU time 3.2 seconds
Started Jun 30 06:41:08 PM PDT 24
Finished Jun 30 06:41:11 PM PDT 24
Peak memory 191712 kb
Host smart-11d1426c-15a6-48ba-9c92-40ca6f58c856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187401819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.4187401819
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3489991894
Short name T253
Test name
Test status
Simulation time 488783986 ps
CPU time 0.88 seconds
Started Jun 30 06:41:00 PM PDT 24
Finished Jun 30 06:41:02 PM PDT 24
Peak memory 191672 kb
Host smart-3fb91565-3545-4a2a-83e3-252ddf0e518b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489991894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3489991894
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1478742882
Short name T231
Test name
Test status
Simulation time 54522843869 ps
CPU time 38.26 seconds
Started Jun 30 06:41:07 PM PDT 24
Finished Jun 30 06:41:46 PM PDT 24
Peak memory 191740 kb
Host smart-3dc9ee87-a8c1-4ecc-94b2-f69b480481f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478742882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1478742882
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2152476754
Short name T258
Test name
Test status
Simulation time 430229006 ps
CPU time 0.71 seconds
Started Jun 30 06:41:07 PM PDT 24
Finished Jun 30 06:41:08 PM PDT 24
Peak memory 196508 kb
Host smart-047a52fd-9c3e-47b4-ad96-f730dc50a792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152476754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2152476754
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1110933502
Short name T52
Test name
Test status
Simulation time 31766241788 ps
CPU time 12.62 seconds
Started Jun 30 06:40:32 PM PDT 24
Finished Jun 30 06:40:45 PM PDT 24
Peak memory 191716 kb
Host smart-66d00d3b-e898-477f-910d-69d69c8d0d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110933502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1110933502
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2213499232
Short name T21
Test name
Test status
Simulation time 8448509251 ps
CPU time 1.54 seconds
Started Jun 30 06:40:28 PM PDT 24
Finished Jun 30 06:40:30 PM PDT 24
Peak memory 215832 kb
Host smart-c01c1fee-05fd-4c04-9e66-6870ce5cba50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213499232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2213499232
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1547427269
Short name T91
Test name
Test status
Simulation time 618640586 ps
CPU time 0.82 seconds
Started Jun 30 06:40:32 PM PDT 24
Finished Jun 30 06:40:33 PM PDT 24
Peak memory 196476 kb
Host smart-3d09d2d9-92cd-4182-8297-d3f61b9f6199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547427269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1547427269
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.847089532
Short name T265
Test name
Test status
Simulation time 16203170801 ps
CPU time 4.13 seconds
Started Jun 30 06:41:08 PM PDT 24
Finished Jun 30 06:41:14 PM PDT 24
Peak memory 191676 kb
Host smart-fd2e4b5d-a5b5-4dd7-ba1f-2fcc5002c226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847089532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.847089532
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.504874955
Short name T237
Test name
Test status
Simulation time 495816534 ps
CPU time 0.83 seconds
Started Jun 30 06:41:09 PM PDT 24
Finished Jun 30 06:41:10 PM PDT 24
Peak memory 196488 kb
Host smart-285222eb-9443-49e7-ba61-7961119b2f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504874955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.504874955
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.860781598
Short name T271
Test name
Test status
Simulation time 11781400300 ps
CPU time 16.21 seconds
Started Jun 30 06:41:09 PM PDT 24
Finished Jun 30 06:41:26 PM PDT 24
Peak memory 191712 kb
Host smart-1a598f23-48a9-409d-8c08-4fe1f3b56d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860781598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.860781598
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2378398741
Short name T30
Test name
Test status
Simulation time 429486911 ps
CPU time 1.19 seconds
Started Jun 30 06:41:08 PM PDT 24
Finished Jun 30 06:41:09 PM PDT 24
Peak memory 191656 kb
Host smart-785499c0-201c-4b32-be7b-ddcc9539540d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378398741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2378398741
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3260681902
Short name T168
Test name
Test status
Simulation time 17961463621 ps
CPU time 70.15 seconds
Started Jun 30 06:41:07 PM PDT 24
Finished Jun 30 06:42:17 PM PDT 24
Peak memory 206584 kb
Host smart-774137c5-b61a-4170-852c-02bc28f7eb4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260681902 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3260681902
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2827058829
Short name T224
Test name
Test status
Simulation time 3585125974 ps
CPU time 3.41 seconds
Started Jun 30 06:41:16 PM PDT 24
Finished Jun 30 06:41:20 PM PDT 24
Peak memory 196552 kb
Host smart-dc743886-2e8a-4006-b51a-c67830eb92f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827058829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2827058829
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3853592057
Short name T254
Test name
Test status
Simulation time 350155173 ps
CPU time 1.03 seconds
Started Jun 30 06:41:06 PM PDT 24
Finished Jun 30 06:41:08 PM PDT 24
Peak memory 191668 kb
Host smart-c5e6ecb6-3f58-4090-b97e-763eabeb67d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853592057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3853592057
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1741324881
Short name T255
Test name
Test status
Simulation time 52343012229 ps
CPU time 9.82 seconds
Started Jun 30 06:41:16 PM PDT 24
Finished Jun 30 06:41:26 PM PDT 24
Peak memory 191724 kb
Host smart-7ff1a141-7196-4a83-b721-32d78080a871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741324881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1741324881
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2749403019
Short name T264
Test name
Test status
Simulation time 541063109 ps
CPU time 0.93 seconds
Started Jun 30 06:41:13 PM PDT 24
Finished Jun 30 06:41:15 PM PDT 24
Peak memory 191660 kb
Host smart-2b998003-62b0-404d-8488-3c1deaf82178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749403019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2749403019
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.795576116
Short name T262
Test name
Test status
Simulation time 55297624513 ps
CPU time 18.84 seconds
Started Jun 30 06:41:13 PM PDT 24
Finished Jun 30 06:41:32 PM PDT 24
Peak memory 196704 kb
Host smart-8cd8cb7b-67b6-414f-8d96-7622b24eb733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795576116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.795576116
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3924253361
Short name T256
Test name
Test status
Simulation time 553960642 ps
CPU time 0.99 seconds
Started Jun 30 06:41:14 PM PDT 24
Finished Jun 30 06:41:16 PM PDT 24
Peak memory 196496 kb
Host smart-9193f681-a3d5-4ff3-8c03-6aa1ff28f6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924253361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3924253361
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2611780112
Short name T270
Test name
Test status
Simulation time 2260857987 ps
CPU time 1.27 seconds
Started Jun 30 06:41:13 PM PDT 24
Finished Jun 30 06:41:14 PM PDT 24
Peak memory 196432 kb
Host smart-60f9464c-a0ac-4f2b-8a3f-46ab13a6c2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611780112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2611780112
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.351127727
Short name T281
Test name
Test status
Simulation time 577533613 ps
CPU time 1 seconds
Started Jun 30 06:41:14 PM PDT 24
Finished Jun 30 06:41:15 PM PDT 24
Peak memory 191644 kb
Host smart-1424d116-b779-4aa6-862a-05d14a61f65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351127727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.351127727
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3055673183
Short name T215
Test name
Test status
Simulation time 26208533217 ps
CPU time 35.41 seconds
Started Jun 30 06:41:13 PM PDT 24
Finished Jun 30 06:41:49 PM PDT 24
Peak memory 196732 kb
Host smart-e2146423-5c50-40fb-acc6-bdedd60dc28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055673183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3055673183
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.413995281
Short name T205
Test name
Test status
Simulation time 517696335 ps
CPU time 0.92 seconds
Started Jun 30 06:41:15 PM PDT 24
Finished Jun 30 06:41:17 PM PDT 24
Peak memory 191652 kb
Host smart-f0eeae9e-490b-4620-a6d0-f8ae06d1e3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413995281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.413995281
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3231133890
Short name T207
Test name
Test status
Simulation time 56194255188 ps
CPU time 39.97 seconds
Started Jun 30 06:41:23 PM PDT 24
Finished Jun 30 06:42:04 PM PDT 24
Peak memory 191736 kb
Host smart-cf0fc159-3182-445b-8a0c-bb85910cdadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231133890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3231133890
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3283034719
Short name T257
Test name
Test status
Simulation time 565511673 ps
CPU time 0.63 seconds
Started Jun 30 06:41:21 PM PDT 24
Finished Jun 30 06:41:22 PM PDT 24
Peak memory 191672 kb
Host smart-64186cbc-40b7-449d-98cc-669824cea06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283034719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3283034719
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.786446572
Short name T219
Test name
Test status
Simulation time 23585401531 ps
CPU time 9.21 seconds
Started Jun 30 06:41:21 PM PDT 24
Finished Jun 30 06:41:31 PM PDT 24
Peak memory 191736 kb
Host smart-fe98dc1d-a976-4fff-a765-285c72385d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786446572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.786446572
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2678307416
Short name T272
Test name
Test status
Simulation time 472966001 ps
CPU time 1.17 seconds
Started Jun 30 06:41:22 PM PDT 24
Finished Jun 30 06:41:23 PM PDT 24
Peak memory 191636 kb
Host smart-ee240d65-220e-45e6-91c4-40725568e6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678307416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2678307416
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3577610932
Short name T260
Test name
Test status
Simulation time 49394786802 ps
CPU time 79.57 seconds
Started Jun 30 06:41:23 PM PDT 24
Finished Jun 30 06:42:44 PM PDT 24
Peak memory 196744 kb
Host smart-41b7faea-d758-4d7c-8205-f564e7ca1046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577610932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3577610932
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.637138375
Short name T259
Test name
Test status
Simulation time 516432365 ps
CPU time 1 seconds
Started Jun 30 06:41:23 PM PDT 24
Finished Jun 30 06:41:25 PM PDT 24
Peak memory 196504 kb
Host smart-f97143d6-caf4-43fc-b8af-7b789eba7831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637138375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.637138375
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.241199248
Short name T29
Test name
Test status
Simulation time 31435656941 ps
CPU time 10.24 seconds
Started Jun 30 06:40:28 PM PDT 24
Finished Jun 30 06:40:38 PM PDT 24
Peak memory 191712 kb
Host smart-75543f13-6130-4386-876c-8da0a66db862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241199248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.241199248
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.715317779
Short name T277
Test name
Test status
Simulation time 593078824 ps
CPU time 1.46 seconds
Started Jun 30 06:40:29 PM PDT 24
Finished Jun 30 06:40:31 PM PDT 24
Peak memory 191660 kb
Host smart-d73454ab-e49b-4788-83b0-fc165a415cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715317779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.715317779
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3210009933
Short name T3
Test name
Test status
Simulation time 30748851426 ps
CPU time 11.45 seconds
Started Jun 30 06:40:34 PM PDT 24
Finished Jun 30 06:40:46 PM PDT 24
Peak memory 191656 kb
Host smart-cfdf4571-4e38-437c-a0f8-117019f2e975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210009933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3210009933
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.4272161877
Short name T210
Test name
Test status
Simulation time 565929343 ps
CPU time 0.81 seconds
Started Jun 30 06:40:34 PM PDT 24
Finished Jun 30 06:40:36 PM PDT 24
Peak memory 196492 kb
Host smart-c960e16a-19a4-457f-9f85-92d0b432d6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272161877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.4272161877
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.4109235264
Short name T214
Test name
Test status
Simulation time 51087497080 ps
CPU time 31.62 seconds
Started Jun 30 06:40:34 PM PDT 24
Finished Jun 30 06:41:06 PM PDT 24
Peak memory 191724 kb
Host smart-8f5e8980-9a09-4530-9611-be4e7bf52977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109235264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.4109235264
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.436158241
Short name T266
Test name
Test status
Simulation time 443266152 ps
CPU time 0.77 seconds
Started Jun 30 06:40:33 PM PDT 24
Finished Jun 30 06:40:34 PM PDT 24
Peak memory 191608 kb
Host smart-4c707d81-fc1a-4946-a504-12b5624a092b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436158241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.436158241
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2174140587
Short name T261
Test name
Test status
Simulation time 13419324748 ps
CPU time 2.73 seconds
Started Jun 30 06:40:34 PM PDT 24
Finished Jun 30 06:40:38 PM PDT 24
Peak memory 191712 kb
Host smart-a7b00890-b78e-4b53-b615-571c4c1e8677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174140587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2174140587
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3871034061
Short name T240
Test name
Test status
Simulation time 378335743 ps
CPU time 0.66 seconds
Started Jun 30 06:40:32 PM PDT 24
Finished Jun 30 06:40:34 PM PDT 24
Peak memory 191688 kb
Host smart-84df0277-5bf4-4b1f-817a-3f3a42368bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871034061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3871034061
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1613693286
Short name T164
Test name
Test status
Simulation time 428168224 ps
CPU time 1.18 seconds
Started Jun 30 06:40:40 PM PDT 24
Finished Jun 30 06:40:42 PM PDT 24
Peak memory 196456 kb
Host smart-c05747e7-dbbb-4600-afdc-6a31d7a6d522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613693286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1613693286
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2774592946
Short name T5
Test name
Test status
Simulation time 36451458080 ps
CPU time 51.82 seconds
Started Jun 30 06:40:39 PM PDT 24
Finished Jun 30 06:41:31 PM PDT 24
Peak memory 191708 kb
Host smart-28f24cf3-ef99-48af-8b00-7da9ac8d0de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774592946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2774592946
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3174730337
Short name T233
Test name
Test status
Simulation time 381066203 ps
CPU time 0.71 seconds
Started Jun 30 06:40:42 PM PDT 24
Finished Jun 30 06:40:43 PM PDT 24
Peak memory 191644 kb
Host smart-e94e48e0-1fe7-476c-81df-8172b2fdec4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174730337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3174730337
Directory /workspace/9.aon_timer_smoke/latest
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