Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	31468	1		T1	561		T3	11		T4	12
bark[1]	226	1		T16	21		T42	39		T85	26
bark[2]	923	1		T8	21		T45	101		T120	30
bark[3]	872	1		T1	239		T15	21		T17	166
bark[4]	542	1		T6	14		T40	68		T148	14
bark[5]	380	1		T6	21		T27	14		T31	14
bark[6]	686	1		T40	196		T41	7		T108	21
bark[7]	320	1		T37	26		T108	26		T84	21
bark[8]	241	1		T9	14		T16	21		T131	54
bark[9]	270	1		T115	14		T131	21		T86	30
bark[10]	766	1		T54	21		T58	14		T93	21
bark[11]	895	1		T5	14		T33	30		T37	30
bark[12]	688	1		T1	26		T16	101		T26	233
bark[13]	522	1		T32	14		T33	28		T172	14
bark[14]	460	1		T2	14		T17	198		T40	21
bark[15]	629	1		T5	21		T54	40		T93	21
bark[16]	435	1		T16	47		T44	30		T91	44
bark[17]	665	1		T42	21		T184	26		T57	85
bark[18]	408	1		T8	21		T45	21		T117	14
bark[19]	157	1		T17	21		T146	21		T159	56
bark[20]	331	1		T54	21		T150	92		T126	21
bark[21]	335	1		T41	26		T42	35		T26	21
bark[22]	306	1		T46	14		T15	26		T37	21
bark[23]	726	1		T1	7		T17	42		T108	70
bark[24]	417	1		T6	26		T15	21		T101	21
bark[25]	652	1		T8	14		T40	30		T171	14
bark[26]	977	1		T1	21		T5	21		T16	21
bark[27]	453	1		T101	21		T90	21		T91	5
bark[28]	492	1		T37	21		T40	21		T26	7
bark[29]	313	1		T1	21		T37	21		T145	21
bark[30]	347	1		T5	57		T120	26		T159	35
bark[31]	467	1		T17	5		T54	21		T145	21
bark_0	4464	1		T1	82		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	31329	1		T1	547		T3	10		T4	11
bite[1]	643	1		T37	30		T108	26		T26	232
bite[2]	195	1		T9	13		T54	21		T131	21
bite[3]	190	1		T8	21		T37	21		T42	21
bite[4]	269	1		T84	85		T138	39		T91	4
bite[5]	273	1		T108	65		T172	13		T131	54
bite[6]	591	1		T5	13		T6	21		T41	26
bite[7]	552	1		T17	4		T37	21		T91	122
bite[8]	313	1		T15	21		T171	13		T26	21
bite[9]	691	1		T46	13		T42	39		T108	26
bite[10]	75	1		T1	6		T117	13		T138	35
bite[11]	531	1		T1	238		T16	100		T120	26
bite[12]	228	1		T15	21		T32	13		T184	26
bite[13]	453	1		T54	42		T146	21		T105	21
bite[14]	645	1		T40	195		T45	21		T159	35
bite[15]	576	1		T17	165		T41	6		T42	21
bite[16]	605	1		T1	25		T15	26		T33	30
bite[17]	1335	1		T2	13		T6	13		T17	218
bite[18]	365	1		T16	46		T44	243		T140	13
bite[19]	1171	1		T8	13		T45	21		T187	13
bite[20]	713	1		T50	13		T148	13		T43	30
bite[21]	689	1		T8	21		T16	21		T17	21
bite[22]	520	1		T5	21		T40	67		T57	85
bite[23]	455	1		T1	21		T45	66		T153	13
bite[24]	411	1		T16	21		T17	21		T115	13
bite[25]	575	1		T40	21		T43	21		T99	21
bite[26]	711	1		T37	21		T93	21		T101	21
bite[27]	195	1		T93	21		T146	21		T94	25
bite[28]	336	1		T16	21		T40	30		T44	21
bite[29]	328	1		T42	34		T43	13		T44	21
bite[30]	167	1		T1	21		T5	21		T33	27
bite[31]	716	1		T5	57		T6	26		T43	229
bite_0	4987	1		T1	99		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	51833	1		T1	957		T2	21		T3	18

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	798	1		T1	19		T40	81		T42	19
prescale[1]	1081	1		T6	32		T8	37		T15	19
prescale[2]	835	1		T16	19		T42	50		T120	41
prescale[3]	1059	1		T1	2		T15	19		T33	19
prescale[4]	494	1		T1	9		T8	19		T42	19
prescale[5]	1195	1		T15	24		T33	28		T40	182
prescale[6]	955	1		T1	2		T4	9		T8	32
prescale[7]	807	1		T5	23		T37	23		T40	2
prescale[8]	832	1		T8	40		T11	9		T17	45
prescale[9]	1097	1		T1	72		T33	37		T42	80
prescale[10]	1183	1		T8	37		T42	28		T195	9
prescale[11]	883	1		T8	19		T33	46		T16	9
prescale[12]	970	1		T6	58		T29	9		T93	19
prescale[13]	505	1		T1	20		T15	19		T16	2
prescale[14]	657	1		T15	19		T41	28		T26	2
prescale[15]	1567	1		T17	65		T37	19		T41	89
prescale[16]	783	1		T1	99		T40	30		T41	2
prescale[17]	907	1		T33	23		T16	93		T37	19
prescale[18]	615	1		T16	50		T17	110		T40	19
prescale[19]	850	1		T1	174		T40	13		T41	2
prescale[20]	838	1		T5	19		T15	9		T16	23
prescale[21]	1342	1		T16	2		T37	37		T42	138
prescale[22]	315	1		T16	2		T43	39		T44	2
prescale[23]	637	1		T17	19		T40	48		T42	2
prescale[24]	962	1		T15	24		T47	9		T17	19
prescale[25]	851	1		T16	2		T40	2		T42	9
prescale[26]	906	1		T12	9		T131	19		T101	38
prescale[27]	983	1		T1	96		T41	127		T43	30
prescale[28]	724	1		T1	41		T16	2		T40	59
prescale[29]	406	1		T15	19		T17	98		T40	19
prescale[30]	1119	1		T6	69		T8	44		T14	9
prescale[31]	1517	1		T1	23		T5	81		T7	9
prescale_0	23160	1		T1	400		T2	21		T3	18

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	38334	1		T1	765		T2	9		T3	9
auto[1]	13499	1		T1	192		T2	12		T3	9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	51833	1		T1	957		T2	21		T3	18

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	31992	1		T1	586		T2	1		T3	13
wkup[1]	246	1		T37	30		T26	21		T43	21
wkup[2]	323	1		T1	21		T16	21		T40	30
wkup[3]	270	1		T16	21		T17	21		T43	21
wkup[4]	117	1		T40	55		T105	21		T114	26
wkup[5]	379	1		T40	21		T171	15		T93	21
wkup[6]	308	1		T5	21		T16	21		T44	21
wkup[7]	140	1		T26	21		T84	35		T87	21
wkup[8]	264	1		T40	21		T55	15		T96	30
wkup[9]	271	1		T8	21		T50	15		T42	30
wkup[10]	334	1		T17	26		T42	30		T27	15
wkup[11]	415	1		T40	21		T42	21		T43	15
wkup[12]	405	1		T1	21		T46	15		T40	30
wkup[13]	289	1		T1	21		T8	21		T42	21
wkup[14]	141	1		T40	21		T90	21		T127	21
wkup[15]	182	1		T41	30		T159	21		T177	21
wkup[16]	327	1		T184	26		T44	42		T175	15
wkup[17]	299	1		T1	8		T6	21		T17	21
wkup[18]	233	1		T1	30		T40	21		T108	30
wkup[19]	227	1		T15	21		T43	15		T120	30
wkup[20]	210	1		T40	42		T26	21		T43	21
wkup[21]	190	1		T42	21		T159	21		T94	45
wkup[22]	149	1		T5	21		T86	21		T91	42
wkup[23]	333	1		T42	21		T108	26		T43	21
wkup[24]	350	1		T5	15		T40	52		T41	8
wkup[25]	294	1		T1	21		T6	15		T37	21
wkup[26]	222	1		T6	39		T87	21		T150	26
wkup[27]	306	1		T17	21		T108	21		T45	21
wkup[28]	275	1		T40	30		T101	21		T150	21
wkup[29]	344	1		T1	26		T37	21		T40	60
wkup[30]	210	1		T17	21		T45	21		T101	21
wkup[31]	327	1		T40	21		T42	39		T93	21
wkup[32]	199	1		T16	31		T40	21		T54	21
wkup[33]	247	1		T15	26		T16	21		T31	15
wkup[34]	263	1		T1	21		T8	15		T17	21
wkup[35]	282	1		T16	21		T159	21		T138	21
wkup[36]	143	1		T43	21		T91	21		T179	15
wkup[37]	220	1		T6	21		T17	21		T159	21
wkup[38]	202	1		T172	15		T90	21		T84	31
wkup[39]	417	1		T1	21		T33	30		T17	29
wkup[40]	378	1		T6	26		T16	56		T40	29
wkup[41]	234	1		T17	6		T41	21		T131	21
wkup[42]	333	1		T32	15		T40	21		T43	35
wkup[43]	243	1		T44	30		T57	21		T99	30
wkup[44]	295	1		T41	21		T54	21		T45	21
wkup[45]	246	1		T17	15		T44	21		T131	21
wkup[46]	243	1		T16	21		T109	15		T131	42
wkup[47]	151	1		T159	31		T150	42		T127	21
wkup[48]	226	1		T1	35		T92	21		T181	15
wkup[49]	256	1		T1	21		T8	42		T37	26
wkup[50]	335	1		T5	42		T16	21		T17	47
wkup[51]	244	1		T43	21		T131	26		T150	30
wkup[52]	285	1		T1	35		T90	21		T105	21
wkup[53]	186	1		T42	26		T54	21		T45	21
wkup[54]	284	1		T1	21		T40	21		T57	21
wkup[55]	207	1		T42	21		T54	21		T131	21
wkup[56]	78	1		T42	21		T156	15		T155	21
wkup[57]	202	1		T16	8		T43	21		T45	21
wkup[58]	458	1		T6	21		T16	21		T40	15
wkup[59]	254	1		T15	21		T43	38		T45	21
wkup[60]	184	1		T159	35		T83	21		T84	21
wkup[61]	353	1		T9	15		T33	29		T16	21
wkup[62]	176	1		T16	21		T17	21		T40	21
wkup[63]	128	1		T2	15		T26	8		T159	21
wkup_0	3509	1		T1	69		T2	5		T3	5