Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
11140 |
1 |
|
T1 |
330 |
|
T5 |
20 |
|
T6 |
92 |
all_values[1] |
11140 |
1 |
|
T1 |
330 |
|
T5 |
20 |
|
T6 |
92 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for cp_intr_en
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER |
[auto[1]] |
0 |
1 |
1 |
Covered bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
22280 |
1 |
|
T1 |
660 |
|
T5 |
40 |
|
T6 |
184 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5994 |
1 |
|
T1 |
204 |
|
T5 |
10 |
|
T6 |
44 |
auto[1] |
16286 |
1 |
|
T1 |
456 |
|
T5 |
30 |
|
T6 |
140 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12740 |
1 |
|
T1 |
414 |
|
T5 |
24 |
|
T6 |
96 |
auto[1] |
9540 |
1 |
|
T1 |
246 |
|
T5 |
16 |
|
T6 |
88 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
12 |
6 |
6 |
50.00 |
6 |
Automatically Generated Cross Bins |
12 |
6 |
6 |
50.00 |
6 |
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Element holes
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | NUMBER |
* |
[auto[0]] |
[auto[1]] |
* |
-- |
-- |
4 |
* |
[auto[1]] |
[auto[1]] |
[auto[1]] |
-- |
-- |
2 |
Covered bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
2906 |
1 |
|
T1 |
94 |
|
T5 |
6 |
|
T6 |
28 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
3452 |
1 |
|
T1 |
118 |
|
T5 |
8 |
|
T6 |
24 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
4782 |
1 |
|
T1 |
118 |
|
T5 |
6 |
|
T6 |
40 |
all_values[1] |
auto[0] |
auto[0] |
auto[0] |
3088 |
1 |
|
T1 |
110 |
|
T5 |
4 |
|
T6 |
16 |
all_values[1] |
auto[0] |
auto[0] |
auto[1] |
3294 |
1 |
|
T1 |
92 |
|
T5 |
6 |
|
T6 |
28 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
4758 |
1 |
|
T1 |
128 |
|
T5 |
10 |
|
T6 |
48 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |